FUJITSU SEMICONDUCTOR MB90210 Series handbook
Contents
1. OO OO POO OO OOO lt KRO wt GO G O T AL word A lt word ear A eam word Qu RWi ear word ear RWi eam a word lt gt eam Note For a and c refer to Table 4 Number of Execution Cycles in Addressing Modes and Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles 81 82 90210 Series Table8 Transmission Instruction Long 11 Instructions Mnemonic A ear A eam A imm32 A SP disp8 A addr24 A A A RLi OSP disp8 A addr24 A ear A eam A Operation long A ear long A eam long A imm32 long A long A long A lt lt SP disp8 lt addr24 lt long A lt long SP disp8 long addr24 lt long ear long eam lt A AH Note For a and refer to Table 4 Number of Execution Cycles in Addressing Modes and Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles MB90210 Series Table 9 Add Subtract Byte Word Long 42 Instructions A imm8 A dir A ear A eam ear A eam A A A ear2. 16 bit reload register 16 bit down counter Internal data bus gt gt N Clear El2OSCLR Clear RELD 0 lt Port TIN 40 90210 Series N 4 UART The UART is a serial I O port for synchronous or asynchronous communication with external resources It has the following features Full duplex double buffer Data transfer synchronous or asynchronous with clock pulses Multiprocessor mode support Mode 2 Built in dedicated baud rate generator Nine types Arbitrary baud rate setting from external clock input or internal timer Use the 16 bit reroad timer 1 channel 2 for internal timer Variable data length 7 to 9 bits without parity bit 6 to 8 bits with parity bit Variable data length 7 to 9 bit no parity 6 to 8 bit with parity Error detection function Framing overrun parity Interrupt function Two sources for transmission and reception Transfer in NRZ format The MB90210 series contains three channels for the UART UART channel 0 has the CTS function UART channel 2 provides dual I O pin switching 1 Register Configuration Serial mode control register UMC Serial mode control register Bit 7 6 5 E 1 0 Address ch 0 000020 ses chi 0000244 UMC ch2 000028 Read wite gt RW RW RW RW W RW RW Initial value
3. RDY f lt tRYHS n RYHS tRYHH No wait Wait 0 8 0 8 0 2 9 Hold Timing 4 5 to 45 5 V Vss 0 0 V Ta 40 C to 70 C Parameter Symbol Condition Remarks Pin floating gt HAK J time la tion g HAK Load condition HAK T gt pin valid time tHAHV Note It takes at least one cycle for HAK to vary after HRQ is fetched HRQ 0 8 Vcc N 0 2 Vcc 0 7 Vcc HAK 0 3 lt XHAL T Each pin High impedance 68 10 UART Timing Single chip mode MB90P214A W214A External bus mode Parameter Serial clock cycle time tscyc SCLK 4 3 SOUT delay time tsLov Valid SIN gt SCLK T tivsH SCLK T gt Valid SIN hold time tsuix Serial clock H pulse width tsHsL Serial clock L pulse width SCLK gt SOUT delay time tsLov Valid SIN gt SCLK T tivsH SCLK T gt Valid SIN hold time Notes e These AC characteristics assume the CLK synchronous mode tsuix MB90210 Series MB90214 P214B W214B 4 5 V to 5 5 V Vss 0 0 V Ta 40 to 105 C Voc 44 5 V to 5 5 V Vss 0 0 V Ta 40 to 85 C Voc 4 5 V to 5 5 V Vss 0 0 V Ta 40 C to 70 C Condition Load condition 80 pF e is the machine c
4. FUJITSU SEMICONDUCTOR 16 bit Proprietary Microcontroller CMOS F MC 16F MB90210 Series MB90214 P214A P214B W214A W214B V210 OUTLINE The MB90210 series is a line of 16 bit microcontrollers particularly suitable for system control of video cameras VTRs and copiers The F MC 16F CPU integrated in this series is based on the F MC 16 while providing enhanced instructions for high level languages and supporting extended addressing modes The MB90210 series incorporates a variety of peripheral resources such as a PWC timer with 4 channels a 10 bit A D converter with 8 channels UART serial ports with 3 channels 1 channel for CTS and 1 channel for dual input output pin switching 16 bit reload timers with 8 channels and an 8 bit PPG timer with 1 channel MB90P214B W214B is under development F MC stands for FUJITSU Flexible Microcontroller PACKAGE 80 pin Plastic QFP 80 pin Ceramic QFP 80 06 80 02 90210 Series N FEATURES F2MC 16F CPU Minimum execution time 62 5 ns 16 MHz oscillation using a duty control system Instruction sets optimized for controllers Upward object compatible with the 16 Various data types bit byte word and long word Instruction cycle improved to speed up operation Extended addressing modes 25 types High coding efficiency Access method bank access with linear pointer Enhanced mul
5. Note For a c and d referto Table 4 Number of Execution Cycles in Addressing Modes and Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles 1 Setto 3 when branch is executed and 2 when branch is not executed 2 8 x c b 8 Reads word of the branch destination address 4 W pushes to stack word and R reads word of the branch destination address Pushes to stack word 6 W pushes to stack long and R reads long of the branch destination address 7 Pushes to stack long Table 21 Branch 2 20 Instructions MB90210 Series Mnemonic B Operation LHAH S T N Z V C RMW timm8 rel CWBNE A stimm16 rel ear stimme rel eam imm8 rel CWBNE ear stimm16 rel CWBNE eam imm16 rel DBNZ ear rel DBNZ eam rel DWBNZ ear rel DWBNZ eam rel INT vct8 INT addr16 addr24 INT9 RETI RETIQ 6 LINK imm8 Branch if byte A z imm8 Branch if word A z imm16 Branch if byte ear z imm8 Branch if byte eam z imm8 Branch if word ear z imm16 Branch if word eam z imm16 byte ear ear 1 Branch if ear z 0 byte eam eam 1 Branch if eam z 0 word ear ear 1 Branch if ear 0 word eam eam 1 Branch if eam z 0 Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt Return from interrupt
6. 16 bit reload timer 1 ch 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Continued 27 90210 Series SSS eee Address Register dr Access Initial value 000048 Timer 2 timer register TMR2 R 16 bit reload XXXXXXXX 000049 timer 1 61 2 3550000X 00004 2 reload register TMRLR2 W XXXXXXXX 00004 XXXXXXXX 00004Cu Timer 3 timer register TMR3 R 16 bit reload XXXXXXXX 000040 timer 1 01 3 00004 3 reload register TMRLR3 W XXXXXXXX 00004 XXXXXXXX 000050 Timer 4 timer register TMR4 R 16 bit reload XXXXXXXX 0000511 timer 2 ch 4 000052 4 reload register TMRLR4 W XXXXXXXX 000053 XXXXXXXX 000054 5 timer register TMR5 R 16 bit reload XXXXXXXX 0000554 timer 2 61 5 3000000 000056 5 reload register TMRLR5 W XXXXXXXX 000057 XXXXXXXX 000058 6 timer register 6 R 16 bit reload XXXXXXXX 000059 UMer emer 50000000 00005Ak Timer 6 reload register TMRLR6 W XXXXXXXX 00005 XXXXXXXX 00005 7 timer register TMR7 R 16 bit reload XXXXXXXX 000050 timer 2 01 7 00005 7 reload register TMRLR7 W XXXXXXXX 00005 XXXXXXXX 000060 control status register 4 TMCSR4 R W 21 00000000 000061 Reserved area 0000624 Timer control status register 5 TMCSR5 R W
7. 90210 Series 2 Characteristics 1 Clock Timing Standards Single chip mode MB90214 P214B W214B Vcc 4 5 V to 5 5 V Vss 0 0 V Ta 40 to 105 Vcc 4 5 V to 5 5 V Vss 0 0 V Ta 40 C to 85 Voc 4 5 V to 5 5 V Vss 0 0 V Ta 40 to 70 MB90P214A W214A External bus mode Parameter Clock frequency Condition Remarks Clock cycle time 1 Input clock pulse width Duty ratio 60 Input clock rising falling time tor tet Clock Input Timings X0 Conditions When crystal or ceramic resonator is used X0 X1 Ci li L C C2 10 pF When an external clock is used Open Select the optimum capacity value for the resonator 62 90210 Series e Relationship between Clock Frequency and Power Supply Voltage V Single chip mode MB90214 P214B W214B Ta 40 to 105 C 10 to 16 MHz MB90P214A W214A TA 40 C to 85 C Fc 10 to 16 MHz External bus mode TA 40 C to 70 C Fc 10 to 16 MHz 5 5b 4 5 Fo 0 10 16 MHz 2 Clock Output Timing Standards Parameter Machine cycle time Symbol tcvc External mode Vcc 4 5 to 45 5 V Vss 0 0 V 40 to 70 C Pin name Condition Va
8. Le x 1010 004 osoo L 18 40 724 REF 0 8 OO2MAX RENE 22 30 0 40 878 016 0 58 023 MAX 031 008 gd sth ei 1994 FUJITSU LIMITED FB00105 3C 2 Dimensions in mm inches 80 pin Ceramic QFP 80 02 0 05 002MIN 22 71 E i STAND OFF T E 124000472 ii mx REF 8 89 350 14 00935 t 942 010 c 5517838 E L INDEX AREA 0 80 0315 TYP 0 35 0 10 0 15 0 05 0142 004 7 15 006 002 18 40 724 REF 1 45 0 20 1 057 008 20 00 3 30 130 MAX 787 0s Mounting height L 23 90 0 30 941 012 ST 22 30 0 25 0 80 0 20 8785 010 0315 008 1994 FUJITSU LIMITED F80018SC 1 2 Dimensions in mm inches 97 90210 Series 90210 Series 99 90210 Series See FUJITSU LIMITED For further information please contact Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT 4 1 1 Kamikodanaka Nakahara ku Kawasaki shi Kanagawa 211 88 Japan Tel 044 754 3763 Fax 044 754 3329 http www fujitsu co jpp North and South America FUJITSU MICROELECTRONICS INC Semiconductor Division 3545 North First Street San Jose CA 95134 1804 U S A Tel 408 922 9000 Fax
9. PWC3 data buffer register PWCR3 PWC timer ch 3 00000000 00000000 00000000 00000000 000080 to 87H Reserved area 000088H PPG operation mode control register PPGC 8 bit PPG timer 00000 1 000089 Reserved area Continued 29 90210 Series Address 00008 00008 Register PPG reload register Register name PRL Resource name 8 bit PPG timer Initial value XXXXXXXX XXXXXXXX 00008 to 80 Reserved area 00008 WI control register WICR Write inhibit RAM 00008 to Reserved area 00009 Delayed interrupt source generate release register DIRR Delayed interrupt generation module 0000A0k Standby control register STBYC Low power consumption mode 0001 0000 1 to 2 Reserved area 0000 Middle address control register MACR 0000 4 Upper address control register HACR 0000 5 External control register EPCR External pin HAH 0 0 00 0000 6 to Reserved area 0000 8 Watchdog timer control register WTG Watchdog timer XXXXXXXX 0000 9 Timebase timer control register TBTC Timebase timer 1 00000 0000 to Reserved area 0000 0 In
10. 0 tittet Til 2 2 2 NS A RWi disp8 A RLi disp8 A SP disp8 MOVPX A addr24 MOVPX A A RWi disp8 RLi disp8 SP disp8 addr24 lt A dir addr16 e e i TT A FF FFF H rds y byte KK KK KK KKK NNNNNNNNNNNNN dir A addr16 A A A byte di byte i Pw ewww Sa DI I Iz Iz IE Sa byte R byte byte A byte io RLi disp8 A SP disp8 addr24 i lt ma a 2 r am RLi disp8 OSP disp8 A addr24 A byte byte byte Il l l l l lll Il l l l l l Il l l l l ll Il l l l l l Il l l P l Il Il l l l lll Il l l l l l Il l l l l g Ri ear Ri eam Ri ear Ri eam Ri Ri timm8 io imms dir fimm8 ear imm8 eam Himm8 AL AH SNNN mooocomtnnmft atnmtnm io imm8 dir imm8 ear imm8 eam imm8 0000000000 000000000 0000000000000 Co e o e T p p e A A ear 0 byte o A eam a byte lt gt eam Ri ear 2 4 0 Ri lt gt ear Ri eam byte Ri lt gt eam
11. 408 922 9179 Customer Response Center Mon Fri 7 am 5 pm PST Tel 800 866 8608 Fax 408 922 9179 http www fujitsumicro com Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6 10 D 63303 Dreieich Buchschlag Germany Tel 06103 690 0 Fax 06103 690 122 http www fujitsu ede com Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD 05 08 151 Lorong Chuan New Tech Park Singapore 556741 Tel 65 281 0770 Fax 65 281 0220 http www fmap com sg F9710 FUJITSU LIMITED Printed in Japan Rights Reserved The contents of this document are subject to change without notice Customers are advised to consult with FUJITSU sales representatives before ordering The information and circuit diagrams in this document presented as examples of semiconductor device applications and are not intended to be incorporated in devices for actual use Also FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams FUJITSU semiconductor devices are intended for use in standard applications computers office automation and other office equipment industrial communications and measurement equipment personal or household devices etc CAUTION Customers considering the use of our products in special applications where failure or abnormal operation may directly affect huma
12. MB90W214A W214B are EPROM products ES only Operating temperature of MB90P214A W214A is 40 C to 85 C However the AC characteristics is assured in 40 C to 70 C MB90V210 is a evaluation device for the program development ES only 90210 Series PRODUCT LINEUP Part number Classification MB90214 Mask ROM product MB90P214A MB90P214B OTPROM product MB90W214A MB90W214B EPROM product MB90V210 For evaluation ROM size 64 Kbytes 64 Kbytes 64 Kbytes RAM size 3 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes CPU functions The number of instructions 412 Instruction bit length 8 or 16 bits Instruction length 1 to 7 bytes Data bit length 1 4 8 16 or 32 bits Minimum execution time 62 5 ns 16 MHz Interrupt processing time 1 0 us 16 MHz min I O ports N ch open drain 8 I O ports CMOS 57 Total 65 PWC timer Number of channels 4 16 bit reload timer operation operating clock cycle 0 25 us to 1 31 ms 16 bit pulse width count operation Allowing continuous one shot measurement H L width measurement inter edge measurement and divided frequency measurement 10 bit A D converter Resolution 10 or 8 bits Number of inputs 8 Single conversion mode conversion for each input channel Scan conversion mode continuous conversion for up to 8 consecutive channels Continuous conversion mode repeated conversion for selected channel S
13. lt SP SP lt SP 2 054 SP SP SP 2n N O Context switch instruction CCR 8 CCR imms byte CCR lt CCR imm8 byte CCR CCR or imm8 RP ILM timm8 byte RP imm8 byte ILM imm8 RWi ear RWi eam A ear A eam word RWi lt ear word RWi eam word A lt ear word A eam N 2 mm ww imm8 imm16 word SP lt SP ext imm8 word SP SP imm16 byte A lt brgl byte brg2 byte brg2 imm8 Wo brgl brg2 brg2 imm8 N No operation Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space Prefix code for no change in flag Prefix for common register bank MOVW SPCU imm16 MOVW SPCL imm16 SETSPC CLRSPC BTSCN A BTSCNS A BTSCND word SPCU lt imm16 word SPCL lt imm16 Enables stack check operation Disables stack check operation N NO N N Bit position of 1 in byte A from word A Bit position x 2 of 1 in byte A from word A Bit position x 4 of 1 in byte A from word A 0000 00000000 0000 Note For and refer to Table 4 Number of Execution Cycles Addressing Modes and Table 5 Correction Values for Num
14. A eam A A imm8 A dir A ear A eam ear A eam A A A ear A eam A A A ear A imm16 ear eam A ADDCW A ear ADDCW A eam SUBW A A eam lt ear A eam A H AL C ear C eam C AL C decimal Co Co X oo S NNNNNNNNN I NNNN NNNN I 9 4 N s T tt SUBW ear SUBW A eam SUBW A mm16 SUBW ear A SUBW eam A SUBCW A ear SUBCW eam TETT oX oo 9 I wo mft ADDL ear ADDL eam ADDL A imm32 SUBL SUBL SUBL A mm32 Note For a to d refer to Table
15. Stores old frame pointer in the beginning of the function set new frame pointer and reserves local pointer area Restore old frame pointer from stack in the end of the function Return from subroutine Return from subroutine Note For a to d refer to Table 4 Number of Execution Cycles in Addressing Modes and Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles 1 Setto 4 when branch is executed and 3 when branch is not executed 2 Setto 5 when branch is executed and 4 when branch is not executed 3 Set to 5 a when branch is executed and 4 a when branch is not executed 4 Set to 6 a when branch is executed and 5 a when branch is not executed 5 Setto 3x b 2x c when an interrupt request is issued and 6 x c for return 6 This is a high speed interrupt return instruction In the instruction an interrupt request is detected When an interrupt occurs stack operation is not performed with this instruction branching to the interrupt vector 7 Return from stack word 8 Return from stack long 91 90210 Series 92 Table22 Miscellaneous Control Types Byte Word Long 36 Instructions word SP lt SP 2 word SP SP 2 PS lt PS 2n SP lt rst 02 02 GO word lt SP SP lt SP 2 word lt SP SP lt SP 2 word PS
16. long A word ear Quotient word Remainder word ear DIVW eam 2 5 77 long A word eam Quotient word Remainder word eam MUL A 2 8 0 byte AH x byte AL gt word l MUL A ear 217910 byte A x byte ear word A MUL 2 10 b byte A x byte eam gt word MULW A 2 11 0 AH x word AL gt long A MULW ear 2 12 0 A x word ear gt long MULW eam 2 13 b word A x word eam 5 long A For b and c refer to Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles 1 2 9 4 6 Ts 8 9 Setto 3 for divide by 0 8 or 18 for an overflow and 18 for normal operation Setto 3 for divide by 0 10 or 21 for an overflow and 22 for normal operation Setto 4 a for divide by 0 11 a or 22 a for an overflow and 23 a for normal operation Positive divided Set to 4 for divide by 0 10 or 29 for an overflow and 30 for normal operation Negative divided Set to 4 for divide by 0 11 or 30 for an overflow and 31 for normal operation Positive divided Set to 4 a for divide by 0 11 a or 30 a for
17. with stop request O EOS is supported however since two interrupt sources are allocated to a single ICR in case is used for one of the two EI OS and ordinary interrupt are not both available for the other with stop request El OS is supported however since two interrupt sources are allocated to a single ICR in case El OS is used for one of the two EI OS and ordinary interrupt not both available for the other with no stop request x EI OS is not supported 33 34 90210 Series N PERIPHERAL RESOURCES 1 Parallel Ports The 90210 series has 57 pins 8 open drain pins Ports 0 to 5 7 and 8 are ports Each of these ports serves as an input port when the data direction register value is 0 and as an output port when the value is 1 Port 6 is an open drain port which may be used as a port when the analog input enable register value is 0 1 Register Configuration Port data registers 0 to 8 PDRO to 8 Port data register Address PDR1 000001 PDR3 0000034 PDR7 0000074 Read write gt R W R W R W RW RW R W R W Initial value X X X X X X X X Bit 15 14 13 12 8 Port data register Bit a 4 3 2 1 0 Address PDRO 000000 PDR2 0000024 PDR4 0000044 PDR6 0000064 PDR8 0000084 Read write gt R W R W R W R W R W RW R W Initial v
18. 00 2 25 RD I gt CLK time RD CLK 2 25 tavcH 0 7 0 3 tavRL TRLRH gt 0 7 Vcc RD 0 3 Vcc lt A23 to AI 0 7 Vcc 0 7 Vcc D15 to DOO Read data 66 90210 Series 7 Bus Write Timing 4 5 to 5 5 V Vss 0 0 V Ta 40 C to 70 C Parameter Pin name Condition Remarks Valid address WR J time taw A23 to A00 2 20 WR I pulse width twiwH WRL WRH tcvc 25 Valid data output gt WR T Load 40 time D15 to DOO condition WR T gt data hold time twHpx 80 pF teve 2 20 WR T 5 address valid time twuax A23 to A00 tcvc 2 20 WR I gt CLK J time twicH WRL WRH CLK 2 25 TWECL 0 3 WR 0 3 Voc 0 7 WRL WRH A23 to A00 D15 to D00 67 90210 Series 8 Ready Signal Input Timing 4 5 to 45 5 V Vss 0 0 V Ta 40 to 70 C Value Parameter Symbol Condition Unit Min Max RDY hold time tRYHH Note Use the auto ready function if the RDY setup time is insufficient anf NO AN EX A23 to 00 A mr WRL WRH d
19. 15 14 13 12 11 10 9 8 Timer register TMR Timer register Upper byte Address ch 0 000041 ch 1 000045 ch 2 000049 ch 3 000040 Read write R R R R R R R Initial value X X X X X X X X Timer register Lower byte Bit 7 6 5 4 3 2 1 0 Address ch 0 000040 chi 000044 ch 2 000048 ch 3 00004 Read write gt R R R R R R Initial value gt X X X X X X X X 36 MB90210 Series E Reload register TMRLR Reload register Upper byte Address ch 0 000043 ch 1 000047 ch 2 00004 ch 3 00004 Read write W W Initial value gt X Reroal register Lower byte Address ch 0 0000424 ch 1 000046 ch 2 00004 61 3 00004 Read write gt W W W W W W W W Initial value gt X X 2 Block Diagram 16 bit reload register 16 bit down counter UF 16 N joe E OUT CTL Z g 2 IRQ Clock selector Clear EI OSCLR Retrigger Port TIN EXCK AA pon our Prescaler clear MOD 2 gt UART timer 1 ch 2 output MOD 1 A D timer 1 ch 3 output Internal clock MOD 0 37 90210 Series 3 16 bit Reload Timer 2 with Gate Mode The 16 bit reload timer 2 consists of a 16 bit dow
20. 4 Number of Execution Cycles in Addressing Modes and Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles 83 90210 Series Table 10 Increment Decrement Byte Word Long 12 Instructions Mnemonic Operation byte ear ear 1 byte eam eam 1 byte ear ear 1 byte eam lt eam 1 word ear ear 1 word eam eam 1 word ear ear 1 word eam lt eam 1 long ear ear 1 long eam lt eam 1 long ear ear 1 long eam lt eam 1 Note For a to d refer to Table 4 Number of Execution Cycles in Addressing Modes and Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles Table 11 Compare Byte Word Long 11 Instructions Mnemonic B Operation S T N Z V C RMW CMP A 1 1 0 byte AH AL exec Pe ELLE CMP A ear 2 2 0 byte A ear _ er fe _ CMP A eam 2 3 a b byte eam CMP A imm8 2 2 0 byte A imm8 5 CMPW 1 1 0 AL ja _ CMPW A ear 2 2 0 A ear m RS E e vr CMPW A eam 2 13 c eam CMPW A imm16 3 2 A imm16 i j
21. Analog input enable register read Internal data bus 35 90210 Series 2 16 bit Reload 1 with Event Count Function The 16 bit reload timer 1 consists of a 16 bit down counter a 16 bit reload register an input pin TIN an output pin TOUT and a control register The input clock can be selected from among three internal clocks and one external clock At the output pin TOUT the pulses in the toggled output waveform are output in the reload mode the rectangular pulses indicating that the timer is counting are in the single shot mode The input pin TIN can be used for event input in the event count mode and for trigger input or gate input in the internal clock mode MB90210 series contains four channels for this timer 1 Register Configuration Timer control status register TMCSR Timer control status register Upper byle Address ch 0 000039 ch 1 00003 ch2 000030 ch3 00003 Readwie gt gt C RW RW RW RW Initial value gt C 0 0 0 0 Timer control status register Lower byte Bit 7 6 5 4 3 2 1 0 Adress cho CT mo me core 000 OUTL RELD INTE UF CNTE TRG ch 3 00003 Read wite gt RW RW RW RW RW RW Initial value gt 0 0 0 0 0 Bit
22. General purpose port This port is always available When these pins are open in input mode through current may leak in stop mode reset mode be sure to fix these pins to Vcc Vss level to use these pins in input mode INT2 External interrupt request input pin Since this input is used whenever external interrupts are enabled the output by any other function must be suspended unless the output is intentionally performed When these pins are open in input mode through current may leak in stop mode reset mode be sure to fix these pins to Vcc Vss level to use these pins in input mode ATG 10 bit A D converter trigger input pin When these pins are open in input mode through current may leak in stop mode reset mode be sure to fix these pins to Vcc Vss level to use these pins in input mode 28 AVcc Power supply Analog circuit power supply pin This power supply must be turned on or off with a potential equal to or higher than AVcc applied to Vcc Be sure that AVcc Vcc before use and during operation 29 AVRH Power supply Analog circuit reference voltage input pin This pins must be turned on or off with a potential equal to or higher than AVRH applied to AVcc 30 AVRL Power supply Analog circuit reference voltage input pin 31 AVss Power supply Analog circuit grounding level FPT 80P MO6 FPT 80C C02 14 CIRCUIT Circuit Standby control MB90210 Series
23. W214A MB90P214B W214B Fc 16 MHz In sleep mode 1 CMOS level input POO to P07 P10 to P17 2 Hysteresis input pins RST HST P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P75 P80 to P82 Ta 25 C In stop mode In hardware standby input time 3 Output pins to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P70 to P75 P80 to P82 4 Output pins to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P75 P80 to P82 The current value applies to the CPU stop mode with A D converter inactive Vcc AVcc AVRH 5 5 6 Other than Vcc Vss AVcc and AVss 7 A list of availabilities of pull up pull down resistors Pin name MB90214 Availability of pull up resistors is optionally defined MB90P214A W214A Pull up resistors available MB90P214B W214B Pull up resistors available Pull up resistors available Unavailable Unavailable MD2 Pull down resistors available Unavailable Unavailable Generic pin 8 Vcc 5 0 V Vss 0 0 V Ta 25 C Fc 16 MHz Availability of pull up pull down resistors is optionally defined Unavailable Unavailable 9 Measurement condition of power supply current external clock pin and output pin are open Measurement condition of Vcc see the table above mentioned 61
24. With left rotate carry byte eam With left rotate carry byte A Arithmetic right barrel shift A RO byte A lt Logical right barrel shift A RO byte A Logical left barrel shift A RO byte A Arithmetic right barrel shift A imm8 A Logical right barrel shift A imm8 A Logical left barrel shift A imm8 Table 19 Shift Type Instruction Byte Word Long 27 Instructions LSRW A SHRWA LSLW A SHLW A A imm8 A imm8 word A Arithmetic right shift A 1 bit word lt Logical right shift A 1 bit word A lt Logical left shift A 1 bit word A Arithmetic right barrel shift A RO A Logical right barrel shift A RO word lt Logical left barrel shift A RO word lt Arithmetic right barrel shift A imm8 Logical right barrel shift A imm8 Logical left barrel shift A imm8 A RO A RO A RO A imm8 A imm8 LSLL A imm8 long A Arithmetic right barrel shift A RO long A Logical right barrel shift A RO long lt Logical left barrel shift A RO long Arithmetic right barrel shift A imm8 long A Logical right barrel shift A imm8 long Logical left barrel shift A imm8 Note For a and b refer to Table 4 Number of Execution Cycles in Addressing Modes and Table 5 Correction Values for Number of Cycles for Cal
25. an overflow and 31 a for normal operation Negative divided Set to 4 a for divide by 0 12 a or 31 a for an overflow and 32 a for normal operation Set to b when the division by 0 or an overflow and 2 x b for normal operation Set to c when the division by 0 or an overflow and 2 x c for normal operation Set to 3 when byte AH is zero 12 when the result is positive and 13 when the result is negative Set to 3 when byte ear is zero 12 when the result is positive and 13 when the result is negative 10 Setto 4 a when byte eam is zero 13 a when the result is positive and 14 a when the result is negative 11 Set to 3 when word AH is zero 12 when the result is positive and 13 when the result is negative 12 Set to 3 when word ear is zero 16 when the result is positive and 19 when the result is negative 13 Setto 4 a when word eam is zero 17 a when the result is positive and 20 a when the result is negative Note When overflow occurs during DIV or DIVW instruction execution the number of execution cycles takes two values because of detection before and after an operation When overflow occurs during DIV or DIVW instruction execution the contents of AL are destroyed MB90210 Series Table 14 Logic 1 Byte Word 39 Instructions lt Mnemonic Operation A fimm8 lt A and imm8 A ear A and ear A eam A a
26. analog input from exceeding the digital power supply Vcc when the analog system power supply is turned on and off Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions They should be connected to a pull up or pull down resistor Treatment of Pins when A D is not Used Connect to be AVcc AVRH and AVss AVRL Vss even if the A D converter is not in use Precautions when Using an External Clock To reset the internal circuit properly by the Low level input to the RST pin the L level input to the RST pin must be maintained for at least five machine cycles Pay attention to it if the chip uses external clock input Vcc and Vss Pins Apply equal potential to the Vcc and Vss pins Supply Voltage Variation The operation assurance range for the Vcc supply voltage is as given in the ratings However sudden changes in the supply voltage can cause misoperation even if the voltage remains within the rated range Therefore it is important to supply a stable voltage to the IC The recommended power supply control guidelines are that the commercial frequency 50 to 60 Hz ripple variation P P value on Vcc should be less than 10 of the standard Vcc value and that the transient rate of change during sudden changes such as during power supply switching should be less than 0 1 V ms Notes on Using an External Clock When using an external clock drive the pin as illustrated belo
27. and 13 for normal operation 3 Set to 5 a when the division by 0 7 a for an overflow and 17 a for normal operation 4 Set to 3 when the division by 0 5 for an overflow and 21 for normal operation 5 Set to 4 a when the division by 0 7 a for an overflow and 25 a for normal operation 6 When the division by 0 b for an overflow and 2 x b for normal operation 7 When the division by 0 c for an overflow and 2 c for normal operation 8 Set to 3 when byte AH is zero 7 when byte AH is not zero 9 Set to 3 when byte ear is zero 7 when byte ear is not zero 10 Set to 4 a when byte eam is zero 8 a when byte eam is not zero 11 Set to 3 when word AH is zero 11 when word AH is not zero 12 Set to 4 when word ear is zero 11 when word ear is not zero 13 Set to 4 a when word eam is zero 12 a when word eam is not zero 85 86 90210 Series n Table 13 Signed multiplication division Word Long 11 Instructions Mnemonic Operation LHAH S T N Z V C RMW DV A 21510 word AH byte AL Z eee ewm Quotient byte AL Remainder byte AH DIV A ear 2 2 0 A byte ear 72 1 1 1 Quotient byte Remainder gt byte ear DIV 2 3 6 A byte eam 72 1 1 Quotient byte A Remainder byte eam DIVW A ear 2 4 0
28. completed 19 13 04 000 4 PWC timer 2 overflow 20 144 FFFFAC H PWC timer 3 count completed A 21 15 FFFFABH ICRO5 000B5H PWC timer 3 overflow 22 16k FFFFA4H 16 bit reload timer 1 0 overflow A 23 17 06 000B6u 16 bit reload timer 1 1 overflow 24 18 FFFF9CuH 16 bit reload timer 1 2 overflow A 25 19H FFFF98H ICR07 000B7H 16 bit reload timer 1 3 overflow A 26 FFFF94H 16 bit reload timer 2 4 overflow A 27 1 FFFF90H ICR08 000B8H 16 bit reload timer 2 5 overflow A 28 1 FFFF8CH 16 bit reload timer 2 6 overflow A 29 10 FFFF88H ICR09 000 9 16 bit reload timer 2 7 overflow 30 FFFF84u A D converter count completed 31 1 8 10 000 Timebase timer interval interrupt A 32 20 7 UART2 transmission completed A 33 21 FFFF78H ICR11 000BBH UART2 reception completed A 34 224 FFFF74u Continued Continued Interrupt source UARTI transmission completed MB90210 Series Interrupt vector Interrupt control register No Address FFFF70u UARTI reception completed FFFF6CH ICR Address 0000 UARTO transmission completed FFFF684 0000BDk UARTO reception completed 0000 Delayed interrupt generation module 4 0000 Stack fault is supported
29. initial value of this bit varies with the reset source i The initial value of this bit varies with the operation mode 1 Access inhibited 2 The only area available for the external access below address 0000FFuisthis area Accesses to these addresses are handled as accesses to an external area 3 When the external bus is enabled do not access any register not serving as a general purpose port in the areas from address 0000004 to 0000054 and from 0000104 to 0000154 4 Writing to bit 15 is possible Writing to other bits is used as a test function 31 32 90210 Series I INTERRUPT SOURCES AND INTERRUPT VECTORS INTERRUPT CONTROL REGISTERS 5 Interrupt vector Interrupt control register support No Address Address Reset x 08 08u INT9 instruction x 09 094 FFFFD8u Exceptional x 10 FFFFD4k UART interrupt 0 A 11 FFFFD0H ICR00 000 0 UART interrupt 1 A 12 OCH UART interrupt 2 A 13 FFFFC8u ICRO1 000 1 UART interrupt 3 A 14 PWC timer 0 count completed A 15 ICRO2 000 2 PWC timer 0 overflow A 16 10 FFFFBCu PWC timer 1 count completed A 17 FFFFB8u ICROS 000B3 PWC timer 1 overflow 18 12 4 PWC timer 2 count
30. intentionally performed When these pins are open in input mode through current may leak in stop mode reset mode be sure to fix these pins to Vcc Vss level to use these pins in input mode General purpose I O port This port is available in the single chip mode or when the WRL pin output is disabled Write strobe output pin for the lower eight bits of data bus This pin is available in an external bus mode and when the WRL pin output is enabled General purpose I O port This port is available in the single chip mode Data bus read strobe output pin This pin is available in an external bus mode General purpose I O port This port is always available When these pins are open in input mode through current may leak in stop mode reset mode be sure to fix these pins to Vcc Vss level to use these pins in input mode RAM write disable request input Since this input is used during this operation at any time the output by any other function must be suspended unless the output is intentionally performed When these pins are open in input mode through current may leak in stop mode reset mode be sure to fix these pins to Vcc Vss level to use these pins in input mode P60 61 62 to P67 ANO 1 2 to Open drain ports These ports are available when the analog input enable register setting is port 10 bit A D converter analog input pins These pins are available
31. the output impedance of the external circuit for analog input under the following conditions External circuit output impedance lt approx 10 kO Sampling period 3 75 us tcvc 62 5 ns 3 Precision values are standard values applicable to sleep mode 4 If Vcc AVcc or Vss AVss is caused by noise to drop to below the analog input voltage the analog input currentis likely to increase In such cases a bypass capacitor or the like should be provided in the external circuit to suppress the noise 90210 Series M Equivalent Circuit of Analog Input Circuit r EE Analog input Co Ron External impedance Ron Approx 1 5 Ci I I I I Ronz Approx 1 5 60 pF I I 4 pF Note The values shown here are reference values A D Converter Glossary Resolution Analog changes that are identifiable with the A D converter When the number of bits is 10 analog voltage can be divided into 21 1024 Total error Difference between actual and logical values This error is caused by a zero transition error full scale transition error linearity error differential linearity error or by noise Linearity error The deviation of the straight line connecting the zero transition point 00 0000 0000 lt gt 00 0000 0001 with the full scale transition point 11 1111 1111 lt 1
32. 00000000 000063 Reserved area 0000644 Timer control status register 6 TMCSR6 R W bd res 00000000 0000654 Reserved area Continued Address 000066 Register Timer control status register 7 MB90210 Series Register name TMCSR7 Access Resource name 16 bit reload timer 2 ch 7 Initial value 00000000 000067 Reserved area 000068H PWCO divide ratio register DIVR0 PWC timer ch 0 000069 Reserved area 00006 PWC1 divide ratio register DIVR1 PWC timer ch 1 00006 Reserved area 00006CH 2 divide ratio register DIVR2 PWC timer ch 2 00006DH Reserved area 00006 PWC3 divide ratio register DIVR3 PWC timer ch 3 00006 Reserved area 000070 000071 PWCO control status register PWCSR0 000072H 000073 PWCO data buffer register PWCR0 PWC timer ch 0 00000000 00000000 00000000 00000000 000074 000075 PWC1 control status register PWCSR1 000076 000077 PWC1 data buffer register PWCR1 PWC timer ch 1 00000000 00000000 00000000 00000000 000078 000079 PWC2 control status register PWCSR2 00007 00007 2 data buffer register PWCR2 PWC timer ch 2 00000000 00000000 00000000 00000000 00007Cu 000070 PWC3 control status register PWCSR3 00007 00007
33. 1 1111 1110 from actual conversion characteristics Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Digital output 11 1111 1111 11 1111 1110 11 1111 1101 Theoretical value Theoretical value V Actual conversion value Total error N 1 LP N LLL N 1 Linerity error 00 0000 0010 m LSB Var 00 0000 0001 00 0000 0000 AVRL V Nr AVRH V Vor Vir Ver Vin tyt V Nenr V 1LSB Vrsr Vor 1LSB theoretical value V AVRL 1022 1022 N 0 to 1022 4 Linearity error Var N x 1LSB Vor l VNT i Vor 1LSB VNT N 1022 Vest Differential linearity error VW VN 0T 4 N 11to 1022 1LSB Total error Vnt N 0 5 x 1LSB theoretical value N 0 to 1022 1LSB theoretical value 73 90210 Series EXAMPLE CHARACTERISTICS 1 Power Supply Current vs Ta example characteristics lcc mA 100 Fc 16 MHz 90 External clock input Voc 55V 80 FFF MB90P214A 70 60 50 MB90214 40 50 0 50 100 150 Ta C vs Ta example characteristics UA 40 5 5 30 Note These are not assured value of characteristics but example characteristics 2 Output Voltage Vo vs example
34. 6 x RWO 8 b x RWO 94 Table 26 Multiple Data Transfer Instructions 18 Instruction Mnemonic MOVM RLi imm8 MOVM eam imm8 MOVM addr16 RLi imm8 MOVM addr16 eam imm8 MOVMW A RLi imm8 MOVMW A eam imm8 MOVMWaddr16 RLi imm8 MOVMWaddr16 eam imm8 MOVM RLi imm8 MOVM eam A imm8 MOVM RLi addr16 imm8 MOVM eam addr16 imm8 MOVMWQGRLi imm8 MOVMW eam A imm8 MOVMW RLIi addr16 imm8 MOVMW eam addr16 imm8 MOVM bnk addr16 bnk addr16 imm8 gt MOVMWbnk addr16 bnk addr16 imm8 5 Operation Multiple data transfer byte RLi Multiple data transfer byte lt eam Multiple data transfer byte addr16 lt RLi Multiple data transfer byte addr16 eam Multiple data transfer word RLi Multiple data transfer word A eam Multiple data transfer word addr16 RLi Multiple data transfer word addr16 eam Multiple data transfer byte RLi lt A Multiple data transfer byte eam A Multiple data transfer byte RLi addr16 Multiple data transfer byte eam lt addr16 Multiple data transfer word RLi A Multiple data transfer word eam lt A Multiple data transfer word RLi addr16 Multiple data transfer word eam lt addr16 Multiple data transfer byte bnk addr16 bnk addr16 Multiple data transfer word bnk ad
35. AVRL MPX AN0 AN1 AN2 p AN4 5