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ST 74LVX238 LOW VOLTAGE CMOS 3 TO 8 LINE DECODER WITH 5V TOLERANT INPUTS handbook

1. 2 0 10 lt 50 uA 1 9 2 0 1 9 1 9 Voltage 3 0 lo 50 pA 29 3 0 2 9 2 9 V 3 0 lo 4 2 58 2 48 2 4 Low Level Output 2 0 lo 50 pA 00 0 1 0 1 0 1 voltage 3 0 10 50 pA 0 0 0 1 0 1 3 0 lo 4 mA 0 36 0 44 0 55 Input Leakage 36 Vi 5V or GND 04 1 1 pA loc Quiescent Supply Current 3 6 VI Voc or GND 2 20 20 ky 3 12 741 238 Table 7 Dynamic Switching Characteristics Test Condition Value Symbol Parameter Veg 25 C 40 to 85 55 to 125 C Unit Dynamic Low 0 3 0 5 Voltage 3 3 Output note 1 2 0 5 0 3 Dynamic High 3 3 Voltage Input note C 50 pF V 1 3 Dynamic Low 3 3 0 8 Voltage Input note 1 3 1 Worst case package 2 Max number of outputs defined as n Data inputs are driven OV to 3 3V n 1 outputs switching and one output at GND 3 Max number of data inputs n switching n 1 switching OV to 3 3V Inputs under test switching 3 3V to threshold OV to threshold f 1MHz Table 8 AC Electrical Characteristics Input t t 3ns Test Condition Value Symbol Parameter 25 40 to 85 55 to 125
2. 741 238 LOW VOLTAGE CMOS 3 8 LINE DECODER WITH 5V TOLERANT INPUTS HIGH SPEED tpb 5 5ns at Vcc 3 3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL 0 8V VIH 2V at Vcc 3V LOW POWER DISSIPATION log 2 uA MAX at 25 m LOW NOISE Vo p 0 3V TYP at Voc 3 3V m SYMMETRICAL OUTPUT IMPEDANCE loi 4mA MIN m BALANCED PROPAGATION DELAYS tPLH OPERATING VOLTAGE RANGE 2V to 3 6V 1 2V Data Retention m PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138 IMPROVED LATCH UP IMMUNITY POWER DOWN PROTECTION ON INPUTS DESCRIPTION The 74LVX238 is a low voltage CMOS 3 TO 8 LINE DECODER fabricated with sub micron silicon gate and double layer metal wiring C MOS technology is ideal for low power battery operated and low noise 3 3V applications If the device is enabled 3 binary select A B and C determine which one of the outputs will go high If enable input G1 is held low or either G2A or G2B Figure 1 Pin Connection And IEC Logic Symbols 5 10525 August 2004 Table 1 Order Codes PACKAGE T amp R TSSOP 74LVX238TTR is held high the decoding function is inhibited all the 8 outputs go low Tree enable inputs are provided to ease cascade connection and application of address decoders for memory systems Power down protection is provided on all inputs and 0 to 7V can be accep
3. 9 12 74LVX238 Tape amp Reel TSSOP16 MECHANICAL DATA N Y _ Po Bo f O D O q i Note Drawing not in scale 10 Revision History 741 238 Date Revision Description of Changes 27 2004 2 Ordering Codes Revision pag 1 11 12 74LVX238 Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2004 STMicroelectronics Rights Reserved STMicroelectronics group of companies Australia Belgium Bra
4. Table 4 Absolute Maximum Ratings 741 238 Symbol Parameter Value Unit Vcc Supply Voltage 0 5 to 7 0 V Vi DC Input Voltage 0 5 to 7 0 V Vo DC Output Voltage 0 5 to Vcc 0 5 V lik DC Input Diode Current 20 mA lok DC Output Diode Current 20 lo DC Output Current 25 Icc lenp DC or Ground Current 50 Tstg Storage Temperature 65 to 4150 C T Lead Temperature 10 sec 300 Absolute Maximum Ratings are those values beyond which damage to device may occur Functional operation under these conditions is not implied Table 5 Recommended Operating Conditions Symbol Parameter Value Unit Vcc Supply Voltage note 1 2 to 3 6 V Input Voltage 0 to 5 5 V Vo Output Voltage 0 to V Top Operating Temperature 55 to 125 dt dv Input Rise and Fall Time note 2 3 3V 0 to 100 ns V 1 Truth Table guaranteed 1 2V to 3 6V 2 from 0 8V to 2 0V Table 6 DC Specifications Test Condition Value Symbol Parameter Vcc 25 40 to 85 55 to 125 C Unit v Min Typ Max Min Max Min Max High Level Input 2 0 1 5 1 5 1 5 Voltage 3 0 2 0 2 0 2 0 V 3 6 2 4 2 4 2 4 Low Level Input 2 0 0 5 0 5 0 5 Voltage 3 0 0 8 0 8 0 8 3 6 0 8 0 8 0 8
5. V PF Min Min Max Min Max tpLH teur Propagation Delay 2 7 15 7 1 13 8 10 165 1 0 18 5 Time 27 50 9 6 17 3 10 20 0 1 0 22 0 3 30 15 55 88 10 1055 10 n5 ns 3 30 50 80 123 10 14 0 1 0 15 0 tph Propagation Delay 2 7 15 8 7 16 3 1 0 19 5 1 0 205 Time 27 50 11 2 19 8 1 0 23 0 1 0 25 0 SUCRE 3 300 15 6 8 106 10 125 1 0 135 3 30 50 9 3 14 1 1 0 160 1 0 17 0 Propagation Delay 2 7 15 88 16 0 1 0 18 5 1 0 19 5 Time _ 27 50 11 3 19 5 1 0 220 1 0 23 0 G2AorG2BtoY 330 15 6 9 104 10 11 5 10 1135 S 3 80 50 9 4 139 10 150 1 0 17 0 tosLH Output To Output 2 7 50 0 5 1 0 1 5 1 5 tosHL Time notet 54 05 10 1 5 1 5 ns 1 Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch ing in the same direction either HIGH or LOW 2 Parameter guaranteed by design Voltage range is 3 3V 0 3V 4 12 Table 9 Capacitive Characteristics 74LVX238 Test Condition Value Symbol Parameter Vec 25 C 40 to 85 55 to 125 C Unit Input 3
6. 3 4 10 10 10 Cpp Power Dissipation Capacitance 3 3 fiy 10MHz 34 pF note 1 1 Opp is defined as the value of the IC s internal equivalent capacitance which i load Refer to Test Circuit Average operating current can be obtained by the Figure 4 Test Circuit C lt 15 50 or equivalent includes jig and probe capacitance ZouT of pulse generator typically 500 SC12220 Figure 5 Waveform Propagation Delays For Inverting Outputs f 1MHz 5096 duty cycle r A B C G2n S calculated from the operating current consumption without ollowing equation lcc opr Cpp x Vcc x fin loc 5 12 74LVX238 Figure 6 Waveform Propagation Delays For Non inverting Outputs f 1 MHz 50 duty cycle A B C G1 SC12810 6 12 741 238 50 16 MECHANICAL DATA 0016020D ky 712 74LVX238 TSSOP16 MECHANICAL DATA 0 173 0 0256 BSC 8 0 8 L 0 45 0 60 0 75 0 018 0 024 0 030 PIN 1 IDENTIFICATION 0080338D 4 8 12 741 238 Tape amp Reel 50 16 MECHANICAL DATA N C Y Y A A MEC Y O O q Note Drawing not in scale
7. ted on inputs with no regard to the supply voltage This device can be used to interface 5V to 3V system It combines high speed performance with the true CMOS low power consumption All inputs and outputs are equipped with protection circuits against static discharge giving them 2KV ESD immunity and transient excess voltage 0 1 2 5 4 5 6 7 1812901 2 1 12 74LVX238 Figure 2 Input Equivalent Circuit Table 2 Pin Description PIN N SYMBOL NAME AND FUNCTION 1 2 3 A B C Address Inputs 4 5 G2A G2B Inputs 6 G1 Enable Input 15 14 13 YO to 7 Outputs 12 11 10 9 7 GND 8 GND Ground 0V dic 16 Voc Positive Supply Voltage SC11940 Table 3 Truth Table INPUTS OUTPUTS ENABLE SELECT G2B G2A G1 v2 YA Y5 Ye YW X X L X X X L L L L L L L L X H X X X X L L L L L L L L H X X X X X L L L L L L L L L L H L L L H L L L L L L L L L H L L H L H L L L L L L L L H L H L L L H L L L L L L L H L H H L L L H L L L L L L H H L L L L L L H L L L L L H H L H L L L L L H L L L L H H H L L L L L L L H L L L H H H H L L L L L L L H X Don t Care Figure 3 Logic Diagram This logic diagram has not be used to estimate propagation delays 2 12 SELECT INPUTS ENABLE INPUTS DATA OUTPUTS
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ST 74LVX238 LOW VOLTAGE CMOS 3 TO 8 LINE DECODER WITH 5V TOLERANT INPUTS handbook

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