ST 74LVX132 handbook
Contents
1. All inputs and outputs are equipped with protection circuits against static discharge giving them 2KV ESD immunity and transient excess voltage LC11020 Rev 3 1 11 74LVX132 Figure 2 Input Equivalent Circuit Table 2 Pin Description PIN N SYMBOL NAME AND FUNCTION 1 4 9 12 1Ato4A Data Inputs 2 5 10 13 1B to 4B Data Inputs 3 6 8 11 1Yto4Y Data Outputs 7 GND Ground 0V 14 Voc Positive Supply Voltage Table 3 Truth Table GND A B Y DU L L H SC11940 L H H H L H H H L Table 4 Absolute Maximum Ratings Symbol Parameter Value Unit Vcc Supply Voltage 0 5 to 7 0 V VI DC Input Voltage 0 5 to 7 0 V Vo DC Output Voltage 0 5 to Vcc 0 5 V lik DC Input Diode Current 20 mA lox DC Output Diode Current 20 mA lo DC Output Current 25 mA Icc Or lenp DC Vec or Ground Current 50 mA Tstg Storage Temperature 65 to 150 C T Lead Temperature 10 sec 300 C Absolute Maximum Ratings are those values beyond which damage to the device may occur Functional operation under these conditions is not implied Table 5 Recommended Operating Conditions Symbol Parameter Value Unit Voc Supply Voltage note 1 2 to 3 6 V VI Input Voltage 0 to 5 5 V Vo Output Voltage 0 to Voc V Top Operating Temperature 55 to 125 C 1 Truth Table guarante2. N C 1 A A A BE Po Bo oF Y O D D O q J Ko AO BUG Note Drawing not in scale 8 11 74LVX132 Tape amp Reel TSSOP14 MECHANICAL DATA N iC Y li A i i BEB Po Bo f O D D O q l Note Drawing not in scale STO 74LVX132 Table 10 Revision History Date Revision Description of Changes 27 Aug 2004 3 Ordering Codes Revision pag 1 10 11 74LVX132 Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2004 STMicroelect
3. AY 74LVX132 LOW VOLTAGE CMOS QUAD 2 INPUT SCHMITT NAND GATE WITH 5V TOLERANT INPUTS m HIGH SPEED tpp 5 9ns TYP at Vcc 3 3V 5V TOLERANT INPUTS LOW POWER DISSIPATION Icc 2 WA MAX at Ta 25 C TYPICAL HYSTERESIS 0 7V at Voc 3 3V LOW NOISE Voip 0 3V TYP at Vee 3 3V mg SYMMETRICAL OUTPUT IMPEDANCE lou lot 4mA MIN m BALANCED PROPAGATION DELAYS tPLH tPHL m OPERATING VOLTAGE RANGE Vec OPR 2V to 3 6V 1 2V Data Retention m PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 132 m IMPROVED LATCH UP IMMUNITY m POWER DOWN PROTECTION ON INPUTS DESCRIPTION The 74LVX132 is a low voltage CMOS QUAD 2 INPUT SCHMITT NAND GATE fabricated with sub micron silicon gate and double layer metal wiring C MOS technology It is ideal for low power battery operated and low noise 3 3V applications Power down protection is provided on all inputs and O to 7V can be accepted on inputs with no regard to the supply voltage Figure 1 Pin Connection And IEC Logic Symbols August 2004 Table 1 Order Codes PACKAGE T amp R 74LVXTS2MTR TSSOP 74LVX132TTR This device can be used to interface 5V to 3V system It combines high speed performance with the true CMOS low power consumption Pin configuration and function are the same as those of the 74LVX00 but the 74LVX132 has hysteresis This together with its schmitt trigger function allows it to be used on line receivers with slow rise fall input signals
4. ed 1 2V to 3 6V 3 2 11 74LVX132 Table 6 DC Specifications Test Condition Value Symbol Parameter Wag Ty 25 C 40 to 85 C 55 to 125 C Unit V Min Typ Max Min Max Min Max Vi High Level Input Threshold 3 0 2 2 2 2 2 2 V Vi Low Level Input Threshold 3 0 0 9 0 9 0 9 V Vu Hysteresis Voltage 3 0 0 3 1 2 03 12 0 3 1 2 V Vou High Level Output 2 0 lo 50 pA 1 9 2 0 1 9 1 9 Voltage 3 0 lo 50 HA 29 3 0 29 2 9 V 3 0 lo 4 MA 2 58 2 48 2 4 VoL Low Level Output 2 0 lo 50 pA 0 0 0 1 0 1 0 1 voltage 3 0 lo 50 pA 0 0 0 1 0 1 01 V 3 0 lo 4 mA 0 36 0 44 0 55 l Input Leakage H Current 3 6 Vj 5V or GND 20 1 1 1 uA lec Quiescent Supply E Current 3 6 Vi Voc or GND 2 20 20 uA Table 7 Dynamic Switching Characteristics Test Condition Value Symbol Parameter Vec Ta 25 C 40 to 85 C 55 to 125 C Unit V Min Typ Max Min Max Min Max Vo_tp Dynamic Low 0 3 0 5 Voltage Quiet 3 3 Vorv Output note 1 2 0 5 0 3 Vinp Dynamic High 3 3 2 2 Voltage Input note C 50 pF V 1 3 Vitp Dynamic Low 3 3 0 9 Voltage Input note 1 3 1 Worst case package 2 Max number of outputs defined as n Data inputs are driven OV to 3 3V n 1 outputs switching and one output at GND 3 Max number of data inputs n swi
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6. t consumption without load Refer to Test Circuit Average operating current can be obtained by the following equation Icc opr Cpp X Vc X fin lcc 4 per gate Figure 3 Test Circuit SC12220 Cj 15 50pF or equivalent includes jig and probe capacitance R7 Zour 0f pulse generator typically 509 a 4 11 74LVX132 Figure 4 Waveform Propagation Delays f 1MHz 50 duty cycle SC08641 ky 5 1 74LVX132 S0 14 MECHANICAL DATA mm inch DIM A 1 35 Kr 1 75 0 053 0 069 At 0 1 0 25 0 010 A2 1 10 1 65 0 065 B 0 33 0 51 0 020 c 0 19 0 25 0 010 D 8 55 8 75 0 344 E 3 8 4 0 0 157 H 5 8 6 2 0 244 h 0 25 0 50 0 020 L 0 4 1 27 0 050 ddd 0 100 0 004 hx45 Jel SIN den Al C IS dad c SEATING PLANE 0 25 mm C GAGE PLANE 14 8 E H a 1 Pi 0016019D 6 11 ky 74LVX132 TSSOP14 MECHANICAL DATA 0 173 0 0256 BSC 8 0 8 L 0 45 0 60 0 75 0 018 0 024 0 030 PIN 1 IDENTIFICATION 0080337D 3 7 14 74LVX132 Tape amp Reel SO 14 MECHANICAL DATA
7. tching n 1 switching OV to 3 3V Inputs under test switching 3 3V to threshold Vj p OV to threshold Vin f 1MHz lt 3 11 74LVX132 Table 8 AC Electrical Characteristics Input t t 3ns Test Condition Value Symbol Parameter Vec CL Ta 25 C 40 to 85 C 55 to 125 C Unit V PF Min Typ Max Min Max Min Max tprytpHL Propagation Delay 2 7 15 75 105 1 0 12 0 1 0 12 0 Time 27 50 8 3 120 1 0 13 5 1 0 13 5 330 15 5 9 8 0 1 0 9 0 1 0 9 0 ns 3 30 50 6 5 9 0 1 0 10 0 1 0 10 0 tostH Output To Output 2 7 50 0 5 1 0 1 5 1 5 tosHL a Time note1 330 so 0 5 1 0 1 5 1 5 ns 1 Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch ing in the same direction either HIGH or LOW 2 Parameter guaranteed by design Voltage range is 3 3V 0 3V Table 9 Capacitive Characteristics Test Condition Value Symbol Parameter Vcc Ta 25 C 40 to 85 C 55 to 125 C Unit V Min Typ Max Min Max Min Max Cin Input Capacitance 3 3 6 10 10 10 pF Cpp _ Power Dissipation Capacitance 3 3 16 pF note 1 1 Cpp is defined as the value of the IC s internal equivalent capacitance which is calculated from the operating curren
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ST 74LVX132 handbook