ST 74LVX3245 handbook
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1. 7TALVX3245 OCTAL DUAL SUPPLY BUS TRANSCEIVER m HIGH SPEED tpp 8ns at 25 Veca 3 3V 5 0V LOW POWER DISSIPATION loca 5uA MAX at 25 LOW NOISE p 0 3V TYP at Voc 3 3V SYMMETRICAL OUTPUT IMPEDANCE lo 24mA MIN m BALANCED PROPAGATION DELAYS tPLH PHL OPERATING VOLTAGE RANGE VccA OPR 22 7V103 6V 1 2V Data Retention Vccg OPR 2 4 5Vto 5 5V 1 2V Data Retention PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 3245 m IMPROVED LATCH UP IMMUNITY DESCRIPTION The 74LVX3245 is a dual supply low voltage CMOS OCTAL BUS TRANSCEIVER fabricated with sub micron silicon gate and double layer metal wiring C MOS technology Designed for use as an interface between a 5V bus and a 3 3V bus in a mixed 5V 3 3V supply systems it achieves high speed operation while maintaining the CMOS low power dissipation Figure 1 Pin Connection And IEC Logic Symbols Er ILI LLEICILCE E EC PC12140 August 2004 Table 1 Order Codes PACKAGE T amp R 741 3245 TSSOP 74LVX3245TTR This IC is intended for two way asynchronous communication between data buses and the direction of data transmission is determined by DIR input The enable input G can be used to disable the device so that the buses are effectively isolated The A port interfaces with the bus the B port with the 5V bus All inputs are equipped with protectio2. 1 Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch ing in the same direction either HIGH or LOW 2 Parameter guaranteed by design 3 Typical values at Veca 3 3V 5 0V Voltage range is 3 0V 0 3V 3 5 13 74LVX3245 Table 10 Capacitive Characteristics Test Condition Value Symbol Parameter 25 40 to 85 55 to 125 C Unit V V Min Typ Max Min Max Min Max Input open open 4 5 V Capacitance Co Input Output 3 3 5 0 10 V Capacitance Cpp Low 3 3 5 0 55 V Level Quiet Output note 1 Ato B Cpp Dynamic Low 3 3 5 0 40 V Level Quiet Output note 1 BtoA 1 Cpp is defined as the value of the IC s internal equivalent capacitance which is calculated from the operating current consumption without load Refer to Test Circuit Average current can be obtained by the following equation Cpp Vcc X fin Icc 8 per circuit Figure 3 Test Circuit PULSE GENERATOR SC08570 TEST SWITCH PHL Open tpLz 2Vcc lpzH tpuz Open C 50pF or equivalent includes jig and probe capacitance R R4 5000 or equivalent Zour of pulse generator typically 500 6 13 3 74LVX3245 Figure
3. 8 6 5 5 Vi Voc or GND 041 1 1 pA loza High Impedance 3 6 5 5 Vig Vina Or Vita 0 5 5 5 pA Output Leakage Vig Vins OF Vip oF GND Iccta Quiescent Supply 3 6 5 5 Via VccA or 5 50 50 pA Current GND Vig Voce or GND Alccta Maximum 3 6 5 5 0 6V 0 35 0 5 0 5 mA Quiescent Supply Vig or Current Input GND An DIR G kyr 3 13 74LVX3245 Table 7 DC Specifications For Test Condition Value Symbol Parameter 25 40 to 85 55 to 125 C Unit CCB Ving High Level Input 3 3 4 5 2 0 2 0 2 0 Voltage 3 3 5 5 2 0 2 0 2 0 Vig Low Level Input 3 3 4 5 0 8 0 8 0 8 Voltage 3 3 5 5 0 8 0 8 0 8 High Level 3 0 4 5 100 uA 44 45 4 4 4 4 Output Voltage 35 45 10 24 386 425 3 75 3 75 Low Level Output 3 0 4 5 100 0 002 04 0 1 0 1 Voltage 38 45 224 mA V o 24 0 18 0 36 0 44 0 44 lip Input Leakage d n Current 3 6 5 5 Vi or GND 0 1 1 1 uA 2 High Impedance 3 6 5 5 ViA VIHA or VILA 0 5 5 5 Output Leakage Or GND Quiescent
4. NC QR Spes dor MU I 1 Ko Ao 4 Note Drawing not in scale 10 13 74LVX3245 Tape amp Reel TSSOP24 MECHANICAL DATA P 11 9 12 1 0 468 0 476 N 1 NN EO Os E KO Ao Lok Note Drawing not in scale ky 11 13 74LVX3245 Table 11 Revision History Date Revision Description of Changes 27 Aug 2004 4 Ordering Codes Revision pag 1 12 13 74LVX3245 Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective ow
5. 4 Waveform Propagation Delays f 1MHz 50 duty cycle 1 2 5 09692 Figure 5 Waveform Output Enable And Disable Time f 1MHz 50 duty cycle tezH 1Yn 2Yn 1Yn 2Yn 504940 r 713 74LVX3245 SO 24 MECHANICAL DATA 0 100 0 004 D hx45 f M 11 SI plete j B ls 1 ddd C SEATING 24 3 PLANE i C 0 25 mm GAGE PLANE bz 4 IDENTIFICATION EH Y PERSE 9 i Hi pd M BS 2 o 0070769 8 13 74LVX3245 TSSOP24 MECHANICAL DATA 0 65 BSC 0 0256 BSC PIN 1 IDENTIFICATION 7047476B 9 13 74LVX3245 Tape amp Reel SO 24 MECHANICAL DATA P 11 9 12 1 0 468 0 476 Y Y A 1 A EB Po Bo
6. Parameter Veca 25 C 40 to 85 C 55 to 125 C Unit V Min Typ Max Min Max Min Max Propagation Delay 2 7 1 0 9 0 1 0 10 0 Time An to Bn 3 0 10 54 80 10 85 10 95 teu Propagation Delay 2 7 85 10 95 302 1 0 56 7 5 10 80 10 95 tpz_ Output Enable 2 7 1 0 9 0 1 0 10 0 Time G to Bn 10 48 8 0 10 85 1 0 95 tezu Output Enable 27 95 10 105 5 Time G to Bn 10 63 85 10 90 1 0 100 Output Disable 2 7 1 0 85 1 0 9 5 Time G to Bn 3 0 10 53 75 10 85 10 95 tpuz Output Disable 27 10 90 Time G to Bn 3 0 10 42 70 10 75 1 0 85 Propagation Delay 2 7 1 0 8 5 1 0 9 5 Time Bn to An 3 0 1 0 5 1 7 5 1 0 8 0 1 0 8 5 iPHL Propagation Delay 2 7 85 10 90 7 Time Bn to An 300 10 57 75 10 80 10 85 Output Enable 2 7 10 95 1 0 10 0 Time G to An 10 63 85 10 90 10 95 Output Enable 27 100 105 Time to An 10 68 9 0 10 95 1 0 10 0 tp_z Output Disable 2 7 1 0 9 0 1 0 9 5 Time G to An 10 53 8 0 10 85 1 0 9 0 tpuz Output Disable 27 75 10 80 Time G to An 10 37 65 10 70 1 0 8 0 tostH Output To Output 2 7 0 5 1 0 1 5 1 5 tosHL 3 Time notet 5 gc 05 1 0 1 5 1 5 ns
7. Supply 3 6 5 5 Via VccA OF 8 80 80 uA Current GND Vig Voce or GND AlcciB Maximum 3 6 5 5 Voca or 1 35 1 5 1 5 mA Quiescent Supply GND Current Input Vip Vccp 2 1V Table 8 Dynamic Switching Characteristics Test Condition Value Symbol Parameter V V 25 40 to 85 55 to 125 C Unit CCB v VoipA Dynamic Low 3 3 5 0 1 0 1 5 Level Quiet V Output note 1 2 3 3 5 0 1 2 0 6 Dynamic Low 3 3 5 0 0 8 1 2 Level Quiet V Output note 1 2 3 3 5 0 0 8 0 5 Vipa Dynamic High Voltage Input 3 3 5 0 2 V note 1 3 Vipa Dynamic Low Voltage Input 3 3 5 0 0 8 V note 1 3 Dynamic High Voltage Input 3 3 5 0 2 V note 1 3 Vupg Dynamic Low Voltage Input 3 3 5 0 0 8 V note 1 3 1 Worst case package 2 Max number of output defined as n Data inputs are driven OV to 3 3V n 1 outputs switching and one output at GND 3 Max number of data inputs n switching n 1 switching OV to 3 3V Inputs under test switching to threshold Vj p OV to threshold f 1MHz 4 13 ky Table 9 AC Electrical Characteristics C 5OpF Input t t 3ns 74LVX3245 Test Condition Value 9 Symbol
8. m Ratings are those values beyond which damage to the device may occur Functional operation under these conditions is not 2 13 74LVX3245 Table 5 Recommended Operating Conditions Symbol Parameter Value Unit Voca Supply Voltage note 1 2 7 to 3 6 V Supply Voltage note 1 4 5 to 5 5 V Vi Input Voltage 0 to Veca V VyoA O Voltage 0 to VccA V Voltage 0 to Vccp V Top Operating Temperature 55 to 125 C dt dv Input Rise and Fall Time note 2 0 to 10 ns V 1 Vix from 30 to 70 of Voc 2 Voca 2 7 to 3 6V 4 5 to 5 5V Table 6 DC Specifications For VccA Test Condition Value Symbol Parameter Veca Vece 25 40 to 85 55 to 125 C Unit V V Min Typ Max Min Max Min Max Vina High Level Input 3 6 5 0 2 0 2 0 2 0 Voltage 2 7 5 0 2 0 2 0 2 0 y Vita Low Level Input 3 6 5 0 0 8 0 8 0 8 Voltage 27 5 0 0 8 0 8 08 V Voua High Level 3 0 45 Io 100 uA 2 9 2 99 2 9 2 9 Output Voltage 35 45 24 2 35 2 65 225 225 27 45 Io 12 2 3 2 5 2 2 2 2 2 7 45 lo 24 mA 2 1 2 3 2 0 2 0 Vota Low Level Output 3 0 4 5 10 100 uA 0 002 0 1 0 1 0 1 Voltage 80 45 10224 mA 0 21 0 36 0 44 0 44 27 45 10 12 mA 0 11 0 36 0 44 0 44 5 2 7 45 24 mA 0 22 0 42 0 5 0 5
9. n circuits against static discharge giving them 2KV ESD immunity and transient excess voltage 1 13 74LVX3245 Figure 2 Input And Output Equivalent Circuit Table 2 Pin Description PIN N SYMBOL NAME QND FUNCTION 2 DIR Directional Control 3 4 5 6 7 1 to A8 Data Inputs Outputs 8 9 10 21 20 19 B1 8 Data Inputs Outputs 18 17 16 15 14 22 Output Enable Input 11 12 13 GND Ground 0V 23 NC Not Connected GND 1 Veca Positive Supply Voltage 24 Positive Supply Voltage Table 3 Truth Table INPUTS FUNCTION OUTPUT G DIR A BUS B BUS L L OUTPUT INPUT A B L H INPUT OUTPUT B A H X 2 2 2 X Don t Care Z High Impedance Table 4 Absolute Maximum Ratings Symbol Parameter Value Unit Voca Supply Voltage 0 5 to 7 0 V VccB Supply Voltage 0 5 to 7 0 V Vi DC Input Voltage 0 5 to Voca 0 5 V VUOA DC I O Voltage 0 5 to 0 5 V DC I O Voltage 0 5 to 0 5 V lic DC Input Diode Current 20 lok DC Output Diode Current 50 mA loa DC Output Current 50 mA DC Output Current 50 mA DC or Ground Current 200 mA DC or Ground Current 100 mA Power Dissipation 180 mW Tstg Storage Temperature 65 to 4150 C Lead Temperature 10 sec 300 C EE Maximu
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ST 74LVX3245 handbook