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ST M74HC109 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR handbook

1. Test Condition Value Symbol Parameter 25 C 40 to 85 55 to 125 Unit V Min Typ Max Min Max Min Max Output Transition 2 0 30 75 95 110 Time 4 5 8 15 19 22 ns 6 0 7 13 16 19 Propagation Delay 2 0 50 150 190 225 Time CK Q 0 4 5 16 30 38 45 ns 6 0 13 26 32 38 tpi Propagation Delay 2 0 50 150 190 225 Time CLR PR 45 16 30 38 45 ns Q Q 6 0 13 26 32 38 fmax Maximum Clock 2 0 6 2 17 5 4 2 Frequency 4 5 31 59 25 21 MHz 6 0 37 67 30 25 Minimum Pulse 2 0 15 75 95 110 tw Width CK 4 5 6 15 19 22 ns 6 0 6 13 16 19 tw Minimum Pulse 2 0 15 75 95 10 Width CLR PR 4 5 6 15 19 22 ns 6 0 6 13 16 19 ts Minimum Set Up 2 0 17 75 95 110 Time 4 5 5 15 19 22 ns 6 0 4 13 16 19 th Minimum Hold 2 0 0 0 0 Time 4 5 0 0 0 ns 6 0 0 0 0 trem Minimum Removal 2 0 13 50 65 75 Time CLR PR 4 5 4 10 13 15 ns 6 0 3 9 11 13 CAPACITIVE CHARACTERISTICS Test Condition Value Symbol Parameter Vcc 25 C 40 to 85 C 55 to 125 C Unit Min Typ Max Min Max Min Max Input Capacitance 5 0 5 10 10 10 pF Cpp Power Dissipation Capacitance note 5 0 41 pF 1 1 is defined as the value of the IC s internal equiv
2. M74HC109 DUAL J K FLIP FLOP WITH PRESET AND CLEAR HIGH SPEED 67MHz Voc 6V m LOW POWER DISSIPATION Icc lt 2 at Ta 25 C m HIGH NOISE IMMUNITY 28 Voc MIN m SYMMETRICAL OUTPUT IMPEDANCE 4mA MIN m BALANCED PROPAGATION DELAYS PHL a WIDE OPERATING VOLTAGE RANGE Vcc OPR 2V to 6V m PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 109 DESCRIPTION The M74HC109 is an high speed CMOS DUAL J K FLIP FLOP WITH PRESET AND CLEAR fabricated with silicon gate 2 5 technology In accordance with the logic level on the J and K input this device changes state on positive going transition of the clock pulse CLEAR and PRESET PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 ORDER CODES TUBE DP SOP 7950 MAHOIOSTTR are independent of the clock are accomplished by a logic low on the corresponding input All inputs are equipped with protection circuits against static discharge and transient excess voltage T amp R 1611150 1 12 M74HC109 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION Alp Asynchronous Reset v 1 3 Vec 1 15 1CLR 2CLR
3. 6 5 3 0 181 0 208 M 0 62 0 024 S 8 max L G M cl 5 PO13H M74HC109 TSSOP16 MECHANICAL DATA mm inch DIM MIN TYP MAX MIN TYP MAX A 1 2 0 047 A1 0 05 0 15 0 002 0 004 0 006 A2 1 05 0 031 0 039 0 041 b 0 19 umm 0 30 0 007 0 012 0 20 0 004 0 0089 D 4 9 5 5 1 0 193 0 197 0 201 E 6 2 6 4 6 6 0 244 0 252 0 260 E1 4 3 4 4 4 48 0 169 0 173 0 176 e 0 65 BSC 0 0256 BSC K 0 8 0 8 L 0 45 0 60 0 75 0 018 0 024 0 030 SARA D ky PIN 1 IDENTIFICATION 1 00803380 11 12 M74HC109 Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics 2001 STMicroelectronics Printed in Italy Rights Reserved STMicroelectronics GROUP O
4. Direct Input 4 1J 2J 1K Synchronous Inputs TM 2K Flip Flops 1 and 2 A 4 12 1CK 2CK Clock Input l 55 Set Direct io n SM Input Active Low be 6 10 1Q 2Q True Flip Flop Outputs GND GND Complement Flip Flop 21 i 10 29 Outputs SD 8 GND Ground 0V 16 Vcc Positive Supply Voltage TRUTH TABLE INPUTS OUTPUTS FUNCTION CLR PR J K CK Q Q L H X X X L H CLEAR H L X X X H L PRESET L L X X X H H H H L H E Qn Qn NO CHANGE H H L L _ L H H H H H Eu H L H H H L 1 Qn TOGGLE H H X X L Qn Qn NO CHANGE X Don t Care LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2 2 M74HC109 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Voc Supply Voltage 0 5 to 7 V Vi DC Input Voltage 0 5 to Voc 0 5 V Vo DC Output Voltage 0 5 to Voc 0 5 V lik DC Input Diode Current 20 mA lox DC Output Diode Current 20 mA lo DC Output Current 25 mA Icc or lanp DC Vec or Ground Current 550 mA Pp Power Dissipation 500 mW Tstg Storage Temperature 65 to 4150 C TL Lead Temperature 10 sec 300 C Absolute Maximum Ratings are those values beyond which damage to the device may occur Functional operation under these conditions is not implied 500mW at 65 C derate to 300mW by 10mW C from 65 C to 85 C RECOMMENDED OPERATING CONDITION
5. F COMPANIES Australia Brazil China Finland France Germany Hong Kong India Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom http www st com 12 12 ky
6. S Symbol Parameter Value Unit Voc Supply Voltage 2106 V VI Input Voltage 0 to Voc V Vo Output Voltage 0 to Voc V Top Operating Temperature 55 to 125 C Input Rise and Fall Time Voc 2 0V 0 to 1000 ns tht Voc 4 5V 0 to 500 ns Voc 6 0V 0 to 400 ns yy 3 12 M74HC109 DC SPECIFICATIONS Test Condition Value Symbol Parameter 25 C 40 to 85 C 55 to 125 C Unit V Min Typ Max Min Max Min Max High Level Input 2 0 1 5 1 5 1 5 Voltage 4 5 3 15 3 15 3 15 V 6 0 4 2 4 2 4 2 Vit Low Level Input 2 0 0 5 0 5 0 5 Voltage 4 5 1 35 1 35 135 V 6 0 18 18 1 8 Vou High Level Output 2 0 20 uA 19 2 0 1 9 1 9 voltage 4 5 lo 20 pA 44 45 44 44 6 0 20 uA 59 6 0 5 9 5 9 V 4 5 4 0 mA 4 18 4 31 4 13 4 10 6 0 Io 5 2 mA 5 68 5 8 5 63 5 60 VoL Level Output 2 0 20 uA 0 0 0 1 0 1 0 1 Voltage 4 5 10 20 pA 0 0 0 1 0 1 0 1 6 0 20 pA 0 0 0 1 0 1 v 4 5 4 0 0 17 0 26 0 33 0 40 6 0 5 2 mA 0 18 0 26 0 33 0 40 6 0 Vi Veo or GND 0 1 1 1 pA Quiescent Supply Vi Voc or GND 2 20 40 pA 4 12 ky AC ELECTRICAL CHARACTERISTICS C 50 pF Input t t 6ns M74HC109
7. alent capacitance which is calculated from the operating current consumption without load Refer to Test Circuit Average operating current can be obtained by the following equation Cpp X Voc X fin 2 per FLIP FLOP 5 2 M74HC109 TEST CIRCUIT 5 12220 C 50pF or equivalent includes jig and probe capacitance Zour of pulse generator typically 500 WAVEFORM 1 PROPAGATION DELAY TIMES SETUP AND HOLD TIMES MINIMUM PULSE WIDTH CK f 1MHz 50 duty cycle 6 12 M74HC109 WAVEFORM 2 PROPAGATION DELAY TIMES MINIMUM PULSE WITDTH CLR PR f 1MHz 50 duty cycle CLR GND GND VoL You gi VoL 5 10172 7 12 M74HC109 WAVEFORM 4 MINIMUM REMOVAL TIME PR to CK f 1MHz 50 duty cycle 50 GND Veo 50 GND tREM VOH Q VOL S 1016 1 8 12 ky M74HC109 Plastic DIP 16 0 25 MECHANICAL DATA mm inch DIM MIN TYP MIN TYP MAX a1 0 51 0 020 B 0 77 1 65 0 030 0 065 b 0 5 0 020 E 8 5 0 335 e 2 54 0 100 e3 17 78 0 700 F 7 1 0 280 2 1 27 0 050 P001C r 912 M74HC109 SO 16 MECHANICAL DATA 10 12 mm inch MIN a2 1 65 0 064 C 0 5 0 019 c1 45 typ D 9 8 10 0 385 0 393 5 8 6 2 0 228 0 244 e 1 27 0 050 G 4

ST M74HC109 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR handbook

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