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ALTERA For Stratix II Stratix II GX HardCopy II PowerPlay Early Power Estimator User Guide

1. PortA Thermal Power W RAM RAM Data RAM Clock Enable Write rw Valid s Type Blocks Width Mode d q E al eel Sedan Mais 1 M512 104 9 100 100 Yes 0 022 2 mak 150 0 100 50 Yes 0 018 3 mak 100 0 100 100 ves 0002 0005 0007 4 mak v 1249 100 0 oo 0 o ves 000 0002 0002 5 mak 18 simple DuatPor 150 0 100 50 150 0 100 100 ves 0003 0008 0011 Mak 24 _ Single Port 751 100 so 00 0 0 ves 0001 0002 0008 7 MRAM 72 Single Port so oo 0 0 ves 0005 0038 0 043 mak so 00 25 so ves 0000 0000 0 000 mak 50 oo 25 sos ves 0000 0000 0 000 Altera Corporation January 2007 Digital Signal Processing DSP Stratix II and Stratix II GX devices have dedicated DSP blocks that can implement high speed parallel processing optimized for DSP applications DSP blocks are ideal for implementing DSP applications that need high data throughput The Digital Signal Processing DSP section in the PowerPlay Early Power Estimator spreadsheet provides power information for Stratix II DSP blocks gt HardCopy II devices use HCell macros which implement the supported modes of operation for the Stratix II DSP block 3 15 PowerPlay Early Power Estimator For Stratix Il Stratix Il GX amp HardCopy II PowerPlay Early Power Estimator
2. er do Nom Y Y Y Stratix Il Device e ANN MN ANN ANN Thermal Pr Thermal Ppp Thermal Pig External Pig The VRgr pins consume minimal current less than 10 WA and is negligible when compared to the power consumed by the general purpose I O pins Therefore the PowerPlay Early Power Estimator spreadsheet does not include the current for Vrgr pins in the calculations Each row in the I O section represents a design module where the I O pins have the same frequency toggle percentage average capacitive load I O standard drive strength on chip termination data rate and I O bank You must enter the following parameters for each design module I O standard Drive strength On chip termination Clock frequency fmax in MHz Number of output input and bidirectional pins I O bank Pin toggle percentage Output enable percentage Average capacitance of the load I O data rate Altera Corporation 3 19 January 2007 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II PowerPlay Early Power Estimator Inputs Table 3 5 describes the I O bank parameters in the I O section of the PowerPlay Early Power Estimator Table 3 5 1 0 Bank Information in the I O Section Column Heading Description Vecio Select the Vccio voltage for each bank Used to cross check selected I O standards in table below for warning purposes lccio A This shows the total
3. RAM Blocks Stratix II and Stratix II GX device TriMatrix memory consists of three types of RAM blocks M512 M4K and M RAM blocks The power consumption for each type of RAM block is different and must be specified in the RAM section of the PowerPlay Early Power Estimator HardCopy II devices contain two types of RAM blocks M4K and M RAM Each row in the RAM section represents a design module where the RAM block s are the same type have the same data width RAM mode and the same port parameters If some or all of the RAM blocks in your design have different configurations enter the information in different rows For each design module you need to enter the type of RAM being implemented the number of RAM blocks and the RAM block mode You must also enter the following parameters for each port m Clock frequency in MHz E The percentage of time the RAM clock is enabled E The percentage of time the port is writing compared to reading 3 10 Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator HO When selecting the RAM block mode you must know how your RAM is implemented by the Quartus II Compiler For example if a ROM is implemented with two ports it is considered a true dual port memory and not a ROM Single port and ROM implementations only use port A Simple dual port and true dual port implement
4. 1 LVTTLLVCMOS 1 8 V ema v 00 22 D o s 7 00 100 0 0 sov PASS PASS 0 000 0 001 0001 0 000 0 000 0 000 2 LVTTLALVCMOS 2 5 V 16 ma v 1000 0 0 B j10 vw 358 500 O R di PASS PASS 0 000 0005 0005 0 001 0 001 0001 3 LDS Defaut v 8401 9 0 0 2 LZ 0 0 100 0 O soR w PASS PASS 0000 0 140 0 140 0 003 0 000 0060 4 WITL3 3 24ma 7 00 0 1 0 hd 00 1000 O soR v PASS PASS 0 000 0000 0000 0000 0 000 0000 5 HSTL Class I1 1 8 20 mA v 1000 20 o v 00 100 0 o joriy PASS PASS 0000 0 148 0 148 0000 0 000 0241 6 wm aas o 24 mA v 998 0 1 o 3 7 200 0 1000 O soR v PASS PASS ooo 0001 0 002 0001 0 000 0 000 7 tm 334 12m z 0 o 1 o ls x 200 100 0 o se v PASS PASS ooo oom ooo ooo oom oo 1 WT 3 34 ima v 748 1 0 o izi 59 4 1000 O sor v PASS PASS 0 000 0 002 0002 0 000 0 000 0 000 9 WITL3 3 24ma vj 00 0 1 o 3 7 00 1000 0 sr v PASS PASS 0 000 0000 0000 0000 0000 0000 10 LVTTLLNCMOS 2 5 4 16 mA v 1000 0 0 30 iz 33 4 50 0 O soR v PASS PASS 0002 0023 0025 0006 0 003 0005 1 LVTTL 33 24m vj 1500 36 o 08 S 36 3 100 0 0 SDR v PASS PASS 0000 0 088 0088 0 004 0010 0 015 12 LDS Defaut v 8401 D 10 0 2 Z 0 0 1000 O soR v PASS PASS 0 000 0 063 0063 0 029 0 000 0011 13 LYTTL LYCMOS 2 54 16m v 00 0 1 D jz iz 0 0
5. 100 0 0 soR w PASS PASS 0 000 0 000 0 000 0 000 0 000 0000 14 WITL3 3 um v 1750 8 o o 3 v 00 100 o soR vw PASS PASS 0 000 oooo 0000 0000 oooo 0000 15 LVTTLLYCMOS 1 8 4 12m4 v 00 6 0 o 9 v 00 1000 0 sor S PASS PASS 0000 0000 0000 0000 0 000 0000 16 WT 3 34 12mA vj 751 0 1 0 j B 65 9 100 0 0 SDR v PASS PASS 0000 0 000 0 000 0000 0 000 0000 17 WDS Defaut v 1050 0 1 D 2 IM 200 09 100 0 O sor v PASS PASS 0 000 0 006 0007 0004 0 000 0 001 18 LVTTL 3 3 12mA vj 1750 0 1 o je I 200 0 100 0 O sor v PASS PASS 0 001 0 002 0003 0 001 0 000 0001 19 umas ED z 00 o 2 o e v 495 1000 o sor y PASS PASS oom 0 001 0001 000t 0 000 0000 20 LVTTL 3 34 24 nA v 998 0 D o 8 iz 20009 100 0 0 soR v PASS PASS 0 000 0001 0002 0001 0 000 0 000 A LVTTL 3 3 12m4 J 100 0 1 D O 6 v 154 5 1000 0 RLZ PASS PASS 0000 0 008 0008 0 000 0001 0002 2 LDS Defaut v 8401 0 8 o 1 lel 00 100 0 0 soR v PASS PASS 0000 0051 0 051 0023 0 000 0009 23 LDS Default v 8401 9 0 D S 0 0 100 0 O soe e PASS PASS 0000 0 140 0 140 0 003 0 000 0 060 24 LVTTLALVCMOS 1 8 V 12 mA vj 00 8 0 o 4 7 00 100 0 0 soR v PASS PASS 0 000 0 000 0000 0 000 0 000 0 000 25 Jumas 24 mA Sen o 2 0 fe 222 woow o Pass Pass nemo omo o oo ooo omo 26 LVTTL 3 3
6. using the dedicated input registers If the dedicated input registers in the DSP or multiplier block are being used select Yes If the inputs are registered using registers in ALMs then the value is No Reg Outputs Select whether the outputs of the dedicated DSP block or multiplier block is registered using the dedicated output registers If the dedicated output registers in the DSP or multiplier block are being used select Yes If the outputs are registered using registers in ALMs then the value is No Pipe lined Select whether the dedicated DSP block is pipelined Routing This shows the power dissipation due to estimated routing in W Routing power is highly dependent on placement and routing which is itself a function of design complexity The values shown are representative of routing power based on experimentation on over 100 customer designs Use the Quartus Il PowerPlay Power Analyzer for detailed analysis based on the routing used in your design This value is calculated automatically Block This shows the estimated power consumed by the DSP blocks in W This value is calculated automatically Total This shows the estimated power in W based on the inputs you entered It is the total power consumed by DSP blocks and is equal to the routing power and the block power This value is calculated automatically User Comments Enter any comments This is an optional entry Altera Corporation Janua
7. 4 ALUT Usage in Resource Usage Summary ALUT usage by number of inputs 7 input functions 6 input functions 5 input functions 4 input functions lt 3 input functions Register only Combinational cells for routing Altera Corporation 3 9 January 2007 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II PowerPlay Early Power Estimator Inputs Figure 3 5 shows the device PowerPlay Early Power Estimator spreadsheet and the estimated power consumed by the logic in this design Figure 3 5 Logic Section in the PowerPlay Early Power Estimator Total Thermal Power W 0 845 39 3 5 6 Estimated LUT Utilization FF Utilization Thermal Power W Combinational Toggle ALUTs ASE TC Module Routing Block Total 12 5 0 000 0 000 0 000 0 12 5 0 000 0 000 0 000 0 0 0 0 1 D 0 0 2 0 0 3 100 0 111 D 48 196 0 002 j 0 004 0 006 4 150 0 86 D 37 3 0 002 0 003 0 005 5 124 9 9 0 41 7 0 000 0 000 0 001 6 75 1 10175 D 92 6 0 316 0 474 0 790 7 105 0 107 0 0 0 0 000 0 000 0 000 8 74 8 27 19 5 0 000 0 000 0 000 9 104 9 D 144 0 0 0 000 0 000 0 000 10 100 0 0 123 31 9 0 004 0 001 0 005 11 150 0 D 87 33 2 0 005 0 001 0 006 12 124 9 9 21 7 0 000 0 000 0 000 13 75 1 0 1003 28 8 0 024 0 006 0 030 14 104 9 0 144 0 0 0 000 0 000 0 000 D 0
8. Estimator e Family e Device e Package e Temperature grade e Power characteristics e Ambient or junction temperature e Airflow e Heat sink e Custom Os or custom 01 e Board thermal model e Custom Dip e Board temp Tg The ambient or junction temperature airflow heat sink custom 054 or custom 0j4 board thermal model custom Oy and board temperature Tg parameters are optional See Main Input Parameters on page 3 1 for more information on these parameters The fmax values imported into the PowerPlay Early Power Estimator spreadsheet are the same as the fmax values specified by the designer in the Quartus II software You can manually edit the fyax and the toggle percentage in the PowerPlay Early Power Estimator spreadsheet to suit your system requirements Importing Information from PowerPlay Early Power Estimator v6 0 If you already have an existing version 6 0 PowerPlay Early Power Estimator file you can import the data directly into version 6 1 of the PowerPlay Early Power Estimator spreadsheet using the Import Legacy feature This can save time and effort otherwise spent manually entering information into the PowerPlay Early Power Estimator To import data from legacy versions of the PowerPlay Early Power Estimator perform the following steps 1 Click the Import EPE v6 0 button 2 Browse to the EPE and click Open 3 Click OK Clicking OK acknowledges that the import is complete Clicking OK clears an
9. Estimator Thermal Analysis Junction Temp T C 9 4 Junction Ambient 84 Junction Board Maximum Allowed Ta C Details Table 3 13 describes the thermal analysis parameters in the PowerPlay Early Power Estimator Table 3 13 Thermal Analysis Section Information Column Heading Junction Temp T C Description This shows the device junction temperature estimated based on supplied thermal parameters The junction temperature is determined by dissipating the total thermal power through the top of the chip and through the board if selected See Details for detailed calculations used 954 Junction Ambient This shows the junction to ambient thermal resistance between the device and ambient air in C W This represents the increase in temperature between ambient and junction for every Watt of additional power dissipation 0 g Junction Board Maximum Allowed TA C This shows the junction to board thermal resistance in C W This is used in conjunction with the board temperature as well as the top of chip 8 and ambient temperatures to compute junction temperature This shows a guideline for the maximum ambient temperature in C that the device can be subjected to without violating maximum junction temperature based on the supplied cooling solution and device temperature grade Altera Corporation January 2007 Power Supply Current A The power supply c
10. Figure 3 7 shows the RAM Summary in the Quartus II software Compilation Report for a design targeting the device family The Compilation Report provides the RAM type the RAM mode and the data width Figure 3 7 RAM Summary in Compilation Report Fitter RAM Summary m ITEM EHE HE El tar mse eet us jus Ju EIE Caec instihnccancitoncram componentillumcram chin cene PETS YNCRAM E Pat 2 6 re e EE See O 5 1 2 Case3inst23laltsyncram altsyncram componentlalisyncram 1ge1 auto generatediLTSYNCRAM MAK Simple Dual Port 256 36 256 36 yes mo yes yes 9216 9216 0 2 0 ls Case3 instlatsyncram altsyncram_componentlaltsyncram_1qe1 auto_generatediALTSYNCRAM MAK Simple Dual Port 256 35 256 36 yes no yes yes 9216 19216 0 2 0 4 Casedinst20laltsyncramaltsynctam componentlaltsyncram paql auto generatediALTSYNCRAM MK Tue Dug Pat 512 36 512 35 yes yes yes yes 18432 18432 0 4 0 5 Case7 inst 3laltsyncram altsyncram componentlalisynciam 1Buauto generatedALTSYNCRAM Mak ROM 52 8 e ves ves E 4096 4096 0 T 0 B myRateMatchiinst1Slaltsyncramcaltsyncram_componentlatsynctam_36d1 auto_generatedALTSYNCRAM M512 Simple DualPor 128 144 128 144 lyes no yes ves 18432 288 8 0 0 Figure 3 8 shows the PowerPlay Early Power Estimator spreadsheet and the estimated power consumed by RAM blocks in this design Figure 3 8 RAM Section in the PowerPlay Early Power Estimator M512 Utilization M4K Utilization MRAM Utilization
11. Input Bidir Termination MHz t Pins Pins Routin Block Total IccINT IccPD IeclO 1 LVTTULVCMOS 19 V 2 LVTTLILVCMOS 2 5 V PASS 0000 0005 0005 0 001 0 001 0 001 3 Lvos PASS 0000 0140 0 0 0003 0000 0 060 4 LYTTL3 3 PASS noo 0000 ooo 0000 oooo 0 000 5 HSTL Class Il 1 8 PASS 0 000 0 148 0 148 0 000 0 000 0241 6 LYTTL9 3 PASS 0000 oom 0002 oom 0900 0 000 7 LYTTL3 3 PASS noo oom oom ooo oooo 0 000 8 LYTTL3 3 PASS 0 000 0 002 0 002 0 000 0 000 0 000 a LYTTLS 3 PASS noo oon oooo 000 0000 0o00 10 LYTTLILYCMOS 2 5 PASS 0 002 0 023 0 025 0 006 0 003 0 005 n LYTTL3 3 PASS 0 000 0 088 0 088 0 004 0 010 0 015 12 vos u PASS 0 000 0 063 0 063 0 029 0 000 0 011 m LVITLILVCMOS 2 5 PASS 0 000 0 000 0 000 0 000 0 000 0 000 mn LVTTLS 3 V PASS 0000 0000 0900 0000 0900 0000 5 LYTTLILYCMOS 1 8 PASS 0 000 0 000 0 000 0 000 0 000 0 000 16 LYTTL3 3 PASS 0000 0000 0 000 0000 0000 0000 T Lvos PASS 0000 0006 0007 0004 0000 0 001 18 LVTTL 3 34 PASS 0001 0002 0003 oom 0 000 0 001 19 LVTTL 3 34 PASS 0000 0001 0 001 0001 0000 0 000 20 LVTTLS 3 V PASS 0000 oom 0002 0001 0 000 0 000 2 LYTTL3 9 PASS ooo 0008 0008 0000 oom 0002 22 tvs PASS ooo 005 0051 0023 0 000 0 009 2 Lvos PASS 0000 0 140 0140 0
12. Pins sss seene High Speed Differential Interface HSDI Phase Locked Loops PLLS ret tinrin in ie aerias rraian CIOCKS E P POE EEE EA S oq ted i tinh Pa ta anda es Transceiver XCVR Power Analysis Thermal POW T Thermal Analysis Not Using a Heat Sink Altera Corporation iii Contents Using a eat Sink e Power Supply Current A T nrc J a cadteani JAUTEIOW Sa E EE TEE EEE EE ice oaaass sha stisheisassacess RATER ER el eem d IE ERO PRE Temperature vaz os Heat Sin TT iv Altera Corporation PowerPlay Early Power Estimator For Stratix Il Stratix II GX amp HardCopy II About this User Guide Revision Histo y The table below displays the revision history for the chapters in this User G uide Date amp Document Version Changes Made January 2007 v1 2 Updated to match PowerPlay Early Power Estimator v6 1 including e Cover title changed Table 1 1 updated e Chapter 2 System Requirements section updated e Minor edits to page 2 2 through page 2 7 page 3 33 page 3 389 page 3 43 Table 2 1 updated Table 2 2 updated Table 3 1 updated Table 3 14 updated Figure 3 1 updated e Figure 3 24 updated Summary of Changes May 2006 v1 1 Updated cross references to match the new chapter titles for the Quartus Il 6 0 Handbook December 2005 First p
13. Preserve counter order PLL location IncikO signal Ind signal EERBREERERESEENEE Switchover on loss of clock clock0 clock0 100 0MHz 75 0 MHz 100 0 MHz 750MHz 599 9 MHz 750 2 MHz 3532 MHz 71 82 MHz 17343MHz 104 28 MHz 0 0 1 1 6 10 1 1 T4 uA 148 uA 1 000000 KOhm 1 000000 KOhm 5pF 8pF 6 93 MHz 5 51 MHz to 11 99 MHz 5 22 MHz 3 95 MHz to 8 99 MHz off ott Off Off PLL amp PLL 3 hkat k Normal clock0 clock0 100 0 MHz 175 01 MHz 100 0 MHz 1750MHz 599 9 MHz 874 9 MHz 95 92 MHz 95 68 MHz 17343 MHz 208 55 MHz 0 0 1 1 B 5 1 1 T4 uA S2u 11 000000 KOhm 1 000000 KOhm 5pF 2pF 6 93 MHz 5 51 MHz to 11 99 MHz 6 74 MHz 5 41 MHz to 11 96 MHz Oif Off of or PLL 5 PLL 4 ckfreq romok DIFFIOCLK 105 01 MHz 105 0 MHz 840 3 MHz 8 1 87 52 MHz 130 34 MHz 4 1 8 1 131 uA 11 000000 KOhm 2pF 6 08 MHz 4 75 MHz to 10 94 MHz Oif or PLL 2 t relcll DIFFIOCLK 10501 MHz 1050MHz 8403 MHz 8 1 87 52 MHz 13034 MHz 4 13104 1 000000 KOhm 2pF 6 08 MHz 4 75 MHz to 10 94 MHz Of Off PLLA gk 3 30 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II Altera Corporation January 2007 Using the PowerPlay Early Power Estimator Figure 3 20 shows the PowerPlay Early Power Estimator spreadsheet and the estimated power consumed by PLLs in this design Figure 3 20 PLL Section in the PowerPlay Early Power Esti
14. dissipated as heat in the FPGA HardCopy II This shows the approximate total power for the equivalent HardCopy II device This field is only available when a Stratix II device is being used For more information on the HardCopy Il device suggested and further power details click the HardCopy II button Altera Corporation January 2007 Thermal Analysis You can choose to enter T directly or compute T based on information provided If you choose to enter Ty select User Entered Tjin the Input Parameters section If you choose to automatically compute Ty select Auto Computed T in the Input Parameters section When automatically computing Ty the device s ambient temperature the airflow the heat sink solution and the board thermal model are considered to determine the junction temperature Tj in degrees Celsius T is the estimated operating junction temperature based on your device and thermal conditions The device can be considered a heat source and the junction temperature is the temperature at the device For simplicity we can assume that the temperature of the device is constant regardless of where it is being measured In reality the temperature varies across the device Power can be dissipated from the device through many paths Different paths become significant depending on the thermal properties of the system In particular the significance of power dissipation paths vary depending on whether or not a hea
15. oj M5 5 62 24 1 no no no no no no no Off 18V EmA LU y P2 5 62 20 3 no no no no no no no Off 18V Bm 12 N4 5 62 23 1 no no no no no no no Off 18V Bre L3 Gio 4 49 3 2 no no no no no no no Off 18V 12m 14 F13 4 38 37 uU jno no no jno no no no Off 18V 12m ps HM 4 5 3 0 no no no no no no mo Of 18V T2mA Le AE12 10 36 0 0 no no no no no no no Off 18V 12m iU Kn 4 48 37 1 no no no no no no no Off 18V 12m Us AC12 10 39 0 1 no no no no no no no Off 18V 12m4 19 F12 4 42 37 2 no no no no no no no Off 18V 12m4 20 26 AE13 10 36 0 2 no no no no no no no Off 18V 12m4 21 c3outf27 EM 4 48 3 2 no no no no no no no Off 18V 12m Altera Corporation 3 25 January 2007 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II PowerPlay Early Power Estimator Inputs Figure 3 16 shows the PowerPlay Early Power Estimator spreadsheet and the estimated power consumed by the I O pins Figure 3 16 1 O Section in the PowerPlay Early Power Estimator Total Thermal Power tv HO Utilization loco A Veco MED C WO Bank2 ss voBaks EEC uO pant FC LB s l lt uO pant e ERO vOBank7 s l lt voBanks ss ENEM v WO Bank 10 x NIA Ec NIA Unassigned Module HO Standard Thermal Power W Supply Current A Bank HO Toggle e THER ank x x 4 Rate Check Bank Voltage Check Drive Strength Clock amp mn On Chip Freq Outpu
16. sections provide a description of the results of the PowerPlay Early Power Estimator 3 36 Altera Corporation PowerPlay Early Power Estimator For Stratix Il Stratix Il GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Figure 3 24 shows the Thermal Power Thermal Analysis and Power Supply Sizing areas in the Main section Figure 3 24 Power Areas in Main Section E Visit the Online PowerPlay Early Power Estimator AN B ER A Power Management Stratix II Stratix Il GX HardCopy II a Resource Center v6 1 Comments Thermal Power W Thermal Analysis Family i I Junction Temp T C suis 94 Junction Ambient hermal Analysis Package l 9 Junction Board Information Temperature Grade il Maximum Allowed Ta C Power Characteristics il Details User Entered Tj Auto Computed Tj Ambient Temp T C LE ox C Custom Theta JA Estimated Theta JA h Power Supply Current A Heat Sink 0 323 licct 0 252 Airflow zoolm toms lecro 0 002 Power Supply Custom Os C W ham 0 004 Sizing Information Board Thermal Model Custom 9 COW Click buttons for Board Temp Tp C Thermal Power Information Thermal Power Thermal power is the power dissipated in the device The total thermal power is shown in W and is a sum of the thermal power of all the resources being used in the device The total thermal power includes the maximum power from
17. sensitive to the actual device design and the environmental operating conditions D For more information about available device resources I O standard support and other device features refer to the appropriate device family handbook Featu res The features of the PowerPlay Early Power Estimator spreadsheet include E Estimate your design s power usage before creating the design during the design process or after the design is complete E Import device resource information from the Quartus II software into the PowerPlay Early Power Estimator spreadsheet with the use of the Quartus II generated PowerPlay Early Power Estimator file E Perform preliminary thermal analysis of your design 1 2 Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 JA DTE YA Chapter 2 Setting Up PowerPlay Early Power Estimator System Requirements Download amp Install the PowerPlay Early Power Estimator Estimating Power Altera Corporation January 2007 The PowerPlay Early Power Estimator spreadsheet requires E A PC running the Windows NT 2000 XP operating system W Microsoft Excel 2002 or higher W Quartus II software version 6 1 or higher if generating a file for import The PowerPlay Early Power Estimator spreadsheet for Altera devices is available from the Altera website www altera com After reading the terms and conditions and clicking I Agree you can download t
18. separate design module You must enter the following parameters for each design module Clock frequency fmax in MHz Number of combinational adaptive look up tables ALUTs Number of registers Toggle percentage 3 5 Altera Corporation PowerPlay Early Power Estimator For Stratix Il Stratix Il GX amp HardCopy II January 2007 PowerPlay Early Power Estimator Inputs Table 3 2 describes the values that need to be entered in the Logic section of the PowerPlay Early Power Estimator Table 3 2 Logic Section Information Part 1 of 2 Column Heading Module Description Enter a name for each module of the design Clock Freq MHz Enter a clock frequency in MHz This value must be in the range of 0 to 550 MHz 100 MHz with a 12 5 toggle means that each LUT or flip flop output toggles 12 5 million times per second 100 x 12 5 Combinational ALUTs Enter the number of combinational ALUTs For Stratix Il and Stratix Il GX this is the sum of combinational with no register combinational with register and unavailable ALUTs from the Quartus II Compilation Report Resource Usage Summary section For the number of Adaptive LUTs used add the values from the following rows in the Fitter Resource Usage Summary 7 input functions 6 input functions 5 input functions 4 input functions 3 input functions Combinational cells for routing Each Stratix Il and Stratix II GX A
19. supply current due to the I O pins in each I O bank This may be higher than the thermal power due to current supplied to off chip termination resistors Unassigned This represents the lccio of all UO modules not assigned to an I O bank Figure 3 11 shows how the V cjo level is listed for each I O bank The PowerPlay Early Power Estimator spreadsheet shows the Iccio listed for each bank Select the Veco voltage in the Vccjo column Figure 3 11 Vecio Listed for Each 1 0 Bank Vecio lccio A VO Bank1 VO Bank 2 VO Bank3 ps x ps x VO Bank 4 VO Bank5 VO Bank 6 VO Bank 7 VO Bank 8 VO Bank 9 VO Bank 10 N A Unassigned Table 3 6 describes the I O module parameters in the I O section of the PowerPlay Early Power Estimator Table 3 6 1 O Module Information in the 1 0 Section Part 1 of 3 Column Heading Description Module Enter a name for the module in this column This is an optional value I O Standard Select the I O standard used for the input output or bidirectional pins in this module from the list The calculated I O power varies based on the I O standard Drive Strength On chip Select the drive strength or on chip termination implemented for the I O pin s in this Termination module Drive strength and on chip termination are mutually exclusive 3 20 Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II Januar
20. 003 0000 0 060 24 LVTTLILYCMOS 1 8 PASS 0 000 0 000 0 000 0 000 0 000 0 000 25 LVTTL 3 3 y PASS 0 000 0 000 0 001 0 000 0 000 0 000 26 LVTTL 3 3 y PASS 0 000 0 001 0 002 0 001 0 000 0 000 2 LVTTL 3 3 y PASS 0 000 0 000 0 000 0 000 0 000 0 000 LVTTL 3 3 y 0 000 0 000 0 000 0 000 0 000 0 000 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II High Speed Differential Interface HSDI Stratix II Stratix II GX and HardCopy II devices feature dedicated circuitry that interface with high speed differential I O standards These are dedicated transmitters and receivers that contain serializer and deserializer blocks respectively The HSDI section in the PowerPlay Early Power Estimator spreadsheet is divided into to receiver and transmitter parts Altera Corporation January 2007 Using the PowerPlay Early Power Estimator EB The power calculated in the HSDI section only applies to the transmitter serializer block or the receiver deserializer block The transmitter and receiver are implemented using the altlvds megafunction The I O buffer power is calculated in the I O section and the PLL power is calculated in the PLL section Each row in the HSDI section represents a separate receiver or transmitter domain You must enter the following parameters for transmitter and receiver domain
21. 10096 5096 0 000 0 0 D 10096 50 0 000 0 0 0 100 50 0 000 0 0 0 100 50 0 000 0 0 0 100 50 0 000 0 0 D 100 50 0 000 0 0 0 100 50 0 000 0 0 D 100 50 0 000 0 0 10096 50 0 000 0 0 D 100 50 0 000 Transceiver XCVR Stratix II GX devices feature dedicated embedded circuitry on the right side of the device that contain up to 20 high speed 6 375 Gbps serial transceiver channels Stratix II GX devices have dedicated transmitters and receivers that contain serializer and deserializer blocks respectively This section therefore is only applicable for designs targeting Stratix II GX devices Importing a file from the Quartus II software does not populate the Vccpsetting field You must enter this information manually The power calculated in this section applies to the transceiver blocks including the channels used and all circuitry used in the Clock Control Unit CCU The transceivers are implemented using the ALT2GXB megafunction The I O buffer power and the PLL power for the transceivers are included in this section Transmitters and receivers assume 100 Otermination 3 33 PowerPlay Early Power Estimator For Stratix Il Stratix Il GX amp HardCopy II PowerPlay Early Power Estimator Inputs There are six transceiver power rails Vecy Vecu Vecr Veca Vccp and Voc Table 3 10 describes the information reported for each rail Table 3 10 Transceiver Power Supply Informatio
22. 12mA x 1050 0 1 0 ji Ml 200 0 100 0 O SOR LZ PASS PASS 0 000 0001 0002 0 001 0 000 0 000 27 WL 3 34 24m v 00 2 0 e v 00 1000 0 lape PASS PASS 0000 0 000 0 000 0000 0 000 0000 LVTTL 3 34 24m v 00 D 0 il 12 5 100096 O soR w 0000 0 000 0000 0000 0000 0000 The PowerPlay Early Power Estimator spreadsheet verifies whether or not the I O standard selected is available in the selected I O bank If there is a discrepancy it is displayed in the Bank I O Std Check column as shown in Figure 3 13 Figure 3 13 1 O Standard Verification PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS Altera Corporation 3 23 January 2007 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II PowerPlay Early Power Estimator Inputs 3 24 The PowerPlay Early Power Estimator spreadsheet also verifies that the Vccio levels match the I O standards for each I O bank If there is a discrepancy it is displayed in the Bank Voltage Check column as shown in Figure 3 14 Figure 3 14 PowerPlay Early Power Estimator Spreadsheet Checks for Vecio Inconsistencies Bank Voltage Check PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS cS Importing the Quartus II estimation file automatically populates the Vccio voltages However certain designs may have discrepancies This occurs most often if I O standards that are li
23. Estimator spreadsheet are referred to as sections Sections in the PowerPlay Early Power Estimator spreadsheet calculate power representing architectural features of the device such as clocks RAM blocks or DSP blocks Main Input Parameters Different devices consume different amounts of power for the same design The larger the device the more power it consumes because of the larger die and longer interconnects in the device In the Main section you may enter the following parameters for the device and design Family Device Package Temperature grade Power characteristics Ambient or junction temperature Airflow Heat sink used Custom heat sink information Board thermal model Custom board thermal model information Board temperature gt Parameters required depend on whether junction temperature is entered manually or auto computed 3 1 PowerPlay Early Power Estimator Inputs Table 3 1 describes the values that need to be specified in the Main section of the PowerPlay Early Power Estimator Table 3 1 Main Section Information Part 1 of 3 Input Parameter Description Family Select the device family The families supported are Stratix Il Stratix II GX and HardCopy II Device Select your device Larger devices consume more static power and have higher clock dynamic power All other power components are unaffected by device Package Select the package that is used Larger packages provid
24. II GX amp HardCopy II Power Analysis 3 46 Toggle rate for Decoder module Toggle rate for RAM Toggle rate for Filter Toggle rate for Modulator Toggle rate for Encoder These estimates can be done in many ways If similar modules were used in the past with data inputs of roughly the same toggle rate that information can be leveraged If there are MATLAB simulations available for some blocks toggle rate information can be obtained If the HDL is available for some of the modules they can be simulated If the HDL is complete the best way to determine toggle rate is to simulate the design The accuracy of toggle rate estimates depends heavily on the accuracy of the input vectors Therefore determining whether or not the simulation coverage is high gives you a good estimate of how accurate the toggle rate information is The Quartus II software can determine toggle rates of each resource used in the design if information from simulation tools is provided Designs can be simulated in many different tools and information provided for the Quartus II software through a Signal Activity File SAF The Quartus II PowerPlay Power Analyzer provides the most accurate power estimate The CSV output file from Quartus II can be used with the PowerPlay Early Power Estimator spreadsheet for estimating power after the design Airflow The PowerPlay Early Power Estimator spreadsheet allows the designer to specify the airflow present at the devic
25. Inputs Each row in the DSP section represents a DSP design module where all instances of the module have the same configuration clock frequency toggle percentage and register usage If some or all DSP or multiplier instances have different configurations you need to enter the information in different rows You must enter the following information for each DSP or multiplier module Configuration Clock frequency fmax in MHz Number of instances Toggle percentage of the data outputs Whether or not the inputs and outputs are registered Whether or not the module is pipelined For more information on Stratix II DSP block configurations refer to the DSP Blocks in Stratix II Devices chapter in volume 2 of the Stratix II Device Handbook For more information on Stratix II GX and HardCopy II DSP block configurations refer to the DSP section in the respective device handbook Table 3 4 describes the values that need to be entered in the DSP section of the PowerPlay Early Power Estimator Table 3 4 DSP amp Multiplier Section Information Part 1 of 2 Column Heading Module Description Enter a name for the DSP module in this column This is an optional value Configuration Clock Freq Select the DSP block configuration The following configurations are offered 9 x 9 simple multiplier 18 x 18 simple multiplier 36 x 36 simple multiplier 18 x 18 multiplier accumulator 9 x 9 two multiplier adder 18 x 18 two m
26. LVDS PLLs used as part of a SERDES VCO Freq Enter the frequency of the voltage controlled oscillator in MHz The VCO frequency is reported in the Nominal VCO frequency row of the Quartus II Compilation Report In the Compilation Report select Fitter and click Resource Section Select PLL Summary and click Nominal VCO frequency Total Power This shows the estimated power in W based on the maximum output frequency and the VCO frequency you entered This value is calculated automatically User Comments Enter any comments This is an optional entry Altera Corporation January 2007 3 29 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II PowerPlay Early Power Estimator Inputs Figure 3 18 shows the PLL Usage section in the Quartus II software Compilation Report for a design The Compilation Report provides the maximum frequency a PLL outputs Figure 3 18 PLL Usage in Compilation Report LPLL instSialtpltalpil component cikO clock 4 LPLL instSlaltpl altpll componenti clkt clock i5 plit inst2laltplkaltpll componentl clk clock 8 plht inst2laltplkaltpll componenti K clock1 EA ROMPLL inst laltplkaltpll component cIkO clockO 8 ROMPLL inst7laltplt altpll_component clk1 clock 3 myLVDSTX inst6laltlvds_ts altlvds_tx_componentllyds_tx_7sO1 auto_generatedipll clock0 10 myLVDSTx inst6laltlvds_tx altlvds_tx_componentllvds_tx_7s 1 auto_generatediplI ENAOUTO enabl
27. O sheet for details on the current drawn from each I O rail lccio includes any current drawn through the I O into off chip termination resistors This can result in Ic lO values that are higher than the reported I O thermal power since this off chip current is dissipated as heat elsewhere and does not factor into the calculation of device temperature locxcvr This shows the total current drawn from the lccxcyg rail s See the XCVR sheet for details on the current drawn from each XCVR rail 3 44 Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Factors Affecting PowerPlay Early Power Estimator Spreadsheet Accuracy There are many factors that greatly affect the estimated values displayed in the PowerPlay Early Power Estimator In particular it is imperative to determine whether or not the input parameters entered are accurate to ensure that the system is modeled correctly in the PowerPlay Early Power Estimator spreadsheet In particular information entered concerning toggle rates airflow temperature and heat sinks are extremely important Toggle Rate The toggle rates specified in the PowerPlay Early Power Estimator spreadsheet can have a very large impact on the dynamic power consumption displayed In order to obtain an accurate estimate it is imperative to input toggle rates that are realistic Determining realistic toggle
28. Play Early Power Estimator file directly from a HardCopy II design Instead generate the PowerPlay Early Power Estimator file for the Stratix II companion revision for the project The PowerPlay Early Power Estimator spreadsheet generates both Stratix II and HardCopy II power estimates from the Stratix II PowerPlay Early Power Estimator file For more information on generating the PowerPlay Early Power Estimator file in the Quartus II software refer to the PowerPlay Power Analysis chapter in the Quartus II Handbook To import data into the PowerPlay Early Power Estimator perform the following steps 1 Click Import Quartus II File in the PowerPlay Early Power Estimator 2 Browse to a power estimation file generated from the Quartus II software and click Open The file has a name revision name early pwr csv 3 Click OK in the confirmation window to proceed 4 When the file is imported click OK Clicking OK acknowledges the import is complete If there are any errors during the import an err file is generated with details Le After importing a file you must verify all your information Importing a file from the Quartus II software populates all input parameters on the main page that were specified in the Quartus II software These parameters include Altera Corporation 2 5 January 2007 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II Entering Information into the PowerPlay Early Power
29. PowerPlay Early Power Estimator User Guide For Stratix Il Stratix Il GX amp HardCopy Il ANU S n AA 101 Innovation Drive San Jose CA 95134 408 544 7000 www altera com Document Date Document Version 1 2 January 2007 Copyright 2007 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device des ignations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Al tera products are protected under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the ap plication or use of any information product or service described herein except as expressly agreed to in writing by Altera NSAI Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published in formation and before placing orders for products or services LS EN ISO 9001 UG PWRPLY 1 2 Al
30. air thermal resistance and thus lower junction temperature Custom D C W Enter the junction to ambient thermal resistance between the device and ambient air in C W This field is only available when you select Auto Computed T and Custom Oy This field represents the increase between ambient temperature and junction temperature for every Watt of additional power dissipation Custom 054 C W Enter the heatsink to ambient thermal resistance from the heat sink data sheet if you select a custom heat sink The quoted values depend on system airflow and may also depend on thermal power dissipation This field is only available when you select Auto Computed T Estimated Oya and if you set the Heat Sink parameter to Custom Solution The Custom 8s parameter is combined with a representative case to heatsink resistance and an Altera provided junction to case resistance to compute overall junction to ambient resistance through the top of the device Altera Corporation January 2007 3 3 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II PowerPlay Early Power Estimator Inputs Table 3 1 Main Section Information Part 3 of 3 Input Parameter Board Thermal Model Description Select the type of board to be used in thermal analysis If no heat sink has been selected the Altera provided 0 4 value includes the board thermal pathway If a board thermal model is selected yo
31. al information correctly Ambient temperature refers to the temperature of the air around the device This is almost always much higher than the ambient temperature outside of the system To get an accurate representation of ambient temperature for the device the temperature must be measured as close to the device as possible This can be done with a thermocouple Entering the incorrect ambient air temperature could drastically alter the power estimates in the PowerPlay Early Power Estimator spreadsheet The figure below illustrates a simple system with the FPGA housed in a box In this case the temperature is very different at each of the numbered locations illustrated in Figure 3 37 3 48 Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Altera Corporation January 2007 Figure 3 37 Temperature Variances O 2 4 O gt FPGA 1 1 x Z gt m For example location 3 is where the ambient temperature pertaining to the device should be obtained for input into the PowerPlay Early Power Estimator spreadsheet Points 1 and 2 are cooler than location 3 location 4 is likely close to 25 degrees C Temperatures close to devices in a system are often around 50 60 degrees but the values can vary significantly In order to obtain accurate power estimates from the PowerPlay Early Power Estimator s
32. ate junction temperature calculating junction temperature is an iterative process The total power is calculated based on the device resource usage which provide 0 and the ambient board and junction temperatures using the following equation P T TA Oya 3 40 Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Using a Heat Sink When a heat sink is used the major paths of power dissipation are from the device through the case thermal interface material and heat sink There is also a path of power dissipation through the board The path through the board has much less impact than the path to air Figure 3 28 shows the thermal representation with a heat sink Figure 3 28 Thermal Representation with Heat Sink Heat Sink A Osa T des Case A 0 Thermal Interface Material JC Device Board 0 Y JB Thermal Representation with Heat Sink In the model used in the PowerPlay Early Power Estimator power can be dissipated through the board or through the case and heat sink The thermal resistance of the path through the board is referred to as the junction to board thermal resistance 8 The thermal resistance of the path through the case thermal interface material and heat sink is referred to as the junction to ambient thermal resistance 8 Figure 3 29 sho
33. ated once SDR or twice DDR a cycle If the data rate of the pin is DDR it is possible to set the data rate to SDR and double the toggle percentage The Quartus II software often uses this method to output information Bank I O Std Check This indicates whether the selected I O standard is available on the selected I O bank Not all I O banks can implement every I O standard Bank Voltage Check This indicates whether or not the selected I O bank has a voltage compatible with the selected I O standard Thermal Power W Routing This shows the power dissipation due to estimated routing in W Routing power is highly dependent on placement and routing which is itself a function of design complexity The values shown are representative of routing power based on experimentation on over 100 real world designs Use the Quartus Il PowerPlay Power Analyzer for detailed analysis based on the routing used in your design This value is calculated automatically Thermal Power W Block This shows the power dissipation due to internal and load toggling of the I O in W Use the Quartus I PowerPlay Power Analyzer for accurate analysis based on the exact I O configuration of your design This value is calculated automatically Thermal Power W Total This shows the total power dissipation in W The total power dissipation is the sum of the routing and block power This value is calculated automatically Suppl
34. ation except if the I O bank I O standard I O voltage are compatible Toggle Enter the average percentage of output and bidirectional pins toggling on each clock cycle The toggle percentage ranges from 0 to 200 If the pin uses a double data rate DDR you can set the data rate to single data rate SDR and double the toggle percentage The Quartus II software often uses this method to output information Typically the toggle percentage is 12 5 To be more conservative you can use a higher toggle percentage OE Enter the average percentage of time that e The output I O pins are enabled e Bidirectional I O pins are outputs and enabled During the remaining time e Output I O pins are tristated e Bidirectional I O pins are inputs This number must be a percentage between 0 and 100 Load pF Enter the pin loading external to the chip in pF Only applies to outputs and bidirectional pins Pin and package capacitance is already included in I O model Therefore you only need to include off chip capacitance in the Load parameter Altera Corporation January 2007 3 21 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II PowerPlay Early Power Estimator Inputs Table 3 6 1 O Module Information in the 1 0 Section Part 3 of 3 Column Heading Data Rate Description Select either SDR or DDR as the I O data rate This indicates whether the I O value is upd
35. ations use port A and port B Table 3 3 describes the parameters in the RAM section of the PowerPlay Early Power Estimator Table 3 3 RAM Section Information Part 1 of 3 Column Heading Module Description Enter a name for the RAM module in this column This is an optional value RAM Type Select whether the RAM is implemented as an M512 M4K or M RAM block The RAM type can be found in the Type column of the Quartus Il Compilation Report In the Compilation Report select Fitter and click Resource Section Click RAM Summary RAM Blocks Enter the number of RAM blocks in the module that use the same type and mode and have the same parameters for each port The parameters for each port are clock frequency in MHz the percentage of time the RAM is enabled and the percentage of time the port is writing as opposed to reading The number of RAM blocks reported can be found in the M512s M4Ks and M RAMs rows of the Quartus Il Compilation Report Resource Usage Summary Data Width Enter the width of the data for the RAM block This value is limited based on the RAM type The width of the RAM block can be found in the Port A Width or the Port B Width column of the Quartus Il Compilation Report In the Compilation Report select Fitter and click Resource Section Click RAM Summary For RAM blocks that have different widths for port A and port B use the larger of the two widths This number must be an inte
36. daptive Logic Module ALM contains up to two combinational ALUTs Smaller ALUTs consume less power than larger ALUTs but the device can fit more of them The total number of ALUTs in the design should not exceed number of ALMs x 2 For HardCopy Il the number of ALUTs is estimated based on the number of HCELLs and HCELL Macros used in the design Generally the number of ALUTS of the HardCopy Il should be comparable to the number of ALUTS for the equivalent Stratix II design FFs Enter the number of flip flops in the module For all devices this is the sum of register only and combinational with a register ALUTs from the Quartus Il Compilation Report Resource Usage Summary For HardCopy Il the number of flip flops is determined from the Stratix II fit report Clock routing power is calculated separately on the Clocks sheet 3 6 Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Table 3 2 Logic Section Information Part 2 of 2 Column Heading Toggle Description Enter the average percentage of logic toggling on each clock cycle The toggle percentage ranges from 0 to 100 Typically the toggle percentage is 12 5 which is the toggle percentage of a 16 bit counter To ensure you do not underestimate the toggle percentage you can use a higher toggle percentage Most logic only toggles infreq
37. dsheet you need to reset all user entered values manually Manually Entering Information You can manually enter values into the PowerPlay Early Power Estimator spreadsheet in the appropriate section White unshaded cells are input cells and may be modified Each section contains a column that allows you to specify a module name based on your design Importing a File If you already have an existing design or a partially completed design the power estimation report file generated by the Quartus II software contains the device resource information You can import this device resource information from the Quartus II software PowerPlay Early Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Setting Up PowerPlay Early Power Estimator Power Estimator file into the PowerPlay Early Power Estimator Importing a file saves you time and effort otherwise spent manually entering information into the PowerPlay Early Power Estimator You can also manually change any of the values after importing a file To generate the PowerPlay Early Power Estimator file you must first compile your design in the Quartus II software After compiling the design click Generate PowerPlay Early Power Estimator File on the Project menu The Quartus II software creates a PowerPlay Early Power Estimator file with the name lt revision name early pwr csv The Quartus II software cannot generate a Power
38. dustry I O standards for increased design flexibility The I O section in the PowerPlay Early Power Estimator spreadsheet allows you to estimate the I O pin power consumption based on the pin s I O standards gt The PowerPlay Early Power Estimator spreadsheet assumes you are using external termination resistors when you design with I O standards that recommend termination resistors SSTL and HSTL If your design does not use external termination resistors you should choose the LVTTL I O standard with the same Vccio and similar drive strength as the terminated I O standard For example if you are using the SSTL 2 class II I O standard without termination resistors using a point to point connection you should select LVTTL LVCMOS 2 5 V as your I O standard and 16mA as the Drive Strength in the PowerPlay Early Power Estimator The power reported for I O signals includes thermal and external I O power The total thermal power is the sum of the thermal power consumed by the device based on each power rail thermal power thermal Pnr thermal Ppp thermal Pio 3 18 Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Figure 3 10 shows a graphical representation of the I O power consumption The Iccio rail power includes both the thermal Pro and the external Pro Figure 3 10 I O Power Representation VCCINT VccPD Vccio
39. e This value affects thermal analysis and bears directly on the power consumed by the device To obtain an accurate estimate it is imperative to correctly determine the airflow at the FPGA not the output of the fan providing the airflow Often it is difficult to place the device adjacent to the fan providing the airflow As such the path of the airflow is likely to traverse a length on the board before reaching the device thus diminishing the actual airflow the device sees In the example shown in Figure 3 33 a fan is placed at the end of the board The airflow at the FPGA is weaker than what it is at the fan Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Figure 3 33 Airflow amp FPGA Position z n FPGA In many cases it is also necessary to take into consideration blocked airflow In the example below there is a device blocking the airflow from the FPGA significantly reducing the airflow seen at the FPGA Also the airflow from the fan often cools board components and other devices before reaching the FPGA Figure 3 34 Figure 3 34 Airflow with Component amp FPGA Positions EE d gt Device FPGA If a custom heat sink is being used there is no need to enter the airflow directly into the PowerPlay Early Power Estimator sp
40. e a larger cooling surface and more contact points to the circuit board leading to lower thermal resistance Package selection does not affect dynamic power Temperature Grade Commercial devices have a maximum operating temperature of 85 C Industrial devices offer 100 C operation Military devices offer 125 C operation This field only affects maximum junction temperature Currently only Stratix II supports the military temperature range Power Characteristics Select typical or theoretical worst case silicon process There is process variation from die to die This primarily impacts the static power consumption Maximum is used for thermal design while Typical provides results that line up with average device measurements Currently only Typical power characteristics are available for the HardCopy II family Junction Temp Ty C Enter the junction temperature of the device This value can range from 55 C to 125 C This field is only available when User Entered T is selected In this case junction temperature is not calculated based on the thermal information provided Ambient Temp Ta C Enter the air temperature near the device This value can range from 55 C to 125 C This field is only available when Auto Computed T is selected If Estimated 0j is selected this field is used to compute junction temperature based on power dissipation and thermal resistances through the top s
41. eD 1 plit insti laltplt altpll_componentLclk1 myLVDSTXinst6laltivds_twaltlvds_tx_componentilvds_tx_7s01 auto_generatediplISCLKOUTO scikout0 8 12 myLVDSRPiXinstSlaltivds rxaltlvds r componentllvds r bkv auto generatedipll 13 myLVDSRXinstSlaltlvds r altivds rx componentllvds r bkv auto generatedipllENADUTO enableO 1 myL VDSRXinstSlalllvds re altivds r componentllvds rx bkv auto generatedipli SCLKOUTO sclkout0 8 clock 1 3 1 1 1 3 5 1 1 1 pre para ery berg Ie mei 150 0 MHz 75 0 MHz 75 0 MHz 100 0 MHz 150 0 MHz 125 01 MHz 175 01 MHz 105 01 MHz 105 01 MHz 840 08 MHz 105 01 MHz 105 01 MHz 840 08 MHz Figure 3 19 shows the PLL Summary in the Quartus II software Compilation Report for a design targeting a Stratix II device The Compilation Report provides the VCO frequency of a PLL Figure 3 19 PLL Summary in Compilation Report Name kde ncaltivd LR PLL mode Feedback source Compensate clock Switchover type Switchover counter Gate lock counter Input frequency O Input frequency 1 Nominal PFD frequency Nominal VCO frequency VCO post scale VCO multiply VCO divide Freq min lock Freq max lock MVCO Tap M Initial M value N value M2 value N2 value 55 counter Downspread Spread frequency Charge pump current Loop fiter resistance Loop fiter capacitance Bandwidth Realtime reconfigurable Scan chain MIF file Isl Ier 21
42. es and disadvantages when using the PowerPlay Early Power Estimator spreadsheet for an FPGA design that is partially complete Table 2 2 Power Estimation When FPGA Design Is Partially Complete Advantages Disadvantages e Power estimation can be done early e Accuracy depends on your inputs in the FPGA design cycle and your estimation of the device e Provides the flexibility to resources where this information automatically fill in the PowerPlay may change during or after your Early Power Estimator spreadsheet design is complete your power based on Quartus Il software estimation results may be less compilation results accurate Use the following steps to estimate power usage with the PowerPlay Early Power Estimator spreadsheet if your FPGA design is partially complete 1 Compile the partial FPGA design in the Quartus II software 2 Generate the PowerPlay Early Power Estimator file lt revision name gt early pwr csv in the Quartus II software by clicking Generate PowerPlay Early Power Estimator File on the Project menu 3 Download the PowerPlay Early Power Estimator spreadsheet from the Altera website www altera com 4 Import the PowerPlay Early Power Estimator file into the PowerPlay Early Power Estimator spreadsheet to automatically populate the PowerPlay Early Power Estimator spreadsheet entries 2 3 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II Entering Informati
43. esigns Use the Quartus Il PowerPlay Power Analyzer for accurate analysis based on the exact synthesis of your design Total This shows the total power dissipation in W The total power dissipation is the sum of the routing and block power User Comments Enter any comments This is an optional entry Altera Corporation January 2007 3 7 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II PowerPlay Early Power Estimator Inputs Figure 3 2 shows a TFF example Figure 3 2 TFF Example Voc TFF PRN RR ieee NE ERE Q C gt tff output d ue INPUT X CNE aaa neta NE er Yoo CLRN Figure 3 3 shows a 4 Bit Counter example Figure 3 3 4 Bit Counter Example i i i i cout3 x couti i cout i d j gt i couto OUTPUT gt coutd pr EE EE EE i GOU OUTPUT gt GOUD i i cout2 OUTPUT gt cout2 i i cout3 OUTPUT cout3 i 3 8 Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Figure 3 4 shows the Resource Usage Summary in the Quartus II software Compilation Report for a design targeting the Stratix II device family The Compilation Report provides the total number of ALUTs and registers used by the design Figure 3
44. et models only the impact on clock tree power This column is not applicable for HardCopy II devices Total Power W This is the total power dissipation due to clock distribution in W This value is calculated automatically User Comments Enter any comments This is an optional entry Figure 3 21 shows the Global amp Other Fast Signals report from the Quartus II software Compilation Report for an example design The report shows the fanout for each signal that uses a global clock The Timing Analysis section of the Compilation Report lists the clock signal frequencies Enter the appropriate information from the Compilation Report into the PowerPlay Early Power Estimator Figure 3 21 Global amp Other Fast Signals Resource Section in Compilation Report Global amp Other Fast Signals Fan Out Global Resource Global Line Enable Signal Name ource Name T E lobal cloc 3 ROMPLL inst7lalipltallpll component clkO 10 Global clock GCLK11 4 ROMPLL inst laltpll akel component clk1 1 Global clock GCLK10 5 myLVDSRXinstSlaltlvds ncallivds rx componentlivds r bkv auto generatedipll 152 Global clock BCLK1 VCC 8 myLVDSRX instSlaltlvds_rx altlvds_rx_componentllvds_rx_bkv auto_generated pll ENAOUTO 18 DIFFIOCLK LZ myLVDSRX inst9 altlvds_rx altlvds_rx_componentlivds_x_bkv auto_generatedipli SCLKOUTO 18 DIFFIOCLK 8 myLVDSTX inst6lalthvds_tx altlvds_tx_c
45. ger The valid range for each RAM type is 8 for M512 e 1 1 e 1 36 1 18 for True Dual Port for M4K e 1 144 1 72 for True Dual Port for MRAM Altera Corporation January 2007 3 11 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II PowerPlay Early Power Estimator Inputs Table 3 3 RAM Section Information Part 2 of 3 Column Heading RAM Mode Description Select from the following modes e Single Port e Simple Dual Port e True Dual Port e ROM The mode is based on how the Quartus Il Compiler implements the RAM If you are unsure how your memory module is implemented Altera recommends compiling a test case in the required configuration in the Quartus II software The RAM mode can be found in the Mode column of the Quartus Il Compilation Report In the Compilation Report select Fitter and click Resource Section Click RAM Summary A single port RAM has one port with a R W control signal A simple dual port RAM has one read port and one write port A true dual port RAM has two ports each with a R W control signal ROMs are read only single port RAMs Port A Clock Freq Enter the clock frequency for port A of the RAM block s in MHz This value is limited by the maximum frequency specification for the RAM type and device family Port A Enable 96 Enter the average percentage of time the input clock enable for port A is active regardless of activity on RAM da
46. he Microsoft Excel file to your hard drive s By default the Microsoft Excel 2002 macro security level is set to High When the macro security level is set to High macros are automatically disabled To change the macro security level in Microsoft Excel 2002 click Options on the Tools menu On the Security tab of the Options window click Macro Security On the Security Level tab of the Security dialog box chose Medium When the macro security level is set to Medium a pop up window asks you whether to enable macros or disable macros each time you open a spreadsheet that contains macros After changing the macro security level you have to close the spreadsheet and re open it in order to use the macros You can estimate power at any point in your design cycle You can use the PowerPlay Early Power Estimator spreadsheet to estimate the power consumption if you have not begun your design or if your design is not complete While the PowerPlay Early Power Estimator spreadsheet can provide you with an estimate for your complete design it is highly recommended to use the PowerPlay Power Analyzer in the Quartus II software to obtain this estimate In general using the PowerPlay Power Analyzer in the Quartus II software should be your preferred method of generating power estimates due to the fact that it knows your exact routing and various modes of operation For more information on the power estimation feature in Quartus II software refer to t
47. he PowerPlay Power Analysis chapter in the Quartus II Handbook 2 1 Estimating Power To use the PowerPlay Early Power Estimator enter the device resources operating frequency toggle rates and other parameters in the PowerPlay Early Power Estimator If you do not have an existing design then you need to estimate the number of device resources your design uses in order to enter the information into the PowerPlay Early Power Estimator Estimating Power Before Starting the FPGA Design FPGAs provide the convenience of a shorter design cycle and faster time to market than ASICs or ASSPs This means that the board design often takes places during the FPGA design cycle and the power planning for the device can happen before any of the FPGA design is complete Table 2 1 shows the advantages and disadvantages of using the PowerPlay Early Power Estimator spreadsheet before you begin the FPGA design Table 2 1 Power Estimation Before Designing FPGA Advantages Disadvantages e Power estimation can be e Accuracy depends on your inputs and performed before starting your your estimation of the device resources FPGA design where this information may change during or after your design is complete your power estimation results may be less accurate e Process can be time consuming To estimate power usage with the PowerPlay Early Power Estimator spreadsheet if you have not started your FPGA design perform the follow
48. ide cooling solution heat sink or none and board if applicable If Custom 0 is selected this field is used to compute junction temperature based on power dissipation and the custom 6 entered 3 2 Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Table 3 1 Main Section Information Part 2 of 3 Input Parameter Heat Sink Description Select the heat sink being used You can specify no heat sink a custom solution or specify a heat sink with set parameters This field is only available when you select Auto Compute T and Estimated Oja Representative examples of heat sinks are provided larger heat sinks provide lower thermal resistance and thus lower junction temperature If the heat sink is known consult the datasheet and enter a Custom heatsink to ambient value according to the airflow in your system The heat sink selection updates 054 and the value is seen in the Custom 054 C W parameter If a custom solution is selected the value is what is entered for Custom sa C W Airflow Select an available ambient airflow in linear feet per minute lfm or meters per second m s The options are 100 Ifm 0 5 m s 200 Ifm 1 0 m s 400 Ifm 2 0 m s or still air This field is only available when you select Auto Computed T and Estimated Dr Increased airflow results in a lower case to
49. imator Table 3 9 Clock Section Information Part 1 of 2 Column Heading Domain Enter a name for the clock network in this column This is an optional value Description Clock Freq MHz Enter the frequency of the clock domain The value must be between 0 and 550 Mhz Altera Corporation January 2007 3 31 PowerPlay Early Power Estimator For Stratix Il Stratix II GX amp HardCopy II PowerPlay Early Power Estimator Inputs Table 3 9 Clock Section Information Part 2 of 2 Column Heading Total Fanout Description Enter the total number of flip flops and RAM DSP and I O blocks fed by this clock The number of resources driven by every global clock and regional clock signal is reported in the Fan out column of the Quartus Il Compilation Report In the Compilation Report select Fitter and click Resource Section Select Global amp Other Fast Signals and click Fan out Global Enable Enter the average of time that the entire clock tree is enabled Each global clock buffer has an enable signal that can be used to dynamically shut down the entire clock tree Local Enable Enter the average of time that clock enable is high for destination flip flops Local clock enables for flip flops in ALMs are promoted to LAB wide signals When a given flip flop is disabled the LAB wide clock is also disabled cutting clock power in addition to power for down stream logic This she
50. ing steps 1 Download the PowerPlay Early Power Estimator spreadsheet from the Altera website www altera com 2 Select the target family device and package from the PowerPlay Early Power Estimator s Family Device and Package sections 3 Enter values for each section in the PowerPlay Early Power Estimator Different worksheets in the file display different power sections such as clocks and PLLs Power is calculated automatically and subtotals are given for each section 4 The calculator displays the estimated power usage in the Total section 2 2 Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Setting Up PowerPlay Early Power Estimator Altera Corporation January 2007 Estimating Power While Creating the FPGA Design When the FPGA design is partially complete you can use the PowerPlay Early Power Estimator file lt revision name gt _early_pwr csv generated by the Quartus II software to supply information to the PowerPlay early power estimator After importing the power estimation file information into the PowerPlay early power estimator you can edit the PowerPlay Early Power Estimator spreadsheet to reflect the device resource estimates for the final design For more information on generating the power estimation file in the Quartus II software refer to the PowerPlay Power Analysis chapter in the Quartus II Handbook Table 2 2 shows the advantag
51. ipated in terminated I O standards on chip and stand by power dissipated in I O banks Click I O to see details HSDI This shows the dynamic power consumed by SERDES hardware for high speed differential I O Click HSDI to see details PLL This shows the dynamic power consumed by PLLs Click PLL to see details Clocks This shows the dynamic power consumed by clock networks Click Clocks to see details XCVR This shows the thermal power consumed by transceiver hardware This includes the standby power consumed by unused transceivers Click XCVR to see details If value equals N A then the transceivers are not available for the chosen device 3 38 Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Table 3 12 Thermal Power Section Information Column Heading Pstatic Description This shows the static power consumed irrespective of clock frequency Does not include static I O current due to termination resistors which is included in the I O power above Pstatic iS affected by junction temperature selected device and power characteristics TOTAL This shows the total power dissipated as heat from the FPGA Does not include power dissipated in off chip termination resistors See Power Supply Current for current draw from the FPGA supply rails This may differ due to currents supplied to off chip components and thus not
52. mated power consumed by HSDI blocks for this design Figure 3 17 HSDI Section in the PowerPlay Early Power Estimator HSDI Retum to Vbin OCMC 0 069 This section only estimates power within the Serializer Deserializer blocks and does not include the 1 0 power nor PLL power Please enter the appropriate parameters in the IO section for 1 0 power and PLL section for PLL power Total TX Module Date Reta mot Toggle Power User Comments Mbps Channels w 1 840 336126 18 100 0 0 035 D 0 100 0 0 000 D 100 0 0 000 D D 100 0 0 000 Total RX Module Dai aale pet Toggle Power User Comments Mbps Channels w 1 840 336126 18 100 0 0 035 0 0 100 0 0 000 0 0 100 0 0 000 0 D 100 0 0 000 Phase Locked Loops PLLs Stratix II Stratix II GX and HardCopy II devices feature enhanced and fast PLLs for general usage If you are using dedicated transmitters or receivers and are using an LVDS PLL to implement serialization or deserialization specify an LVDS PLL and enter power information in the PLL section 2 When fast PLL drives LVDS hardware it is referred to as an LVDS PLL LVDS PLLs drive LVDS clock trees and DPA buses at the VCO frequency 0 to 1040 MHz If an LVDS PLL drives LVDS hardware only enter the appropriate VCO frequency and specify an output frequency of 0 MHz If the LVDS PLL also drives a clock to a pin or to the core specify that clock f
53. mated power consumed by XCVR blocks for an example design Figure 3 23 XCVR Section in the Early Power Estimator Total Thermal Power W 1 661 Average Power per Used Channel W Channel XCVR Channel Utilization 100 0 Equalizer setting and the Calibration Block have negligible effect on power and are therefore not shown on the early power estimator Each channel is assumed to implement a full transceiver Pre emphasis will be fully enabled at a later release pending characterization Transmitters and receivers are assuming a termination resistance of 1000 Power of transceiver I O pins is included in this estimate do not add extra entries to the LO page for XCVR pins Power Rails Voltage V Current A 12 0 178 1 2 E 0 033 1 2 0 348 Ed 0 073 1 2 0 624 Pre Emphasis E pua ccu Total Module Instances Mode Data Rate Mbps ening Voo mV Caney fon Power W Power W z 2590 None ol PCI E X4 DW ojoj Jn lu k c Power Ana lysis The Main section of the PowerPlay Early Power Estimator spreadsheet summarizes the power and current estimates for the design The Main section displays the total thermal power thermal analysis and power supply sizing information The accuracy of the information depends on the information entered The power consumed can also vary greatly depending on the toggle rates entered The following
54. mator etum DO CIENTE TS 0 151 SUED eee 100 095 DECIR Meme 100 096 This section only estimates power from the PLL control blocks and does not include the power from the PLL cloc networks Please enter additional parameters in the Clocks section vco Freq Total Power User Comment PLL DPA Module PLL Type EE Er 1 Fast 2 Lys 874 9 0 088 3 Fast 840 3 0 029 4 Enhanced 599 9 0 022 Fast 0 0 0 000 Fast 0 0 0 000 Fast 0 0 0 000 Fast 0 0 0 000 Fast 0 0 0 000 Fast 0 0 0 000 Fast 0 0 0 000 Fast 0 0 0 000 Clocks Stratix II Stratix II GX and HardCopy II devices have a total of 48 clock domains available that can be on either a global or regional clock network There are 16 global clocks and 8 regional clocks per quadrant for a total of 32 regional clocks For HardCopy II devices there is no distinction between global and regional clocks The PowerPlay Early Power Estimator spreadsheet does not distinguish between global and regional clocks because the difference in power is not significant Each row in the Clocks section represents a clock network or a separate clock domain You must enter the clock frequency fmax in MHz the total fanout for each clock network used the global clock enable percentage and the local clock enable percentage Table 3 9 describes the parameters in the Clock section of the PowerPlay Early Power Est
55. n in the 1 0 Section Column Heading Description Power Rails Power supply rails for the transceiver blocks Voltage V The voltage applied to the specified power rail in Volts V Current A The current drawn from the specified power rail in Amps A This includes power drawn by transceivers in user modes and unused transceivers in power down mode Each row in the XCVR section represents a separate transceiver domain For each transceiver domain used you need to enter the number of channels the mode of the transceiver the data rate in Mbps the width of the parallel data bus the Pre Emphasis setting and the VOD setting For certain modes you must specify whether the byte serializer rate match FIFO setting and 8B10B encoder are used Table 3 11 describes the values that need to be entered in the XCVR section of the PowerPlay Early Power Estimator Table 3 11 XCVR Section Information Part 1 of 2 Column Heading Description Module Enter a name for the module in this column This is an optional value 3t of Channels Used Enter the number of channels used in this transceiver domain The channels are grouped together in one QUAD or two adjacent QUADs and clocked by a common PLL The number of channels allowed in each domain depends on mode PCI Express One to three channels for PIPEx1 four channels for PIPEx4 or eight channels for PIPEx8 XAUI Four channels only Other modes One to four cha
56. nnels Mode Enter the communication protocol or standard these transceivers implement Options include Basic 3G Basic 6G OIF CEI PHY Interface GIGE PCI Express PIPE Scrambled 5G SONET Backplane OC12 SONET Backplane OC48 SONET Backplane OC96 and XAUI Data Rate Mbps Enter the data rate the transceivers will operate at in Mbps In Basic mode this number must be specified e Basic 3G is 622 to 3125 Mbps e Basic 6G is 3126 to 6375 Mbps For other modes the data rate is fixed 3 34 Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Table 3 11 XCVR Section Information Part 2 of 2 Column Heading Parallel Data Width Description Enter the width of the parallel data bus of each channel The allowed range depends on the mode data rate byte serializer setting and 8B10B setting Byte Serializer Used Enter whether or not the byte serializer deserializer is used If the byte serializer is used the transceiver is in double width mode If it is not used the transceiver is in single width mode Rate Match FIFO Used Enter whether or not the rate matching FIFO is used 8B10B Encoder Used Enter whether or not the 8B10B encoder decoder is used Pre Emphasis Setting Pre Tap Enter the pre emphasis pre tap setting used by the transmitter This value cannot currently be impo
57. nput functions 6 input functions 5 input functions 4 input functions lt 3 input functions Register only Combinational cells for routing ALUTs without a partner unpartnered 7 input functions unpartnered B input functions unpartnered 5 input functions unpartnered 4 input functions unpartnered lt 3 input functions Unpartnered registers only ALUTs by mode normal mode extended LUT mode arithmetic mode shared arithmetic mode Total registers Total ALMs Total LABs User inserted logic elements Virtual pins 1 0 pins Clock pins Global signals M512s M4Ks M RAMs Total memory bits Total RAM block bits DSP block S bit elements Global clocks Regional clocks SERDES transmitters SERDES receivers Maximum fan out node Maximum fan out Total fan out Average fan out Combinational with no register Combinational with a register 1456 0 0 0 30 30 100 559 2 305 24 80 4444 1 523 3484 15 264 1 510 17 1 510 29 982 5 6112 13552 45 881 1 694 52 0 o 226 501 45 11 16 68 14 8 202 3 9 144 6 1 1 100 90 400 1 389 728 6 635 904 1 369 728 46 35 128 28 10 16 62 0 32 0 18 58 31 X 18 62 29 LPLL instlaltpllaltpll comp 1005 48004 385 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II Altera Corporation January 2007 Using the PowerPlay Early Power Estimator
58. omponentllvds_tx_7s 1 auto_generatedipll m 152 Global clock GCLKO VEC 3 myLVDSTX inst6laltlvds_tx altlvds_tx_componentlivds_tx_7s01 auto_generatedipl ENAOUTO PLL 2 18 DIFFIOCLK 2 10 myLVDSTX inst6laltlvds_ts altlvds_tx_componentilyds_tx_7s01 auto_generatedipllSCLKOUTO PLL 2 18 DIFFIOCLK K LU pift insttlaltpltaltpll componentLelkO PLL 6 123 Global clock GCLK5 12 pllt inst1 laltpll altpl_componentLclk1 PLLE 87 Global clock GCLK4 13 pilt inst2laltplaltpl_componentLclkO ALES 32 Global clock GCLK13 14 pll inst2laltplkaltpll componenti clkt PLS 10 Global clock GCLK12 3 32 Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Altera Corporation January 2007 Figure 3 22 shows the PowerPlay Early Power Estimator spreadsheet and the estimated power consumed by clocks for this design Figure 3 22 Clocks Section in the PowerPlay Early Power Estimator leifele C NE Retumtolvbin 1 DEDE 0 110 Clock Total Global Local Total Domain Freq Fanon Enable Enable Power User Comments MHz w 1 124 9 10 100 50 0 010 2 74 8 2 100 50 0 006 3 150 0 87 100 50 0 014 4 150 0 10 100 50 0 013 5 100 0 123 100 50 0 010 6 751 1005 100 50 0 014 7 100 0 32 100 50 0 009 8 104 9 152 100 50 0 010 9 175 0 1 100 50 0 014 10 104 9 152 100 50 0 010 0 0
59. on into the PowerPlay Early Power Estimator Entering Information into the PowerPlay Early Power Estimator 2 4 5 After importing the file to populate the PowerPlay early power estimator you can manually edit the cells to reflect final device resource estimates Estimating Power After Completing the FPGA Design When you complete your FPGA design the PowerPlay Power Analyzer in the Quartus II software provides the most accurate estimate of device power consumption The PowerPlay Power Analyzer uses simulation user mode and default toggle rate assignments in addition to place and route information to determine power consumption Altera strongly recommends that you use the PowerPlay Power Analyzer when your FPGA design is complete For more information about how to use the PowerPlay Power Analyzer in the Quartus II software refer to the PowerPlay Power Analysis chapter in the Quartus II Handbook You can either manually enter power information into the PowerPlay Early Power Estimator spreadsheet or load a PowerPlay Early Power Estimator file generated by the Quartus II software version 6 1 You can also clear all the values currently in the PowerPlay Early Power Estimator Clearing All Values All user entered values can be reset in the PowerPlay Early Power Estimator spreadsheet by clicking Reset c In order to use the Reset feature you must enable macros for the spreadsheet If you have not enabled macros for the sprea
60. orporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Table 3 3 RAM Section Information Part 3 of 3 Column Heading Port B R W 96 Description For RAM blocks in true dual port mode enter the average percentage of time port B of the RAM block is in write mode versus read mode For RAM blocks in simple dual port mode enter the percentage of time port B of the RAM block is reading You cannot write to port B in simple dual port mode Port B is ignored for RAM blocks in ROM or single port mode This value must be a percentage number between 0 and 100 The default is 50 Toggle The average percentage of clock cycles that each block output signal changes value Multiplied by clock frequency to determine the number of transitions per second This value only affects routing power 50 corresponds to a randomly changing signal A random signal changes states only half the time Valid Width Mode This check fails if the entered data width or RAM mode is not compatible with the selected RAM type M512s do not support true dual port mode and M RAMs do not support ROM mode See the description of the data width column for the range of available widths for each RAM type Routing This shows the power dissipation due to estimated routing in W Routing power is highly dependent on placement and routing which is i
61. preadsheet it is very important to get a realistic estimate of the ambient temperature near the FPGA device Heat Sink When using a heat sink the power is determined by the following equations Tj Ta Oya P OrA Orc Ocs Osa The value pc is specific to the FPGA and can be obtained from the data sheet The value Ocs refers to the material that binds the heat sink to the FPGA and is approximated to be 0 1 C W The value 054 is obtained from the manufacturer of the heat sink It is important to ensure that when this value is obtained that it is for the right conditions for the FPGA which include analyzing the correct heat sink information at the appropriate airflow at the device For more information on how to determine heat sink information refer to AN 358 Thermal Management for 90 nm FPGAs and www altera com 3 49 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II
62. rPlay Early Power Estimator spreadsheet documented in this user guide Table 1 1 PowerPlay Early Power Estimator Spreadsheet Versions i PowerPlay Early Power Estimator Device Family Spreadsheet Version Stratix II 6 1 and later Stratix II GX 6 1 and later HardCopy II 6 1 and later The PowerPlay Early Power Estimator spreadsheet provides full support for the target Altera device families listed in Table 1 2 Table 1 2 Device Family Support Device Family Support Stratix II Full Stratix Il GX Full HardCopy II Partial Printed circuit board PCB designers need an accurate estimate of the amount of power the device consumes to develop an appropriate power budget design the power supplies voltage regulators heat sink and cooling system You can calculate a device s power using the Microsoft Excel based PowerPlay Early Power Estimator spreadsheet available from the Altera web site or the PowerPlay power analyzer in the Quartus II software You need to enter the device resources operating frequency toggle rates and other parameters in the PowerPlay early power estimator This user guide explains how to use the PowerPlay Early Power Estimator spreadsheet to estimate device power consumption Features These calculations should only be used as an estimation of power not as a specification Be sure to verify the actual power during device operation as the information is
63. rates is a non trivial problem that requires the designer to know what kind of input the FPGA is receiving and how often it toggles If the design is not yet complete it is very difficult to get an accurate estimate The best way to approach the problem is to isolate the separate modules in the design by functionality and estimate resource usage along with toggle rates of the resources The easiest way to accomplish this is to leverage previous designs to estimate toggle rates for modules with similar functionality As an example let us assume that there is a simple design that has an input data bus that has been encoded for data transmission and has a roughly 5076 toggle rate It then goes through a decoder and is stored in RAM The data is then filtered before being modulated with another input data bus and the result is encoded for transmission A simple block diagram is shown in Figure 3 32 Figure 3 32 Decoder amp Encoder Block Diagram Mod Input Data Decoder 9 RAM m Filter Modulator gt Encoder gt Altera Corporation January 2007 In this case the designer would have to estimate the following Data toggle rate Mod input toggle rate Resource estimate for Decoder module Resource estimate for RAM Resource estimate for Filter Resource estimate for Modulator Resource estimate for Encoder 3 45 PowerPlay Early Power Estimator For Stratix II Stratix
64. readsheet but it is required to compute the 05 for the heat sink with the knowledge of what the airflow is at the device Most heat sinks have fins located above the heat sink to facilitate airflow Figure 3 35 shows the case of an FPGA with a heat sink Figure 3 35 AirFlow amp Heat Sinks z n 4 gt Heat Sink Fins Heat Sink FPGA When placing the heat sink on the FPGA it is imperative that the direction of the fins correspond with the direction of the airflow A top view shows the correct orientation of the fins Figure 3 36 Altera Corporation 3 47 January 2007 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II Power Analysis Figure 3 36 Heat Sink Top View Heat Sink Fins gt Z n The considerations above can heavily influence the airflow seen at the device When entering information into the PowerPlay Early Power Estimator spreadsheet it is necessary to consider these implications in order to get an accurate airflow value It is the designer s responsibility to determine the actual airflow at the FPGA and correctly input this value into the PowerPlay Early Power Estimator spreadsheet Temperature The PowerPlay Early Power Estimator spreadsheet requires you to enter the ambient air temperature for the device in order to calculate the device therm
65. readsheet determines the junction to ambient thermal resistance 074 If you are using a low medium or high profile heat sink select the airflow from the options of still air and air flow rates of 100 lfm 0 5 m s 200 lfm 1 0 m s and 400 lfm 2 0 m s If you are using a custom heat sink enter the heat sink to ambient thermal resistance 054 The airflow should also be incorporated into 054 Therefore the Airflow parameter is not applicable in this case Obtain these values from the heat sink manufacturer The ambient temperature does not change but the junction temperature changes depending on the thermal properties Since a change in junction temperature affects the thermal device properties used to calculate junction temperature calculating junction temperature is an iterative process The total power is calculated based on the device resource usage which provide 0j4 9jp and the ambient board and junction temperature using the following equation Tj TA Tj Tp SA S Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Figure 3 30 shows the thermal analysis including the junction temperature Ty total Oja prm and the maximum allowed T4 values For details on the values of the thermal parameters not listed click the Details button Figure 3 30 Thermal Analysis in the PowerPlay Early Power
66. requency as the output frequency 0 to 550 MHz 3 28 Altera Corporation PowerPlay Early Power Estimator For Stratix Il Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Each row in the PLL section represents one or more PLLs in the device You need to enter the maximum output frequency and the VCO frequency for each PLL You must also specify whether each PLL is an LVDS fast or enhanced PLL Table 3 8 describes the values that need to be entered in the PLL section of the PowerPlay Early Power Estimator Table 3 8 PLL Section Information Column Heading Module Description Enter a name for the PLL in this column This is an optional value PLL Type Select whether the PLL is an LVDS fast or enhanced PLL PLL Blocks Enter the number of PLL blocks with the same specific output frequency and VCO frequency combination DPA Buses Enter the number of dynamic phase alignment DPA buses in use DPA is only available for LVDS PLLs Output Freq Enter the maximum output frequency fmax of the PLL in MHz The maximum output frequency is reported in the PLL Usage column of the Quartus Il Compilation Report In the Compilation Report select Fitter and click Resource Section Select PLL Usage and click Output Frequency If there are multiple clock outputs from the PLL choose the maximum output frequency listed The output frequency is the same as the VCO frequency for
67. rs directory names project names disk drive names filenames filename extensions and software utility names are shown in bold type Examples fmax qdesigns directory d drive chiptrip gdf file Italic Type with Initial Capital Letters Document titles are shown in italic type with initial capital letters Example AN 75 High Speed Board Design Italic type Internal timing parameters and variables are shown in italic type Examples tpa n 1 Variable names are enclosed in angle brackets lt gt and shown in italic type Example lt file name gt lt project name gt pof file Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters Examples Delete key the Options menu Subheading Title References to sections within a document and titles of on line help topics are shown in quotation marks Example Typographic Conventions Courier type Signal and port names are shown in lowercase Courier type Examples data1 tdi input Active low signals are denoted by suffix n e g resetn Anything that must be typed exactly as it appears is shown in Courier type For example c qdesigns tutorial chiptrip gdf Also sections of an actual file such as a Report File references to parts of files e g the AHDL keyword SUBDESIGN as well as logic function names e g TRI are shown in Courier 1 2 3 and Numbered steps are
68. rted from Quartus Il and must be entered manually Pre Emphasis Setting First Post Tap Enter the pre emphasis first post tap setting used by the transmitter This value cannot currently be imported from Quartus Il and must be entered manually Pre Emphasis Setting Second Post Tap Enter the pre emphasis second post tap setting used by the transmitter This value cannot currently be imported from Quartus Il and must be entered manually Vop mV Enter the output differential voltage VOD of the transmitter in mV It is assumed that the transmitter is using a termination resistance of 100 Ohms This value cannot currently be imported from Quartus Il and must be entered manually Channel Power W This shows the total power of the Rx and Tx hardware for all channels in W This value is calculated automatically CCU Power W This shows the total power of the PLLs and control circuitry used by all channels in W This value is calculated automatically Total Power W This shows the total power dissipation in W Sum of channel CCU power This value is calculated automatically User Comments Enter any comments This is an optional entry Altera Corporation January 2007 3 35 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II Power Analysis Figure 3 23 shows the Stratix II GX device PowerPlay Early Power Estimator spreadsheet and the esti
69. ry 2007 3 17 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II PowerPlay Early Power Estimator Inputs Figure 3 9 shows the PowerPlay Early Power Estimator spreadsheet and the estimated power consumed by the DSP blocks in this design Figure 3 9 DSP Section in the PowerPlay Early Power Estimator LG ee 0 030 CCC Uiz anon 25 6 Thermal Power W Clock Module Configuration Freq MHz of Toggle Reg Reg Pipe Instances Inputs Outputs lined Boning GS Lota 18x18 Mult Accum 12 5 1 1 2 18x16 Four Mult Adder 100 0 1 12 5 Yes Yes No 0 000 0 006 0 006 3 9x9 Two Mult Adder 100 0 1 12 5 Yes Yes No 0 000 0 001 4 9x9 Four Mult Adder 100 0 1 12 5 Yes Yes No 0 000 0 003 5 18x18 Two Mult Adder 100 0 1 12 5 Yes Yes No 0 000 6 18x18 Simple Mult 100 0 1 28 3 Yes No No 0 001 7 36x36 Simple Mult 0 0 i 12 5 Yes No No 0 000 8 18x18 Simple Mult 150 0 1 21 196 Yes No No 0 001 0 004 0 004 9 99 Simple Mult 100 0 1 34 096 Yes No No 0 000 0 002 0 002 10 9x9 Simple Mult 150 0 1 36 4 Yes No No 0 001 0 003 0 004 9x9 Simple Mult 0 0 D 12 5 Yes Yes No 0 000 0 000 0 000 9x9 Simple Mult 0 0 0 12 596 Yes Yes No 0 000 0000 0 000 General 1 0 Pins Stratix II Stratix II GX and HardCopy II devices feature programmable I O pins that support a wide range of in
70. s W Data rate in Mbps E Number of channels in that transmitter domain E Toggle percentage s The receiver power is the same whether or not the DPA circuitry is used Table 3 7 describes the parameters in the HSDI section of the PowerPlay Early Power Estimator Table 3 7 HSDI Section Information Column Heading TX RX Module Description Enter a name for the module in this column This is an optional value Data Rate Mbps Enter the maximum data rate in Mbps of the receiver or transmitter module The SERDES circuitry can transmit and receive data up to 1 000 Mbps per channel Therefore the data rate must be a decimal number from 0 to 1 000 Mbps 3t of Channels Enter the number of receiver and transmitter channels running at the above data rate This number must be an integer value from 0 to 156 Toggle Enter the average percentage of toggling on each clock cycle The toggle 6 ranges from 0 to 100 The default toggle percentage is 50 Total Power This shows the estimated power in W based on the data rate and number of channels entered This value is calculated automatically User Comments Enter any comments This is an optional entry Altera Corporation January 2007 3 27 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II PowerPlay Early Power Estimator Inputs Figure 3 17 shows the PowerPlay Early Power Estimator spreadsheet and the esti
71. standby and dynamic power gt The total thermal power only includes the thermal component for the I O section and does not include the external power dissipation such as from voltage referenced termination resistors Altera Corporation 3 37 January 2007 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II Power Analysis Figure 3 25 shows the total thermal power in Watts and the static power Pstatic consumed by the device The thermal power for each section is also displayed To see how the thermal power for a section was calculated click on the section to view the inputs entered for that section Figure 3 25 Thermal Power in the PowerPlay Early Power Estimator Thermal Power W Logic RAM DSP Vo HSDI PLL Clocks Pans TOTAL 2277 HardCopy II Table 3 12 describes the thermal power parameters in the PowerPlay Early Power Estimator Table 3 12 Thermal Power Section Information Column Heading Description Logic This shows the dynamic power consumed by ALMs and associated routing Click Logic to see details RAM This shows the dynamic power consumed by RAMs blocks and associated routing Click RAM to see details DSP This shows the dynamic power consumed by DSP blocks and associated routing Click DSP to see details y o This shows the thermal power consumed by I O pins and associated routing This includes static power diss
72. sted as different voltages in the PowerPlay Early Power Estimator spreadsheet can actually be in the same I O bank on the device For more information on I O standard guidelines see the Selectable I O Standards in Stratix II Devices chapter in volume 2 of the Stratix II Device Handbook If there are discrepancies between the Vccjo voltages in banks the PowerPlay Early Power Estimator spreadsheet displays the following message Bank and I O voltage selection inconsistent with I O Bank Voltage See the Bank Voltage column Ensure that the correct Vecio is selected for the bank Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Figure 3 15 shows an example of the Output Pins report in the Quartus II software Compilation Report The Compilation Report lists the I O standard used on each pin Figure 3 15 Output Pins Report in Compilation Report Output Output Enable TR Register Register Primitive Standard 1 fi TTL E 2 no no Off 18V Bm ES 3 no no Of 1 8V Bm 8 aaja 35 7 0 no no no no no m mo Of 18V 12m 5 4D13 10 36 0 1 no no no no no no no Off 1 8V 12m4 8 L3 5 62 22 3 no no no no no no no Off 18V m pe AD1210 38 0 2 no no no no no no no Off 18V 12m i8 L2 5 B2 22 0 no no no no no no no Off 18V EmA ER P3 5 62 20 0 no no no no no no no Off 18V Bm
73. t sink is being used for the device Not Using a Heat Sink When a heat sink is not used the major paths of power dissipation are from the device to the air This can be referred to as a junction to ambient thermal resistance 9 4 In this case there are two significant junction to 3 39 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II Power Analysis ambient thermal resistance paths The first is from the device through the case to the air and the second is from the device through the board to the air Figure 3 26 shows the thermal representation without a heat sink Figure 3 26 Thermal Representation without Heat Sink Case 4 Device Oya Board Thermal Representation without Heat Sink In the model used in the PowerPlay Early Power Estimator power is dissipated through the case and board Values of 0 4 have been calculated for differing air flow options accounting for the paths through the case and through the board Figure 3 27 shows the thermal model for the PowerPlay Early Power Estimator without a heat sink Figure 3 27 Thermal Model in the PowerPlay Early Power Estimator without a Heat Sink Ty Power P Oya Heat Ta Source The ambient temperature does not change but the junction temperature changes depending on the thermal properties Since a change in junction temperature affects the thermal device properties used to calcul
74. ta and address inputs The enable percentage ranges from 0 to 100 The default is set to 25 RAM power is primarily consumed when a clock event occurs Using a clock enable signal to disable a port when no read or write operation is occurring can result in significant power savings Port A Write 96 Enter the average percentage of time port A of the RAM block is in write mode versus read mode For simple dual port 1R 1W RAMs the write port A is inactive when not executing a write For single port and true dual port RAMs port A reads when not written to This field is ignored for RAMs in ROM mode This value must be a percentage number between 0 and 100 The default is 50 Port B Clock Freq Enter the clock frequency for port B of the RAM block s in MHz This value is limited by the maximum frequency specification for the RAM type and device family Port B is ignored for RAM blocks in ROM or single port mode Port B Enable 96 Enter the average percentage of time the input clock enable for port B is active regardless of activity on RAM data and address inputs The enable percentage ranges from 0 to 100 The default is set to 25 Port B is ignored for RAM blocks in ROM or single port mode RAM power is primarily consumed when a clock event occurs Using a clock enable signal to disable a port when no read or write operation is occurring can result in significant power savings 3 12 Altera C
75. tera Corporation PowerPlay Early Power Estimator For Stratix Il Stratix II GX amp HardCopy II N D TE YA Contents About this User Guide Revision History How to Contact Altera Typographic Conventions Chapter 1 About the PowerPlay Early Power Estimator Release Information eee Device Family Support General Description SE i den hene ere Oe CER RU eda E ipe VES CHER evens FRG Ra e cases Edo SEE TRI E Chapter 2 Setting Up PowerPlay Early Power Estimator System Requirements eire nete pere titre ect deett iei de iebecke es ere ETTR isasi oi Download amp Install the PowerPlay Early Power Estimator Estimating POWOet ierit there iens Estimating Power Before Starting the FPGA Design Estimating Power While Creating the FPGA Design Estimating Power After Completing the FPGA Design Entering Information into the PowerPlay Early Power Estimator Cleating AM Vales Manually Entering Information sese entente nennen Importing a File Importing Information from PowerPlay Early Power Estimator V6 0 sss 2 6 Chapter 3 Using the PowerPlay Early Power Estimator FSS OGG TTT PowerPlay Early Power Estimator Inputs Main Input Parameters one nitet erinnere tires En M n RAM Blocks een Digital Signal Processing DSP General I O
76. tself a function of design complexity The values shown are representative of routing power based on experimentation on over 100 customer designs Use the Quartus Il PowerPlay Power Analyzer for detailed analysis based on the routing used in your design This value is calculated automatically Block This shows the power dissipation due to internal toggling of the RAM in W Use the Quartus Il PowerPlay Power Analyzer for accurate analysis based on the exact RAM modes in your design This value is calculated automatically Total This shows the estimated power in W based on the inputs you entered It is the total power consumed by RAM blocks and is equal to the routing power and the block power This value is calculated automatically User Comments Enter any comments This is an optional entry Altera Corporation January 2007 3 13 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II PowerPlay Early Power Estimator Inputs 3 14 Figure 3 6 shows the Resource Usage Summary section in the Quartus II software Compilation Report for a design targeting the device family The Compilation Report provides the number of RAM resources being used Figure 3 6 Resource Usage Summary Fitter Resource Usage Summary Register only ALUTs Unavailable Due to unpartnered 7 input function Due to unpartnered 6 input function ALUT usage by number of inputs 7 i
77. u must enter a board temperature in the Board Temp field This field is only available when you select Auto Computed Ty and Estimated Dr Board thermal resistance is a function of device package number of signal and power layers metallization at each layer inter layer thickness and many other parameters 6 values for a typical customer board stack based on selected device and package are provided for estimation purposes Users should perform a detailed thermal simulation of their system to determine final junction temperature This two resistor thermal model is for early estimation only Custom 65g C W Enter the junction to board thermal resistance obtained from thermal simulation if Custom is selected under Board Thermal Model This field is only available when you select Auto Computed T and Estimated Oya Board Temp Tg C Enter the temperature on the PCB at the back side of the device This temperature is combined with the 6 value of the board to compute the junction temperature for the FPGA This field is only available when you select Auto Computed T and Estimated 0 4 If the entered board temperature is less than ambient the tool assumes ambient temperature in its thermal analysis since it is not possible for the board to be below ambient Similarly board temperatures in excess of the computed junction temperature are capped to the junction temperature 3 4 Altera Corporation PowerPlay Earl
78. ublication to include Stratix Il Stratix II GX and HardCopy v1 0 Il support How to Contact Altera For the most up to date information about Altera products go to the Altera world wide web site at www altera com For technical support on this product go to www altera com mysupport For additional information about Altera products consult the sources shown below Information Type Technical support USA amp Canada www altera com mysupport All Other Locations www altera com mysupport 800 800 EPLD 3753 7 00 a m to 5 00 p m Pacific Time 1 408 544 8767 7 00 a m to 5 00 p m GMT 8 00 Pacific Time Product literature www altera com www altera com Altera literature services literature altera com literature altera com Altera Corporation Typographic Conventions Information Type Non technical customer service USA amp Canada 800 767 3753 All Other Locations 1 408 544 7000 7 00 a m to 5 00 p m GMT 8 00 Pacific Time FTP site ftp altera com ftp altera com Typographic Conventions This document uses the typographic conventions shown below Visual Cue Bold Type with Initial Capital Letters Meaning Command names dialog box titles checkbox options and dialog box options are shown in bold initial capital letters Example Save As dialog box bold type External timing paramete
79. uently and hence toggle rates of less than 50 are more realistic For example a TFF with its input tied to Vcc has a toggle rate of 100 because its output is changing logic states on every clock cycle Figure 3 2 Figure 3 3 shows an example of a 4 bit counter The first TFF with least significant bit LSB output cout has a toggle rate of 100 because the signal toggles on every clock cycle The toggle rate for the second TFF with output cout 1 is 50 since the signal only toggles on every two clock cycles Consequently the toggle rate for the third TFF with output cout2 and fourth TFF with output cout3 are 25 and 12 5 respectively Therefore the average toggle percentage for this 4 bit counter is 100 50 25 12 5 4 46 875 Routing This shows the power dissipation due to estimated routing in W Routing power is highly dependent on placement and routing which is itself a function of design complexity The values shown are representative of routing power based on experimentation on over 100 designs Use the Quartus Il PowerPlay Power Analyzer for detailed analysis based on the routing used in your design Block This shows the power dissipation due to internal toggling of the ALMs in W Logic block power is a function of the function implemented and relative toggle rates of the various inputs The PowerPlay Early Power Estimator spreadsheet uses an estimate based on observed behavior across over 100 real world d
80. ultiplier adder 9 x 9 four multiplier adder 18 x 18 four multiplier adder Enter the clock frequency for the module in MHz This value is limited by the maximum frequency specification for the device family of Instances Enter the number of instances that have the same configuration clock frequency toggle percentage and register usage This value is independent of the number of dedicated DSP blocks being used For example it is possible to use four 9 x 9 simple multipliers that would all be implemented in the same DSP block in a Stratix II device In this case the number of instances would be four 3 16 Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Table 3 4 DSP amp Multiplier Section Information Part 2 of 2 Column Heading Toggle Description Enter the average percentage of DSP data outputs toggling on each clock cycle The toggle percentage ranges from 0 to 50 Typically the toggle percentage is 12 5 For a more conservative power estimate you can use a higher toggle percentage In addition 50 corresponds to a randomly changing signal since half the time the signal changes from a 0 gt 0 or 1 gt 1 This is considered the highest meaningful toggle rate for a DSP block Reg Inputs Select whether the input to the dedicated DSP block or multiplier block is registered
81. urrent provides the estimated current consumption for power supplies The Iccrnr current is the supply current required from Vccint The Iccpp current is the supply current required from Vccpp The total Icco current is the supply current required from Vccio for all I O banks For estimates of Iccio based on I O banks refer to the I O section 3 43 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II Power Analysis of the PowerPlay Early Power Estimator The total Iccxcyg current is the supply current required from all the transceiver specific power rails Vecer Vecu Veer Veca Vece and Vec For estimates of IccxcvR based on power rails refer to Transceiver XCVR on page 3 33 Figure 3 31 shows the power supply current estimation Iccinr Iccrp Iccio and Iccxcvr are displayed Figure 3 31 Power Supply Current in the PowerPlay Early Power Estimator Power Supply Current A lecint lccen lccio Iccxcvn Click buttons for details Table 3 14 describes the parameters in the Power Supply Current parameters of the PowerPlay Early Power Estimator Table 3 14 Power Supply Current Information Column Heading Iocint Description This shows the total current drawn from the lcciyr supply in A locpp This shows the total current drawn from the pre drive Iccpp supply in A lccio This shows the total current drawn from the Iccio power rail s See the I
82. used in a list of items when the sequence of the items is a b c etc important such as the steps listed in a procedure E o Bullets are used in a list of items when the sequence of the items is not important v The checkmark indicates a procedure that consists of one step only LS The hand points to information that requires special attention vi Altera Corporation PowerPlay Early Power Estimator For Stratix Il Stratix II GX amp HardCopy II About this User Guide Typographic Conventions Visual Cue Meaning The caution indicates required information that needs special consideration and understanding and should be read prior to starting or continuing with the procedure or process CAUTION The warning indicates information that should be read prior to starting or continuing the procedure or processes 4a The angled arrow indicates you should press the Enter key ET The feet direct you to more information on a particular topic Altera Corporation vii PowerPlay Early Power Estimator For Stratix II Stratix Il GX amp HardCopy Il Typographic Conventions viii Altera Corporation PowerPlay Early Power Estimator For Stratix Il Stratix II GX amp HardCopy II Chapter 1 About the ANU 8 BA PowerPlay Early Power Estimator Release Information Device Family Support General Description Altera Corporation January 2007 Table 1 1 provides information on the version of the Powe
83. ws the thermal model for the PowerPlay Early Power Estimator Figure 3 29 Thermal Model for the PowerPlay Early Power Estimator with a Heat Sink Ty Ty Power P Power P Tg Heat Source Altera Corporation 3 41 January 2007 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II Power Analysis 3 42 If you want the PowerPlay Early Power Estimator spreadsheet thermal model to take the junction to board thermal resistance 055 into consideration set the Board Thermal Model to either Typical or Custom A Typical board thermal model sets prms to a value based on the package and device selected If you choose a Custom board thermal model you must specify a value for 0j If you do not want the PowerPlay Early Power Estimator spreadsheet thermal model to take the 075 resistance into consideration set the Board Thermal Model to None conservative In this case the path through the board is not considered for power dissipation and a more conservative thermal power estimate is obtained The junction to ambient thermal resistance 074 is determined by the addition of the junction to case thermal resistance 0c the case to heat sink thermal resistance 9cs and the heat sink to ambient thermal resistance 054 Oya Orc Ocs F Osa Based on the device package airflow and the heat sink solution selected in the main input parameters the PowerPlay Early Power Estimator sp
84. y 2007 Using the PowerPlay Early Power Estimator Table 3 6 1 O Module Information in the 1 0 Section Part 2 of 3 Column Heading Clock Freq MHz Description Enter the clock frequency in MHz This value must be in the range of 0 to 1040 MHz 100 MHz with a 12 5 toggle means that each I O pin toggles 12 5 million times per second 100 x 12 5 Output Pins Enter the number of output pins used in this module A differential pair of pins should be considered as one pin Input Pins Enter the number of input pins used in this module A differential pair of pins should be considered as one pin Bidir Pins Enter the number of bidirectional pins used in this module The I O pin is treated as an output when its output enable signal is active and an input when the output enable is disabled An I O configured as bidirectional but used only as an output consumes more power than one configured as an output only due to the toggling of the input buffer every time the output buffer toggles they share a common pin I O Bank Select the I O bank that the module is located in If you do not know which I O bank the pins are assigned to leave the value as Assigning the I O module to a bank checks whether or not your I O voltage assignments are compatible This allows per bank Iccio reporting The PowerPlay Early Power Estimator spreadsheet does not take any I O placement constraints into consider
85. y Current A Iocint This shows the current drawn from the Iccinr rail Powers internal digital circuitry and routing This value is calculated automatically Supply Current A Icep D This shows the current drawn from the Vccpp rail This rail powers the pre drive circuitry and operates at 3 3 V This value is calculated automatically Supply Current A Iccio This shows the current drawn from this bank s Vccio rail Some of this current may be drawn into off chip termination resistors This value is calculated automatically User Comments Enter any comments This is an optional entry 3 22 Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Figure 3 12 shows the I O module parameters in the PowerPlay Early Power Estimator spreadsheet I O section Figure 3 12 PowerPlay Early Power Estimator Spreadsheet O Section Thermal Power W Supply Current A Clock DER Bank Bank i E Hist wine E fai Las VO Std Voltage Routing Block Total IccINT IccPD lcclO vo Me Check Check Drive Strength Module VO Standard OnChip Freq Output Input Bidir Termination MHz Pins Pins Pins
86. y Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Using the PowerPlay Early Power Estimator Figure 3 1 shows the Main section of the PowerPlay Early Power Estimator Figure 3 1 PowerPlay Early Power Estimator Spreadsheet Main Section PowerPlay Early Power Estimator Visit the Online Stratix II Stratix Il GX HardCopy II Power Management Resource Center V6 1 Comments Input Parameters Thermal Power W Thermal Analysis Junction Temp T CC Family Device 9 4 Junction Ambient Package 0 5 Junction Board Temperature Grade Maximum Allowed Ts C Power Characteristics Details User Entered Tj Auto Computed Tj Ambient Temp T C EE C Custom Theta JA Estimated Theta JA Power Supply Current A Heat Sink leer 0252 Airflow leceo 0 002 Custom 85 C W Board Thermal Model Custom 6 CCW Board Temp Te C Iccio 0 004 Click buttons for details HardCopy Il Lm Set Toggle Reset Import Quartus Il File Import EPE V6 0 View Report Logic A design is a combination of several design modules operating at different frequencies and toggle rates Each design module can have a different amount of logic For the most accurate power estimation partition the design into different design modules You can partition your design by grouping modules by clock frequency location hierarchy or entities Each row in the Logic section represents a
87. y user entered values and populates the PowerPlay Early Power Estimator spreadsheet with device resource information from the specified PowerPlay Early Power Estimator spreadsheet legacy version file 2 6 Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 Setting Up PowerPlay Early Power Estimator After importing PowerPlay Early Power Estimator spreadsheets you must manually ensure that all the information is correct Altera Corporation 2 7 January 2007 PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II Entering Information into the PowerPlay Early Power Estimator 2 8 Altera Corporation PowerPlay Early Power Estimator For Stratix II Stratix II GX amp HardCopy II January 2007 L Chapter 3 Using the ANU 8 BA PowerPlay Early Power Estimator Introduction PowerPlay Early Power Estimator Inputs Altera Corporation January 2007 The PowerPlay Early Power Estimator spreadsheet provides the ability to enter information into sections based on architectural features The PowerPlay Early Power Estimator spreadsheet also provides a subtotal of power consumed by each architectural feature and is reported in each section in watts W The following sections of the user guide explain what values you need to enter for each section of the PowerPlay Early Power Estimator The different Excel worksheets of the PowerPlay Early Power

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