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ALTERA FIR Compiler user manual

1. The timing diagrams for Serial Multibit serial and MCV multicycle filters would be similar to Figure 4 17 and Figure 4 18 For an filter with a Clocks to Compute value of N and interpolation factor M new input data is required every NxM clock cycles and a new output would be produced every M clock cycles Decimation Filter Timing Diagrams In a decimation by M filter for every M input data one output will be produced Figure 4 22 on page 4 22 shows that for a Parallel or single cycle decimation by 2 filter new input data is taken each clock cycle and new output data is produced every other clock cycle May 2011 Altera Corporation FIR Compiler User Guide 4 22 Chapter 4 Functional Description Timing Diagrams Figure 4 22 Single Channel Decimation by 2 Parallel MCV Single Cycle clk reset_n ast_sink_ready ast_sink_valid ast_sink_data ast_source_data Q M _ aa y f96 If the filter is time shared by N that is the Clocks to compute value is N then new input data is required every N clock cycles and new output data is produced every NxM cycles Figure 4 23 shows the timing diagram for a Multibit serial filter with two serial units and an input data width of 8 bits Figure 4 23 Three Channel Decimation Filter Serial MBS MCV Multicycle clk reset_n ast_sink_ready ast_sink_valid ast_sink_sop ast_sink_eop ast_sink_data ast_source
2. 4 18 Single Rate Filter Timing Diagram 4 18 Interpolation Filter Timing Diagrams 4 20 Decimation Filter Timing Diagrams 4 21 Coefficient Reloading Timing Diagrams 4 22 Referenced Documents 2 0 0 0 0c ccc ce nn en eee eee en en rh 4 26 Appendix A FIR Compiler Supported Device Structures Supported Device Structures e be eked eter ee ere pe sie bb ERI wea A 1 Support for HardCopy Series Devices A 3 Compiling HardCopy Designs 22 A 3 Additional Information Revisi n HIStory T Info 1 How to Contact Alteta 44e p Cere Ec ee EC ea e ACE Pacte ga Info 2 Typographic Conventions 22220 Info 2 FIR Compiler User Guide May 2011 Altera Corporation 1 About the FIR Compiler A DTE RYA This document describes the Altera FIR Compiler The Altera FIR Compiler provides a fully integrated finite impulse response FIR filter development environment optimized for use with Altera FPGA devices You can use the Altera IP Toolbench interface with the Altera FIR Compiler to implement a variety of filter
3. Technology Option Area Speed Data Throughput Distributed Fully parallel Large area Creates a fast filter 140 to over 300 MSPS throughput with arithmetic pipelining in Stratix II devices Distributed Fully serial Small area Requires multiple clock cycles for a single computation arithmetic Distributed Multibit Medium area Uses several serial units to increase throughput This results arithmetic serial in greater throughput than fully serial but less throughput than fully parallel DSP block Multicycle Area depends on the number Data throughput increases as the number of calculation multiplier of calculation cycles selected cycles decreases This architecture takes advantage of area increases as the number Stratix Stratix 11 Stratix IIl or Stratix IV DSP Blocks and of calculation cycles increases Cyclone II Multipliers Available Pipelining Creates a higher performance Increases throughput with additional latency and size option for all filter with an area increase increase architectures For more information about the filter architectures and how they operate refer to FIR Compiler on page 4 1 May 2011 Altera Corporation FIR Compiler User Guide 3 12 Table 3 4 Multicycle Filter Architecture Chapter 3 Parameter Settings Specify the Architecture Specification Table 3 4 Table 3 5 Table 3 6 and Table 3 7 describe the FIR Compiler options that are available for each architecture
4. FIR Filter Design 6 Weeks Specify Filter Characteristics to FIR Compiler Megafunction FIR Compiler Assists in Area Speed Tradeoff Simulate Synthesize amp Place amp Route Features The Altera FIR Compiler implements a finite impulse response FIR filter MegaCore function and supports the following features m The following hardware architectures are supported to enable optimal trade offs between logic memory DSP blocks and performance m Fully parallel distributed arithmetic m Fully serial distributed arithmetic Multibit serial distributed arithmetic m Multicycle variable structures m Exploit maximal efficiency designs as a result of FIR Compiler hardware optimizations such as interpolation decimation symmetry decimation half band and time sharing m Easy system integration using Avalon Streaming Avalon ST interfaces May 2011 Altera Corporation FIR Compiler User Guide 1 4 Chapter 1 About the FIR Compiler Release Information B Precision control of chip resource utilization m Logic cells M512 M RAM MLAB or M144K for data storage m M512 M9K M20K MLAB or logic cells for coefficient storage m Includes a resource estimator m Support for run time coefficient reloading capability and multiple coefficient sets m Includes a built in coefficient generator to enable efficient design space explorati
5. ast source ready FIR Compiler User Guide May 2011 Altera Corporation Chapter 4 Functional Description 4 21 Timing Diagrams Figure 4 20 Single Channel Interpolation by 2 Parallel MCV Single Cycle ast sink ready Control clk SJUUUUUU UU UU LU UU LU LI LU LI reset n E ast sink ready L TT L5 tt Ti IL ast sink valid ast sink data ast source valid ast source data These timing diagrams also apply to an single cycle filter An interpolation by 2 filter produces two output data for each input data it receives As seen from the figures a new output is produced every cycle This means that new input data is required every other cycle This behavior can be observed easily when the flow of data is controlled by the ast sink valid signal as in Figure 4 19 Figure 4 21 shows the timing diagram for a three channel interpolation by 2 filter with a Parallel or MCV single cycle architecture illustrating the additional start of packet and end of packet signals Figure 4 21 Three Channel Interpolation by 2 Parallel MCV Single Cycle clk PLEL LLL LLL LLL LL LLL LI LL LI LI UT LT LT LI LT UT LI reset n ast sink ready O ast sink valid ast sink sop I 1 ast sink eop 1 Lit 1 L ast sink data 0 1 e 13 amp st source ready ast source valid ast source sop ast source eop ast source data
6. An input data is processed every 1 clock periods Anew output data is generated Pipeline Level 3 every clock period 2 Click Finish when you have set the architecture parameters May 2011 Altera Corporation FIR Compiler User Guide 3 16 Chapter 3 Parameter Settings Resource Estimates Resource Estimates The FIR Compiler automatically calculates and displays the estimated resources that the filter will use in the Resource Estimates box of the Architecture Specification section Parameterize FIR Compiler page The FIR Compiler provides the estimated size in embedded memory blocks DSP blocks and logic cells The Throughput box displays the number of clock cycles required to compute the result Figure 3 10 Figure 3 10 Resource Estimates Resource Utilization esti Throughput Fully Streaming E ae An input data is processed MAK 0 every 1 clock periods Anew output data is generated M144Kk 0 every clock period MLAB 1 Multipliers 0 The resource usage estimate may differ from Quartus resource usage by 30 depending on which optimization method you use in the Quartus II software Additionally the resource estimator is less accurate for small filters 500 logic cells or less For small filters compile the design in the Quartus II software to obtain the resource us
7. Parameterize FIR Compiler n E3 r Rate Specification Add global clock enable pin r Input Specification Number of Input Channels Input Number System Signed Binary Input BitWidth 8 lv r Output Specification Full Resolution Bit Width is 18 Based on Method Actual Coefficients iv Output Number System Full Resolution Iv rArchitecture Specification Device Family Stratix IIl v Force Non Symmetric Structur Resource Logic Cells Utilization esti 1138 Throughput Fully Streaming Structure Distributed Arithmetic Fully Parallel Filter 0 An input data is processed every 1 clock periods Pipeline Level v Anew output data is generated every clock period Data Storage Logic Cells Coefficient Storage Logic Cells Using the FIR Compiler Coefficient Generator 1 Click New Coefficient Set in the Parameterize FIR Compiler page to open the Coefficients Generator dialog box You can use this dialog box to specify parameters for the coefficients including the filter type window type sample rate and excess bandwidth for use with cosine filters Figure 3 2 on page 3 3 shows the default values for a low pass filter FIR Compiler User Guide May 2011 Altera Corporation Chapter 3 Parameter Settings Specifying the Coefficients Fi
8. variation name constraints tcl Constraints setting Tcl file for Quartus II synthesis This file contains the necessary constraints to achieve FIR Filter size and speed lt variation name gt _input txt This text file provides simulation data for the MATLAB model and the simulation testbench variation name mlab m This MATLAB M File provides the kernel of the MATLAB simulation model for the customized FIR MegaCore function variation lt variation name gt _model m This MATLAB M File provides a MATLAB simulation model for the customized FIR MegaCore function variation variation name gt _msim tel This Tcl script can be used to simulate the VHDL testbench together with the simulation model of the customized FIR MegaCore function variation variation name gt _nativelink tcl A Tcl script that can be used to assign NativeLink simulation testbench settings to the Quartus II project variation name param txt This text file records all output parameters for customized FIR MegaCore function variation variation name silent param txt This text file records all input parameters for customized FIR MegaCore function variation variation name core vhd variation name st v variation name st s v variation name st u v variation name st wr v Generated FIR Filter netlists These files are required for Quartus II synthesis and are added to your current Quartus I
9. eene tree hee EX eR hier aer Rhe e Rel t dece e ner 1 4 Device Family Support sas cC eet ee e Maori MEME gles Va b e eet enin 1 5 MegaCore Verification ss est ea s PRA HK E Sh puedo geb Ped o bcn enge dones 1 6 Performance and Resource Utilization 222 1 6 Installation and Licensing 42222222 1 8 OpenCore Plus Evaluation 44444488 cen anda np pis e eate a ee Ie d ee dee etes 1 8 OpenCore Plus Time Out Behavior 22 1 9 Chapter 2 Getting Started Design FLOWS m 2 1 DSP Builder Flow 2 2 2 M tede dede Manette e ed ote ndun a 2 1 MegaWizard Plug In Manager Flow nn 2 2 Parameterize the MegaCore Function 22 2 3 Generate the MegaCore Function nnn 2 6 Simulate the D esigri ssi use hee quer arsenal des 2 8 Simulating in ModelSim 220 2 8 Simulating in MATLAB 444 444 essere ken bene er ehe ee a e Ih eem ee d e 2 9 Simulating in Third Party Simulation Tools Using Nativelink 2 9 Compile the Design and Program a Device 2 9 Chapter 3 Parameter Settings Specifying the Coefficlents oec da n
10. FIR Compiler User Guide May 2011 Altera Corporation TS B4AN 2 Getting Started Design Flows The FIR Compiler MegaCore function supports the following design flows m DSP Builder Use this flow if you want to create a DSP Builder model that includes a FIR Compiler MegaCore function variation m MegaWizard Plug In Manager Use this flow if you would like to create a FIR Compiler MegaCore function variation that you can instantiate manually in your design This chapter describes how you can use a FIR Compiler MegaCore function in either of these flows The parameterization is the same in each flow and is described in Chapter 3 Parameter Settings After parameterizing and simulating a design in either of these flows you can compile the completed design in the Quartus II software DSP Builder Flow Altera s DSP Builder product shortens digital signal processing DSP design cycles by helping you create the hardware representation of a DSP design in an algorithm friendly development environment DSP Builder integrates the algorithm development simulation and verification capabilities of The MathWorks MATLAB and Simulink system level design tools with Altera Quartus II software and third party synthesis and simulation tools You can combine existing Simulink blocks with Altera DSP Builder blocks and MegaCore function variation blocks to verify system level specifications and perform simulation In DSP Builde
11. T T T 0 m SSS SS FIR Compiler User Guide May 2011 Altera Corporation Chapter 4 Functional Description 4 19 Timing Diagrams This filter accepts an input every clock cycle and produces an output every clock cycle Because ast source ready andast sink valid are kept at high the filter can internally run fully streaming An input is transferred when ast sink readyandast sink valid are both high during the rising edge of the clock Figure 4 16 shows a three channel filter with the same specification as the single channel filter in Figure 4 15 Figure 4 16 Three Channel Single Rate Parallel or MCV Single Cycle clk reset_n ast_sink_ready ast_sink_valid ET TETE IE pa TEE EN ET ast sink sop 1 1 ast sink eop 11 1 1 ast sink data 0 Ba nh E nom mn ast source ready ast source valid 1 d ol lb T ast source sop L rT 1 i ast source eop I L ast source data 0 Ja 8 12 En 22 33 le ast_source_channel 0 fi 2 0 le The FIR filter now has start of packet sop and end of packet signals for both the sink input and source output modules The first input data to the FIR filter is accompanied by the high value of the ast sink sop port which means it belongs to the first channel The third input data is marked as an end of packet by the high value of the ast sink eo
12. Timing Diagrams The reset n signal resets the control logic and state machines that control the FIR Compiler not including data storage elements that hold previous inputs used to calculate the result The previous data is not cleared when the reset n signal is applied To clear the data set the ast sink data port to 0 for n clock cycles where n number of coefficients x number of input channels x number of clock cycles needed to compute a FIR result The FIR output value depends on the coefficient values in the design Therefore the timing diagrams of your own design may be different than those shown in the following figures However you can use the testbench generated by the FIR compiler to get the correct timing relation between signals for a specific parameterized case timing diagrams assume a full streaming operation where ast source ready and ast sink ready are always 1 unless otherwise stated May 2011 Altera Corporation FIR Compiler User Guide 4 18 Chapter 4 Functional Description Timing Diagrams Reset and Global Clock Enable Operations Figure 4 14 shows the reset and clock enable operations Figure 4 14 Reset and Clock Enable Protocol clk reset_n enable ast_sink_ready ast_sink_valid ast_sink_data When the reset reset is applied to the filter the ast sink ready and ast source valid signals go low At the next rising edge of the clock c1k after the reset is
13. multibit serial m PAR fully parallel m lt coefficient store is m LC logic cells m M512 M512 and MLAB blocks m and blocks m AUTO Automatic memory block selection m allow or disallow symmetry is m MSYM Take advantage of symmetric coefficients m NOSYM Use nonsymmetric coefficients m number of calculations for coefficient bit width for others is m for multicycle variable filters the number of clock cycles to calculate the result m for all other filters use the coefficient bit width m number of coefficient sets is the user specified number of coefficient sets m lt filter rate is be specified as one of the following SGL INT DEC m SGL Single Rate FIR Filter m INT Interpolating FIR Filter xm DEC Decimating FIR Filter m lt filter factor is an integer value representing the rate changing factor m Forsingle rate filters this argument should be set to 1 m For multirate FIR filters this argument should be an integer between 1 and 16 m lt coefficient bit width is the integer value representing the user specified coefficient bit width which ranges from 2 32 For example coef seq exe D FIR coef log txt D FIR coef in txt M4K MSYM 4 1 SGL 1 8 57 The program checks for symmetry automatically but you can force it to disallow symmetry Your specification should be consistent with the setting in the FIR Compiler wizard The reloading capability allows you to chang
14. An IP Functional Simulation Model is a cycle accurate VHDL or Verilog model produced by the Quartus Il Software It allows for fast functional simulations of IP using industry standard VHDL and Verilog simulators You may only use these simulation model output files for simulation purposes and expressly notfor synthesis or any other purposes Using these models for synthesis will create a non functional design 3 Turn on Generate Simulation Model to create an IP functional model La An IP functional simulation model is a cycle accurate VHDL or Verilog HDL model produced by the Quartus II software May 2011 Altera Corporation Chapter 2 Getting Started 2 5 MegaWizard Plug In Manager Flow Use the simulation models only for simulation and not for synthesis or any other purposes Using these models for synthesis creates a non functional design CAUTION 4 Select the required language from the Language list 5 Click the MATLAB M File tab on the Set Up Simulation page Figure 2 5 6 Turn on the Generate MathWorks MATLAB M File option This option generates a MATLAB m file script that contains functions you can use to analyze a FIR Compiler design in the MATLAB environment A testbench is also generated Figure 2 5 Create a MATLAB M File set Up Simulation FIR Compiler MATLAB M File Generate MathvVorks MATLAB M File Selecting the above option will create a MATLAB M fil
15. Coefficient signed 1 interface and M512 M4K to 32 optional global MLAB M9K unsigned clock enable Auto Interpolation 4 to 32 Avalon ST Logic cell Auto Logic cell Yes N A Reloadable interface and M512 Coefficient must optional global MLAB M9K be in memory clock enable Auto Decimation 4 to 32 Avalon ST Logic cell Auto Logic cell Yes N A Reloadable interface and M512 Coefficient must optional global MLAB M9K be in memory clock enable Auto Multicycle Clocks to 2t032for Avalon ST Logic cell Auto Logic cell if Yes Yes Variable compute 1 signed 1 interface and number of to 32for optional global coefficient unsigned clock enable set gt 1 M512 MLAB M9K Auto Clocks to 2to 32 for Avalon ST Logic cell Auto Logic cell Yes Yes compute 2 signed 1 interface and M512 M4K to 32for optional global MLAB M9K unsigned clock enable Auto Clocks to 21032 for Avalon ST Logic cell M512 Logic cell Yes Yes compute 3 signed 1 interface and MLAB M9K M512 M4K to 32 optional global M144K Auto MLAB M9K unsigned clock enable Auto Interpolation 2to 32 for Avalon ST Logic cell M512 Logic cell Yes N A Clocks per signed 1 interface and MLAB M512 output 1 to 32for optional global M144K Auto MLAB M9K unsigned clock enable Auto Decimation 2t0 32 for Avalon ST Logic cell M512 Logic cell Y
16. Throughput Equivalent ALUTs Registers Bits M9K ALUTs 18x18 MHz MSPS GMACS 7 766 1 166 55 276 42 16 503 101 10 Multicycle variable 1 cycle decimation by 4 pipeline level 1 2 3 336 844 1 400 16 28 14 443 443 43 Multicycle variable 1 cycle interpolation by 4 pipeline level 2 3 200 1 274 64 8 24 372 372 36 Multicycle variable 1 cycle pipeline level 2 2 3 741 1 936 148 1 8 48 443 443 43 Multicycle variable 4 cycle pipeline level 2 2 3 717 1 398 796 6 36 14 323 81 8 Parallel LE pipeline level 1 2 3 2 153 2 672 157 1 8 421 421 41 Parallel M9K pipeline level 1 3 821 1 730 119 872 45 8 457 457 44 Serial M9K pipeline level 1 2 3 245 415 14 231 11 8 523 58 6 Notes to Table 1 6 1 GMAC giga multiply accumulates per second 1 giga 1 000 million 2 This FIR filter takes advantage of symmetric coefficients 3 Using EPASGX70DF29C2X devices 4 The data width is 16 bits and there are 4 serial units May 2011 Altera Corporation FIR Compiler User Guide Chapter 1 About the FIR Compiler Installation and Licensing Installation and Licensing The FIR Compiler MegaCore function is part of the MegaCore IP Library which is distributed with the Quartus II software and downloadable from the Altera website www altera com For system requirements and installation instructions refer to the Altera Software Installation and Lic
17. where N number of polyphase filters x number of clocks to compute each polyphase result The number of polyphase filters is equal to the decimation factor The input data must be held for the time it takes to compute a single polyphase filter May 2011 Altera Corporation Chapter 4 Functional Description 4 11 FIR Compiler Figure 4 10 Decimation Filter Structure input J LN output LPF Yn pum input N Channel P 0 output input gt N Coefficient Set H Accumulator gt output Single Rate FIR Filter d Control Circuitry May 2011 Availability of Interpolation and Decimation Filters Interpolation and decimation filters are available for all architectures Parallel distributed arithmetic Serial distributed arithmetic Multibit serial distributed arithmetic Multicycle variable structures architecture configuration options are available for interpolation and decimation filters including User configuration of data storage type memory or logic cells User configuration of coefficient storage type memory or logic cells Multichannel capability Multiple coefficient set capability Family Specific Features Stratix IV Stratix III and Stratix II filters implement ternary adder structures in all architectures Altera Corporation Fully parallel distributed arithmetic Fully serial distributed arithmetic
18. 3 5 Fully Serial Filter Architecture Note 1 Parameter Data Storage Description Specifies the device resources used for data storage You can select Logic Cells M512 M4K M RAM MLAB M9K M144K or Auto If you select Auto the Quartus II software may store data in logic cells or memory depending on the resources in the selected device the size of the data storage and the number of input channels Coefficient Storage Specifies the device resources used for coefficient storage You can select Logic Cells M512 MLAB M9K or Auto If you select Auto the Quartus software automatically selects the most appropriate memory block size for the selected device The option list changes depending on which device you select Selecting embedded memory reduces logic cell usage and may increase the speed of the filter Force Non Symmetric Structure If you want to create a design that uses both symmetric and non symmetric coefficients turn on this option Symmetric algorithms require an extra clock cycle per calculation cycle which leads to lower throughput Coefficients Reload If you want to change coefficients turn on this option This option is available when you choose to store coefficients in embedded memory Selecting this option increases resource usage turns off several optimization schemes and adds additional input ports to the filter Pipeline Level Creates a higher performance filter
19. Multibit serial distributed arithmetic Multicycle variable FIR Compiler User Guide 4 12 Pipelining Ls FIR Compiler User Guide Chapter 4 Functional Description FIR Compiler All multicycle variable structures allow the use of hard multipliers in Stratix IV Stratix Stratix Stratix Cyclone III and Cyclone II structures In addition Stratix IV Stratix III Stratix II and Stratix multicycle variable implementations take advantage of the built in adder structures in the DSP block Stratix series devices allow the most flexibility for data and coefficient storage You can choose between M512 and MRAM when appropriate for Stratix and Stratix II devices Stratix III and Stratix IV devices support MLAB M9K and M144K Half Band Decimation Filters A decimation half band optimized architecture is available for multicycle variable structures This architecture uses half the number of multipliers compared to the decimation symmetric architecture when a half band coefficient set is selected A halfband coefficient set has an odd number of symmetric coefficients and every other coefficient value is 0 Currently only a single fixed coefficient set is supported with this optimized architecture The data storage and coefficient storage should be set to either Auto or one of the available block memories Any value for the decimation factor and the number of channels can be selected The number of clocks to compute should
20. Rate Specification New Coefficient Set Edit Coefficient Set Remove Coefficient Set Single Rate Iv Facto Low Pass Set 1 Low Pass Set 2 Add global clock enable rInput Specification Number of Input Channels 5 Coefficients 0 499575 Input Number System Signed Binary ss Input Bit Width 8 0 106012 r Output Specification Coefficients Original Value Scaled Value Fixed Point Value Full Resolution Bit Width is 17 0 0167338 0 015734645 4 0 0 0 0 Based on Method Actual Coefficients 0 0187044 0 015734645 0 0 0 0 0 0211985 0 019668307 0 0 0 0 0 0244618 0 023601968 0 0 0 0 0 0289095 0 027535629 0 0 0 0 0 0353359 0 03146929 0 0 0 0 Frequency Response Time Response amp Coefficient Values Coefficients Scaling Auto v Bitwiat v Architecture Specification 26 Output Number System Cn Full Resolution ojojo en co 5 oleo Device Family Stratix 111 Force Non metric Structure Resare Utilization esti Throughput Fully Streaming Logic Cells 4170 Structure Distributed Arithmetic Fully Parallel Filter M512 0 M4K Pipeline Level 1 iv M RAM Anew output data is generated M9K M144K lee clock period Data Storage Logic Cells iv Multiplier Implementation Logic Celle MLAB Multipliers Coefficient S
21. Time Response amp Coefficient Values tab The FIR Compiler supports two s complement signed binary fractional notation which allows you to monitor which bits are preserved and which bits are removed during filtering A signed binary fractional number has the format sign integer bits gt lt fractional bits A signed binary fractional number is interpreted as shown below sign lt x integer bits gt lt y fractional bits Original input data sign x integer bits gt lt y fractional bits Original coefficient data sien i integer bits gt lt y y fractional bits Full precision after FIR calculation sign lt x integer bits gt lt y fractional bits Output data after limiting precision where i ceil log numiber of coefficients x x If for example the number has 3 fractional bits and 4 integer bits plus a sign bit the entire 8 bit integer number is divided by 8 which yields a number with a binary fractional component DSP Builder incorporates the sign bit as part of the integer bits Thus if you are using the FIR filter in a DSP Builder design DSP builder will recognize the sign bit as an additional integer bit When converted to decimal numbers certain fractions have an infinite number of binary bits For example converting 1 3 to a decimal number yields 0 333n with n representing an infinite number of 3s Similarly numbers such as 1 10 cannot be represented in a finite number of binar
22. be greater than 1 The FIR Compiler automatically picks the decimation half band optimized architecture when these conditions are met Symmetric Interpolation Filters A new symmetric interpolation optimized architecture is available for multicycle variable structures This architecture requires half the number of multipliers compared to the standard interpolation filter when a symmetric coefficient set is selected The number of filter taps should be an odd value Currently only a single fixed coefficient set is supported with the optimized architecture The data storage and coefficient storage should be set to either Auto or one of the available block memories Any value for interpolation factor and number of channels can be selected The number of clocks to compute should be greater than 1 The FIR compiler automatically picks the optimized architecture when these conditions are met Pipelining is most effective for producing high performance filters at the cost of increased latency the more pipeline stages you add the faster the filter becomes Pipelining breaks long carry chains into shorter lengths Therefore if the carry chains in your design are already short adding pipelining may not speed your design The FIR Compiler lets you select whether to add one two or three pipeline levels May 2011 Altera Corporation Chapter 4 Functional Description 4 13 Simulation Output Simulation Output The FIR Compiler generates a
23. benefit makes FIR filters attractive enough to be designed into a large number of systems However for a given frequency response FIR filters are a higher order than IIR filters making FIR filters more computationally expensive Altera Corporation FIR Compiler User Guide FIR Compiler User Guide Chapter 1 About the FIR Compiler The structure of a FIR filter is a weighted tapped delay line as shown in Figure 1 2 21 Tapped Delay Line Coefficient Multipliers Adder Tree yout The filter design process involves identifying coefficients that match the frequency response specified for the system These coefficients determine the response of the filter You can change the signal frequencies that pass through the filter by changing the coefficient values or adding more coefficients Figure 1 2 Basic FIR Filter DSP processors have a limited number of multiply accumulators MACs and require many clock cycles to compute each output value the number of cycles is directly related to the order of the filter A dedicated hardware solution can achieve one output per clock cycle A fully parallel pipelined FIR filter implemented in an FPGA can operate at very high data rates making FPGAs ideal for high speed filtering applications Table 1 1 compares resource usage and performance for different implementations of a 120 tap FIR filter with a 12 bit data input bus Table 1 1 FIR Filter Impleme
24. eop Output Marks the end of the outgoing FIR filter result group If 1 a result corresponding to channel A 1 is output where Vis the number of channels ast source error Output Error signal indicating Avalon ST protocol violations on the source side m 00 No error m 01 Missing SOP m 10 Missing EOP m 11 Unexpected EOP Other types of errors are also marked as 11 coef set Input Selects which coefficient set the FIR filter uses for the calculation Appears when multiple coefficient sets are used The width of this signal log number of coefficient sets coef in clk Input Clock to reload coefficients when coefficients are stored in memory Appears when the Coefficient Reload option is selected and the Use Single Clock option is not selected This clock can be different than clk coef set in Input Selects which coefficient set to be reloaded Appears when multiple coefficient sets are used and the Coefficient Reload option is selected The width of this signal log number of coefficient sets coef in Input Input coefficient value when reloading coefficient Appears when the Coefficient Reload option is selected coef we Input Active high write enable signal Enables coefficient overwriting when coefficients are reloadable coef 1 Output Coefficient reload control port This port is created only when multicycle filters are selected and the coefficient storage is logic cells
25. in coef we should be one clock cycle ahead of coef in First data is always 0 5 Serial multibit serial and parallel FIR architectures use a distributed arithmetic algorithm In the algorithm look up tables store partial products of the coefficient the first data of the partial product is always 0 When reloading pre calculated coefficients in serial multibit serial and parallel architectures the first reloading coefficient is always 0 For information about how to pre calculate coefficients refer to Coefficient Reloading and Reordering on page 4 4 May 2011 Altera Corporation FIR Compiler User Guide 4 24 Chapter 4 Functional Description Timing Diagrams Multicycle variable reloading is faster than the fixed FIR with reloading capability Coefficients need sequence adjustment using the same algorithm as fixed FIR filters for all types of coefficient storage The reloading clock is the same as the FIR filter calculation clock coef we should be triggered by the coef_1d signal La When the coefficients are stored in logic cells a reloaded coefficient set reverts backs to the original set after a reset operation Figure 4 26 shows the Multicycle variable coefficient reloading timing diagram when the coefficients are stored in logic cells Figure 4 26 Multicycle Variable Using Logic Cells Coefficient Reloading Timing Diagram Coef we is valid one clock cycle after effective coef Id
26. load multiple coefficient sets If the specified timing requirements are not met when loading multiple coefficient sets a specific set of coefficients will not be identified Figure 4 29 Timing Requirements for Loading Multiple Coefficient Sets cik xp LI crue ast sink ready 7 ast sink data i CINE i 1 coef we coef in coef set coef set in ast source valid ast source data coef set in must be sustained one clock cycle longer than coef we gt May 2011 Altera Corporation FIR Compiler User Guide 4 26 Chapter 4 Functional Description Referenced Documents Referenced Documents FIR Compiler User Guide Altera application notes white papers and user guides providing more detailed explanations of how to effectively design with MegaCore functions and the Quartus II software are available at the Altera web site www altera com In particular refer to the following references MegaCore IP Library Release Notes and Errata AN320 OpenCore Plus Evaluation of Megafunctions Altera Software Installation and Licensing manual Avalon Interface Specifications DSP Builder User Guide Simulating Altera Designs chapter in volume 3 of the Quartus Handbook May 2011 Altera Corporation JAN DTE YA A FIR Compiler Supported Device Structures Supported Device Structures Table A 1 lists the device structures supp
27. number of output files for design simulation After you have created a custom FIR filter you can use the output files with MATLAB or VHDL simulation tools You can use the test vectors and MATLAB software to simulate your design IP functional simulation models will output correct data only when data storage is clear When data storage is not clear functional simulation models will output non relevant data The number of clock cycles it takes before relevant samples are available is N where N number of channels x number of coefficients x number of clock cycles to calculate an output For a full list of files generated by the FIR Compiler refer to Table 2 1 on page 2 6 Avalon Streaming Interface The Avalon Streaming Avalon ST interface defines a standard flexible and modular protocol for data transfers from a source interface to a sink interface and simplifies the process of controlling the flow of data in a datapath Avalon ST interface signals can describe traditional streaming interfaces supporting a single stream of data without knowledge of channels or packet boundaries Such interfaces typically contain data ready and valid signals The Avalon ST interface can also support more complex protocols for burst and packet transfers with packets interleaved across multiple channels The Avalon ST interface inherently synchronizes multi channel designs which allows you to achieve efficient time multiplexed implementati
28. option This option is available when you choose to store coefficients in embedded memory Selecting this option increases resource usage turns off several optimization schemes and adds additional input ports to the filter Pipeline Level Creates a higher performance filter with a resource usage increase Use Single Clock Use this option when creating designs with DSP Builder This option is only available when Coefficients Reload is selected and M512 MLAB M9K is specified in Coefficient Storage This option ties the coe c1k in and clk signals together Note to Figure 3 6 1 When input data is unsigned the input data bit width should be greater than or equal to one When input data is signed the input data bit width should be greater than or equal to two FIR Compiler User Guide May 2011 Altera Corporation Chapter 3 Parameter Settings 3 15 Specify the Architecture Specification 1 Forthis tutorial select Distributed Arithmetic Fully Parallel Filter structure with a pipeline level of 3 Although these settings create a filter that uses a large number of logic cells increasing the pipeline level to 3 decreases the number of clock cycles to one thereby greatly increasing system performance These settings are shown in Figure 3 9 Figure 3 9 Specify the Filter Architecture Parameterize Coefficients Specification Low Pass Set 2 r Rate Specification New Coef
29. or update the coefficients This can be done on chip or by using the coefficient reordering program coef esq exe included in the install path Nfir compilerNmisc directory and described in the section Coefficient Reloading and Reordering on page 4 4 Compiling HardCopy Designs When you store your data in memory or you store your coefficients in memory and reload them you must delete the memory initialization files described below before you can successfully compile a HardCopy design in the Quartus II software If you are storing data in memory to successfully compile your design in the Quartus II software you must delete the following file from the project directory before compiling your design variation name zero hex If you store your coefficients in memory and reload them to successfully compile your design in the Quartus II software you must delete the following file from the project directory before compiling your design variation name coef X hex where X is an integer These files are created by the FIR Compiler and are stored in the project directory you specified when you ran the FIR Compiler May 2011 Altera Corporation FIR Compiler User Guide 4 FIR Compiler User Guide Appendix A FIR Compiler Supported Device Structures Support for HardCopy Series Devices May 2011 Altera Corporation JAN DTE nS AA Additional Information Revision History The following table displays the revi
30. provides greater throughput than a standard serial structure while using less area than a fully parallel structure allowing you to trade off device area for speed Figure 4 5 shows the multibit serial structure Figure 4 5 Multibit Serial Structure Input Data Filter Serial FIR Compiler FIR Created Glue Filtered Filter Logic Data Serial Filter FIR Compiler User Guide 4 8 Le Chapter 4 Functional Description FIR Compiler Figure 4 6 shows the area speed trade off of fixed FIR filters Figure 4 6 Fixed FIR Filters Area Vs Throughput Parallel With Extended Pipelining Throughput Multi Bit With Extended Serial Pipelining ay With Extended Pipelining Area Two serial filters operating in parallel compute the result at twice the rate of a single serial filter Three serial filters operate at triple the speed four operate at four times the speed For example a 16 bit serial FIR filter requires 16 clock cycles to complete a single FIR calculation A multibit serial FIR filter with two serial structures takes only eight clock cycles to compute the result Using four serial structures only four clock cycles are required to perform the computation Three serial structures cannot be used for a 16 bit serial structure however because 16 does not divide evenly by three Multichannel Structures When designing DSP systems you may need to generate two FIR filte
31. released ast sink ready goes high indicating that the design is ready to accept new data This behavior is independent of the filter type and architecture because there is a small FIFO in the Avalon ST controller The global clock enable signal where it exists can also control when the FIR MegaCore function is stalled The Avalon ST controller operates independent of the global clock enable The FIR is stalled as soon as the global clock enable goes low However because of the internal buffering in the Avalon ST controller the ast sink ready signal can go low in the following cycles For the same reason when the global enable is high ast sink ready may go high at a later cycle The ast source valid signal is produced by the Avalon ST controller is therefore independent of the global clock enable When the available valid data is transferred and no more output data is available it goes low until there is valid data to transfer Single Rate Filter Timing Diagram Figure 4 15 shows the timing diagram of a single channel single rate FIR filter implemented either in MCV architecture with a Clocks to Compute value of 1 or in Parallel architecture Figure 4 15 Single Channel Single Rate Parallel or MCV Single Cycle clk reset_n ast_sink_ready ast_sink_valid ast sink data ast source ready ast source valid ast source data JSLUPLILU LULU LULU UP UU uu UU UU iU 1 T1 1 LL vL 31 T L 011
32. startofpacket SOP 10 Missing endofpacket EOP 11 Unexpected EOP or any other error The Avalon Interface Specifications define many signal types many of which are optional Table 4 2 lists the signal types used by the Avalon ST interfaces for the FIR Compiler MegaCore function Any signal type not explicitly listed in the table is not included Table 4 2 Avalon ST Interface Signal Types Signal Type Width Direction ready 1 Sink to Source valid 1 Source to Sink data data width Source to Sink channel log number of channels Source to Sink error 2 Source to Sink startofpacket 1 Source to Sink endofpacket 1 Source to Sink Fora full description of the Avalon ST interface protocol refer to the Avalon Interface Specifications Avalon ST Data Transfer Timing Figure 4 11 shows the Avalon ST interface signals Figure 4 11 Avalon ST Interface Data Source Data Sink ready valid data error M channel startofpacket gt endofpacket _ _ __ gt FIR Compiler User Guide May 2011 Altera Corporation Chapter 4 Functional Description 4 15 Avalon Streaming Interface The sink indicates to the source that it is ready for an active cycle by asserting the ready signal for a single clock cycle Cycles during which the sink is ready for data are called ready cycles During a ready cy
33. with a resource usage increase Use Single Clock Use this option when creating designs with DSP Builder This option is only available when Coefficients Reload is selected and M512 MLAB or M9K is specified in Coefficient Storage This option ties the coe in clk and clk signals together Note to Table 3 5 1 The input data bit width should be greater than or equal to four Table 3 6 Multibit Serial Filter Architecture Part 10f2 Note 1 Parameters Description Number of Serial Units Specifies the number of serial units needed to make the filter You can select 2 3 or 4 The calculation cycles of each result are reduced to one nth of the corresponding serial filter where n is the number of serial units Correspondingly there is an increase in resource utilization Data Storage Specifies the device resources used for data storage You can select Logic Cells M512 M RAM MLAB M9K M144K or Auto If you select Auto the Quartus software selects the type of embedded memory blocks depending on the resources in the selected device the size of the data storage the number of clock cycles to compute a result and the number of input channels The option list changes depending on which device you select and whether you select multirate interpolation or decimation Choosing embedded memory reduces logic cell usage and may increase the speed of the filter Coefficient Sto
34. 4 Functional Description FIR Compiler Because the FIR Compiler is an automated design tool it is possible to implement a multichannel multiple coefficient set interpolation or decimation filter which is further implemented as a multichannel multiple coefficient set structure The net result of these optimization techniques is a general savings in resources Implementation Details for Interpolation and Decimation Structures Figure 4 9 and 4 14 illustrate the results when applying polyphase decomposition to interpolation and decimation filters Figure 4 9 Interpolation Filter Structure input 4 LN p gt output LPF N Channel P 0 output input 9N Coefficient Set output Single Rate FIR Filter N CERES 1 4 4 Control Circuitry P 2 e e e P N 1 FIR Compiler User Guide Figure 4 9 illustrates an interpolation structure It takes a constant number of clocks to compute each polyphase output The input data must be held for the number of clocks to compute each polyphase output multiplied by the number of polyphase units which is the same as the interpolation factor Figure 4 10 on page 4 11 shows a decimation filter with polyphase decomposition Each polyphase filter must be computed prior to computing the final results Because there are several polyphase results that must be accumulated it is clear that the output will update every N clocks
35. Cosine m Root Raised Cosine m Half Band low pass You can adjust the number of taps cut off frequencies sample rate filter type and window method to build a custom frequency response Each time you apply the settings the FIR Compiler calculates the coefficient values and displays the frequency response on a logarithmic scale The coefficients are floating point numbers and must be scaled The values are displayed in the Coefficients scroll box of the Coefficients Generator Dialog box refer to Figure 3 2 on page 3 3 When the FIR Compiler reads in the coefficients it automatically detects any symmetry The filter gives you several scaling options for example scaling to a specified number of bits or scaling by a user specified factor The scaled coefficients are displayed in the Time Response amp Coefficient Values tab of the Parameterize FIR Compiler page refer to Figure 3 5 on page 3 6 Coefficient Scaling Coefficient values are often represented as floating point numbers To convert these numbers to a fixed point system the coefficients must be multiplied by a scaling factor and rounded The FIR Compiler provides five scaling options m Auto scale to a specified number of precision bits Because the coefficients are represented by a certain number of bits itis possible to apply whatever gain factor is required such that the maximum coefficient value equals the maximum possible value for a given number of bits This appr
36. FIR Compiler User Guide S SPAN 101 Innovation Drive San Jose CA 95134 www altera com Software Version 11 0 Document Date May 2011 Copyright 2011 Altera Corporation rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending ap plications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services UG FIRCOMPILER 11 0 LS EN ISO 9001 AEPA Contents Chapter 1 About the FIR Compiler ho uno n 1 3 Release Information 1 eror
37. I project tb variation name gt vhd This VHDL file provides a testbench for the customized FIR MegaCore function variation Notes to Table 2 1 1 variation name is a prefix variation name supplied automatically by IP Toolbench 2 The entity name prefix is added automatically The VHDL code for each MegaCore instance is generated dynamically when you click Finish so that the entity name is different for every instance It is generated from the variation name by appending ast May 2011 Altera Corporation FIR Compiler User Guide Chapter 2 Getting Started MegaWizard Plug In Manager Flow The generation report also lists the ports defined in the MegaCore function variation file Figure 2 7 For a full description of the signals supported on external ports for your MegaCore function variation refer to Table 4 3 on page 4 16 Figure 2 7 Port Lists in the Generation Report Generation FIR Compiler MegaCore Function Variation File Ports een d MegaCore Function Generation Successful 2 After you review the generation report click Exit to close IP Toolbench Then click Yes on the Quartus II IP Files prompt to add the qip file describing your custom MegaCore function variation to the current Quartus II project Simulate the Design FIR Compiler User Guide To simulate your design in Verilog HDL or VHDL use the IP func
38. M Specify the Input and Output Specifications You can specify the Number of Input Channels that is the number of data streams that generate an output for each stream and the Input Number System in the Parameterize FIR Compiler page Figure 3 7 May 2011 Altera Corporation FIR Compiler User Guide 3 10 Ls FIR Compiler User Guide Chapter 3 Parameter Settings Specify the Input and Output Specifications The FIR Compiler calculates how many bits your filter requires for full resolution using two methods actual coefficients or the coefficient bit widths These parameters define the maximum positive and negative output values Select either Bit Width Only or Actual Coefficients in the Output Specification drop down box The FIR Compiler will extrapolate the number of bits required to represent that range of values For full precision you must use this number of bits in your system If your filter has coefficient reloading or multiple sets of coefficients you must select Bit Width Only You can use full or limited precision for the filtered output out To use full precision leave the Output Number System set to Full Resolution default To limit the precision select Custom Resolution or Signed Binary Fractional from the drop down box When the Output Number System is set to Custom Resolution you can choose to truncate or saturate the most significant bit MSB and to truncate or round the least signific
39. Note 1 Parameter Description Clocks to Compute Specifies the number of clock cycles required to compute a result Using more clock cycles to compute a result reduces the filter resource usage The number of multipliers the filter uses is equal to the number of taps divided by the number of clock cycles to compute the result Data Storage Specifies the device resources used for data storage You can select Logic Cells M512 M4K M RAM MLAB M9K M144K or Auto If you select Auto the Quartus II software may store data in logic cells or memory depending on the resources in the selected device the size of the data storage the number of clock cycles to compute a result and the number of input channels The option list changes depending on which device you select and the number of clock cycles to compute a result Choosing embedded memory reduces logic cell usage and may increase the speed of the filter Coefficient Storage Specifies the device resources used for coefficient storage You can select Logic Cells M512 MAK MLAB M9K or Auto If you select Auto the Quartus software automatically selects the most appropriate memory block size for the selected device The option list changes depending on which device you select and the number of clock cycles to compute a result Choosing embedded memory reduces logic cell usage and may increase the speed of the filter Multiplier Implementation Specify the dev
40. Website www altera com support Technical training Website www altera com training Email custrain altera com Product literature Website www altera com literature Non technical support Email nacomp altera com General Software Licensing Email authorization altera com Note to table 1 You can also contact your local Altera sales office or sales representative Typographic Conventions This document uses the typographic conventions shown in the following table Visual Cue Meaning Bold Type with Initial Capital Indicates command names dialog box titles dialog box options and other GUI Letters labels For example Save As dialog box bold type Indicates directory names project names disk drive names file names file name extensions and software utility names For example qdesigns directory d drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicates document titles For example AN 519 Stratix IV Design Guidelines FIR Compiler User Guide May 2011 Altera Corporation Additional Information Typographic Conventions Info 3 Visual Cue Italic type Meaning Indicates variables For example n 1 Variable names are enclosed in angle brackets gt For example file name and project name pof file Initial Capital Letters Indicates keyboard keys and menu names For example Delete key and the Options menu Subheading Title Quotat
41. _ready ast source valid ast source sop ast source eop ast source data 9 18 2 15 30 astsouce chanel OO The filter needs new data every four clock cycles and produces an output every 8 clock cycles Because the flow is controlled by ast sink ready the input data fetching occurs in a groups where ast sink ready goes high for five cycles and five new data inputs are taken at once Then ast sink ready goes low and no data is accepted for 15 cycles The ast source sopand ast source eop signals mark the start of packet and end of packet respectively Coefficient Reloading Timing Diagrams FIR Compiler User Guide The coefficient reload ports are not Avalon ST compliant and work independently of the enable and reset signals and of the Avalon ST controller You can load new coefficients even if the filter is under reset conditions or not enabled Serial multibit serial and parallel FIR filters use a distributed arithmetic algorithm and the coefficients stored in memory blocks are precalculated When updating the coefficients the new coefficients first go through a pre calculating algorithm The first data to reload in each memory block is always zero The rising edge of the coef we signal resets the internal data address counter for reloading May 2011 Altera Corporation Chapter 4 Functional Description 4 23 Timing Diagrams For information about how to pre calculate coefficients refer to Coefficient Reloading and Reor
42. age Filter Design Tips This section provides some additional tips for using the FIR Compiler m To prevent high pass filters from rolling off near Nyquist select an odd number of taps You can import coefficients from the MATLAB software into the FIR Compiler via a text file Simply save your coefficients as fixed or floating point numbers to an ASCII file one coefficient per line m To make a quadrature phase shift keying QPSK quadrature amplitude modulation QAM or phase shift keying PSK modulator or demodulator using the FIR Compiler create a multichannel filter by indicating two or more channels on the input specification area m Acomb filter is a filter that has repetitive notches You can make a comb filter by first making a single notch filter and then using sub sampling The process of sub sampling reflects or mirrors the notches in the frequency domain at all frequencies above Nyquist FIR Compiler User Guide May 2011 Altera Corporation Chapter 3 Parameter Settings Filter Design Tips May 2011 3 17 When importing floating point coefficients you should apply a scaling factor to generate fixed point integer numbers Because coefficients are rounded to the nearest integer the scaling or gain factor can be set to zero i e if it is too small If you do not scale the coefficients appropriately you may have a filter with many zeros The highest throughput filters are parallel filters with exte
43. all controlled within the DSP Builder environment DSP Builder supports integration with SOPC Builder using Avalon Memory Mapped Avalon MM master or slave and Avalon Streaming Avalon ST source or sink interfaces e For more information about these interface types refer to the Avalon Interface Specifications MegaWizard Plug In Manager Flow The MegaWizard Plug in Manager flow allows you to customize a FIR Compiler MegaCore function and manually integrate the MegaCore function variation into a Quartus II design To launch the MegaWizard Plug in Manager perform the following steps 1 Create a new project using the New Project Wizard available from the File menu in the Quartus II software 2 Launch MegaWizard Plug in Manager from the Tools menu and select the option to create a new custom megafunction variation Figure 2 1 Figure 2 1 MegaWizard Plug In Manager MegaWizard Plug In Manager page 1 is The Megawizard Plug In Manager helps you create or modify iA S design files that contain custom variations of megafunctions Which action do you want to perform Create a new custom megafunction variation Edit an existing custom megafunction variation Copy an existing custom megafunction variation Copyright 1991 2009 Altera Corporation Cancel 3 Click Next and select FIR Compiler lt version gt from the DSP gt Filters section in the Installed Plug Ins tab Figu
44. an update other sets Therefore your filter can switch between an infinite number of coefficient sets To maximize silicon efficiency coefficients are not stored in their natural order Reordering is performed automatically during the initial design However if the filter coefficients are reloadable any new coefficient set that you want to reload during the filter operation must be reordered before the reload A C program that can be used to reorder coefficients is provided A precompiled executable for Windows is also provided The program can be found in lt install path gt fir_compiler misc The C source code file is named coef_seq cpp and the executable program for the Windows operating system is coef_seq exe You can add the source code to your coefficient generation program or use the executable file to re order the coefficients The command to use coef_seq exe is coef seq exe path input txt path output txt FIR structure coefficient store allow or disallow symmetry number of calculations for MCV coefficient bit width for others number of coefficient sets filter rate filter factor coefficient bit width 57 You should include the directory path with the input and output coefficient file names as indicated above May 2011 Altera Corporation Chapter 4 Functional Description 4 5 FIR Compiler where m FIR structure is MCV multicycle variable m SER fully serial m MBS
45. ant bit LSB Saturation truncation and rounding are non linear operations Table 3 2 shows the options for limiting the precision of your filter Table 3 2 Options for Limiting Precision Bit Range Option Result MSB Truncate In truncation the filter disregards specified bits Figure 3 8 Saturate In saturation if the filtered output is greater than the maximum positive or negative value that can be represented the output is forced or saturated to the maximum positive or negative value LSB Truncate Same process as for MSB Round The output is rounded away from zero Figure 3 8 shows an example of removing bits from the MSB and LSB Figure 3 8 Removing Bits from the MSB and LSB Bits Removed from MSB Bits Removed from LSB Bits Removed from both MSB amp LSB D15 D15 D111 D15 D14 014 D10 D14 D13 D13 010 D12 D12 D9 D11 D10 D1 D9 gt 09 04 DO D8 gt 08 D3 D3 01 D2 D2 D0 D1 D1 DO DO DO Full Limited Full Limited Full Limited Precision Precision Precision Precision Precision Precision Alternatively you can select Signed Binary Fractional notation and specify the number of bits to keep The FIR Compiler displays how many bits are removed May 2011 Altera Corporation Chapter 3 Parameter Settings 3 11 Specify the Architecture Specification When adjusting the inp
46. architectures including fully parallel serial or multibit serial distributed arithmetic and multicycle fixed variable filters The FIR Compiler includes a coefficient generator Traditionally designers have been forced to make a trade off between the flexibility of digital signal processors and the performance of ASICs and application specific standard product ASSPs digital signal processing DSP solutions The Altera DSP solution reduces the need for this trade off by providing exceptional performance combined with the flexibility of FPGAs Figure 1 1 shows a typical DSP system that uses Altera IP cores including the FIR Compiler and other DSP IP cores Figure 1 1 Typical Modulator System Outer Encoding Layer FEC Convolutional Reed Solomon ped Encoder gt Encoder Viterbi P Input gt Data Inner Coding Layer FIR Compiler NCO Compiler Output FIR Compiler Data May 2011 Many digital systems use signal filtering to remove unwanted noise to provide spectral shaping or to perform signal detection or analysis Two types of filters that provide these functions are finite impulse response FIR filters and infinite impulse response IIR filters Typical filter applications include signal preconditioning band selection and low pass filtering In contrast to IIR filters FIR filters have a linear phase and inherent stability This
47. ase a license you can request a license file from the Altera website at www altera com licensing and install it on your computer When you request a license file Altera emails you a license dat file If you do not have Internet access contact your local Altera representative May 2011 Altera Corporation Chapter 1 About the FIR Compiler 1 9 Installation and Licensing For more information about OpenCore Plus hardware evaluation refer to AN320 OpenCore Plus Evaluation of Megafunctions OpenCore Plus Time Out Behavior OpenCore Plus hardware evaluation supports the following operation modes m Untethered the design runs for a limited time m Jethered requires a connection between your board and the host computer If tethered mode is supported by all megafunctions in a design the device can operate for a longer time or indefinitely megafunctions in a device time out simultaneously when the most restrictive evaluation time is reached If there is more than one megafunction in a design a specific megafunction s time out behavior might be masked by the time out behavior of the other megafunctions The untethered timeout for the FIR Compiler MegaCore function is one hour the tethered timeout value is indefinite The data output signal is forced to zero when the hardware evaluation time expires May 2011 Altera Corporation FIR Compiler User Guide 1 10 Chapter 1 About the FIR Compiler Installation and Licensing
48. cle the source may assert valid and provide data to the sink If it has no data to send it deasserts valid and can drive data to any value When READY 0 data is transferred only when ready and valid are asserted on the same cycle In this mode of operation the source data does not need to receive the sink s ready signal before it begins sending valid data The source provides the data and asserts valid whenever it can and waits for the sink to capture the data and assert ready The sink only captures input data from the source when ready and valid are both asserted Figure 4 12 illustrates the data transfer timing Figure 4 12 Avalon ST Interface Timing with READY LATENCY 0 0 1 2 3 4 5 6 7 8 clk xd i Ve ATEN ee ready valid _ eror 00 o EE 00 data D De a The source provides data and asserts valid on cycle 1 even though the sink is not ready The source waits until cycle 2 when the sink does assert ready before moving onto the next data cycle In cycle 3 the source drives data on the same cycle and because the sink is ready to receive it the transfer occurs immediately In cycle 4 the sink asserts ready but the source does not drive valid data Packet Data Transfers A beat is defined as the transfer of one unit of data between a source and sink interface This unit of data may consist of one or more
49. clk del T uw ves ptem reset n NE coef Id _ coe coef we coef in ast sink ready ast sink data ast source valid ast source data Input coefficients coef in are sequence adjusted For multicycle variable FIR filters when coefficients are stored in memory blocks coef we should be effective two clock cycles before the first coef_in data and should last until the last coe in data is transmitted Coefficients can be transmitted from c0 to cn by a different clock Figure 4 27 shows the Multicycle variable coefficient reloading timing diagram when the coefficients are stored in memory blocks Figure 4 27 Multicycle Variable Using Memory Blocks Coefficient Reloading Timing Diagram coef we is effective two clock cycles before first coef in data ast sink ready ast sink data coef in clk coef we coef in ast source valid ast source data Coefficients from c0 to cN If you use multiple coefficient sets you can update one set of coefficients while using another set for calculation The signals coe set in and coef_we are not clocked in and pipelined synchronously While you update the coefficient set you need to set and hold the coe set in signal for several cycles before coef_we is asserted and aft
50. dering on page 4 4 In serial and multibit serial filters coef we is effective two clock cycles ahead of the first coef in data and lasts until the last coe in data is transmitted In parallel filters coe we only needs to be effective one clock cycle ahead of the first coe in data To reload another set of coefficients coef_we must be low for at least one clock cycle The reload clock does not have to be the same clock as the one used by the FIR calculation Figure 4 24 shows the serial and multibit serial coefficient reloading timing diagram Figure 4 24 Serial and Multibit Serial Coefficient Reloading Timing Diagram Clock to reload coefficients Precalculated coefficient values clk reset n i ast sink ready ast sink data 0 Y 1 Y 1 coef in clk coef we coef in T T myo 7 5 yo coef set T T T T coef set in 1 ast source valid ast source data coef we should be two clock cycles ahead of coef in First data is always 0 Figure 4 25 shows the parallel coefficient reloading timing diagram Figure 4 25 Parallel Coefficient Reloading Timing Diagram clk jo reset_n 1 ast sink data 0 coef in clk coef we coef in coef set coef set
51. e coefficient values These filters may contain optimizations for symmetrical filters If you want a filter that may need both symmetrical and non symmetrical filters turn on Force Non Symmetrical Structures in the Architecture Specification section of the Parameterize FIR Compiler page May 2011 Altera Corporation FIR Compiler User Guide 4 6 Structure Types Chapter 4 Functional Description FIR Compiler If you select multiple set coefficients the filter can update one coefficient set while another set is being used for a calculation The FIR Compiler wizard generates multicycle variable parallel serial multibit serial and multichannel structures of these structures support coefficient reloading For information about reordering the coefficients before reloading them refer to Coefficient Reloading and Reordering on page 4 4 Multicycle Variable Structures Multicycle variable MCV filters are optimized for high throughput In a multicycle variable structure the designer specifies that the filter uses 1 to 1 024 clock cycles to compute a result for any filter that fits into a single device For Stratix Stratix II Stratix or Stratix IV devices if you select the multicycle variable structure selecting DSP Blocks in the Multiplier list box allows the FIR Compiler to use embedded DSP blocks for multipliers This implementation results in a smaller and faster design Parallel Structures A parallel structu
52. e for generated FIR Compiler design Using MATLAB M file you can analyze a generated FIR Compiler design under the MATLAB environment M file contains script of functions that extend the MATLAB environment to solve particular classes of problems M file will be created in your working directory look for file with m extension 7 Click Finish gt The Quartus II Testbench tab contains an option that is not used in this version of the FIR Compiler and should be ignored May 2011 Altera Corporation FIR Compiler User Guide 2 6 Chapter 2 Getting Started MegaWizard Plug In Manager Flow Generate the MegaCore Function To generate your MegaCore function variation perform the following steps 1 Click Step 3 Generate in IP Toolbench to generate your MegaCore function variation and supporting files The generation phase may take several minutes to complete The generation progress and status is displayed in a report window Figure 2 6 shows the generation report Figure 2 6 Generation Report FIR Compiler MegaCore Function E Generation FIR Compiler Cou E MegaCore Variation HDL output Directory o mydesigns fir File Summary The MegaWizard interface is creating the following files in the output directory Fite Description myfitter vhd Quartus symbol file for the MegaCore function variation You can use this myfitter bsf CBE BACC eil ai iae t is MegaCore Function Genera
53. e ready astsouce valid oF TL TL TL est source data Figure 4 18 Single Channel Single Rate Serial Multibit Serial MCV Multicycle ast sink ready Control clk SUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUNL reset n let 1 1 1 1 t1 1 1 ast sink ready amp st sink valid ast sink data 0 210 Bur 74 165 19 124 61 132 137 173 ast source ready amp ast source valid ast source data 0 la f 17 5 22 2 In Figure 4 17 the flow is controlled by the data provider asserting ast sink valid every three clock cycles In Figure 4 18 ast sink validis always held high and the data provider can feed new data in every clock cycle but the filter accepts new data every three clock cycles by asserting ast sink ready In this scenario a number of data samples are fetched at once and then ast sink ready is de asserted for a longer period This behavior is due to the internal buffering of the Avalon ST controller Interpolation Filter Timing Diagrams Figure 4 19 and Figure 4 20 on page 4 21 show a single channel interpolation by 2 filter with a parallel architecture Figure 4 19 Single Channel Interpolation by 2 Parallel MCV Single Cycle ast sink valid Control clk PLILEPLE LI LILI LI LI LILLE LI LI LE LI LI LE LT LIL n eset n ast sink ready eo 1 1 Lh LI tL 1 ast sink valid l l l J ast_sink_data D y je B Ja 2 B Jo
54. ee Ald eed ve eee ee ae Ee We a eer d ee eee tee 3 1 Using the FIR Compiler Coefficient Generator 3 2 Loading Coefficients from a File 2 3 6 Analyzing the Coefficients sx mures une surtt Rb epe te iced ce nde ed deese qe Race 3 8 Specify the Input and Output Specifications 3 9 Specify the Architecture Specification 22 3 11 Resource Estimates uie iie eee Ree doe edi RI iHe ae dee e Re Cae os Dee e ead eer dee 3 16 rg P n SKS M 3 16 Chapter 4 Functional Description FIR Compiler e e t 4 1 Number Systems and Fixed Point Precision 4 1 Generating or Importing Coefficients 22 4 1 Coetficierit5caling esete seyde kamenangan ee s eee eie ba eder exe sae ue Eee cd a debe doe 4 2 Symmetrical Architecture Selection 2 2 eee 4 3 Symmetrical vete rises Ce vue ERE ead bete 4 3 Coefficient Reloading and Reordering 4 4 Str ct re bosque admettre acce ee gd ets 4 6 Multicycle Variable Structures 22 4 6 Pa
55. ensing manual Figure 1 4 shows the directory structure after you install the FIR Compiler where path is the installation directory for the Quartus II software The default installation directory on Windows is c altera lt version gt and on Linux is opt altera lt version gt Figure 1 4 Directory Structure path Installation directory ip Contains the Altera MegaCore IP Library and third party IP cores altera Contains the Altera MegaCore IP Library common Contains shared components fir compiler Contains the FIR Compiler MegaCore function files C iib Contains encrypted lower level design files Contains the coef seq program which calculates and re orders coefficients for reloading OpenCore Plus Evaluation FIR Compiler User Guide With Altera s free OpenCore Plus evaluation feature you can perform the following actions m Simulate the behavior of a megafunction Altera MegaCore function or AMPP megafunction within your system m Verify the functionality of your design as well as evaluate its size and speed quickly and easily m Generate time limited device programming files for designs that include megafunctions m Program a device and verify your design in hardware You only need to purchase a license for the FIR Compiler when you are completely satisfied with its functionality and performance and want to take your design to production After you purch
56. er it is de asserted FIR Compiler User Guide May 2011 Altera Corporation Chapter 4 Functional Description 4 25 Timing Diagrams The selection of the coefficient set for calculation is also not synchronous to the input data because of the Avalon ST flow controller Once the coef_set signal is set to a particular value it immediately affects the operation of the filter This means that some of the input data already received by the Avalon ST controller will be calculated using the new coefficient set Figure 4 28 Figure 4 28 Multiple Coefficient Set Selection Timing Diagram Due to Avalon ST buffering this and some of the previous This data is calculated data values can also be calculated with coef set1 with coef set1 clk ast_sink_ready ast_sink_data coef_in_clk coef_we coef_in coef_set coef_set_in ast_source_valid ast_source_data a For DSP Builder users a button is available that ties the coef_in_c1k to the clk in the wrapper DSP Builder will not work with more than one clock domain per MegaCore function When loading multiple coefficient sets to identify the coefficient set being loaded the duration of the clock cycle for coef_set_in must be one clock cycle longer than the duration of coef we as shown in Figure 4 29 These timing requirements affect all designs that
57. erify that the device family is the same as you specified in the New Project Wizard 5 Select the top level output file type for your design the wizard supports VHDL and Verilog HDL 6 Specify the top level output file name for your MegaCore function variation and click Next to launch IP Toolbench Figure 2 3 on page 2 4 Parameterize the MegaCore Function To parameterize your MegaCore function variation perform the following steps 1 Click Step 1 Parameterize in IP Toolbench to display the Parameterize FIR Compiler window Use this interface to specify the required parameters for the MegaCore function variation For an example of how to set parameters for the FIR Compiler MegaCore function refer to Chapter 3 Parameter Settings May 2011 Altera Corporation FIR Compiler User Guide 2 4 FIR Compiler User Guide Chapter 2 Getting Started MegaWizard Plug In Manager Flow Figure 2 3 Toolbench Parameterize CAL o j Aboutthis Core X Documentation Step 1 acs Parameterize Step 2 Set Up Simulation o Step 3 2279 Generate FIR EX 2 Click Step 2 Setup Simulation in IP Toolbench to display the Set Up Simulation FIR Compiler page Figure 2 4 Figure 2 4 Set Up Simulation Set Up Simulation FIR Compiler Simulation Model Quartus II Testbench MATLAB Functional Simulation Model Language VHDL iv
58. es Yes Clocks per signed 1 interface and MLAB M9K M512 input 1 to 32for optional global M144K Auto MLAB M9K unsigned clock enable Auto FIR Compiler User Guide May 2011 Altera Corporation Appendix A FIR Compiler Supported Device Structures A 3 Support for HardCopy Series Devices Support for HardCopy Series Devices Preloaded RAM can be used by the other supported device families in tapped delay line for data storage or for coefficient storage in reloadable FIR filters However devices in the HardCopy series of devices HardCopy II HardCopy M HardCopy IV E and HardCopy IV GX do not support preloaded RAM elements Preloaded RAM is used by the other devices if you select M512 or M4K for data storage or if you select Auto the Quartus II software selects M512 or 4 and the memory is automatically preloaded with zeros Preloading cannot be done for HardCopy devices For HardCopy devices you must flush the memory by preceding your real data with n zeros when loading the data into memory and then discard the corresponding n outputs The following formula describes the required number of preloaded zeroes n number of channels x number of coefficients Preloaded RAM may also be used by the other device families if you select M512 or for the coefficient storage of reloadable FIR filters This RAM cannot be preloaded in HardCopy devices and you must implement the logic to initialize
59. f Response Input Number System Signed Binary v Input Bit Width 8 lv r Output Specification Full Resolution Bit Width is 21 Based on Method Actual Coefficients v Output Number System Full Resolution v 80 Frequency 0 1 0 2 Frequency Response Time Response amp Coefficient Values Coefficients Scaling Auto Bitwiatn 12 r Architecture Specification SS 3 Simmene Structure T f Device el NEED EAN Resource Utilization esti Throughput Fully Streaming Logic Cells 4170 T Structure Distributed Arithmetic Fully Parallel Filter x M512 0 ARIANE EEE every 1 clock periods 0 Pipeline Level 1 v MRAM 2 new output data is generated i every clock period M144K 0 Data Storage Logic Cells v ti MLAB 1 E T Multipliers 0 Coefficient Storage Logic Cells zoefficients Reload Use Single Clo 3 Warning Force non symmetric structure is always set for coefficient sets with unequal number of coefficients i Warning Coefficients reload is enabled only when coefficient storage is setto M512 or M4k Warning Structure Distributed Arithmetic Fully Serial Filter requires Input Bit Width to be greater or equal to 4 33 Mtarnin e Mulinliar innlaxranntation ic nunnartad only for cticturo Confficinnt 5 Multi Cela
60. ficient Set Edit Coefficient Set Remove Coefficient Set Single Rate LLow Pass Set dj Low Pass Set 2 Add global clack enable pin Plot Option FixedfFloating Coefficients iv Dark Background rInput Specification Number of Input Channels 1 iv Input Number System Signed Binary iv Output Specification Full Resolution Bit Width is 27 Based on Method Bit Width Only Output Number System Floating Coeff Response Fixed Coeff Response Ful Resolution v Frequency 01 0 2 Frequency Response Time Response amp Coefficient Values Coefficients Scaling Auto Bitwiath 12 vl Architecture Specification Device Famiy Sram FORCEMENT Resource Utilization esti Throughput Fully Streaming Logic Cells 4170 Structure Distributed Arithmetic Fully Parallel Filter M512 0 M RAM M144K Data Storage Logic Cells Multiplier Implementation Cell MLAB Multipliers Coefficient Storage Logic Cells coefficients Reload Use Single Clock Warning Force non symmetric structure is always set for coefficient sets with unequal number of coefficients 3 Warning Coefficients reload is enabled only when coefficient storage is setto M512 or M4K Warning Structure Distributed Arithmetic Fully Serial Filter requires Input Bit Width to be greater or equal to 4 PS Se Es Dese
61. gure 3 2 Coefficients Generator Dialog Box Showing Default Low Pass Filter Parameters Coefficients Generator Dialog Floating Coefficient Set Rate Specification Coefficients Time Value 1 0 0176663 la 2 0 013227 3 0 0 4 0 0149911 5 0 0227152 6 0 0172976 7 0 0 8 00204448 9 0 0318046 10 0 0249882 11 0 0 12 0 0321283 Name Low Pass Set Frequency Response 40 60 80 Frequency Floating Caeff Response Single Rate Filter Type Low Pass Coefficients 37 Cutoff Freq 1 1 25E6 0 1 0 2 0 3 0 4 0 5 Window Rectangular Sample Rate 1 0E7 Excess Bandwidth Imported Coefficient Set 2 To generate the coefficients for a simple parallel filter use the Coefficients Generator dialog box to make the settings listed in Table 3 1 Table 3 1 Coefficients Generator Parameter Settings for a Simple Parallel Filter Parameter Value Rate Specification Single Rate Filter Type Band Pass Coefficients 77 Cutoff Freq 1 5e 006 Window Type Hamming Sample Rate 50e 006 Cutoff Freq 2 10e 006 May 2011 Altera Corporation FIR Compiler User Guide Chapter 3 Parameter Settings Specifying the Coefficients 3 After making your settings click Apply The dialog box displays the frequency response of the filter in blue and also displays a list of the actual coefficie
62. he waveform window shows the design signals for analysis For more information refer to the Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook Compile the Design and Program a Device May 2011 You can use the Quartus II software to compile your design After you have compiled your design program your targeted Altera device and verify your design in hardware For instructions on compiling and programming your design and more information about the MegaWizard Plug In Manager flow refer to the Quartus II Help Altera Corporation FIR Compiler User Guide 2 10 Chapter 2 Getting Started MegaWizard Plug In Manager Flow FIR Compiler User Guide May 2011 Altera Corporation 3 Parameter Settings JN OTERA This chapter gives an example of how to parameterize a FIR Compiler MegaCore function and describes the available parameters The Parameterize FIR Compiler pages provide the same options whether they have been opened from the DSP Builder or MegaWizard Plug In Manager flow For information about opening the parameterization pages refer to Design Flows on page 2 1 57 The user interface only allows you to select legal combinations of parameters and warns you of any invalid configurations Specifying the Coefficients A FIR filter is defined by its coefficients The FIR Compiler provides the following options for obtaining coefficients You can use the FIR Compiler to genera
63. ia GX devices May 2007 Added symmetric interpolation support Preliminary Arria GX support Full support for Stratix GX and HardCopy II devices December 2006 Preliminary support for Cyclones 111 December 2006 Preliminary support for Stratix III Updated description for Avalon Streaming interfaces Added half band decimator filter support Minor updates throughout the user guide April 2006 Updated the performance information Minor updates throughout the user guide May 2011 Altera Corporation FIR Compiler User Guide Info 2 Additional Information How to Contact Altera Date Version Changes Made October 2005 3 3 0 Updated features and release information Added information to support new features Preliminary support for Stratix GX and HardCopy II devices Updated screenshots Updated many timing diagrams in Chapter 3 Updated screenshots Updated system requirements Updated release information and device family support tables Updated the features Added OpenCore Plus description Added DSP Builder support information Updated the performance information Enhancements include support for Cyclone 1 devices DSP Builder ready December 2004 3 2 0 June 2004 3 1 0 How to Contact Altera For the most up to date information about Altera products refer to the following table Contact Contact 1 Method Address Technical support
64. ice resources used to implement the multiplier You can select Logic Cells DSP Blocks or Auto If you select Auto the Quartus II software turns on the DSP Block Balancing logic option Using embedded DSP blocks results in a smaller and faster design in a device with enough DSP blocks for all multipliers The most efficient use of DSP block is for 9x9 in groups of 8 or 18x18 in groups of 4 multipliers Force Non Symmetric Structure If you want to create a design that uses both symmetric and non symmetric coefficients turn on this option Non symmetric architectures may use more resources Coefficients Reload Turn on this option to allow coefficient reloading Pipeline Level When you turn on this option FIR Compiler creates a higher performance filter that uses more device resources Use Single Clock Use this option when creating designs with DSP Builder This option is only available when Coefficients Reload is on and M512 MLAB or is specified in Coefficient Storage This option ties the coe c1k in and clk signals together Note to Table 3 4 1 When the input data is unsigned the input data bit width should be greater than or equal to one When the input data is signed the input data bit width should be greater than or equal to two FIR Compiler User Guide May 2011 Altera Corporation Chapter 3 Parameter Settings 3 13 Specify the Architecture Specification Table
65. ion marks indicate references to sections within a document and titles of Quartus Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input Active low signals are denoted by suffix n Example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI 1 2 3 and a b c and so on Numbered steps indicate a list of items when the sequence of the items is important such as the steps listed in a procedure Hu Bullets indicate a list of items when the sequence of the items is not important 57 The hand points to information that requires special attention A caution calls attention to a condition or possible situation that can damage or CAUTION destroy the product or your work A warning calls attention to a condition or possible situation that can cause you WARNING injury The angled arrow instructs you to press the enter key UM The feet direct you to more information about a particular topic May 2011 Altera Corporation FIR Compiler User Guide adn Additional Information Typographic Conventions FIR Co
66. lick Open Your coefficient file should have each coefficient on a separate line and no carriage returns at the end of the file You can use floating point or fixed point numbers as well as scientific notation Do not insert additional carriage returns at the end of the file The FIR Compiler interprets each carriage return as an extra coefficient with the value of the most recent past coefficient The file should have a minimum of five non zero coefficients 3 Click OK to import your coefficient set May 2011 Altera Corporation FIR Compiler User Guide 3 8 Chapter 3 Parameter Settings Analyzing the Coefficients Analyzing the Coefficients FIR Compiler User Guide The FIR Compiler contains a coefficient analysis tool which you can use to create sets of coefficients and perform actions on each set Some actions such as scaling apply to all sets Other actions such as recreating reloading or deleting apply to the set you are currently viewing The FIR Compiler supports up to 16 sets of coefficients You can switch between sets using the coefficient tabs in the Parameterize FIR Compiler page The coefficient sets are numbered for example Low Pass Set 1 Low Pass Set 2 and so on When you select a set the frequency response of the floating point coefficients is displayed in blue and the frequency response of the fixed point coefficients in green You can also view the actual coefficient values by clicking the
67. mpiler User Guide May 2011 Altera Corporation
68. n the Avalon ST input FIFO Otherwise the FIR processing continues ast sink data Input Sample input data ast sink sop Input Marks the start of the incoming sample group The start of packet SOP is interpreted as a sample from channel 0 ast sink eop Input Marks the end of the incoming sample group If there is data associated with N channels the end of packet EOP must be high when the sample belonging to the last channel that is channel N 1 is presented at the data input ast sink error Input Error signal indicating Avalon ST protocol violations on the sink side m 00 No error m 01 Missing SOP m 10 Missing EOP m 11 Unexpected EOP Other types of errors are also marked as 11 ast source ready Input Asserted by the downstream module if it is able to accept data ast source valid Output Asserted by the FIR filter when there is valid data to output FIR Compiler User Guide May 2011 Altera Corporation Chapter 4 Functional Description 4 17 Timing Diagrams Table 4 3 F R Compiler Signals Part 2 of 2 ast source channel Output Indicates the index of the channel whose result is presented at the data output The width of this signal log number of channels ast source data Output Filter output The data width depends on the parameter settings ast source sop Output Marks the start of the outgoing FIR filter result group If 1 a result corresponding to channel 0 is output ast source
69. nd M512 M4K MLAB or M9K is specified in Coefficient Storage This option ties the coe c1k in and clk signals together Note to Table 3 6 1 The bit width of input data should divide evenly by the number of serial units and result of division must be greater than or equal to four Table 3 7 Fully Parallel Filter Architecture Note 1 Parameters Description Data Storage Specifies the device resources used for data storage You can select Logic Cells or Auto If you select Auto the Quartus 11 software may store data in logic cells or memory depending on the resources in the selected device the size of the data storage and the number of input channels Coefficient Storage Specifies the device resources used for coefficient storage You can select Logic Cells M512 MLAB or Auto If you select Auto the Quartus Il software automatically selects the most appropriate memory block size for the selected device The option list changes depending on which device you select Selecting embedded memory reduces logic cell usage and may increase the speed of the filter Force Non Symmetric Structure If you want to create a design that uses both symmetric and non symmetric coefficients turn on this option Non symmetric architectures may use more resources This option is available when coefficients are stored in the embedded memory Coefficient Reload If you want to change coefficients turn on this
70. nded pipelining that generate an output for every clock cycle Altera recommends that you use memory blocks to reduce the area The FIR filter typically runs at a higher fmax if the following constraints are set set global assignment name PHYSICAL SYNTHESIS COMBO LOGIC ON set global assignment name PHYSICAL SYNTHESIS REGISTER RETIMING ON Altera Corporation Standard Fit highest effort is recommended for the fitter settings in the Quartus II software to achieve optimum synthesis results To enable the decimation half band optimized architecture data storage and coefficient storage should be set to either Auto or one of the available block memories Then select the filter tap value to be an odd number The coefficient set should be symmetric and every other coefficient value should be 0 To enable the symmetric interpolation optimized architecture data storage and coefficient storage should be set to either Auto or one of the available block memories The number of taps should be an odd value Currently only even symmetry is supported FIR Compiler User Guide 3 18 Chapter 3 Parameter Settings Filter Design Tips FIR Compiler User Guide May 2011 Altera Corporation 4 Functional Description ANU S RYA FIR Compiler The FIR Compiler has an interactive wizard driven interface that allows you to easily create custom FIR filters The wizard outputs IP functional simulation model files fo
71. nt values Figure 3 3 Figure 3 3 Parallel FIR Filter Coefficient Parameters for Band Pass Filter Coefficients Generator Dialog t3 Coefficients Frequency Response Time Value 1 2 8904E 4 Floating Coeff Response 2 0 00110601 a aun 3 0 00113157 4 8 24765 5 5 0 00154753 20 6 0 001 70926 7 4 13428E 4 40 8 5 80872E 4 8 5 18339 5 60 10 7 85448E 4 11 0 00107188 Ez ZU PANAN MERI Low Pass Set Frequency 0 1 0 2 0 3 0 4 0 5 Floating Coefficient Set Rate Specification Single Rate vl tor Filter Type Band Pass vl Window Type Hamming iv Coeficients 7T Sample Rate 5 0E7 Cutoff Freq 1 5 0E6 1 0E7 Excess Bandwidth O Imported Coefficient Set 4 To generate floating point coefficients for interpolation or decimation rate filters select Interpolation or Decimation and the required Factor from the Rate Specification drop down boxes When you click Auto Generate IP Toolbench generates coefficients for a low pass filter with a cutoff frequency based on the specified rate Figure 3 4 on page 3 5 shows a decimation filter The cut off frequency is 4 of the sampling rate and results in a half band coefficient set For an explanation of interpolation and decimation refer to Interpolation and Decimation on page 4 8 FIR Compiler User Guide May 2011 Altera Corporation Chapter 3 Parameter Set
72. ntation Comparison Note 1 Clock Cycles to Device Implementation Compute Result DSP processor 1 MAC 120 FPGA 1 serial filter 12 1 parallel filter 1 Note to Table 1 1 1 If you use the FIR Compiler to create a filter you can also implement a variable filter in a FPGA that uses from 1 to 120 MACs and 120 to 1 clock cycles The Altera FIR Compiler speeds the design cycle by m Generating the coefficients needed to design custom FIR filters m Generating bit accurate and clock cycle accurate FIR filter models also known as bit true models in the Verilog HDL and VHDL languages and in the MATLAB environment May 2011 Altera Corporation Chapter 1 About the FIR Compiler 1 3 Features m Automatically generating the code required for the Quartus II software to synthesize high speed area efficient FIR filters of various architectures m Generating a VHDL testbench for all architectures Figure 1 3 compares the design cycle using a FIR Compiler with a traditional implementation Figure 1 3 Design Cycle Comparison Traditional Flow FIR Compiler Flow Define amp Design Architectural Define amp Design Architectural Blocks Blocks FIR Filter Design 1 Day Determine Behavioral Characteristics of FIR Filter Calculate Filter Coefficients MATLAB Determine Hardware Filter Architecture Design Structural or Synthesizable FIR Filter Synthesize amp Place amp Route Area Speed Tradeoff
73. oach produces coefficient values with the maximum signal to noise ratio m Auto with a power of 2 With this approach the FIR Compiler selects the largest power of two scaling factor that can represent the largest number within a particular number of bits of resolution Multiplying all of the coefficients by a particular gain factor is the same as adding a gain factor before the FIR filter In this case applying a power of two scaling factor makes it relatively easy to remove the gain factor by shifting a binary decimal point m Manual The FIR Compiler lets you manually scale the coefficient values by a specified gain factor m Signed binary fractional You can specify how many digits to use on either side of the decimal point supported in the variable architecture only m None The FIR Compiler can read in pre scaled integer values for the coefficients and not apply scaling factors May 2011 Altera Corporation Chapter 4 Functional Description 4 3 FIR Compiler May 2011 Symmetrical Architecture Selection Many FIR filters have symmetrical coefficient values The FIR Compiler examines the coefficients and automatically determines the filter s symmetry even odd or none After detecting symmetry the wizard selects an optimum algorithm to minimize the amount of computation needed The FIR compiler determines coefficient symmetry after the coefficients are rounded If symmetry is present two data points are added pri
74. on m User selectable output precision via rounding and saturation m DSP Builder ready Release Information Table 1 2 provides information about this release of the Altera FIR Compiler Table 1 2 FIR Compiler Release Information Item Description Version 11 0 Release Date May 2011 Ordering Code IP FIR Product ID 0012 Vendor ID 6AF7 For more information about this release refer to the MegaCore IP Library Release Notes and Errata Altera verifies that the current version of the Quartus II software compiles the previous version of each MegaCore function The MegaCore IP Library Release Notes and Errata report any exceptions to this verification Altera does not verify compilation with MegaCore function versions older than one release FIR Compiler User Guide May 2011 Altera Corporation Chapter 1 About the FIR Compiler Device Family Support Device Family Support 1 5 Table 1 3 defines the device support levels for Altera IP cores Table 1 3 Altera IP Core Device Support Levels FPGA Device Families Preliminary support The core is verified with preliminary timing models for this device family The IPcore meets all functional requirements but might still be undergoing timing analysis for the device family It can be used in production designs with caution HardCopy Device Families HardCopy Companion The IP core is verified with preliminary timing models for the Ha
75. on by 4 pipeline level 2 4 1 528 2 657 66 1 50 290 290 28 Multicycle variable 1 cycle pipeline level 2 2 4 2 543 4 837 92 1 98 280 280 27 Multicycle variable 4 cycle pipeline level 2 2 3 1 182 1 715 578 9 26 283 71 7 FIR Compiler User Guide May 2011 Altera Corporation Chapter 1 About the FIR Compiler 1 7 Performance and Resource Utilization Table 1 5 FIR Compiler Performance Cyclone 111 Devices Part 2 of 2 Memory 5 Processing Combinational Logic Multipliers Tas Throughput Equivalent LUTs Registers Bits M9K 9x9 MHz MSPS GMACs 7 Parallel LE pipeline level 1 2 3 3 416 3 715 208 3 288 288 28 Parallel M9K pipeline level 1 2 5 1 948 2 155 120 030 48 283 283 27 Serial M9K pipeline level 1 2 3 327 462 14 167 8 323 36 3 Notes to Table 1 5 1 GMAC giga multiply accumulates per second 1 giga 1 000 million This FIR filter takes advantage of symmetric coefficients Using EP3C10F256C6 devices 4 Using EP3C16F484C6 devices Using EP3C40F780C6 devices It may be possible to significantly reduce memory utilization by setting a lower target fmax Table 1 6 shows performance figures for Stratix IV devices Table 1 6 FIR Compiler Performance Stratix IV Devices Memory Processing Combinational Logic Multipliers T o
76. ons without having to implement complex control logic The Avalon ST interface supports backpressure which is a flow control mechanism where a sink can signal to a source to stop sending data The sink typically uses backpressure to stop the flow of data when its FIFO buffers are full or when there is congestion on its output When designing a datapath which includes the FIR Compiler MegaCore function you may not need backpressure if you know the downstream components can always receive data You may achieve a higher clock rate by driving the ast source ready signal of the FIR Compiler high and not connecting the ast sink ready signal The coefficient reload related ports and coefficient set selection ports in multi set filters are not Avalon Streaming compliant The Avalon Interface Specifications define parameters which can be used to specify any type of Avalon ST interface Table 4 1 on page 4 14 lists the values of these parameters that are defined for the Avalon ST interfaces used by the FIR Compiler parameters not explicitly listed in the table have undefined values May 2011 Altera Corporation FIR Compiler User Guide 4 14 Chapter 4 Functional Description Avalon Streaming Interface Table 4 1 Avalon ST Interface Parameters Parameter Name Value READY LATENCY 0 BITS PER SYMBOL data width SYMBOLS PER BEAT 1 SYMBOL TYPE signed unsigned ERROR DESCRIPTION 00 No error 01 Missing
77. or a packet error is detected by the Avalon ST controller of the FIR filter the controller is reset and waits for the next valid startofpacket signal It also transmits the received error signal from its data source module error output The error signal only resets the Avalon ST controller and not the design Therefore the output data produced after an error condition may contain invalid data for several cycles It is recommended that a global reset is applied whenever an error message is present in the system Table 4 3 lists the input and output signals for the FIR Compiler MegaCore function Table 4 3 F R Compiler Signals Part 1 of 2 Signal Direction Description clk Input Clock signal used to clock all internal FIR filter registers enable Input Active high clock enable signal This pin appears when the Add global clock enable pin option is selected on the Parameterize FIR Compiler page The Avalon ST registers are NOT connected to this clock enable reset_n Input Synchronous active low reset signal Resets the FIR filter control circuit on the rising edge of clk This signal should last longer than one clock cycle ast_sink_ready Output Asserted by the FIR filter when it is able to accept data in the current clock cycle ast_sink_valid Input Asserted when input data is valid When ast sink validis not asserted the FIR processing is stopped if new data is required and no data is left i
78. or to the multiplication step saving a multiplication operation taking advantage of filter symmetry reduces the number of multipliers by about half The wizard gives you the option to force non symmetrical structures If the symmetry optimized architecture is not available this option is disabled Odd and even filter structures are shown in Figure 4 1 and Figure 4 2 Figure 4 1 Seven Tap Symmetrical FIR Filter Data Out Symmetrical Serial Symmetrical serial filters take an additional clock cycle to perform the FIR computation so the filter can compute the carry Additional logic cells are required for the symmetrical adder resources Because non symmetrical serial FIR filters do not require this resource non symmetrical filters may be smaller and or faster You can use the Resource Estimator in the Architecture Specification area of the Parameterize FIR Compiler page to determine the best solution available Refer to Figure 3 9 on page 3 15 Altera Corporation FIR Compiler User Guide FIR Compiler User Guide Chapter 4 Functional Description FIR Compiler Figure 4 2 Six Tap Symmetrical FIR Filter Data In C Cy Data Out Coefficient Reloading and Reordering All of the FIR Compiler structures allow multiple coefficient sets and the filter can switch between coefficient sets dynamically Additionally while the filter uses one coefficient set you c
79. orted by the FIR Compiler The data storage depends on the specified user settings Cyclone devices do not support M512 or MRAM memory MLAB M9K and M144K are supported by Stratix III and Stratix IV devices only Table A 1 Device Structures Supported by FIR Compiler Part 1 of 2 Multiple Suh Input Bit Flow Data Coefficient Coefficient Symmetric Structure Structure Width Control Storage Storage Sets Coefficient Serial Fixed 4 to 32 Avalon ST Logic cell M512 Logic cell Yes Yes Coefficient interface and M RAM M512 M4K optional global MLAB M9K MLAB M9K clock enable M144K Auto Auto Reloadable 4 to 32 Avalon ST Logic cell M512 M512 Yes Yes Coefficient interface and M RAM M512 optional global MLAB M9K MLAB M9K clock enable M144K Auto Auto Interpolation 4 to 32 Avalon ST Logic cell M512 Logic cell Yes N A Reloadable interface and M RAM M512 Coefficient must optional global MLAB M9K MLAB M9K be in memory clock enable M144K Auto Auto Decimation 4 to 32 Avalon ST Logic cell M512 Logic cell Yes N A Reloadable interface and M RAM M512 Coefficient must optional global MLAB M9K MLAB M9K be in memory clock enable M144K Auto Auto Multibit Fixed 24 Avalon ST Logic cell M512 Logic cell Yes Yes Serial Coefficient number interface and M RAM M512 M4K of serial o
80. ou exit from IP Toolbench FIR Compiler User Guide May 2011 Altera Corporation Chapter 2 Getting Started MegaWizard Plug In Manager Flow 2 1 Table 2 1 Generated Files Part 2 of 2 Note 1 2 Filename variation name Description Quartus II vector file This file provides simulation test vectors to be used for simulating the customized FIR MegaCore function variation with the Quartus II software variation name gt vhd or v A VHDL or Verilog HDL file that defines a VHDL or Verilog HDL top level description of the custom MegaCore function variation Instantiate the entity defined by this file inside of your design Include this file when compiling your design in the Quartus Il software variation name vho or vo A VHDL or Verilog HDL output file that defines the IP functional simulation model variation name hb v A Verilog HDL black box file for the MegaCore function variation Use this file when using a third party EDA tool to synthesize your design variation name coef in mlab txt variation name coef int txt Text files that provides coefficient inputs for the MATLAB testbench model variation name coef n inv hex variation name coef n hex variation name zero hex Memory initialization files in INTEL Hex format These files are required both for simulation with IP functional simulation models and synthesis using the Quartus II software
81. p port This sequence repeats itself continuously at each cycle When the filter output is ready ast source valid goes high and for the first data output ast source sop goes high to mark the start of the packet The ast source channel output shows to which channel that particular output belongs The last channel data is marked with the high value of the ast source eop port Figure 4 17 and Figure 4 18 on page 4 20 demonstrate another single channel single rate filter timing diagram In these diagrams the FIR filter requires input data every three clock cycles and produces one output data every three clock cycles In general multicycle filters when the Clocks to Compute value is greater than one Multibit Serial filters and Serial filters require a new input data every N clock cycles where N represents the following m Foran MCV multicycle filter N is the clocks to compute value m ForaMultibit Serial filter N input data bit width number of serial units m For a Serial filter N input data bit width 1 May 2011 Altera Corporation FIR Compiler User Guide 4 20 Chapter 4 Functional Description Timing Diagrams Figure 4 17 Single Channel Single Rate Serial Multibit Serial MCV Multicycle ast sink valid Control clk TEU CEE E LLL LLL Lii reset_n LL Tl 1 1 1 J 1 1 1 ast sink ready ast sink valid 1 1 1 F 1 il ast_sink_data 0 lo B Hu ast sourc
82. ptional global MLAB M9K MLAB M9K units clock enable M144K Auto Auto Reloadable 24 Avalon ST Logic cell M512 M512 Yes Yes Coefficient number interface and M RAM M512 M4K of serial optional global MLAB M9K MLAB M9K units clock enable M144K Auto Auto Interpolation 24 Avalon ST Logic cell M512 Logic cell Yes N A Reloadable number interface and M RAM M512 Coefficient must of serial optional global MLAB MLAB M9K bein memory units clock enable M144K Auto Auto Decimation 24 Avalon ST Logic cell M512 Logic cell Yes N A Reloadable number interface and M RAM M512 Coefficient must of serial optional global MLAB MLAB M9K bein memory units clock enable M144K Auto Auto May 2011 Altera Corporation FIR Compiler User Guide A 2 Appendix A FIR Compiler Supported Device Structures Supported Device Structures Table A 1 Device Structures Supported by FIR Compiler Part 2 of 2 Multiple Suh Input Bit Flow Data Coefficient Coefficient Symmetric Structure Structure Width Control Storage Storage Sets Coefficient Parallel Fixed 2to 32 for Avalon ST Logic cell Auto Logic cell Yes Yes Coefficient signed 1 interface and M512 M4K to 32 optional global MLAB M9K unsigned clock enable Auto Reloadable 2to 32 for Avalon ST Logic cell Auto M512 M4K Yes Yes
83. r MegaCore Verification MegaCore Verification Before releasing an updated version of the FIR Compiler Altera runs a comprehensive regression test to verify its quality and correctness features and architectures are tested by sweeping all parameter options and verifying that the simulation matches a master functional model Performance and Resource Utilization This section shows typical expected performance for a FIR Compiler MegaCore function with Cyclone III and Stratix IV devices figures are given for a FIR filter with 97 taps 8 bit input data 14 bit coefficients a target fmax set to 1 GHz Cyclone III devices use combinational look up tables LUTs and logic registers Stratix IV devices use combinational adaptive look up tables ALUTs and logic registers The resource and performance data was generated with the source ready signal ast source ready always driven high as described in Avalon Streaming Interface on page 4 13 Table 1 5 shows performance figures for Cyclone III devices Table 1 5 FIR Compiler Performance Cyclone 111 Devices Part 1 of 2 Memory 6 Processing Combinational Logic Multipliers fma Throughput Equivalent LUTs Registers Bits M9K 9x9 MHz MSPS GMACs 1 899 1 331 55 148 31 310 62 6 Multicycle variable 1 cycle decimation by 4 pipeline level 1 2 3 857 1 336 1 158 12 26 281 281 27 Multicycle variable 1 cycle interpolati
84. r a Simulink symbol for the FIR Compiler appears in the MegaCore Functions library of the Altera DSP Builder Blockset in the Simulink library browser You can use the FIR Compiler in the MATLAB Simulink environment by performing the following steps 1 Create a new Simulink model 2 Select the FIR Compiler block from the MegaCore Functions library in the Simulink Library Browser add it to your model and give the block a unique name 3 Double click the FIR Compiler block in your model to display IP Toolbench and click Step 1 Parameterize to parameterize a FIR Compiler MegaCore function variation For an example of how to set parameters for the FIR Compiler block refer to Chapter 3 Parameter Settings 4 Click Step 2 Generate in IP Toolbench to generate your FIR Compiler MegaCore function variation For information about the generated files refer to Table 2 1 on page 2 6 5 Connect your FIR Compiler MegaCore function variation block to the other blocks in your model May 2011 Altera Corporation FIR Compiler User Guide 2 2 Chapter 2 Getting Started MegaWizard Plug In Manager Flow 6 Simulate the FIR Compiler MegaCore function variation in your DSP Builder model For more information about the DSP Builder flow refer to the Using MegaCore Functions chapter in the DSP Builder User Guide La When you are using the DSP Builder flow device selection simulation Quartus compilation and device programming are
85. r use with Verilog HDL and VHDL simulators Number Systems and Fixed Point Precision The FIR Compiler function supports signed or unsigned fixed point numbers from 4 to 32 bits wide in two s complement and signed binary fractional formats The entire filter operates in a single number system The coefficient precision is independent of input data width you can specify the output precision Generating or Importing Coefficients May 2011 You can use the FIR Compiler function to create coefficients or you can create them using another application such as MATLAB save them as an ASCII file and read them into the FIR Compiler Coefficients can be expressed as floating point or integer numbers each one must be listed on a separate line If you specify negative values for the coefficients the FIR Compiler generates a two s complement signed number Figure 4 1 shows the contents of a sample coefficient text file Figure 4 1 Sample Filter Coefficients 3 09453e 005 0 000772299 0 00104106 0 000257845 0 00150377 0 00163125 0 00278506 0 00150377 0 000257845 0 00104106 0 000772299 3 09453e 005 The FIR Compiler automatically creates coefficients with a user specified number of taps for the following filters m Low Pass m High Pass m Band Pass Altera Corporation FIR Compiler User Guide 4 2 FIR Compiler User Guide Chapter 4 Functional Description FIR Compiler m Band Reject m Raised
86. rage Specifies the device resources used for coefficient storage You can select Logic Cells M512 MLAB M9K or Auto If you select Auto the Quartus Il software automatically selects the most appropriate memory block size for the selected device The option list changes depending on which device you select Selecting embedded memory reduces logic cell usage and may increase the speed of the filter Force Non Symmetric Structure If you want to create a design that uses both symmetric and non symmetric coefficients turn on this option Symmetric algorithms require an extra clock cycle per calculation cycle which leads to lower throughput May 2011 Altera Corporation FIR Compiler User Guide 3 14 Chapter 3 Parameter Settings Specify the Architecture Specification Table 3 6 Multibit Serial Filter Architecture Part 2 0f2 Note 1 Parameters Description Coefficient Reload If you want to change coefficients turn on this option This option is available when you choose to store coefficients in embedded memory Selecting this option increases resource usage turns off several optimization schemes and adds additional input ports to the filter Pipeline Level Creates a higher performance filter with a resource usage increase Use Single Clock Use this option when creating designs with DSP Builder This option is only available when Coefficients Reload is selected a
87. rallel Structures ses Ses Pada dente Ve PR Ox Va PICO a Me ane a Vale Wad nak 4 6 Seria l DtFUCEUTOS Soo steal ee Dele o ets 4 7 Multibit Serial Structure ree eter she eee ee S EE ek sure 4 7 Multichannel Structures 24444 22 4 8 May 2011 Altera Corporation FIR Compiler User Guide iv Contents Interpolation and Decimation enn 4 8 Implementation Details for Interpolation and Decimation Structures 4 10 Availability of Interpolation and Decimation Filters 4 11 Half Band Decimation Filters 0 4 12 Symmetric Interpolation Filters ssis eee eaae 4 12 Pipelining i eR EU RR ac Ltd Se Cae om dant de eee ns iun 4 12 Simulatiori O tput s exe sepes eei e P px e ead Ee Vue Wo eae en 4 13 Avalon Streaming Interface 4444444444 en 4 13 Avalon ST Data Transfer Timing 222 4 14 Packet Data Transfers 4 4 15 Signals vege theese heeds eG ie nee pate Sale de are Ned lien sd read 4 16 dTimang Diagrams 3 iat SR HEU PP CI EE ed et diabetes 4 17 Reset and Global Clock Enable Operations
88. rdCopy companion device The IP core meets all functional requirements but might still be undergoing timing analysis for the HardCopy device family It can be used in production designs with caution Final support The IP core is verified with final timing models for this device family The IP core meets all functional and timing requirements for the device family and can be used in production designs HardCopy Compilation The IP core is verified with final timing models for the HardCopy device family The IP core meets all functional and timing requirements for the device family and can be used in production designs Table 1 4 shows the level of support offered by the FIR Compiler to each Altera device family Table 1 4 Device Family Support Device Family Support Arria GX Final Arria II GX Final Arria Il GZ Final Cyclone Final Cyclone Final Cyclone III Final Cyclone III LS Final Cyclone IV GX Final HardCopye HardCopy Compilation HardCopy III HardCopy Compilation HardCopy IV E HardCopy Compilation HardCopy IV GX HardCopy Compilation Stratixe Final Stratix II Final Stratix Il GX Final Stratix IIl Final Stratix IV GT Final Stratix IV GX E Final Stratix V Preliminary Stratix GX Final Other device families No support May 2011 Altera Corporation FIR Compiler User Guide 1 6 Chapter 1 About the FIR Compile
89. re 2 2 FIR Compiler User Guide May 2011 Altera Corporation Chapter 2 Getting Started MegaWizard Plug In Manager Flow Figure 2 2 Selecting the MegaCore Function 2 3 Which megafunction would you like to customize Select a megafunction from the list below 1 Installed Plug Ins Arithmetic Communications 3 DSP Error Detection Correction Filters CIC v9 1 FIR Compiler v9 1 Signal Generation Transforms fi Video and Image Processing f Gates fq 1 0 f Interfaces Sa IPTCL fs JTAG accessible Extensions Memory Compiler fi Storage IP MegaStore E A E mmm meme MegaWizard Plug In Manager page 2a Which device family will vou be Stratix V Y using Which type of output file do you want to create AHDI VHDL C Verilog HDL What name do you want for the output file Browse F AmydesignsMirsmyfilter Return to this page for another create operation Note To compile a project successfully in the Quartus 11 software your design files must be in the project directory in the global user libraries specified in the Options dialog box Tools menu or a user library specified in the User Libraries page of the Settings dialog box Assignments menu Your current user library directories are Cancel Back Next gt Finish 4 V
90. re calculates the filter output in a single clock cycle Parallel filters provide the highest performance and consume the largest area Pipelining a parallel filter allows you to generate filters that run between 120 and 300 MHz at the cost of pipeline latency Figure 4 3 shows the parallel filter block diagram Figure 4 3 Parallel Filter Block Diagram xin D uL xn ape x Te xout Array Multiplier Array Multiplier yout FIR Compiler User Guide May 2011 Altera Corporation Chapter 4 Functional Description 4 7 FIR Compiler Serial Structures A serial structure trades off area for speed The filter processes input data one bit at a time per clock cycle Therefore serial structures require N clock cycles where N is the input data width to calculate an output In the Stratix IV Stratix III Stratix IL Stratix Cyclone III Cyclone IL and Cyclone device families using memory blocks for data storage will result in a significant reduction in area Figure 4 4 shows the serial filter block diagram Figure 4 4 Serial Filter Block Diagram Bit Array Multiplier Bit Array Multiplier Serial Accumulator May 2011 Multibit Serial Structure A multibit serial structure combines several small serial FIR filters in parallel to generate the FIR result This structure
91. rs that have the same coefficients If high speed is not required your design can share one filter which uses fewer resources than two individual filters For example a two channel parallel filter requires two clock cycles to calculate two outputs The resulting hardware would need to run at twice the data rate of an individual filter To minimize the number of logic elements use a distributed serial arithmetic architecture multiple channels and memory blocks for data and coefficient storage Interpolation and Decimation FIR Compiler User Guide You can use the FIR Compiler to interpolate or decimate a signal Interpolation generates extra points in between the original samples decimation removes redundant data points Both operations change the effective sample rate of a signal The outputs from interpolating and decimating filters that have the same input data are likely to be different This difference is because changing the delay between the reset signal and the first non zero input data sample may make the input sample go down a different path of the polyphase filter This means that the input data is multiplied by a different set of coefficients and the filter results are different May 2011 Altera Corporation Chapter 4 Functional Description 4 9 FIR Compiler May 2011 Mathematically when a signal is interpolated zeros are inserted between data points and the data is then filtered to remove spectral components tha
92. sion history for this user guide Date May 2011 Version 11 0 Changes Made Updated support level to final support for Arria 11 GX Arria II GZ Cyclone III LS and Cyclone IV GX devices Updated support level to HardCopy Compilation for HardCopy 111 HardCopy IV E and HardCopy IV GX devices Updated Appendix A FIR Compiler Supported Device Structures to clarify that RAM cannot be preloaded and you must remove the memory initialization files for all HardCopy series devices not just HardCopy II devices December 2010 10 1 Added preliminary support for Arria GZ devices Updated support level to final support for Stratix IV GT devices July 2010 10 0 Added preliminary support for Stratix V devices Clarified that new filter coefficient set must be reordered before being reloaded for all filter structures November 2009 9 1 Maintenance release Preliminary support for Cyclone 111 LS Cyclone IV and HardCopy IV GX devices March 2009 9 0 Added preliminary support for Arria 11 GX November 2008 8 1 Full support for Stratix 1 devices Applied new technical publications style Withdrawn support for UNIX May 2008 8 0 Full support for Cyclone III devices Preliminary support for Stratix IV devices Option to automatically select memory block size for coefficient storage Separate Getting Started and Parameter settings chapters October 2007 7 2 Full support for Arr
93. symbols and makes it is possible to support modules that convey more than one piece of information about each valid cycle Packet data transfers are used for multichannel transfers Two additional signals startofpacket and endofpacket are defined to implement the packet transfer Figure 4 13 shows an example where the channel signal shows to which channel the data sample belongs Figure 4 13 Packet Data Transfer 1 2 3 4 5 6 7 dk XV V NF NV I NV I T NV T N ready valid J J startofpacket endofpacket channel 1 0 EEEEEEy o0 EE error 1 0 ES oo Co SE SN data ESS NS gt SN May 2011 57 The channel input signal is not used in the FIR Compiler interface Altera Corporation FIR Compiler User Guide 4 16 Signals Chapter 4 Functional Description Signals The data transfer in Figure 4 13 occurs on cycles 1 2 4 and five when both ready and valid are asserted During cycle 1 startofpacket is asserted and the first data is transferred During cycle 5 endofpacket is asserted indicating that this is the end of the packet The channel signal indicates the channel index associated with the data For example on cycle 1 the data D associated with channel 0 is available The error signal stays at value 00 during a normal operation Whenever a value other than 00 is received from the data source as in Figure 4 11
94. t were not present in the original signal Figure 4 7 Figure 4 7 Signal Interpolation Input EX Output ot ol tw Ie om After Zero Stuffing Leet After Low Pass Filtering To decimate a signal a low pass filter is applied which removes spectral components that will not be present at the low sample rate After filtering appropriate sample values are taken Figure 4 8 Figure 4 8 Signal Decimation Input gt Ux M gt Output tk 11 Filtered Data Decimated Data The FIR Compiler generates interpolation and decimation filters by combining high and low level optimization techniques Using the high level optimization technique the FIR Compiler processes the data from a polyphase decomposed filter The polyphase decomposition breaks a single filter into several smaller filters which results in the following m When using an interpolation filter zero stuffed data does not need to be computed potentially saving resources Figure 4 9 on page 4 10 m When using a decimation filter output data which is discarded during downsampling is never computed again potentially saving resources Figure 4 10 on page 4 11 Using the low level optimization technique the polyphase decomposed filter is implemented using a multichannel multiple coefficient set structure with an appropriate wrapper Altera Corporation FIR Compiler User Guide 4 10 Chapter
95. te coefficients The coefficient generator supports single rate interpolation and decimation rate specification filter types For information about generating coefficients for these filter types refer to Using the FIR Compiler Coefficient Generator on page 3 2 m You can load coefficients from a file For example you can create the coefficients in another application such as MATLAB SPW or a user created program save them to a file and import them into the FIR Compiler For more information refer to Loading Coefficients from a File on page 3 6 Figure 3 1 on page 3 2 shows the Parameterize FIR Compiler page You can click New Coefficient Set on this page to define or load new coefficients Alternatively or you can click Edit Coefficient Set to edit the default coefficient set or Remove Coefficient Set to clear the currently loaded coefficients May 2011 Altera Corporation FIR Compiler User Guide 3 2 Figure 3 1 Toolbench Parameterize Page Chapter 3 Parameter Settings Specifying the Coefficients r Coefficients Specification Low Pass Set 1 New Coefficient Set Edit Coefficient Set Single Rate Low Pass Set 1 Plot Option FixedfFloating Coefficients iv Dark Background Floating Coeff Response Fixed Coeff Response 80 Frequency 0 1 0 2 Frequency Response Time Response amp Coefficient Values Coefficients Scaling Auto Bit Width 8
96. tings Specifying the Coefficients Figure 3 4 ow Pass Filter Results for an Interpolation Filter 3 5 Floating Coeff Response Coefficients Frequency Response Time Value 1 0 0167338 l 2 0 0 3 OdB 3 0 0187044 E 4 0 0 28 5 0 0211985 40 6 0 0 7 0 0244618 m 8 9 80 Name Low Pass Set Coefficients Generator Dialog E3 0 3 0 4 0 5 Floating Coefficient Set f e Specification v Auto Generate Excess Bandwidth Window Type Decimation v Factor 2 Filter Type Low Pass Coefficients 39 Cutoff Freq 1 1 25E7 Sample Rate Rectangular 5 0E7 Imported Coefficient Set 5 Click OK when you have finished making the parameter settings The Parameterize FIR Compiler page Figure 3 1 on page 3 2 is updated to display the frequency response of the floating coefficients in blue and the frequency response of the fixed coefficients in green You can click the Time Response amp Coefficient Values tab to list the coefficients as shown in Figure 3 5 on page 3 6 May 2011 Altera Corporation FIR Compiler User Guide 3 6 Chapter 3 Parameter Settings Specifying the Coefficients Figure 3 5 Toolbench Parameterize Page Time Response and Coefficient Values Tab r Coefficients Specification Low Pass Set 2 r
97. tion factor Simulating in Third Party Simulation Tools Using NativeLink You can perform a simulation in a third party simulation tool from within the Quartus II software using NativeLink The Tcl script file variation name nativelink tcl can be used to assign default NativeLink testbench settings to the Quartus II project To perform a simulation in the Quartus II software using NativeLink perform the following steps 1 Create a custom MegaCore function variation as described earlier in this chapter but ensure you specify your variation name to match the Quartus II project name 2 Verify that the absolute path to your third party EDA tool is set in the Options page under the Tools menu in the Quartus II software On the Processing menu point to Start and click Start Analysis amp Elaboration 4 On the Tools menu click Tcl scripts In the Tcl Scripts dialog box select variation name nativelink tcl and click Run Check for a message confirming that the Tcl script was successfully loaded 5 On the Assignments menu click Settings expand EDA Tool Settings and select Simulation Select a simulator under Tool name then in NativeLink Settings select Compile test bench and click Test Benches 6 On the Tools menu point to EDA Simulation Tool and click Run EDA RTL Simulation The Quartus II software selects the simulator and compiles the Altera libraries design files and testbenches The testbench runs and t
98. tion successful Cancel Generation Report FIR Compiler A MegaCore function variation file which defines a VHDL top level description of the custom MegaCore function Instantiate the entity defined by this file inside of your design Include this file when compiling your design in the Quartus Il software Table 2 1 describes the IP Toolbench generated files and other files that may be in your project directory The names and types of files specified in the report vary based on whether you created your design with VHDL or Verilog HDL Table 2 1 Generated Files Part 1 of 2 Note 1 2 Filename entity name vhd Description A VHDL wrapper file for the Avalon ST interface variation name gt bsf A Quartus II block symbol file for the MegaCore function variation You can use this file in the Quartus II block diagram editor lt variation name gt cmp A VHDL component declaration file for the MegaCore function variation Add the contents of this file to any VHDL architecture that instantiates the MegaCore function variation name gt html A MegaCore function report file in hypertext markup language format variation name gt qip A single Quartus II IP file is generated that contains all of the assignments and other information required to process your MegaCore function variation in the Quartus Il compiler You are prompted to add this file to the current Quartus II project when y
99. tional simulation models generated by IP Toolbench The IP functional simulation model is the vo or vho file located in your design directory generated as specified in Step 1 on page 2 3 For more information about IP functional simulation models refer to the Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook Simulating in ModelSim A Tel script variation name msim tcl is also generated which can be used to load the VHDL testbench into the ModelSim simulator This script uses the file variation name input txt to provide input data to the FIR filter The output from the simulation is stored in a file variation name output txt May 2011 Altera Corporation Chapter 2 Getting Started 2 9 MegaWizard Plug In Manager Flow Simulating in MATLAB To simulate in a MATLAB environment run the variation name model m testbench m script which also is located in your design directory This script also uses the file variation name input txt to provide input data The output from the MATLAB simulation is stored in the file variation name model output txt For MCV decimation filters the variation name model output full txt file is generated to display all the phases of the filter You can compare this file with the variation name output txt file to understand which phase the output belongs For all other architectures decimation filters provide the Nth phase where N is the decima
100. torage Logic Cells x Coefficients Reload Use Single Clock An input data is processed every 1 clock periods Loading Coefficients from a File To load a coefficient set from a file perform the following steps 1 Click New Coefficient Set in the Parameterize FIR Compiler page Figure 3 1 on page 3 2 then select Imported Coefficient Set in the Coefficients Generator dialog box Figure 3 6 on page 3 7 FIR Compiler User Guide May 2011 Altera Corporation Chapter 3 Parameter Settings 3 1 Specifying the Coefficients Figure 3 6 Importing a Coefficient Set Coefficients Generator Dialog Coefficients Frequency Response Time Value 1 0 0176662 Floating Coeff Response 2 0 013227 3 0 0 0dB 4 0 0149911 5 0 0227152 20 6 0 0172976 T 0 0 40 8 0 0204448 8 0 0318046 60 10 0 0249882 11 0 0 12 00321283 80 Name Low Pass Set Frequency 0 1 0 2 0 3 0 4 0 5 M O Floating Coefficient Set Imparted Coefficient Set File D lalteraiqdesigns61 fir_filterimy_fir_coefficients t Browse Note to Figure 3 6 1 The radio buttons for the Floating Coefficient Set and Imported Coefficient Set parameters are linked together selecting one disables the other 2 Browse in the file system for the file you want to use and c
101. ut and output specification follow these tips m Truncating from the MSB reduces logic resources more than saturation m The Number of Input Channels option is useful for designs such as modulators and demodulators which have I and Q channels If you are designing this type of application select 2 input channels This tutorial uses the default settings Specify the Architecture Specification You are now ready to select the architecture parameters from the lower half of the Parameterize FIR Compiler page The FIR Compiler supports several filter structures including Variable Fixed coefficient Multicycle Distributed arithmetic Fully Parallel Filter Distributed arithmetic Fully Serial Filter Distributed arithmetic Multibit Serial Filter For maximum clock speed select the Distributed Arithmetic Fully Serial Filter structure For Stratix Stratix II Stratix III or Stratix IV devices using smaller memory resources for coefficient and data storage is faster than using larger memory resources For maximum throughput select the Distributed Arithmetic Fully Parallel structure When reloading coefficients a multicycle variable FIR filter structure has a short reloading time compared to a fixed FIR filter Additionally smaller memory blocks have a shorter reloading time than larger memory blocks Table 3 3 describes the relative trade offs for the different architecture options Table 3 3 Architecture Trade Offs
102. y digits with full precision If you use signed binary fractional notation the FIR Compiler uses the fractional number that most closely matches the original number for the number of bits of precision you select For this tutorial select Auto for Coefficients Scaling and 12 for the Coefficient Bit Width Auto scaling without the power of two option provides the maximum signal to noise ratio All other scaling factors such as Signed Binary Fractional can result in a loss of effective bits that is where each effective bit provides 6dB of SNR May 2011 Altera Corporation Chapter 3 Parameter Settings 3 9 Specify the Input and Output Specifications Figure 3 7 shows the result after you have made the selections Note that the side lobes of the fixed point frequency response decrease when you change the bit width from 8 the default to 12 Figure 3 7 Analyzing the Coefficients Parameterize FIR Compiler BAF r Coefficients Specification Low Pass Set 2 Rate Specification p New Coefficient Set Edit Coefficient Set Remove Coefficient Set Single Rate v e Low Pass Set 1 Low Pass Set 2 _ C Add global clock enable pin Plot Option Fixed Floating Coefficients v Dark Background Input Specification Number of Input Channels 1 iv Floating Coeff Response Fixed Coef

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