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ALTERA MegaCore Function user manual

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1. pas 033 Das 033 Das pss 4 034 081 Da4 034 pet pss 082 pas pss W jJ De2J pas pss DA2 D36 W 083 pa2 036 pa2 se 537 084 pat 87 W 08 DAT 087 DAO D38 085 Dao 38 W Das 38 sas D39 sas f 039 W y Dee sas 089 SA4 D40 W pee SA4 040 186 Sa 040 041 Wy 087 y sas 24 ps 543 4 sa 042 Des sw y 042 pes sa 042 SA1 D43 1 089 y sai Das 089 pas SAO D44 9 Sao f 044 y 090 Sao y Daa TH 1055 1 bot 055 W y psy 5 TLO 046 Tto D46 D92 Tto 146 po 047 1 044 po f pz 57 044 1 564 8 044 564 o bas 077 123 D77 peo v7 D31 078 V D31 028 D31 D78 032 D79 W NEN vo o D32 079 21 WI 1 Wf 1 Pe June 2012 Altera Corporation 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide 3 14 Chapter 3 Functional Description MAC and PHY Functional Description RX Datapath The RX MAC receives Ethernet frames from the PHY and forwards the payload w
2. Simulation Monitor at time 98945000 am locked fffff all locked 1 lanes deskewed framing error 80020 bip error fffff deskew_failure 0 pma_rx_ready 1 pma_tx_ready Number of packets sent 110 d Simulation Monitor at time 104065000 am locked fffff all locked 1 lanes deskewed framing error a2000 bip error fffff H deskew failure 0 pma rx 1 tx ready Number of packets sent 140 FO SSS See SE See Seis Simulation Monitor at time 109185000 am locked fffff all locked 1 lanes deskewed H framing error 82020 bip error cefef deskew_failure 0 pma_rx_ready 1 pma_tx_ready Number of packets sent 168 oS SSS Se Semone Simulation Monitor at time 114305000 am locked fffff all locked 1 lanes deskewed H framing error 02008 bip error fffff H deskew failure 0 pma rx 1 tx ready Number of packets sent 195 ME Simulation Monitor at time 119425000 am locked fffff all locked 1 lanes deskewed framing_error 000a0 bip_error ffcff deskew fa
3. Four unusable words In Figure 3 13 Example A shows the minimum sized packet of eight words Example B shows an 11 word packet which is the worst case for bandwidth utilization Assuming another packet is waiting for transmission the effective ingress bandwidth is reduced by 20 and 26 respectively Running the MAC portion of the logic slightly faster than is required can mitigate this loss of bandwidth Additional increases in the MAC frequency can provide further mitigation although doing so makes timing closure more difficult Order of Transmission Bytes are transmitted starting with the preamble and ending with the FCS in accordance with the IEEE 802 3 standard Transmit frames received from the client on the Avalon ST interface are big endian Frames transmitted on the XGMII CGMII are little endian the MAC TX transmits frames on this interface beginning with the lease significant byte Table 3 3 describes the byte order on the Avalon ST interface Table 3 3 Byte Order on the Avalon ST Interface Lanes Destination Address DA Type 1 Source Address SA Length Data D Octet 514 3 2 1 0 5 4 3 211 0 1 0 00 NN c Bit S In m Je fo S Ia If le S lt m N T co m N T co co YK 0 l wo o o io IS ch Pe iS ES NG um qm ee SS 21
4. Signal Name Direction Description TX Transmission Mode Configuration Ports mac_tx_arst_ST Input pcs tx arst ST Input Refer to Resets on page 3 30 pma arst ST Input clk ref Input Refer to Clocks on page 3 29 tx dataout 9 0 Output Bina PHY Serial Data Interface Refer to Clocks on page 3 29 and TX Data clk din Input Bus without Adapters Custom Streaming Interface on page 3 9 din lt w gt 64 1 0 Input din start lt w gt 1 0 Input Refer to TX Data Bus without Adapters din end pos lt w gt 8 1 0 Input Custom Streaming Interface on page 3 9 din_ack Output clk_ status Input Refer to Clocks on page 3 29 status addr 15 0 Input status read Input status write Input Refer to Control and Status Interface on status writedata 31 0 Input page 3 28 status readdata 31 0 Output status readdata valid Output pause insert tx Input pause insert time 15 0 Input pause insert mcast Input pause insert dst 47 0 Input fe pause insert src 47 0 Input pause match to tx Input pause time to tx 15 0 Input remote fault to tx Input Refer to Link Fault Signaling Interface on local fault to tx Input page 3 24 June 2012 Altera Corporation 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide 3 32 Chapter 3 Functional Description MAC and PHY Functional Description Table 3 14 IP Cores Without Adapters Configuration Ports
5. Note to Table 3 3 1 Destination Address 40 type bit broadcast multicast bit 2 Destination Address 41 Locally administrated address bit June 2012 Altera Corporation 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide Chapter 3 Functional Description MAC and PHY Functional Description 3 13 For example the destination MAC address includes the following six octets AC DE 48 00 00 80 the first octet transmitted octet 0 of the MAC address described in 802 3 is AC and the last octet transmitted octet 7 of the MAC address is 80 The first bit transmitted is the low order bit of AC a zero The last bit transmitted is the high order bit of 80 a one Figure 3 14 further illustrates how the octets of the client frame are transferred over the TX datapath As Table 3 3 and Figure 3 14 illustrate OxAC is driven on DA5 47 40 and 0x80 is driven DAO 7 0 Figure 3 14 Octet Transmission on the Avalon ST Signals clk_txmac l8 tx data 319 312 18 tx data 311 304 18 tx data 303 296 18 tx data 295 288 l8 tx data 287 280 l8 tx data 279 272 l8 tx data 271 264 18 tx data 263 256 l8 tx data 319 312 l8 tx data 311 304 18 tx data 303 296 18 tx data 295 288 l8 tx data 287 280 l8 tx data 279 272 l8 tx data 271 264 18 tx data 263 256 I8 tx data 23 16 18 tx data 15 8 18 tx data 7 0 l8 tx startofpacket l8 tx endofpacket l8 tx empty 5 0
6. n rx empty v 0 lt n gt _rx_startofpacket RX n rx endofpacket RX Client lt gt nc error MAC n rx ready n rx valid n tx fcs valid e lt n gt _rx_fcs_error e Note to Figure 3 16 1 m 4 for the 40GbE IP core and lt n gt 8 for the 100GbE IP core Lane variables are denoted by lt u gt and lt v gt Table 3 4 describes the signals in RX interface Table 3 4 RX Interface with Adapters Part1 of 2 Direction Description l n rx data u 0 Output RX data Indicates the number of empty bytes in a packet if l n rx empty lt gt 0 Output l n rx endofpacket is asserted starting from the least significant byte LSB When asserted indicates the start of a packet The packet starts on l n rx startofpacket Output the MSB l lt n gt _rx_endofpacket Output When asserted indicates the end of packet l n rx error Output When asserted indicates an error condition len rx ready Input Unused 40 and 100 Gbps Ethernet MAC and PHY June 2012 Altera Corporation MegaCore Function User Guide Chapter 3 Functional Description MAC and PHY Functional Description Table 3 4 RX Interface with Adapters Part 2 of 2 3 17 Name Direction Description When asserted indicates that RX data is valid Only valid between l n rx valid Output the 1 n rx
7. rx 1100 3300 6500 151600 17 alt e100 adapter adapter bxadapter tx 400 3200 4900 0 0 alt_e100 e100 51700 53600 80000 149500 17 alt_e100_mac mac 17400 23300 37200 110600 11 alt_e100_mac_csr mac_csr 4000 5600 9400 0 0 alt_e100_mac_rx mac_rx 5400 7400 12400 110600 11 alt_e100_mac_tx mac_tx 7900 10300 15400 0 0 alt_e100_phy phy 34200 30300 42800 38900 6 alt_e100_pcs_rx pcs_rx 19300 15700 25800 0 0 alt e100 pcs txpcs tx 10500 11000 13200 0 0 alt e100 phy csr phy csr 900 1100 1700 0 0 alt e100 pma pma 3500 2500 2100 38900 6 STATS CNTRS OPTION Disabled alt e100 adapter 49800 57600 84900 301100 34 alt e100 adapter adapter rx 1100 3400 6500 151600 17 alt e100 adapter adapter tx 400 3300 4900 0 0 alt e100 e100 48900 50900 73500 149500 17 alt e100 mac mac 14100 20600 30700 110600 11 alt e100 mac csr mac csr 700 1900 3000 0 0 alt e100 mac rx 5400 7400 12400 110600 11 alt e100 mac tx 7900 11200 15300 0 0 alt 100 phy phy 34200 30300 42800 38900 6 alt e100 pcs rx 19300 15700 25800 0 0 alt_e100_pcs_tx pcs_tx 10500 11000 13200 0 0 alt_e100_phy_csr phy_csr 900 1100 1700 0 0 alt_e100_pma pma 3500 2500 2100 38900 6 gt The 40 100GbE IP cores can support full wire line speed with a 64 byte frame length and back to back or mixed length traffic up to a 9600 byte frame size with no drops 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide June 2012 Alt
8. Ha n E Simulation Monitor at time 260015000 am locked fffff all locked 1 lanes deskewed 1 framing error 00000 bip error 00000 deskew failure 0 pma rx ready 1 tx ready 1 Number of packets sent 60 Simulation Monitor at time 265135000 am locked fffff all locked 1 lanes deskewed 1 framing error 00000 bip error 00000 deskew failure 0 pma rx ready 1 tx ready 1 Number of packets sent 90 n Simulation Monitor at time 270255000 am locked fffff all locked 1 lanes deskewed 1 framing error 00000 bip error 00000 deskew failure 0 pma rx ready 1 tx ready 1 Number of packets sent 120 DEPT S Simulation Monitor at time 275375000 am locked fffff all locked 1 lanes deskewed 1 framing error 00000 bip error 00000 deskew failure 0 pma rx ready 1 tx ready 1 Number of packets sent 148 eu tL eee eee ee eee eto EE June 2012 Altera Corporation 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide 2 24 Chapter 2 Getting Started Simulating the 40 100GbE IP Core Example 2 5 100GbE w
9. Number of packets sent 6 ert e re ie See Simulation Monitor at time 34985000 am locked fffff all locked 1 lanes deskewed 1 E framing error 00000 bip error 00000 H deskew failure 0 pma rx ready 1 tx ready 1 Number of packets sent 33 June 2012 Altera Corporation 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide 2 16 Example 2 2 100GbE with Adapters Testbench Stage 2 Continued Chapter 2 Getting Started Simulating the 40 100GbE IP Core HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHH HHH HHH HHH HH 4 HC HC HC HH db Simulation Monitor at time am locked fffff all locked 1 framing error 00000 bip error deskew failure 0 pma rx ready Number of packets sent Simulation Monitor at time am locked fffff all locked 1 framing error 00000 bip error deskew failure 0 pma rx ready Number of packets sent Simulation Monitor at time am locked fffff all locked 1 framing error 00000 bip error deskew failure 0 pma rx ready Number of packets sent Simulation Monitor at time am locked fffff all locked 1 framing error 00000 bip error deskew failure 0 pma rx ready Number of packets sent Simulation Monitor at time am locked fffff all locked 1 framing error 00000 bip error deskew failure 0 pma rx ready Number of packets sent Simulati
10. Virtual index for physical lane 3 5h 00 R 24 20 Virtual index for physical lane 4 5h 00 R 29 25 Virtual index for physical lane 5 5h 00 R 4 0 Virtual index for physical lane 6 5h 00 R 9 5 Virtual index for physical lane 7 5h 00 R 14 10 Virtual index for physical lane 8 5h 00 R 0x021 PCS VLANE1 19 15 Virtual index for physical lane 9 51700 R 24 20 Virtual index for physical lane 10 51700 R 29 25 Virtual index for physical lane 11 51700 R June 2012 Altera Corporation 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide 3 46 Chapter 3 Functional Description Software Register Interface Table 3 31 PCS VLANE Registers Part 2 of 2 Ls 4 0 Virtual index for physical lane 12 51700 R 9 5 Virtual index for physical lane 13 5h 00 R 14 10 Virtual index for physical lane 14 5h 00 R 0x022 PCS VLANE2 19 15 Virtual index for physical lane 15 5h 00 R 24 20 Virtual index for physical lane 16 5h 00 R 29 25 Virtual index for physical lane 17 5h 00 R 4 0 Virtual index for physical lane 18 5h 00 R 0x023 PCS VLANE3 9 5 Virtual index for physical lane 19 51700 R PRBS Registers The PRBS operates on a per virtual lane basis The PRBS streams are bit interleaved to form 10 Gbps lanes PRBS transmissions are unframed There is some deviation among manufacturers regarding the exact PRBS implementation on
11. 0x103 RX FILTER CTRL 2 When set to 1 runt frames are removed regardless of the filtering enable bit 0 013 0 When set to 1 the filter discard packets which are not for a matching destinations address RW RW 1 0 When set to 1 the filter discards packets with FCS errors When set to 0 enables filtering When set 10 1 accepts all traffic However when bit 3 is set runts are removed regardless of the value of bit 0 RW RW Pause Registers The pause register provides programmatic access to the pause functionality via the Avalon MM control and status bus These registers implement the pause functionality as defined in the IEEE 802 3ba 2010 100G Ethernet Standard You can use the pause signals to reduce traffic in a congested networks Table 3 34 describes the pause registers Table 3 34 Pause Registers Part 1 of 2 Addr Name June 2012 Altera Corporation Bit Description HW Reset Value Access 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide 3 48 Chapter 3 Functional Description Software Register Interface Table 3 34 Pause Registers Part 2 of 2 When set to 1 indicates that a pause is in 1 16 progress 0x110 RECEIVE PAUSE STATUS 0x140 15 0 The time value for the pause Reading this 40GbE R field locks the pause source ad
12. dA Se ee oe 40 and 100 Gbps Ethernet and PHY June 2012 Altera Corporation MegaCore Function User Guide Chapter 2 Getting Started Simulating the 40 100GbE IP Core Example 2 5 100GbE with Adapters Testbench Stage 5 Continued 2 21 HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHH HHH HHH Gk db Simulation Monitor at time am locked fffff all locked 1 framing error 00000 bip error deskew failure 0 pma rx ready Number of packets sent 184515000 lanes deskewed 00000 1 pma tx ready 25 Simulation Monitor at time am locked fffff all locked 1 framing error 00000 bip error deskew failure 0 pma rx ready Number of packets sent 189635000 lanes deskewed 00000 1 pma tx ready 50 Simulation Monitor at time am locked fffff all locked 1 framing error 00000 bip error deskew failure 0 pma rx ready Number of packets sent 194755000 lanes deskewed 00000 1 pma tx ready 80 Simulation Monitor at time am locked fffff all locked 1 framing error 00000 bip error deskew failure 0 pma rx ready Number of packets sent 199875000 lanes deskewed 00000 1 pma tx ready 110 Simulation Monitor at time am locked fffff all locked 1 framing error 00000 bip error deskew failure 0 pma rx ready Number of packets sent 204995000 lanes deskewed 00000 1 pm
13. e100 tb dut dout d 319 0 100_tb dut din 1 11 0 020304050607 2A2B2C2D2E2F 525354555657 7A7B7C7DCCC 88898A8B8C8D8E8F909192939495 e100_tb dut din_ack The TX logic supports packets of less than the usual length For example din start might be set to 57511111 indicating the start of a new packet in 5 successive words In this case din end pos equals 40 h0101010101 indicating 5 packets of 8 bytes Each 8 byte packet is padded with 075 to create 64 byte packet June 2012 Altera Corporation 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide 3 12 Chapter 3 Functional Description MAC and PHY Functional Description Bus Quantization Effects The TX custom streaming interface uses two or five words 40 bytes The TX bus allows a packet to start at any of two or five positions to maximize utilization of the link bandwidth If the start of packet SOP must be restricted to the most significant position in the client logic data bus bus bandwidth is reduced Figure 3 13 illustrates the reduction of bandwidth caused by left aligning the SOP for the 100GbE IP core Figure 3 13 Reduced Bandwidth due to left aligned SOP Example A Example B Two unusable words
14. tx startofpacket Input Refer to TX Data Bus with Adapters Avalon ST l n tx endofpacket Input Interface on page 3 6 l n tx ready Output l n tx valid Input tx serial 9 0 Output This signal replaces the tx_dataout signal from the IP cores without adapters RX Transmission Mode Configuration Ports clk_rxmac Input Refer to Clocks on page 3 29 l n rx data u 0 Output 1 lt gt rx empty v 0 Output l n rx startofpacket Output l n rx endofpacket Output Refer to RX Data Bus with Adapters Avalon ST l n rx error Output Interface on page 3 16 l n rx valid Output l n rx fcs valid Output l n rx fcs error Output rx_serial 9 0 Input This signal replaces the rx_datain signal from the IP cores without adapters Note to Table 3 15 1 lt n gt 4 for the 4 to 2 adapter and lt n gt 8 for the 8 to 5 adapter Lane variables are denoted by lt u gt and v Table 3 16 identifies the parameter configurations that differ for the 40 100GbE MAC IP Cores Table 3 16 MAC IP Cores Configuration Ports by Transmission Mode Part 1 of 2 Description Signal Name Direction TX Transmission Mode Configuration Ports miitx rev d w 64 1 0 Output miitx rev c w 8 1 0 Output miitx valid Output din ready Input tx lanes stable Input Refer to MAC to PHY Connection Interface on page 3 26 RX Transmission
15. 0 Lane 16 fully locked at time 241270000 Lane 8 fully locked at time 242050000 EDT 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide June 2012 Altera Corporation Chapter 2 Getting Started Simulating the 40 100GbE IP Core Example 2 5 100GbE with Adapters Testbench Stage 5 Continued 2 23 HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHH HHH Simulation Monitor at time 245955000 am locked fffdf all locked 0 lanes deskewed 0 framing_error 00000 bip_error 00000 deskew_failure 0 pma_rx_ready 1 pma_tx_ready 1 Number of packets sent 0 11 lanes locked Starting deskew at time 246889110 Lane 5 fully locked at time 246990000 All lanes locked at time 247020000 Deskew complete at time 248585060 Lanes deskewed at time 248840000 Wiping stats Restarting Traffic Gee ET Curs Simulation Monitor at time 249775000 am locked fffff all locked 1 lanes deskewed 1 framing error 00000 bip error 00000 deskew failure 0 pma rx ready 1 tx ready 1 Number of packets sent 5 ne c REP quM ccc LR e Simulation Monitor at time 254895000 am locked fffff all locked 1 lanes deskewed 1 framing error 00000 bip error 00000 deskew failure 0 pma rx ready 1 tx ready 1 Number of packets sent 30 C
16. 0x112 RECEIVE SOURCE ADDR MSB 0x113 RECEIVE PAUSE CONTROL 0 007 0 114 INSERT_PAUSE_CONTROL 0 008 0 115 TX_PAUSE_DST_ADDR_LSB RECEIVE_DST_ADDR 0x0b9 0x0ba 0x116 TX_PAUSE_DST_ADDR_MSB 0x117 INSERT_PAUSE 0x0bb 0x118 0x13f Reserved 0x140 MADDR_CTRL Ox0c2 0 141 SRC AD LO 0 040 0 142 580 AD HI 0 041 0x143 0x15f Reserved 0 160 0 0171 DST_ADR Oxe0 OxOff 0x180 x01 ff Reserved 0x200 0x02 TX statistics registers 0x140 0x169 0x0a1 0x0a4 0x200 0x229 TX statistics counters 0 140 0 169 0x0a1 0x0a4 0x022a CNTR TX ST LO 0 0 1 0x022b CNTR TX ST HI Ox0a2 0x022c CNTR TX DB LO 0x0a3 0x022d CNTR TX DB HI 0 0 4 0 0226 0 0271 Reserved 0x280 0x2ff RX statistics registers 0 280 0 249 RX statistics counters 0x180 0x1a9 Ox2aa CNTR_RX_ST_LO 0x09b Ox2ab CNTR_RX_ST_HI 0 09 Ox2ac CNTR_RX_DB_LO 0x09d Ox2ad CNTR_RX_DB_HI 0x09e Ox2ae CNTR_RXF_ST_LO 0 000 Ox2af CNTR_RXF_ST_HI Ox0b1 0 200 CNTR_RXF_DB_LO Ox0b2 0 201 CNTR_RXF_DB_HI 0 003 0 2 2 CNTR_RXF_LONG 0 40 100 Gbps Ethernet and PHY June 2012 Altera Corporation MegaCore Function User Guide Appendix D Address Map Changes for 11 0 SP1 Table D 1 Address Map and Register Name Changes for 11 0 SP1 D 3 June 2012 Altera Corporation Current 40 100GbE Address Current Name Previous Address Previous Name 0 203 Reserved 0 204 CNTR_RX_EBL
17. MDIO Registers on page 3 57 0x414 0x41f Reserved 0x420 0x423 Refer to 2 Wire Serial Registers on page 3 58 Register Initialization To initialize the 40 100GbE IP core complete the following steps 1 Drive the clock ports as specified 2 Reset the IP core for more information refer to Resets on page 3 30 3 Clear the statistics counters by writing 1 to bit 3 of the general control MAC CMD config register 4 Wait until the IP core is fully locked before driving the stimulus Read the fully locked deskew status from bit 1 of AGGREGATE register 40 100GbE IP Core Registers The following sections describe the registers included in the 40 100GbE IP core Transceiver PHY Control and Status Registers The serial clocks for 10 3125 Gbps data on a 40 bit interface should operate at 257812 5 KHz The TX serial rate is based on the reference clock and should be precise and stable The RX serial rate is recovered from the remote system It typically shows some instability during lock acquisition The core clocks should exceed 312500 KHz for proper operation 40 and 100 Gbps Ethernet MAC and PHY June 2012 Altera Corporation MegaCore Function User Guide Chapter 3 Functional Description Software Register Interface The registers in the transceiver PHY provide dynamic access to the analog configuration capability on a per channel pin basis You can also use these registers to place the transceivers in loopbac
18. These address map changes apply to both the Stratix IV and Stratix V devices Table C 1 Address Map and Register Name Changes for 12 0 Current 40 100GbE Address Current Name Previous Address Previous Name 40 100GbE IP Core Registers 0x017 PCS HW ERR HW ERR 0x018 BER MONITOR Reserved 0x019 TEST MODE Reserved 0x01a TEST PATTERN COUNTER Reserved 0 010 Enable Link Fault sequence Reserved 0 010 Reserved 0x120 MAC_HW_ERR Reserved 0x121 MAC Reset Reserved 0x122 a d sequence Reserved 0x123 CRC_CONFIG Reserved 0x162 0x17f Reserved 0 160 0 0171 DST_ADR June 2012 Altera Corporation 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide 0 2 Appendix C Address Map Changes for 12 0 40 and 100 Gbps Ethernet MAC and PHY June 2012 Altera Corporation MegaCore Function User Guide N DTE RYN D Address Map Changes for 11 0 SP1 For improved organization and clarity version 11 0 SP1 of the 40 and 100 Gbps MAC and PHY MegaCore Function has revised the address map and renamed a few registers Table D 1 lists the current addresses and register names and the previous address and names if the name has changed These address map changes apply to both the Stratix IV and Stratix V devices Table D 1 Address Map and Register Name Changes for 11 0 SP1 Current 40 100GbE
19. from an earlier release refer to Appendix C Address Map Changes for 12 0 fora complete list of changes Table 3 18 100GbE and Example Design Address Map Part 1 of 2 Word Offset Register Description 40 100GbE IP Core Registers Refer to Scratch and Clock Registers for Stratix IV and Stratix V Devices 0 000 0 009 on page 3 39 0x00a 0x00f Reserved 0 010 0 014 Refer to Lock Status Registers page 3 41 0x015 0x016 Refer to Bit Error Flag Registers on page 3 42 0x017 Refer to PCS Hardware Error Registers on page 3 42 0x018 Refer to BER Monitor Registers on page 3 43 0x019 Refer to Test Mode Registers on page 3 43 0x01a Refer to Test Pattern Counter Registers on page 3 44 0x01b Refer to Link Fault Signaling Registers on page 3 44 0x01c Reserved 0 014 PHY reset registers Refer to IMAC and PHY Reset Registers on page 3 44 0x01e 0x01f Reserved 0 020 0 023 Refer to PCS VLANE Registers on page 3 45 0x024 0x02F Reserved 0 030 0 032 Refer to PRBS Registers on page 3 46 0x033 0x03F Reserved 0x040 0x07F Stratix IV only Maps to word addresses 0x040 0x07F in the Low Latency PHY IP core 0x040 0x07F register map For more information including loopback configuration Stratix V only refer to the Low Latency PHY IP Core chapter in the Altera Transceiver PHY IP Core User Guide 0x080 0xO0FF Maps to word address
20. the TX datapath are not related and their rates do not have to match Vote to Table 3 5 1 lt w gt 2 for the 40GbE IP core and lt w gt 5 for the 100GbE IP core The data bytes use 100 Gigabit Media Independent Interface CGMII like encoding For packet payload bytes the dout_c bit is set to 0 and the dout_d byte is the packet data You can use this information to transmit out of spec data such as customized preambles when implementing non standard variants of the IEEE 802 3ba 2010 100G Ethernet Standard If the additional customized data is not required simply ignore all words which are marked with dout payload 0 and discard the dout_c bus 40 and 100 Gbps Ethernet MAC and PHY June 2012 Altera Corporation MegaCore Function User Guide Chapter 3 Functional Description 3 19 MAC and PHY Functional Description Figure 3 18 illustrates typical RX bus activity Figure 3 18 RX Bus Activity without Adapters 1 2 3 4 5 6 7 8 e100_tb dut clk_dout 363738393830863 8788898 808 808 afb0b1b2b3b4b5b6 070707070707070 055555 585100616263646 7070 020202020202010 0707070707 e100_tb dut dout_d e100_tb dut dout_c 0000000000 000007ffff ffffffffSO 0000000000 000000003f ffffffffff 800 e100 tb dut dout first data 00 10 00 08 e100_tb dut dout_last_data 0000000000 0000800000 wo 0000000400 0000000000 e100_tb dut
21. 3 41 For information about Stratix V transceiver PHY IP control and status registers refer RX_AGGREGATE 0 aggregates the status of the individual RX PCS channels When set to 1 the RX PCS is operating normally When set to 0 the other information indicates the cause Table 3 21 describes the lock status registers Table 3 21 Lock Status Registers Part 1 of 2 stream HW Reset Address Name Bit Description Value Access 31 25 100 GbE Reserved Ox7f R 24 22 When asserted indicates that the corresponding TX 0 0 R 100 GbE PLL is locked 21 12 100 GbE Reserved Ox3ff R 11 2 When asserted indicates that the corresponding RX 100 GbE CDR locked The lowest bit corresponds to lane 0 and 0x0 R so forth 0x010 IO LOCKS 31 7 40 GbE Reserved Ox1 ffffff R 6 When asserted indicates that the corresponding TX 1100 R 40 GbE PLL is locked 5 2 When asserted indicates that the corresponding RX CDR locked The lowest bit corresponds to lane 0 and 0x0 R 40 GbE so forth 1 When asserted indicates that the TX interface is ready 0 When asserted indicates that the RX interface is ready 1 b0 R Counts the RX continuous up time in seconds The om E E 81 0 counter will roll over in approximately 126 years 0 00000000 i When asserted indicates that the physical channel has 0x012 WORD_LOCKS 19 0 identified 66 bit block boundar
22. 33 Signal Name Direction Description dout_d lt w gt 64 1 0 Output dout_c lt w gt 8 1 0 Output dout first data lt w gt 1 0 Output dout_last_data lt w gt 8 1 0 Output dout_runt_last_data lt w gt 1 0 Output Refer to RX Data Bus without Adapters dout_payload lt w gt 1 0 Output Custom Streaming Interface on page 3 17 dout_fcs error Output dout fcs valid Output dout dst addr match w 1 0 Output dout valid Output clk status Input Refer to Clocks on page 3 29 status addr 15 0 Input status read Input status write Input Refer to Control and Status Interface on status writedata 31 0 Input page 3 28 status readdata 31 0 Output status readdata valid Output June 2012 Altera Corporation 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide 3 34 Chapter 3 Functional Description MAC and PHY Functional Description Table 3 14 IP Cores Without Adapters Configuration Ports by Transmission Mode Part 4 of 4 Signal Name Direction Description rx inc runt Output rx inc 64 Output rx inc 127 Output rx inc 255 Output rx inc 511 Output rx inc 1023 Output rx inc 1518 Output rx inc max Output rx inc over Output rx inc mcast data err Output Refer to Statistics Registers on page 3 50 rx inc bcast data err Ou
23. AVI RA 101 Innovation Drive San Jose CA 95134 www altera com UG 01088 2012 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide Document last updated for Altera Complete Design Suite version Document publication date 12 0 June 2012 NA Feedback Subscribe 2012 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks oF Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ISO 9001 2008 Registered June 2012 Altera Corporation 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide N DTE RYN Conte
24. Address Current Name Previous Address Previous Name 40 100GbE IP Core Registers 0x000 PHY Version 0x081 0x001 SCRATCH PHY 0x080 0x002 CLK TXS 0x082 0x003 CLK RXS 0x083 0x004 CLK TXC 0x084 0x005 CLK RXC 0x085 0x006 TEMP SENSE 0x086 0x007 GX CTRL1 0x087 GX CTL1 0x008 GX CTRL2 0x088 GX CTL2 0x009 GX REPLY 0x089 0x00a 0x00f Reserved 0 010 10 LOCKS 0 090 0 011 LOCKED_TIME 0 091 0 012 WORD_LOCKS 0 092 0 013 AM_LOCKS 0x093 0 014 RX_AGGREGATE 0x094 0 015 FRAMING_ERR 0x095 0 016 0 096 0 017 HW_ERR 0x097 0x018 0x01f Reserved 0x020 PCS VLANEO 5 0 0 8 0 021 PCS VLANE6_11 0 0 9 0 022 PCS VLANE12_17 0x0aa 0x023 PCS VLANE18 19 0x0ab 0x024 0x02f Reserved 0x030 PRBS_CTRL 0x0ac 0x031 PRBS_ERR_INJ 0x0ad 0x032 PRBS_EFLAGS 0x0ae 0x033 0x03f Reserved June 2012 Altera Corporation 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide D 2 Appendix D Address Map Changes for 11 0 SP1 Table D 1 Address Map and Register Name Changes for 11 0 SP1 Current 40 100GbE Address Current Name Previous Address Previous Name 0x040 0x0ff Reserved 0x100 MAC_VERSION 0 0 1 0 101 SCRATCH_MAC 0 0 0 0 102 CMD config 0x0a0 GEN CTRL 0x103 RX FILTER CTRL 0 091 RXF_CTRL 0x104 0x1 Of Reserved 0x110 RECEIVE_PAUSE_STATUS 0 004 0 111 RECEIVE SOURCE ADDR LSB 0 005 0 006
25. File Name alt e100 10 10 Megafunction Name s alt4gxb Simulation Library File s stratixiv hssi ae ee cer kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkk kkkkkkkkkkkkkkkk THIS IS A WIZARD GENERATED FILE DO NOT EDIT THIS FILE 12 0 Build 176 05 18 2012 SJ Full Version kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkk kkkkkkkkkkkkkkkk In some cases the header comments are appended by generic comment lines if you regenerate the PHY IP cores the MegaWizard Plug In Manager will not recognize the files Remove any generic comments from the PHY IP core so the file begins with comments shown in Table B 1 The MegaWizard Plug In Manager will recognize the updated files and complete the regeneration process T Simulation file lists might need to be updated when upgrading to a newer version of the Quartus II software Refer to the Altera Transceiver PHY IP Core User Guide for more information on simulating the IP core 40 and 100 Gbps Ethernet MAC and PHY June 2012 Altera Corporation MegaCore Function User Guide N DTE SYN C Address Map Changes for 12 0 For improved organization and clarity version 12 0 of the 40 and 100 Gbps MAC and PHY MegaCore Function has revised the address map and renamed a few registers Table 1 lists the current addresses and register names and the previous address and names if the name has changed
26. Functional Description MAC and PHY Functional Description Table 3 8 XL CGMII Permissible Encodings Part 2 of 2 Control Data Description 1 fd End of Frame fd frame done 1 fe XL CGMII Error Typically a bit error which switched a 66 bit block between data and control or corrupt control information fe frame error MAC to PHY Connection Interface The MAC to PHY connection interface is included in the 40 100GbE MAC and PHY IP Cores without adapters Table 3 9 describes the TX and RX connections Table 3 9 MAC to PHY TX and RX Connections Signal Name miitx_rev_d lt w gt 64 1 0 Direction Description TX MAC to PHY Connections from MAC Media independent interface MII data TX connection starting with the least significant bit LSB Output miitx_rev_c lt w gt 8 1 0 MAC only MII control TX connection miitx valid Asserted upon valid TX to MII connection din_ready Input Asserted when TX data bus is ready for MII connection tx lanes stable PHY only Asserted when TX lanes are stable and deskewed RX MAC to PHY Connections from MAC rx raw mii d w 64 1 0 Input MII data RX connection starting with the LSB and least significant word outputting a 5 word data stream MII control RX connection Asserted when RX blocks are valid rx raw mii c w 8 1 0 PHY only rx blocks valid Lane to Lane Deskew Interface The lane to
27. IV or Stratix V Figure 2 1 RTL Hierarchy and Wrappers 40GbE and 100GbE MegaCore Function with Adapter alt e adapter 40GbE and 100GbE MegaCore Function without Adapter alt e Transmit Adapter Transmit MAC Transmit PCS alt e adapter tx alt e mac tx alt e pcs tx CSR MAC PHY CSR PMA alt e mac csr alt e phy csr alt e pma Receive Adapter Receive MAC Receive PCS alt e adapter rx alt e mac rx alt e pcs rx Note to Figure 2 1 1 In the file names shown denotes either 40 for 40GbE or 100 for 100GbE 40 and 100 Gbps Ethernet MAC and PHY June 2012 Altera Corporation MegaCore Function User Guide Chapter 2 Getting Started 2 3 Installing the IP Core 57 There are no top level wrapper files provided for the 40GbE or 100GbE MAC IP cores with adapters Two unencrypted top level adapter files are provided to accommodate The unencrypted 40GbE top level adapter files are located in the alt_eth_40g_12 0 zip file at alt_eth_40g quartus_synth rtl_src adapter rx alt_e40_adapter_rx v and alt_eth_40g quartus_synth rtl_src adapter tx alt_e40_adapter_tx v The unencrypted 100GbE top level adapter files are located in the alt eth 100g 12 0 zip file at alt eth 100g Nquartus synthWMrtl 16 e100 adapter rx v and alt eth 100gNquartus synthMrtl srcVadapterMtx Malt e100 adapter tx v The alt e100 adapter v wrapper
28. Mode Configuration Ports June 2012 Altera Corporation 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide 3 36 Chapter 3 Functional Description Software Register Interface Table 3 16 MAC IP Cores Configuration Ports by Transmission Mode Part 2 of 2 Signal Name Direction Description rx raw mii d w 64 1 0 Input Baw Wad 2 1588 12 01 Refer to MAC to PHY Connection Interface on rx_blocks valid Input Refer to Lane to Lane Deskew Interface on lanes deskewed Input page 3 26 La When simulating the full design the lanes deskewed input comes from the output of the RX PCS indicating a fully locked status To avoid confusion when simulating the alt e40 macoralt e100 mac wrapper as the top level drive the lanes deskewed input and the din ready input to 1 Table 3 17 identifies the parameter configurations that differ for the 40 100GbE PHY IP Cores Table 3 17 PHY IP Cores Configuration Ports by Transmission Mode Signal Name Direction TX Transmission Mode Configuration Ports Description clk din Input miitx rev d w 64 1 0 Input miitx rev c w 8 1 0 Input miitx valid Input din ready Output tx lanes stable Output Refer to Clocks on page 3 29 Refer to MAC to PHY Connection Interface on page 3 26 RX Transmission Mode Configuration Ports clk dout Input Refer to Clocks on page 3 29 rx
29. Register Interface Table 3 39 Statistics Counters Increment Vectors Part 2 of 2 Name 1 0 Description rx inc 127 Output Asserted for one cycle when a 127 byte RX frame is received rx inc 255 Output Asserted for one cycle when a 255 byte RX frame is received rx inc 511 Output Asserted for one cycle when a 511 byte RX frame is received rx inc 1023 Output Asserted for one cycle when a 1023 byte RX frame is received rx inc 1518 Output Asserted for one cycle when a 1518 byte RX frame is received rx inc max Output Asserted for one cycle when a maximum size RX frame is received rx inc over Output Asserted for one cycle when an oversized RX frame is received er data err Asserted for one cycle when an errored multicast RX frame excluding control See ee put frames is received Asserted for one cycle when valid a multicast RX frame excluding control frames rx inc mcast data ok Output is received SiO peast data ert BUDE Asserted for one cycle when an errored broadcast RX frame excluding control pos frames is received Asserted for one cycle when a valid broadcast RX frame excluding control frames rx inc beast data ok Output is received O Asserted for one cycle when an errored unicast RX frame excluding control Diis frames is received Asserted for one cycle when a valid unicast RX frame exc
30. Statistics Registers Part 5 of 5 0x2A0 CNTR RX UCAST CTRL LO Number of valid unicast frames received lower 32 bits RC 0 2 1 CNTR RX UCAST CTRL HI Number of valid unicast frames received upper 32 bits RC 0x2A2 CNTR RX PAUSE LO Number of valid pause frames received lower 32 bits RC 0 2 3 CNTR RX PAUSE HI Number of valid pause frames received upper 32 bits RC 0 2 4 CNTR FRAGMENTS LO VOR Lade mou less than 64 bytes and reporting a RC 0x2A5 CNTR FRAGMENTS HI Ra RUE less than 64 bytes and reporting a RC 0 2 6 CNTR RX JABRERS LO oversized frames reporting a CRC error RC 0x2A7 CNTR RX JABRERS HI qucd oversized frames reporting a CRC error RC Number of received frames between the length of 64 and the 0 2 8 CNTR RX CRCERR LO value configured in 0x103 register with CRC error lower 32 RC bits Number of received frames between the length of 64 and the 0 2 9 CNTR RX CRCERR value configured in 0x103 register with CRC error upper 32 RC bits RX Packet Statistics Ox2AA CNTR RX ST LO Number of received frame starts lower 32 bits RC 0 2 CNTR RX ST HI Number of received frame starts upper 32 bits RC 0 2 CNTR RX DB LO Number of received data blocks lower 32 bits RC 0 2 CNTR RX DB HI Number of received data blocks upper 32 bits RC Ox2AE CNTR RXF ST LO Number of acc
31. The 40GbE IP core with four to two word adapters 256 bits to 128 bits and the Avalon MM Avalon ST interface a Stratix V device SV alt e40 avalon tb m The 40GbE IP core with no adapters and a custom interface a Stratix IV device SIV alt e40 custom tb m The 40GbE IP core with no adapters and a custom interface a Stratix V device SV alt e40 custom tb m The 100GbE IP core with eight to five word adapters 512 bits to 320 bits and the Avalon MM Avalon ST interface on a Stratix IV device SIV alt e100 avalon tb m The 100GbE IP core with eight to five word adapters 512 bits to 320 bits and the Avalon MM Avalon ST interface on a Stratix V device SV alt e100 avalon tb m The 100GbE IP core with no adapters and a custom interface on a Stratix IV device SIV alt e100 custom tb m The 100GbE IP core with no adapters and a custom interface on a Stratix V device SV alt e100 custom tb Conceptually the testbenches for the 40 100GbE IP cores with adapters are identical and the testbenches for the 40 100GbE IP cores without adapters are identical except for the bandwidth The following sections first describe the testbenches that include adapters and then describe the testbenches without adapters Each of the eight example testbenches illustrate packet traffic error behavior and asynchronous reset recovery in addition to providing information regarding the transceiver PHY June 2012 Altera Corpora
32. and PHY June 2012 Altera Corporation MegaCore Function User Guide Chapter 3 Functional Description 3 25 MAC and PHY Functional Description IEEE specifies RS monitoring of RXC lt 7 0 gt and RXD lt 63 0 gt for Sequence ordered sets For more information refer to Figure 81 9 Link Fault Signaling state diagram and Table 81 5 Sequence ordered sets from the IEEE 802 3ba 2010 100G Ethernet Standard available from the IEEE website www ieee org The variable link fault is set to indicate the value of as RX Sequence ordered set when four fault sequences containing the same fault value are received with fault sequences separated by less than 128 columns and there are no intervening fault sequences of different fault values The variable link fault is set to OK following any interval of 128 columns not containing a remote fault or local fault Sequence ordered set Table 3 7 describes the link fault signaling interface signals Table 3 7 Link Fault Signaling Interface Signal Name Direction Description pe Output Asserted when remote fault is detected in RX MAC Used only when RX remote_tau t_irom_rx p configurations are instantiated Asserted when local fault is detected in RX MAC Used only when RX c meee eas configurations are instantiated tot input Asserted when remote fault is detected Used only when TX configurations remote rau t 0 are instantiated input Asserted when local fault is detec
33. counts the number of mismatched blocks when in test pattern mode 3 The single register bit Clr counter enables software to clear the test pattern error counter June 2012 Altera Corporation 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide 3 28 Chapter 3 Functional Description MAC and PHY Functional Description Transceiver PHY Serial Data Interface The core uses a 40 bit x lt n gt lane digital interface to send data to the TX high speed serial I O pins operating at 10 3125 Gbps The rx datainand tx dataout ports connect to the 10 3125 Gbps pins The protocol includes automatic reordering of serial lanes so that any ordering is acceptable Virtual lanes 0 and 1 transmit data on tx dataout 0 PCS BER Monitor The PCS implements bit error rate BER monitoring as specified by the IEEE 802 3ba 2010 100G Ethernet Standard When the PCS deskews the data and aligns the lanes the BER monitor checks the signal quality and asserts hi ber if it detects excessive errors When align status is asserted and hi ber is deasserted the RX PCS continuously accepts blocks and generates RXD 63 0 and RXC 7 0 on the XLGMII or CGMII interface High BER occurs when 97 invalid 66 bit synchronous headers are detected for 100GbE within 500 ys or detected for 40GbE within 1 25 ms When less than 97 invalid 66 bit synchronous headers occur in the same window the high BER state is exited For more information refer to Figure 82
34. file describes how to hook up these adapter files For example in the alt e adapter wrapper file where represents 40 for A0GbE IP cores and represents 100 for 100GbE IP cores the alt e adapter rx and alt e adapter tx modules are instantiated and the outputs are connected to the alt e module s MAC level interface signals Similarly you can create a top level wrapper file by instantiating the alt e adapter rx and alt e adapter tx modules and connecting the outputs to the alt e mac wrapper An example directory structure for the 40 100GbE IP core including all possible configurations of 40 Gbps and 100 Gbps bandwidth is shown in Figure 2 2 June 2012 Altera Corporation 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide 2 4 Chapter 2 Getting Started Installing the IP Core Figure 2 2 Directory Structure for the 40GbE and 100GbE Packages exi project dir alt eth 100gbe ver alt eth g quartus synth Contains files needed for Quartus Il compilation wrappers Contains the unencrypted top level wrapper files well as project files for SIV amp SV qpf qsf qip amp sdc e alt_e _adapter alt_e _phy rtl src Contains the encrypted source files for Quartus II compilation gt adapter common mac phy example_design Contains the hardware example designs alt e ada
35. gan I4 tx valid I4 tx error 14 rx data 255 0 14 rx startofpacket I4 rx endofpacket l4 rx empty 4 0 02 U U U Li LIL LP LE LS 12121211 14 rx error Figure 3 7 shows typical traffic for the TX and RX Avalon ST interface of the 100GbE IP core This example was taken from a ModelSim simulation of the parallel testbench described in Testbench with Adapters on page 2 8 Figure 3 7 Traffic on the TX and RX Client Interface for 100GbE IP Core Using the Eight to Five Word Adapters I8 tx data 511 0 01 1 2 OCLI 1273 01263 01253 1 18 tx startofpacket m ry 18 tx endofpacket I8 tx empty 5 0 00 2 00 29 00 18 tx ready iBixvaidf d l8 tx error I8 rx dataps11 0 64 64 Ja J fa 1 16 46 oz rr 07 0707070707070 18 rx startofpacket ry l8 rx endofpacket V 1 8 x 5 0 30 fso 10 20 22 foe fejoof ec o jos PLU U UU U U U UUU U UU U 18 rx error 40 and 100 Gbps Ethernet MAC and PHY June 2012 Altera Corporation MegaCore Function User Guide Chapter 3 Functional Description 3 9 MAC and PHY Functional Description TX Data Bus without Adapters Custom Streaming Interface When no adapters are used the 40G
36. lane deskew signal is included in the 40 100GbE IP Cores with and without adapters When both MAC and PHY options are selected the lane to lane deskew signal acts as an internal signal Table 3 10 describes the lane to lane deskew interface Table 3 10 Lane to Lane Deskew Signal Name Direction Description nen Input Indicates lane to lane skew is corrected Available as an input to the 40 100GbE MAC IP cores only Indicates lane to lane skew is corrected Available as an output from the 40 100GbE PHY IP cores only PCS Test Pattern Generation and Test Pattern Check The PCS can generate a test pattern and detect a scrambled idle test pattern PCS test pattern mode is suitable