Home

ALTERA ALTDLL ALTDQ_DQS Megafunctions user manual

Contents

1. dyn term ctrl p 1 n ce p 0 OBUF dataio gt B datan ts PSEUDO DIFF OUT ALTDQ_DQS term n 1 w IO OBUF lt 4 rk gt p Ln dataout IO IBUF 4 ALTIOBUF Note to Figure 4 17 1 The dyn term ctrl panddyn term n ports are optional Figure 4 18 Bidirectional Complementary dyn term ctrl p 1 C dataio_p _ gt lt E datain p gt ALTDQ_DQS dataout_p e IO IBUF ALTIOBUF dyn term ctrl n 1 gt ir dataio_n oe_n T p datain_n P dataout_n IO IBUF ALTIOBUF Note to Figure 4 17 1 The dyn term ctrl panddyn term n ports are optional ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description 4 22 DQS CONFIG 10 CONFIG Block DQS CONFIG 10 CONFIG Block The DQS CONFIG and IO CONF IG blocks dynamically change the settings of various configuration bits One IO CONFIG block is configured per I O whereas DQS CONFIG block is configured per x4 group of I Os similar to IO CLOCK DIVIDERs These blocks share the datain clk and update signals eventhough they have individual enable signals When dynamic delay chains are enabled two key blocks are used together with the I O buffer block input buffer output buffer or bidirectional buffer
2. output_dq_output data out n 1 0 Output Optiona This port outputs the output DQ signal from the OUTPUT_DQ_OUTPUT_DELAY_CHAIN2 dat aout OUTPUT_DQ_OUTPUT_DELAY_CHAIN1 dat aout OUTPUT DQ OUTPUT FF q OUTPUT DQ OUTPUT DDIO OUT dataout Oroutput dq output data in port output dq sreset n 1 0 Input Optiona GND This port is connected to all sreset ports in the output DQ IO primitives that is used to synchronously reset the registers in those primitives ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description ALTDQ_DQS Megafunction Ports DQ OE Path Megafunction Ports Table 4 17 summarizes all the ports on the megafunction that configure the DQ OE path The possible values for IO are 1 Table 4 17 Megafunction Ports to Configure DQ OE Path 4 42 BIDIR_DQ and OUTPUT DQ Part 1 of 2 Port Name Type Optional Required Default Description bidir_dq_areset n 1 0 Input Optional GND This port is connected to all areset port in the bidir DQ IO primitives that is used to asynchronously reset the registers in those primitives bidir_dq_hr_oe_in 2 1 01 Input Optional GND This port feeds the half rate bidirectional DQ OE signal for the BIDIR OE HR DDIO OUT datainhi datainlo por
3. February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 33 Chapter 4 Functional Description ALTDQ_DQS Megafunction Ports ALTDQ_DQS Megafunction Ports Table 4 11 to Table 4 19 describes the ports of the ALTDQ_DQS megafunction that you can use to configure the DOS input path DOS output path DOS OE path DQ DQS OCT path DQ input path DO output path DO OE path DOSN IO path and 005 CONFIG IO CONFIG path DQS Input Path Megafunction Ports Table 4 11 summarizes all the ports on the megafunction to configure the DOS input path ny number of bidirectional DQ n number of output DQ n number of input DO n number of clock divider Table 4 11 Megafunction Ports to Configure DQS Input Path Part 1 of 2 Port Name Optional Type Required Default Description core_delayctrli n 5 0 Input Optional GND This port receives the Gray coded delay chain setting for the DQS read path from the FPGA core This port does not need to match the polarity of its source and can be inverted dll delayctrlin 5 0 Input Optional GND This port receives the Gray coded delay chain setting for the DQS read path from the ALTDLL delayctrlout 5 0 port This port must match the polarity of its source and cannot be inverted dqs bus out Output Optional This port receives the possibly delayed DQS output signal from the 05 ENABLE dqsbusout DQSBUSOUT
4. La The following blocks are not available in Arria GX devices m Dynamic OCT blocks m Half rate blocks m I O and DOS configuration blocks February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide Chapter 4 Functional Description 4 2 Custom External Memory Interface Datapaths Overview For more information about the blocks available in the datapaths for your target device family refer to the following chapters in the device handbook External Memory Interfaces in HardCopy Devices chapter in volume 1 of the HardCopy Device Handbook m External Memory Interfaces in HardCopy IV Devices chapter in volume 1 of the HardCopy IV Device Handbook m External Memory Interfaces in Arria GX Devices chapter in volume 1 of the II GX Device Handbook m External Memory Interfaces in Stratix IV Devices chapter in volume 1 of the Stratix IV Device Handbook m External Memory Interfaces in Stratix Devices chapter in volume 1 of the Stratix III Device Handbook La The DQ DQS read and write signals in Figure 4 1 may be bidirectional or unidirectional depending on the memory standard When bidirectional the signal is active during both read and write operations Table 4 2 lists the megafunction blocks in Figure 4 1 Table 4 1 Megafunction Blocks Megafunction Block ALTDLL Description The ALTDLL megafunction controls the DLL and DLL offset blocks For
5. 4 36 DQ DQS OCT Path Megafunction Ports 4 37 DQ Input Path Megafunction Ports 4 38 DQ Output Path Megafunction Ports 1 4 40 DQ OE Path Megafunction Ports 4 42 DOSn I O Path Ports ERE RIT ence eens 4 43 DQS_CONFIG IO_CONFIG Megafunction Ports 4 45 Correct Settings for External Memory Interfaces 4 46 February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide Design Example Implementing Half Rate DDR2 Interface in Stratix Devices 4 49 Procedure spiti ied Ret E RES RI seven ieee his 4 49 Understanding the Simulation Results 4 60 Appendix A Clear Box Generator Using Clear Box Generator A 1 Clear Box Generator Options ereire E E nee ee 2 Clear Box 25522 p tee e m RU S Reed 3 Additional Information Revision Pees ET eee ae Pas Se ess Info 1 How to Contact Altera cce
6. Clear Box Parameter Name Legal Value Parameter Name Description DQ Input Register DQ RESYNC REG MODE Enables the DQ resynchronization register Options Supported in Arria 11 GX devices only Use DQ resync register DQ Input Register DQ HALF RATE USE If you turn on this parameter the dataoutbypass Options DATAOUTBYPASS input dynamically routes the directin input to the Use DQ half rate dataout output for lt 0 gt HALF RATE INPUT dataoutbypass block Using this parameter you can bypass the half rate port registers in lt 0 gt HALF RATE INPUT block dynamically during the FPGA run time Not supported in Arria Il GX devices Advanced DQ IPA Setstatically PHASE If you turn on the Set statically to option the phase Options to SETTING setting can be selected from values 0 to 7 for the delay DQ Input Phase or chains If you turn on the Select dynamically using Alignment Phase Set configuration registers option the phase setting is Setting od determined by the phasect xlin input for the delay dynamically chains This parameter fine tunes the resynchronization using phase for the DQ input data The phase settings are also configuration called the levelling delay chains that handle the fly by registers clock topology in DDR3 interfaces Advanced DQ IPA Always DQ_IPA_ADD_INPUT If you turn on Always a single cycle delay is added to Options Never or CYCLE DELAY the input path If you turn on Never n
7. RERUM eK CARE PERSE ES URS NE eas Info 1 Typographic Conventions es wee er gebe eee Info 2 ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation 1 About these Megafunctions RYA The ALIDLL and ALTDO DOS megafunctions provide a custom external memory interface solution to access an FPGA s architecture and allow you to build your own custom external memory interface physical layer PHY blocks Altera recommends that you use the ALTDLL and ALTDO DOS megafunctions when implementing a specialized or customized intellectual property IP for an Altera supported external memory interface that is not supported in Altera s IP ora proprietary interface that is not supported by Altera The ALIDLL and ALTDO DOS custom external memory interface solution offers more efficient logic synthesis and device implementation and saves valuable design time if you choose to code your own logic The ALTDLL megafunction configures the dedicated DQS phase shift circuitry and the ALTDO DOS megafunction implements the read and write PHY required for the interface While the ALTDLL and ALTDO DOS custom external memory interface solution is primarily for building custom memory interface PHY blocks you can also use this solution to interface with any external device such as ASIC ASSP or another FPGA through the double data rate DDR interface gt The
8. Build the Datapath After you identify the requirements for your custom external memory interface the first stage is to build a datapath to interface with the memory blocks To build the datapath you must perform the following steps 1 Create a project in the Quartus II software that targets the preferred Altera device 2 Instantiate the ALTPLL megafunction to provide the required clocking scheme for the custom PHY Ste For more information about instantiating megafunctions and the clocking scheme refer to Instantiate the ALTPLL Megafunction section in volume 5 of the External Memory Interface Handbook For more information about using PLLs refer to the ALTPLL Megafunction User Guide 3 Instantiate the ALTDLL megafunction to implement the DLL February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide Chapter 2 Getting Started 2 2 Design Flow 4 Instantiate the ALTDO DOS megafunction to implement the read and write PHY required for the interface 5 Integrate the custom PHY with user logic and a custom or third party memory controller if needed 6 Instantiate the ALTIOBUF megafunction to use the I O buffers for pin connections This megafunction enables dynamic OCT capabilities for the respective interface pins Ta For more information about the pin connections refer to ALTIOBUF Megafunction and Delay Chains Integration on page 4 18 For more information about the ALTIOBUF me
9. input DQ IO primitives that is used to synchronously reset the registers in those primitives ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description ALTDQ_DQS Megafunction Ports DQ Output Path Megafunction Ports Table 4 16 summarizes all the ports on the megafunction that configure the Output path The possible values for IO are BIDIR_DQ and OUTPUT DQ Table 4 16 Megafunction Ports to Configure DQ Output Path 4 40 Part 1 of 2 Port Name Type Optional Required Default Description bidir_dq_areset n 1 0 Input Optional GND This port is connected to all areset ports in the bidirectional DQ IO primitives that is used to asynchronously reset the registers in those primitives bidir_dq_hr_output_dat a in 4 n 1 0 Input Optional GND This port feeds the half rate DDR bidirectional DQ signal for the BIDIR DQ OUTPUT HR DDIO OUT datainhi datainlo and BIDIR DQ OUTPUT HR DDIO OUT atainhi datainlo ports HIGH As LOW d bidir_dq_output_data_i n nj1 0 Input Optional GND This port feeds the bidirectional DQ signal for the BIDIR OUTPUT FF d BIDIR OUTPUT DELAY CHAIN1 data in BIDIR DQ OUTPUT DELAY CHAIN2 data in Ofbidir dq output out port bidir dq output data i n high
10. RA 101 Innovation Drive San Jose CA 95134 www altera com ALTDLL and ALTDQ_DQS Megafunctions User Guide Software Version 9 1 Document Version 5 0 Document Date February 2012 Copyright 2010 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending ap plications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services UG 01032 5 0 LS EN ISO 9001 ATEA Contents Chapter 1 About these Megafunctions Device SU
11. Both outputs bidir_dq_0_output_hr_ddio_out_high_inst dataout and bidir_dq_0_output_hr_ddio_out_low_inst dataout of the previous DDIO_OUT ports are channeled into another DDIO_OUT port which is clocked at 333 333 MHz by the c1 PLL clock output The output bidir dq 0 output ddio out inst dataout is then connected to the bidirectional DO output delay chain 1 The output bidir dq 0 output delay chainl inst dataout is connected to the bidirectional output delay chain 2 and the output bidir dq 0 output delay chain2 inst dataout is connected to the bidir dq io 0 pin The same data is propagated through the other inputs of bidir dq hr output data in 31 4 which causes the bidir dq io 7 1 pins to toggle in the same manner The throughput of data going out on each pin to the external memory is 666 666 Mbps The output delay chains are disabled The bidir dq 0 output delay chainl inst datain bidir dq 0 output delay chain2 inst datain bidir dq 0 output delay chainl inst dataout and bidir dq 0 output delay chain2 inst dataout signals are aligned which indicates that there s no delay settings on the two output delay chains The same write sequence applies to writing data with different delay chain values activated on the two output delay chains You can obtain the difference in the delay chain values by analyzing the timing paths of the following signals m bidir dq 0 output delay chainl inst datain m bidir dq 0 output d
12. Use Dynamic OCT Turned off Dynamic OCT is not used for input paths Add memory interface specific fitter grouping assignments Turned on 6 Onthe Advanced Options tab on the DOS IN page specify the parameters as shown in Table 2 6 These parameters configure the DOS input path of the DOS instance Table 2 6 Advance Options DQS IN Parameter Sub options Value Enable DQS Input Path Turned on Enable dqs delay chain Selected Advanced delay chain options Select dynamically using Turned off configuration registers DOS delay chain DLL delayctrlin port source The DQS delay chain settings is based on the DLL DOS Delay Buffer Mode Low Use the same mode selected in the DLL settings DOS Phase Shift 9000 Specify a 90 DQS phase shift The phase shift value must inter relate with the selected dqs delay chain stage Enable DOS offset control Turned off Disable DQS delay fine tuning using offset feature Enable DQS delay chain latches Turned off February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 2 9 Chapter 2 Getting Started Design Example Implementing Read Paths Using Stratix III Devices Table 2 6 Advance Options DQS IN Parameter Sub options Value Enable DQS busout delay chain Turned Enable 008 enable block Turned on 7 On the DO
13. l0 DDIO IN DQ Input register blocks Description Samples the DQ signal during a read operation These blocks are clocked by the core or by a clock pin The lt O gt _INPUT_FF block represents a group of flip flops registers in the DQ input path The lt O gt _DDIO_IN represents a group of double data rate input registers in the DQ input path l0 LOW and l0 HIGH Input Phase Alignment IPA Block Represents the circuitry required to phase shift the input signal This is primarily used to match the arrival delay of the DQS triggered by the fly by clock on a DDR3 DIMM to the latest arrival delay of a 005 from the DIMM The input phase alignment block levels or aligns the DQ group signals in the core using different phase shifts For more information about input phase alignment refer to the Leveling Circuitry section in the External Memory Interface chapter of the respective device handbooks l0 HALF RATE INPUT Half rate input registers block Represents the circuitry required to transfer the input signal from a full rate clock to a half rate clock Note that this block is only available in Stratix III and Stratix IV devices DELAY CHAIN Input Delay Chain For more information about the input delay chain refer to Table 4 2 on page 4 4 DQS CONFIG DQS For more information about the 05 CONFIG block refer to Configuration Table 4 2 on page
14. 201 Input Optional GND This port feeds the half rate output DQ OE signal for the OUTPUT DQ OE HR DDIO OUT datainhi datainlo ports February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide Chapter 4 Functional Description ALTDQ_DQS Megafunction Ports Table 4 17 Megafunction Ports to Configure DQ OE Path Part 2 of 2 Optional Port Name Type Required Default Description output dq oe in Input Optional GND This port feeds the bidirectional DQ OE signal for 1 0 the OUTPUT DQ OE FF d OUTPUT DQ OE DDIO OE oe OUTPUT OE DELAY CHAINI1 datain OUTPUT DQ OE DELAY CHAIN2 datain Or output dq oe out port output dq oe out Output Optional This port is driven by the n 1 0 OUTPUT DQ OE DELAY CHAIN2 dataout OUTPUT OE DELAY CHAIN1 dataout OUTPUT DQ OE FF q OUTPUT OE DDIO OE dataout Or output dq oe in port output dq sreset Input Optional GND This port is connected to all sreset ports in the 1 0 output DQ 10 primitives that is used to synchronously reset the registers in those primitives DQSn 1 0 Path Ports Table 4 18 summarizes all the ports that are specific to the DQSn I O other ports are shared with the DOS IO Table 4 18 Megafunction Ports to Configure DQSN IO Path Part 1 of 2 Port Name Ty
15. lt lO gt _OE_DELAY_CHAIN2 06 lO OE CHAINT 05 Uie io oe in 40 gt DDIO OE PM C CONFIG IO OE HR DDIO OUT io hr oe in dg hr output reg io areset io sreset io areset dq output reg clkena DQ OE PATH dq output reg Notes to Figure 4 5 1 The 0 output data out port must be connected to the input port of the output buffer 2 The O oe out port must be connected to the output enable port of the output buffer 3 The lt 0 gt HR DDIO OUT OUTPUT HR DDIO OUT HIGH and lt 0 gt OUTPUT HR DDIO OUT LOW blocks are half rate components February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 11 Chapter 4 Functional Description ALTDQ_DQS Megafunction The DQ output and OE path consist of the following blocks Table 4 5 DQ Output and OE Path Block lt 0 gt oU SEE l0 oU DDIO OUT DQ output register blocks Description Sends data directly to the external memory DQ pins during a write operation through the output buffer These blocks are clocked by the DQ write clock The lt O gt _OUTPUT_FF block represents a group of flip flop registers in the DQ output path The 0 OUTPUT DDIO OUT represents a group of double data rate outp
16. Procedure This section describes a design example that uses the DLL and DO DOS circuitry with half rate DDR2 external memory interface in Stratix III devices The memory interface is running at 333 333 MHz with 8 bit bidirectional pins a 1 bit output DQ pin and a 1 bit differential DOS pin The design examples are available next to the ALTDLL and ALTDO DOS Megafunction User Guides on the Documentation User Guides page of the Altera website This example describes the following steps m Instantiate the ALTDLL Megafunction m Instantiate the ALTDO DOS Megafunction m Instantiate the ALTIOBUF Megafunction Simulate the Design Instantiate the ALTDLL Megafunction To instantiate the ALTDLL megafunction perform the following steps 1 Open the altdll altdq dqs DesignExample ex2 zip project and extract the altdll altdq dqs design ex2 qar file 2 In the Quartus II software open the altdll altdq dqs design ex2 qar file and restore the archived file into your working directory 3 On the Tools menu click MegaWizard Plug In Manager Page 1 of the MegaWizard Plug In Manager appears 4 Select Create a new custom megafunction variation 5 Click Next Page 2a of the MegaWizard Plug In Manager appears Select ALTDLL and Verilog HDL and type the file name as dll inst v 6 On the Parameter Settings tab on the General page specify the parameters as shown in Table 4 24 These parameters configure the general settings f
17. ALTDQ_DQS Megafunction DQS Output OE Path This path sends the DQS strobe signal to the external memory for writing operations Figure 4 6 shows the available blocks in the DOS output and OE path and the connections with the ALTDO DOS ports Figure 4 6 005 Output and OE Path Note 1 2 3 DQS OUTPUT PATH das output data in ro DQS_OUTPUT_FF re nome Qs OUTPUT DELAY CHAINt E CH 968 output data high ant dgs_output_data_in_low DQS_OUTPUT_DDIO_OUT 0 4 IO CONFIG das hr output data in dgs output reg clk DQS OUTPUT HR DDIO OUT HIGH DQS OUTPUT HR DDIO OUT LOW a 4 5 dqs sreset dqs areset dqs output reg clkena dqs output reg EN DQS OE FF 4 945 oe out Om _ DQS OE DELAY CHAIN2 D6 la DQS OE DELAY CHAIN DS dgs oe in DOS OE DDIO OE a 10_CONFIG DQS OE HR DDIO OUT dqs hr oe in dqs hr output reg dqs areset dqs sreset dqs areset daqs output reg clkena dqs output reg DQS OE PATH Notes to Figure 4 6 1 4 output data out port must be connected to the input port of the output buffer 2 The das oe out port must be connected to the output enable port of the output buff
18. Figure A 1 Accessing the Clear Box Generator cx C WINDOWS system32 cmd exe Microsoft Windows Uersion 5 1 26001 lt C gt Copyright 1985 2001 Microsoft Corp H gt C gt altera 8 quartus bin iC altera 8 quartus bin gt clearbox altdq dqs dll f sample param test txt February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 2 Appendix A Clear Box Generator Clear Box Generator Options Clear Box Generator Options This section describes the options available when you generate the ALTDQ_DQS megafunction with the clear box generator To find out the available ports and parameters for this megafunction type the following command at the command prompt of your operating system clearbox altdq dqs dll h Figure 2 shows a sample listing of the available ports and parameters for the ALTDO DOS megafunction Figure A 2 Available Ports and Parameters for the ALTDQ_DQS Megafunction C altera 8 quartus bin gt clearbox altdq dqs lclearbox cbx dll name or mf name options parami value paran2 value porti port2 argument to clearbox can either be a clearbox DLL name or the megafunc tion name different_files Forces the generator to use separate files for subdesig Default ingle file Valid only for UHDL and Verilog f lt param_file gt Get parameter assignments and port selections from the given file r lt source_file gt Get parameter assignments and port
19. 11111111 0 2 1 00000000 10000000 ps 1630000 ps 1530050 ps 1755000 ps 2855000 ps 2955000 ps 3055000 ps 3230000 ps 3230750 ps E 8 LE 245 ns to 1580 ns Now 10 us Delta 16 y00 g 914 09 01 09 500 y 13 dey9 uondnasaq jeuonoung 9c v sasn 500 OGL pue TIQLTV 100107 Bally 2102 AueniqeJ Figure 4 21 shows the second part of the simulation results when the effects of the 50 ps delay has been propagated Figure 4 21 Second Part of the Simulation Results D1 is Set to 50 ps File Edit View Insert Format Tools Window default SMe Key sas QQ Bex top level signals 27 dq das vhd vec ist clk in 27 dq dqs vhd vec tst pll locked test da das vhd vec Ist bidir da interface 8 bit Ej dq das vhd vec tst bidir core dq oe enable EL dq dqs vhd vec Ist bidir core read data high dq das vhd vec Ist bidir core read data low 27 dq das vhd vec tst read das vhd vec tst bidir core dq config enable Configuring the delay chains 27 ftest_dq_dgs_vhd_vec_tst bidit_core_dq_config_enable 0 1 ftest_dq_dgs_vhd_vec_tst config_clk 27 dq das vhd vec Ist config datain 27 dq das vhd vec tst config update bserveing delay effects on bidirectional dq input path dq das vhd vec tst bidi
20. DELAY CHAIN dataout or DQS DELAY CHAIN dqsbusout port dqs enable ctrl clk Input Optional Voc This port is connected to the DQS ENABLE CTRL clk port that is used to capture the DOS ENABLE CTRL dqsenablein signal dqs enable ctrl hr Input Optional GND This port is connected to the datainhi DQS ENABLE CTRL HR DDIO OUT datainhi port This port receives the half rate data for the rising edge of the CLOCK DIVIDER clkout signal dqs enable ctrl hr Input Optional GND This port is connected to the datainlo DQS ENABLE CTRL HR DDIO OUT datainlo port This port receives the half rate data for the falling edge of the CLOCK DIVIDER clkout signal dqs enable ctrl in Input Optional Voc This active high port is connected to the DQS ENABLE CTRL dqsenablein port that is used to enable or disable the DQS ENABLE CTRL dqsenableout port ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description ALTDQ_DQS Megafunction Ports Table 4 11 Megafunction Ports to Configure DQS Input Path 4 34 Part 2 of 2 Port Name Type Optional Required Default Description dqs_enable_in Input Optional Vec This active high port is connected to the DQS ENABLE dqsenable that is used to enable or disable the DOS_ENABLE dqsbusout port When the dqs enable in port is connected to GND the DQS ENABLE dq
21. Design Example Implementing Read Paths Using Stratix Devices 8 On the Output Clocks tab on the clk c0 page specify the parameters as shown Table 2 2 You don t have to parameterize the other pages on the Output Clocks tab because you only use one clock for this design Table 2 2 ALTPLL Output Clocks clk c0 Settings Settings Value Use this clock Turned on Enter output clock frequency 150 Mhz Clock phase shift 0 deg Clock duty cycle 96 50 9 Click Finish 10 Click Finish The ALTPLL instance is generated 11 Click OK to close the Symbol window 12 Place the instance on the altdll altdq 495 design 1 Block Editor Generate the ALTDLL Megafunction To generate the ALTDLL megafunction perform the following steps D gx 59 Double click anywhere on the Block Editor window The Symbol window appears Click MegaWizard Plug In Manager Page 1 of the MegaWizard Plug In Manager appears Select Create a new custom megafunction variation Click Next Page 2a of the MegaWizard Plug In Manager appears Select Create a new custom megafunction variation Click Next Page 2a of the MegaWizard Plug In Manager appears Select ALTDLL and Verilog HDL and type the file name as dll 150MHz v On the Parameter Settings tab on the General page specify the parameters as shown in Table 2 3 These parameters configure the general settings for the ALTDLL instance Table 2 3 ALTDLL Gen
22. Enable DQ output purposes or SSN reduction D6 is a run time adjustable delay chain2 delay chain For more information about configuring delay chains dynamically refer to Delay Chains on page 4 15 00 Output Path Not used FF oUTPUT REG MODE Enables the full rate DQ output registers Options or DDIO l0 ouTPUT FF or OUTPUT DDIO OUT DQ output registers register mode DQ Output Enable USE DQ OE PATH Instantiates the DQ output enable path Options DQ Output Enable Options Enable DQ output enable delay chain1 USE_DQ_OE_DELAY Enables 0 oE DELAY CHAINI 05 in the DQ OE path This parameter is used for deskew purposes or SSN reduction D5 is a run time adjustable delay chain For more information about configuring delay chains dynamically refer to Delay Chains on page 4 15 ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 3 Parameter Settings 3 15 ALTDQ_DQS Parameter Editor Table 3 7 Options on DQ OUT OE Page Part 2 of 2 Parameter Name Legal Value Clear Box Parameter Name Description DQ Output Enable USE DQ OE DELAY Enables 0 DELAY CHAIN2 D6 the DQ OE Options CHAIN2 path This parameter is used for deskew purposes or Enable DQ output SSN reduction D6 is a run time adjustable delay chain enable delay For more information about configuring delay chains chain2
23. Options on Parameter Settings Page Part 2 of 2 Clear Box Parameter Name Legal Value Parameter Name Description Number of input 0 48 NUMBER OF Specifies the number of input DQ ports used in the 00 INPUT DQ DQS instance Number of output 0 48 NUMBER OF Specifies the number of output DQ ports used in the DQ OUTPUT_DQ 005 instance Number of stages 1 2 3 and 4 Dos DELAY CHAIN Specifies the stages of DOS DELAY CHAIN The in PHASE SETTING number of stages depends on the intended phase shift dqs delay chain that you want to clock for O block in the DQ input path The bigger the value you specify the longer the delay The coarse phase shift depends on this option For example in Stratix IV devices if you set the frequency mode to 1 you will get a phase shift of 20 60 90 or 120 If you set Number of stages in 105 delay chain value to 2 you will get 60 phase shift and if you set the Number of stages dqs delay chain value to 1 you will get 30 phase shift DOS input DQS_INPUT_ Specifies the input frequency of the DQS strobe in MHz frequency FREQUENCY The input frequency must match the DLL ALTDLL input frequency Use half rate USE_HALF_RATE Instantiates the half rate blocks in the ALTDQ_DQS components instance This parameter is used only when the external memory interface requires half rate mode Not supported in Arria Il GX devices Us
24. STATIC OFFSET with a range from 63 to 63 If the DLL OFFSET CTRL A USE OFFSET parameter is set to FALSE the value is added to the DLL delay setting value and appears as output on the dll offset ctrl a offsetctrlout 5 0 output bus Ifthe DL OFFSET A USE OFFSET parameter is set to TRUE ignore this value The default value is 0 February 2012 Altera Corporation ALTDLL and ALTDQ DQS Megafunctions User Guide 4 Table A 1 ALTDLL Megafunction Parameters Part 2 of 3 Appendix A Clear Box Generator Clear Box Generator Options Parameter Name Type DLL_OFFSET_CTRL_A_ String USE_OFFSET Required No Available values are T output of the dll offset ctrl output bus If set to T dll offset ctrl not the phase offset s dll offset ctrl Description RUE and FALSE It determines the a offsetctrlout 5 0 RUE then depending on whether the a addnsub input is asserted or pecified on the a offset 5 0 input bus is added or subtracted from the DLL delay setting output to get thedil offset ctrl a offsetctrlout 5 0 output If set to FALS E the phase offset specified by the DLL delay setting to get the dll offset ctrl a offsetctrlout 5 0 output If omitted the default is FALSE DLL OFFSET CTRL B STATIC OFFSET String No This is a Gray coded signed integer expressed as a string with a range from 63 to 63 If t
25. dataout ALTDQ_DQS 0 9 0 datain ALTIOBUF Note to Figure 4 13 1 The oe port is optional Figure 4 14 Output Only Differential cen g 10_OBUF ees ALTDQ_DQS datain a PSEUDO DIFF OUT T oe_n 7 10 OBUF dataout_n ALTIOBUF Note to Figure 4 14 1 The oe oe_n ports are optional ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description ALTIOBUF Megafunction and Delay Chains Integration Figure 4 15 Output Only Complementary 4 20 oe p 1 dataout IO IBUF p P a ES datain p ALTIOBUF ALTDQ_DQS dataout_n IO IBUF gt pk 5 datain_n ALTIOBUF Note to Figure 4 15 1 The oe_p and oe_n ports are optional Figure 4 16 Bidirectional Single Ended dyn_term_ctrl 7 z j 0 OBUF MN ALTDQ_DQS datain gt dataout e t IO IBUF ALTIOBUF Note to Figure 4 16 1 The dyn term ctr1 port is optional February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 21 Chapter 4 Functional Description ALTIOBUF Megafunction and Delay Chains Integration Figure 4 17 Bidirectional Differential
26. lt I0 gt _INPUT_FF ena and lt 0 gt _DDIO_IN ena ports dq ipa clk Input Optional GND This port feeds the clock signal for the l0 HIGH clkand 0 LOW clk ports input dq areset Input Optional GND This port is connected to all areset port in the E input DQ IO primitives that is used to n 1 0 asynchronously reset the registers in those primitives input dq hr input data Output Optional This port outputs the half rate DDR input DQ signal out 4 n 1 0 from the INPUT DQ HALF RATE INPUT dataout port input dq input data in Input Optional GND This port feeds the input DQ signal for the n 1 0 INPUT DQ INPUT DELAY CHAIN datain INPUT DQ INPUT FF d INPUT_DQ_DDIO_IN datain or input dq input data out port input dq input data ou Output Optional This port outputs the full rate DDR input DQ signal t high n 1 0 rising edge from the INPUT HIGH dataout or INPUT DQ DDIO IN regouthi input dq input data ou Output Optional This port outputs the full rate DDR input DQ signal t low n 1 0 falling edge from the INPUT DQ IPA LOW dataout or INPUT DQ DDIO IN regoutlo input dq input data ou Output Optional This port outputs the input DQ signal from the t n 1 0 INPUT DQ INPUT DELAY CHAIN dataout INPUT INPUT FF q Or input dq input data in port input dq sreset Input Optional GND This port is connected to all sreset ports in the n 1 0
27. 4 4 Block IO CONFIG 1 0 For more information about the t0_CONF1IG block refer to Table 4 2 Configuration on page 4 4 Block IO_CLOCK_DIVIDER 1 0 Clock Divider For more information about 1 0 clock divider block refer to Table 4 2 Block on page 4 4 ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description 4 10 ALTDQ_DQS Megafunction DQ Output OE Path This path sends the DQ signal to the external memory for writing operations Figure 4 5 shows the available blocks in the DQ Output and OE path and the connections with the ALTDQ_DQS ports 57 The value for IO depends on your selection in the parameter editor The possible values are BIDIR DQand OUTPUT DQ Figure 4 5 DQ Output and OE Path Note 1 2 3 DQ OUTPUT PATH io output data out 40 OUTPUT DELAY CHAIN2 06 Lig IO OUTPUT DELAY CHAIN1 05 io output data in low IO OUTPUT DDIO OUT lt 4 10 CONFIG io hr output data in dq output reg and lO OUTPUT HR DDIO OUT LOW lt 0 areset jo output data in IO OUTPUT FF r io output data in high and IO OUTPUT HR DDIO OUT HIGH io sreset io areset dq output reg clkena dq output reg clk lO FF re Lo
28. 5 MODE parameter is none When enabled the value may either Complementary pair or Differential pair 008 and DOSn 10 Configuration mode Differential pair or Complement ary pair DQS DQSN MODE If you turn on the Differential pair option the DQSn 1 0 pin is configured in a differential pair along with the DQS 0 pin This means that the OE and OCT paths are configured for the DQSn 1 0 pin which is similar to the DQS 1 0 pin The input and output paths are shared with the DQS 1 0 pin This mode is used mainly for DDR2 and DDR3 SDRAM and RLDRAM II applications If you turn on the Complementary pair option the DQSn 0 is configured in a complementary pair along with the DQS 1 0 pin In this mode the DQSn 1 0 pin is configured similarly to the DQS 1 0 pin This mode is used mainly for QDR QDR II applications Table 3 11 describes the options available on the Reset Config Ports page For more information about reset and config ports refer to DOS Megafunction Ports on page 4 33 Table 3 11 Options on Reset Config Ports Page Part 1 of 2 Clear Box Parameter Name Legal Value Parameter Name Description Reset ports Enables the asynchronous reset port that Create asynchronously resets all registers in the DQS output or dqs areset DQS OE path input port Reset ports Enables synchronous reset port that synchronously Create resets all registers in the DQS output
29. ALTDLL and ALTDO DOS megafunctions are specifically for memory interfaces that support memory burst lengths of two For common memory interfaces that support memory burst lengths of four Altera recommends that you use the ALTMEMPHY or UniPHY based memory controllers to take advantage of the benefits of Altera s IP and timing closure methodologies Ta For more information about the ALTMEMPHY or UniPHY based memory controllers that Altera offers refer to the volume 3 of the External Memory Interface Handbook Device Support The ALIDLL and ALTDO DOS megafunctions support the following Altera device families m Arria II GX HardCopy III HardCopy IV Stratix III Stratix IV February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 1 2 Chapter 1 About these Megafunctions Features Features The ALIDLL and ALTDO DOS megafunctions offer the following features m ALTDLL m A delay locked loop DLL block to center align the read strobe with read data Phase offset control blocks to fine tune the delay time on the read strobe using static or dynamic offset m ALTDO DOS Supports RLDRAM II memory interface DDR registers on the input and output paths to read or write to an external DDR interface Half rate registers to enable successful data transfers between the I O registers and the core logic Access to dynamic on chip termination OCT controls to switch between parallel termination during reads to seri
30. Activated 1 zons 40ns eons inclkO Bons 5 100 120ns rp Pa s 9 fons aons 20 260ns E Ons 300ns LEA aT locked J areset config clk J config_datain f YS config_update c2 TIA bidir dq io config ena 7 0 0 bidir dq hr oe in 15 0 bidir dq 0 oe ddio oe inst dataou bidir dq 0 oe hr ddio out inst dataou 3 bidir_dq_0_oe_delay_chain1_inst dataoui bidir dq 0 oe delay chain2 inst dataou 3 ass UU UU idir_dq_hr_output_data_in 31 0 00000000 FFFFFFFF I 00000000 7 bidir dq 0 output hr ddio out high inst dataou bidir dq 0 output hr ddio out low inst dataoui bidir dq 0 output ddio out inst dataoul output dq 0 output delay inst dataou output dq 0 output delay chain2 inst dataou bidir dq 0 output delay chain1 inst datain bidir dq 0 output delay chain2 inst datain bidir dq 0 output delay inst dataou bidir dq 0 output delay chain2 inst dataou bidir dq io 7 0 00 13 14 Wen dgs hr oe in 1 0 dqs hr output data in 3 0 dqs_output_hr_ddio_out_low_inst dataout 21017
31. DQ input register mode Legal Value Not used FF or DDIO Clear Box Parameter Name DO INPUT REG MODE Description Enables the DQ input registers INPUT FF or I0 DDIO IN registers Select FF if you want flip flop registers or DDIO if you want double data rate 1 0 registers DQ Input Register 005 bus ou DQ INPUT Specifies how the DQ input registers should be clocked Options t port SOURCE You can either clock it from the 045 bus port 005 DO input register Inverted input path the Inverted dqs_bus_out port 005 input clock source dqs bus ou path or directly from the Core FPGA 9r Altera recommends that you turn on the dqs bus out port option to clock the DQ input register When reading from the external memory the DQ data that comes into the DDIO must be center aligned with the DQS strobe that goes through the DQS input path and comes out the das bus out port By center aligning the DDIO with DQS strobe you maximize the setup and hold margins at the DQ input register You can also connect the dqs bus out port to the full rate DQ input register for complementary clocking purpose as used in QDR and QDR II applications You can connect the das bus out port by turning on the Connect DDIO clkn to 005 BUS from complementary DOSn option DQ Input Register Options Use DQ input phase alignment USE DO IPA Enables the input phase
32. LOW LOW HIGH This parameter determines whether the variable delay buffers are working in low frequency mode or high frequency mode DQS_PHASE_SHIFT Optional 0 36 000 This parameter indicates the phase shift between the delayed DQS signal and the input DQS signal in units of hundreds of degrees for example a 90 phase shift is represented as 9 000 This parameter is applicable only for static timing analysis because the phase shift through the delayctrlin 5 0 phasectrlin 2 0 and offsetctrlin 5 0 ports cannot be determined DQS_OFFSETCTRL_ENABLE Optional FALSE FALSE TRUE This parameter describes whether the offsetctrlin 5 0 inputs are used February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide A 8 Table A 3 Megafunction Parameters to Configure DQS Input Path Part 3 of 4 Appendix A Clear Box Generator Clear Box Generator Options Parameter Name Optional Required Default Legal Values Description DOS LATCHES ENABLE Optional FALSE FALSE TRUE This parameter describes whether the delayctrlin 5 0 and offsetctrlin 5 0 inputs are latched or not If set to TRUE only a DLL feeds the delayctrlin 5 0 input bus USE_DQS_ENABLE_CTRL_PHASE _CTRLIN Optional TRUE FALSE TRUE If set to TRUE the phase setting is determined by the phasectrlin input If set to FALSE the phase setting
33. chains 27 ftest_dq_dgs_vhd_vec_tst bidir_core_dq_contig_enable 0 27 ftest_dq_dgs_vhd_vec_tst config_clk 1 test_dq_dqs_vhd_vec_tst config_datain 27 test_dq_dqs_vhd_vec_tst config_update Observeing delay effects on bidirectional dq input path 27 jest dq dqs vhd vec Ist bidir dq interface 8 _ dq das vhd vec tst i1 Zinstl bidir dq input data in 0 test dq das vhd vec tst il instl bidir da 0 input delay chain Now Cursor 1 Cursor 2 Cursor 3 Cursor 4 Cursor 6 Cursor 7 Cursor 8 Cursor 9 Cursor 10 Cursor 11 Cursor 12 Cursor 13 Cursor 14 10000000 ps 1455000 ps 1555000 ps 1630000 ps 1630050 ps 1755000 ps 2855000 ps 2955000 ps 3055000 ps 3230000 ps 3230750 ps 0 Inn T i i RIT 1700 ns to 3100 ns Now 10 us Delta 16 9018 DISNOD 01 9HNOO 500 62 7 y 13 dey9 101141259 jeuonaung uonelodjo2 BAY 20102 094 195 suorounjeDeyy 500 11011 Figure 4 23 shows the fourth part of the simulation results when the effects of the 750 ps delay has been propagated Figure 4 23 Fourth Part of the Simulation Results D1 is Set to 750 ps Delay cS top level signals test_dq_dqs_vhd_vec_tst clk_in test_dq_dgs_vhd_vec_tst pll_locked dq das vhd vec tst bidir dq interface 8 bit test dq das vhd vec tst bidir core dq oe enable test_dq
34. coNrrG block dqsn io config ena Input Optional Vec Enable signal for the DOSN_IO_CONF IG block input_dq_io_config_ena Input Optional Vec Enable signal for the INPUT_DQ_IO_CONFIG n 1 0 block output dq io config ena Input Optional Vec Enable signal for the OUTPUT_DQ_IO_CONFIG block ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description Correct Settings for External Memory Interfaces Correct Settings for External Memory Interfaces Table 4 20 shows the correct settings required for the ALTDLL and ALTDQ_DQS megafunctions to work in the DDR QDR and RLDRAM interfaces 4 46 represents the number of pins in a path The value of n ranges from 0 to 48 but varies according to the memory interface used To determine the value of n for a particular memory interface the External Memory Interface chapter of the respective device handbooks Table 4 20 Correct Settings for DDR QDR and RLDRAM Interfaces QDR RLDRAM Parameter DDR read write read write RLDRAMII mode Unused Unused Turned on Refer to the ALTDQ_DQS Parameter Data mask pin grou Unused Unused Editor page 3 5 0 valid signal group Unused Unused Number of bidirectional DQ n 0 0 n Number of input DQ 0 n 0 0 Number of output DQ 0 0 n 0 Enable DQ output enable path Turned on Turned off Turned on Turned on Use
35. dataou j dqs_output_delay_chain1_inst dataoui dqs_output_delay_chain2_inst dataoui dqs_output_ddio_out_inst dataoui dqs io M x 12 2 8 9 10 17 18 111 WBNS ejdurex ubiseg 9 r y 1 2 uondisag jeuonaung Chapter 4 Functional Description 4 64 Design Example Implementing Half Rate DDR2 Interface in Stratix III Devices Reading Data from the External Memory The following sequence describes the transferring of data from the bidirectional DO pins to the FPGA core with various delay chain settings refer to Figure 4 26 on page 4 65 The interface to the external memory has a throughput of 666 666 Mbps during the read process In Figure 4 26 only the input paths are used therefore bidir dq hr oe in 15 0 16 1 and dqs_hr_oe_in 1 0 2 1 from 5 us onwards Each bit in the bidir dq io 7 0 pin is toggled with a 10 MHz data signal from 5 25 ps to 5 45 us The pin behavior is represented in the waveform in groups of 4 bit signals because the b dir dq io 0 input is connected to the bidir dq hr input data out 3 0 outputs Thebidir dq io 0 pinis connected to the input delay chain The output bidir dq 0 input delay chain inst dataout of the delay chain is connected to the input of the DDIO IN port which is clocked by a specialized DOS circuitry that uses the DLL The outputs bidir dq 0 ddio in inst
36. dqs inst v CBX OUTPUT DIRECTORY c Naltdq dgqswbasic CBX MODULE PREFIX UNLSED REMOVE OPTIONAL WIRES OFF CBXI INSTANCE NAME UNUSED device familysstratixiii use_dqs TRUE use dgs input path TRUE use dgs output path TRUE use_dqs_oe_path TRUE dqs_dqsn_mode DIFFERENTIAL number of bidir dq 8 With the text file you can generate output files using the following command clearbox altdq dqs dll f sample param test txt After the output files are generated you can instantiate the megafunction module into either a HDL file or a block diagram file in the Quartus II software To determine the resource usage for a particular configuration in the ALTDO DOS megafunction type the following command clearbox altdq dqs dll f sample param test txt resc count Clear Box Parameters Table 1 lists the Clear Box parameters for the ALTDLL megafunction Table A 1 ALTDLL Megafunction Parameters Part 1 of 3 Parameter Name Type Required Description DELAY BUFFER MODE String No Determines whether the DLL delay buffers are working in low frequency mode or high frequency mode Available values are LOW and HIGH The default value is Low DELAY CHAIN LENGTH Integer No This parameter represents the number of delay buffers in the delay loop The available values are 6 8 10 12 and 16 This parameter defaults to 12 DLL OFFSET A String No This is a Gray coded signed integer expressed as a string
37. dynamically refer to Delay Chains on page 4 15 DQ Output Enable Not used FF REG MODE Enables the full rate DQ output enable registers Options or DDIO lt 10 gt _ _ or lO DDIO OE registers DQ output enable register mode Select FF if you want flip flop registers or DDIO if you want double data rate 1 0 registers Table 3 8 describes the options available on the Half rate page Table 3 8 Options on Half Rate Page Part 1 of 2 Parameter Name Legal Value Clear Box Parameter Name Description 10 Clock Divider Core IO CLOCK DIVIDER Specifies the 1 0 clock divider clock source which can be Source 148 bus oU SOURCE from the Core FPGA the 145 bus port 005 t port or input path or the Inverted dqs bus port 005 Inverted input path a Altera recommends that you turn on the 105 bus port option to clock the DQ input register When reading from the external memory the DQ data that comes from the full rate DQ input registers must be synchronized to the half rate input block if half rate interfaces are used If the full rate DQ input registers are clocked by the DQS input path via the das bus out port then the 1 0 clock divider and other clock source settings must also be clocked via the dqs bus out port Create clock divider _masterin input port USE IO CLOCK DIVIDER MASTERIN Enables the mast erin inpu
38. instance is now generated 9 Browse to your working directory and open the input txt file 10 Change the value of the OUTPUT DIRI working directory 11 Save the file ECTORY parameter to the path of your 12 Copy the input txt file to the quartusii install dir NquartusNbinN directory February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 51 Chapter 4 Functional Description Design Example Implementing Half Rate DDR2 Interface in Stratix III Instantiate the ALTDQ_DQS Megafunction To instantiate the ALTDQ_DQS megafunction perform the following steps 1 On the Tools menu click MegaWizard Plug In Manager Page 1 of the MegaWizard Plug In Manager appears 2 Select Create a new custom megafunction variation 3 Click Next Page 2a of the MegaWizard Plug In Manager appears Select ALTDO DOS and Verilog HDL and type the file name as dq_dqs_inst v On the Parameter Settings page of the ALTDO DOS parameter editor specify the parameters as shown in Table 4 26 Table 4 26 Parameter Settings Parameter Value RLDRAM II Mode NONE Data mask pin group NONE Q valid signal group NONE Number of bidirectional 00 8 Number of input 00 0 Number of output DO 1 Number of stages dgs delay chain 2 DOS Input Frequency 333 MHz Use half rate components Turned on Use Dynamic OCT Turned off Add memory interface specific fitter grouping as
39. limited to a minimum value of 0 and a maximum value of 63 in low frequency mode and a maximum value of 31 in high frequency mode dll offset ctrl b addnsub Optional This is the addition subtraction control port for DLL OFFSET CTRL B block This port controls whether the delay offset setting B is added or subtracted Ignore this input if the DLL OFFSET B USE OFFSET parameter is set to FALSE If the input is the offset is added if it is GND the offset is subtracted This input defaults to Vec dll offset ctrl b offset 5 0 Optional This is the offset input setting for DLL OFFSET CTRL B block This is a Gray coded offset added or subtracted from the current value of the DLL s delay setting to get the dll offset ctrl b offsetctrlout result Ignore this input if the DLL OFFSET B USE OFFSET parameter is set to FALSE The offset is limited to a minimum value of 0 and a maximum value of 63 in low frequency mode and a maximum value of 31 in high frequency mode ALTDLL and ALTDQ DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description 4 32 ALTDLL Megafunction Ports Table 4 10 lists the output ports of the ALTDLL megafunction Table 4 10 ALTDLL Megafunction Output Ports Optional Port Name Required Default Function dll delayctrlout Required This is the DLL s delay setting output Th
40. on the megafunction the way a simulation can This is an optional field and defaults to 0 Advanced Delay Chain Options Enable 008 offset control DOS OFFSETCTRL ENABLE Enables offset values to be added to DQS DELAY CHAIN block If you turn on this option make sure that the ALTDLL instance is set to use the DLL offset control blocks This option connects the outputs from the DLL offset control blocks to the DQS delay chain block This parameter is optional and turned off by default February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 3 10 Table 3 4 Options on DQS IN Page Part 3 of 3 Chapter 3 Parameter Settings ALTDQ_DQS Parameter Editor Parameter Name Legal Value Clear Box Parameter Name Description Advanced Delay Chain Options Enable DQS delay chain latches DOS CTRL LATCHES ENABLE Enables the delayctrlin 5 0 and offsetctrlin 5 0 inputs to be registered by the dqsupdateen signal The DLL continues changing its delay settings value due to the feedback system These DLL values are propagated through the delayctrlout and offsetctrlout signals of the DLL and DLL offset control blocks to DQS DELAY CHAIN block to calibrate the necessary delay settings These values are updated based on the dll dqsupdate port from the DLL which is connected to the dqsupdateen port To use this option you must turn on the Create a use dqsup
41. or DQS OE path dqs sreset input port Reset ports Enables asynchronous reset port that asynchronously Create resets all registers in the DQ input path input dg areset input port February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 3 18 Table 3 11 Options on Reset Config Ports Page Part 2 of 2 Chapter 3 Parameter Settings ALTDQ_DQS Parameter Editor Clear Box config clk input port Parameter Name Legal Value Parameter Name Description Reset ports Enables synchronous reset port that synchronously Create resets all registers in the DQ input path input dq sreset input port Reset ports Enables asynchronous reset port that asynchronously Create resets all registers in the DQ output or DQ OE path output dg arese t input port Reset ports Enables synchronous reset port synchronously resets all Create registers in the DQ output or DQ OE path output dq srese t input port Reset ports Enables asynchronous reset port that asynchronously Create resets all registers in the bidirectional DQ 1 0 path bidir_dg_areset input port Reset ports Enables synchronous reset port that synchronously Create resets all registers in the bidirectional DQ 1 0 path bidir dq sreset input port Config ports Enables input clock port that feeds coNrF IG block Create for user driven dynamic delay chai
42. register has its bits arranged in correspondence with the values for datain datain values set during the first four configuration clock cycles corresponds to the 4 bit input delay chain values D1 datain values set during the next three configuration clock cycles corresponds to the 3 bit output delay chain values D6 datain values set during the last four configuration clock cycles corresponds to the 4 bit output delay chain values 05 February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 23 Chapter 4 Functional Description DQS_CONFIG IO CONFIG Block In all cases the most significant bit MSB of the delay chain values is shifted in first and the least significant bit LSB is shifted in last For example in the first four configuration clock cycles the first configuration clock cycle corresponds to the MSB of the input delay chain value and the fourth configuration clock cycle corresponds to the LSB The delay only takes effect when the config update signal is asserted for one configuration clock cycle in which all the bits in the serial shift register feeds an 11 bit parallel loaded register Right after the signal is deasserted you can observe the delay from datain ofthe delay chain primitive to dataout of the delay chain block For all delay chains each delay setting increment adds approximately 50 ps of delay the actual value depends on the device speed grade therefo
43. selections from the clearbox generated source file and regenerate the file resc_count Displays the estimated hardware resources used by the Clearbox generated design No HDL file generated ubs Generates TDF INC stub files amp UHDL component declaration of the clearbox generator The stubs are useful for handling clearbox generated design that have TDF equivalent version Returns the version of the specified DLL Version of a DLL is the timestamp of the last file changed in the DLL with the timestamp of all the DLLs it depends on quartus Returns the Quartus i on of the specified DLL gre ybox Generates a greybox the file if clearbox not al wailable or incomplete Greybox option can be used to even gene late greybox outputs for functio ithout clearbox greybox only Always generates a greybox output help Displa list of hidden advanced parameters and parameters common to all clearbox generato Required ports are assumed to be connected but optional ports must be listed as arguments to be considered by the generator The list of valid parameters for this megafunction are MODULE PREFIX UNUSED REMOUE OPTIONAL WIRES ON OFF NUSED LOWiHIGH DELAY _DQS__ENABLE_BY_HALF_CYCLE FALSE it TRUE device family DQ_HALF_RATE_US DQ_INPUT_REG_ DQ_INPUT REG CI DQ INPUT REG MODE NON DQ INPUT REG GH DQ INPUT REG SYNC MOD CLEAR i PRESET DQ_INPUT_REG_USE_CLKN FALSE i TRUE DQ_IPA_AD
44. the MODE PRESET NONE areset port Clears presets or has no effect on the DDIO register s The areset port is required if this parameter is set to CLEAR PRESET DQS_OUTPUT_REG_SYNC_ Optional NONE CLEAR This parameter determines if the MODE PRESET NONE sreset port clears presets or has no effect on the DDIO register s The sreset portis required if this parameter is Set tO CLEAR 0r PRESET Table A 5 summarizes the Clear Box parameters for the ALTDQ_DQS megafunction to configure the DQS OE path Table A 5 Megafunction Parameters to Configure DQS OE Path PRESET NONE Optional Parameter Name Required Default Legal Values Description USE DQS OE DELAY Optional FALSE FALSE TRUE Instantiates DOS OE DELAY CHAIN1 if TRUE USE DQS OE DELAY Optional FALSE FALSE TRUE Instantiates DOS OE DELAY CHAIN2 CHAIN2 if TRUE DQS OE REG MODE Optional NONE NONE FF Instantiates 005 FF if FF DDIO Instantiates Dos DDIO OEif DDIO DQS OE REG POWER UP Optional LOW LOW HIGH This parameter describes the power up condition of all registers in the primitive DQS OE REG ASYNC MODE Optional NONE CLEAR This parameter determines if the PRESET NONE areset port clears presets or has no effect on the DDIO register s The areset portis required if this parameter is set to CLEAR Of PRESET DQS_OE_REG_SYNC_MODE Optional NONE C
45. the I O config block and the delay chain block The CONFIG block controls the configuration of the necessary delay settings The necessary delay settings are set into the respective delay chain block D1 D5 and D6 These delay settings delay data that passes through the delay chain before going through the I O buffer block The ALTDO DOS megafunction allows you to control the delay chain using the following I O config signals config datain config clk config update xxx io config ena xxx depends on which I O pin is controlled input output bidirectional DOS or DOSn I O For more information about the DOS block or the DQSn I O block and the sequence of the shift registers refer to the I O Configuration Block and DQS Configuration Block section in Chapter 7 External Memory Interfaces in Stratix IV Devices of the Stratix IV Devices Handbook For more information about these ports refer to the DOS CONFIG IO CONFIG Megafunction Ports on page 4 45 Configuring Dynamic Delay Chains Using the 0 CONFIG Block The CONFIG block serially shifts the value of config datain only when Xxx io config ena is asserted during which you shift in the value of config datain to a shift register Because a 11 bit shift register is used in the IO CONFIG block you must hold xxx io config ena asserted for 11 configuration clock cycles config clk When the shift registers are fully loaded the shift
46. the clearbox parameter names are provided for the corresponding MegaWizard parameters The Parameter Settings page in the ALTDQ_DQS parameter editor allows you to configure the parameters in Table 3 3 February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 3 6 Chapter 3 Parameter Settings ALTDQ_DQS Parameter Editor Tahle 3 3 Options on Parameter Settings Page Part 1 of 2 Clear Box Parameter Name Parameter Name RLDRAMII mode Legal Value NONE x9 Description RLDRAMII MODE Enables RLDRAM II support for ALTDQ_DQS instance x18 or x36 If you select x9 or x18 mode the DK pins do not have group assignments but they must be placed in the same bank or chip edge as the other pins in the interface If you select X36 mode the DK DK pins must be placed manually in DQS locations If you select x18 mode place the DM pins in either group or group 1 which forces QVLD to the other group If you select X36 mode place the DM pins in group 0 or 1 and QVLD to be in group 0 or 1 All combinations are allowed Not supported in Arria II GX Data mask pin group NONE GROUPO or GROUP1 DM_LOC Specifies the group assignment for the DM pin group If you select NONE for the RLDRAMII mode option then this option defaults to NONE If you select x9 for the RLDRAMII mode option then this option defaults to NONE If you select x18 for the RLDRAMII mode option then for this optio
47. the data is sent at 666 666 Mbps the DOS write strobe clock signalis a 333 333 MHz DDR clock signal To obtain such a signal the dqs hr output data in 3 and hr output data in 2 signals go through a DDIO OUT port which is clocked at 166 666 MHz by the PLL clock output At the same time the dqs hr output data in 1 and dqs hr output data in 0 signals go through another DDIO OUT port which is clocked at 166 666 MHz by the c3 PLL clock output 16 Both outputs dqs output hr ddio out high inst dataout and dqs output hr ddio out low inst dataout ofthe previous DDIO OUT ports are channeled into another DDIO OUT port which is clocked at 333 333 MHz by the c1 PLL clock output 17 The output dqs output ddio out inst dataout is then connected to output delay chain 1 The output dqs output delay inst dataout is connected to output delay chain 2 18 The output dqs output delay chain2 inst dataout is connected to the dqs io pin which acts as a 333 333 MHz DOS write strobe clock signal For details about changing the delay chain values dynamically refer to the I O Buffer ALTIOBUF Megafunction User Guide February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide sasn 500 TIGLIV 100107 Bally 2100 AueniqeJ Figure 4 25 Data Transfer From the FPGA Core to the Bidirectional DQ Pin with No Delay Chains
48. the delay chain U L D ADS types and settings refer to Delay Chains on lt 0 gt _OUTPUT_DELAY_CHAIN2 D6 page 4 15 DQS OUTPUT DELAY CHAINI D5 06 February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 5 Chapter 4 Functional Description ALTDQ_DQS Megafunction Table 4 2 Common Blocks the DQ DQS Input and Output Paths Part 2 of 2 Block Name DQS CONFIG DQS Configuration Block IO CONFIG 1 0 Configuration Block Description A shift register that dynamically changes the settings of various device configuration bits The shift registers power up low The ro cour IG block is used to configure the settings for all 1 0 pins The ro coNrF IG block cannot configure the dynamic delay chains on the OCT path or on the DQS input path D2 D3 0 D3 1 D4 D5 OCT and D6 OCT that are controlled by the Dos coNrF IG block The pos cour re block is used to configure the settings of the DQ DQS 1 0 pins Note that these blocks are only available for Stratix and Stratix IV devices For more information about the 05 CONFIG IO CONFIG blocks refer to DQS CONFIG IO CONFIG Block on page 4 22 IO CLOCK DIVIDER 0 Clock Divider Block Represents a divide by 2 clock divider for transferring data to the core at one half the speed of the 1 0 input or output clock Each divider feeds up to six pins a x4 DQS group in the dev
49. time adjustable delay chain For more information about configuring delay chains dynamically refer to Delay Chains on page 4 15 OCT register mode Not used FF or DDIO OCT REG MODE Enables the full rate dynamic OCT registers lt 10 gt or lt 0 gt registers on both the DQ DQS dynamic OCT paths Select FF if you want flip flop registers or DDIO if you want double data rate 1 0 registers For more component information about this block refer to the Dynamic On Chip Termination Control section in the External Memory Interface chapter of the respective device handbooks ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 3 Parameter Settings ALTDQ_DQS Parameter Editor 3 17 Table 3 10 describes the options available on the DOSn I O page This page allows you to configure the DOS and DQSn I O pins for the ALTDO DOS instance These options are used for memory interfaces that need differential or complementary strobes Table 3 10 Options on DQS DQSn 1 0 Page Parameter Name Use 00 1 0 Legal Value Clear Box Parameter Name DQS DQSN MODE Description Enables access to the DQS 1 0 that is configured as either differential or complementary Altera recommends that you use differential DQS for DDR3 interfaces to improve signal integrity If the DQSn 1 0 is disabled the value for the DOS
50. used as output enable for the registers in those block dqs_sreset Input Optional GND This port is connected to the DOS OUTPUT FF sclr and 5 OUTPUT DDIO OUT sreset ports that is used to synchronously reset all registers in those blocks ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description 4 36 ALTDQ_DQS Megafunction Ports 005 OE Path Megafunction Ports Table 4 13 summarizes all the ports on the megafunction that configure the DQS OE path Table 4 13 Megafunction Ports to Configure DQS OE Path Optional Port Name Type Required Default Description dqs_areset Input Optional GND This port is connected to the Dos OE FF clrn 5 OE DDIO OE areset and DQS OE HR DDIO OUT areset ports that is used to asynchronously reset all registers in those blocks dqs hr oe in 1 0 Input Optional GND This 2 bit port is connected to the DQS OE HR DDIO OUT datainhi datainlo port that is used as the output enable for the half rate registers in that block dqs hr output reg Input Optional GND This port is connected to the DQS OE HR DDIO OUT clkhi clklo muxsel ports that is used to clock the half rate registers in those blocks dqs oe in Input Optional GND This port feeds the Dos DQS OE DDIO OE oe DQS OE DELAY CHAIN1 datain DQS OE DELAY CHAIN2 datain or dqs oe out port For info
51. window 10 Place the instance on the Block Editor T For more information about connecting all the instances refer to Integrate the I O Buffer Modules with the ALTDQ_DQS modules on page 4 55 11 On the Block Editor connect all the instances as shown in Figure 2 2 on page 2 11 Figure 2 2 Block Diagram of the Design Example 50 2 150 2 gil_delayctriout S_ 0 incikO frequency 50 000 MHz Operation Mode No Compensation Chain delay length 1 Delay buffer mode low Input frequency 150 2 Jitter reduction falsd dq dqs input path dgs bus out 0 input dg input data out high 7 0 input dg input data out 7 0 Custom dll delayctrlin S 0 input dg input data in 7 U inst2 5 2 111 XLS Bulsy sued peay ejduuex3 ubisaq pauejs Buray z 1 1 LL 2 12 Chapter 2 Getting Started Design Example Implementing Read Paths Using Stratix III Devices Compile and Simulate the Design On the Processing menu click Start Compilation to compile the design After the design is compiled you can view the implemention in the RTL Viewer You can also view the resource usage in the Compilation Report After you compile your design simulate the design in the ModelSim Altera software to generate a waveform display of the device be
52. with the external memory The settings are specified in the input txt file The block is customized for a half rate operation and represents the interface between the FPGA core and the O buffers that are connected to the external memory pins dqs iobuf inst inst2 This block represents the bidirectional 1 0 buffer that is used as the 005 strobe clock signal for interfacing with the external memory This block is in differential mode and is 1 bit wide It is connected to the dq dqs inst block bidir dq iobuf inst inst3 This block represents the bidirectional 1 0 buffer that is used as the DQ data signals for interfacing with the external memory This block is 8 bits wide It is connected to the dqs inst block output dq iobuf inst inst4 This block represents the output 1 0 buffer that is used as the DQ data signals for interfacing with the external memory This block is 1 bit wide It is connected to the dq_dqs_inst block February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 59 Chapter 4 Functional Description Design Example Implementing Half Rate DDR2 Interface in Stratix III Simulate the Design After instantiating the megafunctions perform the following steps to compile your design 1 9o COND OO Em gm In the Quartus II software on the Project menu click Add Remove Files in Project In the Category list select Files Next to the File name box cli
53. 0 output port When the jitter reduction circuit is enabled the DLL may require up to 1 024 clock cycles to lock When the jitter reduction circuit is disabled the DLL requires only up to 256 clock cycles to lock ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 3 Parameter Settings ALTDLL Parameter Editor 3 3 The DLL Offset Controls Optional Ports page allows you to instantiate the DLL offset control blocks A and B specify whether to use static offset and create the dll aloadand d11_dqsupdate optional ports Table 3 2 shows the options available on DLL Offset Controls Optional Ports page Table 3 2 Options on DLL Offset Controls Optional Ports Page Part 1 of 2 Parameter Name DLL Phase Offset Control A Instantiate dll offset ctri block Legal Value Set statically to or Set dynamically using offset input port Clear Box Parameter Name USE_DLL_OFFSET_ CTRL_A Description Instantiates DLL_OFF SET_CTRL_A block The block can be placed either at the top bottom or side of the FPGA device depending on how the Quartus II Fitter places it If you turn on this parameter you must specify whether you want to set the blocks statically or dynamically 63 to 63 DLL OFFSET CTRL A STATIC OFFSET The Set statically to option is a signed integer Turn on this option if you want a fixed offset value and key in the value you want Th
54. 4 Functional Description 4 18 ALTIOBUF Megafunction and Delay Chains Integration ALTIOBUF Megafunction and Delay Chains Integration You must instantiate the ALTIOBUF megafunction separately to configure the input buffer block output buffer block and differential output buffer block that are used together with the ALTDQ_DQS megafunction These I O buffers are used so that the impedance between the system and the external circuitry matches This implementation maximizes the power transfer and minimizes reflections from the external circuitry The ALTIOBUF megafunction must not be used to configure any dynamic delay chains The ALTIOBUF must only be used to configure the I O buffers to avoid conflict between the dynamic configuration and delay chain circuitry in the ALIDO DOS megafunction CAUTION The dynamic delay chains are controlled by the configuration circuitry encapsulated in the ALTDO DOS megafunction Each instance of the I O buffer uses the D1 D5 and D6 delay chains These delay chains are dynamically configured by the IO CONFIG and DQS_CONFIG blocks The CONFIG and DOS CONFIG blocks are a shift registers that change the delay settings in the I O buffers that are connected to the I O pins and DO and DOS I O pins respectively The CONFIG block cannot configure the dynamic delay chains on the OCT path or the DOS input path because these delay chains are configured by the DOS CONF IG block T For more information about
55. BIDIR IPA HIGH dataout Or BIDIR DQ DDIO IN regouthi bidir dq input ou Output Optional This port outputs the full rate DDR bidirectional DQ t low n 1 0 signal falling edge from the BIDIR IPA LOW dataout Or BIDIR DQ DDIO IN regoutlo February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 39 Chapter 4 Functional Description ALTDQ_DQS Megafunction Ports Table 4 15 Megafunction Ports to Configure DQ Input Path Part 2 of 2 Optional Port Name Type Required Default Description bidir dq input data ou Output Optional This port outputs the bidirectional DQ signal from t n 1 0 the BIDIR DELAY CHAIN dataout BIDIR_DQ_INPUT_FF 4q or bidir_dq_input_data_in port bidir dq sreset Input Optional GND This port is connected to all sreset port in the 1 01 bidirectional DQ IO primitives that is used to synchronously reset the registers in those primitives dll delayctrlin Input Optional GND This port receives the Gray coded delay chain setting 5 0 for the DQ read path from the delayctrlout 5 0 port of the ALTDLL dq input reg clk Input Optional GND This port feeds the clock signal for the l0 INPUT FF clkand O IN clk ports dq input reg clkena Input Optional Vec This port feeds the output enable signal for the
56. CTRL B The Set statically to option is a signed integer STATIC OFFSET Turn on this option if you want a fixed offset value and key in the value you want This fixed value is added to the DLL feedback counter and the output is generated on the dll offset ctrl b offsetctrlout 5 0 output port The default value is 0 DLL OFFSET CTRL B USE OFFSET The Set dynamically using offset input port option determines the output of the dll offset ctrl b offsetctrlout 5 0 output bus Turn on this option if you want a dynamic offset value If you turn on this option depending on whether the dll offset ctrl b addnsub signalis asserted or not the phase offset specified on the offset input bus is added or subtracted from the DLL feedback counter output to get the dll offset ctrl b offsetctrlout 5 0 output Optional Ports Create a 411 aload port DLL ALOAD Enables the asynchronous load signal for the DLL up or down counter When the 411 1 signal is high the counter is asynchronously loaded with the initial delay setting of 16 in low frequency mode when you select Low for the DOS Delay Buffer Mode parameter or 32 in high frequency mode when you select High for the DOS Delay Buffer Mode parameter This input defaults to GND Optional Ports Create a dil_dqsupdate port DLL DOSUPDATE Enables the update enable signal for the delay setting latches in the DQS pins This sig
57. Corporation Chapter 4 Functional Description 4 60 Design Example Implementing Half Rate DDR2 Interface in Stratix Ill Devices Understanding the Simulation Results This section describes the simulation results of Design Example Implementing Half Rate DDR2 Interface in Stratix Devices on page 4 49 Writing Data to the External Memory The following sequence describes the transferring of data from the FPGA core to the bidirectional DQ pins with various delay chain settings refer to Figure 4 25 on page 4 63 1 The simulation begins when the PLL is locked as indicated by the assertion of the locked signal at 225 000 ps refer to Figure 4 25 At this point the PLL input frequency as indicated by the inc1k0 signal is 200 MHz 2 The c0 c1 and c2 ports generate a 333 333 MHz clock output while the c3 port generates a 166 666 MHz clock output 57 This design example uses the half rate option which means that the FPGA core sends and receives data from the external memory interface at a half rate of 166 666 MHz The pin that interfaces with the memory toggles at 333 333 MHz However because this pin is also toggled by a DDIO OUT signal the data throughput is 666 666 Mbps 3 The output path from the FPGA core to the bidirectional DQ pin is represented by a 32 bit input bidir_dq_hr_output_data_in 31 0 The input path from the bidirectional pin to the FPGA core is represented by a 32 bit output bidir_dq_hr_input_da
58. D_INPUT_CYCLE_DELAY FALSE TRUE DYNAMIC DQ_IPA_ADD_PHAS ALSE i TRUE i DYNAMIC DQ_IPA_BYPASS_OUTPUT_REGISTER FA U DQ_IPA_INVERT_PHASE FALSE i TRUE iDYNAMIC DQ_IPA_PHASE_SETTING DQ OE REG fiSYNC MODE NONE CURARI PRESET DQ OE REG MODE NONE FF DDIO Q DQ OUTPUT REG MODE NONE t FF DQ_OUTPUT_REG_POWER_U ES_ENABLE PALSE ELAY_CHAIN_DELAYCTRLIN S SOURCE CORE DLL DQS DELAY CHAIN PHASE SETTING i DIFFERENTIAL ea kA ER RE 5 DQS_INPUT_FREQUENGY DQS_OE_REG_ASYNC_MODE NONE i CLEAR i PRESET DQS OE REG MODE NONE F 19 DQS OE REG POUER UP LOU HIGH DQS OE REG SYNC MODE NONE CLERR i PRESET DQS OFFSETCTRL ENRBLE FARLSE TRUE DQS OUTPUT REG 5 MOD DQS OUTPUT REG MODE NONE DQS OUTPUT REG UP LOU DQS OUTPUT REG SYNC MODE NONE CLER DQS_PHASE_SHIFT To efficiently generate output files for the ALTDQ_DQS megafunction Altera recommends that you use a text file to pass the required ports and parameters to the clear box generator This method promotes reusability and provides an easier way to customize the megafunction ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Clear Box Generator Options A 3 Figure 3 shows a sample text file used for the clear box generator Figure A 3 Sample Text File for Clear Box Generator sample_param_test txt Notepad File Edit Format View Help CBX HDL LANGUAGE Ver i log CBX FILE dq
59. ELAY CHAINI1 datain OUTPUT DQ OCT DELAY CHAIN2 datain or output dq oct out port output dq oct out Output Optional This port outputs signal from the 5 54 001 OUTPUT DQ DELAY CHAIN2 dataout OUTPUT OCT DELAY CHAIN1 dataout OUTPUT OCT FF q OUTPUT OCT DDIO OE dataout or output dq oct in port DQ Input Path Megafunction Ports Table 4 15 summarizes all the ports on the megafunction that configure the DO input path The possible values for IO are BIDIR_DQ and INPUT Table 4 15 Megafunction Ports to Configure DQ Input Path Part 1 of 2 Optional Port Name Type Required Default Description bidir dq areset Input Optional GND This port is connected to all areset port in the n 1 0 bidirectional DQ IO primitives that is used to asynchronously reset the registers in those primitives bidir_dq_hr_input Output Optional This port outputs the half rate DDR bidirectional DQ data out 4 n 1 0 signal from the BIDIR DQ HALF RATE INPUT dataout port bidir dq input data in Input Optional GND This port feeds the bidirectional DQ signal for the n 1 0 BIDIR_DQ_INPUT_DELAY_CHAIN datain BIDIR_DQ_INPUT_FF d BIDIR_DQ_DDIO_IN datain or bidir_dq_input_data_out port bidir dq input data ou Output Optional This port outputs the full rate DDR bidirectional DQ t high n 1 0 signal rising edge from the
60. FALSE the phase setting is determined by the phase setting parameter IO CLOCK DIVIDER PHASE SETTING Optional 0 7 This parameter determines the phase shift implemented by the delay chain if use phasectrlin is set to FALSE otherwise ignore this setting ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Clear Box Generator Options Table A 3 Megafunction Parameters to Configure DQS Input Path Part 4 of 4 A 9 Parameter Name Optional Required Default Legal Values Description IO CLOCK DIVIDER INVERT PHASE Optional FALSE FALSE TRUE DYNAMIC If set to TRUE the phase output is inverted If set to FALSE the phase output is not inverted If it is set to DYNAMIC the phaseinvertctrl input determines whether the inverter is used or not Use the inverter to increase the number of available phases USE IO CLOCK DIVIDER MASTERIN Optional FALSE FALSE TRUE If set to TRUE then the masterin input is used to synchronize this divider with another IO CLOCK DIVIDER If set to FALSE this divider operates independently this mode is meant for the master divider for a group of dividers IO CLOCK DIVIDER CLK SOURCE Optional Core Core 405 bus inverted dqs bus If Core IO CLOCK DIVIDER clk port on the primitive is fed by io clock divider 1 port on the megafunction If d
61. Format Tools Window SBBA 215 sas RELLE top level signals dq das vhd vec Ist clk in 27 dq das vhd vec tst pll locked EL dq dqs vhd vec Ist bidir dq interface 8 bit dq dqs vhd vec tst bidir core dq oe enable dq vhd vec tst bidir core read data high dq das vhd vec tst bidir core read dala low 27 fest dq das vhd vec tst read dq das vhd vec ist bidir core dq config enable Configuring the delay chains 7 ftest_dq_dgs_vhd_vec_tst bidir_core_dq_contig_enable 0 1 ftest_dq_dgs_vhd_vec_tst config_clk 1 jest dq dqs vhd vec Ist config datain 27 dq das vhd vec Ist config update Observeing delay effects on bidirectional dq input path 27 Atest dq vhd vec Ist bidir dq interface 8 bit U dq das vhd vec 181 1 idir ut data 0 5 jest dq das vhd vec tst il instl bidir da 0 input delay chain inst datain 27 dq das vhd vec tst i1 instl bidir 0 input delay chain inst dataout Now Cursor 1 Cursor 2 Cursor 3 Cursor 4 Cursor 5 Cursor 6 Cursor 7 Cursor 8 Cursor 9 Cursor 10 Cursor 11 Cursor 12 Cursor 13 Cursor 14 1111111 0 1 1 1 2 1 00000000 10000000 ps 1455000 ps 1555000 ps 1630000 ps 1630050 ps 1755000 ps 2855000 ps 2955000 ps 3055000 ps 3230000 ps 3230750 ps 4 41089 ps to 124241 ps Now 10 Delta 16 490 g DIANOD O
62. Functional Description Design Example Implementing Half Rate DDR2 Interface in Stratix III Table 4 29 Advance Options DQ IN Part 2 of 2 Parameter Sub options Value Use DQ half rate dataoutbypass port Turned off Use DQ input delay chain Turned on 8 Onthe DO OUT OE page specify the parameters as shown in Table 4 30 These parameters configure the DO OUTPUT and DQ OE path of the ALTDO DOS instance Table 4 30 Advance Options DQ OUT OE Parameter Value Enable DQ output delay chain1 Turned on Enable DQ output delay chain2 Turned on DQ output register mode DDIO Enable DQ output enable Turned on Enable DQ output enable delay 1 Turned on Enable DQ output enable delay chain2 Turned on DQ output enable register mode DDIO 9 On the Half rate page specify the parameters as shown in Table 4 31 These parameters configure the half rate settings of the ALTDQ_DQS instance Table 4 31 Advance Options Half Rate Parameter Value 10 Clock Divider Source Core Create io_clock_divider_masterin input port Turned off Create io clock divider clkout output port Turned on Create io clock divider slaveout output port Turned off 10 Clock Divider Invert Phase Never 10 On the DOSn I O page specify the parameters as shown in Table 4 32 Table 4 32 Advanced Options 005 005 10 Parameter Value Use DOSn 10 Turned on DQS and DQS
63. I 9IHNO9 500 y 13 dey9 uondnasaq jeuonoung v v 4 25 Chapter 4 Functional Description DQS_CONFIG I0 CONFIG Block Setting the Input Delay Chain to 50 ps Delay In Figure 4 20 cursor 3 255 ns to cursor 4 1355 ns show that the delay chain is configured to 50 ps The con ig clock takes 11 1 100 ns clock cycles to load the intended delay values into the IO CONFIG block because of the first four clock cycles for the input delay chain D1 the next three clock cycles for the output delay chain 2 D6 and the last 4 clock cycles for the output delay chain 1 D5 The following steps describe how the input delay chain changes 1 Because there is a 11 bit shift register in the I0 CONFIG block bidir core dq confiq enable 0 is asserted for 11 clock cycles When the shift registers are fully loaded the shift registers have their bits arranges to correspond with datain values 2 The config datain signal is asserted at the 4th clock cycle to change the input delay chain value 3 The delay only takes effect when the config update signal is asserted for one clock cycle at 1455 000 ps Cursor 5 4 After the config update signal is deasserted the delay from bidir dq 0 input delay chain inst datain at 1630 000 ps Cursor 7 to bidir dq 0 input delay chain inst dataout at 1630 050 ps Cursor 8 is noticeable which is 50 ps Refer to Figure 4 21 ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 A
64. IN l0 INPUT DELAY CHAIN if TRUE DQ INPUT REG MODE Optional NONE NONE FF DDIO Instantiates lt O gt _INPUT_FF if FF Instantiates lt O gt _DDIO_IN if DDIO DQ_INPUT_REG_POWER_UP Optional LOW LOW HIGH This parameter describes the power up condition of all registers in the primitive DQ_INPUT_REG_ASYNC_MODE Optional NONE CLEAR PRESET This parameter determines if the areset portclears presets or has no effect on the DDIO register s The areset port is required if this parameter is set to CLEAR or PRESET DQ_INPUT_REG_SYNC_MODE Optional NONE CLEAR PRESET NONE This parameter determines if the sreset port clears presets or has no effect on the DDIO register s The sreset port is required if this parameter is set to CLEAR Or PRESET February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide A 12 Table A 7 Megafunction Parameters to Configure DQ Input Path Part 2 of 3 Appendix A Clear Box Generator Clear Box Generator Options Parameter Name Optional Required Default Legal Values Description DQ_INPUT_REG_CLK_SOURCE Optional dqs bus dqs bus Core If Core lt 0 gt INPUT l0 IN clk port on the primitive is fed by dq input reg 1 port on the megafunction If dqs bus lt O gt _INPUT_FF clk l0 DDIO 1 port on the primitive is fed by dqs bus out port on the megafuncti
65. LEAR This parameter determines if the sreset port clears presets or has no effect on the DDIO register s The sreset portis required if this parameter is set to CLEAR Of PRESET ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Clear Box Generator Options A 11 Table 6 summarizes the Clear Box parameters for the ALTDQ_DQS megafunction to configure the OCT path The possible values for IO are DOS DOSn BIDIR OUTPUT DQ Table A 6 Megafunction Parameters to Configure OCT Path Optional Parameter Namer Required Default Legal Values Mapping to Suh Blocks USE OCT DELAY CHAIN1 Optional FALSE FALSE TRUE Instantiates l0 OCT DELAY CHAINI if TRUE USE OCT DELAY CHAIN2 Optional FALSE FALSE TRUE Instantiates l0 OCT DELAY CHAIN2 if TRUE MODE Optional NONE NONE FF DDIO Instantiates O FF if FF Instantiates lt 0 gt DDIO Table 7 summarizes the Clear Box parameters for the ALTDQ_DQS megafunction to configure the DQ input path The possible values for lt IO gt are BIDIR_DQ and INPUT_DO Table A 7 Megafunction Parameters to Configure DQ Input Path Part 1 of 3 NONE Optional Parameter Name Required Default Legal Values Description USE DQ INPUT DELAY Optional FALSE FALSE TRUE Instantiates CHA
66. LTDO DOS instance On the DOSn I O page turn off the Use DOSn I O option because the design is not using DOSn When you turn off the Use DOSn I O option the other options on this page are disabled In the Reset Config Ports tab tun off all the parameters Click Finish Click Finish The ALTDO DOS instance is generated Click OK to close the Symbol window Place the instance on the Block Editor ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 2 Getting Started Design Example Implementing Read Paths Using Stratix Devices Generate the ALTIOBUF Megafunction 2 10 You must generate the ALTIOBUF megafunction to set the following I O buffer settings m 1 input buffer for input DOS pin m 8 input buffers for input DQ pins To generate the ALTIOBUF megafunction perform the following steps 1 Double click anywhere on the Block Editor window The Symbol window appears 2 Click MegaWizard Plug In Manager Page 1 of the MegaWizard Plug In Manager appears 3 Select Create a new custom megafunction variation 4 Click Next Page 2a of the MegaWizard Plug In Manager appears Select ALTIOBUEF and Verilog HDL and type the file name as ibuf_input_dqs v for DOS pin or ibuf input dq v for DQ pins 5 On the Parameter Settings page specify the parameters as shown in Table 2 8 These parameters configure the general settings for the ALTIOBUF instance Table 2 8 ALTIOBUF Gene
67. N Used Used INPUT DQ INPUT DATA OUT HIGH Used Unused INPUT DQ INPUT DATA OUT LOW Used Unused HR INPUT DATA OUT Unused Used OUTPUT DQ OUTPUT DATA OUT Used Used OUTPUT DQ OUTPUT DATA IN LOW Used Unused OUTPUT DQ OUTPUT DATA IN HIGH Used Unused OUTPUT DQ HR OUTPUT DATA IN Unused Used OUTPUT DQ HR OE IN Unused Used OUTPUT DQ OE IN Used Unused OUTPUT DQ OE OUT Used Used BIDIR INPUT DATA Used Used BIDIR DQ HR INPUT DATA OUT Unused Used BIDIR DQ OUTPUT DATA OUT Used Used BIDIR DQ HR OUTPUT DATA IN Unused Used DQS INPUT DATA Used Used DQS HR OUTPUT DATA Unused Used DQOSN INPUT DATA Used Used DQSN HR OUTPUT DATA Unused Used DOS BUS OUT Used Used DOS OUTPUT DATA OUT Used Used DQ INPUT REG CLK Used Used DQ OUTPUT REG CLK Used Unused DQ HR OUTPUT REG CLK Unused Used DLL DELAYCTRLIN Used Used IO CLOCK DIVIDER Used Used ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description Correct Settings for External Memory Interfaces 4 48 Table 4 22 shows the correct OCT parameter settings for the DDR QDR and RLDRAM interfaces Table 4 22 General OCT Parameter Settings for DDR QDR and RLDRAM Interfaces Controller Parameter Full Rate Half Rate Enable Dynamic OCT Turned on Turned on Enable OCT delay chain 1 Turned on Turned off Turned on Turned off Enable OCT delay chain 2 Turned on Turned of
68. ONE CLEAR This parameter determines if the areset PRESET port clears presets or has no effect on the NONE DDIO register s The areset port is required if this parameter is set to CLEAR Or PRESET DQ_OUTPUT_REG_SYNC_MODE Optional NONE CLEAR This parameter determines if the sreset PRESET port clears presets or has no effect on the NONE DDIO register s The sreset port is required if this parameter is set to CLEAR Or PRESET February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide A 14 Table A 9 Megafunction Parameters to Configure DQ OE Path Appendix A Clear Box Generator Clear Box Generator Options Table 9 summarizes the Clear Box parameters for the ALTDQ_DQS megafunction to configure the DQ OE path The possible values for IO are BIDIR_DQ and OUTPUT Optional Legal Parameter Name Required Default Values Description USE DQ OE DELAY Optional FALSE FALSE Instantiates O OE DELAY CHAINIif CHAIN1 TRUE TRUE USE DQ OE DELAY Optional FALSE FALSE Instantiates O DELAY CHAIN if CHAIN2 TRUE TRUE DQ OE REG MODE Optional NONE NONE FF Instantiates O if FF DDIO Instantiates O OEif DDIO OE REG POWER UP Optional LOW LOW HIGH This parameter describes the power up condition of all registers in the primitive OE REG ASYNC MODE Optional NONE CLEAR This para
69. Ports Table 4 9 lists the input ports for the ALTDLL megafunction Port Name dll aload Optional Required Optional Default GND Description Asynchronous load signal for the DLL counter When d11 aloadis HIGH the counter is asynchronously loaded with the initial delay setting of 16 in low frequency mode when the parameter DELAY BUFFER MODE is set to Low or 32 in high frequency mode when the parameter DELAY BUFFER MODE iS set to HIGH dll Required GND DLL reference clock that matches the frequency of the DQS clock used to determine the delay for the phase shift Feed this input by an input pin or a PLL output This input must match the polarity of its source and cannot be inverted dll offset ctrl a addnsub Optional Addition subtraction control port for DL OFFSET CTRL A block This port controls whether the delay offset setting A is added or subtracted Ignore this input if the DLL OFFSET A USE OFFSET parameter is set to FALSE If the input is the offset is added if it is GND the offset is subtracted dll offset ctrl a offset 5 0 Optional This is the offset input setting for DLL OFFSET CTRL A block This is a Gray coded offset added or subtracted from the current value of the DLL s delay setting to get the dll offset ctrl a offsetctrlout result Ignore this input if the DLL OFFSET USE OFFSET parameter is set to FALSE The offset is
70. QS input used to ground Block the DQS input strobe when the strobe goes to Z after a DDR read postamble The Dos ENABLE block enables the registers to allow enough time for the DQS delay settings to travel from the DQS phase shift circuitry or core logic to all the DQS logic blocks before the next change For more information about the DQS enable block refer to the Update Enable Circuitry section in the External Memory Interfaces chapter of the respective device handbooks DOS DELAY CHAIN DQS Delay For more information about these delay chains refer to Table 4 2 Chain Block on page 4 4 DOSBUSOUT DELAY CHAIN DQS Busout Delay Chain DOS ENABLE DELAY CHAIN DQS Enable Delay Chain 05 CONFIG DQS For more information about Dos CONF IG block refer to Configuration Table 4 2 on page 4 4 Blocks IO CLOCK DIVIDER 1 0 Clock For more information about 1 0 clock divider block refer to Divider Block Table 4 2 on page 4 4 ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description 4 8 ALTDQ_DQS Megafunction DQ Input Path This path receives the DQ signal from the external memory during read operations Instantiate this path for all input only and bidirectional DQ I O pins Figure 4 4 shows the available blocks in the DQ input path and the connections with the ALTDO DOS ports gt The value for IO depends on your selection in the para
71. Quartus II software restore the altdll altdq dqs design 1 file into your working directory Open the altdll altdq dqs design exl1 bdf file Generate the ALTPLL Megafunction Before generating the ALTDLL and ALTDO DOS megafunctions you must generate the ALTPLL megafunction first by performing the following steps Qu P ub 99 Double click anywhere on the Block Editor window The Symbol window appears Click MegaWizard Plug In Manager Page 1 of the MegaWizard Plug In Manager appears Select Create a new custom megafunction variation Click Next Page 2a of the MegaWizard Plug In Manager appears Select Create a new custom megafunction variation Click Next Page 2a of the MegaWizard Plug In Manager appears Select ALTPLL and Verilog HDL and type the file name as PLL_50MHz v On the Parameter Settings tab on the General Modes page specify the parameters as shown in Table 2 1 These parameters configure the general settings for the ALTPLL instance Table 2 1 ALTPLL Parameter Settings Settings Value Currently selected device family Stratix 111 Match project default Turned on What is the frequency of the inclock0 input 50 MHz How will the PLL outputs be generated With no compensation This option is selected because the PLL is used to clock the ALTDLL instance only ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 2 Getting Started 2 6
72. S OUT OE page turn off the Enable DOS output path option When you deselect the Enable DOS output path option the other options on this page are disabled On the DQ IN page specify the parameters as shown in Table 2 7 These parameters configure the input path of the ALTDO DOS instance Table 2 7 Advance Options DQ IN Options Value DQ input register mode DDIO Select DDIO to enable double data rate capture for 00 DQ input register clock source dqs_bus_out port and turn off Connect DDIO clkn to DOS BUS from complementary D Sn Use DQ input phase alignment Turned off The feature is for half rate components the design uses full rate memory components Use DQ input delay chain Turned on 9 10 11 12 13 14 15 16 17 On the DO OUT OE page all the options are automatically disabled because the design is not using output DQ The parameters on this page configure the DQ output and OE paths of the ALTDO DOS instance On the Half rate page for the IO Clock Divider Invert Phase parameter turn on Never because the design requires full rate components The other options are automatically disabled The parameters on this page configure the half rate settings of the ALTDO DOS instance On the OCT Path page all the options are automatically disabled because the design is not using input and output DOS or bidirectional DQ The parameters on this page configure the OCT path of the A
73. SE DQS DELAY CHAIN Optional FALSE FALSE TRUE Instantiates DOS DELAY CHAIN if TRUE USE DQS ENABLE Optional FALSE FALSE TRUE Instantiates DOS ENABLE if TRUE USE DQS ENABLE CTRL Optional FALSE FALSE TRUE Instantiates DOS ENABLE TRUE USE 05 0500 DELAY CHAIN Optional FALSE FALSE TRUE Instantiates DQSBUSOUT DELAY CHAIN if TRUE USE DOSENABLE DELAY CHAIN Optional FALSE FALSE TRUE Instantiates DQSENABLE DELAY CHAIN if TRUE DQS FREQUENCY Optional UNUSE This parameter is set to the frequency D of the DQS strobe clock input expressed as a string and if phase setting is not set to 0 and use phasectrlin is not set to FALSE this needs to match the input frequency parameter of the DLL feeding the delayctrlin 5 0 input This is an optional field and defaults to UNUSED DQS DELAY CHAIN Optional Core DLL This parameter is the Gray coded delay DELAYCTRLIN SOURCE DLL chain setting for the DQS read path This is an optional input and defaults to GND You can ignore this input if the use phasectrlin parameter is set to FALSE and phase setting is set to 0 You can feed this input by the delayctrlout output of a DLL or the core This input does not need to match the polarity of its source and can be inverted unless fed by the delayctrlout output of a DLL ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporati
74. S_ENABLE_CTRL gt DQS_ENABLE_DELAY_CHAIN Db dgs_enable_ctrl_hr_datainhi das enable ctrl hr datainlo io clk divider clk DQS ENABLE CTRL HR DDIO OUT A io_clock_divider_clkout clkout io_clk_divider_masterin IO CLOCK DIVIDER io clock divider slaveout delayctrlin gt Notes to Figure 4 3 1 The dqs_input_data_in port must be connected to the output port of the input buffer 2 dll_offsetctrlin dll_delayctrlin and dqsupdateen ports must be connected to the DLL February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 7 Chapter 4 Functional Description ALTDQ_DQS Megafunction The DQS input path consists of the following blocks Table 4 3 DQS Input Path Block Name Description DQS ENABLE CTRL DQS Enable Represents the circuitry to control the DQS enable block Each 005 Control Block enable block can be controlled by a DQS enable control block For more information about the DQS enable control refer to the DQS Postamble Circuitry section in the External Memory Interface chapter of the respective device handbooks DQS_ENABLE_CTRL_HR_DDIO DQS Enable Represents the circuitry to transfer input to the _OUT Control Half DQS ENABLE block froma half rate clock to a full rate Rate Block clock DQS ENABLE DQS Enable Represents the AND gate control on the D
75. Use round trip delay RTD analysis or create a custom data training circuitry to write and read back a training pattern to and from the memory device and then dynamically adjust the PLL s resyncronization clock phase to find an efficient working phase Even though this block controls the DQS enable signal the megafunction does not consider the necessary timing for this signal Refer to the external memory interface requirements for the necessary timing ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 3 Parameter Settings ALTDQ_DQS Parameter Editor Table 3 4 Options on DQS IN Page Part 2 of 3 3 9 Parameter Name Legal Value Clear Box Parameter Name Description Enable DQS enable block delay chain Enables 005 ENABLE DELAY CHAIN Db that fine tunes the outputs of Dos ENABLE CTRL block so that the DQS enable signal timing matches the DQS strobe Db is a run time adjustable delay chain Advanced Delay Chain Options Set dynamically using configuration registers USE DOS DELAY CHAIN PHASECTRLIN Determines the phasect rlin input for the phase setting If you turn on this option it dynamically chooses the phase applied to the dgsbusout output during the FPGA run time If you turn off this option the phase setting is determined by the Number of stages in 145 delay chain option in the Parameter Settings page This delay chain fine tunes the DQS strob
76. _DQS Megafunction Ports Part 2 of 2 Port Name Type Optional Required Default Description dq output reg clkena Input Optiona Vec This port feeds the output enable signal for the l0 OUTPUT FF ena and l0 OUTPUT DDIO OUT ena ports output dq areset 21 0 Input Optiona GND This port is connected to all areset port in the output DQ IO primitives that is used to asynchronously reset the registers in those primitives output dq hr output data in 4 n 1 0 Input Optiona GND This port feeds the half rate DDR output DQ signal for the OUTPUT_DQ_OUTPUT_HR_DDIO_OUT_HIGH datainhi datainlo and OUTPUT DQ OUTPUT HR DDIO OUT LOW datainhi datainlo ports output dq output data in high n 1 0 Input Optiona GND This port feeds the full rate DDR output DQ signal rising edge for the OUTPUT DQ OUTPUT DDIO OUT datainh i port output dq output data in low n 1 0 Input Optiona GND This port feeds the full rate DDR output DQ signal falling edge for the OUTPUT DQ OUTPUT DDIO OUT datainl o port output dq output data in n 1 0 Input Optiona GND This port feeds the output DQ signal for the OUTPUT_DQ_OUTPUT_FF d OUTPUT_DQ_OUTPUT_DELAY_CHAIN1 dat ain OUTPUT_DQ_OUTPUT_DELAY_CHAIN2 dat ain Of output_dgq_output_data_out port
77. _dgs_vhd_vec_tst bidir_core_tead_data_high test dq das vhd vec Ist bidir core read data low 27 dq das vhd vec tst read dq das vhd vec tst bidir core dq config enable Configuring the delay chains 27 test dq das vhd vec tst bidit core dq config enable 0 fest dq das vhd vec tst config 27 dq das vhd vec tst config datain 27 jest dq das vhd vec tst config update bserveing delay effects on bidirectional dq input path dq das vhd vec tst bidir dq interface 8 bit dq das vhd vec tst i1 instl bidir input data 0 dq das vhd tst i1 instl bidir dq 0 input delay chain inst datain test dq vhd vec tst i instl bidir dq 0 input delay chain inst dataout yi QQ gt Now 10000000 ps Cursor 1 Ops Cursor 2 70000 ps Cursor 3 255000 ps Cursor 4 1355000 ps 1455000 ps Cursor 6 1555000 ps Cursor 7 1630000 ps Cursor 8 1630050 ps Cursor 9 1755000 ps Cursor 10 2855000 ps Cursor 11 2955000 ps Cursor 12 3055000 ps Cursor 13 3230000 ps Cursor 14 3230750 ps RIT Hu 3224636 ps to 3235578 ps Now 10 us Delta 16 9018 DIANOD OI 9IHNO9 500 y 13 dey9 uondiuasag jeuonoung 0 7 4 31 ALTDLL Megafunction Ports This section describes the ports of the ALTDLL megafunction Table 4 9 ALTDLL Megafunction Input Ports Chapter 4 Functional Description ALTDLL Megafunction
78. a dasn hr oe in 1 0 io 9495 io config ena output dq io config ena output dq hr oe 1 0 output dq 0 oe hr ddio out inst dataou output dq 0 oe ddio oe inst dataou output dq 0 oe delay chain inst dataou output dq 0 oe delay chain2 inst dataout output dq hr output data in 3 0 Y output dq 0 output hr ddio out high inst dataou output dq 0 output hr ddio out low inst dataout output dq 0 output ddio out inst dataou 9 III 6 ajdwex3 ubiseg 69 y 1 2 013119590 jeuonaung A Clear Box Generator Using Clear Box Generator You can use the clear box generator a command line executable to configure parameters that are not available in the ALTDQ_DQS parameter editor The clear box generator creates or modifies design files that contain custom megafunction variations which can then be instantiated in a design file To run the clear box generator perform the following steps 1 Type the following command at the command prompt of your operating system lt quartusii_install_dir gt quartus bin 2 The executable name is clearbox exe To use the executable type the following command clearbox altdq_dgqs dll f txt where txt represents one or more text files containing the ports and parameters that you want to generate refer to Figure 1
79. alignment lt 0 gt IPA LOW or lt 0 gt HIGH blocks The input phase alignment blocks represent the circuitry required to phase shift the input signal the DQ data for resynchronization and alignment purpose The resynchronization and alignment are done to match the arrival delay of the DQS triggered by the fly by clock on a DDR DIMM to the latest arrival delay of a DQS from the DIMM Because this block is meant for resynchronization the ALTDQ DQS megafunction does not consider the clocking requirements of this block You must figure the clocking requirements using the RTD analysis or create a custom data training circuitry to read or write back a training pattern to and from the memory device and then dynamically adjust the PLL s resyncronization clock phase to find a good working phase For more component information about the available alignment and resynchronization registers in this block refer to the I O Element IOE Registers section in the External Memory Interface chapter of the respective device handbooks For the available levelling delay chains in this block refer to the Leveling Circuitry section in the External Memory Interface chapter of the respective device handbooks ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 3 Parameter Settings 3 13 ALTDQ_DQS Parameter Editor Table 3 6 Options on DQ IN Page Part 2 of 3
80. ary 2012 Altera Corporation Clear Box Generator Options A 13 Table A 7 Megafunction Parameters to Configure DQ Input Path Part 3 of 3 Optional Parameter Name Required Default Legal Values Description DQ IPA INVERT PHASE OptionalO FALSE FALSE TRUE l0 HIGH invert phase DYNAMIC port on the primitive l0 LOW invert phase port on the primitive HALF RATE USE Optional FALSE FALSE TRUE l0 HALF RATE INPUT use DATAOUTBYPASS dataoutbypass port on the primitive Table A 8 summarizes the Clear Box parameters for the ALTDO DOS megafunction to configure the DQ output path The possible values for IO are BIDIR_DQ and OUTPUT Table A 8 Megafunction Parameters to Configure DQ Output Path Optional Parameter Name Required Default Legal Values Description USE DQ OUTPUT DELAY Optional FALSE FALSE TRUE Instantiates CHAIN1 l0 OUTPUT DELAY CHAINI if TRUE USE DQ OUTPUT DELAY Optional FALSE FALSE TRUE Instantiates CHAIN2 l0 OUTPUT DELAY CHAIN if TRUE DQ OUTPUT REG MODE Optional NONE NONE FF Instantiates port on the primitive if FF DDIO Instantiates lt IO gt _OUTPUT_DDIO_OUT if DDIO DQ_OUTPUT_REG_POWER_UP Optional LOW LOW HIGH This parameter describes the power up condition of all registers in the primitive DQ_OUTPUT_REG_ASYNC_MODE Optional N
81. atainlo and DOS OUTPUT HR DDIO OUT LOW datainhi datainlo ports dqs hr output reg Input Optional GND This port feeds the clock signal for the DOS OUTPUT HR DDIO OUT HIGH clkh clklo muxsel and DOS OUTPUT HR DDIO OUT LOW clkhi clklo muxsel ports dqs output data in Input Optional GND This port feeds the Dos OUTPUT FF d DOS OUTPUT DELAY CHAINI1 datain DOS OUTPUT DELAY CHAIN2 datain Or dqs output data out port dqs output data in Input Optional GND port feeds the high DQS OUTPUT DDIO OUT datainhi that is the full rate data for the rising edge dqs output data in low Input Optional GND This port feeds the DQS OUTPUT DDIO OUT datainlo port that is the full rate data for the falling edge dqs output data out Output Optional This port can be driven by the DOS OUTPUT DELAY CHAIN2 dataout DOS OUTPUT DELAY CHAIN1 dataout DOS OUTPUT FF q DOS OUTPUT DDIO OUT dataout or dqs output data in port dqs output reg clk Input Optional GND This port is connected to the 5 OUTPUT FF clk and the DQS OUTPUT DDIO OUT clkhi clklo muxsel ports that is used to clock the registers in those blocks dqs output reg clkena Input Optional Voc This port is connected to the DOS OUTPUT FF ena and the DOS OUTPUT OUT ena ports that is
82. ay setting to implement an actual 360 phase shift in its delay chain Because each delay buffer is identical each buffer in the delay chain implements a phase shift that is equal to 360 delay chain length The default value is 12 DQS Delay Buffer Mode Low or High DELAY BUFFER MODE Specifies the frequency mode for the variable delay buffers If you select Low the dll offset ctrl a offsetctrlout 5 0 Ordll offset ctrl b offsetctrlout 5 0 output is limited to a maximum value of 63 If you select High the output is limited to a maximum value of 31 The default value is Low Input Clock Frequency INPUT FREQUENCY Specifies the frequency of the clock in MHz that is connected to the c1x input port This frequency must be within the valid range for the device you are using You can specify a duration in ps The value is in floating point format with no decimal point limit The default value is 300 MHz For information about the clock range for the Altera devices refer to the respective device handbook Turn on jitter reduction JITTER REDUCTION Enables the jitter reduction circuit Jitter affects the signal integrity of the clock signal from a PLL clock source or an external clock pin If you turn on this parameter the jitter reduction circuit is enabled on the dll delayctrlout 5 0 and dll offset ctrl a offsetctrlout 5 0 orthe dll offset ctrl b offsetctrlout 5
83. can use the clear box generator For more information about the clear box generator refer to Appendix A Clear Box Generator Some advanced parameters can only be modified through the clear box parameters ALTDLL Parameter Editor Ls This section provides information about the ALTDLL MegaWizard parameters For advanced users who may use the clearbox generator the clearbox parameter names are provided for the corresponding MegaWizard parameters The ALTDLL Parameter Settings page in the ALTDLL parameter editor allows you to configure the parameters in the following pages m General m DLL Offset Controls Optional Ports Table 3 1 shows the options available on the General page February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 3 2 Table 3 1 Options on General Settings Page Chapter 3 Parameter Settings ALTDLL Parameter Editor Parameter Name Number of Delay Chains Legal Value 6 8 10 12 or 16 Clear Box Parameter Name DELAY CHAIN LENGTH Description Represents the number of delay buffers in the delay loop The DLL consists of 6 8 10 12 or 16 DLL controlled delay buffers chained together The total delay in the DLL delay chain is computed with the following equation delay delay_chain_length x delay_buffer_delay The DLL uses the delay chain to implement a 360 phase shift By comparing the incoming clock to the 360 shifted clock the DLL determines the del
84. ck to browse to your working directory Select the dll inst v file and click Open Click Add to add the dll inst v file to your project Repeat steps 3 and 4 to add the dq dqs inst v and test dq dqs bdf files Click OK On the File menu click Save On the Processing menu click Start Compilation to compile the design After the design is compiled you can view implementation in the RTL Viewer You can also view the resource usage in the Compilation Report After you compile your design simulate the design in the ModelSim Altera software to generate a waveform display of the device behavior Set up and simulate the design in the ModelSim Altera software by performing the following steps 1 8 DL UO Unzip the altdll altdq dqs ex2 msim zip file to any working directory on your PC Start the ModelSim Altera software On the File menu click Change Directory Select the folder in which you unzipped the files Click OK On the Tools menu point to TCL and click Execute Macro Select the altdll altdq dqs ex2 msim do file and click Open This is a script file for the ModelSim Altera software to automate all the necessary settings for the simulation Verify the results with the waveform You can rearrange signals remove signals and add signals and change the radix by modifying the script in the altdll altdq dqs ex2 msim do file ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera
85. date port option on the DLL Offset Controls Optional Ports page in the ALTDLL parameter editor Advanced Enable Control Options Set statically to DOS ENABLE CTRL PHASE SETTING If you turn on the Set statically to option you can select the phase setting for the delay chains from 0 up to 4 to fine tune the DQS enable signal DQS Enable or Control Phase Set If you turn on the Select dynamically using Setting dynamically configuration registers option the phase setting is using determined by the phasectrlin input for the delay configuration chains registers Advanced Enable Always DQS ENABLE CTRL If you turn on Always the phase output is inverted Control Options 00 a ee If you turn on Never the phase output is not inverted DQS Enable finurati If you turn on Based on configuration registers the Control Invert configuration a 1 Input determi heth t Phase registers phaseinvertctrl Input determines whether or no the inverter is used The inverter can be used to increase the number of available phases This is an optional field and defaults to Never Enable DQS enable block delay chain USE DOSENABLE DELAY CHAIN Enables 005 ENABLE DELAY CHAIN This delay chain fine tunes the outputs of DOS ENABLE block so that the DQS enable signal timing matches the DGS strobe This delay chain is a run time adjustable delay chain Table 3 5 Options on DQS OUT OE Page Table 3 5 describes opt
86. dq hr oct in Input Optional 2 n 1 0 GND This port feeds the half rate bidirectional DQ signal for the BIDIR DQ OCT HR DDIO OUT datainhi datainlo ports bidir dq oct in Input Optional n 1 0 GND This port feeds the full rate bidirectional DQ signal for the BIDIR OCT FF d BIDIR OCT DDIO OE oe BIDIR OCT DELAY CHAINI datain BIDIR DELAY CHAIN2 datain or dq oct out port bidir dq oct out Output Optional n 1 0 This port outputs signal from the BIDIR DQ OCT DELAY CHAIN2 dataout BIDIR DELAY CHAINI dataout BIDIR OCT FF q BIDIR OCT DDIO OE dataout OF bidir dq oct in port dqs hr oct in 1 0 Input Optional GND This port feeds the half rate DQS signal for the DQS OCT HR DDIO OUT datainhi datainlo ports Input Optional dqs oct in GND This port feeds the full rate DQS signal for the DQS FF d DQS OCT DDIO OE oe DQS OCT DELAY CHAIN1 datain DQS OCT DELAY CHAIN2 datain or dqs oct out port dqs oct out Output Optional This port outputs signal from the DOS OCT DELAY CHAIN2 dataout DOS OCT DELAY CHAIN1 dataout DOS OCT FF q DQS OCT DDIO OE dataout Ordqs oct in port dqsn hr oct in 1 0 Input Optional GND This port feeds the half rate DQSn signal for the DQSN OCT DDIO OUT datainhi datainlo ports dqsn oct i
87. e 0 00 asse Vie i on DY sn cer a d Vete ATTI hate aa rpe 0 ca ot dim on nt mape sse map 0 arpa c 44 1054 7774 gt M si DITURNTIAL SSTL LASS COFERENTIAL 1 V SXTL CLASS T III 245 92209 ejdurex uiseg LS v y 1 2 10119590 jeuonaung Chapter 4 Functional Description 4 58 Design Example Implementing Half Rate DDR2 Interface in Stratix III Devices Table 4 37 provides the description for each block in the design example Table 4 37 Blocks in Design Example Block Name Description pli_inst instl This block represents the Stratix III PLL with the following settings m inclk 200 MHz m co 3 000 ps 50 duty cycle m ci 3 000 ps 50 duty cycle m c2 3 000 ps 50 duty cycle m 6 000 ps 50 duty cycle dll inst inst5 This block represents the DLL circuitry used during a read from the external memory This block is clocked by the PLL with the following settings m delay chain length 10 m delay buffer mode High m input frequency 333 MHz m jitter reduction Turned off dq dqs inst inst This block represents the DQ and 005 circuitry that interfaces
88. e clock phase transfer If you turn off this option no register is added The negative edge register is used to guarantee the setup and hold time for a phase transfer add phase transfer Use 00 input USE INPUT DELAY Enables lt 0 gt DELAY CHAIN D1 This delay chain CHAIN parameter is used for deskew purposes or SSN reduction on the DQ input path Not supported in Arria GX devices For more information about configuring delay chains dynamically refer to Delay Chains on page 4 15 Table 3 7 describes options available on the DO OUT OE page This page allows you to configure the output and OE paths For more information about the output and OE paths refer to DO Output OE Path on page 4 10 Table 3 7 Options on DQ OUT OE Page Part 1 of 2 Parameter Name Legal Value Clear Box Parameter Name Description Enable DQ output enable 00 Output Path USE OUTPUT Enables lt 0 gt OUTPUT DELAY CHAINI D5 in the Options DELAY_CHAIN1 DQ output path This parameter is used for deskew Enable DQ output purposes or SSN reduction D5 is a run time adjustable delay chain1 delay chain For more information about configuring delay chains dynamically refer to Delay Chains on page 4 15 DQ Output Path USE DQ OUTPUT Enables lt 0 gt oUTPUT DELAY CHAIN2 D6 in the Options DELAY CHAIN2 DQ output path This parameter is used for deskew
89. e dynamic OCT USE DYNAMIC OCT Instantiates the dynamic OCT blocks in the DQS path instance This parameter enables access to dynamic OCT paths on both DQ and DQS paths The dynamic OCT features enable parallel termination R during reads from the external memory and disable R during writes to the external memory Not supported in Arria Il GX devices Add memory ADD MEM FITTER Enables the Quartus 11 Fitter to automatically assign the interface specific GROUP ASSIGNMENTS memory interface 1 0 ports to the memory interface 1 0 fitter grouping pins on the FPGA assignments The Advanced Options page allows you to configure the parameters in the following pages m DOSIN m DOS OUT OE m DOIN DOQOUT OE m Half rate m OCT Path mg DQSn I O February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 3 8 m Reset Config Ports Chapter 3 Parameter Settings ALTDQ 005 Parameter Editor Table 3 4 describes the options available on the DOS IN page This page allows you to configure the DOS input path For more information about the DOS input path refer to DOS Input Path on page 4 6 Table 3 4 Options on DQS IN Page Part 1 of 3 Parameter Name Enable DOS Input Path Legal Value Clear Box Parameter Name USE DOS INPUT PA Description Instantiates the DQS input path Enable DOS Input Path USE DOS INPUT PA Instantiates the DQS input pa
90. e reaching the register The DLL consists of two phase offset control blocks one for each edge adjacent to the DLL which resides in the corner of the device Both phase offset control blocks cannot feed the same edge The DLL block computes the necessary delay settings by comparing the period of an input reference clock to the delay through an internal delay chain You can then use the DLL offset control block to fine tune the delay setting Ata minimum the DLL has a single input that is connected to a dedicated PLL output or input pin and six gray coded outputs that are connected to the DOS delay chain block which is part of the ALTDO DOS megafunction Figure 4 2 shows the components of the ALTDLL megafunction The DLL OFFSET CTRL A block is the first phase offset control block and the DLL OFFSET CTRL B block is the second phase offset control block These two phase offset control blocks are connected together to form the ALTDLL megafunction Each offset control block can only control the DOS delay chains on one edge of the device To feed the same offset to the DOS delay chains on two edges you must use both phase offset control blocks Figure 4 2 ALTDLL Megafunction lt i dll_offset_ctrl_a_offsetf offset e e ma E dll offset ctrl addnsub addnsub S oniki ee offsetctrlout dll offset a offsetctriout aload e M gt offsetdelayctriclkout clk dll i clk o
91. e signal Advanced Delay Chain Options DOS delay chain delayctrlin port source DLL or Core DOS DELAY CHAIN DELAYCTRLIN SOURCE Determines whether you want the delayctrlin port to be controlled by DLL outputs or from the Core FPGA If you select DLL the 411 delayctrlin 5 0 port is connected to the dll delayctrlout 5 0 portofthe DLL The DLL option adjusts the delay setting in DQS DELAY CHAIN block across pressure volume and temperature PVT Altera recommends that you always select DLL to optimize the read capture at the DQ input register If you select Core the core delayctrlin portis fed by the core Advanced Delay Chain Options DQS Delay Buffer Mode Low or High DELAY BUFFER MODE Specifies whether the variable delay buffers in the 05 DELAY CHAIN work in low frequency or high frequency mode The frequency mode must match the frequency mode you select for the DOS Delay Buffer Mode parameter on the Parameter Settings page in the ALTDLL parameter editor Advanced Delay Chain Options 005 Phase Shift 0 36 000 DOS PHASE SHIFT Specifies the phase shift between the delayed DQS signal and the input DQS signal in units of hundreds of degrees for example a 90 phase shift is represented as 9 000 Use this parameter for static timing analysis only because timing analysis cannot determine the phase shift through the delayctrlin 5 0 phasectrlin 2 0 and offsetctrlin 5 0 ports
92. ed on register configuration the phaseinvertctrl input determines whether or not the inverter is used The inverter can be used to increase the number of available phases Table 3 9 on page 3 16 describes the options available on the OCT Path page This page allows you to configure the DQ and DQS OCT paths For more information about the DO and DQS OCT paths refer to DO DOS OCT Path on page 4 14 Table 3 9 Options on OCT Path Page Parameter Name Dynamic Termination Control Options Enable Dynamic Legal Value Clear Box Parameter Name USE OCT DELAY CHAIN1 Description Enables 0 DELAY CHAINI 05 on both the DQ and DQS dynamic OCT paths The external memory interfaces synchronize the timing of the turning on and off of the parallel termination during reads and writes from both the DQ and DQS pins and to improve overall Control Options Enable Dynamic Delay chain2 Delay chain1 ae timing margins D5 is a run time adjustable delay chain For more information about configuring delay chains dynamically refer to Delay Chains on page 4 15 Dynamic USE_OCT_DELAY_ Enables lt 0 gt DELAY CHAIN 2 D6 on both the Termination CHAIN2 DQ and DQS dynamic OCT paths The external memory interfaces synchronize the timing of turning on and off of the parallel termination during reads and writes from both the DQ and DQS pins and to improve overall timing margins D6 is a run
93. elay chain2 inst datain m bidir dq 0 output delay chainl inst dataout m bidir dq 0 output delay chain2 inst dataout m bidir dq 0 output hr ddio out high inst dataout m bidir dq 0 output hr ddio out low inst dataout m bidir dq 0 output ddio out inst dataout m bidir dq io 0 57 For more information about how to analyze the timing paths to obtain the delay chain values refer to the timing diagrams in DOS CONFIG IO CONFIG Block on page 4 22 The output path from the FPGA core to the bidirectional DOS pin is represented by 4 bitinput dqs hr output data in 3 0 The OE path is 2 bits wide from the FPGA core to the bidirectional buffer hr oe in 1 0 Theinput path of the DOS pin goes through a specialized circuitry to clock the 8 bit bidirectional DQ pin input paths ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description 4 62 Design Example Implementing Half Rate DDR2 Interface in Stratix III Devices 14 dgs hr output data in 3 0 dqs hr output data in 3 and dqs hr output data in 2 signals are toggled with a constant value of 1 b1 After that the dqs hr output data in 1 and dqs hr output data in 0 signals are toggled with a constant value of 1 b0 The signals are toggled at a constant rate to generate the necessary DOS write strobe clock signals which are sent together with the DQ write data to the external memory 15 As the throughput of
94. er 3 HR OUT DQS OUTPUT HR DDIO OUT HIGH and 5 OUTPUT HR DDIO OUT LOW blocks are half rate components February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 13 Chapter 4 Functional Description ALTDQ_DQS Megafunction The DOS output and OE path consist of the following blocks Table 4 6 DQS Output and OE Path DQS OU Block GER DQS OU DDIO OUT DQS output register blocks Description Sends data directly to the external memory DQs pins during a write operation through the output buffer These blocks are clocked by the DQS write clock The pos FF block represents a group of flip flop registers in the DQS output path The 5 OUTPUT OUT represents a group of double data rate output registers in the DQS output path DOS FF DOS OE DDIO OE DQS output enable register blocks Sends output enable signal to the output buffer These blocks are clocked by the DQS write clock The bos rr block represents a group of flip flop registers in the DQS OE path The 5 DDIO OE represents a group of double data rate registers in the DQS OE path DQS OUTPUT HR DDIO OUT HIGH Half rate output Represents the DDIO registers that are used to transfer and register block DQS signals from the core durin
95. eraL Settings Settings Value Currently selected device family Stratix 111 Match project default Turned on Number of Delay Chains 12 Refer to Stratix III Device Datasheet DC and Switching Characteristics of Stratix III Devices chapter in the Stratix III Device Handbook and pick a DLL mode that supports 150 MHz and find the DLL setting February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 2 1 Chapter 2 Getting Started Design Example Implementing Read Paths Using Stratix III Devices Table 2 3 ALTDLL GeneraL Settings Settings Value DQS Delay Buffer Mode Low Refer to Stratix III Device Datasheet DC and Switching Characteristics of Stratix III Devices chapter in the Stratix III Device Handbook and pick a DLL mode that supports 150 MHz and find the DLL setting Input Clock Frequency 150 MHz Turn on jitter reduction Turned off 8 Onthe DLL Offset Controls Optional Ports page specify the parameters as shown in Table 2 4 Table 2 4 ALTDLL Parameter Settings DLL Offset Controls Optional Ports Settings Settings Value DLL Phase Offset Control A Turned off Instantiate dll offset ctrl block The design is intended to run slow so you do not need to select this parameter However if the read timing is unbalanced you can fine tune the DQS phase shift using this parameter DLL Phase Offset Control B Turned off Instantiate dll offset ctr
96. ernal memory interface m Ifyou use calibrated termination controller logic for all pins in the ALTOCT instances associated with the custom external memory interface T For more information about calibrated termination refer to Dynamic Calibrated On Chip Termination ALTOCT Megafunction User Guide February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 2 3 Chapter 2 Getting Started Design Flow Simulate the Design After instantiating the megafunctions the Quartus II software generates design source files and Verilog or VHDL simulation model files Simulate these files in Modelsim AE Modelsim SE or other third party functional simulator tools UST For information about functional and gate level timing simulations refer to Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook Create Timing Constraints The ALTDLL and ALTDO DOS megafunctions do not provide automatic timing scripts for custom external memory interfaces You must create your own timing constraints for the following paths and clocks m Timing paths from FPGA I O to external device m Timing paths from I O registers to core logic m PLL and other clock constraints After creating your constraints perform the timing analysis using the TimeQuest timing analyzer in the Quartus II software T Because the timing analysis for custom external memory interfaces are the same as the timing analysis for source synchronous i
97. ers configure the DQS OUTPUT and DQS path of the ALTDQ_DQS instance Table 4 28 Advance Options DQS OUT OE Parameter Value Enable 005 Output Path Turned on Enable DQS output delay 1 Turned on Enable DQS output delay 2 Turned on 100 output register mode DDIO Enable DQS output enable Turned on Enable DQS output enable delay chain1 Turned on Enable DQS output enable delay chain2 Turned on DOS output enable register mode DDIO 7 On the DO IN page specify the parameters as shown in Table 4 29 These parameters configure the DO input path of the ALTDO DOS instance Table 4 29 Advance Options DQ IN Part 1 of 2 Parameter DQ input register mode Sub options Value DDIO DQ Input Register Options DQ input register clock source dgs bus out port Turned off Connect DDIO clkn to 005 BUS from complementary 05 Use DQ input phase alignment Turned on Advanced DQ IPA Options DQ Input Phase Alignment Phase Setting Set statically to 0 Add DQ Input Phase Never Alignment Input Cycle Delay Invert DQ Input Phase Never Alignment Phase Register DQ input phase Turned on alignment bypass output Register DQ input phase Turned off alignment add phase transfer Use DQ resync register Turned off February 2012 Altera Corporation ALTDLL and ALTDQ DQS Megafunctions User Guide 4 53 Chapter 4
98. es termination during writes Access to I O delay chains to fine tune delays on the data or strobe signals statically or dynamically Figure 1 1 shows a high level overview of how you can connect the ALTDO DOS megafunction with other megafunctions such as ALTPLL ALTDLL and ALTIOBUF to create a full custom external memory interface Figure 1 1 shows a 36 bit interface created with ALTDO DOS instantiations where each instantiation is configured in the x9 mode Figure 1 1 System Level View ALTPLL i 6 gt ALTIOBUF DQS DQSN lt ALTIOBUF BIDIR ALTDQ_DQS 9 ALTIOBUF INPUT L ALTIOBUF OUTPUT ALTDLL ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation TS B4AN 2 Getting Started Design Flow This chapter describes the FPGA design flow to implement a custom memory interface datapath using the ALTDLL and ALTDQ_DQS megafunctions and Altera s FPGA hardware features Figure 2 1 shows the design flow for creating a custom memory datapath system with the ALTDLL and ALTDQ_DQS megafunctions and the Quartus II software Figure 2 1 Design Flowchart Build the Datapath y Simulate the Design y Create Timing Constraints Compile the Design and Verity Timing Adjust Constraints
99. f Turned on Turned off OCT register mode FF FF Table 4 23 shows the correct OCT port use for the DDR ODR and RLDRAM interfaces Table 4 23 General OCT Ports for DDR and RLDRAM Interfaces Controller Parameter Full Rate Half Rate DQS OCT IN Used Used DQSN OCT IN Used Used BIDIR DQ OCT IN Used if DQ pin is bidirectional Used if DQ pin is bidirectional INPUT OCT IN Used for DQ pin as input Used for DQ pin as input OUTPUT IN Used for DQ pin as output Used for DQ pin as output DQS HR OCT IN Used Unused DQSN HR IN Used Unused BIDIR HR IN Used Unused HR OCT IN Used Unused OUTPUT DQ HR OCT IN Used Unused OCT REG CLK Used Used HR OCT REG CLK Used if controller is at half rate Unused DQS OCT OUT Used Used DQSN OCT OUT Used Used BIDIR OCT OU Used if DQ pin is bidirectional Used if DQ pin is bidirectional INPUT OCT OU Used for DQ pin as input Used if DQ pin is bidirectional OUTPUT DO OCT OUT Used for DQ pin as output Used if DQ pin is bidirectional February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide Chapter 4 Functional Description Design Example Implementing Half Rate DDR2 Interface in Stratix III Design Example Implementing Half Rate DDR2 Interface in Stratix Ill Devices
100. ffset control 4 3 ALTDO DOS Megafunction 2222292 bibe ees ees 4 4 DOS Input bed 4 6 DO Input oR 4 8 DQ Path oser Pedo Se eek der eee els Pees es 4 10 DOS Path enero crios rhe Ree Ya d eR COE EV Rees eS 4 12 DO DUOS OCT Path adaduhquae ttu nde 4 14 Delay Chains ES 4 15 Deskew Delay Chains 2 2 2 0 24 0 e Eee te rua EE UPC CEPR ER d 4 16 ALTIOBUF Megafunction and Delay Chains 4 18 DOS CONFIG IO CONFIG Block eek e AIRE RI AGE RC A e 4 22 Configuring Dynamic Delay Chains Using the IO_CONFIG 4 22 ALTDLL Megafunction Ports 1 4 31 ALTDO DOS Megafunction Ports 4 33 DOS Input Path Megafunction Ports 4 33 DOS Output Path Megafunction Ports 4 35 DOS OE Path Megafunction Ports
101. ffsetdelayctrlout offsetdelayctrlin a od gt i gt delayctrlout dil delayctrlout dll aload aload nal DLL eee dll dgsupdate gt offsetdelayctrlin clk E sss m G offsetetriout gll offset b offsetctriout dll offset b offset offset i Se gt ceo dl offset ctrl b addnsub addnsub Ini ALTDLL a ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description 4 4 ALTDQ_DQS Megafunction The names DLL_OFFSET_CTRL_A and DLL_OFFSET_CTRL_B are logical and do not denote the placement of the actual phase offset blocks With location assignments you can assign these blocks to the top bottom or side of the FPGA depending on which DLL your design uses If location assignments are not used the Quartus II Fitter places these blocks on the top bottom or side of the FPGA device The DLL and DLL offset blocks in the DQS phase shift circuitry generate the control signals to shift the DOS delay chain delays to center align the DQS strobe with the incoming data at the IOE registers This is common when reading from external memory interfaces For more information about the DLL offset control blocks in the DOS phase shift circuitry refer to the DOS Phase Shift Circuitry section in the respective device handbooks For more information about the ALTDLL
102. g half rate write operation DOS OUTPUT HR DDIO OUT LOW These blocks are clocked by the DQS write clock DQS_OE_HR_DDIO_OUT Half rate output Represents the DDIO registers that are used to transfer enable register half rate DQS output enable signals to the output buffer block DOS OUTPUT DELAY 1 05 DQS output delay For more information about the 005 output and OE delay DOS OUTPUT DELAY CHAIN2 D6 chains chains refer to Table 4 2 on page 4 4 DOS OE DELAY CHAINI D5 DQS OE delay 05 OE DELAY CHAIN2 06 chains IO CONFIG 1 0 Configuration For more information about the To coNr IG block refer Block to Table 4 2 on page 4 4 ALTDLL and ALTDQ DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description 4 14 ALTDQ_DQS Megafunction DQ DQS OCT Path Figure 4 7 shows the available blocks in the DQ DQS OCT paths and the connections with the ALTDO DOS ports Use this path to utilize OCT capabilities at the DQ and DOS output paths ILa The IO value depends on your selection in the parameter editor The possible values are DOS DQSn BIDIR_DQ and OUTPUT Figure 4 7 DQ DQS OCT Path Note DQ DQS OCT Path oct reg clk IO OCT FF HM IO DELAY CHAIN2 D6 OCT C lt lO gt _OCT_DELAY_CHAIN1 D5 OCT n lt q lt io gt _oct_in IO OCT DDIOE DQS_CONFIG io hr
103. g if there is more setup margin Design Example Implementing Read Paths Using Stratix Ill Devices This section provides a walkthrough of a simple design example The design example demonstrates a Stratix device reading from an external DDR2 SDRAM The DDR2 external memory interface is implemented using the ALTDLL and ALTDQ_DQS megafunctions This design requires 1 DOS and 8 DQ input pins The DOS frequency for the design is 150 MHz and the data rate is 300 Mbps 57 Fora more complex design example refer to Design Example Implementing Half Rate DDR2 Interface in Stratix III Devices on page 4 49 t design examples are available next to the ALTDLL and ALTDQ DQS Megafunctions User Guide on the Documentation User Guides page of the Altera website February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 2 5 Chapter 2 Getting Started Design Example Implementing Read Paths Using Stratix III Devices Generate the Megafunctions Create a Quartus II project and generate the following megafunctions ALTPLL megafunction ALTDLL megafunction ALTDQ_DQS megafunction ALTIOBUF megafunction Create a Quartus Il Project Create a project in the Quartus II software that targets the EP3SL150F1152 C2 device for the DDR2 SDRAM by performing the following steps 1 3 Open the altdll_altdq_dqs_DesignExample_ex1 zip file and extract the altdll altdq dqs design 1 file In the
104. gafunction refer to I O Buffer ALTIOBUF Megafunction User Guide 7 Connect all the instances of ALTPLL ALTDLL ALTDO DOS ALTIOBUEF and other custom memory controllers in the Quartus II software The following sections discuss other megafunctions or customized controller logic that are used in some cases ALTOCT Megafunction If you use the OCT capabilities in the targeted devices you eliminate the need for external series or parallel termination resistors and you simplify the design of a PCB If theI O in your design uses calibrated series parallel or dynamic termination your design requires a calibration block This block requires a pair of Ryp and pins located in a bank that shares the same Veco voltage as your memory interface This calibration block is not required to be in the same bank or side of the device as the I O elements it is serving To use these capabilities in the FPGA you must turn on the Use dynamic OCT path option when parameterizing the ALTDO DOS megafunction and instantiate the ALTOCT megafunction St For more information about the OCT capabilities in the DQ DQS path refer to DQ DQS OCT Path on page 4 14 Customized Controller Logic In some cases you require a customized controller logic to control the PHY created with the ALTDLL and ALTDQ_DQS instances You must create a controller logic for the following instances m Controller logic for data data valid and strobe pins for the custom ext
105. half rate components For full rate controller Turned off For half rate controller Turned on Use dynamic OCT path Turned on Turned on Enable DQS input path Turned on Turned on Turned off Turned on Turned off Enable DQS output path Turned on Turned off Turned off Enable DQS OE path Turned on Turned off Turned off DQS DQSn IO configuration mode If used Differential Complementary pair Differential pair pair If single ended Turned off DQS input frequency x MHz e g 400 MHz DQS delay chain phase setting n phase_shift 360 X DLL_delay chain_length DQS delay chain delayctrlin port source DLL Enable DQS input delay chain Default Turned off If used Turned on Delay buffer mode High or Low depending on the ALTDLL instantiation settings Enable DQS delay chain Turned on February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 47 Chapter 4 Functional Description Correct Settings for External Memory Interfaces Table 4 2 shows the correct port use for DDR QDR and RLDRAM interfaces Table 4 21 Correct Port Use for DDR QDR and RLDRAM Interfaces Controllers Port Name Full Rate Half Rate INPUT_DQ_INPUT_DATA_I
106. havior Set up and simulate the design in the ModelSim Altera software by performing the following steps 1 Unzip the altdll_altdq_dqs_ex1_msim zip file to your preferred working directory on your PC Start the ModelSim Altera software On the File menu click Change Directory Select the folder in which you unzipped the files in the altdll altdq dqs ex1 msim zip folder Click OK On the Tools menu point to Tcl and click Execute Macro Select the altdll altdq dqs ex1 msim do file and click Open This is a script file for the ModelSim Altera software to automate all the necessary settings for the simulation Verify the results with the simulation waveform 5 You can rearrange remove and add signals and change the radix by modifying the script in the altdll altdq dqs msim do file ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation 3 Parameter Settings RYA gt The Quartus II software provides the MegaWizard Plug In Manager that helps you quickly customize your megafunction variation The parameter editor provides a list of megafunctions and available options for each variation Altera recommends that you use the parameter editor to instantiate the ALTDLL and ALIDO DOS megafunctions However for advanced users if you want to bypass the MegaWizard Plug In Manager and use the megafunctions as directly parameterized instantiations in your design you
107. he DLL OFFSET CTRL B USE OFFSET parameter is set to FALSE the value is added to the DLL delay setting value and appears as output on the dll offset ctrl a offsetctrlout 5 0 output bus If the DLL OFFSET_CTRL_B_USE_OFFSET parameter is set to TRUE ignore this value The default value is 0 DLL_OFFSET_CTRL_B_ USE_OFFSET String No Available values are T output of the dll offset ctrl output bus If set to T dll offset ctrl not the phase offset s dll offset ctrl RUE and FALSE It determines the b offsetctrlout 5 0 RUE then depending on whether the b addnsub input is asserted or pecified on the b offset 5 0 input bus is added or subtracted from the DLL delay setting output to get 11 offset ctrl b offsetctrlout 5 0 output If set to FALSE the phase offset specified by the DLL delay setting to get the dll offset ctrl b offsetctrlout 5 0 output If omitted the default is FALSE INPUT FREQUENCY String Yes This is the frequency of the clock connected to the clk input port Check this parameter value to ensure that it falls within a valid range This field is required and defaults to 0 You can specify a duration by placing a time unit after the value for example 2 5 ns The value is in floating point format with no decimal point limit JITTER REDUCTION String No Available values are TRUE and FALSE If set to TRUE the j
108. he shift registers have their bits arranges to correspond with datain values 2 The config datain signal is asserted at the next 4 clock cycles to change the input delay chain value 3 The delay only takes effect when the config update signal is asserted for one clock cycle at 2955 000 ps Cursor 11 4 After the config update signal is deasserted the delay from bidir dq 0 input delay chain inst datain at3230 000 ps Cursor 13 tobidir dq 0 input delay chain inst dataout at 3230 750 ps Cursor 14 is noticeable which is 750 ps Refer to Figure 4 23 February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide sasn 500 OGL pue 110177 100109 BAY 2102 Avensqa4 Figure 4 21 shows the third part of the simulation results when you set the input delay chain to 750 ps delay Figure 4 22 Third Part of the Simulation Results Input Delay Chain is set to 750 ps Delay 5 hx ex Ka QQ top level signals test_dq_dqs_vhd_vec_tst clk_in dq das vhd vec tst pll locked EL dq dqs vhd vec Ist bidir dq interface 8 bit dq das vhd vec tst bidir core dq oe enable dq vhd vec tst bidir core read data high dq das vhd vec tst bidir core read dala low 27 dq das vhd vec Ist read dq das vhd vec ist bidir core dq config enable Configuring the delay
109. iates DQS output path if TRUE USE_DQS_OE_PATH Optional FALSE FALSE TRUE Instantiates DQS OE path if TRUE DQS_DQSN_MODE Optional NONE NONE Instantiates DQS and DQSn 1 05 as DIFFERENTIAL differential pair if DIFFERENTIAL COMPLEMENTARY Instantiate DQS and DQSn 1 05 as a complementary pair if COMPLEMENTARY Instantiate only DQS IO if NONE NUMBER BIDIR Optional 0 0 1 2 48 Referred as n NUMBER OF OUTPUT Optional 0 0 1 2 48 Referred as n NUMBER OF INPUT DQ Optional 0 0 1 2 48 Referred as n USE DQ OE PATH Optional FALSE FALSE TRUE Instantiates OE path for oUTPUT DO 105 USE_HALF_RATE Optional FALSE FALSE TRUE Instantiates half rate components USE_DYNAMIC_OCT Optional FALSE FALSE TRUE Instantiates dynamic OCT components NUMBER_OF_CLK_DIVIDER Optional 0 0 1 2 8 Referred as n February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide A 6 Appendix A Clear Box Generator Clear Box Generator Options Table 3 summarizes the Clear Box parameters for the ALTDQ_DQS megafunction to configure the DQS input path Table A 3 Megafunction Parameters to Configure DQS Input Path Part 1 of 4 Optional Parameter Name Required Default Legal Values Description USE DQS DELAY CHAIN Optional FALSE FALSE TRUE Instantiates DQS INPUT DELAY CHAIN if TRUE U
110. ice To feed wider DQS groups you need to chain multiple clock dividers together by feeding the slaveout output of one divider to the masterin input of the neighboring pins divider The ro DIVIDER block is used in the DQ and DQS input paths when you enable the Use half rate components option in the parameter editor Note that this block is only available for Stratix and Stratix IV devices For more information about this block refer to the 0 Element IOE Registers section in the External Memory Interfaces chapter of the respective device handbooks ALTDLL and ALTDQ DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description 4 6 ALTDQ_DQS Megafunction DQS Input Path This path receives the DQS strobe signal from the external memory during read operations Figure 4 3 shows the available blocks in the DOS input path Figure 4 3 005 Input Path Note 1 2 DQS Input Path Y DOS CONFIG das input data out r d DQS INPUT DELAY CHAIN 01 dqs input data dqs enable ctrl in DOS DELAY CHAIN m Ls Y Y dqsupdateteen 4 dqs_bus_out dll_offsetetrlin DQSBUSOUT_DELAY_CHAIN Da T 005 ENABLE gt 4 gt core_delayctrlin dqs_enable_in f 8 dll delayctrlin 945 enable ctrl gt gt DQ
111. ide February 2012 Altera Corporation 4 Functional Description ANU S RYA This section describes the functionality of the various blocks and ports in the ALTDLL and ALTDO DOS megafunctions This section also describes the use of delay chains to achieve better timing margins This section also includes an implementation example showing these megafunctions in a custom external memory interface Custom External Memory Interface Datapaths Overview This section describes the functionality of the various blocks in the external memory datapaths that the megafunctions control Figure 4 1 shows the mapping of the ALTDLL and ALTDO DOS megafunctions to the dedicated I O element for external memory interfaces in Stratix IV devices Figure 4 1 Mapping of ALTDLL and ALTDQ_DQS Megafunctions to the Dedicated 1 0 Circuitry FPGA ALTDLL External Memory DLL Clock L DLL ALTPLL DLL Delayed Clock ALTDQ DQS ALTIOBUF DQS Input Path 005 Read ALTIOBUF DQ Input Path DQ Read ALTIOBUF DQ Output Path DQ Write DQ DQS OCTPath Postamble Clock Resynchronization Clock DQ Output Enable Path 0 90 ato DQ Write Clock ee DOS Writ DOS Output Path i 05 Write DQS Write Clock gt DADAS OCT Path Alignment Clock i DQS Output Enable Path
112. ions available on the DOS OUT OE page This page allows you to configure the DOS output and output enable OE paths For more information about the DOS output and OE paths refer to DOS Output OE Path on page 4 12 Part 1 of 2 Parameter Name Legal Value Clear Box Parameter Name Description Enable DQS USE DOS OUTPUT Instantiates the DQS output path output path PATH Enable DOS USE_DQS_OUTPUT_ Instantiates the DQS output path output path PATH ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 3 Parameter Settings 3 11 ALTDQ_DQS Parameter Editor Tahle 3 5 Options on DQS OUT OE Page Part 2 of 2 Clear Box Parameter Name Legal Value Parameter Name Description DQS Output Path USE DQS OUTPUT Enables 005 OUTPUT DELAY CHAIN 05 in the Options DELAY DQS output path This parameter is used for deskew Enable 00 purposes or SSN reduction output delay D5 is a run time adjustable delay chain chain1 DOS Output Path USE DQS OUTPUT Enables 005 OUTPUT DELAY CHAIN2 D6 in the Options DELAY CHAIN2 DQS output path This parameter is used for deskew Enable DOS purposes or SSN reduction output delay D6 is a run time adjustable delay chain chain2 DQS Output Path Not used FF bos oUTPUT REG Enables the Dos OUTPUT FF Or Options or DDIO MODE DQS OUTPUT DDIO OUT outpu
113. is determined by the phase setting parameter DOS ENABLE PHASE SETTING Optional 0 7 This parameter determines the phase shift implemented by the delay chain if use phasectrlin is set to FALSE otherwise you can ignore this setting LEVEL DOS ENABLE OptionalO FALSE FALSE TRUE This is an optional field and defaults to FALSE DELAY DOS ENABLE BY HALF CYCLE Optional FALSE FALSE TRUE This is an optional field and defaults to FALSE DOS ENABLE CTRL ADD PHASE TRANSFER REG Optional FALSE FALSE TRUE DYNAMIC If set to TRUE a negative edge triggered register is added in data path for the clock phase transfer If set to FALSE no register is added If it is set to DYNAMIC the enaphasetransferreg input determines whether the register is added or not You can use the negative edge register to guarantee the setup and hold time for a phase transfer DOS ENABLE CTRL INVERT PHASE Optional FALSE FALSE TRUE DYNAMIC If set to TRUE the phase output is inverted If set to FALSE the phase output is not inverted If it is set to DYNAMIC the phaseinvertctrl input determines whether the inverter is used or not Use the inverter to increase the number of available phases USE_IO_CLOCK_DIVIDER_ PHASECTRLIN Optional TRUE FALSE TRUE If set to TRUE the phase setting is determined by the phasectrlin input If setto
114. is fixed value is added to the DLL feedback counter and the output is generated on the dll offset ctrl a offsetctrlout 5 0 output port The default value is 0 DLL_OFFSET_CTRL_A_ USE_OFFSET The Set dynamically using offset input port option determines the output of the dll offset ctrl a offsetctrlout 5 0 output port Turn on this option if you want a dynamic offset value If you turn on this option depending on whether the dll offset ctrl a addnsub signal is asserted or not the phase offset specified on the offset input bus is added or subtracted from the DLL feedback counter output to get the dll offset ctrl a offsetctrlout 5 0 output February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide DLL Phase Offset Control B Instantiate dll offset ctrl block Set statically to USE DLL OFFSET CTRL B 3 4 Chapter 3 Parameter Settings ALTDLL Parameter Editor Table 3 2 Options on DLL Offset Controls Optional Ports Page Part 2 of 2 Clear Box Parameter Name Legal Value Parameter Name Description Instantiates DLL OFFSET CTRL block The block can be placed either at the top bottom or side of the FPGA device depending on how the Quartus II Fitter or Set places it dynamically If you turn on this option you must specify whether using offset you want to set the blocks statically or dynamically input port 63 to 63 DLL OFFSET
115. is is a 5 0 1 cycle delayed value of the current delay chain setting of the DLL This signal is Gray coded to minimize jitter due to toggling This signal can feed the 811 delayctrlin input port of the ALTDQ_DQS megafunction or the core logic This output is available for SignalTap Embedded Logic Analyzer dll dqsupdate Optional This is an update enable signal for the delay setting latches of the DQS pins This signal can feed the dqsupdateen input port of the ALTDQ 005 megafunction This output is not available for SignalTap II Embedded Logic Analyzer dll offset ctrl Optional This is the offsetctrlout output setting for offsetctrlout 5 0 DLL OFFSET CTRL A block This is a registered Gray coded value of the delay offset setting A This output can be adjusted based on the value of the dll offset ctrl a use offset parameter This signal can feed the o setctrlin input port of the 005 megafunction This signal is not available for SignalTap Embedded Logic Analyzer dll offset ctrl Optional This is the o setctrlout output setting for offsetctrlout 5 0 DLL OFFSET CTRL B block This is a registered Gray coded value of the delay offset setting B This output can be adjusted based on the value of the dll offset ctrl b use offset parameter This signal can feed the o setctrlin input port of the ALTDQ_DQS megafunction This signal is not available for SignalTap Embedded Logic Analyzer
116. itter reduction circuit is enabled on the dll delayctrlout 5 0 and dll offset ctrl a offsetctrlout 5 0 0r dll offset ctrl b offsetctrlout 5 0 outputs and the DLL may require up to 1 024 clock cycles to lock If set to FALSE the jitter reduction circuit is disabled and the DLL only requires up to 256 clock cycles to lock If omitted the default is FALSE ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Clear Box Generator Options A 5 Table A 1 ALTDLL Megafunction Parameters Part 3 of 3 Parameter Name Type Required Description USE_DLL_OFFSET_CTRL_A String No Specifies whether to instantiate DLL_OFFSET_CTRL_A block Values are TRUE and FALSE If omitted the default is FALSE USE_DLL_OFFSET_CTRL_B String No Specifies whether to instantiate DLL_OFFSET_CTRL_B block Values are TRUE and FALSE If omitted the default is FALSE Table A 2 lists the high level Clear Box parameters for the ALTDO DOS megafunction Table A 2 ALTDQ_DQS Megafunction High Level Configurations Optional Parameter Name Required Default Legal Values Description USE DQS Optional FALSE FALSE TRUE Instantiates DQS IO if TRUE USE_DQS_INPUT_PATH Optional FALSE FALSE TRUE Instantiates DQS input path if TRUE USE_DQS_OUTPUT_PATH Optional FALSE FALSE TRUE Instant
117. l Settings 1 bidirectional buffer for 1 output buffer for 8 bidirectional buffers for the differential DQS pins the output DQ pins the bidirectional DQ pins Currently selected device family Stratix 111 Stratix Ill Stratix 111 How do you want to configure this module As bidirectional buffer As output buffer As bidirectional buffer What is the number of buffers to be instantiated 1 1 8 Use bus hold circuitry Turned off Turned off Turned off Use differential mode Turned on Turned off Turned off Use open drain output Turned off Turned off Turned off Use output enable port Turned off Turned on Turned on Use dynamic termination control Turned off Turned off Turned off Use series and parallel termination Turned off Turned off Turned off 5 On the Dynamic Delay Chains page specify the parameters as shown in Table 4 36 Table 4 36 ALTIOBUF Dynamic Delay Chain Settings Value Settings 1 bidirectional buffer for 1 output buffer for 8 bidirectional buffers for the differential DQS pins the output DQ pins the bidirectional DQ pins Enable input buffer dynamic delay chain Turned off Turned off Turned off Enable output buffer dynamic delay chain 1 Turned off Turned off Turned off Enable output buffer dynamic delay chain 2 Turned off Turned off Turned off Create a clkena port Turned off Turned off Turned off 6 Click Finish The I O buffer module dqs iobuf inst v output dq iobuf ins
118. l block Optional Ports Turned off Create a dll aload port Optional Ports Turned off Create a dll dqsupdate port 9 Click Finish 10 Click Finish The ALTDLL instance is generated 11 Click OK to close the Symbol window 12 Place the instance on the Block Editor Generate the ALTDQ 005 Megafunction To generate the ALTDO DOS megafunction perform the following steps 1 Double click anywhere on the Block Editor window The Symbol window appears 2 Click MegaWizard Plug In Manager Page 1 of the MegaWizard Plug In Manager appears 3 Select Create a new custom megafunction variation 4 Click Next Page 2a of the MegaWizard Plug In Manager appears Select ALTDO DOS and Verilog HDL and type the file name as dq dqs input path v 5 On the Parameter Settings page specify the parameters as shown in Table 2 5 These parameters configure the general settings for the ALTDO DOS instance ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 2 Getting Started Design Example Implementing Read Paths Using Stratix Devices Table 2 5 Parameter Settings 2 8 Parameter Value RLDRAMII Mode NONE Number of bidirectional DQ Number of input DQ 8 Number of output DQ Number of stages in 405 delay chain 3 DOS input frequency 150 MHz Use half rate components Turned off The design uses full rate memory components so you do not select this option
119. ltera Corporation 100109 BAY 20102 094 epin9 195 suorounjeDeyy 500 11011 Figure 4 20 shows the first part of the simulation when you set the input delay chain to 50 ps delay Figure 4 20 First Part of the Simulation Results D1 is set to 50 ps Delay moo ault Fie Edit View Insert Format Tools Window E 388A hJX 585 IX BI QQ amp Bcx top level signals 17 ftest_dq_dgs_vhd_vec_tst clk_in 1 ftest_dq_dgs_vhd_vec_tst pll_locked EL test_dq_dqs_vhd_vec_tst bidir_dq_interface_8_bit test_dq_dgs_vhd_vec_tst bidir_core_tead_data_low 27 jest dq das vhd vec tst read dq das vhd vec tst bidir core dq enable Configuring the delay chains dq vhd vec Ist bidir core dq config enable Q 1 da das vhd vec Ist config clk 1 dest dq das vhd vec tst config datain test dq vhd vec Ist config update bserveing delay effects on bidirectional dq input path 27 dq dqs vhd vec tst bidir dq interface 8 bit U 27 dq dqs vhd vec tst ilZinstl bidir dq input data in 0 77 dq das vhd vec tst il instl bidir da 0 input delay chain inst datain test da das vhd vec tst i instl bidir dq 0 input delay chain inst dataout Now Cursor 1 Cursor 2 Cursor 3 Cursor 4 Cursor 5 Cursor 6 Cursor 7 Cursor 8 Cursor 9 Cursor 10 Cursor 11 Cursor 12 Cursor 13 Cursor 14 0 1 1
120. megafunction ports refer to ALTDLL Megafunction Ports on page 4 31 ALTDQ DQS Megafunction 5 This section describes the DQ DQS datapaths and associated blocks of the ALTDQ_DQS megafunction The figures in the subsequent sections show the megafunction blocks used to construct the datapath and their connections of the top level ports with the blocks that configure the paths You must set the appropriate parameters using the parameter editor to enable the blocks and the desired configurations in the paths Table 4 2 list the common blocks that are used in the DO DOS input and output paths The value for IO depends on your selection in the parameter editor The possible values are BIDIR and INPUT Table 4 2 Common Blocks in the DQ DQS Input and Output Paths Part 1 of 2 l0 INPUT DELAY CHAIN 01 Block Name Description DQS DELAY CHAIN Delay Chains Represents the delay chains used to delay DQS INPUT DELAY CHAIN D1 signals DQSBUSOUT DELAY CHAIN Da For more information about the DQS delay chain DQS ENABLE DELAY CHAIN Db block refer to the DQS Delay Chain section of the respective device handbooks 1 DQS OUTPUT DELAY CHAIN2 l0 DELAY CHAINI 05 l0 DELAY CHAIN2 D6 DQS OE DELAY CHAINI 05 DQS OE DELAY CHAIN2 D6 l0 DELAY CHAINI D5 OCT l0 DELAY CHAIN2 D6 OCT For more information about
121. meter determines if the areset PRESET port clears presets or has no effect on the NONE DDIO register s The areset port is required if this parameter is set to CLEAR or PRESET DQ OE REG SYNC MODE Optional NONE CLEAR This parameter determines if the sreset PRESET port clears presets or has no effect on the NONE DDIO register s The sreset port is required if this parameter is set to CLEAR or PRESET ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation JA DTE Additional Information Revision History The following table lists the revision history for this user guide Date Version Changes Made February 2012 v 5 0 Update input frequency May 2010 v4 0 Updated the ALTDLL and ALTDQ_DQS Megafunctions User Guide m Added the new ALTDLL and ALTDQ_DQS parameter editor options Added Appendix for clear box Generator m Added new design example m Removed repetitive and redundant information September 2009 v3 0 Updated and reorganised Chapter 1 and Chapter 2 December 2008 v2 0 Added m HardCopy Ill in Features on page 1 2 Added full rate mode and half rate mode terms and descriptions in Figure 1 3 on page 1 9 Last sentence in Step 1 Understand the Available External Memory Dedicated Circuitry in Devices on page 1 5 m ALTDLL Features on page 1 9 Note 2 3 4 in Figure 1 3 on page 1 6 Added Megafunction Ports and Paramete
122. meter editor The possible values are BIDIR and INPUT Figure 4 4 DQ Input Path Note 1 2 3 DQ Input Path gt lt lO gt _INPUT_FF gt lO input data in lO INPUT DELAY CHAIN D1 lO input data out gt lO input data out low an lO input data out high i 5 54 lt lO gt _DDIO_IN lO CONFIG dq input reg clk dqs bus dqs input reg clkena io areset io sreset lO LOW and lO HIGH DQS_CONFIG J dq ipa clk dll delayctrlin IO CLOCK DIVIDER lO HALF RATE INPUT IO hr input data out lt io gt _sreset Notes to Figure 4 4 1 The lt 0 gt input data in port must be connected to the output port of the input buffer 2 The dl1_delayctrlin port must be connected to the DLL 3 The ro CLOCK DIVIDER lt 0 gt HALF RATE INPUT lt 0 gt lt 0 gt IPA HIGH blocks are half rate components February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 9 Chapter 4 Functional Description ALTDQ_DQS Megafunction The DQ input path consists of the following blocks Table 4 4 DQ Input Path Block l0 INPUT FF
123. more information about the DLL blocks refer to ALTDLL Megafunction on page 4 3 ALTDQ DQS The ALTDQ_DQS megafunction controls the following memory interface datapaths m DQS Input Path m DQ Input Path m DQ Output OE Path m DQS Output OE Path m 00 005 OCT Path For more information about the datapaths refer to ALTDQ_DQS Megafunction on page 4 4 ALTPLL The ALTPLL megafunction block provides the clocking scheme used in the custom external memory interface for half rate or full rate interface For more information about using PLLs refer to the ALTPLL Megafunction User Guide ALTIOBUF The ALTIOBUF megafunction provides 1 0 buffer variations to connect the DQS instance to the FPGA pins and to support dynamic OCT feature February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 3 Chapter 4 Functional Description ALTDLL Megafunction ALTDLL Megafunction This section describes the DLL block and the DLL offset control blocks associated with the ALTDLL megafunction DLL block and DLL offset control block The ALTDLL megafunction controls the DLL and its two associated phase offset control blocks The ALTDLL megafunction also controls the delay chain settings to achieve a compensated delay for PVT For example a DQS read strobe clock that is edge aligned to its associated read data can be used to clock the data into I O registers if the data is delayed befor
124. mplementing OCT Calibration in Stratix III Devices February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 15 Delay Chains Chapter 4 Functional Description Delay Chains The ALTDO DOS megafunction uses various types of delay chains You can control delay chains dynamically to provide a better sampling window for external memory interfaces Table 4 8 shows the delay chain type and their respective settings Table 4 8 Delay Elements and Settings delay D6 OCT is the OCT to 1 0 buffer delay This delay chain is used to reduce simultaneous switching noise SSN These delay chains can be adjusted on a group basis for non DDR3 applications This delay chain works with a write leveling clock to adjust the delay among groups for DDR3 applications D6 is cascaded together with D5 to generate the sum of delays For more information about reducing SSN refer to Deskew Delay Chains on page 4 16 settings for this delay chain because the delay control in the chain is 3 bits wide Maximum Step Value Delay Value Delay Chain Type Function Possible Settings ps ps D1 Tunes the DQ delay read calibration in There are 16 possible 50 0 DDR applications settings for this delay chain because the delay control in the chain is 4 bits wide D5 and D5 OCT D5 is the output register to I O buffer There are 16 possible 50 0 delay D5 OCT is the OCT to 1 0 buffer set
125. n 1 0 Input Optional GND This port feeds the full rate DDR bidirectional DQ signal rising edge for the BIDIR DQ OUTPUT DDIO OUT datainhi port bidir dq output data i n low n 1 0 Input Optional GND This port feeds the full rate DDR bidirectional DQ signal falling edge for the BIDIR DQ OUTPUT DDIO OUT datainlo port bidir dq output data out n 1 0 Output Optional This port outputs the bidirectional DQ signal from the BIDIR DQ OUTPUT DELAY CHAIN2 data out BIDIR DQ OUTPUT DELAY CHAINI1 data out BIDIR OUTPUT FF q BIDIR DQ OUTPUT DDIO OUT dataout Orbidir dq output data in port bidir dq sreset ny 1 0 Input Optional GND This port is connected to all sreset port in the bidirectional DQ IO primitives that is used to synchronously reset the registers in those primitives dq hr output reg clk Input Optional GND This port feeds the output enable signal for the l0 OUTPUT FF ena and l0 OUTPUT DDIO OUT ena ports dq output reg clk Input Optional GND This port feeds the clock signal for the l0 OUTPUT FF clk and l0 OUTPUT DDIO OUT clkhi 1 1 muxsel ports February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide Table 4 16 Megafunction Ports to Configure DQ Output Path Chapter 4 Functional Description ALTDQ
126. n This input port is used as the clock signal of the shift register block The maximum frequency for this clock is 30 MHz Config ports Enables input port that feeds the input data to the serial Create load shift register in ro coNF IG block for user driven config datain dynamic delay chain input port Config ports Enables input port that feeds coNr IG block update Create port for user driven dynamic delay chain config update When asserted the serial load shift register bits feed the input port parallel load register The Simulation Model page allows you to optionally generate simulation model files The Summary page displays a list of the types of files to be generated The automatically generated variation file contains wrapper code in the language you specified earlier On this page you can specify additional types of files to be generated Choose from the AHDL Include file function name gt inc VHDL component declaration file function name cmp Quartus II symbol file function name gt bsf Instantiation template file function name gt v and Verilog HDL black box file function name bb v If you select Generate netlist the Simulation Model page the file for that netlist is also available A gray checkmark indicates a file that is automatically generated and a red checkmark indicates generation of an optional file ALTDLL and ALTDQ_DQS Megafunctions User Gu
127. n IO Configuration mode Differential Pair 11 On the Reset Config Ports page specify the parameters as shown in Table 4 33 Table 4 33 Advanced Options Reset and Config Ports Part 1 of 2 Parameter Value Create 05 areset input port Turned on Create dqs_sreset input port Turned on Create input dq areset input port Turned off Create input dq sreset input port Turned off Create output dq areset input port Turned off ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description 4 54 Design Example Implementing Half Rate DDR2 Interface in Stratix III Devices Table 4 33 Advanced Options Reset and Config Ports Part 2 of 2 Parameter Value Create output_dq_sreset input port Turned off Create bidir_dg_areset input port Turned on Create bidir dg sreset input port Turned on Create config clk input port Turned on Create config datain input port Turned on Create config update input port Turned on 12 Click Finish The dq dqs inst module dq dqs inst v is generated Instantiate the ALTIOBUF Megafunction After instantiating the ALTDLL and ALTDO DOS megafunctions you must instantiate the ALTIOBUF megafunction with the following I O buffer settings m 1 bidirectional buffer for the differential DOS pins m 1 output buffer for the output DO pins m 8 bidirectional buffer
128. n Input Optional GND This port feeds the full rate DQSn signal for the DQSN OCT FF d DQOSN DDIO OE oe DQSN OCT DELAY CHAINI datain DQSN OCT DELAY CHAIN2 datain 0r dqsn oct out port dqsn oct out Output Optional This port outputs signal from the DOSN OCT DELAY CHAIN2 dataout DOSN OCT DELAY CHAIN1 dataout DOSN OCT FF q DQSN OCT DDIO OE dataout 0rdqsn oct in port hr oct reg clk Input Optional GND This port feeds the half rate clock signal for the l0 OCT HR OUT clkhi clklo muxsel ALTDLL and ALTDQ DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description ALTDQ_DQS Megafunction Ports 4 38 Table 4 14 Megafunction Ports to Configure OCT Path Part 2 of 2 Optional Port Name Type Required Default Description oct_reg_clk Input Optional GND This port feeds the full rate clock signal to the l0 lt 0 gt OCT DDIO OE clk ports output dq hr oct in Input Optional GND This port feeds the half rate output DQ signal for the 2 n 1 0 OUTPUT DQ OCT HR DDIO OUT datainhi datainlo ports output dq oct in Input Optional GND This port feeds the full rate output DQ signal for the 1 0 OUTPUT FF d OUTPUT DQ DDIO OE oe OUTPUT OCT D
129. n you can select either NONE GROUPO or GROUP1 If you select GROUPO then GROUP1 is used for the Q valid signal group option and if you select GROUP1 then GROUPO is used for the Q valid signal group option If you select x36 for the RLDRAMII mode option then for this option you can select either NONE GROUPO or GROUP1 Not supported in Arria Il GX devices Q valid signal group NONE GROUPO or GROUP1 OVLD LOC Specifies the group assignment for the Q valid signal group If you select NONE for the RLDRAMII mode option then this option defaults to NONE If you select x9 for the RLDRAMII mode option then this option defaults to GROUPO If you select x18 for the RLDRAMII mode option then this option depends on the Data mask pin group option If you select GROUPO for the Data mask pin group option then GROUPT1 is defaulted for this option and if you select GROUP1 for the Data mask pin group option then GROUPO is defaulted for this option If you select x36 for the RLDRAMII mode option then for this option you can select either NONE GROUPO or GROUP1 Not supported in Arria Il GX devices Number of bidirectional DQ 0 48 NUMBER OF BIDIR DO Specifies the number of bidirectional DQ ports used in the ALTDQ_DQS instance ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 3 Parameter Settings 3 7 ALTDQ_DQS Parameter Editor Table 3 3
130. nal only feeds the dqsupdateen port of the ALTDQ_DQS megafunction To use the d11_dqsupdate signal you must turn on the Enable DQS delay chain latches option on the DQS IN page in the ALTDQ_DQS parameter editor The Simulation Model page allows you to optionally generate simulation model files The Summary page displays a list of the types of files to be generated The automatically generated variation file contains wrapper code in the language you specified earlier On this page you can specify additional types of files to be generated ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 3 Parameter Settings 3 5 ALTDQ_DQS Parameter Editor Choose from the following file types m Quartus file function name gt qip Instantiation template file lt function name gt v Verilog HDL black box file lt function name gt _bb v AHDL Include file lt function name gt inc VHDL component declaration file lt function name gt cmp Quartus II symbol file lt function name gt bsf If you select Generate netlist on the Simulation Model page the file for that netlist is also available A gray checkmark indicates a file that is automatically generated and a green checkmark indicates generation of an optional file ALTDQ DQS Parameter Editor This section provides information about the ALTDQ_DQS MegaWizard parameters 57 For advanced users who may use the clearbox generator
131. nnected to the IO CLOCK DIVIDER slaveout portthat is used when you need to chain multiple clock dividers together to feed wider DQS groups This port must not have more than one fan out and must only be connected to the io clock divider masterin port of another ALTDQ_DQS megafunction offsetctrlin 5 0 Input Optional GND This port receives the Gray coded fine tune delay chain setting for the DQS output path from the ALTDLL dll offset ctrl a offsetctrlo ut 5 0 portor ALTDLL dll offset ctrl b offsetctrlo ut 5 0 This port must match the polarity of its source and cannot be inverted February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 35 Chapter 4 Functional Description ALTDQ_DQS Megafunction Ports DQS Output Path Megafunction Ports Table 4 12 summarizes all the ports on the megafunction that configure the DOS output path Table 4 12 Megafunction Ports to Configure DQS Output Path Optional Port Name Type Required Default Description dqs areset Input Optional GND This portis connected totheDos OUTPUT FF clrn DQS OUTPUT DDIO OUT areset and DQS OUTPUT HR DDIO OUT LOW ares et ports that is used to asynchronously reset all registers in those blocks dqs hr output data Input Optional GND This port feeds the half rate data to the in 3 0 DOS OUTPUT HR DDIO OUT HIGH datainhi d
132. nterfaces refer to the Timing Analysis section in volume 3 of the Quartus II Handbook and AN 433 Constraining and Analyzing Source Synchronous Interfaces The ALTDLL ALTDO DOS custom PHY solution supports timing analysis using the TimeQuest timing analyzer with Synopsys Design Constraints SDC assignments You can derive the timing constraints from the external device data sheet and tolerances from the board layout St For more information about timing constraints refer to Appendix D Interface Timing Analysis section in AN 328 Interfacing DDR2 SDRAM with Stratix II Stratix II GX and Arria GX Devices For more information about creating timing constraints in SDC format for the TimeQuest timing analyzer refer to the The Quartus II TimeQuest Timing Analyzer chapter of the Quartus II Handbook Depending on which simulation tool you are using refer to the appropriate chapter in the Simulation section in volume 3 of the Quartus II Handbook Compile the Design and Verify Timing After constraining your design compile your design in the Quartus II software to generate timing reports to verify whether timing has been met After compiling your design in the Quartus II software run the verifying timing script to produce the timing report for different paths such as write data read data address and command and core entire interface timing paths in your design ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Alte
133. o delay is added If Add 00 Input Based on you turn on Based on configuration registers the Phase Alignment configuration enainputcycledelaysetting input controls Input Cycle Delay registers d or not a single cycle delay is added to the input path Advanced DQ IPA Always DQ IPA INVERT If you turn on Always the phase output is inverted If Options Never or PHASE you turn on Never the phase output is not inverted If Invert DQ Input Based on you turn on Based on configuration registers the Phase Alignment configuration phaseinvertctrl input determines whether or not Phase registers the inverter is used The inverter is used to increase the number of available phases Advanced DQ IPA DQ_IPA_BYPASS_ Controls the output register in the DQ input path If you Options OUTPUT_REGISTER turn on this option the output data bypasses the output Register DQ input register If you turn off this option then the data goes phase alignment through the output register bypass output February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 3 14 Table 3 6 Options on DQ IN Page Part 3 of 3 Chapter 3 Parameter Settings ALTDQ_DQS Parameter Editor Parameter Name Legal Value Clear Box Parameter Name Description Advanced DQ IPA Options Register DQ input phase alignment DO IPA ADD PHASE TRANSFER REG If you turn on this option a negative edge triggered register is added in the data path for th
134. o in inst regoutlo February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide sasn 500 OGL pue TIQLTV 100107 Bally 2100 AueniqeJ Figure 4 26 Data Transfer from the Bidirectional DQ Pin to the FPGA Core with 50 ps Delay Chain Activated 10 19 1 51219 5148 5 1648 1 5189 1 5 2005 5 2206 1 515 sr 1 5005 52 9 Sus 1 5 05 5 538 5 404s 1 54215 1 8448 5 4645 1 bidir dq io 7 0 Y FF Y 00 Y FF Y das hr oe in 1 0 dqs hr output data in 3 0 das output hr ddio out low inst dataout dqs output hr ddio out high inst dataout 998 output delay chain inst dataout 998 output delay chain2 inst dataout das output ddio out inst dataout das io bidir dq 0 input delay chain inst datain NN bidir dq 0 input delay chain inst dataout CT NON F bidir dq 0 ddio in inst regouthi bidir dq 0 ddio in inst regoutlo d T A bidir dq 0 ipa low inst dataou 1 bidir_dq_0_ipa_high_inst dataou OT ff bidir dq 0 half rate input inst dataout 3 0 Y Fy 0i 1 E Y H bidir dq hr input data out 31 0 Y FFFFFFFF C 00000000 FFFFFFFF Y dqs config ena 0 dqsn io config en
135. oct in 1 102 100 io hr oct in 0 qe IO OCT HR hr oct reg clk Notes to Figure 4 7 1 The O oct out port must be connected to the input port of the output buffer 2 The O HR block is a half rate component The DO DOS OCT path consists of the following blocks Table 4 7 DQ DQS OCT Path Block Name Description lt 0 gt FF OCT register blocks The lt 0 gt rr block represents a group of flip flop lt 0 gt OCT DDIOE registers in the DQ DQS OCT output path The lt O gt _OCT_DDIOE represents a group of DDIO registers in the DQ DQS OCT output path l0 HR DDIO Half rate OCT block Represents a group of DDIO registers required to transfer the calibrated output signal in half rate mode l0 DELAY CHAINI1 05 OCT OCT delay chain For more information about the OCT output delay chain l0 ocT DELAY CHAIN2 D6 OCT blocks blocks refer to Table 4 2 on page 4 4 DQS CONFIG DQS Configuration For more information about the DQS_CONF IG block Block refer to Table 4 2 on page 4 4 more information about using the dynamic calibration blocks for termination refer to Dynamic Calibrated On Chip Termination ALTOCT Megafunction User Guide For more information about implementing calibrated dynamic OCT refer to AN 465 I
136. on DO INPUT REG CLK USE CLKN Optional FALSE FALSE TRUE If TRUE lt O gt _DDIO_IN c1k port on the primitive is fed by dqs bus out port on the megafunction and l0 DDIO IN clkn port on the primitive is fed by dqsn bus out port on the megafunction USE FALSE TRUE Instantiates lt O gt _IPA_HIGH l0 LOWif TRUE USE DO IPA PHASECTRLIN Optional FALSE TRUE l0 HIGH use phasectr lin port on the primitive l0 LOW use phasectrl in port on the primitive DO PHASE SETTING Optional 0 7 lt 0 gt HIGH phase settin port on the primitive l0 IPA LOW phase setting port on the primitive DO IPA ADD INPUT CYCLE DELAY Optional FALSE FALSE TRUE DYNAMIC l0 HIGH add input cy cle delay port on the primitive l0 IPA LOW add input le delay port on the primitive DO IPA BYPASS OUTPUT REGISTER Optional FALSE FALSE TRUE l0 HIGH bypass outpu t register on the primitive l0 IPA LOW bypass output register port on the primitive DO IPA ADD PHASE TRANSFER REG Optional FALSE FALSE TRUE DYNAMIC l0 HIGH add phase transfer reg porton the primitive l0 LOW add phase transfer reg on the primitive ALTDLL and ALTDQ_DQS Megafunctions User Guide Febru
137. on A 7 Clear Box Generator Options Table A 3 Megafunction Parameters to Configure DQS Input Path Part 2 of 4 Optional Parameter Name Required Default Legal Values Description USE DQS DELAY CHAIN OptionalO FALSE FALSE TRUE This parameter is the signal used to PHASECTRLIN choose the phase applied to the dqsbusout Output when use phasectrlin is set to TRUE otherwise the phase setting is determined by the phase setting parameter Only feed this port by the dqsinputphasesetting output port of the DQS config You must connect this port if use phasectrlin is set to TRUE otherwise this port is optional and defaults to GND This input must match the polarity of its source and cannot be inverted DQS_DELAY_CHAIN_PHASE Optional 0 1 2 3 4 This parameter is a delay chain setting SETTING If use phasectrlin is set to FALSE this parameter sets the number of DQS delay buffers that the dqsin signal should travel through to the dqsbusout port otherwise you can ignore this setting When it is set to the dqsbusout signal bypasses the DQS delay chain When it is set to 1 2 or 4 the dqsbusout signal goes through 1 2 3 or 4 delay buffers respectively that are controlled by delayctrlin 5 0 The phase shift implemented is determined by the ratio of the DQS delay buffers to DLL delay buffers phase shift phase setting DLL delay chain length 960 DELAY BUFFER MODE Optional
138. or the ALTDLL instance Table 4 24 General Settings Part 1 of 2 Settings Value Currently selected device family Stratix 111 Match project default Turned on Number of Delay Chains 10 DOS Delay Buffer Mode High Input Clock Frequency 333 MHz Turn on jitter reduction Turned off ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description Design Example Implementing Half Rate DDR2 Interface in Stratix III Devices Table 4 24 General Settings Part 2 of 2 4 50 Settings Value DLL Phase Offset Control A Turned off Instantiate dll offset control block DLL Phase Offset Control B Turned off Instantiate dll offset control block Optional Ports Turned off Create a dll aload port Optional Ports Turned off Create a dll dqsupdate port 7 On the DLL Offset Controls Optional Ports page specify the parameters as shown in Table 4 25 Table 4 25 ALTDLL Parameter Settings DLL Offset Controls Optional Ports Settings Settings Value DLL Phase Offset Control A Turned off Instantiate dll offset control block DLL Phase Offset Control B Turned off Instantiate dll offset control block Optional Ports Turned off Create a dll aload port Optional Ports Turned off Create a dll dqsupdate port 8 Click Finish La When you are prompted to add the Quartus II IP file qip to your project click Yes The ALTDLL
139. outputs the output signal from the DQSn output path This port can be driven by DOSN OUTPUT DELAY CHAIN2 dataout DOSN OUTPUT DELAY CHAINI1 dataout DOSN OUTPUT FF qg DQSN OUTPUT DDIO OUT dataout or dqsn output data in port dqsn_sreset Input Optional GND This port is connected to all sreset ports in the DQSn IO primitives that is used to synchronously reset the registers in those primitives February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide DQS CONFIG IO CONFIG Megafunction Ports Table 4 19 summarizes all the ports on the megafunction that configure the DOS CONFIG IO CONFIG path Chapter 4 Functional Description ALTDQ DQS Megafunction Ports Table 4 19 Megafunction Ports to Configure DQS_CONFIG IO_CONFIG Path ny 1 0 Optional Port Name Type Required Default Description bidir_dq_io_config_ena Input Optional Vec Enable signal for the BIDIR_DQ_IO_CONFIG 1 01 block config_clk Input Optional GND Clock signal for the pos CONFIG and IO CONFIG blocks config datain Input Optional GND Input signal for the DOS_CONFIG and IO CONFIG Dlocks config update Input Optional GND Update signal for the Dos coNFIG and IO CONFIG blocks dqs config ena Input Optional Vec Enable signal for the DQS_CONF IG block dqs_io_config_ena Input Optional Vec Enable signal for the bos ro
140. pe Optional Required Default Description dqsn areset Input Optional GND This port is connected to all areset ports in the DQSn IO primitives that is used to asynchronously reset the registers in those primitives dqsn bus out Output Optional This port outputs the signal from DOSN ENABLE dqsbusout DOSNBUSOUT DELAY CHAIN dataout Or DQSN DELAY CHAIN dqsbusout port dqsn hr oe in 1 0 Input Optional GND This port feeds the half rate DDR signal to the DQSn OE path This port is connected to the DQSN OE HR DDIO OUT datainhi datainlo port dqsn hr output data in 34 40 Input Optional GND This port feeds the half rate DDR input signal to the DQSn output path This port is connected to the DOSN OUTPUT HR DDIO OUT HIGH datainhi datainlo and DQOSN OUTPUT HR DDIO OUT LOW datainhi datainlo ports dqsn input data in Input Optional GND This port feeds the input signal to the DQSn input path This port is connected to the DOSN_DELAY_CHAIN dqsin DQSN INPUT DELAY CHAIN datain or dqsn input data out port ALTDLL and ALTDQ DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description ALTDQ_DQS Megafunction Ports Table 4 18 Megafunction Ports to Configure DQSN IO Path 4 44 Part 2 of 2 Port Name Type Optional Required Default Description dqsn inpu
141. pport sivas bie China nee t dle eee Tee prd dede atid ge pe ele gle eres 1 1 ROE EAM OS x 1 2 Chapter 2 Getting Started Design edo ba iode A dette bee Pe deett 2 1 Build the bre ee bep are US Step e e deese eq cec 2 1 Simulate the D sIgi eoo Core eee UDIN Ue P Ce aie eei a er erbe UO eR erbe tte 2 3 Create Timing Constraints i ese esses ed erede ee e e de Rh RA pete gib 2 3 Compile the Design and Verify Timing 2 3 Adjast Constraints iai potete que er nara oreet e K sce hens Bae 2 4 Design Example Implementing Read Paths Using Stratix III Devices 2 4 Generate the Megafunctions 2 5 Compile and Simulate the Design 2 12 Chapter 3 Parameter Settings AT EDGE Parameter Eto e eese dt race e dated 3 1 ALTDO DOS Parameter Editor 222222222 deed a eae aed bee eS 3 5 Chapter 4 Functional Description Custom External Memory Interface Datapaths Overview 4 1 ALTDEL Mesafuneliort ag cocto a ect Sends Ed a acide dadas 4 3 DLL block and DLL o
142. qs bus IO CLOCK DIVIDER clk port on the primitive is fed by dqs bus out port on the megafunction If inverted bus IO CLOCK DIVIDER clk port on the primitive is fed by dqs bus out port on the megafunction Table A 4 summarizes the Clear Box parameters for the ALTDO DOS megafunction to configure the DOS output path Table A 4 Megafunction Parameters to Configure 005 Output Path Part 1 of 2 Optional Parameter Name Required Default Legal Values Description USE DQS OUTPUT DELAY Optional FALSE FALSE TRUE Instantiates CHAIN1 DQS OUTPUT DELAY CHAIN if TRUE USE DOS OUTPUT DELAY Optional FALSE FALSE TRUE Instantiates CHAIN2 DQS OUTPUT DELAY 2 if TRUE DQS OUTPUT REG MODE Optional NONE NONE FF Instantiates 005 OUTPUT FF if FF DDIO Instantiates DOS OUTPUT OUT if DDIO DQS OUTPUT REG POWER Optional LOW LOW HIGH This parameter describes the power up UP condition of all registers in the primitive February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide A 10 Appendix A Clear Box Generator Clear Box Generator Options Table A 4 Megafunction Parameters to Configure 005 Output Path Part 2 of 2 Optional Parameter Name Required Default Legal Values Description DQS_OUTPUT_REG_ASYNC_ Optional NONE CLEAR This parameter determines if
143. r dq ir dq das vhd vec tst il 27 dq das vhd vec Ist il instl bidir da 0 input delay chain inst datain test da das vhd vec tst il instl bidir dq input delay chain inst dataout Now Cursor 1 Cursor 2 Cursor 3 Cursor 4 Cursor 6 Cursor 7 Cursor 8 Cursor 9 Cursor 10 Cursor 11 Cursor 12 Cursor 13 Cursor 14 10000000 ps Ops 70000 ps 255000 ps 1355000 ps 1455000 ps 1555000 ps 1630000 ps 1630050 ps 1755000 ps 2855000 ps 2955000 ps 3055000 ps 3230000 ps 3230750 ps Tit 4 RIT 1629863 ps to 1630179 ps Now 10 us Delta 16 9018 NISNOD 01 9HNOO 500 10 y 13 dey9 101141259 jeuonaung Chapter 4 Functional Description 4 28 DQS CONFIG 10 CONFIG Block Setting the Input Delay Chain to 750 ps Delay Cursor 9 1 755 ns to cursor 10 2 855 ns in Figure 4 22 show that the input delay chain is configured to 750 ps The con ig clock takes 11 1 100 ns clock cycles to load the intended delay values into the IO CONFIG block because of the first four clock cycles for the input delay chain D1 the next three clock cycles for the output delay chain 2 D6 and the last four clock cycles for the output delay chain 1 D5 The following steps describe how the input delay chain changes 1 Because there is a 11 bit shift register in the CONFIG block bidir core dq confiq enable 0 is asserted for 11 clock cycles When the shift registers are fully loaded t
144. ra Corporation Chapter 2 Getting Started 2 4 Design Example Implementing Read Paths Using Stratix Devices The timing analyzer reports margins on the following paths m Address and command setup and hold margin Half rate address and command setup and hold margin Core setup and hold margin Core reset and removal setup and hold margin Write setup and hold margin Read capture setup and hold margin T For more information about timing analysis and reporting using the ALTDLL and ALTDQ_DOS external memory solution refer to the Analyzing Timing of Memory IP chapter in volume 2 of the External Memory Interface Handbook Adjust Constraints The timing report shows the worst case setup and hold margin for the different paths in your design If the setup and hold margin do not meet timing requirements adjust the phase setting of the clocks that latch the data For example the address and command outputs are clocked by an address and command clock that may be different than the system clock which is 0 The system clock clocks the clock outputs going to the memory If the report timing script indicates that using the default phase setting for the address and command clock results in more hold time than setup time adjust the address and command clock to be less negative than the default phase setting to ensure that there is less hold margin Similarly adjust the address and command clock to be more negative than the default phase settin
145. ral Settings Settings Currently selected device family Value 1 input buffer for the 8 input buffer for the input DQS pins input DQ pins Stratix 111 Stratix 111 How do you want to configure this module As an input buffer As an input buffer What is the number of buffers to be instantiated 1 8 Use bus hold circuitry Turned off Turned off Use differential mode Turned off Turned on Use open drain output Turned off Turned off Use output enable port Turned off Turned off Use dynamic termination control Turned off Turned off Use series and parallel termination control Turned off Turned off 6 Onthe Dynamic Delay Chains page specify the parameters as shown in Table 2 9 Table 2 9 ALTIOBUF Dynamic Delay Chain Settings Value 1 input buffer for the 8 input buffer for the Settings input DQS pins input DQ pins Enable input buffer dynamic delay chain Turned off Turned off Enable output buffer dynamic delay chain 1 Turned off Turned off Enable output buffer dynamic delay chain 2 Turned off Turned off Create a clkena port Turned off Turned off February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide uonelodjo2 Bay 2102 094 195 suorpounjeDeyy 500 11011 7 Click Finish 8 Click Finish The ALTIOBUF instance is generated 9 Click OK to close the Symbol
146. rameters directory names project names disk drive names file names file name extensions and software utility names are shown in bold type Examples fmax qdesigns directory d drive chiptrip gdf file Italic Type with Initial Capital Letters Document titles are shown in italic type with initial capital letters Example AN 75 High Speed Board Design Italic type Internal timing parameters and variables are shown in italic type Examples n 1 Variable names are enclosed in angle brackets and shown in italic type Example file name project name gt pof file Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters Examples Delete key the Options menu Subheading Title References to sections within a document and titles of on line help topics are shown in quotation marks Example Typographic Conventions Courier type Signal and port names are shown in lowercase Courier type Examples aata1 tdi input Active low signals are denoted by suffix n e g resetn Anything that must be typed exactly as it appears is shown in Courier type For exam ple c qdesigns tutorial chiptrip gdf Also sections of an actual file such as a Report File references to parts of files 0 the AHDL keyword suBpE SIGN as well as logic function names 6 0 TRI are shown in Courier 1 2 3 and Numbered steps are used ina list of items
147. re the total delay value is equal to the number of stages in the delay chain x50 ps For example if you set the number of stages in the delay chain to five then the total delay value is five times 50 ps which is 250 ps Figure 4 19 through Figure 4 23 are simulation examples that show the results of varying the delay at the input delay chain D1 For more information about controlling these delay chains and how to vary the output delay chains D5 and D6 refer to the Design Example 1 Dynamically Changing Delay Chains in Output Buffer of Stratix III section of the I O Buffer ALTIOBUF Megafunction User Guide Setting the Input Delay Chain D1 to Zero Delay default Figure 4 19 shows that there are no timing difference with the cursor at 70 ns when D1 is set to zero delay The cursor at 70 ns represents the path from the bidirectional buffer Didir dq input data in through the input delay chain bidir dq 0 input delay chain inst You can view the effects of the delay chain by comparing the datain port and the dataout port of the bidir dq 0 input delay chain inst ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation 100109 BAY 20102 094 195 500 11011 Figure 4 19 shows the simulation results for D1 with zero delay Figure 4 19 Simulation Results D1 is Set to Zero Delay Default File Edit View Insert
148. regouthi and bidir dq 0 ddio in inst regoutlo ofthe previous DDIO IN ports channeled to two input phase alignment blocks respectively These input phase alignment blocks are clocked at 333 333 MHz by the c2 clock output of the PLL The outputs of the two IPAs bidir dq 0 ipa high inst dataout and bidir dq 0 ipa low inst dataout are channeled to a half rate input block which is clocked by the CLOCK DIVIDER blocks Theoutputbidir dq 0 half rate input inst dataout 3 0 of this block is then connected to the bidir dq hr input data out 3 0 outputs The same data is propagated through the other bidirectional pins of bidir dq io 7 1 which causes the bidir dq hr input data out 31 4 outputs to toggle in the same manner The throughput of the data in the output ports are at a half rate of 166 666 MHz The input delay chain is enabled Thebidir dq 0 input delay chain inst datain and bidir dq 0 input delay chain inst dataout signals are not aligned which indicates that there is a delay on the input delay chain The same read sequence applies to reading data with different chain values activated on the input delay chain You can obtain the difference in the delay chain values by analyzing the timing paths of the following signals m bidir dq io 0 m bidir dq 0 input delay chain inst datain m bidir dq 0 input delay chain inst dataout m bidir dq 0 ddio in inst regouthi m bidir dq 0 ddi
149. rmation about how to enable these blocks refer to Parameter Settings on page 3 1 dqs oe out Output Optional This port receives the output signal from the DQS OE DELAY CHAIN2 dataout DQS OE DELAY CHAIN1 dataout DQS OE FF q DQS OE DDIO OE dataout Or dqs oe in port For information about how to enable these blocks refer to Parameter Settings on page 3 1 dqs output reg clk Input Optional GND This port is connected to the Dos OE FF c1k and the DOS OE ports that is used to clock the registers in those blocks dqs output reg clkena Input Optional Vec This port is connected to the DOS_OE_FF ena and the DOS OE DDIO OE ena ports that is used as output enable for the registers in those block dqs sreset Input Optional GND 1 This port is connected to the Dos OE FF sclr and DQS OE DDIO OE sreset ports that is used to synchronously reset all registers in those blocks February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 37 DQ DQS OCT Path Megafunction Ports Chapter 4 Functional Description ALTDQ_DQS Megafunction Ports Table 4 14 summarizes all the ports on the megafunction that configure the OCT path The possible values for IO are DOS DOSn BIDIR_DQ and OUTPUT Table 4 14 Megafunction Ports to Configure OCT Path Part 1 of 2 Optional Port Name Type Required Default Description bidir
150. rs tables in About these Megafunctions Added Sub Blocks Parameters and Ports in About these Megafunctions m Added Advanced Options tables in Getting Started m Removed figures in Getting Started m Added new tables in Specifications m Added Primitives on page 1 51 July 2008 v1 0 Initial release How to Contact Altera For the most up to date information about Altera products refer to the following table Contact Contact Note 1 Method Address Technical support Website www altera com support Technical training Website www altera com training Email custrain altera com Altera literature services Email literature altera com Non technical support General Email nacomp altera com February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide Info 2 Typographic Conventions Contact Contact Wote 1 Method Address Email authorization altera com Non technical support Software Licensing Note 1 You can also contact your local Altera sales office or sales representative Typographic Conventions The following table lists the typographic conventions that this document uses Visual Cue Bold Type with Initial Capital Let ters Command names dialog box titles checkbox options and dialog box options are shown in bold initial capital letters Example Save As dialog box bold type External timing pa
151. s for the bidirectional DQ pins To instantiate these three types of I O buffers perform the following steps 1 In the Quartus II software on the Tools menu click MegaWizard Plug In Manager On page 1 select Create a new custom megafunction variation Click Next Page 2a appears On page 2a select or verify the configuration settings shown in Table 4 34 Click Next to advance from one page to the next Table 4 34 ALTIOBUF Configuration Settings Value Settings 1 bidirectional buffer for 1 output buffer for the 8 bidirectional buffers for the differential DQS pins output DQ pins the bidirectional DQ pins Which device family will you be Stratix 111 Stratix 111 Stratix 111 using Which megafunction would you like to ALTIOBUF ALTIOBUF ALTIOBUF customize Which type of output file do you want Verilog HDL Verilog HDL Verilog HDL to create What name do you want for the output dqs_iobuf_inst v output_dq_iobuf_inst v bidir_dq_iobuf_inst v file 4 On the Parameter Settings page specify the parameters as shown in Table 4 35 These parameters configure the general settings for the ALTIOBUF instance February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 55 Table 4 35 ALTIOBUF General Settings Chapter 4 Functional Description Design Example Implementing Half Rate DDR2 Interface in Stratix III Value contro
152. sbusout signal is GND on the next falling edge of the DOS ENABLE dqsin signal The Dos ENABLE dqsbusout is connected directly to the dqs bus out port dqs input data in Input Optional GND This port receives the incoming DQS signal for the DQS input path dqs input data out Output Optional This port receives the outgoing DQS signal from the DQS DELAY CHAIN busout port or directly from the dqs input data in port dqsupdateen Input Optional GND This active high port is connected to the DQS DELAY CHAIN dqsupdateen port that is used to latch the DQS DELAY CHAIN delayctrlin 5 0 and DQS DELAY CHAIN offsetctrlin 5 0 signals The dqsupdateen port is fed by the ALTDLL dll dqsupdate port or the core Io clock divider clk Input Optional GND This port is connected to the IO CLOCK DIVIDER clk port that is the clock input port for that block Io clock divider clkout n 1 0 Output Optional This port is connected to the IO_CLOCK_DIVIDER clkout port that is used to output clock signal that is half the frequency of the IO CLOCK DIVIDER clk signal Io clock divider masterin Input Optional GND This port is connected to the IO CLOCK DIVIDER masterin that is used when you need to chain multiple clock dividers together to feed wider DQS groups Io clock divider Slaveout Output Optional This port is co
153. signments Turned off 5 In the Advanced Options tab of the ALTDO DOS parameter editor on the DOS IN page specify the parameters as shown in Table 4 27 These parameters configure the DOS input path of the ALTDO DOS instance Table 4 27 Advanced Options DQS IN Part 1 of 2 Parameter Sub options Value Enable DQS Input Path Turned on Enable Dynamic Delay Chain Not selected Enable dqs_delay_chain Selected Advanced delay chain options Select dynamically using Turned off configuration registers DOS delay chain delayctrlin port DLL source DOS Delay Buffer Mode HIGH DQS Phase Shift 9000 Enable 005 offset Control Turned off Enable DQS delay chain latches Turned off Enable DQS busout delay chain Turned on Enable DQS enable block Turned on Enable DQS enable control block Turned on ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description Design Example Implementing Half Rate DDR2 Interface in Stratix III Devices Table 4 27 Advanced Options DQS IN Part 2 of 2 4 52 chain Parameter Sub options Value Advanced enable control options DQS Enable Control Phase setting Set Statically to 0 DQS Enable Control Invert Phase Never Enable DQS enable block delay Turned on 6 On the DQS OUT OE page specify the parameters as shown in Table 4 28 These paramet
154. skewing the DQ bus for board trace mismatches between the FPGA and external memory interface The graph on the left is obtained when no deskew delay chains are used The capture window is small because of the board trace delays The graph on the right is obtained when deskew delay chains are used to deskew the DQ bus appropriately based on the board trace delays to maximize the capture window The deskew delay chains reduce SSN by delaying the DQ bus by small amounts of delay compared to the period of the signal on adjacent DQ pins Refer to Figure 4 8 February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 17 Chapter 4 Functional Description Delay Chains Figure 4 9 Reduce SSN Using Deskew Delay Chains The SSN is induced when adjacent pins in a DQ bus that toggle at the same time especially at a high frequency induces noise that affects signal integrity To ensure that the adjacent pins in a DQ bus are not toggled at the same time deskew delay chains are used to provide small amounts of delay Refer to Figure 4 9 You can access these delay chains in the ALTDQ_DQS megafunction for the DQ Input Path D1 and DQ Output Path D5 and D6 These 50 ps step delay chains provide small amounts of delay 297 You must create a custom calibration circuit to control these delay chains to reduce SSN ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter
155. t data out Output Optional This port outputs the signal from the DQSn input path This port is connected to the DQSN DELAY CHAIN dataout or dqsn input data in port dqsn oe in Input Optional GND This port feeds the input signal for the DQSn OE path This port is connected to the DQSN OE FF d DQSN OE DDIO OE oe DQSN OE DELAY CHAINI1 datain DQSN OE DELAY CHAIN2 datain dqsn oe out port dqsn oe out Output Optional This port is fed by the output signal from DQSn OE path This port can be driven by the DQOSN OE DELAY CHAIN2 dataout DQSN OE DELAY CHAIN1 dataout DQSN OE FF q DQSN OE DDIO OE dataout dqsn oe in port dqsn output data in Input Optional GND This port feeds the input signal for DQSn output path This port is connected to the DQSN OUTPUT FF d DQSN OUTPUT DELAY CHAIN1 datain 5 OUTPUT DELAY CHAIN2 datain Or dgqsn output data out port dqsn output data in hig h Input Optional GND This port feeds the full rate DDR input signal rising edge to the DQSn output path This port is connected to the DQSN OUTPUT DDIO OUT datainhi port dqsn output data in low Input Optional GND This port feeds the full rate DDR input signal falling edge to the DQSn output path This port is connected to the DQSN_OUTPU _DDIO_OUT datainlo port dqsn_output_data_out Output Optional This port
156. t registers Select FF DOS output if you want flip flop output registers or DDIO if you want register mode double data rate 1 0 registers DOS Output USE DQS OE PATH Instantiates DQS output enable path Enable Options Enable DOS output enable DOS Output USE DQS OE DELAY Enables 005 OUTPUT DELAY CHAIN 05 in the Enable Options DQS OE path This parameter is used for deskew Enable DOS purposes or SSN reduction D6 is a run time adjustable output enable delay chain delay chain DOS Output USE DQS OE DELAY Enables 005 OUTPUT DELAY CHAIN D6 in the Enable Options CHAIN2 DQS OE path This parameter is used for deskew Enable DOS purposes or SSN reduction D6 is a run time adjustable output enable delay chain delay chain2 DQS Output Not used FF Dos oE REG MODE Enables the Dos OUTPUT FF Or Enable Options or DDIO DQS OUTPUT OUT output registers Select FF DOS output if you want flip flop registers or DDIO if you want double enable register data rate 1 0 registers mode Table 3 6 describes options available on the DQ IN page This page allows you to configure the DQ input path For more information about the DQ input path refer to DQ Input Path on page 4 8 February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 3 12 Chapter 3 Parameter Settings ALTDQ_DQS Parameter Editor Table 3 6 Options on DQ IN Page Part 1 of 3 Parameter Name DQ Input Register Options
157. t to synchronize this divider with another 1 0 clock divider If you turn off this option this divider operates independently This mode is meant for the master divider of a group of dividers Turn on this parameter when you chain the 1 0 clock divider blocks from multiple ALTDQ_DQS instances Create io_clock_divider _clkout output port Divides the clock output signal by two The clock out signal can be connected to the clock input of a half rate Input block or fed to the FPGA core February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 3 16 Table 3 8 Options on Half Rate Page Part 2 of 2 Chapter 3 Parameter Settings ALTDQ_DQS Parameter Editor Create io_clock_divider _Slaveout output port Parameter Name Legal Value Clear Box Parameter Name USE_IO_CLOCK_ DIVIDER_SLAVEOUT Enables the output of the divider s D flip flop DFF The Description output signal can only be connected to the masterin input of another 0 clock divider block and it cannot have more than one fan out Turn on this parameter when you chain the 1 0 clock divider blocks from multiple ALTDQ_DQS instances 10 Clock Divider Invert Phase Always Never or Based on register configuration IO CLOCK DIVIDER INVERT PHASE If you turn on Always the phase output is inverted If you turn on Never the phase output is not inverted If you turn on Bas
158. t v bidir dq iobuf inst v is generated 7 Onthe File menu click Save Integrate the 1 0 Buffer Modules with the ALTDQ 008 modules To integrate the I O buffer modules with the ALTDO DOS modules perform the following steps 1 Open the test dq dqs bdf file in the Quartus II Block Editor software 2 insert the I O buffer modules double click on the Block Editor window Symbol window appears 3 Under Name browse to the I O buffer dqs iobuf inst bsf file 4 Click OK The I O buffer module is inserted into the Block Editor window ALTDLL and ALTDQ DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description 4 56 Design Example Implementing Half Rate DDR2 Interface in Stratix III Devices 5 Repeat steps 1 to 4 to insert other I O buffer modules 6 Use the appropriate connectors from the Block Editor toolbar to connect the I O buffer modules to the dq_dqs_inst v module as shown in Figure 4 24 T For more information about the Quartus II Block Editor refer to Using the Block Editor in the Quartus Help February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide Jasy 500 00117 pue 11011 1001020 Bally 2102 Menga Figure 4 24 shows a block diagram of the design example which consists of six blocks Figure 4 24 Block Diagram of Design Example exssssomonnann
159. ta_out 31 0 The OE path from the FPGA core to the bidirectional buffer bidir_dq_hr_oe_in 15 0 is 16 bits wide and is active low 4 For the DQ output pin the output path in the FPGA core to the bidirectional DO pin is represented by a 4 bit input output dq hr output data in 3 0 The OE path is 2 bits wide from the FPGA core to the bidirectional buffer output dq hr oe in 1 0 gt In the first part of the simulation only output paths are used therefore bidir dq hr oe in 15 0 16 b0 and dgs hr oe in 1 0 270 5 Forbidir dq hr output data in 31 0 eachbitis toggled with a 10 2 data signal from 100 ns to 300 ns The toggling behavior of bidir dq hr output data in 31 0 is represented in the waveform in groups of 4 bit signals for example bidir dq hr output data in 3 0 as the four input paths are connected to thebidir dq io 0 pin 6 Thebidir dq hr output in 3 and bidir dq hr output data in 2 signals go through the DDIO OUT port which is clocked at 166 666 MHz by the c3 PLL clock output At the same time the bidir dq hr output data in 1 and bidir dq hr output data in 0 signals go through another DDIO OUT port which is clocked at 166 666 MHz by the c3 PLL clock output February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 61 7 10 11 12 13 Chapter 4 Functional Description Design Example Implementing Half Rate DDR2 Interface in Stratix III
160. th enable control block Delay chain USE DOS INPUT Enables lt O gt _INPUT_DELAY_CHAIN D1 on the usage DELAY_CHAIN DQS input path If you turn on this parameter Enable dynamic DQS DELAY CHAIN block in the path is disabled D1 delay chain is a run time adjustable delay chain To configure delay chains dynamically refer to Delay Chains on page 4 15 Delay chain USE DOS DELAY Enables 005 DELAY CHAIN block The DQS delay usage CHAIN chain is a DLL controlled delay chain used to phase shift Enable the DQS read clock dqs delay chain Enable DQS USE DQSBUSOUT Enables 05 0500 DELAY CHAIN Da This busout delay DELAY CHAIN busout delay chain fine tunes the outputs of chain DQS DELAY CHAIN block so that the 005 strobe timing matches the DQS enable signal The DQS strobe has 15 steppable delays with each step having 50 ps of delay Da is a run time adjustable delay chain Enable DOS USE DQS ENABLE Enables Dos ENABLE block This block grounds the enable block DQS input strobe when the strobe goes to high impedance state 7 after a DDR read postamble Enable DOS USE_DQS_ENABLE_ Enables DoS ENABLE CTRL block that controls CTRL enable circuitry You must determine an efficient working resync postamble clk clock phase which clocks this block to ensure smooth data transfer The ALTDQ DQS megafunction cannot determine the phase for the data transfer
161. the IO CONFIG and DOS CONFIG blocks refer to DOS CONFIG IO CONFIG Block on page 4 22 T For more information about input buffer output buffer or bidirectional buffer refer to the I O Buffer CALTIOBUF Megafunction User Guide Figure 4 10 through Figure 4 17 show the various configurations of the ALTDQ_DQS megafunction when combined with the ALTIOBUF megafunction These configurations apply to both the DQ and DOS I O pins The use of the datain and datout signals in these figures are generic These signals represent either data clock or strobe in external memory interfaces Figure 4 10 Input Only Single Ended datain dataout po ALTDO pos ALTIOBUF Figure 4 11 Input Only Differential datain e dataout IO IBUF I 9 ALTDQ_DQS datain n ALTIOBUF February 2012 Altera Corporation ALTDLL and ALTDQ_DQS Megafunctions User Guide 4 19 Chapter 4 Functional Description ALTIOBUF Megafunction and Delay Chains Integration Figure 4 12 Input Only Complementary datain p IO IBUF gt dataout_p a ALTIOBUF ALTDQ_DQS i dataout_n datain_n IO IBUF ut ALTIOBUF Figure 4 13 Output Only Single Ended oe 1
162. tings for this delay delay These delay chains are for write chain because the delay calibration in DDR applications D5 is control in the chain is cascaded together with D6 to generate 4 bits wide the sum of delays D6 and D6 OCT D6 is the output register to I O buffer There are 8 possible 50 0 gt Each step value is either 50 or 400 ps Setting the number of stages in the delay chain to 10 means 10 x 50 ps 500 ps of delay The minimum delay value factors in only variable delays but not the intrinsic delay present in the delay chain For more information about intrinsic delays refer to the respective Arria II GX HardCopy IIL HardCopy IV Stratix III and Stratix IV device handbook or data sheet ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description 4 16 Delay Chains Deskew Delay Chains The deskew delay chain feature in Stratix III or Stratix IV devices is useful in external memory interfaces such as DDR or DDR2 external memory interfaces Refer to Figure 4 8 Figure 4 8 Deskew Delay Chains Incoming DQS Prior to de skew small valid capture window strobe phase After de skew maximize valid capture window 005 005 0 15 30 45 60 75 90 105 120 135 150 165 180 0 15 30 45 60 75 90 105 120 135 150 165 180 40 dqt dq2 dq3 4 095 446 097 Incoming DQ data bus This feature is useful in de
163. ts bidir dq oe in ny 1 0 Input Optional GND This port feeds the bidirectional DQ OE signal for the BIDIR DQ OE FF d BIDIR DQ OE DDIO OE oe BIDIR OE DELAY CHAIN1 datain BIDIR DQ OE DELAY CHAIN2 datain Orbidir dq oe out bidir dq oe out n 1 0 Output Optional This port is driven by the BIDIR DQ OE DELAY CHAIN2 dataout BIDIR OE DELAY CHAINi1 dataout BIDIR OE FF q BIDIR OE DDIO OE dataout Or bidir dq oe in port bidir dq sreset n 1 0 Input Optional GND This port is connected to all sreset port in the bidir DQ 10 primitives that is used to synchronously reset the registers in those primitives dq hr output reg clk Input Optional GND This port feeds the half rate clock signal for the l0 HR DDIO OUT clkhi clklo muxse1 ports The clock signal is for the half rate DDIO registers dq output reg clk Input Optional GND This port feeds the clock signal for the l0 OE FF clk and l0 OE DDIO OE clk ports dq output reg clkena Input Optional This port feeds the output enable signal for the l0 FF ena and l0 DDIO OE ena ports output dq areset n 1 0 Input Optional GND This port is connected to all areset ports in the output DQ 10 primitives that is used to asynchronously reset the registers in those primitives output dq hr oe in 2
164. ut registers in the DQ output path l0 FF l0 DDIO OE DQ output enable register blocks Sends output enable signal to the output buffer These blocks are clocked by the DQ write clock lt 0 gt rr block represents a group of flip flop registers in the DQ OE path The lt 0 gt ok represents a group of double data rate registers in the DQ OE path l0 OUTPUT HR DDIO OUT HIGH and l0 OUTPUT HR DDIO OUT LOW Half rate output register block Represents the DDIO registers that are used to transfer DQ signals from the core during half rate write operation These blocks are clocked by the DQ write clock l0 DDIO OUT Half rate output enable register block Represents the DDIO registers that are used to transfer half rate DQ output enable signals to the output buffer l0 OUTPUT DELAY 1 05 DQ output delay For more information about the DQ output and OE delay l0 OUTPUT DELAY CHAIN2 D6 chains chains refer to Table 4 2 on page 4 4 l0 DELAY CHAINI 05 DQ OE delay l0 DELAY CHAIN2 06 chains IO CONFIG 1 0 Configuration For more information about the ro coNF IG block refer Block to Table 4 2 on page 4 4 ALTDLL and ALTDQ DQS Megafunctions User Guide February 2012 Altera Corporation Chapter 4 Functional Description 4 12
165. when the sequence of the items is impor a b etc tant such as the steps listed in a procedure Hm Bullets are used in a list of items when the sequence of the items is not important checkmark indicates procedure that consists of one step only The hand points to information that requires special attention gt Yl CAUTION A caution calls attention to a condition or possible situation that can damage or destroy the product or the user s work P 5 z 2 A warning calls attention to a condition or possible situation that can cause injury to the user t The angled arrow indicates you should press the Enter key The feet direct you to more information on a particular topic ALTDLL and ALTDQ_DQS Megafunctions User Guide February 2012 Altera Corporation

Download Pdf Manuals

Related Search

ALTERA ALTDLL ALTDQ_DQS Megafunctions user manual

Related Contents

                Philips CMS Patient Monitoring System serve Service Manual  JD 4.0 LCD user manual  

Copyright © All rights reserved.