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ALTERA Arria V Hard IP for PCI Express user manual

1. 0 1 2 3 5 4 3 2 1 0 7 6 5 2111017 6 5 413 211 7 6 5 413 21 0 Byte0 R 0 0 0 0 1 0 1 0 0 0 00 0 O 0 ar 0 000000 0 1 Byte 4 Requester ID Tag 0 0 0 O First BE Byte 8 Bus Number Device No Func 0 0 0 0 Ext Reg Register No 0 0 Byte 12 Reserved Table A 6 1 0 Read Request 0 1 2 3 71615 141312111017 165 2111017 6 5 413 211 716 5 413 21 0 Byte0 00 0 IOIO ar 0 000000 0 1 Byte 4 Requester ID Tag 0 0 0 O First BE Byte 8 Address 31 2 0 0 Byte 12 Reserved Table A 7 Message without Data 0 1 2 3 71615 141312 11 0 1765 211107 6 51413211 71615 413 21110 Byteo fojo 1 1 0 5 4 0 vc 0 0 0 0 0 ar 0 00000000 0 Byte 4 Requester ID Tag Message Code Byte 8 Vendor defined or all zeros Byte 12 Vendor defined or all zeros Notes to Table A 7 1 Not supported in Avalon MM Table A 8 Completion without Data 0 1 2 3 7 6 5 4 3 2 1 0 7 6 5 2 1 0 7 6 5143 2 71615 413 211 0
2. tl cfg add 3 0 D Jj 0 1 2 3 il cfg ctl 31 ol 00000084 00000000 28100000 080000 ov Arria V Hard IP for PCI Express User Guide June 2012 Altera Corporation Chapter 7 IP Core Interfaces Arria V Hard IP for PCI Express Configuration Space Register Access The t1 cfg ct1 signal is a multiplexed bus that contains the contents of Configuration Space registers as shown in Table 7 11 Information stored in the Configuration Space is accessed in round robin order where t1 cfg add indicates which register is being accessed Table 7 13 shows the layout of configuration information that is multiplexed on t1 cfg ct1 1 33 Table 7 13 Multiplexed Configuration Register Information Available on tl cfg ctl 1 Index 31 24 23 16 cfg_dev_ctrl_func lt n gt 15 0 15 8 7 0 cfg_dev_ctr12 15 0 cfg_dev_ctr1 14 12 cfg_dev_ctr1l 7 5 Max Read Req Size 2 Max Payload 0 1 16 h0000 cfg slot ctrl 15 0 2 cfg link ctrl 15 0 cfg link ctr12 15 0 3 8 n00 cfg prm cmd func n 15 0 efg root ctr l 720 4 sec ctrl 15 0 cfg secbus 7 0 cfg subbus 7 0 5 cfg msi addr 11 0 cfg io bas 19 0 6 cfg msi addr 43 32 cfg io lim 19 0 7 8h 00 cf
3. 0 1 2 3 5 4 3 2 1 0 7 6 5 4 07 6 5 4 13 2 0171615 14 3 2 11 10 Byte 010 010 0 0 0 00 0 Attr AT Length Byte 4 Requester ID Tag Last BE First BE Byte 8 Address 31 2 0 0 Byte 12 Reserved Table A 2 Memory Read Request Locked 32 Bit Addressing 0 1 2 3 7 6 5 4 3 2 1 0 7 6 5 1 0 7 6 5 141312111017 16 5 413 21110 Byte 0 0 0 0000 1 0 TC 0 0 TD EP AT Length Byte 4 Requester ID Tag Last BE First BE Byte 8 Address 31 2 0 0 Byte 12 Reserved Table A 3 Memory Read Request 64 Bit Addressing 0 1 2 3 7 5 432 1 0 7 6 5 11017 6 5 1413 121110171615 413 2110 ByteO 0 110000 0 0 TC 0 0 TD EP pi AT Length Byte 4 Requester ID Tag Last BE First BE Byte 8 Address 63 32 Byte 12 Address 31 2 0 0 Table A 4 Memory Read Request Locked 64 Bit Addressing 0 1 2 3 7 5141312111017 165 110 7 6 5 41312 111017 615 413 12110 Byteo 0 0 1 00 0 0 10 0 0i ge ar Length Byte 4 Requester ID Tag Last BE First BE Byte 8 Address 63 32 Byte 12 Address 31 2 0 0 June 2012 Altera Corporation Arria V Hard IP for PCI Express User Guide A ii Chapter A Transaction Layer Packet TLP Header Formats TLP Packet Format without Data Payload Table A 5 Configuration Read Request Root Port Type 1
4. Figure 7 19 illustrates the mapping between Avalon ST TX packets and PCI Express TLPs for four dword header with non qword aligned addresses with a 64 bit bus Figure 7 19 64 Bit Avalon ST tx_st_data Cycle Definition for TLP 4 Dword Header with Non Qword Aligned Address eek f LI LJ LI Li ix st data 63 32 Header 1 Header3 Datad Data2 tx_st_data 31 0 HeaderO Header Daai f wxstsp f tx_st_eop ae Arria V Hard IP for PCI Express June 2012 Altera Corporation User Guide Chapter 7 IP Core Interfaces 7 19 Arria V Hard IP for PCI Express Figure 7 20 illustrates the timing of the TX interface when the Arria V Hard IP for PCI Express IP core backpressures the Application Layer by deasserting tx_st_ready Because the readyLatency is two cycles the Application Layer deasserts tx_st_valid after two cycles and holds tx_st_data until two cycles after tx_st_ready is asserted Figure 7 20 64 Bit Transaction Layer Backpressures the Application Layer coredkout esta teen tx st data 63 0 00 Xoo 2 BBBB0306BBB0305A __ TN tx_st_ready siamo tx_st_valid Figure 7 21 illustrates back to back transmission of 64 bit packets with no intervening dead cy
5. 31 16 15 14 13 12119 8 7 6 5 1 0 Rsvd Rsvd Rsvd A Header Log Overflow Status Corrected Internal Error Status Advisory Non Fatal Error Status Replay Timer Timeout Status REPLAY NUM Rollover Status Bad DLLP Status Bad TLP Status Receiver Error Status Arria V Hard IP for PCI Express June 2012 Altera Corporation User Guide RYN 15 Transceiver PHY IP Reconfiguration As silicon progresses towards smaller process nodes circuit performance is affected more by variations due to process voltage and temperature PVT These process variations result in analog voltages that can be offset from required ranges You must compensate for this variation by including the Transceiver Reconfiguration Controller IP Core in your design You can instantiate this component using the MegaWizard Plug In Manager or Qsys It is available for Arria V devices and can be found in the Interfaces Transceiver PHY category for the MegaWizard design flow In Qsys you can find the Transceiver Reconfiguration Controller in the Interface Protocols Transceiver PHY category When you instantiate your Transceiver Reconfiguration Controller IP core the Enable offset cancellation block option is On by default This feature is all that is required to ensure that the transceivers operate within the required ranges but you can choose to enable other features such as the Enable analog PMA reconfiguratio
6. ean 5 2 Device Identification Registers sss en 5 3 PCI Express PCI Capabilities ette eE eet teet ql e e oet ete eon ea 5 3 a c Tc 5 4 Error Reporting eer deg ob eost eH aei E Wa RR 5 5 qe rc CMT PU IE 5 5 Power Management pee ter ace eroe ebbe pe Ee dede ed reside ed este 5 6 Avalon Memory Mapped System Settings sss 5 7 Avalon to PCIe Address Translation Settings 5 7 Chapter 6 IP Core Architecture Key Interfaces PERS a Se Dues A Fe a opido tee ue eet te aed ences 6 2 Avalon ST Interface ics eup paul iR ses dede tedesca s 6 3 RX epe Paese dee Pe 6 3 TX Datta path 6 3 Avalon MM Interface esee ore eia ee ne ie doe oed deed tis 6 3 Clocks and Reset ced Metin eet hee ep eerte depo e erga dete e deducta 6 4 Local Management Interface LMI Interface lsssssssssseeee eee eee 6 4 Transceiver Reconfiguration 0666 he nen 6 4 Interrupts x a s Eee eoe eed Fees cea Fea oo pee dee be oer bere 6 4 Protocol Bayets iius sedes rater ehe spat inn sce Ua tg duet d orden te doses 6 5 Transaction Layer LE Recte ee I SH heb Spe n ae SOR E Se Ree ip oec te en 6 5 Configuration Space iu ente epe eR e e eH wos Gea heey
7. coreclkout M aes eo W EN Header2 Data W Dean i EN Header Datao W Dean rx st data 127 96 Ix St data 95 64 Ix St data 63 32 st data 31 0 HeaderO W Daan IX St sop _ rx_st_eop i rx_st_valid rx_st_empty Arria V Hard IP for PCI Express June 2012 Altera Corporation User Guide Chapter 7 IP Core Interfaces 7 13 Arria V Hard IP for PCI Express Figure 7 13 shows the mapping of 128 bit Avalon ST RX packets to PCI Express TLPs for a four dword header with qword aligned addresses Figure 7 13 128 Bit Avalon ST rx st data Cycle Definition for 4 Dword Header TLP with Qword Aligned Address coreclkout IM rx_st_data 127 96 TENN Headers Dats Datan rx_st_data 95 64 IN Header2 Data2 rx_st_data 63 32 Header Data W rx_st_data 31 0 Headero Dato IX St sop fT W rX St eop Ix st valid W Ix st empty Figure 7 14 illustrates the timing of the RX interface when the Application Layer backpressures the Hard IP by deasserting rx st ready The rx st valid signal must deassert within three cycles after rx st ready is deasserted In this example rx st validis deasserted in the next cycle Figure 7 14 128 Bit Application Laye
8. Specifies the scale used for the Slot power limit The following coefficients are defined m 0 1 0x m 1 0 1x m 2 0 01x m 3 0 001x The default value prior to hardware and firmware initialization is b O or 1 0x Writes to this register also cause the port to send the Set_Slot_Power_Limit Message Refer to Section 6 9 of the PC Express Base Specification Revision 2 1 for more information Slot power scale 0 3 Arria V Hard IP for PCI Express June 2012 Altera Corporation User Guide Chapter 4 Parameter Settings for the Arria V Hard IP for PCI Express 4 7 Port Functions Table 4 5 Slot Capabilities 0x094 Parameter Value Description In combination with the Slot power scale value specifies the upper limit in watts on Slot power limit 0 255 power supplied by the slot Refer to Section 7 8 9 of the PC Express Base Specification Revision 2 1 for more information Slot number 0 8191 Specifies the slot number Power Management Table 4 6 describes the Power Management parameters Table 4 6 Power Management Parameters Parameter Endpoint LOs acceptable latency Value lt 64 ns gt No limit Description This design parameter specifies the maximum acceptable latency that the device can tolerate to exit the LOs state for any links between the device and the root complex It sets the read only value of the Endpoint LOs acceptable latency field of the Device Capa
9. Arria V Hard IP for PCI Express June 2012 Altera Corporation User Guide Chapter 17 Debugging Link Training Table 17 1 Link Training Fails to Reach LO Part 2 of 2 17 3 Possible Causes Symptoms and Root Causes Workarounds and Solutions Link fails with the LTSSM toggling between Detect Quiet 0 Detect Active 1 and Polling Active 2 or Detect Quiet 0 Detect Active 1 and Polling Configuration 4 On the PIPE interface extracted from the test_out bus confirm that the Hard IP for PCI Express IP Core is transmitting valid TS1 in the Polling Active 2 state or TS1 and TS2 in the Polling Configuration 4 state on txdata0 The Root Port should be sending either the TS1 Ordered Set or a compliance pattern as seen on rxdata0 These symptoms indicate that the Root Port did not receive the valid training Ordered Set from Endpoint because the Endpoint transmitted corrupted data on the link You can debug this issue using SignalTap II Refer to PIPE Interface Signals on page 17 6 for a list of the test_out bus signals The following are some of the reasons the Endpoint might send corrupted data m Signal integrity issues Measure the TX eye and check it against the eye opening requirements in the PCI Express Base Specification Rev 2 1 Adjust the transceiver pre emphasis and equalization settings to open the eye m Bypass the Transceiver Reconfiguration Controller IP Core to
10. structure stores the address assigned to each BAR so that the driver code does not need 0 ere to be aware of the actual assigned addresses only the Application Layer specific offsets from the BAR bar_num Number of the BAR used with pcie_offset to determine PCI Express address pcie_offset Address offset from the BAR base lcladdr BFM shared memory address of the data to be written Arria V Hard IP for PCI Express June 2012 Altera Corporation User Guide Chapter 16 Testbench and Design Example 16 29 BFM Procedures and Functions Table 16 20 ebfm_barwr Procedure Part 2 of 2 byte_len Length in bytes of the data written Can be 1 to the minimum of the bytes remaining in the BAR space or BFM shared memory tclass Traffic class used for the PCI Express transaction ebfm_barwr_imm Procedure The ebfm_barwr_imm procedure writes up to four bytes of data to an offset from the specified Endpoint BAR Table 16 21 ebfm_barwr_imm Procedure Location altpcietb bfm driver rp v Syntax ebfm barwr imm bar table bar num pcie offset imm data byte len tclass Address of the Endpoint bar table structure in BFM shared memory The bar table Arguments har tagi structure stores the address assigned to each BAR so that the driver code does not need 0 to be aware of the actual assigned addresses only the Application Layer specific offsets from the BAR bar_num Number of the BAR used with pcie_
11. Current value of the Avalon MM interrupt IRQ input ports to the Avalon MM RX master port m 0 Avalon MM IRQ is not being signaled 15 0 AVL IRQ ASSERTED 15 0 RO m 1 Avalon MM IRQ is being signaled A Qsys generated IP Compiler for PCI Express has as many as 16 distinct IRQ input ports Each AVL IRQ ASSERTED bitreflects the value on the corresponding IRQ input port Arria V Hard IP for PCI Express June 2012 Altera Corporation User Guide Chapter 8 Register Descriptions PCI Express Avalon MM Bridge Control Register Content 8 7 A PCI Express interrupt can be asserted for any of the conditions registered in the PCI Express Interrupt Status Register by setting the corresponding bits in the Avalon MM to PCI Express Interrupt Enable Register Table 8 12 Either MSI or legacy interrupts can be generated as explained in the section Enabling MSI or Legacy Interrupts on page 11 7 Table 8 12 describes the Avalon MM to PCI Express Interrupt Enable Register Table 8 12 Avalon MM to PCI Express Interrupt Enable Register 0x0050 Bits Name Access Description 31 25 Reserved Enables generation of PCI Express interrupts when a 23 16 A2P_MB_IRQ RW specified mailbox is written to by an external Avalon MM master Enables generation of PCI Express interrupts when a 15 0 AVL_IRQ 15 0 RX specified Avalon MM interrupt signal is asserted Your Qsys system may ha
12. Test Signals on page 7 52 Note to Table 7 1 1 Provided for simulation only Ls When you are parameterizing your IP core you can use the Show signals option in the Block Diagram to see how changing the parameterization changes the top level signals Figure 7 1 illustrates this option Figure 7 1 Show Signal Option for the Block Diagram b Arria V Hard IP for PCI Express Megatore altera_pcie_av_hip_ast a Block Diagram y Show signals pcie av hip ast O simu mode pipe tx_outO tx out clk Ix st n rx st valid vcO valid rx endofpacket endofpacket 51_ _ ready ready error error rx_st_data_vc0 63 9 Arria V Hard IP for PCI Express User Guide June 2012 Altera Corporation Chapter 7 IP Core Interfaces Arria V Hard IP for PCI Express Arria V Hard IP for PCI Express Figure 7 2 illustrates the top level signals in Arria V Hard IP for PCI Express IP core Signal names that include lt a gt also exist for functions 1 to 7 Figure 7 2 Signals in the Arria V Hard IP for PCI Express with Avalon ST Interface Arria V Hard IP for PCI Express Avalon ST Interface rx st sop rx st eop Avalon ST 4 rx_st_empty rx_st_ready RX Port rx_st_valid rx_st_err rx_st_mask Component rx_st_bar 7 0 Specific rx_st_be 7 0 15 0 tx_st_sop tx_st_eop Avalon ST 4 ix st
13. Interface Bundles Number of reconfiguration interfaces 5 Optional interface grouping e g 2 2 or leave blank for a single bundle The Transceiver Reconfiguration Controller includes an Optional interface grouping parameter Arria V devices include six channels in a transceiver bank For a x4 variant no special interface grouping is required because all 4 lanes and the TX PLL fit in one bank Ka Although you must initially create a separate logical reconfiguration interface for each lane and TX PLL in your design when the Quartus IT software compiles your design it reduces original number of logical interfaces by merging them Allowing the Quartus II software to merge reconfiguration interfaces gives the Fitter more flexibility in placing transceiver channels 57 You cannot use SignalTap to observe the reconfiguration interfaces Arria V Hard IP for PCI Express June 2012 Altera Corporation User Guide Chapter 15 Transceiver PHY IP Reconfiguration 15 3 Figure 15 3 shows the connections between the Transceiver Reconfiguration Controller instance and the PHY IP Core for PCI Express instance Figure 15 3 ALTGX_RECONFIG Connectivity 1 Hard IP for PCI Express PHY IP Core for PCI Express 100 125 MHz Avalon MM Slave Interface 4 reconfig busy to and from Embedded Controller Notes to Figure 15 3 1 The e
14. italic type Indicates variables For example n 1 Variable names are enclosed in angle brackets For example file name and lt project gt file Initial Capital Letters Indicate keyboard keys and menu names For example the Delete key and the Options menu Subheading Title Quotation marks indicate references to sections in a document and titles of Quartus Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI An angled arrow instructs you to press the Enter key 1 2 3 and Numbered steps indicate a list of items when the sequence of the items is important a b c and so on such as the steps listed in a procedure Hmm Bullets indicate a list of items when the sequence of the items is not important Is The hand points to information that requires special attention The question mark directs you to a software help system with related information
15. 0 666 n 2 18 ha ay 2 21 2 21 Understanding Channel Placement Guidelines 2 22 Quartus I Compilation e Er ena does be te ee ee ee 2 22 Compiling the Design in the MegaWizard Plug In Manager Design Flow 2 22 Compiling the Design in the Osys Design Flow e 2 23 Modifying the Example Design enn 2 24 Chapter 3 Getting Started with the Avalon MM Arria V Hard IP for PCI Express Creating a Quartus IL Project eise eee eere Ree R eee ee E ede a hed dee dee 3 3 Running OS VS oie diated 3 4 Customizing the Avalon MM Arria V Hard IP for PCI Express IP Core 3 4 Adding the Remaining Components to the Osys System 8 8 88 3 7 Completing the Connections in Qsys eee 3 10 Specifying Clocks and Address Assignments 3 11 Specifying Exported Interfaces liiis 3 11 Specifying Address Assignments 8 deires nekrotiese eee eee eee eens 3 11 Specifying Output Directories issuri e en 3 13 Simulating the Osys System 6 6 e enn 3 13 Understanding Channel Placement Guidelines sse 3 13 Gompiling the Design ese etteris Cem ote deter enr de HR ect RU HR cec Rate tech h
16. Register Name Value Vendor ID 0x00000000 Device ID 0x00000001 Revision ID 0x00000001 Arria V Hard IP for PCI Express User Guide June 2012 Altera Corporation Chapter 2 Getting Started with the Arria V Hard IP for PCI Express 2 13 Table 2 15 Device Identification Registers for FuncO Part 2 of 2 Class Code 0x00000000 Subsystem Vendor ID 0x00000000 Subsystem Device ID 0x00000000 11 On the Func 0 Device tab under PCI Express PCI Capabilities for Func 0 turn Function Level Reset FLR On 12 Specify the Link settings listed in Table 2 16 Table 2 16 Link Capabilities Parameter Value Data link layer active reporting Off Surprise down reporting Off 13 On the Func0 MSI tab for Number of MSI messages requested select 4 14 On the Func0 MSI X tab turn Implement MSI X turned off 15 On the Func0 Legacy Interrupt tab keep the default option INTA for Legacy Interrupt INT 16 Click the Finish button 17 To rename the Arria V hard IP for PCI Express in the Name column of the System Contents tab right click on the component name select Rename and type DUT Specifying the Parameters for the Example Design Follow these steps to add the Example design for Avalon Streaming Hard IP for PCI Express component to your Osys system 1 On the Component Library tab click Example design for Avalon Streaming Hard IP for PCI Express and then click Add The pa
17. Arria V Hard IP for PCI Express June 2012 Altera Corporation User Guide Chapter 6 IP Core Architecture 6 3 Key Interfaces Avalon ST Interface An Avalon ST interface connects the Application Layer and the Transaction Layer This is a point to point streaming interface designed for high throughput applications The Avalon ST interface includes the RX and TX datapaths Te For more information about the Avalon ST interface including timing diagrams refer to the Avalon Interface Specifications RX Datapath The RX datapath transports data from the Transaction Layer to the Application Layer s Avalon ST interface Masking of non posted requests is partially supported Refer to the description of the rx_st_mask signal for further information about masking For more detailed information about the RX datapath refer to Avalon ST RX Interface on page 7 5 TX Datapath The TX datapath transports data from the Application Layer s Avalon ST interface to the Transaction Layer The Hard IP provides credit information to the Application Layer for posted headers posted data non posted headers non posted data completion headers and completion data The Application Layer may track credits consumed and use the credit limit information to calculate the number of credits available However to enforce the PCI Express Flow Control FC protocol the Hard IP also checks the available credits before sending a request to the link and i
18. Incorrect payload size Determine if the length field of the last TLP transmitted by End Point is greater than the InitFC credit advertised by the link partner For simulation refer to the log file and simulation dump For hardware use a third party logic analyzer trace to capture PCle transactions If the payload is greater than the initFC credit advertised you must either increase the InitFC of the posted request to be greater than the max payload size or reduce the payload size of the requested TLP to be less than the InitFC value Flow control credit overflows Determine if the credit field associated with the current TLP type in the tx cred bus is less than the requested credit value When insufficient credits are available the core waits for the link partner to release the correct credit type Sufficient credits may be unavailable if the link partner increments credits more than expected creating a situation where the Arria V Hard IP for PCI Express IP Core credit calculation is out of sink with its link partner Add logic to detect conditions where the tx st ready signal remains deasserted for more than 100 cycles Set post triggering conditions to check the value of the tx cred and tx st interfaces Add a FIFO status signal to determine if the TXFIFO is full Arria V Hard IP for PCI Express User Guide June 2012 Altera Corporation Chapter 17 Debugging 17 5 Link Hangs in LO Due To De
19. close the APPS component click the X in the upper right hand corner of the parameter editor Go to Simulating the Example Design on page 2 18 for instructions on system simulation June 2012 Altera Corporation Arria V Hard IP for PCI Express User Guide 2 10 Chapter 2 Getting Started with the Arria V Hard IP for PCI Express Qsys Design Flow Qsys Design Flow This section guides you through the steps necessary to customize the Arria V Hard IP for PCI Express and run the example testbench in Qsys It includes the following steps m Customizing the Endpoint in Qsys Understanding the Files Generated Simulating the Example Design Understanding Channel Placement Guidelines Compiling the Design in the Qsys Design Flow Customizing the Endpoint in Qsys This section begins with the steps necessary to customize the Arria V Hard IP for PCI Express This section also guides you through steps to connect the chaining DMA component testbench described in Chapter 16 Testbench and Design Example to the Endpoint variant For further details about the parameter settings refer to Chapter 4 Parameter Settings for the Arria V Hard IP for PCI Express Follow these steps to instantiate the Arria V Hard IP for PCI Express and chaining DMA example design using the Qsys design flow 1 Create a directory for your project This example uses lt working_dir gt pcie_qsys 2 start Qsys from the Quartus II
20. 4 12 Chapter 4 Parameter Settings for the Arria V Hard IP for PCI Express Port Functions Arria V Hard IP for PCI Express June 2012 Altera Corporation User Guide JA DTE RA 5 Parameter Settings for the Avalon MM Arria V Hard IP for PCI Express This chapter describes the parameters which you can set using the Qsys design flow to instantiate an Avalon MM Arria V Hard IP for PCI Express IP core In the following tables hexadecimal addresses in green are links to additional information in the Register Descriptions chapter System Settings The first group of settings defines the overall system Table 5 1 describes these settings Table 5 1 System Settings for PCI Express Part 1 of 2 Parameter Number of Lanes Value x1 x4 x8 Description Specifies the maximum number of lanes supported Lane Rate Gen1 2 5 Gbps Gen2 5 0 Gbps Specifies the maximum data rate at which the link can operate Port type Native Endpoint Specifies the function of the port Native Endpoints store parameters in the Type 0 Configuration Space which is outlined in Table 8 2 on page 8 2 RX Buffer credit allocation performance for received requests Minimum Low Balanced High Maximum This setting determines the allocation of posted header credits posted data credits non posted header credits completion header credits and completion data credits in the 6 KByte RX buffer The 5 se
21. BFM Configuration Procedures on page 16 34 BFM Log Interface altpcietb bfm driver rp v The BFM log functions provides routines for writing commonly formatted messages to the simulator standard output and optionally to a log file It also provides controls that stop simulation on errors For details on these procedures see BFM Log and Message Procedures on page 16 37 BFM Request Interface altpcietb bfm driver rp v This interface provides the low level interface between the altpcietb bfm rdwr and altpcietb bfm configure procedures or functions and the Root Port RTL Model This interface stores a write protected data structure containing the sizes and the values programmed in the BAR registers of the Endpoint as well as other critical data used for internal BFM management You do not need to access these files directly to adapt the testbench to test your Endpoint application Avalon ST Interfaces altpcietb bfm vc intf v These interface modules handle the Root Port interface model They take requests from the BFM request interface and generate the required PCI Express transactions They handle completions received from the PCI Express link and notify the BFM request interface when requests are complete Additionally they handle any requests received from the PCI Express link and store or fetch data from the shared memory before generating the required completions Arria V Hard IP for PCI Express User Guide 16 22 Chapter 1
22. Software can enable the individual interrupts by writing to the PCI Express to Avalon MM Interrupt Enable Register 0x3070 on page 8 10 through the CRA slave When any interrupt input signal is asserted the corresponding bit is written in the Avalon MM to PCI Express Interrupt Status Register 0x0040 on page 8 6 Software reads this register and decides priority on servicing requested interrupts After servicing the interrupt software must clear the appropriate serviced interrupt status bit and ensure that no other interrupts are pending For interrupts caused by Avalon MM to PCI Express Interrupt Status Register 0x0040 on page 8 6 mailbox writes the status bits should be cleared in the Avalon MM to PCI Express Interrupt Status Register 0x0040 on page 8 6 For interrupts due to the incoming interrupt signals on the Avalon MM interface the interrupt status should be cleared in the Avalon MM component that sourced the interrupt This sequence prevents interrupt requests from being lost during interrupt servicing June 2012 Altera Corporation Arria V Hard IP for PCI Express User Guide 11 6 Chapter 11 Interrupts Interrupts for Endpoints Using the Avalon MM Interface to the Application Layer Figure 11 5 shows the logic for the entire interrupt generation process Figure 11 5 Avalon MM Interrupt Propagation to the PCI Express Link Interrupt Disable Configuration Space Command Register 10 Avalon MM to PCI Express I
23. Additionally the bridge must prevent each PCI Express read request packet from crossing a 4 KByte address boundary Therefore the bridge may split an Avalon MM read request into multiple PCI Express read packets based on the address and the size of the read request For Avalon MM read requests with a burst count greater than one all byte enables must be asserted There are no restrictions on byte enables for Avalon MM read requests with a burst count of one An invalid Avalon MM request can adversely affect system functionality resulting in a completion with the abort status set An example of an invalid request is one with an incorrect address PCI Express to Avalon MM Read Completions The PCI Express Avalon MM bridge returns read completion packets to the initiating Avalon MM master in the issuing order The bridge supports multiple and out of order completion packets PCI Express to Avalon MM Downstream Write Requests When the PCI Express Avalon MM bridge receives PCI Express write requests it converts them to burst write requests before sending them to the interconnect fabric The bridge translates the PCI Express address to the Avalon MM address space based on the BAR hit information and on address translation table values configured during the IP core parameterization Malformed write packets are dropped and therefore do not appear on the Avalon MM interface For downstream write and read requests if more than one byte enable is
24. INFO INFO Se dE db db db db dk 84901 ns TASK chained dma test 84901 ns DMA Write 84901 ns 84901 ns TASK dma wr test 84901 ns DMA Write 84901 ns 84901 ns TASK dma set wr desc data 84901 ns 84901 ns TASK dma set msi WRITE 84901 ns Message Signaled Interrupt Configuration 84901 ns msi address RC memory 0x07F0 87109 ns msi control register 0x00A5 96005ns msi expected OxBOFD 96005ns msi capabilities address 0x0050 96005ns multi message enable 0x0002 96005ns msi number 0001 96005ns msi traffic class 0000 96005 ns 96005 ns TASK dma set header WRITE 96005 ns Writing Descriptor header 96045 ns data content of the DT header 96045 ns 96045 ns Shared Memory Data Display 96045 ns Address Data 96045 ns 96045 ns 00000800 10100003 00000000 00000800 CAFEFADE 96045 ns 96045 ns TASK dma set rclast 96045ns Start WRITE DMA RC issues MWr RCLast 0002 96061 ns 96073 ns TASK msi poll PollingMSI Address 07F0 Data FADE 96257 ns TASK rcmem poll Polling RC Address0000080C current data expected data 00000002 101457 ns TASK rcmem poll Polling RC Address0000080C current data expected data 00000002 105177 ns TASK msi poll Received DMA Write MSI 0000 BOFD 105257 ns TASK rcmem_poll Polling RC Address0000080C current data expected data 00000002 105257 ns TASK rcmem poll gt Received Expected Data 00000002 1052
25. Peripheral Controller Debug Features The Arria V Hard IP for PCI Express includes debug features that allow observation and control of the Hard IP for faster debugging of system level problems For more information about debugging refer to Chapter 16 Debugging June 2012 Altera Corporation Arria V Hard IP for PCI Express User Guide 1 6 Chapter 1 Datasheet IP Core Verification IP Core Verification To ensure compliance with the PCI Express specification Altera performs extensive validation of the Arria V Hard IP Core for PCI Express The Gen1 x8 and Gen2 x4 Endpoints passed all PCI SIG gold tests and interoperability tests with a wide selection of motherboards and test equipment at the PCI SIG Compliance Workshop 79 in February 2012 Altera s simulation environment uses multiple testbenches that consist of industry standard BFMs driving the PCI Express link interface A custom BFM connects to the application side interface Altera performs the following tests in the simulation environment m Directed and pseudo random stimuli areArria applied to test the Application Layer interface Configuration space and all types and sizes of TLPs m Error injection tests that inject errors in the link TLPs and Data Link Layer Packets DLLPs and check for the proper responses m PCISIG Compliance Checklist tests that specifically test the items in the checklist m Random tests that test a wide range of
26. 12 N 12 y 12 N 12 Read Request N N Y N N 19 Y N N 12 Y N N Y N N 1 0 or Configuration N N Y N N 13 Y N N 14 Y N N Y N N Write Request N 11 N 11 Y N 1 NC Read Completion WIN 12 Y Y Y Y N 12 N 12 Y N N 0or amp Configuration 8 Write Y N N Y Y Y Y Y N N Y N N Completion Notes to Table 10 2 A Memory Write or Message Request with the Relaxed Ordering Attribute bit clear b 0 must not pass any other Memory Write or Message Request A Memory Write or Message Request with the Relaxed Ordering Attribute bit set b 1 is permitted to pass any other Memory Write or Message Request 3 Endpoints Switches and Root Complex may allow Memory Write and Message Requests to pass Completions or be blocked by Completions 4 Memory Write and Message Requests can pass Completions traveling in the PCI Express to PCI directions to avoid deadlock 5 If the Relaxed Ordering attribute is not set then a Read Completion cannot pass a previously enqueued Memory Write or Message Request 6 Ifthe Relaxed Ordering attribute is set then a Read Completion is permitted to pass a previously enqueued Memory Write or Message Request 7 Read Completion associated with different Read Requests are allowed to be blocked by or to pass each other 8 Read Completions for Request same Transaction ID must return in address order 9 Non posted requests cannot pass oth
27. 7 36 Chapter 7 IP Core Interfaces Arria V Hard IP for PCI Express Tahle 7 14 Configuration Space Register Descriptions Part 4 of 4 Register Reference Table 7 4 on cfg msi data 16 O cfg msi data 15 0 is message data for MSI page 7 3 0x050 Table A 5 on page A ii 0x08 Register Width Dir Description Bus Device Number captured by or programmed in the cfg busdev 13 0 Hard IP T Refer to the PCI Local Bus Specification for descriptions of the Control registers Table 7 15 describes the use of the various fields of the Configuration MSI Control and Status Register Table 7 15 Configuration MSI Control Register Field Descriptions Bit s Field Description 15 9 reserved Per vector masking capable This bit is hardwired to 0 because the functions do not 8 mask support the optional MSI per vector masking using the Mask Bits and capability Pending Bits registers defined in the PC Local Bus Specification Rev 3 0 Per vector masking can be implemented using Application Layer registers 64 bit 64 bit address capable 7 address m 1 function capable of sending a 64 bit message address capability 0 function not capable of sending a 64 bit message address Multiple message enable This field indicates permitted values for MSI signals For example if 100 is written to this field 16 MSI signals are allocated m 000 1 MSI allocated m 001 2 MSI allocated multipl
28. All unspecified cases are unsupported and the behavior of the Hard IP is unknown 2 The ECRC Generation Enable is inthe Configuration Space Advanced Error Capabilities and Control Register Lane Initialization and Reversal Connected components that include IP blocks for PCI Express need not support the same number of lanes The x4 variations support initialization and operation with components that have 1 2 or 4 lanes The x8 variant supports initialization and operation with components that have 1 2 4 or 8 lanes Arria V Hard IP for PCI Express User Guide June 2012 Altera Corporation Chapter 12 Optional Features Lane Initialization and Reversal Table 12 3 Lane Assignments without Lane Reversal 12 3 The Arria V Hard IP for PCI Express supports lane reversal which permits the logical reversal of lane numbers for the x1 x2 x4 and x8 configurations Lane reversal allows more flexibility in board layout reducing the number of signals that must cross over each other when routing the PCB Table 12 3 summarizes the lane assignments for normal configuration Lane Number 7 6 5 4 3 2 0 x8 IP core 7 6 5 3 2 0 x4 IP core 3 2 0 x1 IP core 0 Table 12 4 summarizes the lane assignments with lane reversal Table 12 4 Lane Assignments with Lane Reversal Core Config 8 4 Slot Size 8 4 2 1 8 4 2 1 8 4 2 1 06 1 5 2 4 3 3 3 4 2 5 1 6 7 0 6 1 3 0
29. Clocks tx st data to the Hard IP when tx st ready is also asserted Between tx st sopandtx st eop tx st valid be asserted only if tx st ready is asserted When tx st ready deasserts this signal must deassert within 1 or 2 clock cycles When tx st ready reasserts and tx st datais in mid TLP this signal must reassert within 2 cycles Refer to Figure 7 20 on page 7 19 for the timing of this signal To facilitate timing closure Altera recommends that you register both the tx st ready and tx st valid signals If no other delays are added to the ready valid latency the resulting delay corresponds to a readyLatency of 2 tx st empty empty Indicates the number of qwords that are empty during cycles that contain the end of a packet When asserted the empty qwords are in the high order bits Valid only when tx st eop s asserted Not used when tx st data is 64 bits When asserted indicates that the upper qword is empty does not contain valid data tx st err error Indicates an error on transmitted TLP This signal is used to nullify a packet It should only be applied to posted and completion TLPs with payload To nullify a packet assert this signal for 1 cycle after the SOP and before the EOP When a packet is nullified the following packet should not be transmitted until the next clock cycle tx st err is not available for packets that are 1 or 2 cycles long The error signal must be asserted while the
30. No Message Prefix DEBUG EBFM_MSG_INFO Specifies informational messages such as configuration register values starting and ending of tests Yes No INFO EBFM MSG WARNING Specifies warning messages such as tests being skipped due to the specific configuration Yes No WARNING EBFM MSG ERROR INFO Specifies additional information for an error Use this message to display preliminary information before an error message that stops simulation Yes No ERROR EBFM MSG ERROR CONTINUE Specifies a recoverable error that allows simulation to continue Use this error for data miscompares Yes No ERROR EBFM MSG ERROR FATAL Specifies an error that stops simulation because the error leaves the testbench in a state where further simulation is not possible N A Yes Cannot suppress Yes Cannot suppress FATAL EBFM MSG ERROR FATAL TB ERR Used for BFM test driver or Root Port BFM fatal errors Specifies an error that stops simulation because the error leaves the testbench in a state where further simulation is not possible Use this error message for errors that occur due to a problem in the BFM test driver module or the Root Port BFM that are not caused by the Endpoint Application Layer being tested N A Y Cannot suppress Y Cannot suppress FATAL Arria V Hard IP for PCI Express User Guide June 2012 Al
31. T T Tli 2 To connect the Avalon ST tx st source interface of the APPS component to the tx st sink interface of the DUT component repeat the technique explained in Step 1 For conduit interface types the APPS component interfaces connect to the DUT interfaces with matching names The Avalon Conduit interface type is a point to point interface type that accommodates individual signals or groups of signals that do not fit into any of the other Avalon types You can connect conduit interfaces to each other inside a Qsys system or export them to make connections to other modules in the design or to FPGA pins June 2012 Altera Corporation Arria V Hard IP for PCI Express User Guide 2 16 Chapter 2 Getting Started with the Arria V Hard IP for PCI Express Qsys Design Flow