ST L6611 DIGITALLY PROGRAMMABLE SECONDARY HOUSEKEEPING CONTROLLER handbook
Contents
1. 0 min 8 max SO20MEC ky 27 28 L6611 Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia Brazil Canada China Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States http www st com 28 28 572. 12V 12V UV OV monitor If connected to a voltage greater than 1 5V e g VREF 14 the function will be disabled Ground pin The connection integrity of this pin is constantly monitored and in case of either a bond wire or a PCB trace going open MFAULT 1 and DFAULT 9 will be forced high switching off the supply programming mode forcing PROG high 5V the chip enters programming mode PW_OK 12 and PS_ON 13 pins are disconnected from their normal functionality and they become inputs for DATA and CLOCK allowing the chip to be programmed The programming mode al lows selecting some options and adjusting some setpoints Power good signal for the Main converter When asserted high this pin indicates that the PW OK voltages monitored are above their UV limits There will be typically 250ms delay from the Main 12 outputs becoming good and PW OK being asserted This is nominally an open drain signal To The chip has 2 operating modes depending on PROG input pin biasing normal mode PROG should be floating or shorted to ground 3 4 28 L6611 PIN DESCRIPTION continued meme 8 3V3 UV OV monitor It uses a Separate reference to the feedback reference Input pin for 5V feedback 5V current sense and 5V UV OV monitor 5V UV OV uses a reference separate from that used for feedback This pin connects the 5V part of the Main error amplifier feedback divider Input pin for 12V feedback
3. Mfault OCP Bounce PW OK Data Logic and Programmable Trimming 5 Clock Debounce 75ms Programming input Vdd 2 50V B Dfault z 2 28 L6611 DESCRIPTION The L6611 is a control and housekeeping IC developed in BCD technology it is intended for acting at the sec ondary side of desktop PC s or server s switching power supplies in presence of standard voltage rails 3 3V 5V 12V generated by a main converter and of a supply line generated by an auxiliary converter The typical application circuit is showed on the front page The Housekeeping s main function is to control and monitor the voltages generated by both the main and the auxiliary converter it senses those voltages sends feedback signals to the primary controllers for regulation and upon detection of an undervoltage UV or overvoltage OV condition reports such fault and takes proper action to protect the system However the peculiar feature of this IC is its digital programming capability that enables an accurate trimming of the output voltage rails during production test via software without any use of external discrete trimming com ponents or need for manual intervention on the PSU It is also possible to program some of the monitoring func tions and select how UV and OC conditions are handled in the m
4. Positive input supply voltage Vdd is normally supplied from the Auxiliary power supply output voltage If Vdd UVL detects a sustained under voltage PW OK 12 will be pulled low and sending MFAULT 1 high will disable the main converter Analog of bulk voltage for AC fail warning The usual source of this analog pin is one of the secondary windings of the main transformer Hysteresis is provided through a trimmable 50uA current sink on this pin that is activated as the voltage at the pin falls below the internal reference 2 5V improve robustness this output has a limited current sink capability In programming mode this pin is used for data input then the absolute maximum rating will be Vdd 0 5V Control pin to enable the Main converter This pin has debouncing logic A recognized high value lt 9 this pin will cause PW OK 12 to go immediately low and after a delay of 2 5ms to shut Clock down the main PWM by allowing MFAULT 1 to go high During normal operation or if not used this pin has to be connected to a voltage lower than 0 8V In programming mode this pin will be used to clock serial data into the chip 2 5V reference for external applications This is a buffered pin Shorting this pin to ground or to VREF Vdd 10 will not affect integrity of control or monitor references An external capacitor max 100nF is required whenever the pin is loaded up to 5 mA otherwise it can be left floating
5. O Leon 0 0 57 16611 DIGITALLY PROGRAMMABLE SECONDARY HOUSEKEEPING CONTROLLER m OV UV DETECTION FOR 3 3V 5V 12V RAILS AND 5V OR 3 3V AUX VOLTAGE BCD TECHNOLOGY m AC MAINS UV BROWNOUT DETECTION WITH HYSTERESIS m ON LINE DIGITAL TRIMMING FOR 5V 12V 3 3V OR 3 3V AUX FEEDBACK REFERENCES AND AC MAINS UV m DIGITALLY SELECTABLE OPTIONS m ERROR AMPLIFIERS FOR 5V 12V RAILS MAIN SUPPLY 3V3 POST REGULATOR DIP20 5020 MAG_AMP OR LINEAR AND AUXILIARY SUPPLY ORDERING NUMBERS m MAIN SUPPLY ON OFF CONTROL AND L6611N L6611D POWER GOOD SIGNAL L6611DTR T amp Reel m 50mA CROWBAR DRIVE FOR AUXILIARY OUTPUT OVP m OPEN GROUND PROTECTION APPLICATIONS m 8ms DIGITAL SOFT START m SWITCHING POWER SUPPLIES FOR m 64 ms UV OC BLANKING AT START UP DESKTOP PC S SERVERS AND WEB SERVERS m SUPERVISOR FOR DISTRIBUTED POWER TYPICAL APPLICATION CIRCUIT zv 19 AUR sv WIDE RANGE MAIN CONTROL MAINS D WN lt 45Vaux 5V lt com zv lt G3 3V el AUXILIARY CONTROL April 2002 1 28 L6611 BLOCK DIAGRAM 3V3 5V UV 1 25V B 2 50V A Softs 45V 1
6. Vpmon Vpp PS ON low ue De KIZ pep Pese Gee 11 28 L6611 TYPICAL ELECTRICAL CHARACTERISTICS Figure 1 Supply start up UV and OV Voo V 5 over voltage 5 5 4 FAK s pear 48 JW phe CR Gk pu del wies batt a rts 1 sse UU ULlloClc lt IOeC u s _ 3 5 50 25 0 25 50 75 100 125 150 Figure 2 IC Supply current vs supply voltage IDD mA 10 7 lbo mA 4 Beat du P test Ef test cda cde an Rs 0 4 3 50 25 0 25 50 75 100 125 150 T C 12 28 Figure 4 Monitored inputs bias current 80 pA 70 147 7 075 s 5 7757 60 12Voutput gt 7 3 3Voutput 40 30 50 25 0 25 50 75 100 125 150 T C Figure 5 3 3V fault thresholds V 5 33v V overvoltage pam o mS Ze ei sS Teu de up SO undervoltage 2 50 25 0 25 50 75 100 125 150 T C Figure 6 5V fault thresholds Overvoltage 4 nar EI E ae tetas Tus Be Z xe ee bu cae ud undervo
7. 12V current sense and 12V UV OV monitor 12V UV OV uses a reference separate from that used for feedback This pin connects the 12V part of the Main error amplifier feedback divider Whenever one of the Main output voltages is detected going above its own OVP threshold this function set MFAULT 1 high latching the outputs off The latch is released after cycling PS ON 13 switch or by reducing Vdd 10 below the UV threshold Whenever one of the Main output voltages is detected going under its own UVP threshold this function sets MFAULT 1 high if latch mode has been selected this function will be latched Otherwise an attempt will be made to restart the device after 1 second delay If ACsns 11 is low due to a brownout condition UVP is disabled Undervoltage blanking When either converter is enabled the relevant UV OC monitoring circuits must not intervene to allow all outputs to come within tolerance 64 ms timing is provided for the auxiliary converter the timing starts as the IC has a valid supply for the main converter it starts as the ACsns pin detects a valid input voltage for the converter PW OK delay After power up when the all of the monitored voltages are above their own UV PW OK delay threshold the PW OK pin 12 will be kept low for additional 250ms typ to make sure all the outputs are settled Power off delay As soon as PS ON 13 pin is recognized high indicating an imminent turn off OFF delay condition
8. Reset Dmon_OV Debounce 6us gt Clock T Reset Dmon UV Debounce 500us Reset ii UVB 64ms Vdd OV Eu Vdd UVL Ss Restart Mode Delay 1s Reset Delay 2 5ms 5 Reset T Delay 250ms Reset T Debounce TMS 0814 ten 5 Main inputs overvoltage whenever one of main outputs 3 3V 12V is detected as going over voltage MFAULT is latched high which stops the Main PWM and PW OK goes low Cycling the PS ON switch or reducing Vdd below its undervoltage threshold releases the latch A delay of is imple mented before MFAULT latching The OV protection for the 12V and 5V outputs can be disabled see On board trimming and mode op erating section Main inputs undervoltage when an undervoltage on main outputs is detected MFAULT is latched high the Main PWM stops and PW OK goes low The latches are released by default cycling the PS ON switch or reducing Vdd below its undervoltage threshold latching mode optionally an attempt is made to restart the supply after of 1 second bounce mode The choice depends on the sele
9. 3V Vsv 5V V 12v 12V Vpmon Vpp PS ON low vases Dus we ue 40 7 t3 PS ON debounce PS ON input minimum pulse 50 75 100 ms width for a valid logic change tss Error Amp Soft Start period VFB quasi monothonic ramp from ms 0 to 2 5V Vstep Soft Start Step Ramp OV to 2 5V __ I VOLTAGE REFERENCE BUFFERED EXTERNAL PIN e sees e MAIN CONVERTER FEEDBACK ERROR AMPLIFIER 31 141 pee Divider impedance from Ainv to GND 5V and 12V 35 50 65 connected to GND eem e pon fe Te qmwememm 5 we m paa fm p emma y D 3 pe Deme or morea foarme MAGAMP OR LINEAR POST REGULATOR FEEDBACK ERROR AMPLIFIER B 1571 9 28 L6611 ELECTRICAL CHARACTERISTCS continued unless otherwise specified Ty 0 to 105 C Vpp 5V 3 3V Vsv 5V V 12v 12V VDmon Vpp PS ON low mes 1 C DH AUXILIARY CONVERTER FEEDBACK ERROR AMPLIFIER C Input Voltage Tamb 25 C 3 gt gt 3 o o ew sasa PROGRAMMING FUNCTIONS gt Clock Input High 3 10 28 L6611 ELECTRICAL CHARACTERISTCS continued unless otherwise specified Ty 0 to 105 C Vpp 5V Vsvs 3 3V Vsv 5V V 12v 12V
10. about 3 5V to improve response time Large signal slew rate is limited to reduce noise sensitivity 3 28 L6611 PIN DESCRIPTION continued 7 Output of the error amplifier for the main converter This pin typically drives an optocoupler and is also used for compensation along with Ainv pin 5 Main loop error amplifier inverting input The non inverting input is connected to an internal 2 5V 5 Ainv reference that can be digitally trimmed A high impedance internal divider from 12V and 5V UV OV sense pins 19 20 eliminates the need for external divider in most applications The pin is used for error amplifier compensation Auxiliary loop optocoupler drive Also node for error amp compensation Large signal slew rate is Cout limited to reduce sensitivity to switching noise Inverting input for Auxiliary error amplifier The non inverting input is connected to an internal 1 25V reference that can be digitally trimmed Dual or Auxiliary UV OV monitor Dmon is programmable to monitor 3V3 or 5V To allow a correct power up the UV function on this pin is blanked out during initial start up There is no delay for the OV function Dual or Auxiliary fault protection When Dmon 8 recognizes an over voltage DFAULT and DFAULT MFAULT 1 go high DFAULT is capable of sourcing up to 50mA Possible applications are a crowbar across the Auxiliary output or an opto coupled fault signal to the primary side 3 lt
11. and reference voltage 3 3V section error amplifier B Auxiliary section error amplifier C Normal operation timing diagram n nnne 20 Undervoltage overvoltage and relevant timings esee 21 AC sense mains undervoltage warning 2 L aa 22 Application example u y a8 ahd dte te e ee edle od Ri n de dee tee enun 23 Applicatior Ideas iet pei ge eei rtm Fed cun ert pe i t nct eed 25 15 28 L6611 APPLICATION INFORMATION 1 ONBOARD DIGITAL TRIMMING AND MODE SELECTION By forcing the PROG input pin high the chip enters programming mode the multifunction pins PW_OK and PS_ON are then disconnected from their normal functions output pins and are connected to internal logic as DATA and CLOCK inputs respectively allowing chip programming even when the device is assembled on the application board Onboard chip programming allows selecting some working options reference voltage setpoints adjusting It is also possible to verify the expected results before programming the chip definitively in first instance data can be loaded into a re writeble volatile memory a flip flop array where they are kept as long as the chip is supplied and can be changed as many times as one desires A further operation is necessary to confirm the loaded data and permanently store them into a PROM a poly fuse array inside the IC Several steps compose the t
12. OK Vdd ACsns 5Vaux IN3W395VNVIN H3MOd 9 4015 24 28 L6611 7 APPLICATION IDEAS In fig 23 a circuit is suggested to obtain the regulated 3 3V output with a linear configuration instead of the Magamp circuitry In this case the output of the E A modulates the gate source voltage of a power MOS in series with the power stage In fig 24 a simple and cheap latch circuit is showed to manage an OV fault on the Auxiliary output in the same way of an OC UV fault without having recourse to a expensive power crowbar By tuning the value of RsET it is possible to set the voltage value that triggers the latch circuit defines the turn on delay A diode con nected between the collector of Q1 and Cout pulls down the output of the auxiliary E A this has the same effect of the OCP bounce internal signal that guarantees the reduction of duty cycle Figure 23 Controlling a Linear Regulator with the Error Amplifier B 25 28 L6611 OUTLINE AND MIN TYP MAX MIN TYP MECHANICAL DATA S A L6611 OUTLINE AND MECHANICAL DATA Doer ar
13. OV function Enabled Enable Disable 5V UV OV function Enabled Do 5V 3V3 Dmon selection 5V selection Di don t care 3 16 28 L6611 Table 2 Trim Coding E A A threshold E A B threshold E A C threshold ACsns threshold ACsns Parameter Hysteresys 50 typ 0001 0010 0011 0010 0101 Tuning Bits D3 D2 D1 DO D2 D1 DO Ds 02 Di Do AV mV Al uA 1 25V typ 1 25V typ Table 3 Mode coding Parameter Bounce or Latch Enable Disable Enable Disable 5V 3 3V Dmon Mode 12V UV OV 5V UV OV Selection A3 A2 A1 Bit Value Tuning Bit _ 5 et 0 Latch Enabled Enabled 5V 1 Bounce Disabled Disabled 3 3V Figure 14 Trimming programming procedure timing diagram PROG PS_ON Clock PW OK Data 17 28 L6611 2 ERROR AMPLIFIERS AND REFERENCE VOLTAGES Three error amplifiers are implemented on the IC to achieve regulation of the output voltages a brief description follows for each section Main section error amplifier A and Soft Start The circuit is designed to directly control the Main primary PWM through an optocoupler providing very good regulation and galvanic isolation from the primary side Typical solutions require a shunt regulator like the TL431 as a reference and feedback amplifier to sense the output voltage and gen erate a corresponding error voltage this voltage is then converted in a cu
14. PW OK 12 pin will go low immediately The converter will be turned off after a delay of 2 5ms D bo nce The PS ON signal input has debounce logic to prevent improper activation All of the monitored inputs have digital filtering debounce logic on board for high noise immunity AC sense hysteresis Programmable hysteresis is provided on the ACsns input 11 to avoid AC hysteresis undesired shutdown caused by noise as the voltage at the pin is near the threshold or by the voltage ripple across the bulk capacitor Vdd is monitored for overvoltage If an overvoltage is detected MFAULT 1 and DFAULT 9 Vdd OVP are latched high To prevent false signals of any of IC s output pins an under voltage lock out circuit monitors Vdd Vdd UVL and keeps all IC s output at their default OFF level until Vdd reaches a sufficient minimum voltage for ensuring integrity When Vdd goes below the UV threshold all latches are reset and volatile programming memory cleared Dual OVP Dmon is monitored to detect an overvoltage condition in this case MFAULT 1 and DEAD uh are latched high Dual UVP Dmon 8 is monitored to detect an undervoltage condition in this case MFAULT 1 is latched high and Cout 6 is pulled low 5 28 L6611 FUNCTION DESCRIPTION continued 7 ae The IC provides an on board 8ms soft start a quasi monotonic ramp from OV to 2 5V for the A error amplifier reference voltage in order to avo
15. ain converter whether latched mode the information is latched and released only by forcing the restart of the IC or bouncing mode an attempt is made to automatically restart the converter after 1 second wait A key feature of this IC is its contribution to a very low external component count Besides the extensive use of onboard programmable switches which prevents the need for external trimming components the IC embeds reference voltages error amplifiers and most of the housekeeping circuitry normally required PIN CONNECTION top view MFAULT Binv Bout Aout Ainv Cout Cinv Dmon DFAULT Vdd PIN DESCRIPTION Main converter on off control This pin is a 10mA current sink used for driving an opto isolator It is normally low when PS ON 13 is pulled low If a fault is detected or PS ON goes high this pin goes high too To allow power up the functions are digitally blanked out for a period UVB function and MFAULT 1 stays low There is no delay for the OV protection function MFAULT Inverting input to the error amplifier for the 3V3 post regulator either mag amp or linear The non inverting input is connected to an internal 1 25V reference that can be digitally trimmed Output of the 3V3 error amplifier It typically drives either a PNP transistor that sets the mag amp core or the pass element of a linear regulator Also node for error amplifier compensation The maximum positive level of this output is clamped at
16. change the weight of the two contributions or even eliminate one of them by connecting external resistors of much lower value RL and or in fig 15 that bypass the internal ones appropriately For example using 2 4 1 3 9 and 24 then the ratio between 5V and 12V output weight will be equal to 6 4 By simply making Rui RL for example 2 4K with no only the output is kept under feed back because the contribution of 12V branch through the internal 600K resistor will be negligible The pin 24 12V has to be connected to 12V output to guarantee the OV UV monitoring Figure 15 Main feedback section 12V output to MAIN control 5V output optional to change feedback weight H2 3 3V section error amplifier B It is the error amplifier used to set the magamp core through an external circuitry see a typical sche matic in figure 16 The non inverting input of the error amplifier is connected to a trimmable 1 25V internal voltage ref erence see On board trimming and mode operating paragraph The E A inverting input is exter nally available Binv pin 2 and is connected to the output divider Ry and Ru the output pin Bout 18 28 1571 L6611 pin 3 drives the external circuitry that biases the magamp core Between these pins it
17. cted mode see On board trimming and mode operating section Debounce logic is implemented for 3 3V and 5V so that an undervoltage condition on these signals has to last 450 to be recognized as valid while debounce logic is implemented for 12V and 12V input signal When all main undervoltages are over and ACsns is OK see the relevant section PW OK goes high after a delay of 250ms Dmon input overvoltage whenever the Dmon input pin is detected as going overvoltage both MFAULT and DFAULT are latched high The latch is released by reducing Vdd below its undervoltage threshold Debounce logic is implemented so that MFAULT and DFAULT signals are latched only if the overvoltage condition lasts more than 6us To protect the load against overvoltage typical solutions make use of a power crowbar SCR driven by 174 21 28 L6611 DFAULT the Application ideas section another simple circuit is showed to guarantee the same pro tection without the SCR Dmon input undervoltage when an undervoltage on Dmon is detected MFAULT is put high Cout is pulled low an internal OCP_BOUNCE signal is generated see fig 19 and PW_OK falls down This function is enabled 64ms after the UVLO signal falls down Debounce logic is implemented so that MFAULT and OCP_BOUNCE signals are generated only if the undervoltage condition lasts more than 500us The Dmon UV and OV protections can be set to work with thresholds set for 5V or 3 3V outp
18. esents 4 standard outputs 3 3V 5V 12V At the secondary side the housekeeping circuitry governed by the L661 1 checks the outputs and sends control signals to the primary side through three optocouplers It also generates power good information to the system while managing all timings during power up and power down sequences In fig 22 a detailed circuit for the sec ondary side is presented it is possible to note the very low number of external components required Simply connecting the power supply outputs to the L6611 relevant pins ensures the protection against over un dervoltage in the Main section A crowbar on the auxiliary output is switched on through DFAULT in case of overvoltage The L6611 is supplied by the Auxiliary output the signals sent to the primary side are digital ON OFF signal through an optocoupler that drives the relevant pin of primary Main controller to switch the Main converter ON and OFF two analog signals that provide voltage feedback for both the Auxiliary and the Main section driving the primary controller pins responsible for the duty cycle modulation ki 23 28 L6611 Figure 22 Detailed Secondary Side DFAULT pw
19. id high current peaks in the primary circuit and output voltage overshoots at start up In fact if this reference gets the nominal value as soon as the power up occurs the A E A will go out of regulation and tend to sink much more current thus forcing PWM to work with the maximum duty cycle Bounce or This option allows setting either latched mode or auto restart after 1 second delay in case of Latch mode undervoltage faults ABSOLUTE MAXIMUM RATINGS Supply voltage 00000 voltage 0 5 to 7 pg EON on PS ON Clock DFAULT VREF and error 0 5 to Vdd 0 5 amplifier pins Voltage on MFAULT PW OK Dmon and positive UV OV OC AC 0 5 to 16 sense pins Voltage on and 12V UV OV sense pin on and 12V UV OV sense pin LS news wee Lead Temperature soldering 10 seconds THERMAL DATA Max Thermal Resistance junction to ambient mounted on board 3 6 28 L6611 ELECTRICAL CHARACTERISTCS unless otherwise specified Ty 0 to 105 C 5V Vaya 3 3V Vsv 5V V 12v 12V Vpmon Vpp PS ON low 5 3 SUPPLY SECTION 0 FAULT THRESHOLDS Vout 3 3V mee Vout 12V 0 pepe Vout 12V V uA esse Cd 15 Vout 3 3V Aux Dual Dmon option _______ ________ v Vout 5V Aux Dual Dmon option eee ACsense Hys
20. is connected the compensation network Zc The maximum positive output voltage is clamped at about 3 5V to improve response time The feedback control circuit determines the magamp off time converting the voltage at the output of error amplifier into a current IR which resets the magamp If the output voltage exceeds its preset value V Bout decreases this causes a higher voltage across Rc which in turn implies a larger volt age across Re and larger reset current Ig Vee of Qi is supposed constant A larger IR causes the PWM waveform across D2 to get narrower This pulls the output voltage back to the desired level and achieves regulation Itis possible to use this section to drive a pass transistor to obtain 3 3V with a linear regulator in the Application idea section an example is showed to implement this solution Figure 16 Magamp control feedback section magamp Auxiliary section error amplifier C This section fig 17 provides the feedback signal for the auxiliary converter following the same oper ating principles as the Main section The auxiliary output voltage Vaux is often defined as Standby voltage because the converter remains alive during standby condition the Main converter is stopped to supply the chip and all the ancillary circuits Typical values for its output voltage are 5V or 3 3V The inverting in
21. ltage 3 50 25 0 2 50 75 100 125 150 C 4 TYPICAL ELECTRICAL CHARACTERISTICS continued Figure 7 12V fault thresholds 15 V overvoltage 50 25 0 2 50 75 C 100 125 150 Figure 8 3 3V 5V Dmon fault thresholds V 3 3V undervoltage 50 25 0 25 50 75 100 125 150 T C Figure 9 12V bias current 20 30 40 50 100 125 150 16611 Figure 10 12V fault thresholds 12 15 18 overvoltage undervoltage O 50 25 0 25 50 75 100 125 150 Figure 11 ACsense and external voltage references 2 7 ap 2 5 aa 2 3 V 50 25 0 25 50 75 100 125 150 C Figure 12 Error amplifier A B and C reference 0 5 voltage V 50 25 0 25 50 75 C 100 125 150 13 28 L6611 TYPICAL ELECTRICAL CHARACTERISTICS continued Figure 13 Error amplifiers A B C Gain and Phase 1e 00 1e 01 1e 02 1e 03 1e 04 14 28 1e 05 1e 06 1e 07 7e 07 L6611 APPLICATION INFORMATION INDEX On board digital trimming and mode selection a Page 16 Error amplifiers and reference volage 18 Main section error amplifier A and Soft Start E A
22. put Cinv pin 7 is connected to the output voltage through an external resistor divider whereas the non inverting one is connected to a 1 25V trimmable internal voltage reference see On board trimming and mode operating paragraph The compensation network Zc aux is placed between E A inverting input and output pins When Dmon recognizes an undervoltage condition on the auxiliary output an internal n channel MOS in open drain configuration grounds E A output pin the high current flowing through the optocoupler is then transferred to the primary side causing a duty cycle as short as possible this prevents a high energy transfer from primary to secondary under short circuit conditions thus reducing the thermal stress on the power components Figure 17 Auxiliary feedback section to AUX control 1 25V OCP bounce GND L6611 19 28 L6611 3 NORMAL OPERATION TIMING DIAGRAM FIG 18 The time intervals t1 t5 are listed below t1 UV OC blanking of MFAULT While Main outputs are ramping up the UV comparators are blanked for this interval to prevent a false turn off No such blanking is applied to OV faults t2 PW OK delay This period starts when all monitored outputs and AC sense are above their respec tive UV levels and finishes at PW OK going high t3 PS ON debounce period The voltage on PS ON must be continuou
23. rimming programming process 1 PROG pin is forced high 2 clock signal is sent to the PS ON clock 3 a byte with the following structure Address is serially sent to the PW OK DATA pin and loaded into the IC s volatile memory bit by bit on the falling edges of the clock signal see Fig 14 Address is the identification code of the parameter that has to be trimmed and Data contains the tuning bits 4 PROG pin is forced low warning Vdd must never fall below during this process otherwise the con tents of the volatile memory will be lost and the result of the previous step is checked 5 after any iterations of the steps 1 4 that might be necessary to achieve the desired value force PROG pin high and send the following burn code MSB LSB to permanently store the data in the PROM memory Table 1 shows the list of the 6 programmable classes of functions each one identified by a different code 0 and the corresponding trimmable parameter s in table 2 it is possible to find the trim coding for the E A reference setpoints and in table 3 all the selections mode option coding are showed The timing diagram of fig 14 shows the details of data acquisition Table 1 Programmable functions 0001 Error amplifier A threshold art eroranpifer estas tas Ds Dv o ww AC sense esas S D3 AC sense hysteresis 0101 Enable Disable 12V UV
24. rrent transferred to the pri mary side through the optocoupler The feedback E A amplifier is integrated in the IC its non inverting input is connected to an internally gen erated voltage reference whose default value is typically 2 5V It can however be trimmed to obtain a better precision see On board trimming and mode operating section Then no TL431 is needed The E A inverting input Ainv pin 5 and the E A output Aout pin 4 are externally available and the frequency compensation network Zc will be connected between them see fig 15 The high impedance in the hundred kQ internal divider from 12V and 5V UV OV sense pins elimi nates the need for an external one in most applications allowing a further reduction in the number of external component Under closed loop condition the two upper branches connected to 12V and 5V pins supply equally the current flowing through R3 80 6K equal to 2 5V R3 In order to avoid high current peaks in the primary circuit and output voltage overshoots at start up the IC provides an on board 8ms soft start a quasi monotonic ramp from OV to 2 5V for the A error amplifier reference voltage In fact if this reference gets the nominal value as soon as the power up occurs the A E A will go out of regulation and tend to sink much more current thus forcing PWM to work with the maximum duty cycle E A and references voltage Being the inverting input of E A externally available it is possible to
25. sis instead of a more usual voltage hysteresis an internal 50 current generator is ON if the voltage is below 2 5V and is turned off when the voltage applied at the non invert ing input exceeds 2 5V This approach provides an additional degree of freedom it is possible to set the ON threshold and the OFF 22 28 L6611 threshold separately by properly choosing the resistors of the external divider The following relationships can be established for the ON and OFF VB orr thresholds of the input voltage VB 2 5 R ON _ 2 5 2 Ro VB OFF R R 25 which solved for R1 and R2 yields yN Broni VB orr 2 5 Ro 1 VB OFF 2 5 Both the ACsns threshold and the hysteresis current be trimmed see On board trimming and mode ating section Figure 21 ACsns circuit and timing diagram VB off AC_GOOD A 50uA R 5 50 GND 6 APPLICATION EXAMPLE In applications like desktop PC s server or web server the system usually consists of two converters Main and Auxiliary that can be supplied directly from either the AC Mains or a PFC stage The control and supervision at the secondary side is usually entrusted to a housekeeping circuit The Auxiliary section supplies a stand by voltage 5V typ through a flyback converter The Main section in forward configuration pr
26. sly present in a high or low state for a minimum period for that state to be recognized t4 Tdelay The time from PS ON being recognized as going high to MFAULT going high This is to provide a power down warning When PS ON requests power off PW OK goes low immediately 15 UV blanking of DFAULT During initial power up a period of UV blanking is applied to DFAULT as soon as Vdd to the chip is in the correct range No such blanking is applied to OV faults Figure 18 Normal Operation Timing Diagram ON OFF with PS ON or the AC power switch AC Vdd _ 70 Vadon I Vdd ok 8 15 gt UVBdfault I ACsns ACsns_low Off PS ON Mfault ah tl Main OPs POK UVBmfault 3 20 28 L6611 4 UNDERVOLTAGE OVERVOLTAGE DETECTION AND RELEVANT TIMINGS The IC provides on board undervoltage and overvoltage protection for 3V3 5V 12V Main input pins and Dmon auxiliary input pin Overcurrent protection is available for 12V and 5V or 3 3V digitally selectable The internal fault logic is illustrated in figure 19 Figure 19 Simplified Fault logic Main_OV Debounce Gus Clock 12V_Main_UV Debounce vd at 2 Mfault 3V3 5V_Main_UV Debounce 500us 1 Rexel T UVB 64ms ACsense
27. teresis 57 7 28 L6611 ELECTRICAL CHARACTERISTCS continued unless otherwise specified Ty 0 to 105 C Vpp 5V Vsvs 3 3V Vsv 5V V 12v 12V VDmon Vpp PS ON low we we a fe fe x me FAULT OUTPUTS Dee womeme TT D eoo etm fe Wa mmm ax irons 8 pw D m MFAULT OV debounce Minimum OV pulse before 4 us MFAULT is latched MFAULT debounce Minimum UV pulse before 4 us 12V UV MFAULT is latched MFAULT debounce Minimum UV pulse before 250 450 650 us 5V 3V3 UV MFAULT is latched DFion DFAULT output high source Overvoltage condition 25 50 95 current VprAULT 1 5V Dryou DFAULT output high voltage IDFAULT OMA Tamb 25 C 2 1 2 4 2 7 V Overvoltage condition DFAULT output low voltage IDFAULT 1mA no faults DFAULT OV debounce Minimum OV pulse before 4 us DFAULT is latched DFAULT UV debounce Minimum UV pulse before 250 450 650 us DFAULT is latched START UP SHUTDOWN FUNCTIONS ite DFAULT UV blanking delay Delay from Vpp on to DFAULT 44 64 84 ms UV active 11 MFAULT UV blanking delay Delay from ACsws high to Main 44 64 84 ms UV active PW OK blanking delay Main s UV good to PW OK high 4 PS ON delay time Delay from PS ON input to 1 75 2 5 3 25 tDELAY MFAULT 8 28 3 L6611 ELECTRICAL CHARACTERISTCS continued unless otherwise specified Ty 0 to 105 C Vpp 5V 3
28. ut voltage the choice depends on the IC programming Figure 20 Fault timing diagram Output EE au POK Main output s undervoltage 1 1 1 1 1 1 1 1 1 1 1 1 1 M 1 Mfault Mfault 1 1 Auxiliary output s overvoltage Auxiliary output s undervoltage 1 1 1 1 1 1 1 1 1 1 1 1 1 1 l Dfault current Cout 1 l 1 1 1 is connected to the Auxiliary output Rail 5 AC SENSE MAINS UNDERVOLTAGE WARNING The device monitors the primary bulk voltage and warns the system when the power is about to be lost pulling down the PW_OK output The ACsns pin is typically connected to one of the windings of the main transformer see fig 21 Through a single diode rectification filter a voltage equal to VB VBULK N where Vgurkis the voltage across the bulk ca pacitor on primary side and N is the transformer turn ratio is present at point B A resistor Rr could be useful to clamp voltage spikes present The fault signal is generated by means of AC GOOD the output of an internal comparator this comparator is internally referred to a trimmable 2 5V reference and indicates an AC fault if the voltage applied at its externally available non inverting input is below the internal reference as shown in fig 21 This comparator is provided with current hystere
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