UNITRODE UC1823A B/1825A B UC2823A B/2825A B UC3823A B/3825A B handbook
Contents
1. UDG 95113 GND D2 1N5820 UDG 95114 APPLICATIONS INFORMATION cont GROUND PLANES Each output driver of these devices is capable of 2A peak currents Careful layout is essential for correct op eration of the chip A ground plane must be employed A unique section of the ground plane must be desig nated for high di dt currents associated with the output stages This point is the power ground to which the PGND pin is connected Power ground can be sepa rated from the rest of the ground plane and connected at a single point although this is not strictly necessary if the high di dt paths are well understood and ac counted for VCC should be bypassed directly to power ground with a good high frequency capacitor The UC1823A B 1825A B UC2823A B 2825A B UC3823A B 3825A B sources of the power MOSFET should connect to power ground as should the return connection for input power to the system and the bulk input capacitor The output should be clamped with a high current Schottky diode to both VCC and PGND Nothing else should be connected to power ground VREF should be bypassed directly to the signal portion of the ground plane with a good high frequency capaci tor Low ESR ESL ceramic 1uF capacitors are recom mended for both VCC and VREF All analog circuitry should likewise be bypassed to the signal ground plane lt TO ANALOG CIRCUITRY2. All currents are positive into negative out of the specified ter minal Consult Packaging Section of Databook for thermal limi tations and considerations of packages PLCC 20 LCC 20 Top View Q L Packages N C INV NI 3 2 1 2019 EAOUT me CLK LEB N C RT CTH 14 9 10 11 12 13 RAMP GND Ss ILIM N C ELECTRICAL CHARACTERISTICS Unless otherwise stated these specifications apply for Ta 55 C to 125 C for the UC1823A B and UC1825A B 40 C to 85 C for the UC2823A B and UC2825A B 0 C to 70 C for the UC3823A B and UC3825A B RT 3 65k CT 1nF VCC 12V Ta Ty PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Reference Section Output Voltage Ty 25 C lo 1mA 5 05 5 1 5 15 V Line Regulation 12 lt VCC lt 20V 2 15 mV Load Regulation 1mA lt lo lt 10mA 5 20 mV Total Output Variation Line Load Temp 5 03 5 17 V Temperature Stability Tmn lt Ta lt Tmax Note 1 0 2 0 4 mV C Output Noise Voltage 10Hz lt f lt 10kHz Note 1 50 uVRMS Long Term Stability Ty 125 C 1000 hours Note 1 5 25 mV Short Circuit Current VREF OV 30 60 90 mA UC1823A B 1825A B UC2823A B 2825A B UC3823A B 3825A B ELECTRICAL CHARACTERISTICS Unless otherwise stated these specifications apply for Ta 55 C to 125 C for the UC1823A B and UC1825A B 40 C
3. a 7 V 7 V V SIGNAL GROUND Open Loop Test Circuit This test fixture is useful for exercising many of the UC3823A B UC3825A B functions and measuring their specifications As with any wideband circuit careful POWER GROUND UDG 95115 grounding and bypass procedures should be followed The use of a ground plane is highly recommended CLK LEB RT CT Les RT 3 65k CT 1 0nF Le I UC3823A B UC3825A B OSCILLATOR vec 1N5820 4 UNITRODE CORPORATION 7 CONTINENTAL BLVD MERRIMACK NH 03054 TEL 603 424 2410 FAX 603 424 3460 UDG 95116 IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its semiconductor products to the specifications applicable at the time of
4. B out puts operate together at the switching frequency and can vary from 0 to some value less than 100 The UC3825A B outputs are alternately controlled During every other cycle one output will be off Each output then switches at one half the oscillator frequency vary ing in duty cycle from 0 to less than 50 To limit maximum duty cycle the internal clock pulse blanks both outputs low during the discharge time of the oscillator On the falling edge of the clock the ap propriate output s is driven high The end of the pulse is controlled by the PWM comparator current limit com parator or the overcurrent comparator Normally the PWM comparator will sense a ramp crossing a control voltage error amp output and termi nate the pulse Leading edge blanking LEB causes the PWM comparator to be ignored for a fixed amount of time after the start of the pulse This allows noise in herent with switched mode power conversion to be re jected The PWM ramp input may not require any filtering as result of leading edge blanking To program a Leading Edge Blanking period connect a capacitor C to CLK LEB The discharge time set by C and the internal 10k resistor will determine the blanked interval The 10k resistor has a 10 tolerance For more accuracy an external 2k 1 resistor R can be added resulting in an equivalent resistance of 1 66k with a tolerance of 2 4 The design equation is UC1823A B 1825A B UC2823A B 2825A B UC
5. soft start Should the fault latch be set during soft start the outputs will be immediately terminated but the soft start cap will not be discharged until it has been fully charged This re ACTIVE LOW OUTPUTS DURING UVLO The UVLO function forces the outputs to be low and con siders both VCC and VREF before allowing the chip to operate Simplified Schematic 0 4 0 6 1 0 CURRENT A UDG 95108 PWM APPLICATIONS Current Mode SWITCH L 4 gt OSCILLATOR CT 1 25V ii RAMP FROM E A UDG 95109 UC1823A B 1825A B UC2823A B 2825A B UC3823A B 3825A B Soft Start and Fault Waveforms sults in a controlled hiccup interval for continuous fault conditions Output V and I During UVLO UDG 95107 Voltage Mode OSCILLATOR FROM E A UDG 95110 APPLICATIONS INFORMATION cont SYNCHRONIZATION The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor Program the free running frequency of the oscillator to be 10 to 15 slower than the desired synchronous frequency The pulse width should be greater than 10ns and less than half the discharge time of the oscillator The rising edge of the CLK LEB pin can be used to gener
6. 3823A B 3825A B Maximum Duty Cycle vs Ry Curve TT 7 100 UDG 95104 LEB Operational Waveforms CLK LEB RAMP INPUT BLANKED RAMP TO PWM UDG 95105 tLeB 0 5 R 10k C Values of R less than 2k should not be used Leading edge blanking is also applied to the current limit comparator After LEB if the ILIM pin exceeds the one volt threshold the pulse is terminated The over current comparator however is not blanked It will catch catastrophic over current faults without a blanking delay Any time the ILIM pin exceeds 1 2V the fault latch will be set and the outputs driven low For this rea son some noise filtering may be required on the ILIM pin APPLICATIONS INFORMATION cont UVLO SOFT START AND FAULT MANAGEMENT Soft start is programmed by a capacitor on the SS pin At power up SS is discharged When SS is low the error amp output is also forced low As the internal 9uA source charges the SS pin the error amp output follows until closed loop regulation takes over Anytime ILIM exceeds 1 2V the fault latch will be set and the output pins will be driven low The soft start cap is then discharged by a 250uA current sink No more output pulses are allowed until soft start is fully discharged and ILIM is below 1 2V At this point the fault latch will be re set and the chip will execute a
7. O O UC2823A0 0 D Unitrode Products from Texas Instruments application p UC1823A B 1825A B f INEO UC2823A B 2825A B available UC3823A B 3825A B High Speed PWM Controller FEATURES Improved versions of the UC3823 UC3825 PWMs Compatible with Voltage or Current Mode Topologies Practical Operation at Switching Frequencies to 1MHz 50ns Propagation Delay to Output e High Current Dual Totem Pole Outputs 2A Peak e Trimmed Oscillator Discharge Current e Low 100uA Startup Current e Pulse by Pulse Current Limiting Comparator Latched Overcurrent Comparator With Full Cycle Restart BLOCK DIAGRAM Pri COWMPARATOA CUAGERT LIMIT Ley OVER CURAENT iang si DESCRIPTION The UC3823A amp B and the UC3825A amp B family of PWM control ICs are improved versions of the standard UC3823 amp UC3825 family Performance enhancements have been made to several of the circuit blocks Error ampli fier gain bandwidth product is 12MHz while input offset voltage is 2mV Cur rent limit threshold is guaranteed to a tolerance of 5 Oscillator discharge current is specified at 10mA for accurate dead time control Frequency ac curacy is improved to 6 Startup supply current typically 100A is ideal for off line applications The output drivers are redesigned to actively sink current during UVLO at no expense to the startup current specification In addition each output is
8. ate a synchroniz ing pulse for other chips Note that the CLK LEB pin will no longer accept an incoming synchronizing signal General Oscillator Synchronization l 5 VsYNG eee Q gi 500 External Clock UDG 95111 HIGH CURRENT OUTPUTS Each totem pole output of the UC3823A B and UC3825A B can deliver a 2 amp peak current into a ca pacitive load The output can slew a 1000pF capacitor 15 volts in approximately 20 nanoseconds Separate collec tor supply VC and power ground PGND pins help de couple the IC s analog circuitry from the high power gate drive noise The use of 3 Amp Schottky diodes 1N5120 USD245 or equivalent as shown in the figure from each output to both VC and PGND are recommended The di odes clamp the output swing to the supply rails neces sary with any type of inductive capacitive load typical of a MOSFET gate Schottky diodes must be used because a low forward voltage drop is required DO NOT USE stan dard silicon diodes Although a single ended device two output drivers are available on the UC3823A B devices These can be par alleled by the use of a one half ohm noninductive resis tor connected in series with each output for a combined peak current of 4 amps UC1823A B 1825A B UC2823A B 2825A B UC3823A B 3825A B Operational Waveforms UDG 95112 Two Units MASTER
9. capable of 2A peak currents during transitions Functional improvements have also been implemented in this family The UC3825 shutdown comparator is now a high speed overcurrent comparator with a threshold of 1 2V The overcurrent comparator sets a latch that en sures full discharge of the soft start capacitor before allowing a restart While the fault latch is set the outputs are in the low state In the event of continuous faults the soft start capacitor is fully charged before discharge to insure that the fault frequency does not exceed the designed soft start period The UC3825 Clock pin has become CLK LEB This pin combines the functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing continued RE T ST APT COMPLETE peor anT DELAY LATCH mea Note 1823A B Version Toggles Q and Qare always low UDG 95101 SLUS334A AUGUST 1995 REVISED NOVEMBER 2000 DESCRIPTION cont UC1823A B 1825A B UC2823A B 2825A B UC3823A B 3825A B ABSOLUTE MAXIMUM RATINGS The UC3825A B has dual alternating outputs and the Supply Voltage VC VCC 0 0c eee 22V same pin configuration of the UC3825 The UC3823A B Output Current Source or Sink Pins OUTA OUTB outputs operate in phase with duty cycles from zero to DC D aa a aA LA AA je Skis ae is Ode Madan ls aaa a a ese 0 5A less than 100 The pin configuration of the UC3823A B Pulse 0 5us ey 2 2A Power G
10. e Blanking R 2k C 470pF 300 375 450 ns LEB Resistor VCLK LEB 3V 8 5 10 11 5 kohm EAOUT Zero D C Threshold Vramp OV 1 1 1 25 1 4 V Delay to Output Veaout 2 1V Vramp 0 to 2V Step Note 1 50 80 ns Current Limit Start Sequence Fault Section Soft Start Charge Current Vss 2 5V 8 14 20 HA Full Soft Start Threshold 4 3 5 V Restart Discharge Current Vss 2 5V 100 250 350 uA Restart Threshold 0 3 0 5 V ILIM Bias Current 0 lt Vium lt 2V 15 uA Current Limit Threshold 0 95 1 1 05 V UC1823A B 1825A B UC2823A B 2825A B UC3823A B 3825A B ELECTRICAL CHARACTERISTICS Unless otherwise stated these specifications apply for Ta 55 C to 125 C for the UC1823A B and UC1825A B 40 C to 85 C for the UC2823A B and UC2825A B 0 C to 70 C for the UC3823A B and UC3825A B RT 3 65k CT 1nF VCC 12V Ta Ty PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Current Limit Start Sequence Fault Section cont Over Current Threshold 1 14 1 2 1 26 V ILIM Delay to Output Vium 0 to 2V Step Note 1 50 80 ns Output Section Output Low Saturation lout 20MA 0 25 0 4 V lout 200mA 1 2 2 2 V Output High Saturation lout 20mMA 1 9 2 9 V lout 200mA 2 3 V UVLO Output Low Saturation lo 20mMA 0 8 1 2 V Rise Fall Time C_ 1nF Note 1 20 45 ns UnderVoltage Lockout Start Threshold UCX823B and X825B only 16 17 V Stop Threshold UCX823B a
11. nd X825B only 9 10 V UVLO Hysteresis UCX823B and X825B only 5 6 7 V Start Threshold UCX823A and X825A only 8 4 9 2 9 6 V UVLO Hysteresis UCX823A and X825A only 0 4 0 8 1 2 V Supply Current Startup Current VC VCC VrH start 0 5V 100 300 uA lcc 28 36 mA Note 1 Guaranteed by design Not 100 tested in production APPLICATIONS INFORMATION OSCILLATOR Oscillator The UC3823A B 3825A B oscillator is a saw tooth The rising edge is governed by a current controlled by the RT pin and value of capacitance at the CT pin The falling edge of the sawtooth sets dead time for the outputs Se lection of RT should be done first based on desired maximum duty cycle CT can then be chosen based on desired frequency RT and Dmax The design equations are 3V RT d0mA 1 Dmax 16 Dmax CI RTP Recommended values for RT range from 1k to 100k Control of Dmax less than 70 is not recommended UDG 95102 APPLICATIONS INFORMATION cont OSCILLATOR conit Oscillator Frequency vs Ry and Cy Curve 10000 s c 47 Ope Corp C 2 5 E S54 Ine C tonp Cx2an FREQUENCY kHz DG 95103 LEADING EDGE BLANKING The UC3823A B 3825A B performs fixed frequency pulse width modulation control The UC3823A
12. round PGND 00 00 e eee eee 0 2V is the same as the UC3823 except pin 11 is now an out Analog Inputs put pin instead of the reference pin to the current limit INV NI RAMP 0 00c0er eee eeeee 0 3V to 7V comparator A version parts have UVLO thresholds EIME SSe ranae G4 loaves odie el Ao 0 3V to 6V identical to the original UC3823 25 The B versions Clock Output Current CLK LEB 5mA have UVLO thresholds of 16 and 10V intended for ease Error Amplifier Output Current EAOUT SmA of use in off line applications Soft Start Sink Current SS 0 2 2 00 00 e eee eee 20mA Oscillator Charging Current RT 2 000 00 5mA Consult Application Note U 128 for detailed technical Power Dissipation at Ta 60 C 000000 1W and applications information Contact the factory for fur Storage Temperature Range 65 C to 150 C ther packaging and availability information Junction Temperature sissien 55 C to 150 C Lead Temperature Soldering 10 sec 300 C UVLO 9 2V 8 4V 16V 10V 9 2V 8 4V 16V 10V Dmax lt 100 lt 100 lt 50 lt 50 Device UC3823A UC3823B UC3825A UC3825B CONNECTION DIAGRAMS DIL 16 SOIC 16 Top View J or N Package DW Package YL NI EAOUT CLK LEB RT CT
13. sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using TI components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 2000 Texas Instruments Incorporated
14. to 85 C for the UC2823A B and UC2825A B 0 C to 70 C for the UC3823A B and UC3825A B RT 3 65k CT 1nF VCC 12V Ta Ty PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Oscillator Section Initial Accuracy Ty 25 C Note 1 375 400 425 kHz Total Variation Line Temperature Note 1 350 450 kHz Voltage Stability 12V lt VCC lt 20V 1 Temperature Stability Tmi lt Ta lt Tmax Note 1 5 A Initial Accuracy RT 6 6k CT 220pF Ta 25 C Note 1 0 9 1 1 1 MHz Total Variation RT 6 6k CT 220pF Note 1 0 85 1 15 MHz Clock Out High 3 7 4 V Clock Out Low 0 0 2 V Ramp Peak 2 6 2 8 3 V Ramp Valley 0 7 1 1 25 V Ramp Valley to Peak 1 6 1 8 2 V Oscillator Discharge Current RT Open Vct 2V 9 10 11 mA Error Amplifier Section Input Offset Voltage 2 10 mV Input Bias Current 0 6 3 uA Input Offset Current 0 1 1 uA Open Loop Gain 1V lt Vo lt 4V 60 95 dB CMRR 1 5V lt Vom lt 5 5V 75 95 dB PSRR 12V lt VCC lt 20V 85 110 dB Output Sink Current Veaout 1V 1 2 5 mA Output Source Current Veaout 4V 0 5 1 3 mA Output High Voltage lEaouT 0 5mA 4 5 4 7 5 V Output Low Voltage lEaouT 1MA 0 0 5 1 V Gain Bandwidth Product F 200kHz 6 12 MHz Slew Rate Note 1 6 9 V us PWM Comparator RAMP Bias Current Vramp OV 1 8 uA Minimum Duty Cycle 0 Maximum Duty Cycle 85 Leading Edg
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UNITRODE UC1823A B/1825A B UC2823A B/2825A B UC3823A B/3825A B handbook