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TEXAS INTRUMENTS UC1823A/UC2823A/UC2823B/UC3823A/UC3823B/UC1825A/UC2825A/UC2825B/UC3825A/UC3825B handbook

1. 5962 8 68102EA X TEXAS i UC1823A UC2823A UC2823B INSTRUMENTS e Qe UC3823A UC3823B UC1825A www ti com UC2825A UC2825B UC3825A UC3825B SLUS334C AUGUST 1995 REVISED AUGUST 2004 HIGH SPEED PWM CONTROLLER FEATURES DESCRIPTION Improved Versions of the UC3823 UC3825 The UC3823A and UC3823B and the UC3825A and PWMs UC3825B family of PWM controllers are improved Compatible with Voltage Mode or versions of the standard UC3823 and UC3825 family Current Mode Control Methods Performance enhancements have been made to several of the circuit blocks Error amplifier gain bandwidth product e Practical Operalion at Switching Frequencies is 12 MHz while input offset voltage is 2 mV Current limit ote threshold is assured to a tolerance of 5 Oscillator 50 ns Propagation Delay to Output discharge current is specified at 10 mA for accurate dead High Current Dual Totem Pole Outputs time control Frequency accuracy is improved to 6 2 A Peak Startup supply current typically 100 uA is ideal for off line e Trimmed Oscillator Discharge Current applications The output drivers are redesigned to actively sink current during UVLO at no expense to the startup Low 100 4A Startup Current current specification In addition each output is capable of Pulse by Pulse Current Limiting Comparator 2 A peak currents during transitions Latched Overcurrent Comparator With Full Cycle Restart BL
2. ARS RT 4 d 39pF 1200 CT VsYNC id HB SP ael 4 7k 220 ANN I6 MASTER cr SLAVE O bH 100 H RT 115RT 50Q gt s External e Clock E UDG 95111 UDG 95113 Figure 9 General Oscillator Synchronization Figure 10 Two Unit Interface VSYNG VcT UDG 95112 Figure 11 Operational Waveforms UC1823A UC2823A UC2823B UC3823A UC3823B UC1825A 3 Texas UC2825A UC2825B UC3825A UC3825B ME T SLUS334C AUGUST 1995 REVISED AUGUST 2004 HIGH CURRENT OUTPUTS Each totem pole output of the UC3823A and UC3823AB UC3825A and UC3825B can deliver a 2 A peak current into a capacitive load The output can slew a 1000 pF capacitor by 15 V in approximately 20 ns Separate collector supply VC and power ground PGND pins help decouple the device s analog circuitry from the high power gate drive noise The use of 3 A Schottky diodes 1N5120 USD245 or equivalent as shown in the Figure 13 from each output to both VC and PGND are recommended The diodes clamp the output swing to the supply rails necessary with any type of inductive capacitive load typical of a MOSFET gate Schottky diodes must be used because a low forward voltage drop is required DO NOT USE standard silicon diodes Although they are single ended devices two output drivers are available on the UC3823A and UC3823B devices These can be paralleled by the use of a 0 5 Q noninductive resistor connected in series with each output for a combined peak c
3. RT 6 6 kQ CT 220 pF 0 85 eeeeeenneeiepseah nai deeeeeieeniiediiaranenn Temperature sabi TmmeTAsTmay a Hgeeeapteige dk S 4 Cd towieveloutputvotage dock T oo amma OO O 26 28 3 v Ramwiy 9r 3 355 Ramp valeyiopeak 3 38 ERROR AMPLIFIER input ofset voltage a Total variation 1 1V lt Vo lt 4V 15V lt Vom lt 5 5V 12 V lt Voc 20 V VEAOUT 1 V VEAOUT 4 V IEAOUT 0 5 mA IEAOUT 1 mA Gain bandwidth product f 200 kHz o Slew rate 1 Eee O un 1 Ensured by design Not production tested UC1823A UC2823A UC2823B WS Texas UC3823A UC3823B UC1825A Sees UC2825A UC2825B UC3825A UC3825B SLUS334C AUGUST 1995 REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS TA 55 C to 125 C for the UC1823A UC1825A TA 40 C to 85 C for the UC2823x UC2825x TA 0 C to 70 C for the UC3823x UC3825x RT 3 65 KQ CT 1 nF Voc 12 V Ta TJ unless otherwise noted PWM COMPARATOR Vzpc Zero dc threshold voltage EAOUT VRAMP 0 V 1 10 1 25 1 4 V tDELAY Delay to output time VEAOUT 2 1 V VILIM 0 V to 2 V step 50 80 CURRENT LIMIT START SEQUENCE FAULT Iss Soft start charge current Vss 2 5 V 8 14 20 V Vss Full soft start threshold voltage 4 3 5 IpscH Restart discharge current Iss Restart threshold voltage IBIAS ILIM bias current ICL Current limit threshold voltage Overcurrent threshold voltage 1 14 1 2 1 26
4. x 1 Dy To Rrx 1 Recommended values for Ry range from 1 kO to 100 kQ Control of Dmax less than 70 is not recommended RT lt P i CLK Ww HH Huh p UDG 95102 Figure 1 Oscillator OSCILLATOR FREQUENCY MAXIMUM DUTY CYCLE vs vs TIMING RESISTANCE TIMING RESISTANCE 10M 100 95 p N o 90 S Sg o Z 85 5 a 5 E 80 Es I X 75 a 10k 70 1k 10k 100 k 1k 10k 100 k Ry Timing Resistance Q RT Timing Resistance Q Figure 2 Figure 3 UC1823A UC2823A UC2823B WS Texas UC3823A UC3823B UC1825A INSTRUMENTS UC2825A UC2825B UC3825A UC3825B SLUS334C AUGUST 1995 REVISED AUGUST 2004 LEADING EDGE BLANKING The UC3823A UC2823B UC3825A and UC3825B perform fixed frequency pulse width modulation control The UC3823A and UC3823B outputs operate together at the switching frequency and can vary from zero to some value less than 100 The UC3825A and UC3825B outputs are alternately controlled During every other cycle one output is off Each output then switches at one half the oscillator frequency varying in duty cycle from 0 to less than 50 To limit maximum duty cycle the internal clock pulse blanks both outputs low duri
5. Br UC2825ADWTR ACTIVE SOIC DW 16 2000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br UC2825ADWTRG4 ACTIVE SOIC DW 16 2000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br UC2825AN ACTIVE PDIP N 16 25 Green RoHS amp CUNIPDAU Level NC NC NC no Sb Br UC2825ANG4 ACTIVE PDIP N 16 25 Green RoHS amp CUNIPDAU Level NC NC NC no Sb Br UC2825AQ ACTIVE PLCC FN 20 46 Green RoHS amp CU SN Level 2 260C 1 YEAR no Sb Br UC2825BDW ACTIVE SOIC DW 16 40 Green RoHS amp CUNIPDAU Level 2 260C 1 YEAR no Sb Br UC2825BDWTR ACTIVE SOIC DW 16 2000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br UC2825BJ OBSOLETE CDIP J 16 TBD Call TI Call TI UC2825BN ACTIVE PDIP N 16 25 Green RoHS amp CUNIPDAU Level NC NC NC no Sb Br UC2825BNG4 ACTIVE PDIP N 16 25 Green RoHS amp CU NIPDAU Level NC NC NC no Sb Br UC3823ADW ACTIVE SOIC DW 16 40 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br UC3823ADWG4 ACTIVE SOIC DW 16 40 Green RoHS amp CUNIPDAU Level 2 260C 1 YEAR no Sb Br UC3823ADWTR ACTIVE SOIC DW 16 2000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br UC3823ADWTRG4 ACTIVE SOIC DW 16 2000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br UC3823AN ACTIVE PDIP N 16 25 Green RoHS amp CU NIPDAU Level NC NC NC no Sb Br UC3823ANG4 ACTIVE PDIP N 16 25 Green RoHS amp CUNIPDAU Level NC NC NC no Sb Br UC3823BDW ACTIVE SOIC DW 16 40 Green RoHS amp CUNIPDAU Level 2 260C 1 YEAR no
6. J 16 1 TBD Call TI Level NC NC NC 5962 8768102XA OBSOLETE TO 92 LP 28 TBD Call TI Call TI 5962 8768103XA OBSOLETE TO 92 LP 28 TBD Call TI Call TI 5962 89905022A ACTIVE LCCC FK 20 1 TBD POST PLATE Level NC NC NC 5962 8990502EA ACTIVE CDIP J 16 1 TBD A42 SNPB Level NC NC NC 5962 8990502VEA ACTIVE CDIP J 16 1 TBD Call TI Level NC NC NC UC1823AJ ACTIVE CDIP J 16 1 TBD A42 SNPB Level NC NC NC UC1823AJ883B ACTIVE CDIP J 16 1 TBD A42 SNPB Level NC NC NC UC1823AJQMLV ACTIVE CDIP J 16 TBD Call TI Call TI UC1823AL ACTIVE LCCC FK 20 1 TBD POST PLATE Level NC NC NC UC1823AL883B ACTIVE LCCC FK 20 1 TBD POST PLATE Level NC NC NC UC1823BJ OBSOLETE CDIP J 16 TBD Call TI Call TI UC1823BJ883B OBSOLETE CDIP J 16 TBD Call TI Call TI UC1823BL OBSOLETE LCCC FK 20 TBD Call TI Call TI UC1823BL883B OBSOLETE LCCC FK 20 TBD Call TI Call TI UC1825AJ ACTIVE CDIP J 16 1 TBD A42 SNPB Level NC NC NC UC1825AJ883B ACTIVE CDIP J 16 1 TBD A42 SNPB Level NC NC NC UC1825AJQMLV ACTIVE CDIP J 16 TBD Call TI Call TI UC1825AL ACTIVE LCCC FK 20 1 TBD POST PLATE Level NC NC NC UC1825AL883B ACTIVE LCCC FK 20 1 TBD POST PLATE Level NC NC NC UC1825ALP883B OBSOLETE TO 92 LP 28 TBD Call TI Call TI UC1825ALQMLV ACTIVE LCCC FK 20 TBD Call TI Call TI UC1825BJ OBSOLETE CDIP J 16 TBD Call TI Call TI UC1825BJ883B OBSOLETE CDIP J 16 TBD Call TI Call TI UC1825BL 81047 OBSOLETE TO SOT L 20 TBD Call TI Call TI UC1825BL883B OBSOLETE LCCC FK 20 TBD Call TI Call TI UC1825BLP883B OBSOLETE TO 92 LP 28 TBD Call T
7. amp esEN non lt 100 UC3823ADW UC3823AN UC3823AQ UC3823BDW UC3823BN dax UC3825ADW UC3825AN Uc3825AQ UC3825BDW UC3825BN UC3825BQ 1 1 The DW and Q packages are also available taped and reeled Add TR suffix to the device type i e UC2823ADWR To order quantities of 1000 devices per reel for the Q package and 2000 devices per reel for the DW package UVLO TA MAXIMUM 9 2 V 8 4 V DUTY CYCLE CDIP 16 LCCC 20 RUNE PIN ASSIGNMENTS DW J OR N PACKAGES Q OR L PACKAGES TOP VIEW TOP VIEW z 3 EAOUT CLK LEB NC 16L NC RT CT 10 NC 9 E i aw zo lt tc NC no connection 4 UC1823A UC2823A UC2823B TEXAS UC3823A UC3823B UC1825A IST RIIME NTS UC2825A UC2825B UC3825A UC3825B SLUS334C AUGUST 1995 REVISED AUGUST 2004 TERMINAL FUNCTIONS TERMINAL NO y o DESCRIPTION NAME J or DW QorL CLK LEB 4 5 O Output of the internal oscillator CT 6 8 Timing capacitor connection pin for oscillator frequency programming The timing capacitor should be connected to the device ground using minimal trace length EAOUT 3 4 O Output of the error amplifier for compensation GND 10 13 A Analog ground return pin ILIM 9 12 l Input to the current limit comparator INV 1 2 l Inverting input to the error amplifier NI 2 3 l Non inverting input to the error amplifier OUTA 11 14 O High current totem pole output A of the on chip drive stage OUTB 14 18 O High curren
8. and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of
9. order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is wit
10. ENTS www ti com zi TO ANALOG T CIRCUITRY CT VREF GND OUT UC1823A UC2823A UC2823B UC3823A UC3823B UC1825A UC2825A UC2825B UC3825A UC3825B SLUS334C AUGUST 1995 REVISED AUGUST 2004 VIN SIGNAL GROUND OPEN LOOP TEST CIRCUIT This test fixture is useful for exercising many functions of this device family and measuring their specifications As with any wideband circuit careful grounding and bypass procedures should be followed The use of a ground plane is highly recommended Figure 13 Ground Planes Diagram UC3823A B UC3825A B Leg RT 3 65k Le 3E Figure 14 Open Loop Test Circuit Schematic 4 CLK LEB vec t SIRT OSCILLATOR 6 CT ve 7 RAMP OUTA EAOUT gt RTN UDG 95115 UDG 95116 11 4 Texas INSTRUMENTS www ti com PACKAGING INFORMATION PACKAGE OPTION ADDENDUM 17 Nov 2005 Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type Drawing Qty 5962 87681022A ACTIVE LCCC FK 20 1 TBD POST PLATE Level NC NC NC 5962 8768102EA ACTIVE CDIP J 16 1 TBD A42 SNPB Level NC NC NC 5962 8768102V2A ACTIVE LCCC FK 20 1 TBD Call TI Level NC NC NC 5962 8768102VEA ACTIVE CDIP
11. I Call TI UC2823ADW ACTIVE SOIC DW 16 40 Green RoHS amp CUNIPDAU Level 2 260C 1 YEAR no Sb Br UC2823ADWTR ACTIVE SOIC DW 16 2000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br UC2823ADWTRG4 ACTIVE SOIC DW 16 2000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br UC2823AJ ACTIVE CDIP J 16 1 TBD A42 SNPB Level NC NC NC UC2823AN ACTIVE PDIP N 16 25 Green RoHS amp CUNIPDAU Level NC NC NC no Sb Br UC2823ANG4 ACTIVE PDIP N 16 25 Green RoHS amp CU NIPDAU Level NC NC NC no Sb Br UC2823AQ ACTIVE PLCC FN 20 46 Green RoHS amp CU SN Level 2 260C 1 YEAR no Sb Br UC2823BDW ACTIVE SOIC DW 16 40 Green RoHS amp CUNIPDAU Level 2 260C 1 YEAR Addendum Page 1 X5 Texas INSTRUMENTS www ti com PACKAGE OPTION ADDENDUM 17 Nov 2005 Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type Drawing Qty no Sb Br UC2823BDWG4 ACTIVE SOIC DW 16 40 Green RoHS amp CUNIPDAU Level 2 260C 1 YEAR no Sb Br UC2823BJ OBSOLETE CDIP J 16 TBD Call TI Call TI UC2823BN ACTIVE PDIP N 16 25 Green RoHS amp CU NIPDAU Level NC NC NC no Sb Br UC2823BNG4 ACTIVE PDIP N 16 25 Green RoHS amp CU NIPDAU Level NC NC NC no Sb Br UC2825ADW ACTIVE SOIC DW 16 40 Green RoHS amp CUNIPDAU Level 2 260C 1 YEAR no Sb Br UC2825ADWG4 ACTIVE SOIC DW 16 40 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb
12. OCK DIAGRAM Pe a RT 5 11 OUTA osc cT 6 l rawe 7i 1 25 V OUTB EAOUT 3 14 12 PGND Sara INV 4 ss 8 ILIM 9 1 2V 4_ RESTART d DELAY i i 0 2 V VCC ES B 16V i0V A 9 2V 8 4V I S r 4L 16 5 1 VREF EGO CCP ECCE S E UDG 02091 On the UC1823A version toggles Q and Q are always low Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments A semiconductor products and disclaimers thereto appears at the end of this data sheet PRODUCTION DATA information is current as of publication date Products Copyright 2004 Texas Instruments Incorporated conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters UC1823A UC2823A UC2823B UC3823A UC3823B UC1825A 3 Texas UC2825A UC2825B UC3825A UC3825B e SLUS334C AUGUST 1995 REVISED AUGUST 2004 y These devices have limited built in ESD protection The leads should be shorted together or the device placed in conductive foam during t A storage or handling to prevent electrostatic damage to the MOS gates DESCRIPTION CONTINUED Functional improvements have also been implemented in this family The UC3825 shutdown comparator is now a high speed overcurrent comparator with a threshold of 1 2 V The overcurrent compara
13. Sb Br UC3823BDWTR ACTIVE SOIC DW 16 2000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br UC3823BDWTRG4 ACTIVE SOIC DW 16 2000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br UC3823BN ACTIVE PDIP N 16 25 Green RoHS amp CUNIPDAU Level NC NC NC no Sb Br Addendum Page 2 K Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 17 Nov 2005 Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type Drawing Qty UC3825ADW ACTIVE SOIC DW 16 40 Green RoHS amp CUNIPDAU Level 2 260C 1 YEAR no Sb Br UC3825ADWTR ACTIVE SOIC DW 16 2000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br UC3825ADWTRG4 ACTIVE SOIC DW 16 2000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br UC3825AN ACTIVE PDIP N 16 25 Green RoHS amp CU NIPDAU Level NC NC NC no Sb Br UC3825AQ ACTIVE PLCC FN 20 46 Green RoHS amp CU SN Level 2 260C 1 YEAR no Sb Br UC3825AQTR ACTIVE PLCC FN 20 1000 Green RoHS amp CU SN Level 2 260C 1 YEAR no Sb Br UC3825BDW ACTIVE SOIC DW 16 40 Green RoHS amp CUNIPDAU Level 2 260C 1 YEAR no Sb Br UC3825BDWTR ACTIVE SOIC DW 16 2000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br UC3825BDWTRG4 ACTIVE SOIC DW 16 2000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br UC3825BN ACTIVE PDIP N 16 25 Green RoHS amp CUNIPDAU Level NC NC NC no Sb Br The marketing status values are defined a
14. Storage temperature 65 C to 150 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds tsTG Storage temperature 65 C to 150 C Lead temperature 1 6 mm 1 16 inch from cases for 10 seconds 300 C 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability UC1823A UC2823A UC2823B 3 UC3823A UC3823B UC18254 I TEXAS s UC2825A UC2825B UC3825A UC3825B wana icem SLUS334C AUGUST 1995 REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS TA 55 C to 125 C for the UC1823A UC1825A TA 40 C to 85 C for the UC2823x UC2825x TA 0 C to 70 C for the UC3823x UC3825x RT 3 65 KQ CT 1 nF Voc 12 V Ta TJ unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE VREF Vo Ouput voltage range Ty 25 C Io 1mA Line regulation 12V lt VCC lt 20V Load regulation 1mAs lt IQ lt 10mA Temperature stability 1 T min lt TA lt T max 0 2 0 4 mV C Output noise voltage 1 10 Hz lt f lt 10 kHz uVRMS Long term stability 1 Ty 125 C 1000 hours 5 25 mV OSCILLATOR um TJ 25 C 375 400 425 osc Initial accuracy RT 6 6kQ CT 220 pF TA 25 C 0 9 1 14
15. VCC and VREF before allowing the chip to operate 3 55 C A 2 Z 25C 5 S 1 Vcc OPEN 0 PGND 0 0 2 0 4 0 6 0 8 1 0 CURRENT A UDG 95108 UDG 95106 Figure 6 Output Voltage vs Output Current Figure 7 Output V and I During UVLO UC1823A UC2823A UC2823B 43 Texas UC3823A UC3823B UC1825A ISTRI ME NTS UC2825A UC2825B UC3825A UC3825B SLUS334C AUGUST 1995 REVISED AUGUST 2004 CONTROL METHODS Current Mode Voltage Mode ISWITCH 1 ANA Js OSCILLATOR Pam LL cr CT 6 OSCILLATOR 7 CT 3d 125V 1 25V l 7 il 7 ii RSENSE RAMP T CT RAMP FROM E A FROM E A UDG 95110 UDG 95109 gt Figure 8 Control Methods SYNCHRONIZATION The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor Program the free running frequency of the oscillator to be 10 to 15 slower than the desired synchronous frequency The pulse width should be greater than 10 ns and less than half the discharge time of the oscillator The rising edge of the CLK LEB pin can be used to generate a synchronizing pulse for other chips Note that the CLK LEB pin no longer accepts an incoming synchronizing signal
16. equired on the ILIM pin CLK LEB Exec LEB IL dL RAMP INPUT BLANKED RAMP TO PWM UDG 95105 Figure 4 Leading Edge Blanking Operational Waveforms UC1823A UC2823A UC2823B 4 UC3823A UC3823B UC1825A TEXAS rs UC2825A UC2825B UC3825A UC3825B www ti com SLUS334C AUGUST 1995 REVISED AUGUST 2004 UVLO SOFT START AND FAULT MANAGEMENT Soft start is programmed by a capacitor on the SS pin At power up SS is discharged When SS is low the error amplifier output is also forced low While the internal 9 uA source charges the SS pin the error amplifier output follows until closed loop regulation takes over Anytime ILIM exceeds 1 2 V the fault latch is set and the output pins are driven low The soft start cap is then discharged by a 250 uA current sink No more output pulses are allowed until soft start is fully discharged and ILIM is below 1 2 V At this point the fault latch resets and the chip executes a soft start Should the fault latch get set during soft start the outputs are immediately terminated but the soft start capacitor does not discharge until it has been fully charged first This results in a controlled hiccup interval for continuous fault conditions 1 2V FAULT 5 0V Vss 1 2V 0 2V ON 7 PWM OFF 4 UDG 95106 Figure 5 Soft Start and Fault Waveforms ACTIVE LOW OUTPUTS DURING UVLO The UVLO function forces the outputs to be low and considers both
17. hout alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Telephony www ti com telephony Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2005 Texas Instruments Incorporated
18. ng the discharge time of the oscillator On the falling edge of the clock the appropriate output s is driven high The end of the pulse is controlled by the PWM comparator current limit comparator or the overcurrent comparator Normally the PWM comparator senses a ramp crossing a control voltage error amplifier output and terminates the pulse Leading edge blanking LEB causes the PWM comparator to be ignored for a fixed amount of time after the start of the pulse This allows noise inherent with switched mode power conversion to be rejected The PWM ramp input may not require any filtering as result of leading edge blanking To program a leading edge blanking LEB period connect a capacitor C to CLK LEB The discharge time set by C and the internal 10 kQ resistor determines the blanked interval The 10 kQ resistor has a 10 tolerance For more accuracy an external 2 kQ 1 resistor R can be added resulting in an equivalent resistance of 1 66 kQ with a tolerance of 2 4 The design equation is Values of R less than 2 kQ should not be used Leading edge blanking is also applied to the current limit comparator After LEB if the ILIM pin exceeds the 1 V threshold the pulse is terminated The overcurrent comparator however is not blanked It catches catastrophic overcurrent faults without a blanking delay Any time the ILIM pin exceeds 1 2 V the fault latch is set and the outputs driven low For this reason some noise filtering may be r
19. s follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free RoHS or Green RoHS amp no Sb Br please check http Awww ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications
20. t totem pole output B of the on chip drive stage PGND 12 15 Ground return pin for the output driver stage Non inverting input to the PWM comparator with 1 25 V internal input offset In voltage mode RAMP 7 9 l operation this serves as the input voltage feed forward function by using the CT ramp In peak current mode operation this serves as the slope compensation input RT 5 T l Timing resistor connection pin for oscillator frequency programming SS 8 10 Soft start input pin which also doubles as the maximum duty cycle clamp Power supply pin for the output stage This pin should be bypassed with a 0 1 uF monolithic ceramic Me 1e d A low ESL capacitor with minimal trace lengths VCC 15 19 7 Power supply pin for the device This pin should be bypassed with a 0 1 uF monolithic ceramic low ESL capacitor with minimal trace lengths VREF 16 20 o 5 1 V reference For stability the reference should be bypassed with a 0 1 uF monolithic ceramic low ESL capacitor and minimal trace length to the ground plane ABSOLUTE MAXIMUM RATINGS over operating free air temperature range unless otherwise noted 1 tr 7 VIN Supply voltage VC VCC 22 V lO Source or sink current DC OUTA OUTB Source or sink current pulse 0 5 us OUTA OUTB lo Analog inputs Power ground IcLK Clock output current lo EA Error amplifier output current Iss Soft start sink current S RT TJ Operating virtual junction temperature range 55 C to 150 C Tstg
21. td Delay to output time ILIM 1 VILIM 0 V to 2 V step 50 80 OUTPUT iowevel f l IOUT 20 mA 0 25 0 4 ow level output saturation voltage IOUT 200 mA 12 22 IOUT 20 mA 1 9 2 9 High level output saturation voltage IOUT 200 mA a a 2 3 i Rise fall time 1 CL 1nF 20 45 UNDERVOLTAGE LOCKOUT UVLO UC2823B UC2825B UC3825B UC3825B 16 17 Start threshold voltage UC1823A UC1825A UC2823A UC2825A 84 9 2 9 6 UC3825A UC3825A Stop threshold voltage UC2823B UC2825B UC3825B UC3825B UC1823A UC1825A UC2823A UC2825A 04 0 8 12 UC3825A UC3825A i 5 6 7 UC2823B UC2825B UC3825B UC3825B OVLO hysteresis SUPPLY CURRENT Isu Startup current VC VCC VTH 0 5 V 100 300 uA Ico Input current Doo O 28 3 1 Ensured by design Not production tested UC1823A UC2823A UC2823B 4 UC3823A UC3823B UC1825A TEXAS rs UC2825A UC2825B UC3825A UC3825B www ti com SLUS334C AUGUST 1995 REVISED AUGUST 2004 APPLICATION INFORMATION The oscillator of the UC3823A UC3823B UC3825A and UC3825B is a saw tooth The rising edge is governed by a current controlled by the RT pin and value of capacitance at the CT pin Cct The falling edge of the sawtooth sets dead time for the outputs Selection of RT should be done first based on desired maximum duty cycle CT can then be chosen based on the desired frequency RT and Dmax The design equations are c 3v i _ 16 x Dmax T 10 mA
22. tor sets a latch that ensures full discharge of the soft start capacitor before allowing a restart While the fault latch is set the outputs are in the low state In the event of continuous faults the soft start capacitor is fully charged before discharge to insure that the fault frequency does not exceed the designed soft start period The UC3825 CLOCK pin has become CLK LEB This pin combines the functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing The UC3825A and UC3825B have dual alternating outputs and the same pin configuration of the UC3825 The UC3823A and UC3823B outputs operate in phase with duty cycles from zero to less than 100 The pin configuration of the UC3823A and UC3823B is the same as the UC3823 except pin 11 is now an output pin instead of the reference pin to the current limit comparator A version parts have UVLO thresholds identical to the original UC3823 and UC3825 The B versions have UVLO thresholds of 16 V and 10 V intended for ease of use in off line applications Consult the application note The UC3823A B and UC3825A B Enhanced Generation of PWM Controllers SLUA125 for detailed technical and applications information ORDERING INFORMATION UVLO MAXIMUM DUTY CYCLE soic 16 1 PDIP 16 PLCC 20 1 SOIC 16 PDIP 16 PLCC 20 1 arcu asc 100 UcasasabW UCZS SAN UC2S SAQ Uc2823BDWw UCZSESEN 50 ucesesabw UOB2SAN UOZB2sAQ UC2S25BDW UCa
23. urrent of 4 A Avc ae EP inf 10pF I n A D1 Jour ue n m Np2 PGND prc GND D1 D2 1N5820 UDG 95114 Figure 12 Power MOSFET Drive Circuit GROUND PLANES Each output driver of these devices is capable of 2 A peak currents Careful layout is essential for correct operation of the chip A ground plane must be employed A unique section of the ground plane must be designated for high di dt currents associated with the output stages This point is the power ground to which the PGND pin is connected Power ground can be separated from the rest of the ground plane and connected at a single point although this is not necessary if the high di dt paths are well understood and accounted for VCC should be bypassed directly to power ground with a good high frequency capacitor The sources of the power MOSFET should connect to power ground as should the return connection for input power to the system and the bulk input capacitor The output should be clamped with a high current Schottky diode to both VCC and PGND Nothing else should be connected to power ground VREF should be bypassed directly to the signal portion of the ground plane with a good high frequency capacitor Low ESR ESL ceramic 1 mF capacitors are recommended for both VCC and VREF All analog circuitry should likewise be bypassed to the signal ground plane 10 35 TEXAS INSTRUM

TEXAS INTRUMENTS UC1823A/UC2823A/UC2823B/UC3823A/UC3823B/UC1825A/UC2825A/UC2825B/UC3825A/UC3825B handbook

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