UNITRODE UC1633/UC2633/UC3633 handbook
Contents
1. I Motor Ko Phase Detector Gain 4V RAD N GPD Power Stage Transductance 1A V 101 02 050 10 2 0 5 1 2 5 10 20 50100 KT Motor Torque Constant 022NM A J Motor Moment of Inertia 0015NM A SEC Normalized Frequency f f u gt fu 4Hz s 2nijf Note For a current mode driver the electrical time constant Lm Rm of the motor does not enter into the small signal response If a voltage mode drive scheme is used then the asymptote plotted as 2 above can be approximated by kr RM Ne K eo KPDeKT a 2n ede Rm 27 e LM s e Je Rm Lu if RM gt KT J and Here Kpp Voltage gain of Driver Stage Rm Motor Winding Resistance Lm Motor Winding Inductance UNITRODE CORPORATION 7 CONTINENTAL BLVD e MERRIMACK NH 03054 TEL 603 424 2410 FAX 603 424 3460 IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its semiconducto2. Input Voltage n nana 00 eee eee 3V to 5V Sense Amplifier Input Voltage 3V to 20V Power Dissipation at TA 25 C Note2 1000mW Power dissipation at Tc 25 C Note 2 2000mW Operating Junction Temperature 55 C to 150 C Storage Temperature 005 65 C to 150 C Lead Temperature Soldering 10 Seconds 300 C DIL 16 TOP VIEW J or N Package Div 4 5 Input Div 2 4 8 Input Lock Indicator Output Phase Detector Output Dbl Edge Disable Input 12 Output Sense Amp Aux Amp Input 11 Inv Input 5V Ref Aux Amp Output 10 Non Inv Input Loop Amp Inv Input 16 Ground osc 15 Input osc 14 Output 13 VIN Aux Amp 9 Loop Amp Output UC1633 UC2633 UC3633 Note1 Voltages are referenced to ground Pin 16 Currents are positive into negative out of the specified terminals Note 2 Consult Packaging Section of Databook for thermal limi tations and considerations of package CONNECTION DIAGRAMS PLCC 20 TOP VIEW Q Package PACKAGE PIN FUNCTION FUNCTION PIN N C 1 Div 4 5 Input 2 Div 2 4 8 Input 3 Lock Indicator Output 4 Phase Detector Output 5 N C 6 Dbl Edge Disable Input 7 Sense Amp Input 8 5V Ref Output 9 Loop Amp Inv Input 10 N C 11 Loop Amp Output 12 Aux Amp Non Inv Input 13 14 15 16 17 18 19 20 3 2 1 2019 KZ Aux Amp Inv Input Aux Amp
3. 8V to 15V 70 100 dB Short Circuit Current Source Vout 0V 16 35 mA Sink Vout 5V 16 30 mA Auxiliary Op Amp Input Offset Voltage Vom 2 5V 8 mV Input Bias Current Vom 2 5V 0 8 0 2 uA Input Offset Current Vom 2 5V 01 0 1 uA AVOL 70 120 dB PSRR Vin 8V to 15V 70 100 dB CMRR Vom OV to 10V 70 100 dB Short Circuit Current Source VouT OV 16 35 mA Sink VouT 5V 16 30 mA Note 3 These impedence levels will vary with Ty at about 1700ppm C APPLICATION AND OPERATING INFORMATION Determining the Oscillator Frequency The frequency at the oscillator is determined by the de sired RPM of the motor the divide ratio selected the number of poles in the motor and the state of the double edge select pin fosc Hz Divide Ratio e Motor RPM e 1 60 SEC MIN e No of Rotor Poles 2 e x 2 if Pin 5 Low UC1633 UC2633 UC3633 The resulting reference frequency appearing at the phase detector inputs is equal to the oscillator frequency divided by the selected divide ratio If the double edge option is used Pin 5 low the frequency of the sense amplifier in put signal is doubled by responding to both the rising and falling edges of the input signal Using this option the loop reference frequency can be doubled for a given motor RPM Recommended Oscillator Configuration Using AT Cut Quartz Crystal lt 10MHz 10pF 1VpP i Ss L 1VPP May Be Required To Prevent Spurious O
4. O 0 Ucea o 0 UC1633 SAA UNITRODE C2638 EN UC3633 Phase Locked Frequency Controller amp FEATURES DESCRIPTION e Precision Phase Locked Frequency The UC1633 family of integrated circuits was designed for use in phase Control System locked frequency control loops While optimized for precision speed control of DC motors these devices are universal enough for most ap plications that require phase locked control A precise reference fre e Programmable Reference Frequency quency can be generated using the device s high frequency oscillator Dividers and programmable frequency dividers The oscillator operates using a broad range of crystals or can function as a buffer stage to an external frequency source e Crystal Oscillator e Phase Detector with Absolute Frequency Steering The phase detector on these integrated circuits compares the refer ence frequency with a frequency phase feedback signal In the case of e Double Edge Option on the Frequency a motor feedback is obtained at a hall output of other speed detection Feedback Sensing Amplifier device This signal is buffered by a sense ampilfier that squares up the signal as it goes into the digital phase detector The phase detector re sponds proportionally to the phase error between the reference and the e 5V Reference Output sense amplifier output This phase detector includes absolute fre quency steering to provide maximum drive signals when any frequency error exist
5. Output N C VIN OSC Output OSC Input Ground 9 10 11 12 13 ELECTRICAL CHARACTERISTICS Unless otherwise stated these specifications apply for Ta 0 C to 70 C for the UC3633 25 C to 85 C for the UC2633 55 C to 125 C for the UC1633 VIN 12V TA Ty PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Supply Current VIN 15V 20 28 mA Reference Output Voltage VREF 4 75 5 0 5 25 V Load Regulation louT OV to 7mA 5 0 20 mV Line Regulation VIN 8V to 15V 2 0 20 mV Short Circuit Current VouT 0V 12 30 mA Oscillator DC Voltage Gain Oscillator Input to Oscillator Output 12 16 20 dB Input DC Level Vis Oscillator Input Pin Open Tu 25 C 1 15 1 3 1 45 V Input Impedance Note 3 VIN VB 0 5V Ty 25 C 1 3 1 6 1 9 kQ Output DC Level Oscillator Input Pin Open Tu 25 C 1 2 1 4 1 6 V Maximum Operating Frequency 10 MHz Dividers Maximum Input Frequency Input 1VpPP at Oscillator Input 10 MHz Div 4 5 Input Current Input 5V Div by 4 150 500 uA Input OV Div by 5 5 0 0 0 5 0 uA Div 4 5 Threshold 0 5 1 6 2 2 V Note 3 These impedence levels will vary with TJ at about 1700ppm C UC1633 UC2633 UC3633 ELECTRICAL Unless otherwise stated these specificat
6. gh for a time equal to the time dif ference between the rising edges of the inputs and will be at its middle level for the remainder of the period If the phase relationship is reversed then the detector will go low for a time proportional to the phase difference of the inputs The resulting gain of the phase detector k is UC1633 UC2633 UC3633 5V 4r radians or about 0 4V radian The dynamic range of the detector is 27 radians The operation of the phase detector is illustrated in the figures below The upper figure shows typical voltage waveforms seen at the detector output for leading and lagging phase conditions The lower figure is a state dia gram of the phase detector logic In this figure the circles represent the 10 possible states of the logic and the con necting arrows represent the transition events paths to and from these states Transition arrows that have a clock wise rotation are the result of a rising edge on the input and conversely those with counter clockwise rotation are tied to the rising edge of the input signal The normal operational states of the logic are 6 and 7 for positive phase error 1 and 2 for a negative phase error States 8 and 9 occur during positive frequency error 3 and 4 during negative frequency error States 5 and 10 occur only as the inputs cross over from the frequency er ror to anormal phase error only condition The level of the phase detector output is determined by the logic s
7. ions apply for Ta 0 C to 70 C for the UC3633 CHARACTERISTICS cont 25 C to 85 C for the UC2633 55 C to 125 C for the UC1633 VIN 12V TA Ty PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Dividers cont Div 2 4 8 Input Current Input 5V Div by 8 150 500 uA Input OV Div by 2 500 150 uA Div 2 4 8 Open Circuit Voltage Input Current OA Div by 4 1 5 2 5 3 5 V Div by 2 Threshold 0 20 0 8 V Div by 4 Threshold 1 5 3 5 V Div by 8 Threshold Volts Below VREF 0 20 0 8 V Sense Amplifier Threshold Voltage Percent of VREF 27 30 33 Threshold Hysteresis 10 mV Input Bias Current Input 1 5V 1 0 0 2 uA Double Edge Disable Input Input Current Input 5V Disabled 150 500 uA Input OV Enabled 5 0 0 0 5 0 uA Threshold Voltage 0 5 1 6 2 2 v Phase Detector High Output Level Positive Phase Freq Error Volts Below VREF 0 2 0 5 V Low Output Level Negative Phase Freq Error 0 2 0 5 V Mid Output Level Zero Phase Freq Error Percent of VREF 47 50 53 High Level Maximum Source Current VouT 4 3V 2 0 8 0 mA Low Level Maximum Sink Current VouT 0 7V 2 0 5 0 mA Mid Level Output Impedance Note 3 louT 200 to 200nA Tu 25 C 4 5 6 0 7 5 kQ Lock Indicator Output Saturation Voltage Freq Error IOUT 5mA 0 3 0 45 V Leakage Current Zero Freq Error VouT 15V 0 1 1 0 uA Loop Amplifier NON INV Reference Voltage Percent of VREF 47 50 53 Input Bias Current Input 2 5V 0 8 0 2 uA AVOL 60 75 dB PSRR Vin
8. nse 0 0 20 40 60 80 10 Voltage Gain dB Phase Shift degrees 0 1 0 2 0 40 60 81 2 4 6 8 10 0 1 02 0 40 6 0 8 1 Normalized Frequency N Normalized Frequency oN Variable is Ta Variable is ue For R1 R2 1 C1 C2 For R1 R2 1 C1 C2 UC1633 UC2633 APPLICATION AND OPERATION INFORMATION UC3633 Design Example 022V SEC RAD Lock Indication 022NM AMP Output 1 5E 3 NM SEC Includes 3 5 Platters MHz iu 1OpF 00224 15H 3 9 3 UC3620 Switchmode 3 6 Driver UC3633 Phase Locked Controller 4 Mol 12 12 91k 91k Hall Logic Outputs 022p 474 270k 0224 F Precision phase locked frequency control of 3 phase motor at 3600 RPM Drive scheme is current fed using the UC3620 switch mode driver for 3 motors Bode Plots Design Example Open Loop Response 1 KLF s KRF s 2 N K o GPD Kr l seed 3 Combined Overall Open Loop Response SK Where KLF s Loop Filter Response NL KRF s Reference Filter Response N 4 Using Double Edge Sensing With 4 Pole
9. r products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not cons
10. s This feature allows optimum start up and lock times to be realized e Digital Lock Indicator e Two High Current Op Amps Two op amps are included that can be configured to provide necessary loop filtering The outputs of the op amps will source or sink in excess of 16mA so they can provide a low impedence control signal to driving circuits Additional features include a double edge option on the sense amplifier that can be used to double the loop reference frequency for increased loop bandwidths A digital lock signal is provided that indicates when there is zero frequency error and a 5V reference output allows DC op erating levels to be accurately set 2 Divide a Select Div 4 5 Div 2 4 8 Output BLOCK DIAGRAM Input Output Detector Sense Amplifier Double Edge Logic Lock Do ble Edge es gt Indicator Disable Loop Amplifier 5V VIN Gnd Out 4 97 ABSOLUTE MAXIMUM RATINGS Input Supply Voltage VIN 2 cee ee eee 20V Reference Output Current 0000 eee ee 30mA Op Amp Output Currents 0000000 30mA Op Amp Input Voltages 0 05 3V to 20V Phase Detector Output Current 10mA Lock Indicator Output Current 2 0 005 15mA Lock Indicator Output Voltage 0 0 20 ee 20V Divide Select Input Voltages 3V to 10V Double Edge Disable Input Voltage 3V to 10V Oscillator
11. scillation 1 6k Oscillator 16DB UCi633 External Reference Frequency Input External Reference 1 To aver SNS AHE Or 2VpP to 2V Oscillator 1uF 100k 1 VPP gt 300mVPP Low Level Analog Hall Output Sense Amplifier This signal may require filtering if chopped mode drive scheme is used APPLICATION AND OPERATION INFORMATION Phase Detector Operation The phase detector on these devices is a digital circuit that responds to the rising edges of the detector s two in puts The phase detector output has three states a high 5V state a low OV state and a middle 2 5V state In the high and low states the output impedance of the detector is low and the middle state output impedence is high typi cally 6 0kQ When there is any static frequency difference between the inputs the detector output is fixed at its high level if the input the sense amplifier signal is greater in frequency and fixed at its low level if the input the refer ence frequency signal is greater in frequency When the frequencies of the two inputs to the detector are equal the phase detector switches between its middle state and either the high or low states depending on the relative phase of the two signals If the input is leading in phase then during each period of the input frequency the detector output will be hi
12. tate as defined in the state diagram figure The lock indicator out put is high off when the detector is in states 1 2 6 or 7 Typical Phase Detector Output Waveforms T One Period of Reference Frequency Sense Amplifier Input Leading Reference Frequency Input By 90 Degrees Sense Amplifier Input Trailing Reference Frequency Input By 90 Degrees Rising Edge on Phase Detector gt Input Reference Rising Edge on Phase Detector Input Sense Amp Output 5V output 2 5V Output 0V Digital Lock Indicator High During States 1 2 6 and 7 UC1633 UC2633 APPLICATION AND OPERATION INFORMATION UC3633 Suggested Loop Filter Configuration From Ref Filter To Power _ Vout Drive Stage R2G1 Loop UCi633 l Amp 1 VADJ 5V or OV u R Re C1 The static phase error of the loop is easily adjusted by Where AVOUT VOUT 2 5V adding resistor R4 as shown To lock at zero phase error and VouT DC Operating Voltage At R4 is determined by Loop Amplifier Output During Phase Lock _ 2 5Ve R3 If VOUT 2 5 gt 0 R4 Goes to OV Ra A Vout Vout 2 5 lt 0 R4 Goes to 5 0V Reference Filter Configuration From Phase Detector ToL Output o Filter VIN Input VOUT UC1633 Auxiliary Op Amp Note with R1 R2 Reference Filter Design Aid Gain Response Reference Filter Design Aid Phase Respo
13. titute Tl s approval warranty or endorsement thereof Copyright 1999 Texas Instruments Incorporated
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UNITRODE UC1633/UC2633/UC3633 handbook