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TEXAS INSTRUMENTS TL16C552A TL16C552AM handbook

1. LX TTL oes cyst 2 iE programmable baud rate generator The ACE serial channel contains a programmable baud rate generator BRG that divides the clock dc to 8 MHz by any divisor from 1 to 216 1 The output frequency of the baud generator is 16x the data rate divisor clock baud rate x 16 referred to in this document as RCLK Two 8 bit divisor latch registers store the divisor in a 16 bit binary format These divisor latch registers must be loaded during initialization Upon loading either of the divisor latches a 16 bit baud counter is immediately loaded This prevents long counts on initial load The BRG can use any of three different popular frequencies to provide standard baud rates These frequencies are 1 8432 MHz 3 072 MHz and 8 MHz With these frequencies standard bit rates from 50 to 512 kbps are available Tables 14 15 16 and 17 illustrate the divisors needed to obtain standard rates using these three frequencies 32 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PRINCIPLES OF OPERATION programmable baud rate generator continued Table 14 Baud Rates Using a 1 8432 MHz Crystal BAU
2. n a Z cc gt lt Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet IBM PC AT is a trademark of International Business Machines Corporation PRODUCTION DATA information is current as of publication date Copyright 1999 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments ik standard warranty Production processing does not necessarily include testing of all parameters I EXAS POST OFFICE BOX 655303 DALLAS TEXAS 75265 1 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PN PACKAGE TOP VIEW 12 oEEBREEEZ888888852899 2 zezolei ioocnoanononocaoanononoazcmmzz 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 e gt description The TL16C552A is an enhanced dual channel version of the popular TL16C550B asynchronous communications element ACE The device serves two serial input output interfaces simultaneously in microcomputer or microprocessor based systems Each channel performs serial to parallel conversion on data characters received from peripheral devices or modems and parallel to serial conversion on data ch
3. 50 51 32 3 Be 19 Chip select Each CSx input acts as an enable for the write and read signals for serial channels 1 CS0 38 and 2 CS1 CS2 enables the signals to the printer port 28 13 44 26 Clearto send The logical state of each CTSx terminal is reflected in the CTS bit of the modem status register CTS is bit 4 of the modem status register written as MSR4 of each ACE A change of state in either CTS terminal since the previous reading of the associated MSR causes the setting of ACTS MSRO of each modem status register Data bits DBO DB7 The data bus provides eight I O lines with 3 state outputs for the transfer of data control and status information between the TL16C552A and the CPU These lines are normally in the high impedance state except during read operations DBO is the least significant bit LSB and is the first serial data bit to be received or transmitted Data carrier detect DCD is a modem input Its condition can be tested by the CPU by reading MSR7 DCD of the modem status registers MSR3 ADCD of the modem status register indicates whether DCD has changed states since the previous reading of the MSR DCD has no effect on the receiver Data set ready The logical state of the DSRx terminals is reflected in MSR5 of its associated modem status register ADSR MSR1 indicates whether the associated DSRx terminal has changed states since the previous reading of the MSR Data terminal ready Each DTRx can be se
4. 1 60 MAX 2 0 08 4040135 11 96 NOTES Alllinear dimensions millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 026 TEXAS INSTRUMENTS 38 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE
5. Terminal Functions Continued TERMINAL NO y o DESCRIPTION FN Serial data outputs SOUTO and SOUT1 are the serial data outputs from the ACE transmitter circuitry A mark is a high state and a space is a low state Each SOUT is held in the mark condition when the transmitter is disabled RESET is asserted low the transmitter register is empty or when in the loop mode Line printer strobe STB provides communication between the TL16C552A and the printer When STB is active low it provides the printer with a signal to latch the data currently on the parallel port STB has an internal pullup resistor to Vpp of approximately 10 3 state output control input TRI controls the 3 state control of all I O and output terminals When TRI is asserted all l Os and outputs are in the high impedance state allowing board level testers to drive the outputs without overdriving internal buffers TRI is level sensitive and is pulled down with an internal resistor that is approximately 5 kO TXRDYO Transmitter ready Two types of DMA signaling are available Either can be selected using FCR3 when TXRDY1 operating in FIFO mode Only DMA mode 0 is allowed when in TL16C450 mode Single transfer DMA atransfer is made between CPU bus cycles is supported by mode 0 Multiple transfers that are made continuously until the transmitter FIFO has been filled are supported by mode 1 Mode 0 In FIFO mode FCRO 1 FCR3 0 or in TL16C450 mode FCRO
6. 0 when there are characters in the transmitter holding register or transmitter FIFO TXRDYx is active low Once TXRDYx is activated low it goes inactive after the first character is loaded into the holding register of the transmitter FIFO Mode 1 TXRDY goes active low in FIFO mode FCRO 1 when FCR3 1 and there are no characters the transmitter FIFO When the transmitter FIFO is completely full TXRDY goes inactive high 23 40 6 36 a Power supply The Vpp requirement is 5 V 5 64 56 absolute maximum ratings over operating free air temperature range unless otherwise noted t Supply voltage range Vpp see Note 1 0 5 V to Vpp 0 3 V Input voltage range Vj seus tarer ostoi rame detente ttd 0 5Vto7V Output voltage range Vo ee eme made ern 0 5 V to Vpp 0 3 V Continuous total power dissipation See Dissipation Rating Table Operating free air temperature range Suffix 40 C to 85 C MSU seemed emm eem wem nee 55 C to 125 C Storage temperature range sete pasen ee Rp doro ecce Rad aaa agunt 65 C to 150 C t Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond
7. 9 Pin D Connector Address Bus Dual ACE and Printer Control Bus Port 9 Pin D Connector Option Jumpers 25 Pin D Connector A2 A1 A0 5096 Valid 5096 11 gt CS0 CST 52 50 509 tsut d 4 42 4 ta1 gt E tsu2 Acti Active IOR 50 Active 50 50 A tw4 rit 192 gt or M v IOW 50 Active tpd1 6 3 es BDO 50 N 5096 I 9 tdis ten DBO DB7 Valid Data Figure 4 Read Cycle Timing Waveforms 35 TEXAS INSTRUMENTS J POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION A2 A1 A0 5096 Valid 50 th3 gt CS0 CS1 52 50 ui 50 tsu4 gt 4 tha 4 td3 gt tsu5 IOW 50 Active 50 50 Active A t i tw5 4 d4 IOR 50 Active tsu6 th5 DBO DB7 Valid Data Figure 5 Write Cycle Timing Waveforms Start Sian Serial Out eae Data Bits 5 8 50 SOUT Stop 1 2 145 Parity I 9 tae THRE 50 50 50 50 50 tpd2 4 I4 le tpd2 gt IOW WR THR 50 50 50 14 9 IOR N 50 RD IIR 50 Figure 6 Transmitter Timing Waveforms Byte 1 IOW WR
8. FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 1999 Texas Instruments Incorporated
9. indicated or trigger level reached However the receiver and transmitter FIFOs still have the capability of holding characters The LSR must be read to determine the ACE status interrupt enable register IER The IER independently enables the four serial channel interrupt sources that activate the interrupt INTO or INT1 output All interrupts are disabled by clearing IERO IER3 Interrupts are enabled by setting the appropriate bits of the IER Disabling the interrupt system inhibits the interrupt identification register and the active high interrupt output All other system functions operate in their normal manner including the setting of the LSRs and MSRs The contents of the IER shown in Table 3 are described in the following bulleted list Bit0 When IERO is set IERO enables the received data available interrupt and the time out interrupts in the FIFO mode 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 21 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PRINCIPLES OF OPERATION interrupt enable register IER continued Bit 1 When IER1 is set the transmitter holding register empty interrupt is enabled Bit 2 When 2 is set the receiver line status interrupt is enabled Bit 3 When IER3 is set the modem status interrupt is enabled Bits 4 7 IER4 through IER are cleared In order to
10. is the initialize printer control bit When INIT is set the INIT signal is negated When INIT is cleared the INIT signal is asserted on the LPT interface Bit3 SLIN isthe select input control bit When SLIN is set the SLIN signal is asserted on the LPT interface When SLIN is cleared the signal is negated Bit4 INT2 EN isthe interrupt request enable control bit When set INT2 EN enables interrupts from the LPT port When cleared INT2 EN disables interrupts and places INT2 signal in the high impedance state Bit 5 DIR is the direction control bit which is only used when PEMD is high When DIR is set the output buffers in the LPD port are disableded to allow data driven from external sources to be read from the LPD port When DIR is cleared the LPD port is in the output mode 6 7 These bits are reserved and are always cleared 435 TEXAS INSTRUMENTS 26 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PRINCIPLES OF OPERATION line status register LSR The LSR is a single register that provides status indicators The LSR bits shown in Table 9 are described in the following bulleted list BitO DR is the data ready bit When set an incoming character is received and transferred into the receiver buffer register or in the FIFO LSRO is cleared by a CPU read of the data in t
11. minimize software overhead during data character transfers the serial channel prioritizes interrupts into four levels The four levels of interrupt conditions are as follows Priority 1 Receiver line status highest priority Priority 2 Receiver data ready or receiver character time out Priority 3 Transmitter holding register empty Priority 4A Modem status lowest priority Information indicating that a prioritized interrupt is pending and the type of interrupt is stored in the IIR The IIR indicates the highest priority interrupt pending The contents of the IIR are indicated in Table 5 Table 5 Interrupt Control Functions INTERRUPT IDENTIFICATION INTERRUPT SET AND RESET FUNCTIONS REGISTER PRIORITY INTERRUPT RESET LEVEL INTERRUPT TYPE INTERRUPT SOURCE CONTROL First Receiver line status OE PE FE or BI LSR read Second Received data available Receiver data available or trigger level read until FIFO reached drops below the trigger level Character time out No characters have been removed from or RBR read indicator input to the receiver FIFO during the last four character times and there is at least one character in it during this time THRE IIR read if THRE is the interrupt source or THR write Modem status CTS DSR RI or MSR read Bit 0 IIRO indicates whether an interrupt is pending When IIRO is cleared an interrupt is pending Bits 1 and 2 IIR1 and IIR2 identify the hi
12. of the FIFO Bit 4 Bl is the break interrupt bit Bl is set when the received data input is held in the spacing low state for longer than a full word transmission time start bit data bits parity stop bits The BI indicator is cleared when the CPU reads the contents of the LSR In FIFO mode this is associated with a particular character in the FIFO LSR4 reflects when the break character is at the top of the FIFO The error is detected by the CPU when its associated character is at the top of the FIFO during the first LSR read Only one zero character is loaded into the FIFO when BI occurs LSR1 LSR4 are the error conditions that produce a receiver line status interrupt priority 1 interrupt in the interrupt identification register when any ofthe conditions are detected This interrupt is enabled by setting IER2 in the interrupt enable register Bit5 THRE is the transmitter holding register empty bit THRE indicates that the ACE is ready to accept a new character for transmission The THRE bit is set when a character is transferred from the transmitter holding register into the transmitter shift register LSR5 is cleared by the loading of the transmitter holding register by the CPU LSR5 is not cleared by a CPU read of the LSR In FIFO mode when the transmitter FIFO is empty this bit is set It is cleared when one byte is written to the transmitter FIFO When the THRE interrupt is enabled by IER1 THRE causes a priority 3 interrupt i
13. receiver FIFO or after a new character is received when there has been no time out interrupt 4 Atime outinterruptis cleared and the timer is reset when the CPU reads a character from the receiver FIFO Transmitter interrupts occur as follows when the transmitter and transmitter FIFO interrupts are enabled FCRO 1 IER 1 1 Whenthetransmitter FIFO is empty the transmitter holding register interrupt IIR 2 02 occurs The interrupt is cleared when the transmitter holding register is written to or the IIR is read One to sixteen characters can be written to the transmit FIFO when servicing this interrupt 2 Thetransmitter FIFO empty indicators are delayed one character time minus the last stop bit time when the following occurs THRE 1 and there is not a minimum of two bytes atthe same time in transmitter FIFO since the last THRE 1 The first transmitter interrupt after changing FCRO is immediate assuming it is enabled Receiver FIFO trigger level and character time out interrupts have the same priority as the received data available interrupt The transmitter holding register empty interrupt has the same priority as the transmitter FIFO empty interrupt FIFO polled mode operation Clearing IERO IER1 IER2 IERS or all with FCRO 1 puts the ACE into the FIFO polled mode The receiver and transmitter are controlled separately Either one or both can be in the polled mode In the FIFO polled mode there is no time out condition
14. souri RH 60 INTI SIN1 61 RXRDY1 csi 42 TXRDYi 0 2 iow Select IOR Gon BDO RESET Logic CLK PD0 PD7 INIT AFD STB 8 is sm 98 59 INT2 CS2 38 ENIRO 43 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 3 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 Terminal Functions TERMINAL NO DESCRIPTION NAME 10 Line printer acknowledge ACK goes low to indicate a successful data transfer has taken place ACK generates a printer port interrupt during its positive transition Line printer autofeed AFD is an open drain line that provides the printer with an active low signal when continuous form paper is to be autofed to the printer AFD has an internal pullup resistor to Vpp of approximately 10 AO A1 A2 Address The address lines 0 2 select the internal registers during CPU bus operations See Table 2 for the decode of the serial channels and Table 13 for the decode of the parallel printer port Bus buffer BDO is the active high output and is asserted when either the serial channel or the parallel port is read BDO controls the system bus driver 74LS245 or 54LS245 BUSY Line printer busy BUSY is an input line from the printer that goes high when the printer is not ready to accept data 14 1 Clock CLK is the external clock input to the baud rate divisor of each
15. the ACE in addition to the current status of four bits of the MSR These four bits indicate whether the modem inputs have changed since the last reading of the MSR The delta status bits are set when a control input from the modem changes state and are cleared when the CPU reads the MSR The modem input lines are CTS DSR RI and DCD MSR4 MSR7 are status indicators of these lines A set status bit indicates that the input is low A cleared status bit indicates that the input is high When the modem status interrupt in the interrupt enable register is enabled IER3 an interrupt is generated whenever MSR3 is set The MSR is a priority 4 interrupt The contents of the MSR are described in Table 11 Bit0 MSROis the delta clear to send ACTS bit ACTS displays that the CTS input to the serial channel has changed states since it was last read by the CPU Biti MSR1 is the delta data set ready ADSR bit A DSR indicates that the DSR input to the serial channel has changed states since the last time it was read by the CPU Bit2 MSR2is the trailing edge of the ring indicator TERI bit TERI indicates that the RI input to the serial channel has changed states from low to high since the last time it was read by the CPU High to low transitions on RI do not activate TERI 35 TEXAS INSTRUMENTS 30 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLL
16. those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTE 1 All voltage levels are with respect to GND DISSIPATION RATING TABLE TA lt 25 DERATING FACTORS 70 TA 125 C PACKAGE POWER RATING ABOVE TA 25 C POWER RATING POWER RATING 1730 mW 19 2 mW C 865 mW 1689 mW 13 5 mW C 1081 mW t Power ratings assume a maximum junction temperature TJ of 115 C for I and 150 C for M suffix devices Derating factor is the inverse of the junction to ambient thermal resistance RoJA ki TEXAS INSTRUMENTS 6 POST OFFICE BOX 655303 DALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 recommended operating conditions INT NOM Supply voltage Vpp 4 75 5 5 25 Clock high level input voltage 2 VDD Clock low level input voltage Vii CLK suffix Operating free air temperature TA M suffix package thermal characteristics FN Package HV Package PARAMETER TEST CONDITIONS UNIT MIN MIN ReJA Junction to ambient thermal impedance Board mounted no air flow TJ Junction temperature 55 LLL 180 ON electrical characteristics over recommended ranges of operating free air temperature and supply voltage unless otherw
17. 0 ms tod7 Propagation delay time from RD RBR RD LSR J to reset interrupt 4 100 pF 150 ms ipdg Propagation delay time from IOR RD to RXRDY ooo 90 m NOTES 13 These parameters are not production tested 14 The receiver data available indicator the overrun error indicator the trigger level interrupts and the active RXRDY indicator are delayed three RCLK cycles in FIFO mode FCRO 1 After the first byte has been received status indicators PE FE Bl are delayed three RCLK cycles These indicators are updated immediately for any further bytes received after RDRBR goes active There are eight RCLK cycle delays for trigger change level interrupts modem control switching characteristics over recommended ranges of operating free air temperature and supply voltage 100 pF see Note 15 and Figure 14 PARAMETER MAX UNIT ipdg Propagation delay time from IOW WR MCR 710 RTS DTR 1 10 Propagation delay time from modem input CTS DSR JT to interrupt 7 todi1 Propagation delay time from IOR RD MSR f to interrupt 4 ipd12 Propagation delay time from RI 7 to interrupt 7 NOTE 15 These parameters are not production tested 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 9 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 parallel port timing requirements over recommende
18. 16C552A into an idle mode in which all serial data activities are suspended The modem control register and its associated outputs are cleared The line status register is cleared except for the transmitter holding register empty THRE and TEMT bits which are set All functions of the device remain in an idle state until programmed to resume serial data activities RESET has a hysteresis level of typically 400 mV IOR 37 53 Input output read strobe IOR is an active low input that enables the selected channel to output data to the data bus DBO DB7 The data output depends on the register selected by the address inputs AO A1 A2 and chip select Chip select 0 CSO selects ACE 1 chip select 1 CS1 selects ACE 2 and chip select 2 CS2 selects the printer port IOW 36 52 Request to send The RTS outputs are set low by setting MCR1 of its UARTs modem control register Both RTS terminals are reset high by RESET A low on RTS indicates that its ACE has data ready to transmit In half duplex operations RTS controls the direction of the line RXRDYO Receiver ready Receiver direct memory access DMA signaling is also available through this output RXRDY1 One of two types of DMA signaling can be selected using FCR3 when in FIFO mode Only DMA mode 0 is allowed when in TL16C450 mode For signal transfer DMA a transfer is made between CPU bus cycles mode 0 is used Multiple transfers that are made continuously until the receiver FIFO has been
19. 9D NOVEMBER 1994 REVISED JANUARY 1999 MECHANICAL DATA FK S CQCC N LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN NO OF TERMINALS 18 17 16 15 14 13 12 0 358 9 09 0 458 11 63 0 560 14 22 20 28 44 0 560 82 14 22 0 858 idi 21 8 1 063 27 0 26 27 28 1 2 3 4 0 020 0 51 0 080 2 03 0 010 0 25 i 0 064 1 63 0 020 0 51 0 010 0 25 0 055 1 40 0 045 1 14 0 035 0 89 0 028 0 71 P 0 045 1 14 0 022 0 54 0 035 0 89 0 050 1 27 4040140 D 10 96 NOTES A Alllinear dimensions are in inches millimeters B This drawing is subject to change without notice C This package can be hermetically sealed with a metal lid D The terminals gold plated E Falls within JEDEC MS 004 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 37 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 MECHANICAL DATA PN S PQFP G80 PLASTIC QUAD FLATPACK 0 13 NOM 5 9 50 12 20 11 80 50 0 05 14 20 13 80 SQ Seating Plane
20. ALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 transmitter switching characteristics over recommended ranges of operating free air temperature and supply voltage see Note 11 and Figures 6 7 and 8 PARAMETER TEST CONDITIONS MIN UNIT 1085 Delay time interrupt THRE J to SOUT J at start See Figure 6 dren RCLK Delay time SOUT J at start to interrupt THRE T See Note 12 and Figure 6 cycles RCLK Delay time IOW WR THR f to interrupt THRE T See Note 12 and Figure 6 cycles C 100 pF RCLK Delay time SOUT J at start to TXRDY J See Figures 7 and 8 qm 100 pF See Figure 6 100 pF See Figure 6 C 100 pF See Figures 7 and 8 tpd2 Propagation delay time from TOW WR THR J to interrupt THRE 4 ipd4 Propagation delay time from IOR RD IIR 1 to interrupt THRE 1 tpd5 Propagation delay time from IOW WR THR 7 to TXRDY NOTES 11 These parameters are not production tested 12 When the transmitter interrupt delay is active this delay is lengthened by one character time minus the last stop bit time receiver switching characteristics over recommended ranges of operating free air temperature and supply voltage see Note 13 and Figures 9 through 13 PARAMETER TEST CONDITIONS MIN UNIT tag Delay time from stop to INT T See Note 14 a tod6 Propagation delay time from RCLK T to sample CLK P0
21. Bit 0 of a data word is always the first serial data bit received and transmitted The ACE data registers are double buffered TL16C450 mode or FIFO buffered FIFO mode so that read and write operations can be performed when the ACE is performing the parallel to serial or serial to parallel conversion Table 2 Register Selectiont MNEMONIC REGISTER Receiver buffer register read only Transmitter holding register write only Interrupt enable register Interrupt identification register read only FIFO control register write only Line control register Modem control register Line status register Modem status register Scratch pad register LSB divisor latch MSB divisor latch t The serial channel is accessed when either CSO or CS1 is low X irrelevant L low level high level L L L X X X X X X X H pp UD GE Gb IE rr E GE ae gp GE I 35 TEXAS INSTRUMENTS 18 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PRINCIPLES OF OPERATION accessible registers Using the CPU the system programmer has access to and control over any of the ACE registers that are summarized in Table 1 These registers control ACE operations receive data and transmit data Descriptions of these registers follow Tab
22. D RATE DIVISOR N USED TO PERCENT ERROR DIFFERENCE DESIRED GENERATE 16x CLOCK BETWEEN DESIRED AND ACTUAL 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 33 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PRINCIPLES OF OPERATION programmable baud rate generator continued Table 16 Baud Rates Using an 8 MHz Clock BAUD RATE DIVISOR N USED TO PERCENT ERROR DIFFERENCE DESIRED GENERATE 16x CLOCK BETWEEN DESIRED AND ACTUAL 50 75 110 134 5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 128000 256000 512000 50 75 110 134 5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 128000 256000 512000 1000000 35 TEXAS INSTRUMENTS 34 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PRINCIPLES OF OPERATION programming The serial channel of the ACE is programmed by the control registers LCR IER DLL DLM MCR and FCR These control words define the character length number of stop bits parity baud rate and modem interface While the control registers can be written to in any order the IER should be written to last because it controls the interrupt enables Once the serial channel is programmed and operational thes
23. ERATION FIFO control register FCR This write only register is at the same location as the interrupt identification register It enables and clears the FIFOs sets the trigger level of the receiver FIFO and selects the type of DMA signaling Bit 0 FCRO enables both the transmitter and receiver FIFOs All bytes in both FIFOs can be cleared by clearing FCRO Data is cleared automatically from the FIFOs when changing from the FIFO mode to the TL16C450 mode and vice versa Programming of other FCR bits is enabled by setting FCRO Bit1 When set FCR1 clears all bytes in the receiver FIFO and resets the counter This does not clear the shift register Bit 2 When set FCR2 clears all bytes in the transmitter FIFO and resets the counter This does not clear the shift register Bit 3 When set FCR3 changes the RXRDY and TXRDY terminals from mode 0 to mode 1 when FCRO is set Bits 4 and 5 FCR4 and FCR5 are reserved for future use Bits 6 and 7 FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt see Table 4 Table 4 Receiver FIFO Trigger Level FIFO interrupt mode operation The following receiver status occurs when the receiver FIFO and receiver interrupts are enabled 1 LSROis set whena character is transferred from the shift register to the receiver FIFO When the FIFO is empty it is reset IIR 06 receiver line status interrupt has higher priority than the received data available interrupt
24. IFO First Byte Sets RDR Waveforms SIN X Y Stop N Sample CLK Time Out or 119 FIFO at or above Trigger Level see Note A trigger level Interrupt 50 50 FIFO below tpd7 trigger level isi N Interrupt 50 Top Byte of FIFO 50 IOR RD LSR Active 5096 RD RER Active 50 50 Active Previous Byte Read From FIFO NOTE A This is the reading of the last byte in the FIFO Figure 11 Receiver FIFO After First Byte After RDR Set Waveforms 35 TEXAS INSTRUMENTS 14 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION RD BER 50 Active SIN see Note A first byte Stop N Sample CLK 149 w see Note B RXRDY 71 50 50 NOTES A This is the reading of the last byte in the FIFO B If FCRO 1 tg9 RCLK cycles For a time out interrupt tgg 8 RCLK cycles Figure 12 Receiver Ready Mode 0 Waveforms IOR RD RBR 50 Active SIN first byte that reaches S the trigger level top Sample CLK tag see Note B RXRDY 50 50 see Note A NOTES A This is the reading of the last byte in the FIFO B If FCRO 1 tgo cycles For a trigger change level interrupt 199 8 RCLK Figur
25. IIR 04 Receive data available interrupt is issued to the CPU when the programmed trigger level is reached by the FIFO When the FIFO drops below its programmed trigger level it is cleared IIR 04 receive data available indicator also occurs when the FIFO reaches its trigger level It is cleared when the FIFO drops below the programmed trigger level The following receiver FIFO character time out status occurs when receiver FIFO and receiver interrupts are enabled 20 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PRINCIPLES OF OPERATION FIFO interrupt mode operation continued 1 When the following conditions exist a FIFO character time out interrupt occurs a Minimum of one character in FIFO b The last received serial character is longer than four previous continuous character times if two stop bits are programmed the second one is included in the time delay Thelast CPU read of the FIFO is more than four previous continuous character times At 300 baud and 12 bit characters the FIFO time out interrupt causes a latency of 160 ms maximum from received character to interrupt issued 2 Byusingthe RCLK input for a clock signal the character times can be calculated The delay is proportional to the baud rate 3 Thetime outtimer is reset after the CPU reads the
26. S189D NOVEMBER 1994 REVISED JANUARY 1999 PRINCIPLES OF OPERATION modem status register MSR continued Bit 3 MSR3 is the delta data carrier detect ADCD bit ADCD indicates that the DCD input to the serial channel has changed states since the last time it was read by the CPU Bit 4 MSR4 is the clear to send CTS bit CTS is the complement of the CTS input from the modem that indicates to the serial channel that the modem is ready to receive data from SOUT When the serial channel is in the loop mode MCR4 is set MSR4 reflects the value of RTS in the MCR Bit 5 MSR5 is the data set ready DSR bit DSR is the complement of the DSR input from the modem to the serial channel that indicates that the modem is ready to provide received data to the serial channel receiver circuitry When the channel is in loop mode MCR4 is set MSR5 reflects the value of DTR in the MCR Bit 6 MSR 6 is the ring indicator RI bit RI is the complement of the RI input When the channel is in loop mode MCR4 is set MSR6 reflects the value of OUT1 in the MCR Bit 7 MSR7 is the data carrier detect DCD bit Data carrier detect indicates the status of the data carrier detect DCD input When the channel is in loop mode MCR4 is set MSR7 reflects the value of OUT2 in the MCR Reading the MSR register clears the delta modem status indicators but has no effect on the other status bits For LSR and MSR the setting of status bits is inhibited during
27. THR 50 SOUT Data Stop 5096 Start tpd5 tdg gt TXRDY 50 50 N Figure 7 Transmitter Ready Mode 0 Timing Waveforms Interrupt 35 TEXAS INSTRUMENTS 12 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 low WR THR SOUT TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION Byte 16 50 Start of Data Byte 16 tas tpd5 TXRDY 50 FIFO Full UN RCLK CLK TL16C450 Mode SIN receiver input data Sample CLK Interrupt data ready or RCVR ERR IOR Figure 8 Transmitter Ready Mode 1 Timing Waveforms 4 8 CLK Cycles Start Data Bits 5 8 50 50 E i Active 5096 Figure 9 Receiver Timing Waveforms 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION SIN 177 Data Bits 5 8 Parity Stop Sample CLK FIFO at or above Trigger m ae trigger level Interrupt 50 FCR6 7 0 0 FIFO below trigger level IOR o RD RBR 50 X Active 50 50 LSI Interrupt i gt IOR Active RD LSR 50 Figure 10 Receiver F
28. TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 IBM PC AT Compatible Programmable Serial Interface Two TL16C550 ACEs Characteristics for Each Channel 5 6 7 or 8 Bit Characters e Enhanced Bidirectional Printer Port Even Odd or No Parity Bit Generation e 5 5 16 Byte FIFOs Reduce CPU Interrupts and Detection Up to 16 MHz Clock Rate for up to 1 Mbaud 1 1 1 2 or 2 Stop Bit Generation Operation 3 State Outputs Provide TTL Drive for the Transmit Receive Line Status and Data Data and Control Bus on Each Channel Set Interrupts on Each Channel Hardware and Software Compatible With Independently Controlled TL16C452 Individual Modem Control Signals for Each Channel HV or FN PACKAGE TOP VIEW gt gt O Ie a gt Q Exe Six oo alr 5 rc l elc jo lt gt Iu tcc L IL IL LJL 9 7 432 SOUTI 10 INT1 DTR1 11 INT2 RTS1 12 58 SLIN CTS1 13 57 INIT DBO 14 5e AFD 15 55 STB DB2 16 54 GND DB3 17 53 PDO DB4 18 52 PD1 DB5 19 51 PD2 DB6 20 50 PD3 DB7 21 49 PDA TXRDYO 22 48 PD5 Vpp 23 47 PD6 RTSO 24 46 PD7 DTRO 25 45 INTO SOUTO 26 44 BDO __ LLL LL LLL LE 2 8 amp amp lt lne 2 Ele SEBEERB
29. aracters transmitted by the CPU The complete status of each channel of the dual ACE can be read at any time during functional operation by the CPU The information obtained includes the type and condition of the transfer operations being performed and the error conditions encountered In addition to its dual communications interface capabilities the TL16C552A provides the user with a bidirectional parallel data port that fully supports the parallel Centronics type printer interface The parallel port andthe two serial ports provide IBM PC AT compatible computers with a single device to serve the three system ports A programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and 216 1 is included TL16C552A is available in a 68 pin plastic leaded chip carrier FN package a 48 pin TQFP PN package and the 80 pin TQFP PN package The TL16C552AM is available in a 68 pin ceramic quad flat HV package 35 TEXAS INSTRUMENTS 2 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 functional block diagram 28 24 RTSO DSRO 25 STRO DCDO 26 SOUTO RIO 45 INTO SINO 9 RXRDYO 50 22 TXRDYO DBO DB7 CTS1 12 RTS Dsri 2 11 prRi DCD1 10
30. cant bits The status bits are printer busy BSY acknowledge ACK a handshake function paper empty PE printer selected SLCT error ERR and printer interrupt PRINT The read control register allows the state of the control lines to be read The write control register sets the state of the control lines They are direction DIR interrupt enable INT2 EN select in SLIN initialize the printer INIT autofeed the paper AFD and strobe STB which informs the printer of the presence of a valid byte on the parallel bus The write data register allows the microprocessor to write a byte to the parallel bus The parallel port is completely compatible with the parallel port implementation used in the IBM serial parallel adapter Table 12 Parallel Port Registers REGISTER BITS REGISTER REGISTER BIT 7 BIT 6 BIT 5 BIT 4 3 2 1 BIT 0 eaim Por Pos Pm pos Poe e Poo o o sin WT wo se Por Pos Pos Poa Pos Poe Por Poo Wrteconoi o o DIR INT2EN SUN AFD STB Table 13 Parallel Port Register Select os La ft EE Hr ji r r ae IJI rir r a LS D
31. d ranges of supply voltage and operating free air temperature see Note 16 and Figures 15 16 and 17 tsu7 Setup time data valid before STB 4 us the Hold time data valid after STB T us tw6 Pulse duration STB 4 us ig10 Delay time BUSY T to ACK 4 Defined by printer ig11 Delay time BUSY 4 to ACK 4 Defined by printer tw7 Pulse duration BUSY T Defined by printer twe Pulse duration 4 Defined by printer td12 Delay time BUSY after STB T Defined by printer td13 Delay time INT2 4 after ACK J see Note 17 22 ns 1914 Delay time INT2 7 after 7 see Note 17 20 ns 1915 Delay time INT2 7 after 7 see Note 17 24 ns td16 Delay time INT2 J after IOR 7 see Note 17 ns NOTES 16 These parameters are not production tested 17 tg13 tg16 all measured with a 15 pF load PARAMETER MEASUREMENT INFORMATION tw1 CLK XTAL1 EN 0 8 V ae 2 fclock 16 MHz MAX Figure 1 CLK Voltage Waveform 2 54 V Device Under Test TL16C552A 82 T see Note 680 NOTE A This includes scope and jig capacitance Figure 2 Output Load Circuit 35 TEXAS INSTRUMENTS 10 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION TL16C552A Serial Channel 1 Buffers Data Bus
32. e 13 Receiver Ready Mode 1 Waveforms 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 15 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 iow WR MCR INTO 1INT 2 INT IOR RD MSR DATA STB BUSY PARAMETER MEASUREMENT I 5096 4 5 50 NFORMATION 5096 55 tpd9 50 tpd10 4 5 50 Figure 14 Modem Control Timing Waveforms tsu7 lt gt the 50 7 50 50 X 50 4 td10 tati 50 50 X 50 1 12 e tw7 gt Figure 15 Parallel Port Timing Waveforms 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION ENIRG N ACK 50 Jf 50 13 gt 4 4 i ta14 INT2 50 5096 Line Printer Status Register Nt fo Bit 2 PRINT o 4 td int Gas Note A IOR N RD LPS 30 NOTE timing value is not provided for taint in the tables because the line printer status register bit 2 PRINT is an internal signal Figure 16 Parallel Port AT Mode Timing ENIRQ Low Waveforms ENIRQ INT2 50 50 PRINT N IOR N Z o RD LPS 30 Figure 17 Parallel Port PS 2 Mode Timi
33. e mode until initialization A low on RESET causes the following tinitializes the transmitter and receiver clock counters tclears the LSR except for transmitter shift register empty TEMT and transmit holding register empty THRE which are set The MCR is also cleared All of the discrete lines memory elements and miscellaneous logic associated with these register bits are also cleared or turned off The LCR divisor latches receiver buffer register and transmitter holding buffer register are not affected Following the removal of the reset condition RESET high the ACE remains in idle mode until programmed A hardware reset of the ACE sets the THRE and TEMT status bit in the LSR When interrupts are subsequently enabled an interrupt occurs due to THRE A summary of the effect of a reset on the ACE is given in Table 10 28 ki TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PRINCIPLES OF OPERATION master reset continued Table 10 RESET Effects on Registers and Signals REGISTERISIGNAL RESET CONTROL Reset Reset Read RBR Reset Low Read IIR Write THR Reset Low Interrupt modem status changes Read MSR Reset Low OUT2 modem control register MCR The MCR controls the interface with the modem or data set as described in Figure 20 MCR can be writt
34. e registers can be updated any time the ACE serial channel is not transmitting or receiving data receiver Serial asynchronous data is input into SIN The ACE continually searches for a high to low transition from the idle state When the transition is detected a counter is reset and counts the 16x clock to 7 1 2 which is the center of the start bit The start bit is valid if SIN is still low Verifying the start bits prevents the receiver from assembling a false data character due to a low going noise spike on the SIN input The LCR determines the number of data bits in a character LCRO and LCR1 When parity is used LCR3 and the polarity of parity LCR4 is needed Status for the receiver is provided in the LSR When a full character is received including parity and stop bits the data received indicator in LSRO is set The CPU reads the receiver buffer register which clears LSRO If the character is not read prior to a new character transfer from the RSR to the RBR the overrun error status indicator is set in LSR1 If there is a parity error the parity error is set in LSR2 If a stop bit is not detected a framing error indicator is set in LSR3 If the data into SIN is a symmetrical square wave the center of the data cells occurs within 3 125 of the actual center providing an error margin of 46 875956 The start bit can begin as much as one 16x clock cycle prior to being detected scratchpad register The scratch register is an 8 bit r
35. ead write register that has no effect on either channel in the ACE It is intended to be used by the programmer to hold data temporarily 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 35 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 MECHANICAL DATA HV S GQFP F68 CERAMIC QUAD FLATPACK 1 500 38 10 1 300 33 02 SQ 0 025 0 635 0 013 0 330 0 008 0 203 0 400 10 16 TYP E 0 500 12 70 0 485 12 32 p 0 007 0 178 1 _ 0 154 3 912 0 005 0 127 0 134 3 404 SQ 4040072 C 04 96 NOTES A Alllinear dimensions are in inches millimeters B This drawing is subject to change without notice C This package can be hermetically sealed with a ceramic lid using glass frit 35 TEXAS INSTRUMENTS 36 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS18
36. ect 1 0 7 Data Bits 1 128 Data Bits 5 0 1 Stop Bits Stop Bit 1 1 5 Stop Bits if 5 Data Bits Selected Select 2 Stop Bits if 6 7 8 Data Bits Selected 0 z Parity Disabled Ps Pan 1 Parity Enabled Even Parity 0 Odd Parity Select 1 Even Parity 0 Stick Parity Disabled 1 Stick Parity Enabled gt Stick Parity 0 Break Disabled 1 Break Enabled gt Break Control Divisor Latch 0 Access Receiver Buffer Access Bit 1 Access Divisor Latches Figure 19 Line Control Register Contents line printer port The line printer port contains the functionality of the port included in the TL16C452 but offers a hardware programmable extended mode controlled by the printer enhancement mode PE terminal This enhancement is the addition of a direction control bit and an interrupt status bit register 0 line printer data register The line printer LPT port is either output only or bidirectional depending on the state of the extended mode terminal and data direction control bits Compatibility mode PEMD L Reads to the LPT data register and returns the last data that was written to the port Write operations immediately output data to PDO PD7 Extended mode PEMD H Read operations return either the data last written to the LPT data register when the direction bit is cleared or return the data that is present on PDO PD7 when the direction is set to read Write operations t
37. ediately received This allows the processor to verify the transmit and receive data paths of the selected serial channel Interrupt control is fully operational however interrupts are generated by controlling the lower four MCR bits internally Interrupts are not generated by activity on the external terminals represented by those four bits 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 29 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PRINCIPLES OF OPERATION modem control register MCR continued Bits 5 7 MCR5 MCH are permanently cleared Modem Control Register MCR MCR MCR MCR MCR MCR MCR MCR 7 6 5 4 3 2 1 0 Data Terminal 0 DTR Output High inactive Ready 1 DTR Output Low active Request 0 RTS Output High inactive to Send 1 RTS Output Low active Outi No Effect on External Operation internal Out2 0 z External Interrupt Disabled internal 1 External Interrupt Enabled gt Loop 0 Loop Disabled 1 Loop Enabled Bits Cleared Figure 20 Modem Control Register Contents modem status register MSR The MSR provides the CPU with status of the modem input lines from the modem or peripheral devices The MSR allows the CPU to read the serial channel modem signal inputs This is done by accessing the data bus interface of
38. emptied are supported by mode 1 Mode 0 RXRDY is active low in FIFO mode FCRO 1 FCR3 0 or in TL16C450 mode FCRO 0 and the receiver FIFO or receiver holding register contains at least one character When there are no more characters in the FIFO or holding register RXRDY goes inactive high Mode 1 RXRDY goes active low in the FIFO mode FCRO 1 when 1 and the time out or trigger levels have been reached RXRDY goes inactive high when the FIFO or holding register is empty Ring indicator The RI signal is a modem control input Its condition is tested by reading MSR6 RI of each ACE The modem status register output TERI MSR2 indicates whether RI has changed from high to low since the previous reading of the modem status register Serial data SINO and SIN1 move information from the communication line or modem to the TL16C552A receiver circuits Mark is a high state and space is a low state Data on serial data inputs is disabled in loop mode Line printer select SLCT is an input line from the printer that goes high when the printer is selected Line printer select SLIN is an open drain I O that selects the printer when active low SLIN has an internal pullup resistor to Vpp of approximately 10 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 5 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999
39. en to and read from The RTS and DTR outputs are directly controlled by their control bits in this register A high input asserts a low signal active at the output terminals The MCR bits are defined in the following bulleted list JBit0 When is set the output is forced low When MCRO is cleared the DTR output is forced high The DTR output of the serial channel can be input into an inverting line driver in order to obtain the proper polarity input at the modem or data set Bit 1 When is set the RTS output is forced low When MCR1 is cleared the RTS output is forced high The RTS output of the serial channel can be input into an inverting line driver to obtain the proper polarity input at the modem or data set Bit 2 MCR2 has no effect on operation Bit 3 When MCR3 is set the external serial channel interrupt is enabled Bit 4 MCR4 provides a local loopback feature for diagnostic testing of the channel When MCR4 is set SOUT is set to the marking high state and the SIN is disconnected The output of the transmitter shift register is looped back into the receiver shift register input The four modem control inputs CTS DSR DCD and RI are disconnected The modem control outputs RTS OUT1 and OUT2 are internally connected to the four modem control inputs The modem control output terminals are forced to their inactive high state on the TL16C552A In the diagnostic mode data transmitted is imm
40. ghest priority interrupt pending as indicated in Table 5 Bit 3 IIR3 is always cleared in TL16C450 mode This bit is set along with bit 2 in FIFO mode and when a trigger change level interrupt is pending Bits 4 and 5 IIR4 and IIR5 are always cleared Bits 6 and 7 IIR6 and IIR7 are set when FCRO 1 35 TEXAS INSTRUMENTS 22 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PRINCIPLES OF OPERATION line control register LCR The format of the data character is controlled by the LCR The LCR can be read Its contents are described in the following bulleted list and shown in Figure 19 Bits 0 and 1 LCRO and LCR1 are the word length select bits The number of bits in each serial character is programmed as shown Bit 2 LCR2 is the stop bit select bit LCR2 specifies the number of stop bits in each transmitted character The receiver always checks for one stop bit Bit 3 LCR3 is the parity enable bit When LCR3 is set a parity bit between the last data word bit and stop bit is generated and checked Bit 4 LCR4 is the even parity select bit When LCR4 is set even parity is enabled Bit 5 LCR5 is the stick parity bit When parity is enabled LCR3 1 LCR5 1 causes the transmission and reception of a parity bit to be in the opposite state from the value of LCR4 This forces parity to a known state a
41. he receiver buffer register or in the FIFO Bit 1 OE is the overrun error bit An OE indicates that data in the receiver buffer register is not read by the CPU before the next character is transferred into the receiver buffer register overwriting the previous character The OE indicator is cleared whenever the CPU reads the contents of the LSR An overrun error occurs in FIFO mode after the FIFO is full and the next character is completely received The overrun error is detected by the CPU on the first LSR read after it happens The character in the shift register is not transferred to the FIFO but it is overwritten Bit 2 PE is the parity error bit A PE indicates that the received data character does not have the correct parity as selected by LCR3 and LCR4 The PE bit is set upon detection of a parity error and is cleared when the CPU reads the contents of the LSR In FIFO mode the parity error is associated with a particular character in the FIFO LSR2 reflects the error when the character is at the top of the FIFO Bit3 FEisthe framing error bit An FE indicates that the received character does not have a valid stop bit LSR3 is set when the stop bit following the last data bit or parity bit is detected as a zero bit spacing level The FE indicator is cleared when the CPU reads the contents of the LSR In FIFO mode the framing error is associated with a particular character in the FIFO LSR3 reflects the error when the character is at the top
42. ise noted PARAMETER TEST CONDITIONS MAX UNIT 12 mA for PDO PD7 High level output voltage 4 mA for all other outputs see Note 2 IOL 12 mA for PDO PD7 VoL Low level output voltage IOL 12 mA for INIT AFD STB and SLIN 0 4 V loL 4 mA for all other outputs Vpp 5 25 V see Note 3 n Input current All other terminals are floating us p CLK Clock input current V 0 to 5 25 V 2 5 25 V VQ 0 with chip deselected or loz High impedance output current VQ 5 25 V with chip and write mode selected see Note 2 seg pA Vpp 5 25 V No loads on outputs DD Supply current Inputs at0 8 Vor2 V folock 8 MHz d mA NOTES 2 Excluding INIT AFD STB and SLIN They are open drain terminals with an internal pullup resistor to Vpp of approximately 10 KQ 3 Excluding the TRI input terminal It contains an internal pulldown resistor of approximately 5 clock timing requirements over recommended ranges of operating free air temperature and supply voltage OT tw1 Pulse duration CLK T external clock see Figure 1 tw2 Pulse duration CLK 4 external clock see Figure 1 iw3 duration RESET 1000 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 7 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 read cycle timing requirements over
43. ive transition of the ACK signal This bitis set after a read of the status port Bit 3 ERR is the error status bit and corresponds to ERR input Bit 4 SLCT is the select status bit and corresponds to SLCT input Bit 5 PE is the paper empty status bit and corresponds to PE input Bit 6 ACK is the acknowledge status bit corresponds to ACK input Bit 7 BSY is the busy status bit and corresponds to BUSY input active high 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 25 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PRINCIPLES OF OPERATION register 2 line printer control register The line printer control LPC register is a read write port that controls the PDO PD7 direction and drives the printer control lines Write operations set or clear these bits whereas read operations return the state of the last write operation to this register The bits in this register are defined in Table 8 and the following bulleted list Table 8 LPC Register Bit Description BERE HER 7 Reserves Bit0 STB is the printer strobe control bit When STB is set the STB signal is asserted on the LPT interface When STB is cleared the STB signal is negated Bit 1 AFD is the autofeed control bit When AFD is set the AFD signal is asserted on the LPT interface When AFD is cleared the signal is negated Bit 2 INIT
44. le 3 Table 3 Summary of Accessible Registers REGISTER BIT NUMBER ADDRESS REGISTER MNEMONIC 7 BIT6 BIT5 BIT4 Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 s an MSB THR Data Data Data Data write only Bit 7 Bit 6 Bit 5 Bit 4 DLM Bit 13 EDSSI Enable modem status wa Enable interrupt receiver line transmitter received status holding data interrupt register available empty interrupt interrupt Jad 01 FCR Receiver Receiver Reserved write only trigger MSB trigger LSB IR FIFOs FIFOs read only enabledt enabledt interrupt pending DLAB Set Stick EPS PEN STB WLSB1 WLSBO Divisor latch break parity 55 parity ES NS of Tuc pam Word length access bit select stop bits select bit 1 select bit 0 Error in TEMT THRE FE OE receiver Transmitter Transmitter Framing i Overrun empty holding i error error register empty Loop OUT2 Enable OUT1 RTS DTR external an unused Request Data interrupt internal to send terminal INTO or INT1 signal ready RI ADCD TERI ADSR ACTS Data carrier Ring Delta data Trailing edge Delta data Delta clear indicator carrier detect ring indicator set ready clear to send t These bits are always 0 when FIFOs are disabled 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 19 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PRINCIPLES OF OP
45. n the IIR If THRE is the interrupt source indicated in IIR INTRPT is cleared by a read of the IIR Bit 6 TEMT is the transmitter empty bit TEMT is set when the transmitter holding register THR and the transmitter shift register are both empty LSR6 is cleared when a character is loaded into the THR and remains cleared until the character is transferred out of SOUT TEMT is not cleared by a CPU read of the LSR In FIFO mode when both the transmitter FIFO and shift register are empty TEMT is set Bit7 LSR7 is the receiver FIFO error bit The LSR7 bitis always cleared in 16 450 mode In FIFO mode itis set when at least one of the following data errors occurs in the FIFO parity error framing error or break interrupt indicator It is cleared when the CPU reads the LSR if there are no subsequent errors in the FIFO 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 27 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PRINCIPLES OF OPERATION line status register LSR continued NOTE The LSR may be written to However this function is intended only for factory test It should be considered as read only by applications software Table 9 Line Status Register Bits master reset After power up the ACE RESET input should be held low for one microsecond to reset the ACE circuits to an idl
46. nd allows the receiver to check the parity bit in a known state Bit 6 LCR6 is the break control bit When LCR6 is set the serial output SOUT1 SOUTO is forced to the spacing state low The break control bit acts only on the serial output and does not affect the transmitter logic When the following sequence is used no invalid characters are transmitted because of the break Step 1 Load a zero byte in response to the transmitter holding register empty THRE status indicator Step 2 Set the break in response to the next THRE status indicator Step 3 Wait for the transmitter to be idle when transmitter empty status signal is set high TEMT 1 then clear the break when the normal transmission has to be restored Bit 7 LCR7 is the divisor latch access bit DLAB bit LCR7 must be set to access the divisor latches DLL and DLM of the baud rate generator during a read or write operation LCR7 must be cleared to access the receiver buffer register the transmitter holding register or the interrupt enable register 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 23 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PRINCIPLES OF OPERATION line control register LCR continued Line Control Register LCR LCR LCR LCR LCR LCR LCR LCR 7 6 5 4 3 2 1 0 0 0 5 Data Bits Word Length 0 1 26 Data Bits Sel
47. ng ENIRQ High Waveforms RESET 50 50 tw3 Figure 18 RESET Voltage Waveform 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 17 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PRINCIPLES OF OPERATION Three types of information are stored in the internal registers used in the ACE control status and data Mnemonic abbreviations for the internal registers are shown in Table 1 Table 1 Internal Register Mnemonic Abbreviations CONTROL MNEMONIC STATUS MNEMONIC DATA MNEMONIC Line control register LCR Line status register LSR Receiver buffer register RBR FIFO control register FCR Modem status register MSR Transmitter holding register THR Modem contolegiter DwewlenisB S SSS mmprmbemu ER The address read and write inputs are used with the divisor latch access bit DLAB in the line control register bit 7 to select the register to be written to or read from see Table 2 Individual bits within the registers are referred to by the register mnemonic and the bit number in parenthesis As an example LCR7 refers to line control register bit 7 The transmitter holding register and receiver buffer register are data registers that hold from five to eight bits of data If fewer than eight data bits are transmitted data is right justified to the LSB
48. nsmitter holding register empty and modem status The interrupt is cleared on appropriate Service Upon reset the interrupt output is in the high impedance state 35 TEXAS INSTRUMENTS 4 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 Terminal Functions Continued TERMINAL DESCRIPTION NAME Printer port interrupt INT2 is an active high 3 state output generated by the positive transition of ACK INT2 is enabled by bit 4 of the write control register Upon reset INT2 is in the high impedance state Its mode is also controlled by ENIRQ Input output write strobe IOW is an active low input causing data from the data bus to be inputto either ACE orto the parallel port The destination depends on the register selected by the address inputs AO 1 A2 and chip selects CS0 CS1 and CS2 PDO PD7 53 46 72 65 I O Parallel data bits 0 7 PDO PD7 provide a byte wide input or output port to the system Line printer paper empty PE is an input line from the printer that goes high when the printer runs out of paper Printer enhancement mode When low PEMD enables the write data register to the PDO PD7 lines A high on PEMD allows direction control of the PDO PD7 port by the DIR bit in the control register PEMD is usually tied low for the printer operation Reset When low RESET forces the TL
49. o the LPT data register latch data into the output register however they only drive the LPT port when the direction bitis cleared TEXAS INSTRUMENTS 24 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PRINCIPLES OF OPERATION line printer port continued Table 6 summarizes the configuration of the PD port based on the combinations of the logic level on the PEMD terminal and the value of the direction control bit DIR Table 6 Extended Mode and Direction Control Bit Combinations PDO PD7 FUNCTION PC AT mode output PS 2 mode output PS 2 mode input register 1 read line printer status register The line printer status LPS register is a read only register that contains interrupt and printer status of the LPT connector terminals Table 7 in the default column shows the values of each bit after reset in the case of the printer being disconnected from the port Table 7 LPS Register Bit Description DESCRIPTION DEFAULT ME t Outputs are des upon device inputs Bits 0 and 1 LPSO and LPS1 are reserved and always set Bit 2 LPS2 is the printer interrupt PRINT active low status bit When cleared LPS2 indicates that the printer has acknowledged the previous transfer with an ACK handshake if bit 4 of the control register is set The bitis cleared on the active to inact
50. recommended ranges of operating free air temperature and supply voltage see Note 4 and Figure 4 uer tw4 Pulse duration IOR 1 ns tsut Setup time CSx valid before IOR 4 see Note 5 tsu2 Setup time A2 A0 valid before IOR 1 see Note 5 NOTES 4 These parameters are not production tested 5 The internal address strobe is always active 6 In FIFO mode tg1 425 ns min between reads of the receiver FIFO and the status registers interrupt identification register and line status register write cycle timing requirements over recommended ranges of operating free air temperature and supply voltage see Note 7 and Figure 5 tw5 Pulse duration IOW 1 tsu4 Setup time CSx valid before IOW J see Note 8 NOTES 7 These parameters are not production tested 8 The internal address strobe is always active read cycle switching characteristics over recommended ranges of operating free air temperature and supply voltage 100 pF see Note 9 and Figure 4 PARAMETER MIN MAX UNIT tod1 Propagation delay time from IOR J to BDO 7 or from IOR to BDO J tdis Disable time from IOR 7 to DBO DB7 released see Note 10 NOTES 9 These parameters are not production tested 10 VoL and and the external loading determine the charge and discharge time POs ten Enable time from IOR J to DBO DB7 valid see Note 10 60 ms ojs 35 TEXAS INSTRUMENTS 8 POST OFFICE BOX 655303 9 D
51. status register read operations If a status condition is generated during a read operation the status bit is not set until the trailing edge of the read When a status bit is set during a read operation and the same status condition occurs that status bit is cleared at the trailing edge of the read instead of being set again In loop back mode when modem status interrupts are enabled the CTS DSR RI and DCD input terminals are ignored however a modem status interrupt can still be generated by writing to MCR3 MCRO Applications software should not write to the MSR Table 11 Modem Status Register Bits cms wes 7 500 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 31 TL16C552A TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D NOVEMBER 1994 REVISED JANUARY 1999 PRINCIPLES OF OPERATION parallel port registers The TL16C5524 parallel port can connect the device to a Centronic style printer interface When chip select 2 CS2 is low the parallel port is selected Table 12 shows the registers associated with this parallel port The read or write function of the register is controlled by the state of the read IOR and write IOW terminals as shown The read data register allows the microprocessor to read the information on the parallel bus The read status register allows the microprocessor to read the status of the printer in the six most signifi
52. t low by setting MCRO modem control register bit O of its associated ACE DTRx is cleared high by clearing the DTR bit MCRO or whenever a reset occurs When active low DTRx indicates that its ACE is ready to receive data Parallel port interrupt source mode selection When ENIRQ is low the AT mode of interrupts is enabled In AT mode INT2 is internally connected to ACK When ENIRQ is tied high the PS 2 mode of interrupt is enabled and INT2 is internally tied to the inverse of the PRINT bit in the line printer status register INT2 is latched high on the rising edge of ACK INT2 is held until the status register is read which then clears the PRINT status bit and INT2 Line printer error ERR is an input line from the printer The printer reports an error by holding ERR low during the error condition Ground 0 V All terminals must be tied to GND for proper operation Line printer initialize INIT is an open drain line that provides the printer with an active low signal that allows the printer initialization routine to be started INIT has an internal pullup resistor to Vpp of approximately 10 INTO INT1 45 60 64 79 External serial channel interrupt Each serial channel interrupt 3 state output enabled by bit 3 of the MCR goes active high when one of the following interrupts has an active high condition and is enabled by the interrupt enable register of its associated channel receiver error flag received data available tra

TEXAS INSTRUMENTS TL16C552A TL16C552AM handbook

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