ST L6235Q handbook
Contents
1. Figure 2 Pin connection top view u S og 5 2 90 y a BE SR E eee Fs 5 2 48 46 45 44 43 42 41 40 39 38 37 NC a 38 NC OUT 2 ERAD 35 VSA oun 3 34 VSA NC MN E NC Nc 5 32 NC GND 6 31 GND NC 7 30 NC ME 28 NC NC 9 28 NC Nc 39 27 vss NC 3 26 vsB TACHO CR 25 NC 13 14 15 16 dE 18 19 20 21 2o 23 24 ND ge Sp YE FEE LY 3 eee 823833 g DG D Ss a S E AMO02556v1 Note The exposed PAD must be connected to GND pin Table 3 Pin description Pin Name Type Function 43 H1 Sensor input Single ended Hall effect sensor input 1 Open drain Overcurrent detection and thermal protection pin An internal open 44 DIAG ege ut drain transistor pulls to GND when an overcurrent on one of the S high side MOSFETs is detected or during thermal protection Half bridge 1 and half bridge 2 source pin This pin must be 45 46 SENSE Power supply connected together with pin SENSEg to power ground through a sensing power resistor 48 RC RC pin RC network pin A parallel RC network connected between this pin or P and ground sets the current controller OFF time 2 3 OUT1 Power output Output 1 6 31 GND GND Groun2. 1 Le DIAG RpsioN 400 TYP AMO2563v1 Figure 20 shows the overcurrent detection operation The disable time tpisAg g before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs It is affected by both Cgy and Rey values and its magnitude is reported in Figure 21 The delay time tpg Ay before turning off the bridge when an overcurrent has been detected depends only on the Cen value Its magnitude is reported in Figure 22 Cen is also used for providing immunity to pin EN against fast transient noises Therefore the value of Cgy should be chosen as big as possible according to the maximum tolerable delay time and the Rey value should be chosen according to the desired disable time The resistor Rey should be chosen in the range from 2 2 kQ to 180 kQ Recommended values for Rey and Cey are respectively 100 kQ and 5 6 nF which allow to obtain 200 us disable time Doc ID 018997 Rev 2 19 33 L6235Q Circuit description Figure 20 Overcurrent protection waveforms M tEN FALL tocD ON AMO2564v1 Doc ID 018997 Rev 2 20 33 L6235Q Circuit description Figure 21 tpisABLE vs Cen and Ren Vpp 5 V
3. Doc ID 018997 Rev 2 R 220 kQ R 100 kQ 1 10 zm Ren 47 KQ Ren 33 kQ Ren 10 kQ m 100 El ea lt ES S 10 1 1 10 100 Cen nF Figure 22 tpELAY vs Cen Vpp 5 V 10 my X gt 4 E S 0 1 1 10 100 Cen nF 21 33 Circuit description L6235Q 4 8 22 33 Thermal protection In addition to the overcurrent detection the L6235Q integrates a thermal protection to prevent device destruction in case of junction overtemperature It works sensing the die temperature by means of a sensitive element integrated in the die The device switches off when the junction temperature reaches 165 C typ value with 15 C hysteresis typ value Doc ID 018997 Rev 2 ky L6235Q Application information 5 Application information A typical application using L6235Q is shown in Figure 23 Typical component values for the application are shown in Table 7 A high quality ceramic capacitor C2 in the range of 100 to 200 nF should be placed between the power pins VS and VSg and ground near the L6235Q to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching The capacitors Cey connected from the EN input to ground sets the shutdown time when an overcurrent is detected see Section 4 7 The two current sensing inputs SENSE and SENSEp should be connected to the sensing resistors Rsgwse with a trace length as short as possible in the lay
4. AM02572v1 AM02573v1 Figure 27 Normalized typical quiescent Figure 28 Normalized Rps on vs junction current vs switching frequency temperature typical value Iq Iq 1 kHz Ros ow Rps ou 25 C 1 7 18 1 6 15 1 6 1 4 14 1 3 12 1 2 1 1 10 1 07 0 9 0 8 0 20 40 60 80 100 0 20 40 60 80 100 120 140 fsw kHz Tj C AM02574v1 AM02575v1 ky Doc ID 018997 Rev 2 27 33 Electrical characteristics curves L6235Q Figure 29 Typical low side Rpsion VS supply Figure 30 Typical drain source diode forward voltage ON characteristic Roson Q Isp A 0 300 3 0 T Ze 0 296 25 0 292 2 0 0 288 1 5 0 284 1 0 0 280 0 5 0 276 0 0 0 5 10 15 20 25 30 700 800 900 1000 1100 1200 1300 Vs M Vsp mV AM02576v1 AM02577v1 28 33 Doc ID 018997 Rev 2 ky L6235Q Package mechanical data 9 Package mechanical data In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark Table 8 VFQFPN48 7 x 7 x 1 0 mm package mechanical data mm Dim Min Typ Max A 0 80 0 90 1 00 Al 0 02 0 05 A2 0 65 1 00 A3 0 25 0 18 0 23 0 30 D 6 85 7 00 7 15 D2 4 95 5 10 5
5. kyy L6235Q DMOS driver for 3 phase brushless dc motor Features m Operating supply voltage from 8 to 52 V W 5 6A output peak current m Hps on 0 3 Q typ value Ty 25 C m Operating frequency up to 100 kHz m Non dissipative overcurrent protection m Diagnostic output m Constant tore PWM current controller m Slow decay synchronous rectification m 60 and 120 Hall effect decoding logic m Brake function m Tacho output for speed loop m Cross conduction protection m Thermal shutdown m Undervoltage lockout m Integrated fast freewheeling diodes Figure 1 Block diagram QFN 48 7 x 7 mm Description The L6235Q is a DMOS fully integrated 3 phase motor driver with overcurrent protection Realized in BCDmultipower technology the device combines isolated DMOS power transistors with CMOS and bipolar circuits on the same chip The device includes all the circuitry needed to drive a 3 phase BLDC motor including a 3 phase DMOS bridge a constant OFF time PWM current controller and the decoding logic for single ended Hall sensors that generates the required sequence for the power stage Available in QFN48 7x7 package the L6235Q features a non dissipative overcurrent protection on the high side power MOSFETs and thermal shutdown THERMAL PROTECTION OCD1 CH OCD3 H3 Q GATE LOGIC T DECODING LOGIC d TACHO 10V 5V o e g m o Le E Ve gt o oO g
6. FWD REV BRAKE Vu Low level logic input voltage 0 3 0 8 V Vu High level logic input voltage 2 7 V liL Low level logic input current GND logic input voltage 10 pA Ju High level logic input current 7 V logic input voltage 10 pA Vincon Turn on input threshold 1 8 2 0 V VthOrr Turn off input threshold 0 8 1 3 Vi uvs Input threshold hysteresis 0 25 0 5 V Switching characteristics tD onjen Enable to out turn ON delay time I oap 2 5 A resistive load 100 250 400 ns tp oyeN Enable to out turn OFF delay time I oap 2 5 A resistive load 300 550 800 ns D on IN Geer TEEN li oAp 2 5 A resistive load 2 ns D off IN Massen EES li oAp 72 5 A resistive load 2 ns 6 33 Doc ID 018997 Rev 2 ky L6235Q Electrical characteristics Table 4 Electrical characteristics continued Symbol Parameter Test condition Min Typ Max Unit tRISE Output rise time li oAp 72 5 A resistive load 40 250 ns tEALL Output fall time 2 lLoap 2 5 A resistive load 40 250 ns tot Dead time protection 0 5 1 us fcp Charge pump frequency Tj 25 C to 125 C 7 0 6 1 MHz PWM comparator and monostable lhcorr Source current at pin RCorr Vncorr 2 5 V 3 5 55 mA Voffset Offset voltage on sense comparator Vpef 0 5 V 5 mV terop Turn OFF propagation delay 500 ns ae Internal blanking time on SENSE 1 us comparator tonqm
7. Half bridge 3 power supply voltage It must be connected to the Se Ma Power supply supply voltage together with pin VS4 Half bridge 1 and half bridge 2 power supply voltage It must be Se VSA Power supply connected to the supply voltage together with pin VSp 38 39 OUT Power output Output 2 40 VCP Output Charge pump oscillator output 41 Ho Sensor input Single ended Hall effect sensor input 2 42 Ha Sensor input Single ended Hall effect sensor input 3 A Doc ID 018997 Rev 2 5 33 Electrical characteristics L6235Q 3 Electrical characteristics Vs 48 V Ta 25 C unless otherwise specified Table 4 Electrical characteristics Symbol Parameter Test condition Min Typ Max Unit Vem ow Turn on threshold 6 6 7 7 4 V Vaw orr Turn off threshold 5 6 6 6 4 V ls Quiescent supply current i OFF Tj 25 C to 5 10 mA T OFF Thermal shutdown temperature 165 C Output DMOS transistors Tj 25 C 0 34 0 4 High side switch ON resistance Tj 125 c n 0 53 0 59 Ros on Tj 25 C 02810341 Low side switch ON resistance Tj 125 c n 0 47 0 53 EN low OUT Vs 2 mA Ipss Leakage current EN low OUT GND 0 15 mA Source drain diodes Vsp Forward ON voltage Isp 2 5 A EN low 1 15 1 3 V tn Reverse recovery time If22 5A 300 ns te Forward recovery time 200 ns Logic input H1 H2 H3 EN
8. 25 E 6 85 7 00 7 15 E2 4 95 5 10 5 25 e 0 45 0 50 0 55 L 0 30 0 40 0 50 ddd 0 08 Doc ID 018997 Rev 2 29 33 Package mechanical data L6235Q Figure 31 VFQFPN48 7 x 7 x 1 0 mm package outline SEATING PLANE C ES lt L 1 A3 A E2 UUUUUUUUUUUU fe BOTTOM VIEW 30 33 Doc ID 018997 Rev 2 ky L6235Q Order codes 10 Order codes Table 9 Ordering information Order codes L6235Q Package QFN48 7 x 7x 1 0 mm L6235QTR Packaging Tray Tape and reel Doc ID 018997 Rev 2 31 33 Revision history L6235Q 11 32 33 Revision history Table 10 Document revision history Date Revision Changes 30 Jul 2011 1 First release 28 Nov 2011 2 Document moved from preliminary to final datasheet Doc ID 018997 Rev 2 L6235Q Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible
9. PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2011 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 018997 Rev 2 33 33
10. REV BRAKE EN H1 H2 and H3 are TTL CMOS and uC compatible logic inputs The internal structure is shown in Figure 6 Typical value for turn on and turn off thresholds are respectively Vihon 1 8 V and Vuen 1 3 V Pin EN enable may be used to implement overcurrent and thermal protection by connecting it to the open collector DIAG output If the protection and an external disable function are both desired the appropriate connection must be implemented When the external signal is from an open collector output the circuit in Figure 7 may be used For external circuits that are push pull outputs the circuit in Figure 8 may be used The resistor Ren should be chosen in the range from 2 2 kO to 180 kQ Recommended values for Rey and Cen are respectively 100 kQ and 5 6 nF More information for selecting the values can be found in Section 4 7 Figure 6 Logic inputs internal structure ESD PROTECTION ols AMO2560v1 Figure 7 EN pins open collector driving DIAG OPEN COLLECTOR OUTPUT ESD PROTECTION AMO2561v1 Figure 8 EN pins push pull driving PUSH PULL OUTPUT ESD 1 PROTECTION AMO2562v1 10 33 Doc ID 018997 Rev 2 ky L6235Q Circuit description 4 3 PWM current control The L6235Q includes a constant OFF time PWM current controller The current control circuit senses the bridge current by sensing the voltage drop across an external sense resisto
11. S E E o m rs 7 m gt V e Sg o OUT3 fe SENSEs PWM VOLTAGE REGULATOR ONE SHOT MASKING I MONOSTABLE TIME SENSE A VREF COMPARATOR RCOFF AMO2555v1 November 201 1 Doc ID 018997 Rev 2 1 33 www st com Contents L6235Q Contents 1 LE E WEE 3 1 1 Absolute maximum ratings 3 1 2 Recommended operating conditions 3 2 Pin connection DM 4 3 Electrical characteristics 6 4 Circuit description Aa ag EI EES EIER EEN ES 9 4 1 Power stages and charge pump cece eee eee 9 4 2 te leg Tit 4 634026 o2enee8 bBo twee E eta So ep ees RR Lee one 10 4 3 PWM current Control 11 44 Slow decay mode 15 4 5 Decoding logic 260 icie aise ENEE RE R REP EE EE A 15 4 6 RE Lei EE 16 4 7 Non dissipative overcurrent detection and protection 18 4 8 Thermal protection EE unos pedals Rae indu 22 5 Application information eee 23 6 Output current capability and IC power dissipation 25 7 Thermal management eeeeeeeees esses 26 8 Electrical characteristics curves sesssess 27 9 Package mechanical data Leeeee 29 10 Order codes Lois Eeer Eet CR DR Cn ac 31 11 Revision history weg RENERT Re CR cC COCA KEE ee eae 32 2 33 Doc ID 018997 Rev 2 ky L6235Q Electrical
12. an vary maintaining the PWM regulation 100 3 t 10 8 1 5us typ value A III KEE 1 zt 0 1 1 10 100 Coff nF 14 33 Doc ID 018997 Rev 2 ky L6235Q Circuit description 4 4 4 5 Slow decay mode Figure 13 shows the operation of the bridge in slow decay mode during the OFF time At any time only two legs of the 3 phase bridge are active therefore only the two active legs of the bridge are shown in the figure and the third leg is off At the start of the OFF time the lower power MOSFET is switched off and the current recirculates around the upper half of the bridge Since the voltage across the coil is low the current decays slowly After the dead time the upper power MOSFET is operated in the synchronous rectification mode reducing the impedance of the freewheeling diode and the related conducting losses When the monostable times out the upper power MOSFET that was operating the synchronous mode turns off and the lower power MOSFET is turned on again after some delay set by the dead time to prevent cross conduction Figure 13 Slow decay mode output stage configurations BESE A ON TIME B 1us DEAD TIME C SYNCHRONOUS D 1us DEAD TIME RECTIFICATION DO1IN1336 Decoding logic The decoding logic section is a combinatory logic that provides the appr
13. charged before the next time the monostable is triggered Therefore the ON time toy which depends on motors and supply parameters must be bigger than tpcri se to allow a good current regulation by the PWM stage Furthermore the ON time toy can not be smaller than the minimum ON time Loun 12 33 Doc ID 018997 Rev 2 ky L6235Q Circuit description ton gt toN MIN 1 5us typ ton gt tacrise tpt tacrise 600 Corr Figure 12 shows the lower limit for the ON time toy for having a good PWM current regulation capacity It should be mentioned that toy is always bigger than tonmin because the device imposes this condition but it can be smaller than tpcnisg tpr In this last case the device continues to work but the OFF time tore is not more constant Therefore a small Corr value gives more flexibility to the applications allows smaller ON time and therefore higher switching frequency but the smaller the value for Copp the more influential the noises on the circuit performance Figure 11 torr vs Copp and Roff 4 1 10 Ro 100kQ Rot 47kQ 100 toff us 0 1 1 10 100 Coff nF ky Doc ID 018997 Rev 2 13 33 Circuit description L6235Q Figure 12 Area where toy c
14. circuit OCD for full protection With this internal overcurrent detection the external current sense resistor normally used and its associated power dissipation are eliminated Figure 19 shows a simplified schematic of the overcurrent detection circuit To implement the overcurrent detection a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power MOSFET Since this current is a small fraction of the output current there is very little additional power dissipation This current is compared with an internal reference current Inge When the output current reaches the detection threshold typically Isover 5 6 A the OCD comparator signals a fault condition When a fault condition is detected an internal open drain MOSFET with a pull down capability of 4 mA connected to pin DIAG is turned on Pin DIAG can be used to signal the fault condition to a uC or to shut down the 3 phase bridge simply by connecting it to pin EN and adding an external R C see Ren Cen 18 33 Doc ID 018997 Rev 2 ky L6235Q Circuit description Figure 19 Overcurrent protection simplified schematic OUT VS OUT OUT VS HIGH SIDE DMOS HIGH SIDE DMOS HIGH SIDE DMOS POWER SENSE 1 cell POWER SENSE cell POWER SENSE cell POWER DMOS n cells POWER DMOS POWER DMOS n cells i uC or LOGIC n cells TO GATE LOGIC INTERNAL OPEN DRAIN
15. d terminals Open drain Frequency to voltage open drain output Every pulse from pin H4 is 12 TACHO output shaped as a fixed and adjustable length pulse RC network pin A parallel RC network connected between this pin 13 RCPULSE RC pin and ground sets the duration of the monostable pulse used for the frequency to voltage converter 4 33 Doc ID 018997 Rev 2 ky L6235Q Pin connection Table 3 Pin description continued Pin Name Type Function Half bridge 3 source pin This pin must be connected together with 15 16 SENSE Power supply pin SENSE to power ground through a sensing power resistor At this pin also the inverting input of the sense comparator is connected Selects the direction of the rotation High logic level sets forward 17 FWD REV Logic input operation whereas low logic level sets reverse operation If not used it must be connected to GND or 5 V Chip enable Low logic level switches off all power MOSFETs If not 18 EM Logic input used it must be connected to 5 V 19 VREF Logic input Current controller reference voltage Do not leave this pin open or connect to GND Brake input pin Low logic level switches on all high side power 20 BRAKE Logic input MOSFETs implementing the brake function If not used it must be connected to 5 V 21 VBOOT Supply voltage Bootstrap voltage needed for driving the upper power MOSFETs 22 23 OUT3 Power output Output 3
16. data 1 Electrical data 1 1 Absolute maximum ratings Table 1 Absolute maximum ratings Symbol Parameter Parameter Value Unit Vs Supply voltage Vsa Vsp Vs 60 V Differential voltage between Vsa Vss Vg 60 V Vop VSa OUT1 A OUT2A SENSE and VSENSEA VSENSEg 60 V VSp OUT1g OUT2g SENSEg GND Vgoor Bootstrap peak voltage Vsa Vsp Vs Vg 10 V Vin Ven Input and enable voltage range 0 3to 7 V VREF Voltage range at pin VREF 0 3to 7 V Vncorr Voltage range at pin RCofF 0 3to 7 V Voltage range at pins SENSE and V 1 to 4 V SENSE SENSE Pulsed supply current for each Vsa Vsa Vsg Vg 71 A S peak and Vsp pin tPULSE lt 1 ms DC supply current for each VS and 8 uH Is VSg pin VS84 V8g Vs 2 5 A E Tor Storage and operating temperature 40t0 150 C range 1 2 Recommended operating conditions Table 2 Recommended operating conditions Symbol Parameter Parameter Min Max Unit Vs Supply voltage VS4 VSp Vs 8 52 V Differential voltage between VS VSe Va Vop VSa OUT1 OUT2 SENSE and V eR SCH S 52 V VSp OUT1g OUT2p SENSE SENSEA SENSEB Voer Voltage range at pin Ver 0 1 5 V V Voltage range at pins SENSE and Pulsed tw lt tr 6 6 v SENSE SENSEg DC aw louT DC output current VS VSp Vg 25 A Ti Operating junction temperature 25 4125 C fey Switching frequency 100 kHz ky Doc ID 018997 Rev 2 3 33 Pin connection L6235Q 2 Pin connection
17. ematic BLANKING TIME TO GATE MONOSTABLE LOGIC FROM THE LOW SIDE GATE DRIVERS MONOSTABLE SET o DRIVERS DRIVERS DEAD TIME DEAD TIME DEAD TIME E e SENSE COMPARATOR SENSE Corr Doc ID 018997 Rev 2 11 33 Circuit description L6235Q Figure 10 Output current regulation waveforms Jour 4 EE ce ee RsENSE VSENSE 4 Tus tBLANK Tus tBLANK VREF p tenm et ek geet ee 0 Slow Decay Slow Decay Vre 4 tRCRISE tRCRISE Vi L ech E Ee pe ee eee Al eee RCFALL tRCFALL 1us tot Tus tot Orr LSYNCHRONOUS RECTIFICATION DO2IN1351 Bla c ILS A Pa c Pl Figure 11 shows the magnitude of the OFF time torr versus Corr and Rofr values It can be approximately calculated from the equations lacra 0 6 Rorr Corr torr tRcrALL tpr 0 6 Rofe Corr tor where Rofr and Corr are the external component values and tp is the internally generated dead time with 20 kQ lt Rorr lt 100 kQ 0 47 nF lt Corp x 100 nF tpr 1 us typical value therefore toFF MIN 8 6 us torF MAx 6 ms These values allow a sufficient range of torr to implement the drive circuit for most motors The capacitor value chosen for Corr also affects the rise time tacrise of the voltage at the pin Rcorr The rise time tacrise is only an issue if the capacitor is not completely
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19. in Minimum ON time 1 5 2 us torr PWM recirculation time E is Rorr 100 KQ Core 1 nF 61 us ine eee current at pins VREF and 10 uA B Tacho monostable IRcPULsE Source current at pin RCPULSE VRCPULSE 2 5 V 3 5 5 5 mA RpuL 20 KQ Cou 1 nF 12 us tpu_se Monostable of time RpuL 100 KQ Cpyj 1 nF 60 us RtacHo Open drain ON resistance 40 60 Q Over current detection e protection ln mr ede protection 25 C lt Tj lt 125 C An 56 71 A Roppr Open drain ON resistance l 4mA 40 60 Q loH OCD high level leakage current Vpiaa 5 V 1 UA tocp on OCD turn on delay time 4 mA CEN lt 100 pF 200 ns tocp orr OCD turn off delay time Hl 4 mA CEN lt 100 pF 100 ns 1 Tested at 25 C in a restricted range and guaranteed by characterization 2 See Figure 3 3 Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin Ver 4 See Figure 4 Ky Doc ID 018997 Rev 2 7 33 Electrical characteristics L6235Q 8 33 Figure 3 Switching characteristic definition EN Vih ON 9o So Se eet Vi orF F 7777777 N77 louT be ck 90 E 4 nm EE 10 EE SE iac E i f a J 1 t DO1IN1316 1 aT s A BG EE RES i FALL fi fi RISE D OFF EN D ON EN AM02557v1 Figure 4 Overcurrent detection timing definition lout ISOVER VDIAG 90 10 gt toCD ON tocD OFF AM02558v1 Doc ID 018997 Rev 2 d L6235Q Circu
20. it description 4 Circuit description 4 1 Power stages and charge pump The L6235Q integrates a 3 phase bridge which consists of 6 power MOSFETs connected as shown in Figure 1 each power MOSFET has an Rps oy 0 3 Q typical value 25 C with intrinsic fast freewheeling diode Switching patterns are generated by the PWM current controller and the Hall effect sensor decoding logic Chapter 4 3 on page 11 Cross conduction protection is implemented by using a dead time tpr 1 us typical value set by internal timing circuit between the turn off and turn on of two power MOSFETs in one leg of a bridge Pins VS and VSg must be connected together to the supply voltage Vs Using an N channel power MOSFET for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage The bootstrapped supply Vgoor is obtained through an internal oscillator and a few external components to realize a charge pump circuit as shown in Figure 5 The oscillator output pin VCP is a square wave at 600 kHz typically with 10 V amplitude Recommended values part numbers for the charge pump circuit are shown in Table 5 Table 5 Charge pump external component values Component Value CBoor 220 nF Cp 10 nF Rp 100 Q D1 1N4148 D2 1N4148 Figure 5 Charge pump circuit VCP VBOOT VS VSs AMO2559v1 Doc ID 018997 Rev 2 9 33 Circuit description L6235Q 4 2 Logic inputs Pins FWD
21. ng the 60 and the 120 codes it is possible to drive the motor with all four conventions by changing the direction set Doc ID 018997 Rev 2 15 33 Circuit description L6235Q 4 6 16 33 Table 6 60 and 120 electrical degree decoding logic in forward direction Hall 120 1 2 3a 4 5 6a Hall 60 1 2 3b 4 5 6b H1 H H L L L H L H2 L H H H L L L H3 L L L H H H L OUT Vs High Z GND GND GND High Z Vs Vs OUT2 High Z Vs Vs Vs High Z GND GND GND OUTS3 GND GND High Z High Z Vs Vs High Z High Z Phasing 1 3 2 538 2 51 2 21 3 51 3 22 1 22 1 22 Figure 14 o Hs H Tacho The tachometer function consists of a monostable with constant OFF time oun sg whose input is one Hall effect signal H4 It allows to develop an easy speed control loop by using an external op amp as shown in Figure 17 For component values refer to Section 5 The monostable output drives an open drain output pin TACHO At each rising edge of the Hall effect sensors H1 the monostable is triggered and the MOSFET connected to pin TACHO is turned off for a constant time tpyLse see Figure 16 The OFF time tpy sg can be set using the external RC network Dun CpuL connected to the pin RCPULSE Figure 18 gives the relation between tpyj se and Cpu Rpy It is approximately tpuLse 9 6 Reut Cp
22. opriate driving of the 3 phase bridge outputs according to the signals coming from the three Hall sensors that detect rotor position in a 3 phase BLDC motor This novel combinatory logic discriminates between the actual sensor positions for sensors spaced at 60 120 240 and 300 electrical degrees This decoding method allows the implementation of a universal IC without dedicating pins to select the sensor configuration There are eight possible input combinations for three sensor inputs Six combinations are valid for rotor positions with 120 electrical degrees sensor phasing see Figure 14 positions 1 2 3a 4 5 and 6a and six combinations are valid for rotor positions with 60 electrical degrees phasing see Figure 15 positions 1 2 3b 4 5 and 6b Four of them are used in common 1 2 4 and 5 whereas there are two combinations used only in 120 electrical degrees sensor phasing 3a and 6a and two combinations used only in 60 electrical degrees sensor phasing 3b and 6b The decoder can drive motors with different sensor configurations simply by following Table 2 For any input configuration H1 H2 and H3 there is one output configuration OUT OUT and OUT3 The output configuration 3a is the same as 3b and analogously output configuration 6a is the same as 6b The sequence of the Hall codes for 300 electrical degrees phasing is the reverse of 60 and the sequence of the Hall codes for 240 phasing is the reverse of 120 So by decodi
23. out The sense resistors should be non inductive resistors to minimize the di dt transients across the resistor To increase noise immunity unused logic pins are best connected to 5 V high logic level or GND low logic level see Section 2 It is recommended to keep power ground and signal ground separated on the PCB Table 7 Component values for typical application Component Value B 100 uF Co 100 nF C3 220 nF Cgoor 220 nF Corr 1 nF Cpu 10 nF Creri 33 nF CREF2 100 nF CEN 5 6 nF Cp 10 nF D 1N4148 D 1N4148 Ry 5K60 Ro 1K80 R3 4K7Q R4 1 MO Rpp 1KQ Ren 100 kQ Rp 100 Q HsENsE 0 30 Rorr 33 KQ FipuL 47 kO Rp1 Ru Bus 10 kQ Doc ID 018997 Rev 2 23 33 Application information L6235Q Note 24 33 Figure 23 Typical application Vs 8 52Vpc POWER GROUND SIGNAL GROUND FWD REV AMO2566v1 To reduce the IC thermal resistance therefore improving the dissipation path the NC pins can be connected to GND Doc ID 018997 Rev 2 d L6235Q Output current capability and IC power dissipation 6 Output current capability and IC power dissipation Figure 24 shows the approximate relation between the output current and the IC power dissipation using PWM current control For a given output current the power dissipated by the IC can be easily evaluated in order to establish which package should be u
24. r connected between the source of the three lower power MOSFET transistors and ground as shown in Figure 9 As the current in the motor increases the voltage across the sense resistor increases proportionally When the voltage drop across the sense resistor becomes greater than the voltage at the reference input pin Vagg the sense comparator triggers the monostable switching the bridge off The power MOSFET remains off for the time set by the monostable and the motor current recirculates around the upper half of the bridge in slow decay mode as described in Section 4 4 When the monostable times out the bridge again turns on Since the internal dead time used to prevent cross conduction in the bridge delays the turn on of the power MOSFET the effective OFF time torr is the sum of the monostable time plus the dead time Figure 10 shows the typical operating waveforms of the output current the voltage drop across the sensing resistor the pin RC voltage and the status of the bridge More details regarding the synchronous rectification and the output stage configuration are included in Section 4 4 Immediately after the power MOSFET turns on a high peak current flows through the sense resistor due to the reverse recovery of the freewheeling diodes The L6235 provides a 1us blanking time tg Aw that inhibits the comparator output so that the current spike cannot prematurely re trigger the monostable Figure 9 PWM current controller simplified sch
25. sed and how large the onboard copper dissipating area must be to guarantee a safe operating junction temperature 125 C maximum Figure 24 IC power dissipation vs output power 10 8 P W DI A 2 Test Conditions Supply Voltage 24 V a 0 05 1 15 2 25 3 NGAM A 777 fy 30 kHz slow decay ourl AM02570v1 Doc ID 018997 Rev 2 25 33 Thermal management L6235Q 7 Thermal management In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition Selecting the appropriate package and heatsinking configuration for the application is required to maintain the IC within the allowed operating temperature range for the application 26 33 Doc ID 018997 Rev 2 ky L6235Q Electrical characteristics curves 8 Figure 25 Typical quiescent current vs Electrical characteristics curves Figure 26 Typical high side Rps on vs supply supply voltage voltage Iq mA Roson 2 P few 1kHz Tj225C 0 380 0 376 5 4 0 372 0 368 52 0 364 0 360 50 0 356 0 352 0 348 4 8 0 344 0 340 4 6 0 336 0 10 20 30 40 50 60 0 5 10 15 20 25 30 Vs V Vs IV
26. uL Doc ID 018997 Rev 2 ky L6235Q Circuit description where Cou should be chosen in the range 1 nF 100 nF and Bou in the range 20 kQ 100 KQ By connecting the tachometer pin to an external pull up resistor the output signal average value VM is proportional to the frequency of the Hall effect signal and therefore to the motor speed This realizes a simple frequency to voltage converter An op amp configured as an integrator filters the signal and compares it with a reference voltage Ver which sets the speed of the motor tpULSE Vu E el Von Figure 16 Tacho operation waveforms tPULSE I 1 5 Figure 17 Tachometer speed control loop H gt e RCPULSE e TACHO MONOSTABLE Von eeneg Rpur Cou R Rs ji pe TACHO Ly Ka R VREF VREF e e R2 Cneri Doc ID 018997 Rev 2 17 33 Circuit description L6235Q Figure 18 tpuLsE vs CpuL and RpuL 4 1 10 tpulse us Cpul nF 4 7 Non dissipative overcurrent detection and protection The L6235Q integrates an overcurrent detection
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