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ST STM32F205xx STM32F207xx handbook

1. re a5 OO wise dnm NT Ok ug NOt 000000008 00 8 0200 00202 gt gt 858852953925885235899599399 38858888 1 132 2 131 4 3 130 H PH15 PESO 4 129 PH14 5 128 6 127 H 2 PI8 RTC AF2 9 7 126 H Vss 2 PC13 RTC 0 8 125 H Vcap 2 PC14 OSC32 9 124 D 13_ PC15 OSC32_OUT 10 123 E PA12 PISCI 11 122 1 11 12 121 10 11 13 120 9 55 130 14 119 15 118 9 16 117 DO PC8 17 116 B PC7 18 115 19 114 4 0 20 113 B Vas PF5 21 112 D PGS Vss 22 LQFP176 111 ied Vpp 5 23 110 D PG6 PF6r 24 109 1 pas 25 108 5 26 9 27 PG2 PF10Lj 28 PD15 5 INL 29 PD14 PH1 OSC 30 NRSTO 31 Vas 32 PD13 PC1Lj 33 PD12 2 34 PD11 35 PD10 12 36 PD9 55 37 PD8 VreriO 38 PB15 39 14 4
2. AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 L sys TIM1 2 TIM3 4 5 12 1 2 2 2 262 283 USARTI23 VARTA 2 FS OTG HS ETH FC HS DCMI PB14 TIM1_CH2N TIM8_CH2N SPI MISO USART3_RTS TIM12_CH1 OTG_HS_DM EVENTOUT PB15 RTC 50Hz TIM1_CH3N TIM8_CH3N Pra 12 CH2 OTG HS DP EVENTOUT PCO Hs ULPI STP EVENTOUT PCI ETH_MDC EVENTOUT 2 SPI MISO HS ULPI ETH MIL TXD2 EVENTOUT SPI ora Hs NXT ETH MIL EVENTOUT brad 221 PC5 IPM XI EVENTOUT PC6 TIM3 TIMB 252 USART6 TX SDIO D6 DCMI_D0 EVENTOUT PC7 TIM3_CH2 TIM8_CH2 253 USART6_RX SDIO_D7 DCMI_D1 EVENTOUT PC8 TIM3_CH3 TIM8_CH3 USART6_CK SDIO_D0 DCMI_D2 EVENTOUT PC9 MCO2 TIM3 1203 SDA 1282 CKIN 1283 01 EVENTOUT PC10 SEK USART3 TX UART4 TX SDIO_D2 EVENTOUT PCI 888 MISO USARTS RX UART4 RX SDIO 0 EVENTOUT PC12 8 8 sp USARTS UARTS TX SDIO_CK DCMI_D9 EVENTOUT PC13 PC14 OSC32_IN PC15 OSC32 OUT PDO FSMC D2 EVENTOUT PDI TX FSMC D3 EVENTOUT PD TIM3 ETR UARTS_RX DCMLDi EVENTOUT PD3 USART2_CTS FSMC_CLK EVENTOUT PDA USART2_RTS FSMC_NOE EVENTOUT PD5 USART2 TX FSM
3. OSPEEDRy 1 0 bit Symbol Parameter Conditions Min Max Unit value C 30 pF Vpp gt 2 70 V 1009 C 30 pF Vpp gt 1 8 V 50 Fmax 0 out Maximum frequency 4 2 C 10 pF gt 2 70 V 200 10 pF Vpp 18 V 11 Output high to low level fal 20 2 4 lt lt 2 7 TBD Oout time C 10 pF Vpp gt 2 7 V ns Output low to high level rise 20 2 4 Vpp 27V TBD time C 10 pF Vpp gt 2 7 V TBD Pulse width of external signals detected by the EXTI 10 ns controller 1 The I O speed is configured using the OSPEEDRy 1 0 bits Refer to the STM32F20 21xxx reference manual for description of the GPIOx SPEEDR GPIO port output speed register TBD stands for to be defined The maximum frequency is defined in Figure 37 For maximum frequencies above 50 MHz the compensation cell should be used Figure 37 1 AC characteristics definition 90 0 EXTERNAL tr 1O out 3 t 10 out OUTPUT ON 50pF e a Maximum frequency is achieved if t t x 2 3 T and if the duty cycle is 45 55 when loaded by 50pF 14131 100 174 Doc ID 15818 Rev 9 ky STM32F20xxx Electrical characteristics 5 3 17 NRST pin characteristics The NRST pin input driver uses CMOS technology It is connected to a permanent pu
4. 1 97 static characteristics 1 98 Output voltage characteristics 99 AC m 100 Doc ID 15818 Rev 9 5 175 List of tables STM32F20xxx Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 Table 89 Table 90 Table 91 Table 92 Table 93 Table 94 6 175 NRST pin characteristics 102 Characteristics of TIMx connected to the APB1 domain 103 Characteristics of TIMx connected to the APB2 domain 104 2 characteristics TRE ETC TETTE TETTE TE 105 SCL frequency fpc 42 30 MHz Vpp 3 3 106 SPI characteristics 107 areren 110 USB OTG FS startup 112 USB OTG
5. E o O aommommmmamaoooocz lt zs lt gt gt b m 0 B G 64 63 62 61 Be 7 n 53 55 51 50 1 4 VDD 2 PC13 RTC AF1 2 47 H VCAP 2 PC14 OSC32 46 PA13 PC15 OSC32 OUT 45 O PA12 PHO OSC IN 05 44 H PA11 PH1 OSC OUT O 6 43 L1 PA10 NRST 7 42 PCO 41 PC1 9 64 40 H PC9 PC2 10 39 O PC8 141 38 VSSA 12 37 H PC6 13 36 H PB15 PAO WKUP 14 35 H PB14 PA1 15 34 O PB13 PA2 33 L1 PB12 Tou T 2 68 i gt gt S gt 5 31159695 Figure 10 5 32 20 WLCSP64 2 ballout 1 2 3 4 5 6 7 8 9 A VDD 2 B PC13 IRROFF D VSS 3 E NRST E PC1 G H REGOFF PA1 J PA7 4 31184700 1 Doc ID 15818 Rev 9 STM32F20xxx Pinouts and pin description Figure 11 STM32F20x LQFP100 pinout i E
6. 8 2 1 2 4 3 5 4 5 6 13 _ 1 7 PC14 OSC32 INH 8 PC15 OSC32 9 10 11 12 13 14 15 Vss 5 16 pp 5 17 18 19 LQFP144 20 PF9rj 21 PF10rj 22 23 PH1 OSC 24 NRST 25 26 PC1 27 PC2L 28 29 120 30 lt lt 31 VRer O 32 33 PA 0 WKUP O 34 PA10 35 PA20 36 OQ O QW CO sf LO O O O f O GN C f LO O CO CO sP sb SF Sb SF SF F L 10 LO 10 LO 10 LO LO LO LO O O O O O O O O O O LT ULT LT UT UT LT UT LT LT LT LT UT ET LT LT LT LT LT LT UT LT HE ULT LT LTET LTET LT LT ELT LT ELT CT 2022 aud tnn s ai15971d 1 RFU means reserved for future use This can be tied to Vpp Vgg or left unconnected 38 174 Doc ID 15818 Rev 9 STM32F20xxx Pinouts and pin description Figure 13 STM32F20x LQFP176 pinout
7. 162 8 Revision history 164 4 175 Doc ID 15818 Rev 9 157 STM32F20xxx List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 ky Device SUMMAN ws bei eee oe ee eae eda dee ae 1 STM32F205xx features and peripheral 12 STM32F207xx features and peripheral 13 Timer feature 04 27 USART feature comparison 30 STM32F20x and ball definitions 41 FSMC pin definition 52 Alternate function 0 55 Voltage 1 6
8. 0 2 T O gt 0 0 0 09 O gt O gt O gt 0 00 OO 2 1 75 VDD 2 2 74 H VSS 2 4 3 73 VCAP 2 4 72 13 5 71 5 12 6 70 H PA 11 PC13 RTC AF1L 7 69 H PA 10 PC14 OSC32 8 E PA 9 PC15 OSC32 9 67 8 VSS 50 10 66 O PC9 VDD_5 11 65 H PC8 PHO0 OSC 12 64 H 1 5 _ 0 13 LQFP100 6 NRSTq 14 62 O PD15 PCOd 15 61 H PD14 PC1H 16 60 1 PD13 17 59 PD12 18 58 D PD11 VDD_120 19 57 PD10 VSSAr 20 56 H PD9 21 55 H PD8 22 15 23 53 14 PA10 24 52 H PB13 2 25 51 12 90998595985 9 1717 gt gt gt gt ai15970d 1 RFU means reserved for future use This pin can be tied to Vpp Vas or left unconnected ky Doc ID 15818 Rev 9 37 174 Pinouts and pin description STM32F20xxx Figure 12 5 32 20 LQFP144 pinout
9. 8 Alternate function mapping AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 Port AF014 AF15 UARTA 5 CAN1 CAN2 FSMC SDIO svs TIM1 2 TIM3 4 5 2 252 283 2 VARTA CANUGANA FS OTG HS OTO HS DCMI TI PA0 WKUP 5 8 USART2 CTS UART4 TX ETH MIL CRS EVENTOUT PAI TIM2_CH2 TIMS_CH2 USART2 RTS UART4 RX RMII EVENTOUT _ PAZ TIM2_CH3 TIM5 CH3 TIM9 USART2 TX ETH MDIO EVENTOUT TIM2 CHA TIM5 CHA TIM9 USART2_RX HS DO ETH COL EVENTOUT PAA SPI1_NSS 4 88 USART2 CK HS SOF DCML HSYNC EVENTOUT TIM2 8 SPI1 SCK HS ULPI EVENTOUT PAG TIM1_BKIN TIM3 TIM8_BKIN SPI1 MISO TIM13 EVENTOUT DV TIM3_CH2 TIM8_CHIN SPI1_MOSI TIM14_CH1 ETH EVENTOUT CRS DV PAB MCO1 1203_SCL USART1_CK OTG_FS_SOF EVENTOUT 12 3_ USART1_TX DCMI DO EVENTOUT PA10 CH3 USART1_RX OTG_FS_ID DCMI D EVENTOUT PA USART1_CTS CAN FS DM EVENTOUT 12 USART1_RTS CAN1_TX OTG_FS_DP EVENTOUT PA13 JTMS SWDIO EVENTOUT EVENTOUT TIM NSS PAIS JTDI M
10. 1 87 ACC versus temperature 2 88 PLL output clock waveforms in center spread mode 92 PLL output clock waveforms in down spread mode 92 Doc ID 15818 Rev 9 7 75 List of figures STM32F20xxx Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 Figure 76 Figure 77 Figure 78 Figure 79 Figure 80 Figure 81 Figure 82 Figure 83 Figure 84 Figure 85 8 175 AC characteristics definition 101 Recommended NRST pin protection 102 bus AC waveforms and measurement 106 SPI timing diagram slave mode 0 108 SPI timing diagram slave mode and 10 108 SPI timing diagram master mode CT 109 25 slave timing diagram Philips
11. TBD stands for to be defined If IRROFF is set to Vpp this value can be lowered to 1 7 V when the device operates in the 0 to 70 C temperature range It is recommended to maintain the voltage difference between Vpgge and Vppa below 1 8 V Based on characterization not tested in production is internally connected to Vpp4 and is internally connected to Vgga Rapc maximum value is given for 1 8 V and minimum value for 3 3 V cw Beo ge For external triggers a delay of 1 fpc must be added to the latency specified in Table 64 Equation 1 Rajj max formula k 0 5 2 Ranc Rain Na fane X X In 2 The formula above Equation 1 is used to determine the maximum external impedance allowed for an error below 1 4 of LSB 12 from 12 bit resolution and k is the number of sampling periods defined in the 5 1 register 4 Doc ID 15818 Rev 9 117 174 Electrical characteristics STM32F20xxx Note 118 174 Table 65 accuracy 1 Symbol Parameter Test conditions Typ Max Unit ET Total unadjusted error 2 5 EO Offset error feci 60 MHz 21 5 22 5 EG Gain error fapc 30 MHz Rain lt 10 1 5 3 LSB ED Differential linearity error 1 8910 3 6 V 1 2 EL Integral linearity error 1 5 3 Based on characterization not tested in
12. 160 Master clock used to drive the external audio 161 Master clock not used to drive the external audio 161 MII mode using 25 MHz 1 162 with a 50 MHz 162 with a 25 MHz crystal and PHY with 163 Doc ID 15818 Rev 9 9 175 Introduction STM32F20xxx 10 174 Introduction This datasheet provides the description of the STM32F205xx and STM32F207xx lines of microcontrollers For more details on the whole STMicroelectronics STM32 family please refer to Section 2 1 Full compatibility throughout the family The STM32F205xx and STM32F207xx datasheet should be read in conjunction with the STMS2F20x STM32F21x reference manual They will be referred to as STM32F20x devices throughout the document For information on programming erasing and protection of the internal Flash memory please refer to the STM32F20x STM32F21x Flash programming manual 0059 The reference and Flash programming manuals are both available from the STMicroelectronics website www st com For information on the core please refer to the Cortex M3 Technical Reference Manual available from the www arm com website at the following address http infocenter arm
13. 82 High speed external user clock characteristics 83 Low speed external user clock 83 HSE 4 26 MHz oscillator characteristics 85 LSE oscillator characteristics fj sg 32 768 2 86 HSI oscillator characteristics 87 LSI oscillator characteristics 88 Main 88 PLLI2S audio PLL characteristics 89 SSCG parameters 91 Flash memory 92 Flash memory 0 4 93 Flash memory programming with 93 Flash memory endurance and data 94 EMS characteristics des Ede er duse ose es EXE aha 95 EMI 96 ESD absolute maximum 08 96 Electrical sensitivities 97 current injection
14. highest input codes when 3 9 HS Ri cap 5 DAC OUT reaches final value 41 58 Total Harmonic Distortion C lt 50 pF THD _ _ u B LOAD Buffer ON oAp gt 5 Max frequency for a correct Update DAC OUT change when _ _ 1 MS s Ci oap lt 50 pF rate small variation in the input RioAp 2 5 code from code i to i 1LSB Wakeup time from off state Ci oap 50 pF gt 5 twaxeup Setting the ENx bit in the 6 5 10 US code between lowest and DAC Control register highest possible ones Power supply rejection ratio PSRR 2 to VppA static DC 67 40 dB Ci oAD 50 pF measurement 1 If IRROFF is set to Vpp this value can be lowered to 1 7 V when the device operates in the 0 to 70 C temperature range 2 Guaranteed by design not tested in production 3 Guaranteed by characterization not tested in production 122 174 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 54 12 bit buffered non buffered DAC Buffered Non buffered DAC Buffer 1 12 bit digital to analog converter ai17157 1 DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier The buffer can be bypassed by configuring the BOFFx bit in the DAC CR register 5 3 22
15. 104 5 3 20 12 bit ADC characteristics 117 5 3 21 electrical characteristics 122 5 3 22 Temperature sensor characteristics 124 5 3 23 Vpar monitoring characteristics 124 5 3 24 Embedded reference voltage 125 5 3 25 FSMC 125 5 3 26 Camera interface DCMI timing specifications 143 5 3 27 80 5010 MMC card host interface SDIO characteristics 143 5 3 28 RTC characteristics 144 6 Package characteristicS 145 6 1 Package mechanical data 145 6 2 Thermal characteristics 152 7 Part numbering iux xo acm a 6 e dr RR Re RR 153 Appendix Application block diagrams 154 A 1 Main applications versus package 154 A 2 Application example with regulator 155 USB OTG full speed FS interface solutions 156 4 USB OTG high speed HS interface 158 A 5 Complete audio player 159 A Ethernet interface
16. Vpp 2 7 to 8 3 0 to 3 6 V 4 time up to 3 I O and program 3 6 V SLE memory wait tion YP t0 operations p state compensation p works when Vpp 2 7 to 3 0 V 1 number of wait states be reduced by reducing the CPU frequency see Figure 20 If IRROFF is set to Vpp this value can be lowered to 1 7 V when the device operates the 0 to 70 C temperature range Thanks to the ART accelerator and the 128 bit Flash memory the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state program execution 4 The voltage range for OTG USB FS can drop down to 2 7 V However it is degraded between 2 7 and 3 V 66 174 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 20 Number of wait states versus fcpu and Vpp range Number of Wait states Wait states vs and VDD range 0 OO CN KO O xf QN O xt 00 QN CO O st 00 QN CO O t 00 ON ON QV CO sr LO 10 CO O CO OOOO E Fcpu MHz NEUES e 8 1 8 to2 1V 2 1 to 2 4V amp 24102 7V 2 7 to 3 6V ai18748b 1 The supply voltage can drop to 1 7 V when the device operates in the 0 to 70 temperature range and 5 3 2 IRROFF is set to Vpp VCAP1 VCAP2 exter
17. 011 EVENTOUT PE15 TIM1_BKIN FSMC_D12 EVENTOUT PF0 1202 SDA FSMC A0 EVENTOUT 1202 A1 EVENTOUT 2 1262 FSMC EVENTOUT FSMC EVENTOUT PF4 FSMC_A4 EVENTOUT PF5 FSMC_A5 EVENTOUT PF6 TIM10_CH1 FSMC_NIORD EVENTOUT PF7 TIM11_CH1 FSMC_NREG EVENTOUT FSMC EVENTOUT PF9 TIM14 CHI FSMC CD EVENTOUT PF10 FSMC_INTR EVENTOUT PF11 DCMI D12 EVENTOUT PF12 FSMC_A6 EVENTOUT PF13 FSMC_A7 EVENTOUT PF14 FSMC_A8 EVENTOUT uondiosep pue s nouid 5 6 81881 01 90d 21 24 Table 8 Alternate function mapping continued AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 svs TIM1 2 TIM3 4 5 1 i2C1 l2C2 2C3 82 283 VARTA 2 FS OTG HS ETH HS DCMI 15 A9 EVENTOUT FSMC A10 EVENTOUT PG1 FSMC_A11 EVENTOUT PG2 FSMC_A12 EVENTOUT PG3 FSMC_A13 EVENTOUT PG4 FSMC_A14 EVENTOUT PG5 FSMC_A15 EVENTOUT PG6 FSMC_INT2 EVENTOUT PG7 USART6_CK FSMC_INT3 EVENTOUT PG8 USART6_RTS ETH_PPS_OUT EVENTOUT PG9 USART6_RX ESMO NCES EVENTOUT PG10 EVENTOUT FSMC NCE4 2 EVENTOUT PG12 USART6 RTS FSMC NEA EVENTOUT PG13 UART6_CTS
18. 143165 75 10 12 FT 12 EVENTOUT FSMC_D10 TIM1_CH3 44 66 76 N11 PE13 FT PE13 EVENTOUT FSMC_D11 TIM1_CH4 45 67 77 P11 14 FT 14 EVENTOUT FSMC_D12 TIM1_BKIN 46 68 78 11 15 FT 15 EVENTOUT SPI2_SCK 1252 5 12 2 SCL USART3 29 H3 47 69 79 812 10 FT 10 OTG HS ULPI D3 MII ER 2 EVENTOUT 44 174 Doc ID 15818 Rev 9 ky STM32F20xxx Pinouts and pin description Table 6 STM32F20x pin and ball definitions continued Pins a N Main e 315 8 function Alternate functions Other lt gt functions Lo u uu 9 o after reset S S ooon 27 5 12 2 SDA USART3 RX HS ULPI D4 30 J2 48 70 80 R13 11 11 RMII TX EN TX EN CH4 EVENTOUT 31 J3 49 71 81 M10 1 5 1 32 50 72 82 N10 Vp 3 S VDD 1 12 2 SMBA TIM12 83 11 6 10 FT PH6 RXD2 EVENTOUT 12 3 84 N12 7 10 FT PH7 ETH_MII_RXD3 EVENTOUT 12C3_SDA DCMI_HSYNC 85 12 PH8 FT PH8 EVENTOUT 12 3 5 TIM12 2 86 13 PH9 FT PH9 DCMI 00 EVENTOUT 5 DOMI D1 8
19. 65 5 8 1 General operating conditions 65 5 3 2 VCAP1 VCAP2 external capacitor 68 5 3 3 Operating conditions at power up power down regulator ON 69 5 3 4 Operating conditions at power up power down regulator OFF 69 5 3 5 Embedded reset and power control block characteristics 70 5 3 6 Supply current characteristics 71 5 3 7 Wakeup time from low power mode 82 5 3 8 External clock source characteristics 83 5 3 9 Internal clock source characteristics 87 5 3 10 PLL characteristics 88 5 3 11 spread spectrum clock generation SSCG characteristics 91 57 Doc ID 15818 Rev 9 3 175 Contents STM32F20xxx 5 3 12 Memory characteristics 92 5 3 13 characteristics 94 5 3 14 Absolute maximum ratings electrical sensitivity 96 5 3 15 current injection characteristics 97 5 3 16 port characteristics 98 5 3 17 NRST pin characteristics 102 5 318 timer characteristics 103 5 3 19 Communications interfaces
20. 0 3 4 0 Input voltage on five volt tolerant pin 55 0 3 Vpp44 V Input voltage on any other pin Vas 0 3 4 0 IAVppyl Variations between different Vpp power pins 50 IVssx Vssl Variations between all the different ground pins 50 see Section 5 3 14 Electrostatic discharge voltage human body model Ae a sensitivity 1 All main power Vpp Vppa and ground Vss Vssa pins must always be connected to the external power supply in the permitted range 2 maximum value must always be respected Refer to Table 10 for the values of the maximum allowed injected current Doc ID 15818 Rev 9 63 174 Electrical characteristics STM32F20xxx Table 10 Current characteristics Symbol Ratings Max Unit Total current into power lines source 120 lyss Total current out of Vss ground lines sink 120 Output current sunk by any and control 25 Output current source by any I Os and control pin 25 mA 2 Injected current five volt tolerant I O 9 5 0 INPN Injected current on any other pin 25 Total injected current sum of all I O and control 25 1 main power Vppa and ground Vss Vssa pins must always be connected to the external power supply in the permitted range 2 Negative injection disturbs the analog performance of the device See n
21. Table 88 LQFP144 20 x 20 mm 144 low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 21 800 22 000 22 200 0 8583 0 8661 0 874 D1 19 800 20 000 20 200 0 7795 0 7874 0 7953 D3 17 500 0 689 E 21 800 22 000 22 200 0 8583 0 8661 0 8740 E1 19 800 20 000 20 200 0 7795 0 7874 0 7953 E3 17 500 0 6890 0 500 0 0197 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 3 5 TS 0 3 59 7 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits 148 174 Doc ID 15818 Rev 9 STM32F20xxx Package characteristics Figure 82 LQFP176 Low profile quad flat package 24 x 24 x 1 4 mm package outline 1 Drawing is not to scale Seating plane identification 0 25 mm gauge plane L1 1T ME Table 89 LQFP176 Low profile quad flat package 24 x 24 x 1 4 mm package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 Al 0 050 0 150 0 0020 0 0059 A2 1 350 1 450 0 0531 0 0571 b 0 170 0 270 0 0067 0 0106 0 090 0 200
22. Typ 5 T 25 85 105 120 2 61 81 93 90 2 48 68 80 60 2 33 53 65 30 2 18 38 50 External all peripherals enabled 25 MHz 14 34 46 16 MHz 10 30 42 8 2 6 26 38 120 2 33 54 66 90 2 27 47 59 60 2 19 39 51 External all peripherals disabled 25 MHz 8 28 41 16 MHz 6 26 38 8MHz 4 24 36 1 Based on characterization tested in production at max and fck max with peripherals enabled External clock is 4 MHz and is on when fuc gt 25 MHz When the ADC is on ADON bit set in the CR2 register add an additional power consumption of 1 6 mA per ADC for the analog part 4 Inthis case HCLK system clock 2 4 Doc ID 15818 Rev 9 71 174 Electrical characteristics STM32F20xxx Table 19 Typical and maximum current consumption Run mode code with data processing running from Flash memory ART accelerator enabled or RAM 0 Typ Max Symbol Parameter Conditions fucik ns ns Unit 25 C 85 105 C 120 MHz 49 63 72 90 MHz 38 51 61 60 MHz 26 39 49 30 2 14 27 37 3 External clock m 25 MHz 11 24 34 peripherals enabled 16 MHz 8 21 30 8 MHz 17 27 4 MHz 16 26 Supply current in 2 MHz 2 15 25 120 2
23. Value Parameter Symbol Unit Min Max Control in ULPI_DIR setup time 2 0 Control setup time 1 5 Control DIR hold time tuc Data in setup time tsp 2 0 ns Data in hold time tup 0 Control out STP setup time and hold time tpc 9 2 Data out available from clock rising edge tpp 10 7 1 Vpp 2 7 V to 3 6 V and T4 40 to 85 C Ethernet characteristics Table 60 shows the Ethernet operating voltage Table 60 Ethernet DC electrical characteristics Symbol Parameter Min Unit Input level Ethernet operating voltage 2 7 3 6 V 1 Allthe voltages are measured from the local ground potential Table 61 gives the list of Ethernet MAC signals for the SMI station management interface and Figure 47 shows the corresponding timing diagram Doc ID 15818 Rev 9 113 174 Electrical characteristics STM32F20xxx 114 174 Figure 47 Ethernet SMI timing diagram ETH_MDC MDIO I 15666 Table 61 Dynamics characteristics Ethernet MAC signals for SMI Symbol Rating Min Typ Max Unit cycle time 2 38 MHz AHB 60MHz 411 420 425 ns write data valid time 6 10 13 ns Read data setup time TBD TBD TBD ns Read data hold time TBD TBD TBD ns 1 TBD stands for
24. 1 and inputs are available only on 100 pin packages 3 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics 5 3 21 DAC electrical characteristics Table 66 DAC characteristics Symbol Parameter Min Typ Max Unit Comments Analog supply voltage 1 8 3 6 V VREF Reference supply voltage 1 80 3 6 VREF lt VppA VssA Ground 0 0 V Resistive load with buffer ON 5 When the buffer is OFF the Impedance output with buffer _ 15 Minimum resistive load between 9 OFF DAC_OUT and Vss to have a 1 accuracy is 1 5 Maximum capacitive load at CioAp Capacitive load 5 50 pF DAC OUT when the buffer is ON It gives the maximum output DA Lower DAC OUT voltage 02 _ _ v excursion of the DAC DUMET ON It corresponds to 12 bit input code 0x0E0 to OxF1 C at VREF DAC_OUT Higher DAC_OUT voltage _ Vana 0 2 3 6 and 0x1C7 to 8 at max with buffer ON 1 8 V DAC OUT Lower DAC OUT voltage ith buffer Lr i min It gives the maximum output DAC OUT Higher DAC OUT voltage _ NES II max with buffer OFF Hebr With no load worst code 0x800 170 240 at Vref 3 6 V in terms DC DAC DC Vggr current consumption on the inputs lvner 9 consumption in quiescent mode Standby mode Wit
25. ER EVENTOUT PI HS ULPI DIR EVENTOUT uondiosep uid pue sjnouid 0242 61115 STM32F20xxx Memory mapping 4 Memory mapping The memory map is shown in Figure 15 ky Doc ID 15818 Rev 9 59 174 Memory mapping STM32F20xxx Figure 15 Memory map OxFFFF FFFF E2 byte block 7 Cortex M3 s internal 0 000 0000 peripherals OxDFFF FFFF 512 Mbyte block 6 Not used 0 000 0000 OxBFFF FFFF 512 Mbyte block 5 IFSMC registers 0 000 0000 Ox9FFF FFFF 512 Mbyte block 4 FSMC bank 3 amp bank4 512 Mbyte block 3 FSMC bank1 amp bank2 0x8000 0000 Ox7FFF FFFF 0x6000 0000 Ox5FFF FFFF 512 Mbyte block 2 Peripherals 0 4000 0000 Ox3FFF FFFF 512 Mbyte block 1 SRAM 0x2002 0000 Reserved SRAM 16 KB aliased by bit banding SRAM 112 KB aliased by bit banding 0x2001 C000 0x2001 FFFF 02000 0000 0 8000 0000 0x2001 BFFF 512 Mbyte block 0 Code OxiFFF C008 0x1FFF Option Bytes Ox1FFF C000 Ox1FFF C007 0 0000 0000 Reserved Ox1FFF 7A10 OXAFFF 7FFF System memory 0x1FFF 0000 Ox1FFF 7 Reserved 0x0810 0000 OXOFFF Flash 0x0800 0000 0x080F FFFF Reserved 0 0001 C000 Ox07FF Aliased to Flash system memory or SRAM depending 0x0000 0000 0x000F FFFF on the BOOT pins Reserved FSMC control register FS
26. CH4 11 CH1 62 A7 96 140 168 B4 9 FT PB9 SDIO_D5 DCMI_D7 l2C1 SDA CAN1 TX EVENTOUT NBLO 97 141 169 4 FT PEO D2 EVENTOUT FSMC_NBL1 D3 98 142 170 PE1 FT PE1 EVENTOUT T D5 Vss 5 Vas 631081 Vss 5 99 143 171 C6 9 64 09 110011441172 C5 Vpp 3 S Vpp 3 50 174 Doc ID 15818 Rev 9 ky STM32F20xxx Pinouts and pin description Table 6 STM32F20x pin and ball definitions continued Pins 2 amp E 9 2 2 8 9 function Alternate functions 6 amp gt functions Lo u uu 9 o after reset SS s 8 8 gt 5 1 1 173 a 8 174 PI5 DCMI_VSYNC EVENTOUT SEE Pl6 VO FT 58008 PI7 IRROFF TS IRROFF NW input output S supply HiZ high impedance FT 5 V tolerant 3 6 V tolerant Function availability depends on the chosen device PC13 PC14 PC15 and 8 are supplied through the power switch Since the switch only sinks a limited amount of current 3 the use of GPIOs 1 to PC15 PI8 in ou
27. 05 133 Synchronous non multiplexed PSRAM write 05 134 PC Card CompactFlash controller waveforms for common memory read access 135 PC Card CompactFlash controller waveforms for common memory write access 136 PC Card CompactFlash controller waveforms for attribute memory read Eie pP T 137 PC Card CompactFlash controller waveforms for attribute memory write rie c 138 PC Card CompactFlash controller waveforms for I O space read access 138 PC Card CompactFlash controller waveforms for I O space write access 139 controller waveforms for read access 141 controller waveforms for write 141 controller waveforms for common memory read 142 controller waveforms for common memory write 142 SDIO high speed mode 143 SD default 144 LQFP64 10 10 mm 64 pin low profile quad flat package outline 146 Recommended footprint MEM 146 WLCSP64 2 0 400 mm pitch wafer level chip size package outline 147 LQFP100 14 x 14 mm 100 pin low profile quad flat package outline 148 Recommended footprint dtd anii te eic fona ac eh
28. 15 21 5 6 FSMC A5 EVENTOUT ADC3 IN15 H9 10 16 22 G2 Vss 5 S Vss 5 1 111117123 G3 5 5 5 10 CH1 18 24 K2 6 FSMC NIORD IN4 EVENTOUT BUM 6 TIM11 CH1 FSMC NREG 19 25 FT 7 ADC3 1 5 TIM13 1 1 1 120 26 13 PFa 9 FT PF8 NIOWR ADC3 IN6 EVENTOUT 6 14 FSMC_CD 21 27 12 9 VO 9 EVENTOUF ADC3 1 7 221 28 L1 PF10 9 10 FSMC INTR EVENTOUT ADC3 IN8 9 12 23 29 61 5 I O FT OSC IN 6 13 24 30 H1 1 05 OUT PH1 EVENTOUT OSC OUT ky Doc ID 15818 Rev 9 41 174 Pinouts and pin description STM32F20xxx Table 6 STM32F20x and ball definitions continued Pins N e 315 8 function Alternate functions Other lt functions Lo iw uu 9 o after reset S S ooon 5 7 8 14 25 31 J1 5 NRST 6 OTG HS ULPI STP ADC123 8 69 15 26 32 2 FT NAO 9 F8 16 27 33 10 PC1 ETH MDC EVENTOUT i SPI2_MISO 6 HS ADC123 10 07 17 28 34 4 2 2 ETH TXD2 INS EVENTOUT S
29. 51515 FT PE6 TIM9_CH2 DCMI_D7 EVENTOUT 1 14916 6 6 Ct VBAT S VBAT 40 174 Doc ID 15818 Rev 9 STM32F20xxx Pinouts and pin description Table 6 STM32F20x pin and ball definitions continued Pins a N Main t e 315 e 5 Pin name 8 function Alternate functions Other lt gt functions Lo u uu o o after reset S S ooo a 5 7 02 Plg9 EVENTOUT RTC AF2 8 7 17 8 D1 PC13 9 136 EVENTOUT RTC AF1 9 8 8 E1 14 05 32 146 05632 IN 4 9 9 9 10 F1 15 9 15 EVENTOUT OSC32 OUT OSC32_OUT x 1 1 141 03 9 10 FT 9 EVENTOUT 121 VO 10 OTG HS DIR 13 E4 11 VO PI11 140 F2 Vss 13 S Vss 13 15 Vpp 13 Vpp 13 FSMC 0 12 2 SDA 10 16 E2 VO FT PFO 1 12 2 SCL 1 1 111117 PF1 VO FT PF1 EVENTOUT FSMC A2 I2C2 SMBA 12 18 H2 2 VO FT PF2 13 19 J2 PF3 FSMC A3 EVENTOUT IN9 14 20 43 FT 4 FSMC A4 EVENTOUT ADC3 IN14
30. Electrical characteristics STM32F20xxx 5 3 18 102 174 TIM timer characteristics The parameters given in Table 48 and Table 49 are guaranteed by design Refer to Section 5 3 16 I O port characteristics for details on the input output alternate function characteristics output compare input capture external clock PWM output Table 48 Characteristics of TIMx connected to the APB1 domain Symbol Parameter Conditions Min Max Unit AHB APB1 1 trIMxCLK prescaler distinct from 1 ftimxcLkK 167 Timer resolution time 60 MHz AHB APB1 1 trIMxCLK prescaler 1 ftimxcLk 30 MHz 33 3 ns ses Timer external clock 0 2 2 frequency to CH4 0 30 MHz Restim Timer resolution 16 32 bit 16 bit counter clock period 1 65536 trIMxCLK when internal clock is f 60 MHz selected 0 0167 1092 us tcounteR APB1 30 MHz 32 bit counter clock period 1 trIMxCLK when internal clock is selected 0 0167 71582788 us 65536 x 65536 trIMxCLK Maximum possible count 71 6 s 1 TIMx is used as a general term to refer to the TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 and TIM12 timers Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Table 49 Characteristics of TIMx connected to the APB2 domain Sy
31. 84 174 Table 28 HSE 4 26 MHz oscillator characteristics 2 Symbol Parameter Conditions Min Typ Max Unit fosc Oscillator frequency 4 26 MHz Feedback resistor 200 Vpp 3 3 V ESR 30 0 449 1 C 5 pF 25 MHz Ipp HSE current consumption Vpp 3 3 V ESR 300 532 C 210 pF 925 MHz Om Oscillator transconductance Startup 5 mA V tsu use Startup time Vpp is stabilized 2 ms 1 Resonator characteristics given by the crystal ceramic resonator manufacturer Based on characterization not tested in production tsu HSE is the startup time measured from the moment it is enabled by software to a stabilized 8 MHz oscillation is reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For and 2 it is recommended to use high quality external ceramic capacitors in the 5 pF to 25 pF range typ designed for high frequency applications and selected to match the requirements of the crystal or resonator see Figure 31 C 4 and C are usually the same size The crystal manufacturer typically specifies a load capacitance which is the series combination of C and gt PCB and MCU pin capacitance must be included 10 pF can be used as a rough estimate of the combined pin and board capacitance when sizing C 4 and 2 Refer to the application note AN2867 Oscillator des
32. STM32F20xxx Pinouts and pin description Table 6 STM32F20x pin and ball definitions continued Pins q 9 e 2 e S R Pin name 9 function Alternate functions rner gt functions F after reset S S ooon 55 5 54 7 83 116 144 012 PD2 FT PD2 SDIO_CMD DCMI_D11 EVENTOUT FSMC_CLK USART2_CTS 84 117145 011 PD3 FT PD3 EVENTOUT FSMC_NOE USART2_RTS 85 118 146 510 PD4 FT PD4 7 EVENTOUT FSMC_NWE USART2_TX 86 119147 11 PD5 FT PD5 EVENTOUT 120148 5 Vss 10 121149 VDD 40 S 5 87 1221150 B11 PD6 FT PD6 USART2 RX EVENTOUT USART2 CK FSMC 1 188 123 1151 A11 PD7 FT PD7 FSMC NCE2 EVENTOUT USART6 124152 C10 PG9 PG9 NE2 FSMC EVENTOUT FSMC 1 125 153 B10 PG10 FT PG10 FSMC NE3 EVENTOUT FSMC 4 2 ETH MII TX EN 26 154 PG11 FT PG11 ETH TX EVENTOUT FSMC NE4 127 155 B8 PG12 FT PG12 USART6_RTS EVENTOUT 5 24 USART6 CTS 128156 8 PG13 13 ETH 0 ETH_RMII_TXDO EVENTOUT FSMC_A25 USART6_TX ETH_MII_TXD1 429 157 A7 PG14 FT PG14
33. Vss 0 Q resistor or soldering bridge present for the STM32F10xx configuration not present in the STMS2F2xx configuration ai15962b Doc ID 15818 Rev 9 15 174 Description STM32F20xxx 16 174 Figure 2 Compatible board design between STM32F10xx and STM32F2xx for LQFP100 package 0 resistor or soldering bridge present for the STM32F10xx configuration not present in the STM32F2xx configuration Vss Two 0 resistors connected to VDDVss Vss for STM32F10xx Vos for the STM32F10xx Vpp for STM32F2xx Vpp Vss or NC for the STM32F2xx ai15961c Figure 3 Compatible board design between STM32F10xx and STM32F2xx for LQFP144 package 109 0 Q resistor or soldering bridge present for the STM32F10xx configuration not present in the 143 RFU STM32F2xx configuration Vss Two 0 Q resistors connected to L Vgg for the STM32F10xx VDD vss Vss or NC for the STM32F2xx ai15960c 1 reserved for future use Doc ID 15818 Rev 9 STM32F20xxx Description Figure 4 Compatible board design between STM32F10xx and STM32F2xx for LQFP176 package 132 89 133 88 171 RFU 176 45 1 44 VDD Vss Two 0 resistors connected to Ves for the STM32F10xx Vpp Vss or NC for the STM32F2xx MS19925V1 1 RFU reserved for future use Doc ID 15818 Rev 9 17 174 Description STM32
34. after reset S S ooon l 5 USART2 5 4 9 2 2 17 67 26 37 47 R2 OTG HS ADC123 IN3 EVENTOUT 18 27 38 48 Vss 4 5 Vss 4 H7 L4 REGOFF REGOFF 19 1 28 39 49 4 5 4 SPI1 5 5 58 USART2 CK ADC12_IN4 20 J8 29 40 50 N4 40 VO TT PA4 DCMI_HSYNC GUT OTG HS SOF I2S3 WS EVENTOUT SPI1_SCK 6 OTG_HS_ULPI_CK ADC12 IN5 21 6 30 41 51 PA5 TT PA5 2 CH1 ETRY DAC2 OUT TIM8 CHIN EVENTOUT SPI1_MISO 6 TIM8 22 H5 31 42 52 FT PA6 PIXCLK TIM3 ADC12 ING TIM1 BKIN EVENTOUT SPI1 MOSI 8 CH1N TIM14 TIM3 CH2 23 7 32 43 53 PA7 9 7 _ _ _ ADC12_IN7 TIM1_CH1N CRS DV EVENTOUT ETH RMII D0 24 33 44 54 5 40 4 ETH DO ADC12_IN14 EVENTOUT ETH D1 25 23 34 45 55 PC5 9 FT PC5 D1 ADC12_IN15 EVENTOUT TIM3_CH3 TIM8_CH2N 6 OTG HS ULPI D1 26 6 35 46 56 R5 FT PBO ETH RXD2 ADC12_IN8 TIM1_CH2N EVENTOUT TIM3_CH4 TIM8_CH3N 6 OTG_HS_ULPI_D2 27 J5 36 47 57 FT PB1 ETH RXD3 ADC12 IN9
35. ai16042 1 125 is the 125 serial clock to the external audio DAC not to be confused with 125 CK Doc ID 15818 Rev 9 160 174 STM32F20xxx Application block diagrams A 6 Ethernet interface solutions Figure 96 MII mode using a 25 MHz crystal Ethernet MAC 10 100 HCLK 1 IEEE1588 PTP Timer input trigger Timestamp comparator STM32 TX TX EN TXD 3 0 CRS MII COL 0 RX DV ER MDIO MDC PPS our 2 Ethernet PHY 10 100 MDC 17 519968 1 1 must greater than 25 MHz 2 Pulse per second when using IEEE1588 PTP optional signal Figure 97 RMII with a 50 MHz oscillator HCLK 1 Timer input trigger 2 or 20 2 5 or 25 MHz synchronous 50 MHz STM32 RMII TX EN Ethernet MAC 10 100 TXD 1 0 RMII_RXD 1 0 RMII_CRX_DV IEEE1588 PTP RMII_REF_CLK Timestamp comparator 50MHz XT1 Ethernet PHY 10 100 RMII 7 pins RMII MDC 9 pins 50 MHz MS19971V1 1 must be greater than 25 MHz Doc ID 15818 Rev 9 161 174 Application block diagrams STM32F20xxx 162 174 Figure 98 with a 25 MHz crystal and PHY with PLL STM32F RMII TX EN Ethernet TX
36. and timers are based on a 16 bit auto reload up downcounter and a 16 bit prescaler They all feature 4 independent channels for input capture output compare PWM or one pulse mode output This gives up to 16 input capture output compare PWMs on the largest packages The 2 5 general purpose timers can work together or with the other general purpose timers and the advanced control timers TIM1 and 8 the Timer Link feature for synchronization or event chaining The counters of TIM2 TIM3 TIM4 TIM5 be frozen in debug mode Any of these general purpose timers can be used to generate PWM outputs TIM2 TIM3 5 all have independent DMA request generation They are capable of handling quadrature incremental encoder signals and the digital outputs from 1 to 4 hall effect sensors e TIM10 TIM11 and TIM9 These timers are based on a 16 bit auto reload upcounter and a 16 bit prescaler 10 and TIM11 feature one independent channel whereas 9 has two independent channels for input capture output compare PWM or one pulse mode output They can be synchronized with the TIM2 TIM3 TIMB full featured general purpose timers They can also be used as simple time bases e TIM12 TIM13 and TIM14 These timers are based on a 16 bit auto reload upcounter and a 16 bit prescaler TIM13 and TIM14 feature one independent channel whereas TIM12 has two independent channels
37. Added WLCSP66 64 2 package Added note 1 related to LQFP176 on cover page Added trademark for ART accelerator Updated Section 2 2 2 Adaptive real time memory accelerator ART Accelerator Updated Figure 6 Multi AHB matrix Added case of BOR inactivation using IRROFF on WLCSP devices in Section 2 2 15 Power supply supervisor Reworked Section 2 2 16 Voltage regulator to clarify regulator off modes Renamed PDROFF IRROFF in the whole document Added Section 2 2 19 operation Updated LIN and IrDA features for UART4 5 in Table 5 USART feature comparison Table 6 STM32F20x ball definitions Modified and added note related to the NL pin renamed BYPASS REG REGOFF and add IRROFF pin renamed USART4 5 UART4 5 USARTA pins renamed UARTA Changed Vgg sa to Vss and Vpp sa pin reserved for future use Updated maximum HSE crystal frequency to 26 MHz Section 5 2 Absolute maximum ratings Updated minimum and maximum values and note related to five volt tolerant inputs in Table 9 Voltage characteristics Updated li maximum values and related notes in Table 10 Current characteristics Updated minimum value in Table 12 General operating conditions Added Note 2 and updated Maximum CPU frequency in Table 13 Limitations depending on the operating power supply range and added Figure 20 Number of wait states versus and Vpp range Added brownout level
38. H tsu SDA gt h STA 4 9 lt Ih SDA tw SCLH 34 i SCL PH 8 04 1 5 1 Isu STO ai14979b 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7Vpp Table51 SCL frequency fpc 30 MHz Vpp 3 3 v 2 2 value Rp 4 7 kQ 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012C 20 OxO2EE 1 Rp External pull up resistance fsc speed 2 For speeds around 200 kHz the tolerance on the achieved speed is of 5 For other speed ranges the tolerance on the achieved speed 2 These variations depend on the accuracy of the external components used to design the application Doc ID 15818 Rev 9 105 174 Electrical characteristics STM32F20xxx 106 174 126 SPI interface characteristics Unless otherwise specified the parameters given in Table 52 for SPI or in Table 53 for 25 derived from tests performed under the ambient temperature fpc frequency and Vpp supply voltage conditions summarized in Table 12 Refer to Section 5 3 16 port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO for SPI and WS SD for 125 Table 52 SPI characteristics Symbol Parameter Conditions Min Max Unit f Master mode z 30 SCK SPI clock frequency MHz Slave mode 30 Misery
39. 0x4003 FFFF 0 4002 8000 0x4002 93FF 0 4002 6800 0x4002 7FFF 0 4002 6400 0x4002 67FF 0 4002 6000 0x4002 63FF 0 4002 5000 0 4002 0 4002 4000 0x4002 4FFF 0 4002 3 00 0x4002 3FFF 0 4002 3800 0x4002 0 4002 3400 0x4002 37FF 0 4002 3000 0x4002 33FF 0 4002 2400 0x4002 2FFF 0 4002 2000 0x4002 23FF 0 4002 1 00 0x4002 1FFF 0 4002 1800 0x4002 1BFF 0 4002 1400 0x4002 17FF 0 4002 1000 0x4002 13FF 0 4002 0x4002 OFFF 0 4002 0800 0 4002 OBFF 0 4002 0400 0x4002 07FF 0 4002 0000 0x4002 0 4001 4 00 0x4001 FFFF 0 4001 4800 0x4001 4BFF 0 4001 4400 0x4001 47FF 0 4001 4000 0x4001 43FF 0 4001 3 00 0x4001 3FFF 0 4001 3800 0x4001 0 4001 3400 0x4001 37FF 0 4001 3000 0x4001 33FF 0 4001 2 00 0x4001 2FFF 0 4001 2800 0x4001 2BFF 0 4001 2400 0x4001 27FF 0 4001 2000 0x4001 23FF 0 4001 1800 0x4001 1FFF 0 4001 1400 0x4001 17FF 0 4001 1000 0x4001 13FF 0 4001 0800 0x4001 OFFF 0 4001 0400 0x4001 07 0 4001 0000 0x4001 03FF 0 4000 7800 0 4000 0 4000 7400 0x4000 77FF 0 4000 7000 0x4000 73FF 0 4000 6 00 0x4000 6FFF 0 4000 6800 0x4000 6BFF 0 4000 6400 0x4000 67FF 0 4000 6000 0x4000 63FF 0 4000 5 00 0x4000 5FFF 0 4000 5800 0x4000 5BFF 0 4000 5400 0x4000 57FF 0 4000 5000 0x4000 53FF 0 4000 4 00 0x4000 0 4000 4800 0x4000 4BFF 0 400
40. 12 14 15 USB FS DP DM 17 21 24 USB HS DP DM 9 OTG FS VBUS 0 65 1 1 2 0 OTG HS VBUS PA12 PB15 USB FS USB HS DP Vin Vss 15 18 2 1 9 13 OTG FS VBUS Vin Vss 0 25 0 37 0 55 OTG HS VBUS 1 Allthe voltages are measured from the local ground potential The STM32F205xx and STM32F207xx USB OTG FS functionality is ensured down to 2 7 V but not the full USB OTG FS electrical characteristics which are degraded in the 2 7 to 3 0 V voltage range Guaranteed by design not tested in production is the load connected on the USB OTG FS drivers Doc ID 15818 Rev 9 111 174 Electrical characteristics STM32F20xxx 112 174 Figure 45 USB OTG FS timings definition of data signal rise and fall time Crossover points Differen tial data lines CRS 14137 USB OTG FS electrical characteristics Driver characteristics Table 56 Symbol Parameter Rise time Conditions C 50 pF Min Max 20 Unit Fall time 2 C 50 pF 20 110 2 0 V Rise fall time matching t t 90 Vors Output signal crossover voltage 1 3 Guaranteed by design not tested in production 2 Measured from 10 to 90 of the data signal For more detailed informations please refer to USB Specification Chapter 7 version 2 0
41. 2 Dimensions are in millimeters Table 87 LQPF100 14 x 14 mm 100 pin low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 15 800 16 000 16 200 0 6220 0 6299 0 6378 D1 13 800 14 000 14 200 0 5433 0 5512 0 5591 D3 12 000 0 4724 E 15 80v 16 000 16 200 0 6220 0 6299 0 6378 E1 13 800 14 000 14 200 0 5433 0 5512 0 5591 E3 12 000 0 4724 0 500 0 0197 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 3 5 7 0 3 5 7 0 080 0 0031 1 Values in inches converted from mm and rounded to 4 decimal digits Doc ID 15818 Rev 9 147 174 Package characteristics STM32F20xxx Figure 80 LQFP144 20 x 20 mm 144 pin low profile quad Figure 81 Recommended flat package outline footprint 2 Seating plane 0 25 mm 73 135 aege piene identification ME 1A a 144 VUTUN t 19 9 22 6 MIO 1 Drawing is not to scale 2 Dimensions are in millimeters
42. 57 STM32F205xx STM32F207xx ARM based 32 bit MCU 150DMIPs up to 1 MB Flash 128 4KB RAM USB OTG HS FS Ethernet 17 TIMs ADCs 15 comm interfaces amp camera Features m Core ARM 32 bit Cortex M3 CPU with Adaptive real time accelerator ART Accelerator allowing O wait state execution performance from Flash memory frequency up to 120 MHz memory protection unit 150 DMIPS 1 25 DMIPS MHz Dhrystone 2 1 m Memories Upto 1 Mbyte of Flash memory 512 bytes of OTP memory Upto 128 4 Kbytes of SRAM Flexible static memory controller that supports Compact Flash SRAM PSRAM NOR and NAND memories LCD parallel interface 8080 6800 modes m Clock reset and supply management From 1 65 to 3 6 V application supply and PVD and BOR 4to 26 MHz crystal oscillator Internal 16 MHz factory trimmed RC 1 accuracy at 25 C 32 kHz oscillator for RTC with calibration Internal 32 kHz RC with calibration m Low power Sleep Stop and Standby modes Vear supply for RTC 20 x 32 bit backup registers and optional 4 KB backup m 12 bit 0 5 us A D converters up to 24 channels upto 6 MSPS in triple interleaved mode m 2 12 bit D A converters m General purpose DMA 16 stream DMA controller with centralized FIFOs and burst support m Upto 17 timers Upto twelve 16 bit and two 32 bit timers up to 120 MHz each with up to 4 I
43. CPOL 0 x 0 CPOL 1 ta SO 60 4 SCK tgis SO 4 B 6 MOSI 1 1 14134 55 SU NSS y 1 tc SCKj a 66 CPHA 1 X CPOL 0 Eu T 1 W SGKH lt n icc x mo NEM uus CEN uec uud M la S0 gt lt no lt p MISO 50 tsu Sl lt gt lt MOSI INPUT MSB IN EHI IN LSB IN 14135 SCK Input 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7Vpp Doc ID 15818 Rev 9 107 74 Electrical characteristics STM32F20xxx Figure 42 SPI timing diagram master mode SCK Input SCK Input High NSS input lc SCKj CPHA 0 M CPOL 0 U A e fi CPHA 0 r MI OUTUT BIT1 OUT OUT 3114136 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7Vpp 108 174 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Table 53 126 characteristics Symbol Parameter Conditions Min Max Unit Master 1 23 1 24 25 clock frequency MHz c CK Slave 0 TBD Ici 12 clock rise and fall time lt load C 50 pF tws 2 WS valid time Master 0 3 tws 2 WS hold time Master 0 tsu ws 2 WS setup time Slave 3 th
44. FSMC A24 EVENTOUT PG14 USART6_TX FSMC_A25 EVENTOUT PG15 USART6_CTS DCMI_D13 EVENTOUT PHO OSC_IN PH1 OSC OUT PH2 ETH MIL CRS EVENTOUT ETH MIL COL EVENTOUT PHA 1202_SCL ora HS ULPI NXT EVENTOUT PHS 12C2_SDA EVENTOUT PH6 12 2_ TIM12 MIL RXD2 EVENTOUT 1263 SCL ETH MIL RXD3 EVENTOUT PH8 I2C3 SDA DCMI HSYNC EVENTOUT PH9 12 3 12 CH2 DCMI EVENTOUT PH10 TIM5_CH1 DCMI_D1 EVENTOUT PHI TIMS_CH2 DCMI_D2 EVENTOUT PH12 TIM5_CH3 DCMI_D3 EVENTOUT PH13 TX EVENTOUT XXXOZJZENLS uondiosep pue s nould 21 84 6 81881 01 90d Table 8 Alternate function mapping continued AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 svs TIM1 2 TIM3 A 5 1 2 252 283 VARTA 2 FS OTG HS ETH C OTO HS DCMI PH14 TIM8_CH2N DCMI_D4 EVENTOUT PH15 TIM8_CH3N DCMI D1 EVENTOUT Plo TIMS 4 Tex WS DCMI EVENTOUT PH CE DCMI_D8 EVENTOUT TIM8 SPI MISO 09 EVENTOUT TIM8 DCMI D10 EVENTOUT TIM8 BKIN 05 EVENTOUT TIM8 VSYNC EVENTOUT PIG TIM8 CH DCMI D6 EVENTOUT PI7 TIM8 CH3 DCMI 07 EVENTOUT Pig EVENTOUT ETH
45. SPI clock rise and fall Capacitive load C 30 pF 8 ns time DuCy SCK clock Slave mode 30 70 tsunss NSS setup time Slave mode 2 NSS hold time Slave mode SCK hi Master mode 30 MHz igh and low time t 3 t 3 9 presc 2 2 5 Data input setup time t su Sl Slave mode 5 2 Master mode 5 2 Data input hold time this Slave mode 4 as Data output access taso 9 time Slave mode 20 MHz 0 tisso 2 output disable Slave mode 2 10 20 Data output valid time Slave mode after enable edge 25 tuo Data output valid time Master mode after enable edge 5 tiso Slave mode after enable edge 15 Data output hold time Master mode after enable edge 2 1 Remapped SPI1 characteristics to be determined the data the data in Hi Z Based on characterization not tested in production Doc ID 15818 Rev 9 Min time is for the minimum time to drive the output and the max time is for the maximum time to validate Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put STM32F20xxx Electrical characteristics Figure 40 SPI timing diagram slave mode and CPHA 0 NSS input 55 0
46. Updated Figure 3 Compatible board design between STM32F 10xx and STM32F2xx for LQFP144 package and Figure 2 Compatible board design between STM32F 10xx and STM32F2xx for LQFP100 package Added camera interface for STM32F207Vx devices in Table 2 STM32F205xx features and peripheral counts Removed 16 MHz internal RC oscillator accuracy in Section 2 2 12 Clocks and startup Updated Section 2 2 16 Voltage regulator Modified 125 sampling frequency range in Section 2 2 12 Clocks startup Section 2 2 24 Inter integrated sound FS and Section 2 2 30 Audio PLL PLLI2S Updated Section 2 2 17 Real time clock RTC backup SRAM and backup registers and description of TIM2 and 5 in Section General purpose timers Modified maximum baud rate oversampling by 16 for in Table 5 USART feature comparison Updated note related to RFU pin below Figure 11 STM32F20x LQFP100 pinout Figure 12 STM32F20x LQFP144 pinout Figure 13 STM32F20x LQFP176 pinout Figure 14 STM32F20x UFBGA176 ballout and Table 6 STM32F20x pin and ball definitions In Table 6 STM32F20x pin and ball definitions changed 252 and 1253_ to 1252 5 1253 5 respectively added PA15 TT 3 6 V tolerant I O Added RTC_50Hz as PB15 alternate function in Table 6 STM32F20x pin and ball definitions and Table 8 Alternate function mapping Removed ETH _RMII_TX_CLK for PC3 AF11 in Table 8 Alternate function
47. 1 80 Vepnhyst 2 hysteresis 40 Doc ID 15818 Rev 9 69 174 Electrical characteristics STM32F20xxx Table 17 Embedded reset and power control block characteristics continued Symbol Parameter Conditions Min Typ Max Unit Brownout level 1 Falling edge 2 13 2 19 2 24 V threshold Rising edge 2 23 2 29 2 33 V Brownout level 2 Falling edge 2 44 2 50 2 56 V threshold isi Rising edge 2 53 2 59 2 63 V 7 Brownout level 3 Falling edge 2 5 283 288 V BOR threshold Rising edge 2 85 2 92 2 97 Vaonnys BOR hysteresis 100 2 29 Reset temporization 05 15 3 0 ms InRush current on 2 voltage regulator _ IRUSH power on POR or 160 200 mA wakeup from Standby InRush energy on p UO Voltage regulator Vpp 1 8 V Ta 105 C _ _ RUSH power on POR or 171 mA for 31 us i H wakeup from Standby 1 The product behavior is guaranteed by design down to the minimum value Guaranteed by design not tested in production 3 The reset temporization is measured from the power on POR reset wakeup from to the instant when first instruction is read by the user application code 5 3 6 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage ambient temper
48. 111 25 master timing diagram Philips 1 111 USB OTG FS timings definition of data signal rise and fall time 113 ULP timing 114 Ethernet SMI timing diagram 115 Ethernet timing 1 115 Ethernet timing 116 ADC accuracy 1 119 Typical connection diagram using the ADC 120 Power supply and reference decoupling Vggr not connected to 121 Power supply and reference decoupling connected to 121 12 bit buffered non buffered 124 Asynchronous non multiplexed SRAM PSRAM NOR read waveforms 126 Asynchronous non multiplexed SRAM PSRAM NOR write waveforms 127 Asynchronous multiplexed PSRAM NOR read waveforms 128 Asynchronous multiplexed PSRAM NOR write waveforms 129 Synchronous multiplexed NOR PSRAM read timings 130 Synchronous multiplexed PSRAM write 0 132 Synchronous non multiplexed NOR PSRAM read
49. 5 3 8 External clock source characteristics High speed external user clock generated from an external source The characteristics given in Table 26 result from tests performed using an high speed external clock source and under ambient temperature and supply voltage conditions summarized in Table 12 Table 26 High speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit External user clock source fHSE_ext frequency 1 8 26 MHz input pin high level voltage 0 7Vpp Vpp 7 Vusg IN input pin low level voltage Vss 0 3Vpp W HSE OSC IN high or low time 5 tw HSE ns 5 056 IN rise or fall time 20 5 input capacitance 5 Duty cycle 45 55 96 IL OSC_IN Input leakage current Vss lt VIN lt Vpp 1 1 Guaranteed by design not tested in production Low speed external user clock generated from an external source The characteristics given in Table 27 result from tests performed using an low speed external clock source and under ambient temperature and supply voltage conditions summarized in Table 12 Table 27 Low speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit User External clock source fisE ex frequency 32 768 1000 kHz OSC32 IN input pin high le
50. Changes Appendix A 3 USB OTG full speed FS interface solutions updated Figure 87 USB OTG FS full speed host only connection and added Note 2 updated Figure 88 OTG FS full speed connection dual role with internal PHY and added Note 3 and Note 4 modified Figure 89 HS high speed device connection host and dual role in high speed mode with external PHY and added Note 2 Appendix A 4 USB OTG high speed HS interface solutions removed figures USB OTG HS device only connection in FS mode and USB OTG HS host only connection in FS mode updated Figure 89 HS high speed device connection host and dual role in high speed mode with external PHY Added Appendix A 6 Ethernet interface solutions Updated disclaimer on last page Doc ID 15818 Rev 9 171 174 Revision history STM32F20xxx Table 94 Document revision history continued Date 24 Apr 2012 Revision Changes Updated Vpp minimum value in Section 2 Description Updated number of USB OTG HS and FS modified packages for STM32F207Ix part numbers added Note 1 related to FSMC and Note 2 related to SPI I2S and updated Note Table 2 STM32F205xx features and peripheral counts and Table 3 STM32F207xx features and peripheral counts Added Note 2 and update 5 in Figure 5 STM32F20x block diagram Updated maximum number of maskable interrupts in Section 2 2 10 Nested vectored interrupt controller NVIC
51. Doc ID 15818 Rev 9 141 174 Electrical characteristics STM32F20xxx Table 81 Switching characteristics for Flash write cycles 2 Symbol Parameter Min Max Unit ty NWE D FSMC_NWE low to FSMC_D 15 0 valid 0 ns th nwe p FSMC_NWE high to FSMC_D 15 0 invalid 5 ta D NWE FSMC D 15 0 valid before FSMC_NWE high 5THCLK ns lqaLE NwE ALE valid before FSMC_NWE low 2 ns tn NwE ALE FSMC NWE high to FSMC_ALE invalid 2 ns 1 2 30pF 2 Based on characterization not tested in production 5 3 26 Camera interface DCMI timing specifications Table 82 DCMI characteristics Symbol Parameter Conditions Min Max Unit Frequency ratio DOMI PIXCLK 04 DOMI PIXCLK fuci K 48 MHz 5 3 27 SD SDIO card host interface 5010 characteristics Unless otherwise specified the parameters given in Table 83 are derived from tests performed under ambient temperature fpc frequency and Vpp supply voltage conditions summarized in Table 12 Refer to Section 5 3 16 port characteristics tor more details on the input output alternate function characteristics D 7 0 CMD CK Figure 73 SDIO high speed mode tr CK D CMD output D CMD input 14887 142 174 Doc ID 15818 Rev 9 ky STM32F20xxx Electrical characteristics 5 3 28
52. Doc ID 15818 Rev 9 ky STM32F20xxx Electrical characteristics 5 3 16 port characteristics General input output characteristics Unless otherwise specified the parameters given in Table 44 are derived from tests performed under the conditions summarized in Table 12 All I Os are CMOS and TTL compliant Table 44 static characteristics Symbol Parameter Conditions Min Typ Max Unit Vi Input low level voltage 0 3 2 0 8 TTL ports TT input high level volt 2 Vpp O O input high level voltage 2 7 V lt Vpp lt 3 6V 0 ppt 0 3 input high level voltage 2 0 5 5 Inputlow level voltage 0 3 i 0 3Vpp CMOS ports TT I O input high level voltage 3 60 E 3 3 1 8 VsVpps3 6V 0 1 5 2 Vint 0 7Vpp FT I O input high level voltage CMOS ports 550 2 0 3 6 V Schmitt trigger voltage hysteresis 200 Vh i mV ys Schmitt trigger voltage 4 hysteresis 5 input leakage current 0 Vss 1 Ik H 9 OFT input leakage current 0 VI 5 3 All pins except for 30 40 50 R Weak pull up equivalent PA10 and V PU rasistor PB12 Vin Vss PA10 and PB12 8 11 15 kQ All pins except for 30 40 50 R Weak pull down PA10 and Vus V PD equivalent resistor 12 IN DD PA10 and PB12 8 11 15 Cio I O pin capacita
53. FSMC NE NE th NE NOE t FSMC NOE FSMC_NWE FSMC_A 25 16 j BL FSMC NBL 1 0 h Data NE NE H tsu Data_NOE gt h Data NOE FSMC AD 15 0 6 NADV tw NADV FSMC_NADV ai14892b Table 72 Asynchronous multiplexed PSRAM NOR read timings Symbol Parameter Min Max Unit tw NE FSMC_NE low time 1 1 5 t NoE FSMC_NEx low to FSMC_NOE low 2Tucik 2 0 5 ns tw NOE FSMC_NOE low time 1 5 th NE_NOE FSMC NOE high FSMC NE high hold time 0 3 ns Np FSMC NEx low to FSMC valid 2 ns tyNADV NE NEx low to FSMC_NADV low 1 2 5 ns NADV low time 1 5 5 2 valid hold time after Tonik _ E gh tA Address hold time after FSMC_NOE high ns FSMC BL time after NOE high 0 ns FSMC NEx low to BL valid 1 ns tsu Data_NE Data to FSMC high setup time 2 ns tsu Data_NOE Data to FSMC NOE high setup time Tucuk ns Data hold time after FSMC_NEx high 0 ns th Data_NOE Data hold time after FSMC_NOE high 0 ns 1 30pF 2 Based on characterization not tested in production Doc ID 15818 Rev 9 127 174 Electrical characteristics STM32F20xxx Figure 58 Asynchronou
54. FSMC_NCEx ALE FSMC A17 CLE FSMC A16 5 NWE la ALE NOE th NOE ALE lt FSMC NOE tsu D NOE FSMC D 15 0 14901 Figure 70 controller waveforms for write access FSMC NCEx N ALE FSMC_A17 CLE FSMC_A16 la ALE NWE n NWE ALE FSMC_NWE FSMC_NOE NRE LINWE D FSMC D 15 0 ai14902c 140 174 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 71 controller waveforms for common memory read access FSMC NCEx N ALE FSMC_A17 CLE FSMC 2 ty ALE NOE th NOE ALE FSMC_NWE tw NOE FSMC_NOE tsu D NOE FSMC D 15 0 ai14912c Figure 72 NAND controller waveforms for common memory write access FSMC NCEx N ALE FSMC_A17 la ALE NOE tw NWE th NOE ALE FSMC_NWE FSMC NOE 7 th NWE D FSMC D 15 0 14913 Table 80 Switching characteristics for Flash read cycles 1 2 Symbol Parameter Min Max Unit tw NOE FSMC_NOE low width 4 1 4 2 5 valid data before _ 9 _ s th NoE p FSMC D 15 0 valid data after FSMC_NOE high 3 ns tataLE NoE FSMC_ALE valid before FSMC_NOE low 3THCLK ns th NOE ALE FSMC_NWE high to FSMC_ALE invalid 3TucLKt 2 ns 1 C_ 30 pF 2 Based on characterization not tested in production
55. Updated Vpp minimum value in Section 2 2 14 Power supply schemes Updated Note Section Regulator ON Removed STM32F205xx in Section 2 2 28 Universal serial bus on the go full speed OTG_FS Removed support of 2 for OTG PHY in Section 2 2 29 Universal serial bus on the go high speed OTG_HS Removed OTG_HS_SCL OTG_HS_SDA OTG_FS_INTN in Table 6 STM32F20x pin and ball definitions and Table 8 Alternate function mapping Renamed PH10 alternate function into 5 in Table 8 Alternate function mapping Added Table 7 FSMC pin definition Updated Note 1 Table 12 General operating conditions Note 2 Table 13 Limitations depending on the operating power supply range and Note 1 below Figure 20 Number of wait states versus and Vpp range Updated Table 17 Embedded reset and power control block characteristics Updated typical values in Table 22 Typical and maximum current consumptions in Standby mode and Table 23 Typical and maximum current consumptions in Vg4r mode Updated Table 28 HSE 4 26 MHz oscillator characteristics and Table 29 LSE oscillator characteristics f sg 32 768 kHz Updated Table 35 Flash memory characteristics Table 36 Flash memory programming and Table 37 Flash memory programming with Updated Section Output driving current Updated Note 3 and removed note related to minimum hold time value in Table 50 PC characteristics Updated
56. Vpp minimum value is 1 7 V when the device operates in the 0 to 70 temperature range and IRROFF is set to Vpp Table 3 STM32F207xx features and peripheral counts Peripherals STM32F207Vx STM32F207Zx STM32F207Ix Flash memory in Kbytes 256 512 768 1024 256 512 768 1024 256 512 768 1024 System 128 SRAM in Kbytes SRAM1 SRAM2 112 16 Backup 4 FSMC memory controller Yes Ethernet Yes General purpose 10 Timers Advanced control 2 Basic 2 Random number generator Yes 5 3 22 3 USART 4 Comm interfaces UART 2 USB OTG FS Yes USB OTG HS Yes CAN 2 Camera interface Yes GPIOs 82 114 140 SDIO Yes 12 bit ADC 3 Number of channels 16 24 24 12 bit DAC Yes Number of channels 2 Maximum CPU frequency 120 MHz 1 8 V to 3 6 Operating voltage 0242 61115 uonduosog 3 STM32F207xx features and peripheral counts continued iy Peripherals STM32F207Vx 5 32 2072 STM32F207Ix Ambient temperatures 40 to 85 40 to 105 C Operating temperatures Junction temperature 40 to 125 LQFP176 Package 100 LQFP144 UFBGA176 1 For the LQFP100 package only FSMC Bank1 Bank2 are available Bank1 can only support a multiplexed NOR PSRAM memory using the Chip Select Bank2 can only support a 16 or 8 bit NAND Flash memory using the NCE2 Chip
57. as input floating with or without pull up or pull down or as peripheral alternate function Most of the GPIO pins are shared with digital or analog alternate functions AII GPIOs are high current capable and have speed selection to better manage internal noise power consumption and electromagnetic emission The alternate function configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I Os registers To provide fast I O handling the GPIOs on the fast AHB1 bus with a clock up to 120 MHz that leads to a maximum toggling speed of 60 MHz ADCs analog to digital converters Three 12 bit analog to digital converters are embedded and each ADC shares up to 16 external channels performing conversions in the single shot or scan mode In scan mode automatic conversion is performed on a selected group of analog inputs Additional logic functions embedded in the ADC interface allow e Simultaneous sample and hold e Interleaved sample and hold The ADC can be served by the DMA controller An analog watchdog feature allows very precise monitoring of the converted voltage of one some or all selected channels An interrupt is generated when the converted voltage is outside the programmed thresholds The events generated by the timers TIM1 2 TIM3 4 TIM5 and TIM8 be internally connected to the ADC start trigger and injection trigger respectively to all
58. to be defined Table 62 gives the list of Ethernet MAC signals for the and Figure 48 shows the corresponding timing diagram Figure 48 Ethernet timing diagram RMII REF CLK RMIL TX EN RMII TXD 1 0 tsu RXD tih RXD tsu CRS tih CRS RMII_RXD 1 0 RMII_CRS_DV 15667 Table 62 Dynamics characteristics Ethernet MAC signals for Symbol Rating Min Typ Max Unit lsu RXD Receive data setup time 1 tin RXD Receive data hold time 1 5 tsu CRS Carrier sense set up time 0 tih CRS Carrier sense hold time 2 ta TXEN Transmit enable valid delay time 9 11 13 ta TxD Transmit data valid delay time 9 11 5 14 Doc ID 15818 Rev 9 ky STM32F20xxx Electrical characteristics Table 63 gives the list of Ethernet MAC signals for and Figure 48 shows the corresponding timing diagram Figure 49 Ethernet timing diagram lsu RXD tsu ER su DV RXD 3 0 RX DV RX ER TX la TXEN la TxD TX TXD 3 0 3115668 Table 63 Dynamics characteristics Ethernet MAC signals for MII Symbol Rating Min Typ Max Unit lsu RXD Receive data setup time 7 5 10 ns tin RXD Receive data hold time 1 10 ns tsu DV Data valid setup time 4 2 10 ns tih DV Data valid hold time 0 10
59. 0 0035 0 0079 D 23 900 24 100 0 9409 0 9488 E 23 900 24 100 0 9409 0 9488 e 0 500 0 0197 HD 25 900 26 100 1 0197 1 0276 HE 25 900 26 100 1 0197 1 0276 0 0 450 0 750 0 0177 0 0295 L1 1 000 0 0394 20 1 250 0 0492 2 1 250 0 0492 k 0 7 0 7 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits 2 L dimension is measured at gauge plane at 0 25 mm above the seating plane 57 Doc ID 15818 Rev 9 149 174 Package characteristics STM32F20xxx Figure 83 UFBGA176 25 ultra thin fine pitch ball grid array 10 x 10 x 0 6 mm package outline A2 4 eg 3 1 1 Seating plane Ball A1 BOTTOM VIEW TOP VIEW AOE7 ME V2 1 Drawing is not to scale Table 90 UFBGA176 25 ultra thin fine pitch ball grid array 10 x 10 x 0 6 mm mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 0 460 0 530 0 600 0 0181 0 0209 0 0236 Al 0 050 0 080 0 110 0 002 0 0031 0 0043 A2 0 400 0 450 0 500 0 0157 0 0177 0 0197 0 130 0 0051 4 0 270 0 320 0 370 0 0106 0 0126 0 0146 b 0 230 0 280 0 330 0 0091 0 0110 0 0130 D 9 950 10 000 10 050 0 3740
60. 0 100 us lat latency i 3 3 1 4 fADC 30 MHz 0 067 us tial Regular trigger conversion latency 7 20 1 30 2 0 100 16 us 8 Sampling time 3 480 l fApc 0 Power up time 2 3 us f 30 MHz ADO i 0 5 x 16 40 us 12 bit resolution 30 2 0 43 16 34 10 bit resolution 2s Total conversion time including f 30 MHz 0 37 16 27 CONV sampling time 8 bit resolution f 30 MH ADC 0 3 1620 ys 6 bit resolution 9 to 492 ts for sampling n bit resolution for successive approximation Vfapc 3 116 174 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Table 64 ADC characteristics continued Symbol Parameter Conditions Min Typ Max Unit 12 bit resolution 2 Single 12 bit resolution O Sampling rate Interleave Dual ADC 5 3 75 Msps 5 30 MHz mode 12 bit resolution Interleave Triple ADC 5 6 30 2 3 sampling time 300 500 4 ADC Veer DC current 12 bit resolution m VREF consumption in conversion mode 30 MHz 480 sampling time 16 12 bit resolution fADC 30 MHz 3 sampling time 1 6 1 8 mA 4 ADC DC current 12 bit resolution c VDDA consumption in conversion mode fapc 30 MHz 480 sampling time 60 pA 12 bit resolution
61. 0 3937 0 3957 E 9 950 10 000 10 050 0 3740 0 3937 0 3957 e 0 600 0 650 0 700 0 0236 0 0256 0 0276 F 0 400 0 450 0 500 0 0157 0 0177 0 0197 0 080 0 0031 0 150 0 0059 fff 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits 150 174 Doc ID 15818 Rev 9 STM32F20xxx Package characteristics 6 2 Thermal characteristics The maximum chip junction temperature max in degrees Celsius may be calculated using the following equation Ty max TA max Pp max x Where max is the maximum ambient temperature C Oy is the package junction to ambient thermal resistance in C W Pp is the sum of Pint max max Pp max Max Pint max is the product of Ipp and Vpp expressed in Watts This is the maximum chip internal power max represents the maximum power dissipation on output pins where Pio max gt x loi Z Vpp x taking into account the actual loj and of the I Os at low and high level in the application Table 91 Package thermal characteristics Symbol Parameter Value Unit Thermal resistance junction ambient LQFP 64 10 x 10 mm 0 5 mm pitch 59 Thermal resistance junction ambient 51 WLCSP64 2 0 400 mm pitch Thermal resistance junction ambient 46 LQFP100 14 x 14 mm 0 5 mm pitch Oya
62. 1 2 and 3 thresholds in Table 17 Embedded reset and power control block characteristics Changed fosc maximum value in Table 28 HSE 4 26 MHz oscillator characteristics Changed fp L jy maximum value in Table 32 Main PLL characteristics and updated jitter parameters in Table 33 PLLI2S audio PLL characteristics Section 5 3 16 I O port characteristics updated and in Table 44 I O static characteristics Added Note 1 below Table 45 Output voltage characteristics Updated Rpp and parameter description in Table 55 USB FS DC electrical characteristics Updated minimum value in Table 64 ADC characteristics Updated Table 69 Embedded internal reference voltage Removed Ethernet and USB2 for 64 pin devices in Table 93 Main applications versus package for STM32F2xxx microcontrollers Added A 2 Application example with regulator OFF removed FS connection with external PHY figure updated Figure 87 Figure 88 and Figure 90 to add STULPIO1B Doc ID 15818 Rev 9 165 174 Revision history STM32F20xxx 166 174 Table 94 Document revision history continued Date 22 Apr 2011 Revision Changes Changed datasheet status to Full Datasheet Introduced concept of SRAM1 and SRAM2 LQFP176 package now in production and offered only for 256 Kbyte and 1 Mbyte devices Availability of WLCSP64 2 package limited to 512 Kbyte and 1 Mbyte devices
63. 125 MS19012V2 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Low speed internal LSI RC oscillator Table 31 LSI oscillator characteristics 1 Symbol Parameter Min Typ Max Unit fig _ Frequency 17 32 47 kHz LSI oscillator startup time 15 40 us Ibos LSI oscillator power consumption 0 4 0 6 1 3 TA 40 to 105 C unless otherwise specified Based on characterization tested in production Guaranteed by design not tested in production Figure 34 si versus temperature Normalized deviation 96 5 15 25 35 45 55 65 75 85 95 105 Temperature C MS19013V1 5 3 10 PLL characteristics The parameters given in Table 32 and Table 33 are derived from tests performed under temperature and Vpp supply voltage conditions summarized in Table 12 Table 32 Main PLL characteristics Symbol Parameter Conditions Min Typ Max Unit PLL input clock Ea 1 2 10 MHz oUT PLL multiplier output clock 24 120 2 multiplier output _ 3 48 MHz vco OUT PLL VCO output 192 432 MHz ky Doc ID 15818 Rev 9 87 174 Electrical characteristics STM32F20xxx Table 32 Main PLL characteristics continued Symbol Parame
64. 174 Description STM32F20xxx 28 174 Advanced control timers TIM1 TIM8 The advanced control timers TIM1 TIM8 can be seen as three phase PWM generators multiplexed on 6 channels They have complementary PWM outputs with programmable inserted dead times They can also be considered as complete general purpose timers Their 4 independent channels can be used for e Input capture e Output compare e PWM generation edge or center aligned modes e One pulse mode output If configured as standard 16 bit timers they have the same features as the general purpose TIMx timers If configured as 16 bit PWM generators they have full modulation capability 0 10095 TIM1 and TIM8 counters be frozen debug mode Many of the advanced control timer features are shared with those of the standard TIMx timers which have the same architecture The advanced control timer can therefore work together with the TIMx timers via the Timer Link feature for synchronization or event chaining General purpose timers TIMx There ten synchronizable general purpose timers embedded in the STM32F20x devices see Table 4 for differences e 2 5 The STMS2F20x include 4 full featured general purpose timers 2 TIM5 are 32 bit timers and TIM3 and are 16 bit timers The TIM2 and TIM5 timers are based on a 32 bit auto reload up downcounter and 16 bit prescaler The
65. 21 34 44 90 2 17 30 40 60 2 12 25 35 m 30 MHz 7 20 30 3 External clock all 25 MHz 5 18 2g peripherals disabled 16 MHz 9 4 0 17 0 27 0 8 MHz 2 5 15 5 25 5 4 MHz 2 0 14 7 24 8 2 MHz 1 6 14 5 24 6 1 Code and data processing running from SRAM1 using boot pins 2 Based on characterization tested in production at max and fic max with peripherals enabled 3 External clock is 4 MHz and is on when fuc gt 25 MHz 4 When the ADC is on ADON bit set in the 2 register add an additional power consumption of 1 6 mA per ADC for the analog part 5 In this case HCLK system clock 2 72 174 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 22 Typical current consumption vs temperature Run mode code with data processing running from RAM and peripherals ON 60 50 105 C 40 gt 85 C lt 70C 5 55 C 30 C 20 45 C 10 0 0 20 40 60 80 100 120 CPU frequnecy MHz MS19014V1 Figure 23 Typical current consumption vs temperature Run mode code with data processing running from RAM and peripherals OFF Ipp RUN 60 CPU Frequency MHz 519015 1 Doc ID 15818 Rev 9 73 174 Electrical characteristics STM32F20xxx Figure 24 Typical current consumption vs temperature Run mode code with data processing running from Flash ART accelerator OFF periphe
66. 24 x 24 x 1 4 mm package mechanical data 150 UFBGA176 25 ultra thin fine pitch ball grid array 10 x 10 x 0 6 mm mechanical data 151 Package thermal 152 Ordering information 153 Main applications versus package for STM32F2xxx microcontrollers 154 Document revision history 164 Doc ID 15818 Rev 9 ky STM32F20xxx List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 ky Compatible board design between STM32F10xx and STM32F2xx for LQFP64 15 Compatible board design between STM32F10xx and STM32F2xx for 100 16 Compatible board design between STM32F10xx and STM32F2xx for LQFP144 16 Compatible board design between STM32F10xx and STM32F2x
67. 256 Kbytes 512 Kbytes 768 Kbytes or 1 Mbytes available for storing programs and data The devices also feature 512 bytes of OTP memory that can be used to store critical user data such as Ethernet MAC addresses or cryptographic keys Doc ID 15818 Rev 9 19 174 Description STM32F20xxx 2 2 5 2 2 6 2 2 7 Figure 6 CRC cyclic redundancy check calculation unit The CRC cyclic redundancy check calculation unit is used to get a CRC code from a 32 bit data word and a fixed generator polynomial Among other applications CRC based techniques are used to verify data transmission or storage integrity In the scope of the 60335 1 standard they offer means of verifying the Flash memory integrity The CRC calculation unit helps compute a software signature during runtime to be compared with a reference signature generated at link time and stored at a given memory location Embedded SRAM All STM32F20x products embed e 128 Kbytes of system SRAM accessed read write at CPU clock speed with 0 wait states e 4 Kbytes of backup SRAM The content of this area is protected against possible unwanted write accesses and is retained in Standby or VBAT mode Multi AHB bus matrix The 32 bit multi AHB bus matrix interconnects all the masters CPU DMAs Ethernet USB HS and the slaves Flash memory RAM FSMC AHB and APB peripherals and ensures a seamless and efficient operation even when several hi
68. 8 pins are sunk at same time llo 6 mA i i 2V lt Vpp lt 2 7 V Output high level voltage for an I O DD Vpp 0 4 _ when 8 pins are sourced at same time 1 PC13 PC14 PC15 PI8 are supplied through the power switch Since the switch only sinks a limited amount of current 3 mA the use of GPIOs PC13 to PC15 and PI8 in output mode is limited the speed should not exceed 2 MHz with a maximum load of 30 pF and these I Os must not be used as a current Source e g to drive an LED 2 The lig current sunk by the device must always respect the absolute maximum rating specified in Table 10 and the sum of lig I O ports and control pins must not exceed lyss 3 The lig current sourced by the device must always respect the absolute maximum rating specified in Table 10 and the sum of lig I O ports and control pins must not exceed lypp Doc ID 15818 Rev 9 ky STM32F20xxx Electrical characteristics 4 Based on characterization data not tested in production Input output AC characteristics The definition and values of input output AC characteristics are given in Figure 37 and Table 46 respectively Unless otherwise specified the parameters given in Table 46 are derived from tests performed under the ambient temperature and Vpp supply voltage conditions summarized in Table 12 Table 46
69. AC characteristics 2 OSPEEDRy 1 0 bit Symbol Parameter Conditions Min Max Unit value CL 50 pF gt 2 70 V 2 50 pF 1 8V 2 1 Maximum frequency MHz CL 10 pF 2 70 V 5 00 10 pF 1 8 V TBD Output high to low level fall tr Io out 3 5 50 pF Vpp 1 8 V to ns t Output low to high level rise 3 6 V _ TBD r IO out time C 50 pF Vpp gt 2 70 V 6 25 C 50 pF Vpp 1 8 V 12 50 fmax lO out Maximum frequency 2 4 MHz C 10 pF Vpp gt 2 70 V 500 C 10 PF 1 8 V TBD 01 i Output high to low level fall 50 pF Vpp 2 7 7 7 TBD flout Hime C 10 pF Vpp gt 2 7 V TBD ns t Output low to high level rise C 50 pF Vpp 2 7 V 7 TBD C 10 pF gt 27 V E TBD C 40 pF Vpp 2 70 V 50 C 40 pF Vpp 1 8V 25 Maximum frequency 5 2 C 10 pF gt 2 70 V 100 10 pF Vpp gt 1 8 V TBD 10 Output high to low level fal 50 pF 2 4 lt lt 2 7 N TBD time C 10 pF Vpp gt 2 7 V TBD ns 4 Output low to high level rise CL 50 pF 2 4 lt lt 2 7 TBD time C 10 pF Vpp gt 2 7 V 5 y Doc ID 15818 Rev 9 99 174 Electrical characteristics STM32F20xxx Table 46 AC characteristics 2 continued
70. CH3N EVENTOUT ky Doc ID 15818 Rev 9 43 174 Pinouts and pin description STM32F20xxx Table 6 STM32F20x pin and ball definitions continued Pins N 0 55955 Pin 9 function Alternate functions rner gt functions after reset S S o oo o gt 5 28 37 48 58 6 PB2 PB2 BOOT1 EVENTOUT 49 59 R6 PF11 FT PF11 DOMI 12 EVENTOUT 50 60 P6 12 FT 12 FSMC A6 EVENTOUT 51 61 Vss 6 5 Vss 6 52 62 N8 Vpp 5 Vpp 6 53 63 PF13 FT PF13 FSMC A7 EVENTOUT 54164 R7 PF14 FT PF14 FSMC_A8 EVENTOUT 155 65 P7 PF15 FT PF15 FSMC A9 EVENTOUT 56 66 7 PGO FT PGO FSMC_A10 EVENTOUT 57 67 M7 PG1 FT PG1 FSMC_A11 EVENTOUT FSMC_D4 TIM1_ETR 38 58 68 R8 7 FT PE7 EVENTOUT FSMC_D5 TIM1_CH1N 39 59 69 P8 PE8 FT PE8 EVENTOUT FSMC_D6 TIM1_CH1 40 160 70 9 FT 9 EVENTOUT gt 61 71 M9 Vss 7 Vss 7 62 72 Vpp 7 Vpp 7 FSMC D7 TIM1 CH2N 41 63 73 R9 10 FT PE10 EVENTOUT FSMC_D8 TIM1_CH2 42 64174 10 PE11 11 EVENTOUT FSMC 9
71. ETH TXD1 EVENTOUT 30158 07 5 431 159 ph ii 5 VoD 11 USART6_CTS 132 160 B7 PG15 FT PG15 D13 EVENTOUT 4 Doc ID 15818 Rev 9 49 174 Pinouts and pin description STM32F20xxx Table 6 STM32F20x and ball definitions continued Pins a N Main e 315 8 function Alternate functions Other lt gt functions Lo u uu 9 o after reset S S ooo a JTDO TRACESWO JTDO SPI3 1253 55 4 89 133 161 A10 FT TRACESWO 2 2 8 SCK NJTRST SPI3_MISO 56 4 90 1341162 AQ 4 10 NJTRST TIM3_CH1 SPI1_MISO EVENTOUT 12 1 SMBA CAN2_RX OTG_HS_ULPI_D7 ETH_PPS_OUT TIM3_CH2 57 91 1351163 5 FT PB5 SPI1_MOSI SPI3 MOSI DCMI_D10 12S3_SD EVENTOUT 2 SCL CAN2_TX 58 B5 92 1361164 B6 PB6 FT PB6 D5 USART1 TX EVENTOUT 2 1 SDA FSMC DOMI VSYNC 59 93 1371165 B5 PB7 FT PB7 USART1_RX CH2 EVENTOUT 60 B6 94 138 166 06 BOOTO Vpp CH3 SDIO D4 TIM10 DCMI_D6 61 7 95 139 167 A5 PB8 FT PB8 ETH_MII_TXD3 2 SCL 1 RX 5 2 NSS 1252 WS
72. FS DC electrical 112 USB OTG FS electrical 113 USB HS DC electrical 113 Clock timing 1 2 1 41 113 BIBIT 114 Ethernet DC electrical 114 Dynamics characteristics Ethernet MAC signals for 115 Dynamics characteristics Ethernet MAC signals for 115 Dynamics characteristics Ethernet MAC signals for 116 ADC characteristics 4 117 ADC accuracy sce Rd dyed 119 DAC characteristics 41 122 TS characteristics du was Pa Rar ERR 124 monitoring characteristics 124 Embedded internal reference 125 Asynchronous non multiplexed SRAM PSRAM NOR read timings 126 Asynchronous non multiplexed SRAM PSRAM NOR write timings 127 Asynchronous multiplexed PSRAM NOR read timings 128 Asynchrono
73. FSMC NADV je tw NE NE NE NBL tv NADV NE tw NADV th BL_NWE 4 I lv Data NE h Data ai14990 1 Mode 2 B and D only In Mode 1 NADV is not used Table 71 Asynchronous non multiplexed SRAM PSRAM NOR write timings Symbol Parameter Min Max Unit tw NE FSMC_NE low time 4 t NwE FSMC_NEx low to FSMC NWE low 0 5 Tucik 0 5 ns tw NWE FSMC_NWE low time 0 5 ns lig NWE ee high to FSMC_NE high hold Tier _ NE FSMC NEx low to FSMC A valid B 0 ns NwE Address hold time after NWE high ns tv BL_NE FSMC_NEx low to FSMC_BL valid 0 5 ns hold time after NWE _ Data to FSMC_NEx low to Data valid 5 ns th Data Data hold time after FSMC_NWE high 0 5 2 8 NEx low FSMC_NADV low 2 2 ns tw NADV FSMC_NADV low time 1 5 ns 1 2 30pF 2 Based on characterization not tested in production Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 57 Asynchronous multiplexed PSRAM NOR read waveforms
74. Figure 74 SD default mode CK lOHD D 14888 Table 83 SD MMC characteristics Symbol Parameter Conditions Min Max Unit Clock frequency in data transfer C lt 30 pF 0 48 MHz mode SDIO CK fpgc o frequency ratio 8 3 Clock low time fpp 16 MHz C lt 30 pF 32 tw ckH Clock high time fpp 16 MHz C lt 30 pF 31 ns t Clock rise time C lt 30 pF 3 5 t Clock fall time C lt 30 pF 5 CMD D inputs referenced to CK tisu Input setup time lt 30 pF 2 ns Input hold C lt 30 pF 0 CMD D outputs referenced to CK in MMC and SD HS mode toy Output valid time C lt 30 pF 6 ns tou Output hold time C lt 30 pF 0 3 CMD D outputs referenced to CK in SD default mode tovp Output valid default time C lt 30 pF 7 ns loup Output hold default time C lt 30 pF 0 5 1 Referto SDIO CLKCR the SDI clock control register to control the CK output RTC characteristics Table 84 RTC characteristics Symbol Parameter Conditions Min Max Unit Any read write trequency operation from to an 4 i RTC register Doc ID 15818 Rev 9 143 174 Package characteristics STM32F20xxx 6 6 1 144 174 Package characteristics Package mechanical data In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages
75. Select The interrupt line cannot be used since Port G is not available in this package 2 SPI2 and SPI3 interfaces give the flexibility to work an exclusive way in either the SPI mode or the 125 audio mode 3 minimum value is 1 7 V when the device operates in the 0 to 70 C temperature range and IRROFF is set to Vpp 9590 024261115 STM32F20xxx Description 2 1 Full compatibility throughout the family The STM32F205xx STM32F207xx constitute the STM32F20x family whose members are fully pin to pin software and feature compatible allowing the user to try different memory densities and peripherals for a greater degree of freedom during the development cycle The STM32F205xx and STM32F207xx devices maintain a close compatibility with the whole STM32F 10xxx family All functional pins are pin to pin compatible The STM32F205xx STM32F207xx however are not drop in replacements for the STM32F 10xxx devices the two families do not have the same power scheme and so their power pins are different Nonetheless transition from the STM32F10xxx to the STM32F20x family remains simple as only a few pins are impacted Figure 3 Figure 4 and Figure 1 provide compatible board designs between the STM32F20x the STM32F10xxx family Figure 1 Compatible board design between STM32F10xx and STM32F2xx for LQFP64 package N
76. Symbol Parameter Conditions A 105 C Unit z 18V 24V 33V Vpp 3 6 V Backup SRAM ON low speed 1 1 oscillator and RTC ON TS 1 68 18 m Backup Backup SRAM OFF low speed 1 1 Supply loscillator RTC ON 8 19 current Backup SRAM ON RTC OFF 0 79 0 81 0 86 90 160 Backup SRAM OFF OFF 0 10 0 10 0 10 50 70 1 Based on characterization not tested in production On chip peripheral current consumption The current consumption of the on chip peripherals is given in Table 24 The MCU is placed under the following conditions 78 174 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics e At startup all pins are configured as analog inputs by firmware e All peripherals are disabled unless otherwise mentioned e given value is calculated by measuring the current consumption with all peripherals clocked off With one peripheral clocked on with only the clock applied e Thecode is running from Flash memory and the Flash memory access time is equal to 3 wait states at 120 MHz e Prefetch and Cache ON e When the peripherals are enabled HCLK 120MHZ fpc fucik 4 and 2 e typical values are obtained for Vpp 3 3 V and 25 C unless otherwise spe
77. Temperature sensor characteristics Table 67 TS characteristics Symbol Parameter Min Typ Max Unit TM Vsense linearity with temperature 1 2 C Average slope 2 5 mV C Voltage at 25 C 0 76 terni Startup time 6 10 us ADC sampling time when reading the Ts temp temperature 10 _ _ 1 C accuracy 1 Based on characterization not tested production 2 Guaranteed by design not tested in production 3 Shortest sampling time can be determined in the application by multiple iterations 5 3 23 Vgar monitoring characteristics Table 68 monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for 50 Ratio on measurement 2 Error 1 1 ADC sampling time when reading the Vgar T 2 2 5 s S_vbat 1mV accuracy 1 Guaranteed by design not tested in production 2 Shortest sampling time can be determined in the application by multiple iterations Doc ID 15818 Rev 9 123 74 Electrical characteristics STM32F20xxx 5 3 24 Embedded reference voltage The parameters given in Table 69 are derived from tests performed under ambient temperature and Vpp supply voltage conditions summarized in Table 12 Table 69 Embedded internal reference voltage Symbol Parameter Conditio
78. Vpp 9 1252 8 CH1 SDIO 6 37 02 63 96 115 15 6 6 USART6_TX DCMI_D0 TIM3_CH1 EVENTOUT 1253 TIM8 CH2 SDIO D7 38 F2 64 97 116 615 FT PC7 USART6 RX DCMI_D1 TIM3_CH2 EVENTOUT TIM8_CH3 SDIO_DO 39 65 98 117 614 TIM3_CH3 USART6 D2 EVENTOUT 1252 CKIN I283 CKIN MCO2 40101166 99 118 F14 PC9 9 TIM8_CH4 SDIO_D1 I2C3 SDA DOMI CH4 EVENTOUT MCO 1 USART1_CK TIM1 1 12 3 SCL 41 E2 67 1100 119 F15 PA8 PA8 OTG FS SOF EVENTOUT USART1_TX CH2 OTG FS 42 68 101 120 E15 9 9 12 3 5 DOMI DO VBUS EVENTOUT USART1_RX TIM1_CH3 43 03 69 10211211 D15 PA10 10 OTG FS D1 EVENTOUT CTS CAN1 RX 44 D2 70 103 122 C15 PA11 11 CH4 OTG FS DM EVENTOUT USART1_RTS CAN1_TX 45 C1 71 104 123 15 12 FT PA12 TIM1_ETR OTG_FS_DP EVENTOUT JTMS 46 B2 72 105 124 15 PA13 FT SWDIO JTMS SWDIO 47 C2 73 106 125 F13 Vcap 2 Vcap 2 1 74 107 126 F12 Vss 2 Vss 2 48 75 108 127 G13 Vpp 2 S Vpp 2 ky Doc ID 15818 Rev 9 47 174 Pinouts and pin description STM32F20xxx Table 6 STM32F20x and ball definitions continued Pins e 2 Main t e 212 8
79. and Ethernet interfaces The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 kHz to 192 kHz In addition to the audio PLL a master clock input pin can be used to synchronize the 25 flow with an external PLL or Codec output Digital camera interface DCMI The camera interface is not available STM32F205xx devices STM32F207xx products embed a camera interface that can connect with camera modules and CMOS sensors through an 8 bit to 14 bit parallel interface to receive video data The camera interface can sustain up to 27 Mbyte s at 27 MHz or 48 Mbyte s at 48 MHz It features e Programmable polarity for the input pixel clock and synchronization signals e Parallel data communication can be 8 10 12 or 14 bit e Supports 8 bit progressive video monochrome or raw Bayer format YCbCr 4 2 2 progressive video RGB 565 progressive video or compressed data like JPEG e Supports continuous mode or snapshot a single frame mode e Capability to automatically crop the image True random number generator RNG All STM32F2xxx products embed a true RNG that delivers 32 bit random numbers produced by an integrated analog circuit Doc ID 15818 Rev 9 33 174 Description STM32F20xxx 2 2 33 2 2 34 2 2 35 34 174 GPIOs general purpose inputs outputs Each of the GPIO pins can be configured by software as output push pull or open drain with or without pull up or pull down
80. cR e rre RU 148 LQFP144 20 x 20 mm 144 pin low profile quad flat package 149 Recommended footprint T Tp Eq 149 LQFP176 Low profile quad flat package 24 x 24 x 1 4 mm package outline 150 UFBGA176 25 ultra thin fine pitch ball grid array 10 x 10 x 0 6 mm package outline 151 Regulator OFF internal reset 1 155 Regulator OFF internal reset 155 Doc ID 15818 Rev 9 ky STM32F20xxx List of figures Figure 86 Figure 87 Figure 88 Figure 89 Figure 90 Figure 91 Figure 92 Figure 93 Figure 94 Figure 95 Figure 96 Figure 97 Figure 98 USB OTG FS full speed device only 156 USB OTG FS full speed host only 156 OTG FS full speed connection dual role with internal PHY 157 OTG HS high speed device connection host and dual role in high speed mode with external 158 Complete audio player solution 1 159 Complete audio player solution 2 159 Audio player solution using PLL PLLI2S USB 1 160 Audio PLL PLLI2S providing accurate 125
81. clocked via a dedicated internal audio PLL or via an external PLL to allow synchronization 4 USARTs and 2 UARTS A USB OTG full speed with high speed capability with the ULPI A second USB OTG full speed Two 5 An SDIO interface Ethernet and camera interface available on STM32F207xx devices only The STM32F205xx STM32F207xx devices operate in the 40 to 105 C temperature range from a 1 8 V to 3 6 V power supply The supply voltage can drop to 1 7 V when the device operates in the 0 to 70 temperature range IRROFF is connected to Vpp A comprehensive set of power saving modes allow the design of low power applications STM32F205xx and STM32F207xx devices are offered in four packages ranging from 64 pins to 176 pins The set of included peripherals changes with the device chosen These features make the STM32F205xx STM32F207xx microcontroller family suitable for a wide range of applications Motor drive and application control Medical equipment Industrial applications PLC inverters circuit breakers Printers and scanners Alarm systems video intercom and HVAC Home audio appliances Figure 5 shows the general block diagram of the device family Doc ID 15818 Rev 9 11 174 2 6 81881 01 90d Table 2 STM32F205xx features and peripheral counts Peripherals STM3
82. current consumption 1 Oscillator Transconductance 2 8 startup time is stabilized 2 5 1 Guaranteed by design tested in production 2 sg is the startup time measured from the moment it is enabled by software to a stabilized 39 68 kHz oscillation is reached This value is measured for a standard crystal resonator it can vary significantly with the crystal manufacturer For C 2 is recommended to use high quality external ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator see Figure 32 C and are usually the same size The crystal manufacturer typically specifies a load capacitance which is the series combination of C 1 and C 2 Load capacitance C has the following formula C Cj X 2 where Cstray s the pin capacitance and board or trace PCB related capacitance Typically it is between 2 pF and 7 pF For information on electing the crystal refer to the application note AN2867 Oscillator design guide for ST microcontrollers available from the ST website www st com To avoid exceeding the maximum value of C 4 and C 15 pF it is strongly recommended to use a resonator with a load capacitance C 7 pF Never use a resonator with a load capacitance of 12 5 pF Example if you choose a resonator with a load capacitance of C 6 pF and Cstray 2 p
83. depth 0 25 2 96 MODEPER INCSTEP 215 1 1 Guaranteed by design tested in production 90 174 Equation 1 The frequency modulation period MODEPER is given by the equation below MODEPER round f iN 4 fuod and must be expressed in Hz As an example If fp y 1 MHz and fuop 1 kHz the modulation depth MODEPER is given by equation 1 MODEPER round 10 4 x 10 25 Equation 2 Equation 2 allows to calculate the increment step INCSTEP INCSTEP round 2 1 x md x 100 x 5 x MODEPER our Must be expressed in MHz With a modulation depth md 2 4 peak to peak and fyco out 240 in MHz INCSTEP round 2 1 x 2x 240 100 x 5 x 25 1258md quantitazed An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values rounded to the nearest integer of MODPER and INCSTEP As a result the achieved modulation depth is quantized The percentage quantized modulation depth is given by the following formula Mdguantized MODEPER x INCSTEP x 100 x 5 2 1 As a result md 25 1258 x 100 x 5 2 1 x 240 1 99954 peak quantized The error in modulation depth is consequently 2 0 1 99954 0 00046 Doc ID 15818 Rev 9 ky STM32F20xxx Electrical characteristics Figure 35 and F
84. for the Flash memory at higher operating frequencies To release the processor full 150 DMIPS performance at this frequency the accelerator implements an instruction prefetch queue and branch cache which increases program execution speed from the 128 bit Flash memory Based on CoreMark benchmark the performance achieved thanks to the ART accelerator is equivalent to O wait state program execution from Flash memory at a CPU frequency up to 120 MHz Memory protection unit The memory protection unit MPU is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks It is usually managed by an RTOS real time operating system If a program accesses a memory location that is prohibited by the MPU the RTOS can detect it and take action In an RTOS environment the kernel can dynamically update the MPU area setting based on the process to be executed The MPU is optional and can be bypassed for applications that do not need it Embedded Flash memory The STM32F20x devices embed a 128 bit wide Flash memory of 128 Kbytes
85. high 0 2 1 ns la CLKL NADVL FSMC CLK low to FSMC_NADV low 5 1 5 ns la CLKL NADVH 5 low to FSMC_NADV high 2 5 lt ns ta CLKL AV FSMC_CLK low to FSMC_Ax valid x 16 25 0 5 la CLKL AIV FSMC CLK low to FSMC Ax invalid 16 25 0 ns td CLKL NOEL FSMC_CLK low to FSMC_NOE low 1 ns la CLKL NOEH FSMC CLK low to FSMC NOE high 1 i ns la CLKL ADV FSMC low to FSMC AD 15 0 valid 5 3 ns la CLKL ADIV 5 low to FSMC_AD 15 0 invalid 0 5 5 A D 15 0 valid data before FSMC tsu ADV CLKH high 5 ns th CLKH ADV FSMC A D 1 5 0 valid data after FSMC CLK high 0 ns 1 C 30 pF 2 Based on characterization not tested in production Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 60 Synchronous multiplexed PSRAM write timings LEO tw CLK 4 9 tw CLK td CLKL ADV FSMC_AD 15 0 FSMC_NWAIT ME N WAITCFG 0b WAITPOL 0b Isu NWAITV CLKH th CLKH NWaITV BUSTURN 0 149929 Table 75 Synchronous multiplexed PSRAM write timings Symbol Parameter Min Max Unit FSMC period 2 1 ns ta CLKL NExL FSMC_CLK low to FSMC_NEx low x 0 2 0 ns low to FSMC_NEx high 0 2 2 ns ta CLKL NADVL FSMC CLK low to FS
86. production temperature range Better performance could be achieved in restricted Vpp frequency and temperature ranges If IRROFF is set to Vpp this value can be lowered to 1 7 V when the device operates in the 0 to 70 C ADC accuracy vs negative injection current injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to analog pins which may potentially inject negative currents Any positive injection current within the limits specified for lj pi and in Section 5 3 16 does not affect the ADC accuracy Figure 50 accuracy characteristics M 1LSBipga or depending on package 4096 4096 gt 3 l 3 456 7 4093 4094 4095 4096 ai14395c Example of an actual transfer curve Ideal transfer curve End point correlation line EO Offset Error deviation between the first actual transition and the first ideal one EG Gain Error deviation between the last ideal transition and the last actual one ED Differential Linearity Error maximum deviation between actual steps and the ideal one Total Unadjusted Error maximum deviation between the actual and the ideal transfer curves EL Integral
87. the RTC the backup registers and the backup SRAM Note When the microcontroller is supplied from external interrupts RTC alarm events do not exit it from operation 2 2 20 Timers and watchdogs The STM32F20x devices include two advanced control timers eight general purpose timers two basic timers and two watchdog timers All timer counters can be frozen in debug mode Table 4 compares the features of the advanced control general purpose and basic timers Table 4 Timer feature comparison Counter Counter Prescaler Capture Complementary max Max Timer type Timer request compare interface timer resolution type factor output generation channels clock clock Up Any integer 16 Down between 1 Yes 4 Yes 60 MHz Ud Up down and 65536 Up Any integer TIM 32 bit Down between 1 Yes 4 No 30 MHz 50 5 2 General Up down and 65536 purpose Up Any integer 16 bit Down between 1 Yes 4 No 30 MHz Up down 65536 Bu 16 bit Up between 1 Yes 0 No 30 MHz 65536 120 9 16 between 1 2 60 2 MHz and 65536 Any integer TIMTO 16 bit Up between 1 No 1 No 60 MHz TIM11 MHz General and 65536 purpose Any integer 60 TIM12 16 bit Up between 1 No 2 No 30 MHz MHz and 65536 Any integer Bars 16 bit Up between 1 No 1 No 30 MHz aie and 65536 ky Doc ID 15818 Rev 9 27
88. to 1GHz 14 enabled SAE EMI level 3 5 5 3 14 Absolute maximum ratings electrical sensitivity Based on three different tests ESD LU using specific measurement methods the device is stressed in order to determine its performance in terms of electrical sensitivity Electrostatic discharge ESD Electrostatic discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts x 1 supply pins This test conforms to the JESD22 A114 C101 standard Table 41 ESD absolute maximum ratings Symbol Ratings Conditions Class mm Unit value Electrostatic discharge Voltage human body TA 25 C conforming to JESD22 A114 2 20000 model V Electrostatic discharge voltage charge device TA 25 C conforming to JESD22 C101 500 model 1 Based on characterization results not tested in production 2 On VBAT pin VESD HBM is limited to 1000 V Static latch up Two complementary static tests are required on six parts to assess the latch up performance e A supply overvoltage is applied to each power supply e Accurrent injection is applied to each input output and configurable pin These tests are compliant with EIA JESD 78 IC latch up standard Doc ID 15818 Rev 9 95 74 Electrical characteristics STM32F20x
89. 0 4400 0x4000 47FF 0 4000 4000 0x4000 43FF 0 4000 3 00 0 4000 3FFF 0 4000 3800 0x4000 0 4000 3400 0x4000 37FF 0 4000 3000 0x4000 33FF 0 4000 2 00 0x4000 2FFF 0 4000 2800 0x4000 2BFF 0 4000 2400 0x4000 27FF 0 4000 2000 0x4000 23FF 0 4000 1 00 0x4000 1FFF 0 4000 1800 0x4000 1BFF 0 4000 1400 0x4000 17FF 0 4000 1000 0x4000 13FF 0 4000 0x4000 OFFF 0 4000 0800 0x4000 OBFF 0 4000 0400 0x4000 07FF 0 4000 0000 0x4000 31176150 60 174 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics 5 Electrical characteristics 5 1 Parameter conditions Unless otherwise specified all voltages are referenced to Vgg 5 1 1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at 25 C and T Tamax given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 32 5 1 2 Typical values Unless otherwise specified typical data are based o
90. 0 PB13 PA1 41 PB12 42 Vpp 14 2 43 Vss 14 44 12 99 9 985005898580 ITITITIT UT MO co 10 O gt gt ai15972d 1 RFU means reserved for future use This pin can be tied to Vpp Vas or left unconnected ky Doc ID 15818 Rev 9 39 174 Pinouts and pin description STM32F20xxx Figure 14 5 32 20 UFBGA176 ballout 4 13 PI8 1 TAMP2 14 08632 IN E 15 OSC32 OUT PHO OSC IN 2 3 4 5 6 7 8 9 10 11 12 13 14 15 H PH4 J PH5 K VDD_4 L REGOFF ai17293b RFU means reserved for future use This pin can be tied to Vpp Vss or left unconnected 2 Top view Table 6 STM32F20x pin ball definitions Pins e 515 8141813 8 8 function Alternate functions iss lt functions ul o after reset S S o Oo 018 4 414 5 FSMC 23 111111 2 MII TXD3 EVENTOUT TRACEDO FSMC A19 1 1 2 2 2 A PE3 EVENTOUT TRACED1 FSMC_A20 1 13 13 13 B1 PE4 FT PE4 D4 EVENTOUT TRACED2 FSMC A21 1 141414 B2 5 5 9 DCMI_D6 EVENTOUT TRACEDS FSMC A22
91. 05VC STM32F205VE STM32F205VF STM32F205VG STM32F205ZC STM32F205ZE STM32F205ZF STM32F205ZG 5 32 205 5 32 2071 STM32F207IE STM32F207IF STMS32F2071G STM32F207ZC STM32F207ZE STM32F207ZF STM32F207ZG STM32F207VC STM32F207VE STM32F207VF STM32F207VG STM32F207xx 1 174 This is information on a product in full production www st com Contents STM32F20xxx Contents 1 Introduction ss essa 10 2 11 2 1 Full compatibility throughout the family 15 2 2 Device overview 18 2 2 1 Cortex M3 core with embedded Flash SRAM 19 2 2 2 Adaptive real time memory accelerator ART Accelerator 19 2 2 3 Memory protection unit 19 2 2 4 Embedded Flash memory 19 2 2 5 CRC cyclic redundancy check calculation unit 20 2 2 6 Embedded SRAM 20 2 2 7 Multi AHB bus 20 2 2 8 DMA controller DMA 21 2 2 9 Flexible static memory controller FSMC 21 2 2 10 Nested vectored interrupt controller 22 2 211 External interrupt event controller EXTI 22 2 212 Clocks and sta
92. 1 ball location 28 Wafer back side Side view Bump side SO rotated by 90 C Qyeee 2 Seating plane AOFX ME 1 Drawing is not to scale Table 86 WLCSP64 2 0 400 mm pitch wafer level chip size package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 0 520 0 570 0 600 0 0205 0 0224 0 0236 A1 0 170 0 190 0 210 0 0067 0 0075 0 0083 A2 0 350 0 380 0 410 0 0138 0 0150 0 0161 b 0 245 0 270 0 295 0 0096 0 0106 0 0116 D 3 619 3 639 3 659 0 1425 0 1433 0 1441 E 3 951 3 971 3 991 0 1556 0 1563 0 1571 e 0 400 0 0157 3 218 0 1267 0 220 0 0087 0 386 0 0152 0 050 0 0020 146 174 Doc ID 15818 Rev 9 ky STM32F20xxx Package characteristics Figure 78 LQFP100 14 x 14 mm 100 quad flat package outline nn low profile Figure 79 Recommended footprint 0 25 mm 0 10 inch GAGE PLANE SEATING PLANE 4 1L ME 6 167 143 MUN 00 12 3 6 sme 3114906 Drawing is not to scale
93. 20xxx Electrical characteristics Table 12 General operating conditions continued Symbol Parameter Conditions Min Max Unit Internal core voltage to be supplied externally in REGOFF mode Y VCAP2 y LQFP64 444 WLCSP66 392 Power dissipation at TA 85 for LQFP100 7 434 T MAE B y id mW suffix 6 or T 105 C for suffix 7 144 500 LQFP176 526 UFBGA176 513 Ambient temperature for 6 suffix Maximum power dissipation 40 85 version Low power dissipation 40 105 Ambient temperature for 7 suffix Maximum power dissipation 40 105 C version Low power dissipation 40 125 6 suffix version 40 105 Junction temperature range 7 suffix version 40 125 1 IRROFF is set to Vpp this value be lowered to 1 7 V when the device operates the 0 to 70 temperature range a reduced temperature range 2 When the ADC is used refer to Table 64 ADC characteristics 3 Itis recommended to power Vpp and from the same source A maximum difference of 300 mV between Vpp and Vppa be tolerated during power up and power down operation If TA is lower higher Pp values are allowed as long as Tj does not exceed T In low power dissipation state TA can be extended to this range as long as Tj does not exceed T jmay Table 13 Limitations depending on the operating power supply range Max
94. 2F205Rx STM32F205Vx 5 32 2052 Flash memory in Kbytes 128 256 512 768 1024 128 256 512 768 1024 256 512 768 1024 System 64 96 128 64 96 128 96 128 SRAM in Kbytes 2 48 16 80 16 112 16 48 16 80 16 112 16 80 16 112 16 4 4 4 FSMC memory controller No Ethernet No General purpose 10 Timers Advanced control 2 Basic 2 Random number generator Yes SPI 2S 2 2 PC 3 USART 4 Comm UART 2 interfaces USB OTG FS Yes USB OTG HS Yes CAN 2 Camera interface No GPIOs 51 82 114 SDIO Yes 12 bit ADC Number of channels 16 16 24 12 bit DAC Yes Number of channels 2 Maximum CPU frequency 120 MHz Operating voltage 1 8 V to 3 6 Ambient temperatures 40 to 85 C 40 to 105 C Operating temperatures Junction temperature 40 to 125 LQFP64 LOFP6 LQFP64 Package LQFP64 WLCSP64 4 WLCSP6 LQFP100 LQFP144 2 4 2 XXXOCACENLS 6 81881 01 90d 1 Forthe LQFP100 package only FSMC Bank1 Bank2 are available Bank1 can only support multiplexed NOR PSRAM memory using the NE1 Chip Select Bank2 can only support a 16 or 8 bit NAND Flash memory using the NCE2 Chip Select The interrupt line cannot be used since Port G is not available in this package The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the 25 audio mode
95. 4 Current characteristics 65 Thermal 65 General operating conditions 65 Limitations depending on the operating power supply range 66 VCAP1 VCAP2 operating conditions 68 Operating conditions at power up power down regulator ON 69 Operating conditions at power up power down regulator 69 Embedded reset and power control block characteristics 70 Typical and maximum current consumption in Run mode code with data processing running from Flash memory ART accelerator 72 Typical and maximum current consumption in Run mode code with data processing running from Flash memory ART accelerator enabled or RAM 738 Typical and maximum current consumption in Sleep 76 Typical and maximum current consumptions in Stop 78 Typical and maximum current consumptions in Standby mode 79 Typical and maximum current consumptions in 79 Peripheral current consumption 80 Low power mode wakeup timingS
96. 71113 FT PH10 EVENTOUT TIM5_CH2 DCMI_D2 881112 11 10 FT 11 EVENTOUT 5 DCMI_D3 89 K12 12 FT PH12 EVENTOUT 90 12 Vss 14 S Vss 14 Vpp 14 S Vpp 14 5 2 NSS I282 WS 12 2 SMBA 5 CK TIM1 BKIN 33 J1 51 73 92 12 12 FT PB12 HS ULPI_DS5 TXDO TXDO HS ID SPI2 5 1252 5 USART3_CTS TIM1_CH1N CAN2_TX OTG HS 34 H2 52 74 93 P13 FT PB13 OTG HS ULPI D6 VBUS _ ETH_RMII_TXD1 ETH_MII_TXD1 EVENTOUT ky Doc ID 15818 Rev 9 45 174 Pinouts and pin description STM32F20xxx Table 6 STM32F20x pin and ball definitions continued Pins N 0 55955 Pin 9 function Alternate functions rner za 5 gt functions E tia F after reset S S ooon 5 SPI2 MISO TIM1 2 TIM12 CH1 OTG HS DM 35 1 53 75 94 R14 14 FT 14 USART3 RTS TIM8 CH2N EVENTOUT SPI2 MOSI I282 SD TIM1 CHSN 8 CH3N 36 61 54 76 95 R15 15 FT 15 TIM12 2 OTG HS 50Hz FSMC D13 USARTS TX 155 77 96 15 PD8 FT PD8 EVENTOUT FSMC D14 USART3 RX 156 7
97. 8 97 P14 PD9 FT PD9 EVENTOUT FSMC_D15 USART3_CK 57 79 98 N15 PD10 FT PD10 EVENTOUT FSMC_A16 USART3_CTS 58 80 99 N14 PD11 FT PD11 EVENTOUT FSMC A17 TIM4 159181 100 N13 PD12 FT PD12 USART3 RTS EVENTOUT FSMC_A18 TIM4_CH2 160182 1 15 PD13 FT PD13 EVENTOUT 8311021 Vss 8 Vss 8 8411031 413 Vpp 8 Vpp 8 FSMC DO TIM4 CH3 161185 104 M14 PD14 PD14 EVENTOUT FSMC D1 TIM4 CH4 162186 105 114 PD15 FT PD15 EVENTOUT 187 1061115 PG2 FT PG2 FSMC_A12 EVENTOUT 188 7 15 PG3 FT PG3 FSMC_A13 EVENTOUT 89 108 K14 PG4 FT PG4 FSMC_A14 EVENTOUT 90 109 K13 PG5 FT PG5 FSMC_A15 EVENTOUT 9111101 415 PG6 FT PG6 FSMC_INT2 EVENTOUT FSMC_INT3 USART6_CK 192 1111914 PG7 FT PG7 EVENTOUT USART6_RTS 93 112 14 PG8 FT PG8 ETH_PPS_OUT EVENTOUT 94 1113912 Vss 9 5 Vss 9 46 174 Doc ID 15818 Rev 9 ky STM32F20xxx Pinouts and pin description Table 6 STM32F20x pin and ball definitions continued Pins N Main e 315 e 8 function Alternate functions Other lt gt functions Lo u uu 9 o after reset S S ooon 5 95 114 13 Vpp 9 S
98. 8 shared scalable filter banks all of them can be used even if one CAN is used The 256 bytes of SRAM which are allocated for each CAN are not shared with any other peripheral 2 2 28 Universal serial bus on the go full speed OTG_FS The devices embed an USB OTG full speed device host OTG peripheral with integrated transceivers The USB OTG FS peripheral is compliant with the USB 2 0 specification and with the OTG 1 0 specification It has software configurable endpoint setting and supports suspend resume The USB OTG full speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator The major features are e Combined Rx and Tx FIFO size of 320 x 35 bits with dynamic FIFO sizing Supports the session request protocol SRP and host negotiation protocol HNP 4 bidirectional endpoints 8 host channels with periodic OUT support HNP SNP IP inside no need for any external resistor For OTG Host modes a power switch is needed in case bus powered devices are connected e Internal FS OTG PHY support 2 2 29 Universal serial bus on the go high speed OTG HS The STM32F20x devices embed USB OTG high speed up to 480 Mb s device host OTG peripheral The USB OTG HS supports both full speed and high speed operations It integrates the transceivers for full speed operation 12 MB s and features a UTMI low pin interface ULPI for high speed operation 480 MB s When using the USB OTG HS in HS mod
99. A Ncex low FSMC_Ay valid 0 ns th NCEx_al FSMC_NCEx high to FSMC_Ax invalid 4 5 ns ta NREG NCEx NCEx low to FSMC_NREG valid 3 5 ns th NCEx NREG FSMC_NCEx high to FSMC_NREG invalid 4 5 ta NCEx NWE FSMC_NCEx low to FSMC_NWE low 5 1 ns ta NCEx NOE FSMC NCEx low to FSMC NOE low 5 ns tw NOE FSMC_NOE low width 8 0 5 8 1 ns 4 NcEx NOE high to FSMC_NCEx high 2 5 5 tsu D 15 0 valid data before FSMC_NOE high 4 ns th NOE D FSMC NOE high to FSMC D 15 0 invalid 2 ns tw NWE FSMC_NWE low width 8 1 8 4 ns ta NWE_NCEx FSMC_NWE high to FSMC NCEx high 5 1 5 ns ta NcEx NwE FSMC_NCEx low FSMC_NWE low 5HCLK 1 ns tv 0 FSMC NWE low FSMC D 15 0 valid 0 ns th NwE D FSMC NWE high to FSMC_D 15 0 invalid 8 ns la D NWE FSMC D 15 0 valid before FSMC_NWE high 13Tucik ns 1 30 pF 2 Based on characterization not tested in production 138 174 Doc ID 15818 Rev 9 571 STM32F20xxx Electrical characteristics Table 79 Switching characteristics for PC Card CF read and write cycles 2 Symbol Parameter Min Max Unit tw NIOWR FSMC_NIOWR low width 8 0 5 ns tv NIOWR D FSMC_NIOWR low to FSMC_D 15 0 valid 5 1 5 th NIOWR D
100. A OTG FS SCL and OTG FS alternate functions Changed 1253 SCK into I283 MCK for PC7 AF6 Updated peripherals corresponding to AF12 Removed CEXT and ESR from Table 12 General operating conditions Added maximum power consumption at 25 C in Table 21 Typical and maximum current consumptions in Stop mode Updated md minimum value in Table 34 SSCG parameters constraint Added examples in Section 5 3 11 PLL spread spectrum clock generation SSCG characteristics Updated Table 52 SPI characteristics and Table 53 FS characteristics Updated Figure 46 ULPI timing diagram and Table 59 ULPI timing Updated Table 61 Dynamics characteristics Ethernet MAC signals for SMI Table 62 Dynamics characteristics Ethernet MAC signals for RMII and Table 63 Dynamics characteristics Ethernet MAC signals for MII Section 5 3 25 FSMC characteristics updated Table 70 to Table 81 changed C value to 30 pF and modified FSMC configuration for asynchronous timings and waveforms Updated Figure 60 Synchronous multiplexed PSRAM write timings Updated Table 82 DCMI characteristics Updated Table 90 UFBGA176 25 ultra thin fine pitch ball grid array 10 x 10 x 0 6 mm mechanical data Updated Table 92 Ordering information scheme 170 74 3 Doc ID 15818 Rev 9 STM32F20xxx Revision history 4 Table 94 Document revision history continued Date 20 Dec 201 1 Revision 8 continued
101. A Regulator OFF internal reset OFF Doc ID 15818 Rev 9 23 174 Description STM32F20xxx Regulator ON The regulator ON modes are activated by default on LQFP packages On WLCSP66 package they are activated by connecting both REGOFF IRROFF pins to Vss while only REGOFF must be connected to Vss on UFBGA176 package IRROFF is not available minimum value is 1 8 There are three regulator ON modes e is used in nominal regulation mode Run e LPR used in Stop mode e Power down is used in Standby mode The regulator output is in high impedance the kernel circuitry is powered down inducing zero consumption but the contents of the registers and SRAM are lost Regulator OFF e Regulator OFF internal reset ON On WLCSP66 package this mode is activated by connecting REGOFF pin to Vpp and IRROFF pin to Vas On UFBGA176 package only REGOFF must be connected to Vpp IRROFF not available The regulator OFF internal reset ON mode allows to supply externally a 1 2 V voltage source through 1 and Vcap 2 pins in addition to The following conditions must be respected Vpp should always be higher than 1 and 210 avoid current injection between power domains Ifthe time for VcAp 1 and 210 reach 1 08 V is faster than the time for Vpp to reach 1 8 then PAO should be connected to the NRST pin see Figure 7 Otherwise should be asserted low ex
102. ADV NE tw NADV _ ai14991c 1 Mode 2 B C and D only In Mode 1 FSMC NADV is not used Table 70 Asynchronous non multiplexed SRAM PSRAM NOR read timings Symbol Parameter Min Max Unit tw NE FSMC_NE low time 2 0 5 2 0 5 ns FSMC_NEx low to NOE low 0 5 2 5 ns NOElow me 2 05 ns th NE_NOE FSMC NOE high to FSMC high hold time 0 ns NE FSMC NEx low to FSMC A valid 4 ns Address hold time after FSMC_NOE high 0 ns NE FSMC NEx low to FSMC valid 0 5 ns FSMC_BLholdtimeafterFSMC_NOEhigh ns uta DatatoFSMC_NExhigh setup time 05 ns tsu Data_NOE Data to FSMC_NOEx high setup time 2 5 ns tn Data Data hold time after 5 NOE high 0 ns th Data_NE Data hold time after FSMC_NEx high 0 ns ly NADV NE FSMC NEx low to low 2 5 ns 1 2 30pF 2 Based on characterization not tested in production Doc ID 15818 Rev 9 125 174 Electrical characteristics STM32F20xxx 126 174 Figure 56 Asynchronous non multiplexed SRAM PSRAM NOR write waveforms FSMC_NEx FSMC_NOE lt v NWE_NE tw NWE 3 th NE NWE 5 NWE NWE gt 5 A 25 0 5 NBL 1 0
103. ART Standard Modem LIN SPI irDA Smartcard in Mbit s in Mbit s APB name features RTS CTS master ISO 7816 oversampling oversampling mapping by 16 by 8 APB2 max USART1 1 87 7 5 60 MHz APB1 max USART2 X X X X X X 1 87 3 75 30 MHz APB1 max USART3 X X X 1 87 3 75 30 MHz APB1 max UART4 1 87 3 75 30 MHz APB1 max 5 3 75 3 75 30 MHz APB2 max USART6 X X X 3 75 7 5 60 MHz 2 2 23 Serial peripheral interface SPI The STM32F20x devices feature up to three SPIs in slave and master modes in full duplex and simplex communication modes SPI1 can communicate at up to 30 Mbits s while SPI2 and SPI3 can communicate at up to 15 Mbit s The 3 bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits The hardware CRC generation verification supports basic SD Card MMC modes All SPIs can be served by the DMA controller The SPI interface can be configured to operate mode for communications in master mode and slave mode 2 2 24 Inter integrated sound 25 Two standard 25 interfaces multiplexed with SPI2 and SPI3 are available They can operate in master or slave mode in simplex communication modes and can be configured to operate with a 16 32 bit resolution as input or output channels Audio sampling frequencies from 8 kHz up to 192 kHz are supported When either or both of the 125 interfaces is are config
104. C OC PWM or pulse counter and quadrature incremental encoder input m Debug mode Serial wire debug SWD amp JTAG interfaces Cortex M3 Embedded Trace Macrocell April 2012 Doc ID 15818 Rev 9 Datasheet production data WLCSP6442 0 400 mm pitch 1 LQFP64 10 x 10 mm LQFP100 14 x 14 mm UFBGA176 LQFP144 20 x 20 mm 10 x 10 mm LQFP176 24 x 24 mm m Upto 140 ports with interrupt capability Up 136 fast I Os up to 60 MHz Up to 138 5 V tolerant I Os m Upto 15 communication interfaces Upto 3 x interfaces SMBus PMBus Up to 4 USARTs and 2 UARTS 7 5 Mbit s ISO 7816 interface LIN IrDA modem control Upto 5 30 Mbit s 2 with muxed 125 to achieve audio class accuracy via audio PLL or external PLL 2x CAN interfaces 2 0B Active SDIO interface m Advanced connectivity USB 2 0 full speed device host OTG controller with on chip PHY USB 2 0 high speed full speed device host OTG controller with dedicated DMA on chip full speed PHY and ULPI 10 100 Ethernet MAC with dedicated DMA supports IEEE 1588v2 hardware MII RMII m 8 to 14 bit parallel camera interface up to 48 Mbyte s m CRC calculation unit m 96 bit unique ID m Analog true random number generator Table 1 Reference Device summary Part number STM32F205RB STM32F205RC STM32F205RE STM32F205RF STM32F205RG STM32F205VB STM32F2
105. C W Thermal resistance junction ambient LQFP144 20 x 20 mm 0 5 mm pitch 40 Thermal resistance junction ambient 38 LQFP176 24 x 24 mm 0 5 mm pitch Thermal resistance junction ambient 39 UFBGA176 10x 10 mm 0 5 mm pitch Reference document JESD51 2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection Still Air Available from www jedec org Doc ID 15818 Rev 9 151 174 Part numbering STM32F20xxx 7 Part numbering Table 92 Ordering information scheme Example STM32 F 205 E T 6 xxx Device family STM32 ARM based 32 bit microcontroller Product type F general purpose Device subfamily 205 STM32F20x connectivity USB OTG high speed with full speed capability 207 STM32F20x connectivity USB OTG high speed with full speed capability additional USB OTG full speed camera interface Ethernet Pin count 64 pins or 66 pins V 100 pins Z 144 pins 176 pins Flash memory size B 128 Kbytes of Flash memory C 256 Kbytes of Flash memory E 512 Kbytes of Flash memory F 768 Kbytes of Flash memory G 1024 Kbytes of Flash memory Package T LQFP H UFBGA Y WLCSP Temperature range 6 Industrial temperature range 40 to 85 C 7 Industrial temperature range 40 to 105 C Software option Internal code or Blank Options programmed parts TR tape and r
106. C_NWE EVENTOUT PD6 USART2_RX FSMC_NWAIT EVENTOUT PD7 USART2_CK EVENTOUT USART3 TX FSMC D13 EVENTOUT PD9 USART3_RX FSMC_D14 EVENTOUT PD10 USART3_CK FSMC_D15 EVENTOUT PD11 USART3_CTS FSMC A16 EVENTOUT PD12 TIM4_CH1 USART3_RTS FSMC_A17 EVENTOUT PD13 TIM4_CH2 FSMC_A18 EVENTOUT XXXOZJZENLS pue s nould 2 11 94 6 81881 01900 Table 8 Alternate function mapping continued AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 i svs TIM1 2 4 5 2 252 5 253 VARTA 2 FS OTG HS DCMI oce TIM4 FSMC DO EVENTOUT PD15 TIM4_CH4 FSMC_D1 EVENTOUT PEO TIM4_ETR FSMC_NBLO DCMLD2 EVENTOUT FSMC BLN1 EVENTOUT PE2 TRACECLK ETH TXD3 A23 EVENTOUT TRACEDO A19 EVENTOUT 4 TRACED FSMC_A20 EVENTOUT PES TRACED2 TIM9 FSMC A21 DCMI 06 EVENTOUT PEG TIM9 CH FSMC A22 07 EVENTOUT PE7 ETR FSMC 04 EVENTOUT FSMC 05 EVENTOUT PE9 TIM1_CH1 FSMC D6 EVENTOUT PE10 TIM1_CH2N FSMC_D7 EVENTOUT FSMC DB EVENTOUT PE12 TIM1_CH3N FSMC_D9 EVENTOUT PE13 TIM1_CH3 FSMC_D10 EVENTOUT PE14
107. D 1 0 MAC 10 100 RXD 1 0 RMII CRX DV RMII REF CLK Ethernet PHY 10 100 IEEE1588 HCLK 1 02 25 MHz XT1 519970 1 1 must greater than 25 MHz 2 The 25 MHz PHY CLK must be derived directly from the HSE oscillator before the PLL block Doc ID 15818 Rev 9 STM32F20xxx Revision history 8 Revision history Table 94 Document revision history Date Revision Changes 05 Jun 2009 1 Initial release Document status promoted from Target specification to Preliminary data In Table 6 STM32F20x pin and ball definitions Note 4 updated 09 Oct 2009 2 sa and Vpp pins inverted Figure 11 STM32F20x LQFP100 pinout Figure 12 STM32F20x LQFP144 pinout and Figure 13 STM32F20x LQFP176 pinout corrected accordingly Section 6 1 Package mechanical data changed to LQFP with no exposed pad LFBGA144 package removed STM32F203xx part numbers removed Part numbers with 128 and 256 Kbyte Flash densities added 01 Feb 2010 3 Encryption features removed PC13 TAMPER RTC renamed to PC13 RTC_AF1 and PI8 TAMPER RTC renamed to PI8 RTC_AF2 Renamed high speed SRAM system SRAM Removed combination 128 KBytes Flash memory in LQFP144 Added UFBGA176 package Added note 1 related to LQFP176 package in Table 2 Figure 13 and Table 92 Added information on ART acce
108. EI SPIt_NSS EVENTOUT TIM3 8 ULPI D1 ETH MIL RXD2 EVENTOUT PB TIM1_CH3N 8 CH3N Hs ULPI 02 ETH MIL RXD3 EVENTOUT PB2 EVENTOUT JTDO SPIS_SCK PB3 TM2 cH2 EVENTOUT PB4 JTRST TIM3_CH1 SPH_MSO 5 MiSO EVENTOUT 5 MOSI PB5 TIM3_CH2 SMBA 8 CAN2 RX HS 07 ETH PPS OUT D10 EVENTOUT TIM4 2 1 USART1_TX CAN2 TX 05 EVENTOUT PB7 TIM4 CH l2C1 SDA USART1_RX FSMC NL DCMI VSYNC EVENTOUT PBB TIM4_CH3 TIMIQ 21 SCL RX ETH 500 04 DCMI 06 EVENTOUT 5 2 NSS TIM4 I2C1 SDA TX 800 05 DCMI_D7 EVENTOUT 2 5 PB10 TIM2_CH3 laca SCL USART3 TX HS 03 ETH MIL RX ER EVENTOUT ETH MIL TX EN PB11 TIM2_CH4 12C2_SDA USART3_RX OTG_HS_ULPLD4 TX EN EVENTOUT SPI2 NSS ETH TXDO PB12 TIM1_BKIN 12C2_SMBA bal We USART3_CK HS ULL Ds ETAT TAS HS ID EVENTOUT 2 SCK MIL TXD1 PB13 gone USART3 CTS OTG Hs De TW EVENTOUT uondiosep uid pue sjnouid 024261115 6 81881 01 90d 721 99 8 Alternate function mapping continued
109. ExH FSMC_CLK low to FSMC_NEx high 0 2 1 5 ta CLKL NADVL CLK low to FSMC_NADV low 5 ns lqCcLKL low to FSMC NADV high 6 ns NADVH ta cLkL Av FSMC low to FSMC valid x 16 25 0 ns ta cLKL Ai low to FSMC invalid 16 25 8 ns ta CLKL NWEL low to FSMC_NWE low 1 ns ta CLKL NWEH FSMC CLK low to FSMC_NWE high 1 ns taCLKL Data FSMC_D 15 0 valid data after FSMC_CLK low 2 ns taCLKL NBLH FSMC_CLK low to FSMC_NBL high 2 5 1 30 pF 2 Based on characterization not tested in production Doc ID 15818 Rev 9 133 174 Electrical characteristics STM32F20xxx 134 174 PC Card CompactFlash controller waveforms and timings Figure 63 through Figure 68 represent synchronous waveforms together with Table 78 and Table 79 provides the corresponding timings The results shown in this table are obtained with the following FSMC configuration COM FSMC_SetupTime 0x04 COM FSMC_WaitSetupTime 0x07 COM FSMC_HoldSetupTime 0x04 COM FSMC_HiZSetupTime 0x00 ATT FSMC_SetupTime 0x04 ATT FSMC_WaitSetupTime 0x07 ATT FSMC_HoldSetupTime 0x04 ATT FSMC_HiZSetupTime 0x00 IO FSMC SetupTime 0x04 1IO FSMC_WaitSetupTime 0x07 IO FSMC HoldSetupTime 0x04 IO FSMC HiZSetupTime 0x00 TCLRSetupTime 0 TARSetupTime 0 In all timing tables the Tuck is the HCLK clock period Figure 63 PC Card CompactF
110. F then Cio 8 pF Figure 32 Typical application with a 32 768 kHz crystal Resonator with integrated capacitors bonor 5 ui 9 Bias 32 768 kHz controlled STM32F 17531 Doc ID 15818 Rev 9 85 174 Electrical characteristics STM32F20xxx 5 3 9 86 174 Internal clock source characteristics The parameters given in Table 30 and Table 31 are derived from tests performed under ambient temperature and Vpp supply voltage conditions summarized in Table 12 High speed internal HSI RC oscillator Table 30 HSI oscillator characteristics 1 Symbol Parameter Conditions Min Typ Max Unit fusi Frequency 16 MHz User trimmed with the CR _ 1 register Aena 40 10 10590 8 45 oscillator Factory 2 1 Ta 10t085 C 4 4 TA 25 C 1 1 9 HSI oscillator 3 tsutis 2 startup time 22 4 HSI oscillator IDD HSI power consumption 60 80 pA 1 3 3 V T4 40 to 105 C unless otherwise specified 2 Refer to application note AN2868 STM32F10xxx internal RC oscillator HSI calibration available from the ST website www st com 3 Guaranteed by design not tested in production Figure 33 versus temperature Normalized deviation 5 5 15 25 35 45 55 65 75 85 Temperature C 95 105 115
111. F20xxx 2 2 Device overview Figure 5 STM32F20x block diagram NJTRST JTDI CLK NE 3 0 A 23 0 JTCK SWCLK D 31 0 OEN WEN OSN pass controller FSMC lt Eoi elt APES JTDO TRACESWO lt gt SRAM PSRAM NOR Flash Bibel NWAIT IORDY CD NIORD IOWR INT 2 3 LINTN NIIS16 as AF TRACECLK Cortex M3 120 2 Card ATA Flash ART accelerator 5 E RNG or as Ethernet MAC SRAM 112 KB O Camera HSYNC VSYNC 10 100 5 SE interface PIXCLK D 13 0 DM SRAM 16 ULPI CK D 7 0 DIR STP NXT m SCL SDA INTN ID VBUS SOF i Q USB T DM a OTG FS 8 SDA INTN ID VBUS SOF Power managm 12 lt 9 Vpp 1 8 to 3 6 V regulator 3 3 Vto 12 V Vss VDDA VDD VcAP1 2 Pon Supply PA 15 0 C GPIO PORT A Reset Supervision RCLS ini POR PDR PB 15 0 BOR VSSA lt gt GPIO PORT B PLL1 amp 2 4 573 NRST PC 15 0 lt gt GPIO PORTC VDDA VDD Ponsa 02 GPIO PORT D XTAL OSC OSC IN 4 26MHz OSC OUT eso GPIO PORTE Reset amp E 7 lt GPIO PORT F control St
112. FSMC_NIOWR high to FSMC D 15 0 invalid 8TucLK ns ta NCE4_1 Niowr FSMC_NCE4_1 low to FSMC_NIOWR valid 5 1 5 ns th NCEx Niowr NCEx high to FSMC_NIOWR invalid 5TuciK ns 4 FSMC_NCEx low to FSMC_NIORD valid 1 5 th NCEx NIORD FSMC_NCEx high to NIORD valid 5Tucik 0 5 ns tw NIORD FSMC_NIORD low width 8 1 ns end valid before NIORD 9 5 ta NIORD D FSMC_D 15 0 valid after FSMC_NIORD high 0 ns 1 30 pF 2 Based on characterization not tested in production NAND controller waveforms and timings Figure 69 through Figure 72 represent synchronous waveforms together with Table 80 and Table 81 provides the corresponding timings The results shown in this table are obtained with the following FSMC configuration COM FSMC_SetupTime 0x01 COM FSMC_WaitSetupTime 0x03 COM FSMC_HoldSetupTime 0x02 COM FSMC_HiZSetupTime 0x01 ATT FSMC_SetupTime 0x01 ATT FSMC_WaitSetupTime 0x03 ATT FSMC_HoldSetupTime 0x02 ATT FSMC_HiZSetupTime 0x01 Bank FSMC_Bank_NAND MemoryDataWidth FSMC_MemoryDataWidth_16b ECC FSMC ECC Enable ECCPageSize FSMC ECCPageSize 512Bytes TCLRSetupTime 0 TARSetupTime 0 In all timing tables the is the clock period Doc ID 15818 Rev 9 139 174 Electrical characteristics STM32F20xxx Figure 69 NAND controller waveforms for read access
113. Figure 25 Updated Table 20 Typical and maximum current consumption in Sleep mode and added Figure 26 and Figure 27 Updated Table 21 Typical and maximum current consumptions in Stop mode Added Figure 28 Typical current consumption vs temperature in Stop mode Updated Table 22 Typical and maximum current consumptions in Standby mode and Table 23 Typical and maximum current consumptions in mode Updated On chip peripheral current consumption conditions and Table 24 Peripheral current consumption Updated twUSTDBY and twUSTOP and added Note 3 in Table 25 Low power mode wakeup timings Maximum ex and minimum ty 4sg values updated in Table 26 High speed external user clock characteristics Updated C in Table 28 HSE 4 26 MHz oscillator characteristics Updated 12 and tg in Table 29 LSE oscillator characteristics f s 32 768 kHz Added Note 1 and updated 0 and in Table 30 22 Apr 2011 5 2 ia su HS continued HSI oscillator characteristics Added Figure 33 versus temperature Updated f ts sj IDDq sy in Table 31 LSI oscillator characteristics Added Figure 34 ACC s versus temperature Table 32 PLL characteristics removed note 1 updated jitter IDD ip and added Note 2 for jy minimum and maximum values Table 33 PLLI2S audio PLL characteristics removed note 1 updated t
114. Figure 46 ULPI timing diagram Removed note related to ADC calibration in Table 65 Section 5 3 20 12 bit ADC characteristics ADC characteristics tables merged into one single table tables ADC conversion time and ADC accuracy removed Updated Table 66 DAC characteristics Updated Section 5 3 22 Temperature sensor characteristics and Section 5 3 23 monitoring characteristics Update Section 5 3 26 Camera interface DCMI timing specifications Added Section 5 3 27 SD SDIO MMC card host interface SDIO characteristics and Section 5 3 28 RTC characteristics Added Section 6 2 Thermal characteristics Updated Table 89 LQFP176 Low profile quad flat package 24 x 24 x 1 4 mm package mechanical data and Figure 82 LQFP176 Low profile quad flat package 24 x 24 x 1 4 mm package outline Changed tape and reel code to TX in Table 92 Ordering information scheme Added Table 93 Main applications versus package for STM32F2xxx microcontrollers Updated figures in Appendix A 3 USB OTG full speed FS interface solutions and A 4 USB OTG high speed HS interface solutions Updated Figure 92 Audio player solution using PLL PLLI2S USB and 1 crystal and Figure 93 Audio PLL PLLI2S providing accurate I2S clock Doc ID 15818 Rev 9 ky STM32F20xxx Revision history Table 94 Document revision history continued Date 25 Nov 2010 Revision Changes Update I Os in Section Features
115. I or 9 signals for RMII and can be clocked using the 25 MHz or 50 MHz output from the STM32F207xx The STM32F207xx includes the following features e Supports 10 and 100 Mbit s rates e Dedicated DMA controller allowing high speed transfers between the dedicated SRAM and the descriptors see the STM32F20x and STM32F21x reference manual for details Tagged MAC frame support VLAN support Half duplex CSMA CD and full duplex operation MAC control sublayer control frames support 32 bit CRC generation and removal Several address filtering modes for physical and multicast address multicast and group addresses e 32 bit status code for each transmitted or received frame e Internal FIFOs to buffer transmit and receive frames The transmit FIFO and the receive FIFO are both 2 Kbytes that is 4 Kbytes in total e Supports hardware PTP precision time protocol in accordance with IEEE 1588 2008 PTP V2 with the time stamp comparator connected to the TIM2 input e Triggers interrupt when system time becomes greater than target time Doc ID 15818 Rev 9 31 174 Description STM32F20xxx 2 2 27 Controller area network CAN The two CANs are compliant with the 2 0A and B active specifications with a bitrate up to 1 Mbit s They can receive and transmit standard frames with 11 bit identifiers as well as extended frames with 29 bit identifiers Each CAN has three transmit mailboxes two receive FIFOS with 3 stages and 2
116. Linearity Error maximum deviation between any actual transition and the end point correlation line Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 51 Typical connection diagram using the ADC STM32F Sample and hold ADC converter 12 bit converter Cparasitic ai17534 Refer to Table 64 for the values of Rain Ranc and represents the capacitance of the dependent soldering and layout quality plus the pad capacitance roughly 7 pF A high Value downgrades conversion accuracy To remedy this should be reduced Doc ID 15818 Rev 9 119 174 Electrical characteristics STM32F20xxx 120 174 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 52 or Figure 53 depending on whether is connected to or not The 10 nF capacitors should be ceramic good quality They should be placed them as close as possible to the chip Figure 52 Power supply and reference decoupling not connected to STM32F 1 10 nF 1 uF 10 nF See note 1 17535 1 Vref and inputs are available only on 100 pin packages Figure 53 Power supply and reference decoupling Vngr connected to STM32F VREF VDDA See note 1 1 pF 10 nF Vngr VssA See note 1 ai17536
117. MC bank4 PC Card FSMC bank3 NAND NAND2 FSMC bank2 1 FSMC NOR PSRAM 4 FSMC NOR PSRAM 3 FSMC NOR PSRAM 2 FSMC NOR PSRAM 1 Reserved Heserved DCMI Reserved USB OTG FS Reserved USB OTG HS Reserved ETHERNET Reserved DMA2 DMA1 Reserved BKPSRAM Flash interface Reset clock controller RCC Reserved 2 2 9 8 Reserved Port Port H Port Port F Port E Port D Port C Port B Port A Reserved TIM11 TIM10 TIM9 SYSCFG Reserved SPI SDIO Reserved Reserved ADC2 ADC3 Reserved USART6 USART1 Heserved TIM8 PWM2 TIM1 PWM1 Reserved DAC1 DAC2 PWR Reserved 2 1 1223 1262 1201 5 UART4 USART3 USART2 Reserved SPI3 I2S3 5 12 252 Reserved IWDG WWDG RTC amp BKP registers Reserved TIM14 TIM12 TIM7 6 5 4 TIM3 TIM2 ADC1 0 000 1000 OXBFFF FFFF 0 000 0000 0xA000 OF FF 0 9000 0000 Ox9FFF 0 8000 0000 0 7000 0000 Ox7FFF FFFF 0 6 00 0000 0x6FFF 0 6800 0000 0x6BFF 0 6400 0000 0x67FF FFFF 0 6000 0000 0x63FF FFFF 0 5006 1000 OxSFFF 0 5006 0800 0x5006 OFFF 0 5005 0400 0x5006 7FFF 0 5005 0000 0x5005 03FF 0 5004 0000 0x5004 OFFF 0 5000 0000 0x5003 FFFF 0 4002 9400 Ox4FFF 0 4004 0000 0x4007 FFFF 0 4002 9400
118. MC_NADV low 2 ns ta CLKL NADVH low to high 3 ns ta CLKL AV FSMC_CLK low to FSMC_Ax valid x 16 25 0 ns ta CLKL AlV FSMC_CLK low to FSMC_Ax invalid x 16 25 7 5 taCLKL NWEL low to FSMC_NWE low gt 1 ns taCLKL NWEH FSMC_CLK low to FSMC_NWE high 0 ns ta cikL Apiv FSMC low to FSMC_AD 15 0 invalid 0 ns ta cikL bparA A D 15 0 valid data after FSMC low 2 ns ta CLKL NBLH FSMC low to FSMC NBL high 0 5 ns 1 30 pF 2 Based on characterization not tested in production Doc ID 15818 Rev 9 131 174 Electrical characteristics STM32F20xxx Figure 61 Synchronous non multiplexed NOR PSRAM read timings BUSTURN 0 FSMC_CLK FSMC_NEx FSMC_NOE FSMC D 15 0 td CLKL NExL gt 44 th CLKH DV tsu NWAITV CLKH lt lt th CLKH NWA TV d CLKL NADVL gt q CLKL NADVH FSMC_NADV 4 G T WAITCFG 0b WAITPOL Ob su NWAITV CLKH rr th CLKH NWAJTV Table 76 Synchronous non multiplexed NOR PSRAM read timings Symbol Parameter Min Max Unit tw CLK FSMC_CLK period s ta CLKL NExL FSMC low to FSMC NEx low 0 2 2 0 FSMC_CLK low to FSMC_NEx high 0 2 1 ta CLKL NADVL FSMC_CLK low to FSMC_NADV low 25 ns t
119. OUT as AF as AF ai17614b 1 timers connected to APB2 are clocked from TIMxCLK up to 120 MHz while the timers connected to are clocked from TIMxCLK up to 60 MHz 2 USB OTG FS Camera interface and Ethernet are available only in STM32F207xx devices 18 174 Doc ID 15818 Rev 9 ky STM32F20xxx Description 2 2 1 2 2 2 2 2 3 2 2 4 Cortex M3 core with embedded Flash and SRAM The ARM Cortex MG processor is the latest generation of ARM processors for embedded systems It was developed to provide a low cost platform that meets the needs of MCU implementation with a reduced pin count and low power consumption while delivering outstanding computational performance and an advanced response to interrupts The ARM Cortex M3 32 bit RISC processor features exceptional code efficiency delivering the high performance expected from an ARM core in the memory size usually associated with 8 and 16 bit devices With its embedded ARM core the STM32F20x family is compatible with all ARM tools software Figure 5 shows the general block diagram of the STM32F20x family Adaptive real time memory accelerator ART Accelerator The ART Accelerator is a memory accelerator which is optimized for STM32 industry standard Cortex M3 processors It balances the inherent performance advantage of the ARM Cortex M3 over Flash memory technologies which normally requires the processor to wait
120. PI2 1282 SD 6 HS ADC123 11 G8 18 29 35 M5 PC3 I O FT PC3 ETH MIL TX CLK N43 EVENTOUT 19 30 36 12 5 12 12 20 31 37 M1 VssA S Vssa 11 22 51 VREF 5 VREF 27 21 32 38 P1 VREF 5 VREF 13 22 33 39 R1 VDDA S VDDA USART2_CTS UARTA TX ETH CRS 14 E7 23 34 40 PAO WKUP 2 5 8 ETR USART2 UART4_RX 6 REF CLK 15 H8 24 35 41 1 ETH MILRX ADC123_ 1 TIM5_CH2 2 2 EVENTOUT USART2 TX TIM5 CH3 16 9 25 36 42 P2 2 6 2 9 2 CH3 ADC123 IN2 MDIO EVENTOUT ETH CRS 43 F4 2 2 UENTOMT ETH 44 SVENTOUT 12 2_ 1 1 1 145 4 4 4 HS EVENTOUT 46 5 5 I2C2 SDA EVENTOUT 42 174 Doc ID 15818 Rev 9 ky STM32F20xxx Pinouts and pin description Table 6 STM32F20x pin and ball definitions continued Pins e N Main t e 2 e S R Pin name 9 8 function Alternate functions rner lt gt functions E tia
121. Pin name 2 8 function Alternate functions 1 o T after reset S s s o o gt 5 28 E12 PH13 M h29 Eta 14 14 7 1 1 1 A30D13 15 15 5 2 85 Plo 1252 WS DCMI_D13 EVENTOUT K 32 014 PH 8 SPI2_MISO 1 1 1 22 TIM8_ETR SPI2 MOSI H84 C18 252 SD DCMI_D10 EVENTOUT 135 09 Vss 15 5 Vss 15 36 co VDD 15 5 Wop 45 49 A1 76 1091137 A14 14 FT 5 JTCK SWCLK EVENTOUT JTDI SPI3_NSS 50 2 77 11011381 A13 15 JTDI 1253 WS TIM2 ETR SPI1 NSS EVENTOUT 50 1253 UART4_TX SDIO_D2 DCMI_D8 USART3_TX EVENTOUT 51 B3 78 11111391 B14 PC10 FT PC10 UART4_RX SPI3_MISO SDIO D3 DCMI_D4 USART3_RX EVENTOUT 52 79 112 140 B13 PC11 VO FT PC11 5 TX SDIO CK D9 SPI3 MOSI 1253 SD CK EVENTOUT FSMC D2 CAN1 RX EVENTOUT FSMC D3 CAN1 TX EVENTOUT 53 80 11311411 A12 12 12 81 114142 12 PDO PDO 82 115143 C12 PD1 FT PD1 48 174 Doc ID 15818 Rev 9 ky
122. S full speed host only connection Vpp EN GPIO Current limiter ower switch GPIO4IRQ Overcurrent STM32F20xx USB Std A connector ai17296c 1 The current limiter is required only if the application has to support Vgys powered device A basic power switch can be used if 5 V are available on the application board 2 The same application can be developed using the OTG HS FS mode to achieve enhanced performance thanks to the large Rx Tx FIFO and to a dedicated DMA controller Doc ID 15818 Rev 9 155 174 Application block diagrams STM32F20xxx Figure 88 OTG FS full speed connection dual role with internal PHY 5 voltage regulator 1 GPIO Current limiter GPIO IRQ Overcurrent power switch 2 STM32F20xxx USBmicro AB connector 17294 External voltage regulator only needed when building a Vays powered device 2 The current limiter is required only if the application has to support Vgyg powered device A basic power Switch can be used if 5 V are available on the application board 3 The ID pin is required in dual role only 4 The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx Tx FIFO and to a dedicated DMA controller 156 174 Doc ID 15818 Rev 9 STM32F20xxx Application block diagrams A 4 USB OTG high speed HS interface so
123. SOF synchronization of input output audio streaming using a hardware Codec Figure 91 Complete audio player solution 2 LCD touch Screen Control buttons XTAL 25 MHz or 14 7456 MHz USB Mass storage i audio Audio DAC ampli 1 1 1 audio streaming 16040 1 SOF start of frame 158 174 Doc ID 15818 Rev 9 STM32F20xxx Application block diagrams Figure 92 Audio player solution using PLL PLLI2S USB and 1 crystal PLLI2S x N2 ai18412b Figure 93 Audio PLL PLLI2S providing accurate 125 clock Phase lock detector M 1 2 3 64 125 256 x 11 2896 2 44 1 2 12 2880 MHz for 48 0 kHz IPSCOM CK 1250 2 3 4 129 ai16041b ky Doc ID 15818 Rev 9 159 174 STM32F20xxx Application block diagrams Figure 94 Master clock MCK used to drive the external audio DAC 125 controller 2 3 4 129 125 280 125 256 x Fsaypio 11 2896 MHz for 44 1 kHz 12 2880 MHz for 48 0 kHz 125 SCK 125 8 16 bit stereo 2125 4 for 32 bit stereo 16042 1 125 SCKis the 125 serial clock to the external audio DAC not be confused with 125 CK Figure 95 Master clock MCK not used to drive the external audio DAC 125 controller 25 CK Feaupio
124. STM32F20xxx Electrical characteristics Figure 66 Card CompactFlash controller waveforms for attribute memory write access FSMC 4 1 FSMC 4 2 High tv NCE4_1 A th NCE4_1 Al FSMC A10 A FSMC_NIOWR FSMC_NIORD td NREG NCE4_1 th NCE4_1 NREG gt FSMC_NREG N td NCE4_1 NWE tw NWE FSMC_NWE Id NWE NCEA 1 1 NOE tv NWE D FSMC_DJ 7 0 1 31148980 1 Only data bits O 7 are driven bits 8 15 remains Hi Z Figure 67 PC Card CompactFlash controller waveforms for space read access FSMC 4 1 5 4 2 th NCE4_1 Al 5 A 10 0 NREG FSMC_NWE FSMC NOE FSMC NIOWR td NIORD NCE4_1 FSMC_NIORD tsu D NIORD td NIORD D FSMC_D 15 0 ai14899B Doc ID 15818 Rev 9 137 174 Electrical characteristics STM32F20xxx Figure 68 PC Card CompactFlash controller waveforms for I O space write access FSMC_NCE4_1 5 4 2 5 A 10 0 5 NREG 5 NWE FSMC NOE FSMC NIOWR FSMC D 15 0 td NCE4_1 NIOWR ATTXHIZ 1 th NCE4_1 Al tw NIOWR th NIOWR D FSMC_NIORD ai14900c Table 78 Switching characteristics for PC Card CF read and write cycles in attribute common space Symbol Parameter Min Max Unit l NCEx
125. Table 62 Dynamics characteristics Ethernet MAC signals for Updated Note 2 IWREF4 gt and 64 characteristics Updated Note 3 and note concerning ADC accuracy vs negative injection current in Table 65 ADC accuracy Updated Vote 1 in Table 66 DAC characteristics Updated Section Figure 83 UFBGA176 25 ultra thin fine pitch ball grid array 10 x 10 x 0 6 mm package outline 172 174 Doc ID 15818 Rev 9 ky STM32F20xxx Revision history Table 94 Document revision history continued Date Revision Changes Appendix A 1 Main applications versus package removed number of address lines for FSMC NAND in Table 93 Main applications versus 9 package for STM32F2xxx microcontrollers continued Appendix A 5 Complete audio player solutions updated Figure 90 Complete audio player solution 1 and Figure 91 Complete audio player solution 2 24 Apr 2012 Doc ID 15818 Rev 9 173 74 STM32F20xxx Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the c
126. USB HS characteristics Table 57 shows the USB HS operating voltage Table 57 Symbol USB HS DC electrical characteristics Parameter Min Max Unit Input level Vpp USB OTG HS operating voltage 2 7 3 6 V 1 Allthe voltages are measured from the local ground potential Table 58 Clock timing parameters Parameter Frequency first transition 8 bit 10 Symbol FSTART_sBIT Min Nominal 60 Max Unit MHz Frequency steady state 500 ppm FsSTEADY 60 60 03 MHz Duty cycle first transition 8 bit 10 DsTART_8BIT 50 Duty cycle steady state 500 ppm DsrEADY 50 50 025 Time to reach the steady state frequency and duty cycle after the first transition TsrEADY ms Clock startup time after the de assertion of SuspendM Peripheral TsraRT ms Host TsrART HOST PHY preparation time after the first transition of the input clock TPREP us 1 Guaranteed by design not tested in production Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 46 ULPI timing diagram Clock t Control In E DIR is THD data In 8 bit t t D DC Control out STP 100 data 8 bit Table 59 ULPI timing ai17361c
127. WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2012 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 15818 Rev 9 175 175
128. a CLKL NADVH FSMC_CLK low to FSMC_NADV high 4 2 ta CLKL AV FSMC_CLK low to FSMC_Ax valid x 16 25 0 ns ta CLKL AlV FSMC_CLK low to FSMC_Ax invalid x 16 25 3 m la CLKL NOEL 5 low to NOE low 1 5 taCLKL NOEH low to FSMC_NOE high 15 ng tsu DV CLKH FSMC D 15 0 valid data before FSMC_CLK high 8 _ hs n CLKH DV FSMC D 15 0 valid data after high 3 5 ns 1 C 30pF 2 Based on characterization not tested in production 132 474 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 62 Synchronous non multiplexed PSRAM write timings td CLKL N FSMC_NADV tw CLK T lt ta CLKL NExL 7 44 FSMC_NEx FSMC_A 25 0 gt tq CLKL NWEL FSMC_NWE td CLKL Data FSMC D 15 0 FSMC NWAIT WAITCFG 0b WAITPOL 0b gt lt Pr tw CLK r 1 1 1 ADVL ta CLKL AV tsu NWAITV CLKH BUSTURN 0 td CLK th CLKH NWAITV q CLKLENWEH td CLKL Data 2 00 4 1 4 FSMC NBL 31149939 Table 77 Synchronous non multiplexed PSRAM write timings 1 2 Symbol Parameter Min Max Unit lw CLK FSMC_CLK period 2 1 ns ta CLKL NExL FSMC low to FSMC_NEx low 0 2 1 ns ta CLKL N
129. able 56 USB OTG FS electrical characteristics Updated Vpp minimum value in Table 60 Ethernet DC electrical characteristics Updated Table 64 ADC characteristics and Rap equation Updated Ray equation Updated Table 66 DAC characteristics Updated tsrTanr in Table 67 TS characteristics Updated typical value in Table 68 monitoring characteristics Updated Table 69 Embedded internal reference voltage Modified FSMC_NOE waveform in Figure 55 Asynchronous non multiplexed SRAM PSRAM NOR read waveforms Shifted end of FSMC_NEx NADV addresses NWE NOE NWAIT of a half FSMC_CLK period changed tq cLKH NExH O taCLKL NExH gt ta CLKH AlV O ta CLKL AIV ta CLKH NOEH 10 fa cLkL NoEH and tq CLKH NWEH O ta CLKL and updated data latency from 1 to 0 in Figure 59 Synchronous multiplexed NOR PSRAM read timings Figure 60 Synchronous multiplexed PSRAM write timings Figure 61 Synchronous non multiplexed NOR PSRAM read timings and Figure 62 Synchronous non multiplexed PSRAM write timings Changed 10 ta CLKL NExH gt ta CLKH AIV O ta cLKL AIV ta CLKH NOEH O ta cLKL NoEH ta CLKH NWEH 10 ta cLKL NwEH and modified minimum value in Table 74 Table 75 Table 76 and Table 77 Updated note 2 in Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 and Table 77 Modified in Figure 68 PC Card CompactFlash controller waveforms for I O spa
130. ackup circuitry OSC32K RTC Wakeup logic Backup registers backup RAM Kernel logic CPU digital Level shifter amp RAM Flash memory Analog RCs PLL 175274 Each power supply pair must be decoupled with filtering ceramic capacitors shown above These capacitors must be placed as close as possible to or below the appropriate pins on the underside of the PCB to ensure the good functionality of the device To connect REGOFF and IRROFF pins refer to Section 2 2 16 Voltage regulator Doc ID 15818 Rev 9 The two 2 2 uF ceramic capacitors should be connected when the voltage regulator is OFF The 4 7 ceramic capacitor must be connected to one of the Vpp pin STM32F20xxx Electrical characteristics 5 1 7 Current consumption measurement Figure 19 Current consumption measurement scheme 5 2 VDDA ai14126 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 9 Voltage characteristics Table 10 Current characteristics and Table 11 Thermal characteristics may cause permanent damage to the device These are stress ratings only and functional operation of the device at these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 9 Voltage characteristics Symbol Ratings Min Max Unit Vpp Vss External main supply voltage including
131. anagement features with minimum interrupt latency External interrupt event controller EXTI The external interrupt event controller consists of 23 edge detector lines used to generate interrupt event requests Each line can be independently configured to select the trigger event rising edge falling edge both and can be masked independently A pending register maintains the status of the interrupt requests The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period Up to 140 GPIOs can be connected to the 16 external interrupt lines Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock The 16 MHz internal RC oscillator is factory trimmed to offer 1 accuracy The application can then select as system clock either the RC oscillator or an external 4 26 MHz clock source This clock is monitored for failure If failure is detected the system automatically switches back to the internal RC oscillator and a software interrupt is generated if enabled Similarly full interrupt management of the PLL clock entry is available when necessary for example if an indirectly used external oscillator fails The advanced clock controller clocks the core and all peripherals using a single crystal or oscillator In particular the ethernet and USB OTG FS peripherals can be clocked by the system clock Several prescalers and PLLs allow the configuration of the two AHB
132. andby 1 65 to 3 6 V C amoronra 21 Y 1 25 05632 5 0 gt GPIO Po 3 OSC32 OUT C GPIO PORT I ere lt re k 4 channels ETR as AF c 4 channels ETR as AF Kr 4 channels ETR as AF Kr 3 4 channels Kr Kr DMA1 AHB APB2 AHB APB1 MOAF EXT IT WKUP TIM12 2 channels as AF 00 0 ck as at SDIO MMC 166 K N 1 channel as AF 4 compl channels TIM1 CH 1 4 4 channels CMT Cura ERI PWM TiM14 166 1 channel AF 4 compl channels TIM1_CH 1 4 4 channels TIM1 CH 1 4 ETR BKIN as AF TIM8 PWM 16 771777 USART2 Smcard RX TX CK smcard RX TX CK USART3 CTS RTS as AF TIM9 gt 2 channels as AF ichannelasAF lt _ 2 c umm RX TX as AF u 69 Crac mre IO ee MOSI MISO Cy s SCL SDA as AF SCK NSS as AF 12C2 SMBUS KCL SDA SMBA as AF VppnEF Apc gt K I2C3 SMBUS SCL SDA SMBA 8 analog inputs common VDDA to the 3 ADCs 8 analog inputs common gt DAC1 to ADC1 amp 2 m gt 9 Km Rx 8 analog inputs to ADC3 2 TIE OUT DAC2
133. ature pin loading device software configuration operating frequencies I O pin switching rate program location in memory and executed binary code The current consumption is measured as described in Figure 19 Current consumption measurement scheme All Run mode current consumption measurements given in this section are performed using CoreMark code 70 74 Doc ID 15818 Rev 9 3 STM32F20xxx Electrical characteristics Typical and maximum current consumption The MCU is placed under the following conditions e At startup all pins are configured as analog inputs by firmware e All peripherals are disabled except if it is explicitly mentioned e The Flash memory access time is adjusted to fic frequency 0 wait state from 0 to 30 MHz 1 wait state from 30 to 60 MHz 2 wait states from 60 to 90 MHz and wait states from 90 to 120 MHz e When the peripherals are enabled HCLK is the system clock fpc 4 and 2 2 except is explicitly mentioned e Themaximum values are obtained for 3 6 V and maximum ambient temperature and the typical values for 25 and 3 3 V unless otherwise specified Table 18 Typical and maximum current consumption in Run mode code with data processing running from Flash memory ART accelerator disabled Symbol Parameter BD in Run mode
134. buses the high speed APB 2 and the low speed APB1 domains The maximum frequency of the two AHB buses is 120 MHz and the maximum frequency the high speed APB domains is 60 MHz The maximum allowed frequency of the low speed APB domain is 30 MHz The devices embed a dedicate PLL PLLI2S which allow to achieve audio class performance In this case the 125 master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz Doc ID 15818 Rev 9 ky STM32F20xxx Description 2 2 13 2 2 14 2 2 15 2 2 16 Boot modes At startup boot pins are used to select one out of three boot options Boot from user Flash Boot from system memory e Boot from embedded SRAM The boot loader is located in system memory It is used to reprogram the Flash memory by using USART1 PA9 PA10 USART3 PC10 PC11 or PB10 PB11 CAN2 PB5 PB13 USB OTG FS in Device mode PA11 PA12 through DFU device firmware upgrade Power supply schemes Vpp 1 8 to 3 6 external power supply for I Os and the internal regulator when enabled provided externally through pins WLCSP package Vpp ranges from 1 7 to 3 6 V VppA 1 8 to 3 6 external analog power supplies for ADC DAC Reset blocks RCs PLL and Vssa must be connected to Vpp and Vas respectively 1 65 to 3 6 V power supply for RTC external clock 32 kHz oscillator and backup registers t
135. capacitor until a functional disturbance occurs This test is compliant with the IEC 61000 4 4 standard A device reset allows normal operations to be resumed The test results are given in Table 39 They are based on the EMS levels and classes defined in application note AN1709 Doc ID 15818 Rev 9 93 174 Electrical characteristics STM32F20xxx Table 39 EMS characteristics Symbol Parameter Conditions vel Class Voltage limits to be applied any I O pin to 3 3 V LQFP100 T 25 VFESD induce a functional disturbance fheLk 75 MHz conforms to eB IEC 61000 4 2 Fast transient voltage burst limits to be Vpp 3 3 V LQFP100 T4 25 C applied through 100 pF on Vpp and Vss 75 MHz conforms to 4A pins to induce a functional disturbance IEC 61000 4 2 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Software recommendations The software flowchart must include the management of runaway conditions such as e Corrupted program counte
136. capacitor value to 2 2 UF in Figure 18 Power supply scheme Removed DAC modified ADC limitations and updated compensation for 1 8 to 2 1 V range in Table 13 Limitations depending on the operating power supply range Added VBoRM IRUSH in Table 17 Embedded reset and power control block characteristics Removed table Typical current consumption in Sleep mode with Flash memory in Deep power down mode Merged typical and maximum current consumption sections and added Table 18 Typical and maximum current consumption in Run mode code with data processing running from Flash memory ART accelerator disabled Table 19 Typical and maximum current consumption in Run mode code with data processing running from Flash memory ART accelerator enabled or RAM Table 20 Typical and maximum current consumption in Sleep mode Table 21 Typical and maximum current consumptions in Stop mode Table 22 Typical and maximum current consumptions in Standby mode and Table 23 Typical and maximum current consumptions in mode Update Table 32 Main PLL characteristics and added Section 5 3 11 PLL spread spectrum clock generation SSCG characteristics Added Note 8 for CIO in Table 44 I O static characteristics Updated Section 5 3 18 TIM timer characteristics Added Table 47 NRST pin characteristics Updated Table 50 characteristics Removed 8 bit data in and data out waveforms from
137. ce write access Modified FSMC_NCEx signal in Figure 69 controller waveforms for read access Figure 70 NAND controller waveforms for write access Figure 71 NAND controller waveforms for common memory read access and Figure 72 NAND controller waveforms for common memory write access Specified Full speed FS mode for Figure 89 USB OTG HS peripheral only connection in FS mode and Figure 90 USB OTG HS host only connection in FS mode 3 Doc ID 15818 Rev 9 STM32F20xxx Revision history Table 94 Document revision history continued Date Revision Changes Added SDIO in Table 2 STM32F205xx features and peripheral counts Updated for 5V tolerant pins in Table 9 Voltage characteristics Updated jitter parameters description in Table 32 Main PLL characteristics Remove jitter values for system clock in Table 33 PLLI2S audio PLL characteristics Updated Table 40 EMI characteristics Update Note 2 Table 50 characteristics Updated Avg Slope typical value and Ts temp minimum value in 14 Jun 2011 7 Table 67 TS characteristics Updated Ts minimum value in Table 68 monitoring characteristics Updated Ts mimimum value in Table 69 Embedded internal reference voltage Added Software option in Section 7 Part numbering In Table 93 Main applications versus package for STM32F2xxx microcontrollers renamed USB1 and USB2 USB OTG FS and USB OTG HS respect
138. cified Table 24 Peripheral current consumption Peripheral Typical consumption at 25 C Unit 0 45 0 43 GPIO 0 46 D 0 44 0 44 GPIO F 0 42 GPIO G 0 44 GPIO H 0 42 AHB1 GPIO I 0 43 HS ULPI 3 64 CRC 147 BKPSRAM 0 21 DMA1 2 76 DMA2 2 85 ETH MAC ETH MAC TX 2 99 ETH MAC RX ETH MAC PTP OTG FS 3 16 AHB2 DOMI 0 60 AHBS3 FSMC 1 74 Doc ID 15818 Rev 9 79 174 Electrical characteristics 80 174 Doc ID 15818 Rev 9 STM32F20xxx Table 24 Peripheral current consumption continued Peripheral Typical consumption at 25 C Unit TIM2 0 61 TIM3 0 49 TIM4 0 54 5 0 62 6 0 20 0 20 12 0 36 TIM13 0 28 TIM14 0 25 USART2 0 25 USART3 0 25 m UART4 0 25 UART5 0 26 12 1 0 25 12 2 0 25 12 3 0 25 SPI2 0 20 0 10 SPI3 0 18 0 09 CAN1 0 31 CAN2 0 30 DAC channel 102 1 11 DAC channel 19 1 11 PWR 0 15 WWDG 0 15 3 STM32F20xxx Electrical characteristics Table APB2 24 Peripheral current consumption continued Peripheral Typical consumption at 25 C SDIO 0 69 TIM1 1 06 TIM8 1 03 TIM9 0 58 TIM10 0 37 11 0 39 1 2 13 20 2 04 3 212 SPI1 1 20 USART1 0 38 USART6 0 37 Unit mA ONS 5 3 7 Wakeup time from low power mode External clock is 25 MHz HSE o
139. com help index jsp topic com arm doc ddi0337e Doc ID 15818 Rev 9 ky STM32F20xxx Description 2 Note Description The STM32F20x family is based on the high performance Cortex M3 32 bit RISC core operating at a frequency of up to 120 MHz The family incorporates high speed embedded memories Flash memory up to 1 Mbyte up to 128 Kbytes of system SRAM up to 4 Kbytes of backup SRAM and an extensive range of enhanced I Os and peripherals connected to two APB buses two AHB buses and a 32 bit multi AHB bus matrix The devices also feature an adaptive real time memory accelerator ART Accelerator which allows to achieve a performance equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 120 MHz This performance has been validated using the CoreMark benchmark All devices offer three 12 bit ADCs two DACs a low power RTC twelve general purpose 16 bit timers including two PWM timers for motor control two general purpose 32 bit timers a true number random generator RNG They also feature standard and advanced communication interfaces New advanced peripherals include an SDIO an enhanced flexible static memory control FSMC interface for devices offered in packages of 100 pins and more and a camera interface for CMOS sensors The devices also feature standard peripherals Upto three I Cs e Three SPls two 1255 To achieve audio class accuracy the 25 peripherals can
140. depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark Doc ID 15818 Rev 9 ky STM32F20xxx Package characteristics Figure 75 LQFP64 10 x 10 mm 64 pin low profile quad flat package outline Figure 76 Recommended footprint 11 g 9 28 31143980 49 05 0 3 32 64 5 Y 34 12 7 ai14909 1 Drawing is not to scale 2 Dimensions are in millimeters Table 85 LQFP64 10 x 10 mm 64 pin low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 1 0 050 0 150 0 0020 0 0059 2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 12 000 0 4724 D1 10 000 0 3937 E 12 000 0 4724 E1 10 000 0 3937 e 0 500 0 0197 0 0 3 5 7 0 3 59 7 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 Number of pins 64 1 Values in inches are converted from mm and rounded to 4 decimal digits 57 Doc ID 15818 Rev 9 145 174 Package characteristics STM32F20xxx Figure 77 WLCSP64 2 0 400 mm pitch wafer level chip size package outline A
141. e an external PHY device connected to the ULPI is required The USB OTG HS peripheral is compliant with the USB 2 0 specification and with the OTG 1 0 specification It has software configurable endpoint setting and supports suspend resume The USB OTG full speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator The major features are e Combined Rx and Tx FIFO size of 1024x 35 bits with dynamic FIFO sizing e Supports the session request protocol SRP and host negotiation protocol HNP e 6 bidirectional endpoints e 12 host channels with periodic OUT support e Internal OTG PHY support e External HS or HS OTG operation supporting ULPI in SDR mode The OTG PHY is connected to the microcontroller ULPI port through 12 signals It can be clocked using the 60 MHz output e Internal USB DMA e HNP SNP IP inside no need for any external resistor e ForOTG Host modes a power switch is needed in case bus powered devices are connected 32 174 Doc ID 15818 Rev 9 ky STM32F20xxx Description 2 2 30 2 2 31 2 2 32 Audio PLL PLLI2S The devices feature an additional dedicated PLL for audio 125 application It allows to achieve error free 155 sampling clock accuracy without compromising on the CPU performance while using USB peripherals The PLLI2S configuration can be modified to manage an 125 sample rate change without disabling the main PLL PLL used for CPU USB
142. e range 7 9 V Minimum current sunk on IPP the pin 18 8 Cumulative time during _ _ tvpp which Vpp is applied 1 Guaranteed by design tested in production 2 The maximum programming time is measured after 100K erase operations 3 Vpp should only be connected during programming erasing Table 38 Flash memory endurance and data retention Value Symbol Parameter Conditions Unit Min TA 40 to 85 C 6 suffix versions N Endurance kcycles END TA 40 to 105 C 7 suffix versions 19 y 1 2 at TA 85 C 30 Data retention 1 2 at 105 C 10 Years 10 kcycles at Ty 55 20 1 Based on characterization not tested in production 2 Cycling performed over the whole temperature range 5 3 13 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization Functional EMS electromagnetic susceptibility While a simple application is executed on the device toggling 2 LEDs through I O ports the device is stressed by two electromagnetic events until a failure occurs The failure is indicated by the LEDs Electrostatic discharge ESD positive and negative is applied to all device pins until a functional disturbance occurs This test is compliant with the IEC 61000 4 2 standard e FTB A burst of fast transient voltage positive and negative is applied to and Vgs through a 100 pF
143. eel 1 66 pins is available on WLCSP package only For a list of available options speed package etc or for further information on any aspect of this device please contact your nearest ST sales office 152 174 Doc ID 15818 Rev 9 ky STM32F20xxx Application block diagrams Appendix Application block diagrams A 1 Main applications versus package Table 93 gives examples of configurations for each package Table 93 Main applications versus package for STM32F2xxx microcontrollers 64 pins 100 pins 144 pins 176 pins Config Config Config Config Config Config Config Config Config Config Config Config Config 1 2 3 1 2 3 4 1 2 3 4 1 2 USB FS 2 FS gs x x x x HS T X x X X X X X USB OTG HS E x x x x x x x x FS X X X X X X X Ethernet MII 2 X x x x x SPI I2S2 nime X X X X X X X X X X SDIO SDIO X X X X X X X 8 bit X X X X X Data SDIO SDIO SDIO SDIO 22 Mos x x P x x x pemi 12 bit X X X X X 14 bit Dis X X X X NOR RAM X X X X X X X X X X Muxed NOR FSMC HAN x x x x x x NAND x x x x CF x X X X X X CAN X X X X X X X X 1 Not available STM32F2x7xx 2 Notavailable on STM32F2x5xx ky Doc ID 15818 Rev 9 153 174 Applicat
144. era interface 34 2 2 32 True random number generator RNG 34 2 2 33 GPIOs general purpose inputs outputs 35 2 2 34 ADCs analog to digital 35 2 2 35 digital to analog 35 2 2 36 Temperature 36 2 2 37 Serial wire JTAG debug port 36 2 2 38 Embedded Trace Macrocell 36 3 Pinouts and pin description 37 4 Memory mapping 60 5 Electrical characteristics 62 5 1 Parameter conditions 62 5 1 1 Minimum and maximum values 62 5 1 2 Typical values u deseen ae eee lee ace hm ERA Rx 62 5 1 3 Typical curves 62 5 1 4 Loading capacitor 62 5 1 5 Pin input voltage lisi mv ER RE ER 62 5 1 6 Power supply scheme 63 5 1 7 Current consumption measurement 64 5 2 Absolute maximum ratings 64 53 Operating conditions
145. ernate function characteristics SDA and SCL Doc ID 15818 Rev 9 103 174 Electrical characteristics STM32F20xxx 104 174 Table 50 characteristics Standard mode 1220 Fast mode 12 1 0 Symbol Parameter Unit Min Max Min Max twscii SCL clock low time 4 7 1 3 tw SCLH SCL clock high time 4 0 0 6 SDA setup time 250 100 SDA data hold time 0 0 9009 SDA and SCL rise time 1000 2040 10 300 ns SDA and SCL fall time 300 300 Start condition hold time 4 0 0 6 Repeated Start condition us IsuSTA setup time cd 06 tsusro Stop condition setup time 4 0 0 6 us Stop to Start condition time Iw STO STA bus free 4 7 1 3 load for each bus _ 400 _ 400 pF 1 Guaranteed by design not tested in production 2 must be at least 2 MHz to achieve standard mode 2 frequencies It must be at least 4 MHz to achieve fast mode I C frequencies and a multiple of 10 MHz to reach the 400 kHz maximum fast mode clock 3 The maximum Data hold time has only to be met if the interface does not stretch the low period of the SCL signal Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 39 12 bus waveforms and measurement circuit VDD VDD STM32Fxx
146. for input capture output compare PWM or one pulse mode Doc ID 15818 Rev 9 ky STM32F20xxx Description 2 2 21 2 2 22 output They can be synchronized with the TIM2 TIM3 5 full featured general purpose timers They can also be used as simple time bases Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation They can also be used as a generic 16 bit time base Independent watchdog The independent watchdog is based on a 12 bit downcounter and 8 bit prescaler It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock it can operate in Stop and Standby modes It can be used either as a watchdog to reset the device when a problem occurs or as a free running timer for application timeout management It is hardware or software configurable through the option bytes The counter can be frozen in debug mode Window watchdog The window watchdog is based on a 7 bit downcounter that can be set as free running It can be used as a watchdog to reset the device when a problem occurs It is clocked from the main clock It has an early warning interrupt capability and the counter can be frozen in debug mode SysTick timer This timer is dedicated to real time operating systems but could also be used as a standard downcounter It features e A24 bit downcounter e Autoreload capability e Maskable system interrupt generati
147. fore the first byte Figure 44 125 master timing diagram Philips protocol CK output 80 MT th SD_MT SDtransmit LSB transmit Bitn transmit LSB transmit SDreceive LSB receive Bitn receive X LSB receive ai14884b 1 Based on characterization not tested in production 2 LSB transmit receive of the previously transmitted byte LSB transmit receive is sent before the first byte 110 174 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics 4 USB OTG FS characteristics The USB OTG interface is USB IF certified Full Speed This interface is present in both the USB OTG HS and USB OTG FS controllers Table 54 USB FS startup time Symbol Parameter Max Unit teranrup USB OTG FS transceiver startup time 1 us 1 Guaranteed by design not tested in production Table 55 USB OTG FS DC electrical characteristics Symbol Parameter Conditions Min Max Unit Voo USB OTG FS operating 3 00 36 voltage 3 p 05 FS P Differential input sensitivity USB HS DP DM 0 2 levels i Vom Differential common mode Includes Vp range 0 8 _ 25 V range 3 Single ended receiver _ VSE threshold 20 Output Static output level low R of 1 5 to 3 6 0 3 levels Static output level high RL of 15 to Vas 2 8 3 6 11
148. gh speed peripherals work simultaneously Multi AHB matrix Bus matrix S ai15963b 20 174 Doc ID 15818 Rev 9 ky STM32F20xxx Description 2 2 8 2 2 9 DMA controller DMA The devices feature two general purpose dual port DMAs DMA1 and DMA2 with 8 streams each They are able to manage memory to memory peripheral to memory and memory to peripheral transfers They share some centralized FIFOs for APB AHB peripherals support burst transfer and are designed to provide the maximum peripheral bandwidth AHB APB The two DMA controllers support circular buffer management so that no specific code is needed when the controller reaches the end of the buffer The two DMA controllers also have a double buffering feature which automates the use and switching of two memory buffers without requiring any special code Each stream is connected to dedicated hardware DMA requests with support for software trigger on each stream Configuration is made by software and transfer sizes between source and destination are independent The DMA can be used with the main peripherals SPI and 125 USART UART General purpose basic and advanced control timers TIMx DAC SDIO Camera interface DCMI ADC Flexible static memory controller FSMC The FSMC is embedded in all STM32F20x devices It has four Chip Select outputs supporting the following modes PC Card Compact Flash SRAM PSRAM NOR Flash and NAND Fla
149. h no load worst code OxF1C 50 75 at 3 6 V in terms of DC consumption on the inputs _ 280 380 UA load middle code 0x800 DAC DC VDDA current on the Inputs consumption in quiescent With no load worst code 1 mode Standby mode 475 625 UA at Vgge 3 6 V in terms of DC consumption on the inputs Given for the DAC in 10 bit Differential non linearity 7 0 5 LSB configuration DNL Difference between two consecutive code 1LSB Given for the DAC in 12 bit 2 LSB configuration ky Doc ID 15818 Rev 9 121 174 Electrical characteristics STM32F20xxx Table 66 DAC characteristics continued Symbol Parameter Min Typ Max Unit Comments Integral non linearity _ _ 1 LSB Given for the DAC in 10 bit difference between configuration INL measured value at Code i and the value at Code i on a Given for the DAC in 12 bit line drawn between Code 0 4 LSB configuration and last Code 1023 _ _ 10 Given for the DAC in 12 bit Offset error configuration difference between for the DAC in 10 bit at Offset measured value at Code 2 3 LSB d 28 BU 0x800 and the ideal value 2 _ _ Given for the DAC in 12 bit at 12 LSB Vera 3 6 V eain err r _ 1 405 Given for the DAC in 12 bit error configuration Settling time full scale for a 10 bit input code transition 3 between the lowest and the I lt 50 pF
150. her reduced by up to 50 as part of ST continuous improvement of test procedures New versions of the datasheet will be released to reflect these changes Figure 28 Typical current consumption vs temperature Stop mode Ipp srop Temperature 0 stop mr flhstop dd stop mr flhdeep dd stop flhstop 144 stop flhdeep MS19020V1 1 All typical and maximum values from table 18 and figure 26 will be reduced over time by up to 50 as part of ST continuous improvement of test procedures New versions of the datasheet will be released to reflect these changes Doc ID 15818 Rev 9 77 174 Electrical characteristics STM32F20xxx Table 22 Typical and maximum current consumptions in Standby mode Typ Max Symbol Parameter Conditions 85 105 Unit Vpp 18V 24V 33 Voo 3 6 V Backup SRAM ON low speed 1 1 oscillator and RTC ON 9 40 m dis Supply current Backup SRAM OFF low 1 1 8 in A speed oscillator and ON 24 d d Te E uA mode Backup SRAM ON RTC OFF 2 4 2 6 3 0 12 50 24 80 Backup SRAM OFF RTC 1 7 1 9 22 9 80 19 20 1 Based on characterization not tested production Table 23 Typical and maximum current consumptions in mode Typ Max 25 85
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152. hrough power switch when Vpp is not present Refer to Figure 18 Power supply scheme for more details Power supply supervisor The devices have an integrated power on reset POR power down reset PDR circuitry coupled with a Brownout reset BOR circuitry At power on BOR is always active and ensures proper operation starting from 1 8 V After the 1 8 V BOR threshold is reached the option byte loading process starts either to confirm or modify default thresholds or to disable BOR permanently Three BOR thresholds are available through option bytes The device remains in reset mode when is below a specified threshold or without the need for an external reset circuit On devices WLCSP package BOR can be inactivated by setting IRROFF to Vpp see Section 2 2 16 Voltage regulator The devices also feature an embedded programmable voltage detector PVD that monitors the Vpp VppA power supply and compares it to the Vpyp threshold An interrupt can be generated when Vpp VppA drops below the Vpyp threshold and or when Vpp VppA is higher than the Vpyp threshold The interrupt service routine can then generate a warning message and or put the MCU into a safe state The PVD is enabled by software Voltage regulator The regulator has five operating modes e Regulator ON Main regulator mode MR Low power regulator LPR Power down e Regulator OFF A Regulator OFF internal reset ON
153. i ocio jitter IDD pi 125 and IDDA PLLI2S added Note 3 for fpLLI2S_IN minimum and maximum values Added Note 1 in Table 34 SSCG parameters constraint Updated Table 35 Flash memory characteristics Modified Table 36 Flash memory programming and added Note 2 for Updated tprog and added Note 1 in Table 37 Flash memory programming with Vpp Modified Figure 38 Recommended NRST pin protection Updated Table 40 EMI characteristics and EMI monitoring conditions in Section Electromagnetic Interference EMI Added Note 2 related to Table 41 ESD absolute maximum ratings Updated Table 44 I O static characteristics Added Section 5 3 15 current injection characteristics Modified maximum frequency values and conditions in Table 46 AC characteristics Updated tresctim in Table 48 Characteristics of TIMx connected to the APB1 domain Modified tresctimy and fexr Table 49 Characteristics of TIMx connected to the APB2 domain Doc ID 15818 Rev 9 167 74 Revision history STM32F20xxx Table 94 Document revision history continued Date 22 Apr 2011 168 174 Revision 6 continued Changes Changed twigckH to tw scLH twsckL 10 tw scLL tresc to 1821 and to in Table 50 characteristics and in Figure 39 bus AC waveforms and measurement circuit Added Table 55 USB OTG FS DC electrical characteristics and updated T
154. ign guide for ST microcontrollers available from the ST website www st com For information on electing the crystal refer to the application note AN2867 Oscillator design guide for ST microcontrollers available from the ST website www st com Figure 31 Typical application with an 8 MHz crystal Resonator with integrated capacitors CH 4 MHz Bias controlled T resonator B i STM32F Clo EXT 17530 1 value depends on the crystal characteristics Low speed external clock generated from a crystal ceramic resonator The low speed external LSE clock can be supplied with a 32 768 kHz crystal ceramic resonator oscillator All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 29 In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal Doc ID 15818 Rev 9 ky STM32F20xxx Electrical characteristics Note Note Caution resonator manufacturer for more details on the resonator characteristics frequency package accuracy Table 29 LSE oscillator characteristics f s 32 768 kHz 0 Symbol Parameter Conditions Min Typ Max Unit Feedback resistor 18 4 MO Ipp LSE
155. igure 36 show the main PLL output clock waveforms in center spread and down spread modes where FO is fpLL_OUT nominal Tmode is the modulation period md is the modulation depth Figure 35 PLL output clock waveforms in center spread mode Frequency PLL_OUT tmode 2 tmode Time ai17291 Figure 36 PLL output clock waveforms in down spread mode Frequency PLL_OUT Time tmode 2 tmode ai17292 5 3 12 Memory characteristics Flash memory The characteristics are given at TA 40 to 105 C unless otherwise specified Table 35 Flash memory characteristics Symbol Parameter Conditions Min Typ Max Unit Write Erase 8 bit mode _ 5 _ Vpp 1 8 V Write Erase 16 bit mode Supply current Vpp 2 1 V 8 mA Write Erase 32 bit mode _ 12 Vpp 3 3 V ky Doc ID 15818 Rev 9 91 174 Electrical characteristics STM32F20xxx 92 174 Table 36 Flash memory programming Symbol Parameter Conditions Min Typ Max Unit Program erase parallelism _ 2 torog Word programming time PSIZE x 8 16 32 16 100 us Program erase parallelism PSIZE x 8 unius Program erase parallelism _ lERAsE16kp Sector 16 KB erase time PSIZE x 16 300 600 ms Program erase parallelism PSIZE x 32 Program erase parallelism PSIZE x 8 1200 2400 Progra
156. igure 59 through Figure 62 represent synchronous waveforms and Table 75 through Table 77 provide the corresponding timings The results shown in these tables are obtained with the following FSMC configuration BurstAccessMode FSMC_BurstAccessMode_Enable MemoryType FSMC_MemoryType_CRAM WriteBurst FSMC_WriteBurst_Enable e DataLatency 1 for NOR Flash DataLatency 0 for PSRAM In all timing tables the is the HCLK clock period Figure 59 Synchronous multiplexed NOR PSRAM read timings Electrical characteristics CLKDivision 1 0 is not supported see the STM32F20xxx 21xxx reference manual BUSTURN 0 td CLKL NExH 22222265122 5 m lt s E ER S td CLKL AIV FSMC A 25 16 td CLKL NOEL Id CLKL NOERI FSMC NOE ld CLKL ADIV gt tsu A td CLKL ADV FSMC AD 15 0 Isu NWAITV CLKH 4 9 Ltn CLKH NWAITV FSMC NWAIT WAITCFG 0b WAITPOL 0b tsu NWAITV CLKH th CLKH NWAITV ai14893g Doc ID 15818 Rev 9 129 174 Electrical characteristics STM32F20xxx 130 174 Table 74 Synchronous multiplexed NOR PSRAM read timings Symbol Parameter Min Max Unit tw CLk FSMC_CLK period 2THCLK ns td CLKL NExL FSMC_CLK low to FSMC_NEx low x 0 2 0 ns la CLKL NExH FSMC low to FSMC
157. imum Number of wait Operating Flash states at FSMC CLK Possible power ADC memory maximum CPU operation supply operation access frequency synchronous memory range frequency fcpumax accesses operations friasnmax 120 MHz D 16 MHz with 8 bit erase Vpp 1 8 to SERO and program PET time up to 79 performance to 30 MHz 2 1 V 1 Msps memory wait No VO operations P state aii only compensation Degraded 6 16 bit erase time up to 60 performance 30 2 program 24 1 Msps I O operations state compensation ky Doc ID 15818 Rev 9 65 174 Electrical characteristics STM32F20xxx Table 13 Limitations depending on the operating power supply range Maximum Number of wait Operating Flash states at FSMC_CLK Possible power ADC memory maximum CPU operation supply operation access frequency synchronous memory range frequency fcpumax accesses operations fFlashmax 120 MHz Degraded 24 MHz with speed Vpp 2 4 to Come rsion no Flash 3 performance 16 bit erase time up to 4 up to 48 MHz and program 2 7V memory wait 10 2 Msps operations state compensation works up to Full speed 60 MI iZ i hen Conversion 30 Mrz With operation 32
158. interrupt a 16 bit programmable binary auto reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 us to every 36 hours A 20 bit prescaler is used for the time base clock It is by default configured to generate a time base of 1 second from a clock at 32 768 kHz The 4 Kbyte backup SRAM is EEPROM like area It can be used to store data which need to be retained in VBAT and standby mode This memory area is disabled to minimize power consumption see Section 2 2 18 Low power modes It can be enabled by software The backup registers are 32 bit registers used to store 80 bytes of user application data when Vpp power is not present Backup registers are not reset by a system a power reset or when the device wakes up from the Standby mode see Section 2 2 18 Low power modes Like backup SRAM the RTC and backup registers are supplied through a switch that is powered either from the Vpp supply when present or the pin Low power modes The STM32F20x family supports three low power modes to achieve the best compromise between low power consumption short startup time and available wakeup sources Sleep mode In Sleep mode only the CPU is stopped All peripherals continue to operate and can wake up the CPU when an interrupt event occurs Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers A
159. ion block diagrams STM32F20xxx A 2 Application example with regulator OFF Figure 84 Regulator OFF internal reset ON Power down reset risen Power down reset risen after 1 VCAP 2 stabilization before 1 VCAP 2 stabilization 1 2 monitoring Application reset Ext reset controller active signal optional when 1 2 1 08V Application reset signal optional VDD 1 8 to 3 6 V VDD 1 8 to 3 6 V ST 1 IRROFF 2 18476 1 This mode is available only UFBGA176 WLCSP64 2 packages Figure 85 Regulator OFF internal reset OFF VDD 1 2V DD CAP 1 2 monitoring Ext reset controller active when Vpp 1 65 V and 1 5 lt 1 08 V 1 65 to 3 6 V IRROFF REGOFF 18477 1 This mode is available only WLCSP64 2 package 154 174 Doc ID 15818 Rev 9 STM32F20xxx Application block diagrams A 3 USB OTG full speed FS interface solutions Figure 86 USB OTG FS full speed device only connection 5V to Volatge regulator 0 STM32F20xxx OSC IN OSC OUT 5 o o m 2 o e 2 ai17295 1 The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx Tx FIFO and to a dedicated DMA controller Figure 87 USB OTG F
160. ively and removed USB OTG FS and camera interface for 64 pin package added USB OTG HS on 64 pin package added Note 1 and Note 2 Doc ID 15818 Rev 9 169 174 Revision history STM32F20xxx Table 94 Document revision history continued Date 20 Dec 2011 Revision Changes Updated SDIO register addresses in Figure 15 Memory map Updated Figure 3 Compatible board design between STM32F 10xx and STM32F2xx for LQFP144 package Figure 2 Compatible board design between STM32F 10xx and STM32F2xx for LQFP100 package Figure 1 Compatible board design between STM32F 10xx and STM32F2xx for LQFP64 package and added Figure 4 Compatible board design between STM32F 10xx STM32F2xx for LQFP176 package Updated Section 2 2 3 Memory protection unit Updated Section 2 2 6 Embedded SRAM Updated Section 2 2 28 Universal serial bus on the go full speed OTG_FS to remove external FS OTG PHY support In Table 6 STM32F20x pin and ball definitions changed SPI2_MCK MCK to 252 and 1253 respectively Added ETH RMII TX EN atlternate function to PG11 Added EVENTOUT in the list of alternate functions for I O pin balls Removed OTG FS SDA OTG FS SCL and OTG FS INTN alternate functions In Table 8 Alternate function mapping changed 1253 SCK to 1253 for PC7 AF6 added FSMC for FSMC NES for PG10 and for PD7 Removed OTG FS SD
161. lash controller waveforms for common memory read access FSMC 4 20 4 1 th NCEx NREG th NCEx NIORD th NCEx NIOWR td NREG NCEx td NIORD NCEx FSMC_NREG FSMC_NIOWR FSMC_NIORD FSMC_NWE td NCE4_1 NOE tw NOE FSMC_NOE tsu D NOE th NOE D ai14895b 1 FSMC 4 2 remains high inactive during 8 bit access Doc ID 15818 Rev 9 ky STM32F20xxx Electrical characteristics Figure 64 PC Card CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 High PH t NCEA 1 A th NCE4_1 Al __ th NCE4_1 NREG th NCE4_1 NIORD th NCE4_1 NIOWR c td NREG NCE4_1 td NIORD NCE4_1 FSMC_NREG FSMC NIOWR FSMC NIORD 1 NWE tw NWE Pr a NWE NCEA 1 5 NWE FSMC NOE MEMXHIZ 1 tv NWE D 4 th NWE D ai14896b Doc ID 15818 Rev 9 135 174 Electrical characteristics STM32F20xxx 136 174 Figure 65 PC Card CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 tv NCE4_1 A th NCE4_1 Al FSMC NCE4 2 Tigh 5 A 10 0 FSMC NIOWR 5 NIORD td NREG NCE4_1 th NCE4_1 NREG FSMC_NREG FSMC_NWE td NCE4_1 NOE gt t td NOE NCE4_1 FSMC_NOE tsu D NOE FSMC_D 15 0 148970 1 Only data bits O 7 are read bits 8 15 are disregarded Doc ID 15818 Rev 9
162. lerator and audio PLL PLLI2S Added Table 5 USART feature comparison Several updates on Table 6 STM32F20x pin and ball definitions and Table 8 Alternate function mapping ADC DAC oscillator RTC_AF WKUP and VBUS signals removed from alternate functions and moved to the other functions column in Table 6 STM32F20x pin and ball definitions TRACESWO added in Figure 5 STM32F20x block diagram Table 6 STM32F20x pin and ball definitions and Table 8 Alternate function 13 Jul 2010 4 mapping XTAL oscillator frequency updated on cover page in Figure 5 STM32F20x block diagram and in Section 2 2 11 External interrupt event controller EXT Updated list of peripherals used for boot mode in Section 2 2 13 Boot modes Added Regulator bypass mode in Section 2 2 16 Voltage regulator and Section 5 3 4 Operating conditions at power up power down regulator OFF Updated Section 2 2 17 Real time clock RTC backup SRAM and backup registers Added Note Note in Section 2 2 18 Low power modes Added SPI TI protocol in Section 2 2 23 Serial peripheral interface SPI 4 Doc ID 15818 Rev 9 163 174 Revision history STM32F20xxx 164 174 Table 94 Document revision history continued Date 13 Jul 2010 Revision 4 continued Changes Added USB OTG_FS features in Section 2 2 28 Universal serial bus on the go full speed OTG_FS Updated 1 and 2
163. ll clocks in the 1 2 V domain are stopped the PLL the HSI RC and the HSE crystal oscillators are disabled The voltage regulator can also be put either in normal or in low power mode The device can be woken up from the Stop mode by any of the line The EXTI line source can be one of the 16 external lines the PVD output the RTC alarm wakeup tamper time stamp events the USB OTG FS HS wakeup or the Ethernet wakeup e Standby mode The Standby mode is used to achieve the lowest power consumption The internal voltage regulator is switched off so that the entire 1 2 V domain is powered off The PLL the HSI RC and the HSE crystal oscillators are also switched off After entering Standby mode the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected The device exits the Standby mode when an external reset NRST pin an IWDG reset a rising edge on the WKUP pin or an RTC alarm wakeup tamper time stamp event occurs The RTC the IWDG and the corresponding clock sources are not stopped when the device enters the Stop or Standby mode Doc ID 15818 Rev 9 ky STM32F20xxx Description 2 2 19 Operation The pin allows to power the device domain from an external battery or an external supercapacitor operation is activated when is not present The VBAT pin supplies
164. ll up resistor Rpy see Table 44 Unless otherwise specified the parameters given in Table 47 are derived from tests performed under the ambient temperature and Vpp supply voltage conditions summarized in Table 12 Table 47 5 pin characteristics Symbol Parameter Conditions Min Typ Max Unit Vii NRS 7 NRST Input low level voltage 0 5 0 8 NRST Input high level voltage 2 Vppt 0 5 NRST Schmitt trigger voltage Vhys NRST hysteresis 209 7 mv Rpu Weak pull up equivalent resistor Vin Vss 30 40 50 Venas NRST Input filtered pulse 100 ns VuriNRsT NRST Input not filtered pulse Vpp 2 7V 300 ns our Generated reset pulse duration Internal 20 us Reset source 1 Guaranteed by design not tested in production 2 The pull up is designed with a true resistance in series with a switchable PMOS This PMOS contribution to the series resistance must be minimum 1095 order Figure 38 Recommended NRST pin protection External reset circuit PR S Se Internal Reset hi Filter 1 9 0 1 STM32Fxxx ai14132c 2 The reset network protects the device against parasitic resets The user must ensure that the level on the NRST go below the max level specified in Table 47 Otherwise the reset is not taken into account by the device Doc ID 15818 Rev 9 101 174
165. lus the maximum Run consumption of the MCU sourced cannot exceed the absolute maximum rating lypp see Table 10 e The sum of the currents sunk by all the I Os on plus the maximum Run consumption of the MCU sunk on Vss cannot exceed the absolute maximum rating lyss see Table 10 Output voltage levels Unless otherwise specified the parameters given in Table 45 are derived from tests performed under ambient temperature and Vpp supply voltage conditions summarized in Table 12 All Os are CMOS and TTL compliant Table 45 Output voltage characteristics Symbol Parameter Conditions Min Max Unit Output low level voltage for an I O pin _ VoL when 8 pins are sunk at same time TTL port ae lio 8mA V 3 Output high level voltage for an I O pin 2 7 3 6 V when 8 pins are sourced at same time lt pp lt 0 4 p Output low level voltage for an I O pin _ VoL when 8 pins are sunk at same time CMOS port 22 Output high level voltage for an pi cem wr d HN 3 utput high level voltage for an pn 36V _ when 8 pins are sourced at same time lt pp lt vo 24 Output low level voltage for an 13 when 8 pins are sunk at same time lio 20 mA 7 Vou Output high level voltage for an pin 2 7 V lt 3 6 V Vpp 1 3 _ when 8 pins are sourced at same time 9 Output low level voltage for an VO pin _ 0 4 when
166. lutions Figure 89 OTG HS high speed device connection host and dual role in high speed mode with external PHY not connected FS PHY USB HS OTG Ctrl ULPI D 7 0 ULPI DIR USB connector I ULPI_STP ULPI_NXT High speed OTG PHY lt V gt URN ee ai16036c 124 or 26 MHz XT MCO 1 or 2 1 Itis possible to use MCO1 MCC2 to save a crystal It is however not mandatory to clock the STM32F20x with a 24 or 26 MHz crystal when using USB HS The above figure only shows an example of a possible connection 2 ID pin is required in dual role only Doc ID 15818 Rev 9 157 74 Application block diagrams STM32F20xxx A 5 Complete audio player solutions Two solutions are offered illustrated in Figure 90 and Figure 91 Figure 90 shows storage media to audio DAC amplifier streaming using a software Codec This solution implements an audio crystal to provide audio class 25 accuracy on the master clock 0 596 error maximum see the Serial peripheral interface section in the reference manual for details Figure 90 Complete audio player solution 1 XTAL 25 MHz 14 7456 MHz USB Mass storage device 16039 Figure 91 shows storage media to audio Codec amplifier streaming with
167. m erase parallelism _ lERAsEe4kp Sector 64 KB erase time PSIZE x 16 700 1400 ms Program erase parallelism PSIZE x 32 290 1188 Program erase parallelism _ 2 4 PSIZE 2 x 8 Program erase parallelism tERAsE128kp Sector 128 KB erase time Tx 4 1 3 2 6 5 Program erase parallelism _ 1 2 PSIZE x 32 Program erase parallelism PSIZE x 8 16 ll oe 3 Program erase parallelism tue Mass erase time PSIZE x 16 11 22 5 parallelism _ 8 16 PSIZE x 32 32 bit program operation 2 7 3 6 Programming voltage 16 bit program operation 2 1 3 6 V 8 bit program operation 1 8 3 6 1 Based on characterization not tested in production 2 The maximum programming time is measured after 100K erase operations Table 37 Flash memory programming with Vpp Symbol Parameter Conditions Min Typ Max Unit torog Double word programming 16 1000 Us tERASE16KB Sector 1 6 KB erase time 0 to 40 x 230 tERASEe4kp Sector 64 KB erase time 3 3 V 490 ms teRAsE128kp Sector 128 KB erase time 8 5 875 Mass erase time 6 9 Vorog Programming voltage 2 7 3 6 Doc ID 15818 Rev 9 31 STM32F20xxx Electrical characteristics Table 37 Flash memory programming with Vpp continued Symbol Parameter Conditions Min Typ Max Unit Vpp Vpp voltag
168. mapping Updated Table 9 Voltage characteristics and Table 10 Current characteristics Tera updated to 65 to 150 in Table 11 Thermal characteristics Added ESL and ESR in Table 12 General operating conditions as well as Section 5 3 2 VCAP1 VCAP2 external capacitor Modified Note 4 in Table 13 Limitations depending on the operating power supply range Updated Table 15 Operating conditions at power up power down regulator ON and Table 16 Operating conditions at power up power down regulator OFF Added 5 OUT pin in Figure 16 Pin loading conditions and Figure 17 Pin input voltage Updated Figure 18 Power supply scheme to add IRROFF and REGOFF pins and modified notes Updated 2 typical value and added Enusr and Note in Table 17 Embedded reset and power control block characteristics Doc ID 15818 Rev 9 ky STM32F20xxx Revision history Table 94 Document revision history continued Date Revision Changes Updated Typical and maximum current consumption conditions as well as Table 18 Typical and maximum current consumption in Run mode code with data processing running from Flash memory ART accelerator disabled and Table 19 Typical and maximum current consumption in Run mode code with data processing running from Flash memory ART accelerator enabled or RAM Added Figure 22 Figure 23 Figure 24 and
169. mbol Parameter Conditions Min Max Unit AHB APB2 1 trIMxCLK prescaler distinct from 1 friMxcLK 8 3 Timer resolution time 120 MHz AHB APB2 1 5 prescaler 1 60 MHz 16 7 ns Timer external clock 0 2 2 frequency to CH4 0 60 MHz Timer resolution 16 bit f 120 MHz 16 bit counter clock period Tees 1 65536 triMxCLK tcounter when internal clock is APB2 60 MHz selected 0 0083 546 us 65536 x 65536 ttimxcLk possible count 35 79 5 5 3 19 1 is used as general term to refer to the TIM1 TIM8 9 10 TIM11 timers Communications interfaces interface characteristics Unless otherwise specified the parameters given in Table 50 are derived from tests performed under the ambient temperature fpc frequency and Vpp supply voltage conditions summarized in Table 12 STM32F205xx and STM32F207xx 2 interface meets the requirements of the standard re communication protocol with the following restrictions the I O pins SDA and SCL are mapped to are not true open drain When configured as open drain the PMOS connected between the I O pin and Vpp is disabled but is still present The 12 characteristics are described in Table 50 Refer also to Section 5 3 16 I O port characteristics for more details on the input output alt
170. n TA 25 C 3 3 for the 1 8 V lt Vpp 3 6 V voltage range They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have error less than or equal to the value indicated 27 5 1 3 Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested 5 1 4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 16 5 1 5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 17 Figure 16 Pin loading conditions Figure 17 Pin input voltage STM32F pin STM32F pin OSC OUT Hi Z when OSC OUT Hi Z when using HSE or LSE using HSE or LSE MS19011V1 MS19010V1 ky Doc ID 15818 Rev 9 61 174 Electrical characteristics STM32F20xxx 5 1 6 62 174 Power supply scheme Figure 18 Power supply scheme VBAT APower switch OUT GP 108 IN _ 1 2x22yF Vpp a 1 2 14 15 15 x 100 nF V 1x47yF E u gt ub REGOFF IRROFF IL VDDA gu VREF 1 VREF 10 10 nF ADC 1pF TRF 1 B
171. n definition continued FSMC NOFUPSRAMIS NOR PSRAM Mux NAND 16 bit iod RAM 4 4 PF5 A5 A5 PF6 NIORD PF7 NREG PF8 NIOWR PF9 CD PF10 INTR PF12 A6 A6 PF13 A7 A7 PF14 A8 A8 PF15 A9 A9 PG0 A10 A10 PG1 A11 PE7 D4 D4 DA4 D4 Yes PE8 D5 D5 DA5 D5 Yes PE9 D6 D6 DA6 D6 Yes PE10 D7 D7 DA7 D7 Yes PE11 D8 D8 DA8 D8 Yes PE12 D9 D9 DA9 D9 Yes PE13 D10 D10 DA10 D10 Yes PE14 D11 D11 DA11 D11 Yes PE15 D12 D12 DA12 D12 Yes PD8 D13 D13 DA13 D13 Yes PD9 D14 D14 DA14 D14 Yes PD10 D15 D15 DA15 D15 Yes PD11 A16 A16 CLE Yes PD12 A17 A17 ALE Yes PD13 A18 A18 Yes PD14 D0 D0 DA0 D0 Yes PD15 D1 D1 DA1 D1 Yes PG2 A12 PG3 A13 PG4 A14 Doc ID 15818 Rev 9 STM32F20xxx Pinouts and pin description Table 7 FSMC pin definition continued FSMC ia CF ia NOR PSRAM Mux NAND 16 bit iio PG5 A15 PG6 INT2 PG7 INT3 PDO D2 D2 DA2 D2 Yes PD1 D3 D3 DA3 D3 Yes PD3 CLK CLK Yes PD4 NOE NOE NOE NOE Yes PD5 NWE NWE NWE NWE Yes PD6 NWAIT NWAIT NWAIT NWAIT Yes PD7 NE1 NE1 NCE2 Yes 9 2 2 PG10 4 1 PG11 4 2 PG12 NE4 4 PG13 A24 A24 PG14 A25 A25 PB7 NADV NADV Yes PEO NBLO NBLO Yes PE1 NBL1 NBL1 Yes 57 Doc ID 15818 Rev 9 53H74 6 81881 01900
172. nal capacitor Stabilization for the main regulator is achieved by connecting an external capacitor to the VCAP1 VCAP2 pins is specified in Table 14 Figure 21 External capacitor au ESR R Leak MS19044V1 1 Legend ESR is the equivalent series resistance Table 14 VCAP1 VCAP2 operating conditions Symbol Parameter Conditions CEXT Capacitance of external capacitor 2 2 UF ESR ESR of external capacitor 20 ky Doc ID 15818 Rev 9 67 174 Electrical characteristics STM32F20xxx 5 3 3 Operating conditions at power up power down regulator ON Subject to general operating conditions for T4 Table 15 Operating conditions at power up power down regulator ON Symbol Parameter Min Max Unit Vpp rise time rate 20 tvpp us V fall time rate 20 oo 5 3 4 Operating conditions at power up power down regulator OFF Subject to general operating conditions for TA Table 16 Operating conditions at power up power down regulator OFF Symbol Parameter Conditions Min Max Unit Vpp rise time rate Power up 20 tvpp fall time rate Power down 20 s V Vonp and p Power up 20 H time rate lyCAP Vcap Vcap 2fall Power down 20 time rate 68 174 Doc ID 15818 Rev 9 ky STM32F20xxx Electrical characteristics 5 3 5 Embedded reset a
173. nce 5 pF 1 If maximum value cannot be respected the injection current must be limited externally to maximum value 2 TT 3 6 V tolerant 3 FT 5V tolerant 4 With a minimum of 100 mV 5 Hysteresis voltage between Schmitt trigger switching levels Based on characterization not tested in production 6 Leakage could be higher than the maximum value if negative current is injected on adjacent pins 7 Pull up and pull down resistors are designed with a true resistance in series with a switchable PMOS NMOS This MOS NMOS contribution to the series resistance is minimum 1096 order 8 Guaranteed by design not tested in production ky Doc ID 15818 Rev 9 97 174 Electrical characteristics STM32F20xxx 98 174 All are CMOS and TTL compliant no software configuration required Their characteristics cover more than the strict CMOS technology or TTL parameters Output driving current The GPIOs general purpose input outputs can sink or source up to 8 mA and sink or source up to 20 mA with a relaxed Vo except PC13 PC14 and PC15 which can sink or source up to When using the PC13 to PC15 GPIOs in output mode the speed should not exceed 2 MHz with a maximum load of 30 pF In the user application the number of I O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5 2 e Thesum of the currents sourced by all the 1 on p
174. nd power control block characteristics The parameters given in Table 17 are derived from tests performed under ambient temperature and Vpp supply voltage conditions summarized in Table 12 Table 17 Embedded reset and power control block characteristics Symbol Parameter Conditions Min Unit PLS 2 0 000 rising 209 214 219 PLS 2 0 000 falling 1 98 2 04 2 08 V edge PLS 2 0 001 rising 223 230 237 V edge PLS 2 0 001 falling 213 2 19 2 25 V edge PLS 2 0 010 rising 239 245 251 V edge PLS 2 0 010 falling 229 235 239 V edge PLS 2 0 011 rising 254 260 265 V edge PLS 2 0 011 falling 2 44 2 51 2 56 V Programmable voltage edge detector level selection S 2 0 100 rising PLS 2 0 100 falling PLS 2 0 101 rising 286 293 299 edge PLS 2 0 101 falling rem az saa S edge PLS 2 0 110 rising 2 96 3 03 3 10 PLS 2 0 110 falling edge PLS 2 0 111 rising 307 314 3 21 PLS 2 0 111 falling sac soe edge Vpvpnyst PVD hysteresis 100 Power on power down Falling edge 1 600 1 68 1 76 POR PDR reSettireshold Rising edge 1 64 1 72
175. ns tsu ER Error setup time 3 5 10 ns Error hold time 0 10 ns ta TXEN Transmit enable valid delay time 7 5 11 14 ns ta TXD Transmit data valid delay time 7 5 11 14 ns 1 stands for be defined CAN controller area network interface Refer to Section 5 3 16 I O port characteristics for more details on the input output alternate function characteristics CANTX and CANRX ki Doc ID 15818 Rev 9 115 174 Electrical characteristics STM32F20xxx 5 3 20 12 bit ADC characteristics Unless otherwise specified the parameters given in Table 64 are derived from tests performed under the ambient temperature fpc frequency and supply voltage conditions summarized in Table 12 Table 64 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VppA __ Power supply 1 800 3 6 V Positive reference voltage 1 800 VDDA V VppA 1 8 to 2 4 V 0 6 15 MHz ADC clock frequency 2 4 to 3 6 V 0 6 30 MHz f 30 MHz 823 kHz External trigger frequency 17 1 5 0 _ Vain Conversion voltage range tied to ground VREF V 4 See Equation 1 for _ RAIN External input impedance details 50 RApc Sampling switch resistance 1 5 6 4 Internal sample and hold 1 I Capc capacitor 4 pF 1 4 Injection trigger conversion fapc 30 MHz 2 7
176. ns Min Typ Max Unit Internal reference voltage 40 lt Ty lt 105 1 18 1 21 1 24 V ADC sampling time when Ts reading the internal reference 10 us voltage Internal reference voltage REBINT 5 spread over the temperature 3 3 5 mV range 2 Temperature coefficient 30 50 tsranr Startup time 6 10 us 1 Shortest sampling time can be determined in the application by multiple iterations 2 Guaranteed by design not tested in production 5 3 25 FSMC characteristics Asynchronous waveforms and timings Figure 55 through Figure 58 represent asynchronous waveforms and Table 70 through Table 73 provide the corresponding timings The results shown in these tables are obtained with the following FSMC configuration e AddressSetupTime 1 e AddressHoldTime 1 e DataSetupTime 1 e BusTurnArounaDuration 0x0 In all timing tables the is the HCLK clock period 124 174 Doc ID 15818 Rev 9 ky STM32F20xxx Electrical characteristics Figure 55 Asynchronous non multiplexed SRAM PSRAM NOR read waveforms hi tw NE gt 5 tv NOE_NE tw NOE gt h NE_NOE FSMC_NOE FSMC NWE 7 NE NOE gt NE NOE 14 FSMC NBL 1 0 gt th Data NE su Data NOE NOE tsu Data_NE FSMC D 15 0 tv N
177. on when the counter reaches 0 e Programmable clock source Inter integrated circuit interface Up to three bus interfaces can operate in multimaster and slave modes They can support the Standard and Fast modes They support the 7 10 bit addressing mode and the 7 bit dual addressing mode as slave A hardware CRC generation verification is embedded They can be served by DMA and they support SMBus 2 0 PMBus Universal synchronous asynchronous receiver transmitters UARTS USARTS The STM32F20x devices embed four universal synchronous asynchronous receiver transmitters USART1 USART2 USART3 USART6 and two universal asynchronous receiver transmitters UART4 and UART5 These six interfaces provide asynchronous communication IrDA SIR ENDEC support multiprocessor communication mode single wire half duplex communication mode and have LIN Master Slave capability The USART1 and USARTE6 interfaces are able to Doc ID 15818 Rev 9 29 174 Description STM32F20xxx communicate at speeds of up to 7 5 Mbit s The other available interfaces communicate at up to 3 75 Mbit s USART1 USART2 USART3 and USARTS also provide hardware management of the CTS and RTS signals Smart Card mode ISO 7816 compliant and SPI like communication capability All interfaces can be served by the DMA controller Table 5 USART feature comparison Max baud rate Max baud rate US
178. ote in Section 5 3 20 12 bit ADC characteristics 3 Positive injection is not possible on these I Os A negative injection is induced by Viy Vss must never be exceeded Refer to Table 9 for the values of the maximum allowed input voltage 4 A positive injection is induced by Viy Vpp while a negative injection is induced by Viy Vss must never be exceeded Refer to Table 9 for the values of the maximum allowed input voltage 5 When several inputs are submitted to a current injection the maximum 2 liN PIN is the absolute sum of the positive and negative injected currents instantaneous values Table 11 Thermal characteristics Symbol Ratings Value Unit TsrG Storage temperature range 65 to 4150 Maximum junction temperature 125 C 5 3 Operating conditions 5 3 1 General operating conditions Table 12 General operating conditions Symbol Parameter Conditions Min Max Unit Internal AHB clock frequency 0 120 fPcLk1 Internal APB1 clock frequency 0 30 MHz Internal 2 clock frequency 0 60 Vpp Standard operating voltage 180 3 6 Analog operating voltage 180 36 gt limited to 1 M samples 3 Must be the same potential as V Analog operating voltage 24 3 6 ADC limited to 2 M samples VBAT Backup operating voltage 1 65 3 6 V 64 174 Doc ID 15818 Rev 9 ky STM32F
179. ow the application to synchronize A D conversion and timers DAC digital to analog converter The two 12 bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs The design structure is composed of integrated resistor strings and an amplifier in inverting configuration This dual digital Interface supports the following features two DAC converters one for each output channel 8 bit or 12 bit monotonic output left or right data alignment in 12 bit mode synchronized update capability noise wave generation triangular wave generation dual DAC channel independent or simultaneous conversions DMA capability for each channel external triggers for conversion input voltage reference Eight DAC trigger inputs are used in the device The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams Doc ID 15818 Rev 9 ky STM32F20xxx Description 2 2 36 2 2 37 2 2 38 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature The conversion range is between 1 8 and 3 6 V The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value As the offset of the temperature sensor varies from chip to chip due to process variation the internal temperature sensor is mainly suitable for applica
180. r e Unexpected reset e Critical Data corruption control registers Prequalification trials Most of the common failures unexpected reset and program counter corruption can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Electromagnetic Interference EMI The electromagnetic field emitted by the device are monitored while a simple application executing EEMBC code is running This emission test is compliant with SAE IEC61967 2 standard which specifies the test board and the pin loading 94 174 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Table 40 EMI characteristics Max vs Symbol Parameter Conditions Monitored Unit frequency band 8 120 MHz 0 1 to 30 MHz 21 Vpp 3 3 V Ta 25 C LQFP176 package conforming to SAE J1752 3 30 to 130 MHz 28 dBuV code running with ART 130 MHz to 1GHz 31 enabled SAE EMI Level 4 SEM Peak level Vpp 3 3 V 25 LQFP176 package conforming to SAE 1752 3 30 to 130 MHz 15 dBuV code running with ART enabled PLL spread spectrum 130 MHz
181. rals ON Ipp RuN mA 60 CPU frequnecy MHz 519016 1 Figure 25 Typical current consumption vs temperature Run mode code with data processing running from Flash ART accelerator OFF peripherals OFF DD RUN MS19017V1 74 174 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Table 20 Typical and maximum current consumption in Sleep mode Typ Symbol Parameter Conditions The Unit Ty 25 C Ty 85 10550 120 2 38 51 61 90 2 30 43 53 60 2 20 33 43 30 MHz 11 25 35 1 enabled 9 23 MHZ 8 21 31 16 MHz 6 19 29 8 MHz 3 6 17 0 27 0 4 MHz 2 4 15 4 25 3 Supply e rrentih 2 MHz 1 9 14 9 247 120 2 8 21 31 90 2 7 20 30 60 2 5 18 28 30 2 3 5 16 0 26 0 2 25MHz 25 160 250 16 MHz 2 1 15 1 25 0 8 MHz 1 7 15 0 25 0 4 MHz 1 5 14 6 24 6 2 MHz 1 4 14 2 24 3 1 Based on characterization tested in production at max and fuc max with peripherals enabled External clock is 4 MHz and is on when gt 25 MHz Add an additional power consumption of 0 8 mA per ADC for the analog part In applications this consumption occurs only while the ADC is on ADON bit is set in the CR2 register Doc ID 15818 Rev 9 75 174 Electrical characteristics STM32F20x
182. re is valid both whatever the internal reset mode ON or OFF Figure 8 Startup in regulator OFF fast slope power down reset risen before 4 Vcap 2 Stabilization PDR 1 8 V N 12V CAP 1 VCAP 2 1 08 time asserted externally time Real time clock RTC backup SRAM and backup registers The backup domain of the STM32F20x devices includes e Thereal time clock RTC e 4Kbytes of backup SRAM e 20backup registers The real time clock RTC is an independent BCD timer counter Dedicated registers contain the second minute hour in 12 24 hour week day date month year in BCD binary coded decimal format Correction for 28 29 leap year 30 and 31 day of the month are performed automatically The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes It is clocked by a 32 768 kHz external crystal resonator or oscillator the internal low power RC oscillator or the high speed external clock divided by 128 The internal low speed RC Doc ID 15818 Rev 9 25 174 Description STM32F20xxx 2 2 18 Note 26 174 has a typical frequency of 32 kHz The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison To generate a periodic
183. ristics Table 33 1125 audio PLL characteristics continued Symbol Parameter Conditions Min Typ Max Unit Cycle to cycle at RMS E 90 12 343 MHz on peak 48KHz period to D 280 432 4 R 5 Master 125 clock jitter 4 Average frequency of 12 343 MHz N 432 P 4 R 5 ps on 256 samples Cycle to cycle at 48 KHz WS 125 clock jitt 400 S ad on 1000 samples 5 PLLI2S power consumption on VCO freq 192 MHz 0 15 0 40 lpp PLLI2S _ VCO freq 432 MHz 0 45 0 75 5 PLLI2S power consumption on _ VCO freq 192 MHz 0 30 0 40 IDDA PLLI2s _ 432 2 0 55 0 85 1 stands for be defined 2 Take care of using the appropriate division factor M to have the specified PLL input clock values 3 Guaranteed by design not tested in production 4 Value given with main PLL running 5 Basedon characterization not tested in production ky Doc ID 15818 Rev 9 89 174 Electrical characteristics STM32F20xxx 5 3 11 PLL spread spectrum clock generation SSCG characteristics The spread spectrum clock generation SSCG feature allows to reduce electromagnetic interferences see Table 40 EMI characteristics It is available only on the main PLL Table 34 SSCG parameters constraint Symbol Parameter Min Max Unit Modulation frequency 10 KHz md Peak modulation
184. rtup 22 22 13 Bootmodes aos ee dea ee hha 23 2 214 Power supply schemes 23 2 2 15 Power supply supervisor 23 2 216 Voltage regulator eh 23 2 2 47 Real time clock RTC backup SRAM and backup registers 25 2 2 18 Low power modes 26 2 2 19 cess kb eere Ros oda 4 27 2 2 20 Timers and 08 27 2 2 24 Inter integrated circuit interface PC 29 2 2 22 Universal synchronous asynchronous receiver transmitters UARTS USARTS 29 2 2 23 Serial peripheral interface 30 2204 jinterintegrated sound 30 2 225 SDIO IG ER Ee 32 2 2 26 Ethernet MAC interface with dedicated DMA and IEEE 1588 support 32 2 2 27 Controller area network 33 2 2 28 Universal serial bus on the go full speed OTG FS 33 2 75 Doc ID 15818 Rev 9 ky STM32F20xxx Contents 2 2 29 Universal serial bus on the go high speed OTG_HS 33 2 2 80 Audio PEL PLEIPS uoce Eb Rex nwa deb Yee hieu 34 2 2 34 Digital cam
185. s multiplexed PSRAM NOR write waveforms FSMC_A 25 16 FSMC_NBL 1 0 FSMC_AD 15 0 FSMC_NADV FSMC NOE lt ty NWE_NE lw NWE gt 4 5 NWE lt j ly BL NE tv NADV NE th AD_NADV tw NADV th A_NWE 7 n Data NWE ai14891B Table 73 Asynchronous multiplexed PSRAM NOR write timings 1 2 Symbol Parameter Min Max Unit tw NE FSMC_NE low time 4 1 4 ns lv NWE_NE FSMC low to FSMC_NWE low Tucuc 1 5 tw NWE FSMC_NWE low tim e 2THcLK 2 1 ns th NE_NWE FSMC_NWE high to FSMC_NE high hold time Tuck 1 5 NE FSMC_NEx low to FSMC valid 0 ns ty NADV NE NEx low to low 1 2 ns tw NADV FSMC_NADV low time 2 2 5 2 valid hold time after Pin s 2 gh Address hold time after FSMC_NWE high 0 5 ns th BL_NWE FSMC_BL hold time after FSMC_NWE high 1 ns NE FSMC NEx low to FSMC BL valid 0 5 ns ly Data NADV FSMC NADV high to Data valid 2 5 th Data_NWE Data hold time after FSMC_NWE high 0 5 5 1 C 30 pF 2 Based on characterization not tested in production Doc ID 15818 Rev 9 STM32F20xxx Synchronous waveforms and timings F
186. scillator with 25 MHz crystal and PLL is on EN1 bit is set in DAC_CR register EN2 bit is set in DAC_CR register 2 2 ADON bit set in ADC_CR2 register The wakeup times given in Table 25 is measured on a wakeup phase with a 16 MHz HSI RC oscillator The clock source used to wake up the device depends from the current operating mode e Stop or Standby mode the clock source is the RC oscillator e Sleep mode the clock source is the clock that was set before entering Sleep mode All timings are derived from tests performed under ambient temperature and Vpp supply voltage conditions summarized in Table 12 Table 25 Low power mode wakeup timings Symbol Parameter Min Typ Unit twusipep Wakeup from Sleep mode 1 us Wakeup from Stop mode regulator in Run mode 13 2 Wakeup from Stop mode regulator in low power mode 17 40 twusToP us Wakeup from Stop mode regulator in low power mode 110 and Flash memory in Deep power down mode 29 Wakeup from Standby mode 260 375 480 us 1 Based on characterization not tested in production 2 The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction 3 twusrpBy minimum and maximum values are given at 105 C and 45 C respectively Doc ID 15818 Rev 9 81 174 Electrical characteristics STM32F20xxx
187. sh Functionality overview e Write FIFO e Code execution from external memory except for Flash and e Maximum frequency for external access is 60 MHz LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers It supports the Intel 8080 and Motorola 6800 modes and is flexible enough to adapt to specific LCD interfaces This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration Doc ID 15818 Rev 9 21 74 Description STM32F20xxx 2 2 10 2 2 11 2 2 12 22 174 Nested vectored interrupt controller NVIC The STM32F20x devices embed a nested vectored interrupt controller able to manage 16 priority levels and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the Cortex M3 The NVIC main features are the following Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support tail chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt m
188. ter Conditions Min Typ Max Unit VCO freq 192 MHz 75 200 lock time Hus VCO freq 432 MHz 100 300 RMS 25 Cycle to cycle jitter peak to 2150 System clock peak 120 MHz RMS 15 Period Jitter peak ara r 3 to 200 Jitter peak ps Main clock output MCO for Cycle to cycle at 50 MHz _ 32 _ RMII Ethernet on 1000 samples Main clock output for MII Cycle to cycle at 25 MHz _ 40 _ Ethernet on 1000 samples Bit Time CAN jitter Cycle to eycleat 1 MHz 330 1000 samples VCO freq 192 MHz 0 15 0 40 4 PLL power consumption on VDD DD PLL P P VCO freq 432 MHz 0 45 0 75 4 power consumption on VCO freq 192 MHz 0 30 0 40 DDA PLL VDDA VCO freq 432 MHz 0 55 0 85 1 Take care of using the appropriate division factor M to obtain the specified PLL input clock values The M factor is shared between PLL and PLLI2S 2 Guaranteed by design not tested in production 3 The use of 2 PLLs in parallel could degraded the Jitter up to 43096 Based on characterization not tested in production Table 33 PLLI2S audio PLL characteristics Symbol Parameter Conditions Min Typ Max Unit PLLI2S_IN PLLI2S input clock 0 959 1 2 10 3 MHz PLLI2S_OUT PLLI2S multiplier output clock 216 MHz fyco_ouT PLLI2S VCO output 192 432 MHz VCO freq 192 MHz 75 200 ti ock PLLI2S lock time us VCO freq 432 MHz 100 300 88 174 Doc ID 15818 Rev 9 ky STM32F20xxx Electrical characte
189. ternal capacitor 1 244 68 Typical current consumption vs temperature Run mode code with data processing running from RAM and peripherals 74 Typical current consumption vs temperature Run mode code with data processing running from RAM and peripherals 74 Typical current consumption vs temperature Run mode code with data processing running from Flash ART accelerator OFF peripherals 75 Typical current consumption vs temperature Run mode code with data processing running from Flash ART accelerator OFF peripherals OFF 75 Typical current consumption vs temperature in Sleep mode peripherals a 77 Typical current consumption vs temperature in Sleep mode peripherals OFF oss eee am A e ende e eiae OR 77 Typical current consumption vs temperature in Stop 78 High speed external clock source AC timing diagram 84 Low speed external clock source AC timing diagram 84 Typical application with an 8 MHz 85 Typical application with a 32 768 kHz 86 ACCyg versus
190. ternally during POR until reaches 1 8 V see Figure 8 In this mode PAO cannot be used as a GPIO pin since it allows to reset the part of the 1 2 V logic which is not reset by the NRST pin when the internal voltage regulator in OFF e Regulator OFF internal reset OFF WLCSP66 package this mode activated by connecting REGOFF to and IRROFF to Vpp IRROFF cannot be activated in conjunction with REGOFF This mode is available only on the WLCSP package It allows to supply externally a 1 2 V voltage source through 1 and Vcap 2 pins in addition to The following conditions must be respected Vpp should always be higher than 1 and 2 to avoid current injection between power domains see Figure 7 should be kept low to cover both conditions until 1 and 2 reach 1 08 V and until Vpp reaches 1 65 V NRST should be controlled by an external reset controller to keep the device under reset when Vpp is below 1 65 V see Figure 6 a Vpp minimum value is 1 7 V when the device operates in the 0 to 70 temperature range and IRROFF is set to Vpp 24 174 Doc ID 15818 Rev 9 ky STM32F20xxx Description 2 2 17 Figure 7 Startup in regulator OFF slow Vpp slope power down reset risen after 1 2 Stabilization PDR 1 8V N 12V CAP 1 VCAP 2 time PAO tied to NRST time 1 This figu
191. tions that detect temperature changes instead of absolute temperatures If an accurate temperature reading is needed then an external temperature sensor part should be used Serial wire JTAG debug port SWJ DP The ARM SWJ DP interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target The JTAG TMS and TCK pins are shared with SWDIO and SWCLK respectively and specific sequence on the TMS is used to switch between JTAG DP and SW DP Embedded Trace Macrocell The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the 5 32 20 through a small number of ETM pins to an external hardware trace port analyzer device The is connected to a host computer using USB Ethernet or any other high speed channel Real time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software TPA hardware is commercially available from common development tool vendors The Embedded Trace Macrocell operates with third party debugger software tools Doc ID 15818 Rev 9 35 174 Pinouts and pin description STM32F20xxx 3 36 174 Pinouts and pin description Figure 9 5 32 20 LQFP64 pinout
192. tput mode is limited the speed should not exceed 2 MHz with a maximum load of 30 pF and these I Os must not be used as a current source e g to drive an LED 5 Main function after the first backup domain power up Later on it depends on the contents of the RTC registers even after reset because these registers not reset by the main reset For details on how to manage these I Os refer to the RTC register description sections in the STM32F20x and STM32F21x reference manual available from the STMicroelectronics website www st com FT 5 V tolerant except when in analog mode or oscillator mode for PC 14 PC15 PHO and 1 7 If the device is delivered UFBGA176 package and if the REGOFF pin is set to Vpp Regulator OFF then PAO is used as an internal Reset active low FSMC_NL pin is also named FSMC_NADV on memory devices RFU means reserved for future use This pin can be tied to Vpp Vgg or left unconnected 4 Table 7 FSMC pin definition FSMC NOR PSRAM S NOR PSRAM Mux NAND 16 bit 2 23 23 Yes PES A19 A19 Yes 4 20 20 Yes PE5 A21 A21 Yes PE6 A22 A22 Yes PFO 0 0 1 1 PF2 A2 A2 Doc ID 15818 Rev 9 51 174 Pinouts pin description STM32F20xxx 52 174 Table 7 FSMC pi
193. ured in master mode the master clock can be output to the external DAC CODEC at 256 times the sampling frequency All I2Sx interfaces be served by the DMA controller 30 174 Doc ID 15818 Rev 9 ky STM32F20xxx Description 2 2 25 2 2 26 SDIO An SD SDIO MMC host interface is available that supports MultiMediaCard System Specification Version 4 2 in three different databus modes 1 bit default 4 bit and 8 bit The interface allows data transfer at up to 48 MHz in 8 bit mode and is compliant with the SD Memory Card Specification Version 2 0 The SDIO Card Specification Version 2 0 is also supported with two different databus modes 1 bit default and 4 bit The current version supports only one SD SDIO MMC4 2 card at any one time and a stack of MMC4 1 or previous In addition to SD SDIO MMC this interface is fully compliant with the CE ATA digital protocol Rev1 1 Ethernet MAC interface with dedicated DMA and IEEE 1588 support Peripheral available only on the STM32F207xx devices The STM32F207xx devices provide an IEEE 802 3 2002 compliant media access controller MAC for ethernet LAN communications through an industry standard medium independent interface MII or a reduced medium independent interface RMII The STM32F207xx requires an external physical interface device PHY to connect to the physical LAN bus twisted pair fiber etc the PHY is connected to the STM32F207xx MII port using 17 signals for MI
194. us multiplexed PSRAM NOR write timings 129 Synchronous multiplexed NOR PSRAM read timings 131 Synchronous multiplexed PSRAM write 1 132 Synchronous non multiplexed NOR PSRAM read 0 133 Synchronous non multiplexed PSRAM write 05 134 Switching characteristics for PC Card CF read and write cycles in attribute common 139 Switching characteristics for PC Card CF read and write cycles space 140 Switching characteristics for Flash read 142 Switching characteristics for Flash write 143 DCMI 143 SD MMC 144 RTC characteristics 1 4 144 LQFP64 10 x 10 mm 64 pin low profile quad flat package mechanical data 146 WLCSP64 2 0 400 mm pitch wafer level chip size package mechanical data 147 LQPF100 14 x 14 mm 100 pin low profile quad flat package mechanical data 148 LQFP144 20 x 20 mm 144 pin low profile quad flat package mechanical data 149 LQFP176 Low profile quad flat package
195. vel VLSEH voltage 0 7 OSC32 IN input pin low level VLSEL voltage Vss 0 3Vpp 32 IN high or low time 450 TLSE ns LSE OSC32 IN rise or fall time 1 50 sE OSC32 IN input capacitance 5 pF Duty cycle 30 70 96 IL OSC32 IN Input leakage current Vss lt ViN lt Vpp 1 1 Guaranteed by design tested in production 82 74 Doc ID 15818 Rev 9 STM32F20xxx Electrical characteristics Figure 29 High speed external clock source AC timing diagram External clock source JUUL ai17528 1 1 t External clock source TULL STM32F ai17529 High speed external clock generated from a crystal ceramic resonator The high speed external HSE clock can be supplied with a 4 to 26 2 crystal ceramic resonator oscillator All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 28 In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details on the resonator characteristics frequency package accuracy Doc ID 15818 Rev 9 83 174 Electrical characteristics STM32F20xxx Note
196. ws WS hold time Slave 0 2 5 CK high and low time Mte PODE 189 tw CKL presc 7 tsu SD_MR 2 Master receiver 45 _ 2 Data input setup time Slave receiver 0 2 3 2 3 Data input hold time Master 2 18 th SD_SR Slave receiver 0 0 MR 2 5 Master 120 MHz 13 5 ata input hold time sm 2 4 Slave 120 MHz 0 Slave transmitter after 2 12 tsp 29 Data output valid time enable edge 120 MHz 12 2 Slave transmitter after _ lh sD sT Data output hold time enable edge 10 Master transmitter after T le edge 4 tsp wr 9 9 Data output valid time enable edge 120 MHz 4 6 2 Master transmitter after _ th SD_MT Data output hold time enable edge 0 1 stands for to be defined 2 Based on design simulation and or characterization results not tested in production 3 Depends on For example if 8 MHz then 1 fpLeLk 125 ns ky Doc ID 15818 Rev 9 109 174 Electrical characteristics STM32F20xxx Figure 43 125 slave timing diagram Philips protocol lt CK Input su SD_SR 8 88 SDreceive LSB receive Bitn receive LSB receive ai14881b Measurement points are done at CMOS levels 0 3 x and 0 7 x Vpp 2 LSB transmit receive of the previously transmitted byte LSB transmit receive is sent be
197. x for LQFP176 17 STM32F20x block 18 Multi AHB 0 2 5 20 Startup in regulator OFF slow Vpp slope power down reset risen after VcAp 1 2 2 25 Startup in regulator OFF fast Vpp slope power down reset risen before 1 2 Stabilization 25 STM32F20x LQFP64 pinout 37 STM32F20x WLCSP6442 37 STM32F20x LQFP100 38 STM32F20x LQFP144 1 39 STM32F20x LQFP176 1 40 STM32F20x UFBGA176 1 41 Memory Map ETE ete de ease a Nusa s 61 Pin loading 62 Pin input voltage iussum aee eR 62 Power supply scheme 1 63 Current consumption measurement scheme 64 Number of wait states versus fopy and Vpp 06 68 Ex
198. xx Table 42 Electrical sensitivities Symbol Parameter Conditions Class LU Static latch up class Ta 105 C conforming to JESD78A Il level A 5 3 15 current injection characteristics 96 174 As a general rule current injection to the I O pins due to external voltage below Vss or above Vpp for standard V capable pins should be avoided during normal product operation However in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens susceptibility tests are performed on a sample basis during device characterization Functional susceptibilty to current injection While a simple application is executed on the device the device is stressed by injecting current into the I O pins programmed in floating input mode While current is injected into the pin one at a time the device is checked for functional failures The failure is indicated by an out of range parameter ADC error above a certain limit 55 LSB TUE out of spec current injection on adjacent pins or other functional failure for example reset oscillator frequency deviation The test results are given in Table 43 Table 43 1 current injection susceptibility Functional susceptibility Symbol Description Negative Positive Unit injection injection Injected current on all FT pins 5 0 ling mA Injected current on any other pin 5 5
199. xx Figure 26 Typical current consumption vs temperature in Sleep mode peripherals ON 12651 mA 60 MS19018V1 Figure 27 Typical current consumption vs temperature in Sleep mode peripherals OFF IDDts mA 60 80 CPU Frequency MHz MS19019V1 76 174 Doc ID 15818 Rev 9 ky STM32F20xxx Electrical characteristics Table 21 Typical and maximum current consumptions in Stop mode Typ Max Symbol Parameter Conditions TA Ln Ts Unit 25 C 25 C 85 C 105 Flash in Stop mode low speed and high speed Supply current internal RC oscillators and high speed oscillator 0 55 1 2 11 00 20 00 in Stop mode OFF no independent watchdog with main Flash in Deep power down mode low speed regulatorin high speed internal RC oscillators and Run mode high speed oscillator OFF no independent 9 59 watchdog 6 Flash in Stop mode low speed and high speed Supply current internal RC oscillators and high speed oscillator 0 35 1 1 8 00 15 00 in Stop mode OFF no independent watchdog with main regulator in Flash in Deep power down mode low speed Low Power and high speed internal RC oscillators and 0 30 14 8 00 15 00 mode high speed oscillator OFF no independent watchdog 1 All typical and maximum values will be furt

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