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ST STM32F101x8 STM32F101xB handbook

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1. Description Figure 2 Clock tree gt FLITFCLK to Flash programming interface 8 MHz i HSI RC HSI 2 HCLK 36 MHz max to AHB bus core Clock memory and DMA sw 8 Enable 3 bits p to Cortex System timer PLLSRC PLLMUL L p FCLK Cortex HSI free running clock 2a X16 SYSCLK AHB APB1 SEM max BOU x2 x3 x4 gt Prescaler Prescaler gt PLL PLECLK 36 MHZ 5 512 1 2 4 8 16 I m max DUI Periphetal Clock Peripherals Enable 13 bits TIM2 3 4 toe css If APB1 prescaler 1 x1 TIMXCLK gt else X2 Peripheral Clock Enable 3 bits PLLXTPRE L SELON 36 MHz max Ss PCLK2 OSC our M 2 4 8 16 pa E 4 16 MHz e pie iis ad Peripheral Clock peripherals HSE OSC Enable 11 bits OSC_IN I1 2 E moe to ADC rescaler 128 12 4 6 8 ADCCLK OSC32 IN 3 LSE OSC use 5e 32 768 kHz RTCCLK OSC32 OUT RTCSEI 1 0 LSI RC i LSI to Independent Watchdog IWDG 40 kHz IWDGCLK Legend HSE high speed external clock signal HSI high speed internal clock signal Main H 2 PLLCLK LSI low speed internal clock signal Clock Output LSE low speed external clock signal MCO HSI HSE I SYSCLK MCO ai15104 1 When the HSI is used as a PLL clock input the maximum system clock frequency that can be achieved is 36 MHz 2 To have an ADC conversion time of 1 us APB2 must be at 14 MHz or 28 MHz Doc I
2. 1 Guaranteed by design not tested in production 2 The pull up is designed with a true resistance in series with a switchable PMOS This PMOS contribution to the series resistance must be minimum 1096 order Figure 28 Recommended NRST pin protection VDD External reset circuit 1 RPU Internal reset gt Filter STM32F10x ai14132d 1 The reset network protects the device against parasitic resets 2 The user must ensure that the level on the NRST pin can go below the Vi ygsr max level specified in 3 Table 37 Otherwise the reset will not be taken into account by the device Doc ID 13586 Rev 14 59 87 Electrical characteristics STM32F101x8 STM32F101xB 5 3 15 5 3 16 60 87 TIM timer characteristics The parameters given in Table 38 are guaranteed by design Refer to Section 5 3 12 I O current injection characteristics for details on the input output alternate function characteristics output compare input capture external clock PWM output Table 38 TIMx characteristics Symbol Parameter Conditions Min Max Unit e 1 tTIMXCLK tres TIM _ Timer resolution time ftimxcLk 36 MHz 27 8 ns js Timer external clock 0 FrimxcLk 2 MHz frequency on CH1 to CH4 frimxcuK 36 MHz 0 18 MHz Resp Timer resolution 16 bit 16 bit counter clock period 1 65536 ITIMXCLK tcouNrER When internal clock is selected frim
3. T cycles ts ps Rain Max kQ 1 5 0 11 0 4 7 5 0 54 5 9 13 5 0 96 11 4 28 5 2 04 25 2 41 5 2 96 37 2 55 5 3 96 50 71 5 5 11 NA 239 5 17 1 NA 1 Guaranteed by design not tested in production Table 44 ADC accuracy limited test conditions Symbol Parameter Test conditions Typ Max Unit ET Total unadjusted error fpcLk2 28 MHz 1 3 2 EO Offset error fanc 14 MHz Ran lt 10 KO 1 1 5 V 3Vto3 6V EG Gain error DDA bi 0 5 1 5 LSB Ta 25 C EL Integral linearity error ADC calibration 0 8 41 5 1 ADC DC accuracy values are measured after internal calibration 2 ADC Accuracy vs Negative Injection Current Injecting negative current on any of the standard non robust analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for Iinu pin and Xlin pin in Section 5 3 12 does not affect the ADC accuracy 3 Based on characterization not tested in production 3 Doc ID 13586 Rev 14 67 87 Electrical characteristics STM32F101x8 STM32F101xB Table 45 ADC accuracy 2 3 Symbol ET Parameter Total unadjusted error EO Offs
4. Table 2 Device features and peripheral counts STM32F101xx medium density access line Peripheral STM32F101Tx STM32F101Cx STM32F101Rx STM32F101Vx Flash Kbytes 64 128 64 128 64 128 64 128 SRAM Kbytes 10 16 10 16 10 16 10 16 2 General purpose 3 3 3 3 6 SPI 1 2 2 2 S Pc 1 2 2 2 c 2 E 5 USART 2 3 3 3 12 bit synchronized ADC 1 1 1 1 number of channels 10 channels 10 channels 16 channels 16 channels GPIOs 26 37 51 80 CPU frequency 36 MHz Operating voltage 2 0 to 3 6 V Operating temperatur s Ambient temperature 40 to 85 C see Table 8 P 9 P Junction temperature 40 to 105 C see Table 8 LQFP48 Pack VFQFPN36 LQFP64 LQFP1 ackages Q VFOFPN48 QFP6 QFP100 Doc ID 13586 Rev 14 11 87 Description STM32F101x8 STM32F101xB Figure 1 STM32F101xx medium density access line block diagram TRACECLK TRACEDI0 3 as AS aki re gus gt Trace E Ti Controller POWER JNTRSTC Voo 2to 3 6V JTDI VOLT REG JTCKISWCLK C dus De asvro1av Vss JTMS SWDIO 9
5. 140 DO 120 z 100 3 8 80 3 3 V d dons 9 O 40 20 0 po n 45 25 70 90 Temperature C ky Doc ID 13586 Rev 14 39 87 Elect rical characteristics STM32F101x8 STM32F101xB Figure 17 Typical current consumption in Stop mode with regulator in Low power mode versus temperature at Vpp 3 3 V and 3 6 V Consumption pA 100 90 80 70 60 3 3 V 50 m 3 6 V 40 30 20 10 45 C 25 C 85 C Temperature C Figure 18 Typical current consumption in Standby mode versus temperature at Vpp 3 3 V and 3 6 V Consumption pA 40 87 2 3 3 V 1 5 m 3 6 V 1 0 5 0 45 25 70 90 Temperature C Doc ID 13586 Rev 14 ky STM32F101x8 STM32F101xB Electrical characteristics Typical current consumption The MCU is placed under the following conditions e All I O pins are in input mode with a static value at Vpp or Vss no load e All peripherals are disabled except if it is explicitly mentioned e The Flash access time is adjusted to fjjc frequency 0 wait state from O to 24 MHz 1 wait state from 24 to 36 MHz e Prefetch is on reminder this bit must be set before clock setting and bus prescaling e When the peripherals are enabled fpci 1 fucikj4 fpcike fHcuK 2 ADCCLK frcLko 4 The parameters given in Table 16 are derived fr
6. Symbol Parameter Conditions Min Typ Max Unit fusi Frequency 8 MHz DuCy usi Duty cycle 45 55 Yo een with the RCC_CR 4 3 a register Ta 40 to 105 2 2 Yo ACC Accuracy of the HSI S Dip Ton e 2 S oscillator Factory Ta 10to85 C 1 5 2 2 4 calibrated 0 to 70 C 1 3 2 Ta 25 C 1 1 18 96 4 HSI oscillator tsu HSI startup time L HS 4 HSI oscillator power 80 100 LA consumption Ipp HSI Vpp 3 3 V Ta 40 to 105 C unless otherwise specified 2 Refer to application note AN2868 STM32F10xxx internal RC oscillator HSI calibration available from the ST website www st com Guaranteed by design not tested in production Based on characterization not tested in production q Doc ID 13586 Rev 14 STM32F101x8 STM32F101xB Electrical characteristics 5 3 8 Low speed internal LSI RC oscillator Table 24 LSI oscillator characteristics 1 Symbol Parameter Min Typ Max Unit fis Frequency 30 40 60 kHz tsuisy LSI oscillator startup time 85 us Ibos LSI oscillator power consumption 0 65 1 2 LA 1 Vpp 3 V Ta 40 to 85 C unless otherwise specified 2 Basedon characterization not tested in production 3 Guaranteed by design not tested in production Wakeup time from low power mode The wakeup times given in Table 25 are measured on a wakeup phase with an 8 MHz H
7. 78 87 Evaluating the maximum junction temperature for an application When ordering the microcontroller the temperature range is specified in the ordering information scheme shown in Table 53 Ordering information scheme Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and to a specific maximum junction temperature Here only temperature range 6 is available 40 to 85 C The following example shows how to calculate the temperature range needed for a given application making it possible to check whether the required temperature range is compatible with the STM32F101xx junction temperature range Example high performance application Assuming the following application conditions Maximum ambient temperature Tama 82 C measured according to JESD51 2 Ippmax 50 mA Vpp 3 5 V maximum 20 I Os used at the same time in output at low level with ly 8 mA Vo 0 4 V and maximum 8 l Os used at the same time in output mode at low level with loj 20 mA Vo 1 3 V PiNTmax 50 mA x 3 5 V 175 mW Piomax 20 x 8 mA x 0 4 V 8 x 20 mA x 1 3 V 272 mW This gives Pintmax 175 mW and Pjomax 272 mW Ppmax 175 272 447 mW Thus Ppmax 447 mW Using the values obtained in Table 52 T max is calculated as follows For LQFP64 45 C W Timax 82 C 45 C W x 447 mW 82 C 20 1 C 102 1 C This is within the junction temperature range of
8. e Prefetch in on reminder this bit must be set before clock setting and bus prescaling e When the peripherals are enabled fpci 1 fuci ko fPeLK2 fHciK The parameters given in Table 12 are derived from tests performed under the ambient temperature and Vpp supply voltage conditions summarized in Table 8 Doc ID 13586 Rev 14 35 87 Electrical characteristics STM32F101x8 STM32F101xB Table 12 Maximum current consumption in Run mode code with data processing running from Flash Max Symbol Parameter Conditions fucik Unit TA 85 C 36 MHz 28 6 External clock 2 all 24 MHz 19 9 peripherals enabled 16 MHz 14 7 Supply current 8 MHz 8 6 mA E in Run mode 36 MHz 19 8 External clock all 24 MHz 13 9 peripherals Disabled 16 MHz 10 7 8 MHz 6 8 1 Based on characterization not tested in production 2 External clock is 8 MHz and PLL is on when fic gt 8 MHz Table 13 Maximum current consumption in Run mode code with data processing running from RAM Max Symbol Parameter Conditions fucLk Unit TA 85 C 36 MHz 24 mA External clock all 24 MHz 17 5 peripherals enabled 16 MHz 125 i Supply current in 8 MHz 7 5 n Run mode 36 MHz 16 External clock all 24 MHz 11 5 peripherals disabled 16 MHz 8 5 8 MHz 5 5 1 Based on characterization tested in production at Vpp max fic xk max 2 External clock is 8
9. 3 3 V 2 I2C CCR value fscL kHz Rp 4 7 ka 400 Ox801E 300 0x8028 200 0x803C 100 0x00B4 50 0x0168 20 0x0384 Rp External pull up resistance fac I C speed 2 For speeds around 200 kHz the tolerance on the achieved speed is of 5 For other speed ranges the tolerance on the achieved speed 2 These variations depend on the accuracy of the external components used to design the application Doc ID 13586 Rev 14 4 STM32F101x8 STM32F101xB Electrical characteristics 3 SPI interface characteristics Unless otherwise specified the parameters given in Table 41 are derived from tests performed under the ambient temperature fpc frequency and Vpp supply voltage conditions summarized in Table 8 Refer to Section 5 3 12 I O current injection characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 41 SPI characteristics Symbol Parameter Conditions Min Max Unit f Master mode 0 18 SCK SPI clock frequency MHz l tcisck Slave mode 0 18 Heh SW pate I tal Capacitive load C 30 pF 8 t sck time tsu Nss NSS setup time Slave mode 4 tpcik truss NSS hold time Slave mode 73 1 lW SCKH SCK high and low time Master mode feci 38 MHz go 60 tw SCKL presc 4 t 1 Data input setup time SPH 1 SuMI Master mode SPI 5 bs 1 Data input setup tim
10. AYI STM32F101x8 STM32F101xB Medium density access line ARM based 32 bit MCU with 64 or 128 KB Flash 6 timers ADC and 7 communication interfaces Features m Core ARM 32 bit Cortex M3 CPU 36 MHz maximum frequency 1 25 DMIPS MHz Dhrystone 2 1 performance at O wait state memory access Single cycle multiplication and hardware division m Memories 64to 128 Kbytes of Flash memory 10to 16 Kbytes of SRAM m Clock reset and supply management 2 0 to 3 6 V application supply and I Os POR PDR and programmable voltage detector PVD 4 to 16 MHz crystal oscillator Internal 8 MHz factory trimmed RC Internal 40 kHz RC PLL for CPU clock 32 kHz oscillator for RTC with calibration m Low power LQFP64 14 x 14 mm 10x 10 mm LQFP48 VFQFPN48 VFQFPN36 7x7 mm 7x7 mm 6x6mm H Six timers Three 16 bit timers each with up to 4 IC OC PWM or pulse counter 2watchdog timers Independent and Window SysTick timer 24 bit downcounter m Upto 7 communication interfaces Upto 2 x IC interfaces SMBus PMBus Up to 3 USARTS ISO 7816 interface LIN IrDA capability modem control Upto2 SPls 18 Mbit s Sleep Stop and Standby modes m CRC calculation unit 96 bit unique ID Vegar supply for RTC and backup registers m ECOPACK packages m Debug mode i Serial wire debug SWD and JTAG Table 1 Device summary interf
11. Document revision history Date O6 Jun 2007 Revision 1 Changes First draft 20 Jul 07 80 87 Ipp values modified in Table 11 Maximum current consumption in Run and Sleep modes TA 85 C Vgar range modified in Power supply schemes VREF min value ISTAB liat and frRrIG added to Table 42 ADC characteristics Table 38 TIMx characteristics modified Note 6 modified and Note 8 Note 5 and Note 7 added below Table 4 Medium density STM32F101xx pin definitions Figure 20 Low speed external clock source AC timing diagram Figure 11 Power supply scheme Figure 28 Recommended NRST pin protection and Figure 29 I2C bus AC waveforms and measurement circuit 1 modified Sample size modified and machine model removed in Electrostatic discharge ESD Number of parts modified and standard reference updated in Static latch up 25 C and 85 C conditions removed and class name modified in Table 32 Electrical sensitivities tsu LsE changed to tsy sg in Table 21 HSE 4 16 MHz oscillator characteristics In Table 28 Flash memory endurance and data retention typical endurance added data retention for Ta 25 C removed and data retention for Ta 85 C added Note removed below Table 8 General operating conditions Vag changed to Vpegrint in Table 11 Embedded internal reference voltage Ipp max values added to Table 11 Maximum current consumption in Run and Sleep modes TA 85 C Ipp Hsi M
12. FT OSC IN 6 6 82 3 PD1 WO FT OSC OUT 54 83 PD2 WO FT PD2 TIM3 ETR zl os eub e PD3 WO FT PD3 USART2 CTS 85 PD4 WO FT PD4 USART2 RTS 26 87 Doc ID 13586 Rev 14 ky STM32F101x8 STM32F101xB Pinouts and pin description Table 4 Medium density STM32F101xx pin definitions continued Pins m Alternate functions 9 2 olg 3 Main 232 2 Pin name 2 3 function ce E Ta ma O after reset Default Remap GO G G 8 gt dz 86 PD5 yo FT PD5 USART2 TX 87 PD6 1 0 FT PD6 USART2_RX 88 PD7 1 0 FT PD7 USART2_CK TIM2_CH2 PB3 39 55 89 30 PB3 yo FT JTDO TRACESWO SPI1 SCK PB4 TIM3 CH1 40 56 90 31 PB4 1 0 FT JNTRST SPI1_MISO TIM3 CH2 41 57 91 32 PB5 1 0 PB5 12C1_SMBAI SPI1_MOSI I2C1 SCL 9 42 58 92 33 PB6 1 0 FT PB6 TIM4 CH1 8 USART1 TX 12C1_SDA 43 59 93 34 PB7 1 0 FT PB7 TIM4 CH2 8 USART1 RX 44 60 94 35 BOOTO l BOOTO 45 61 95 PB8 O FT PB8 TIM4 CH3 8 I2C1 SCL 46 62 96 PB9 WO FT PB9 TIM4 CH4 8 I2C1 SDA 97 PEO 1 0 FT PEO TIM4_ETR 98 PE1 1 0 FT PE1 47 63 99 36 Vss 3 S Vss 3 48 64 100 1 Vpp 3 S Vop 3 input O output S supply HiZ high impedance FT 5 V tolerant Function availability depends on the chosen device For devices having reduced peripheral counts it is always the lower
13. For C y and C it is recommended to use high quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator C y and C are usually the same size The crystal manufacturer typically specifies a load capacitance which is the series combination of C and C gt Load capacitance C has the following formula C C 4 x Cio Cj 4 Cj 5 Cstray where Cstay is the pin capacitance and board or trace PCB related capacitance Typically it is between 2 pF and 7 pF To avoid exceeding the maximum value of C 4 and C 15 pF it is strongly recommended to use a resonator with a load capacitance C 7 pF Never use a resonator with a load capacitance of 12 5 pF Example if you choose a resonator with a load capacitance of C 6 pF and Cstay 2 pF then C 4 C2 8 pF Doc ID 13586 Rev 14 47 87 Electrical characteristics STM32F101x8 STM32F101xB 5 3 7 48 87 Figure 22 Typical application with a 32 768 kHz crystal Resonator with integrated capacitors OL T S Bias 1 FA 32 768 KHz controlled L Qo uc ll STM32F10xxx Ci ai14129b Internal clock source characteristics The parameters given in Table 23 are derived from tests performed under the ambient temperature and Vpp supply voltage conditions summarized in Table 8 High speed internal HSI RC oscillator Table 23 HSI oscillator characteristics
14. Max Symbol Parameter Conditions Unit y Vpp Vgar Vpp VaAr Vpp Vgar Ta 2 0V 24V 33V 85 C Regulator in Run mode Low speed and high speed internal RC oscillators and high speed oscillator OFF 23 9 zi 209 Supply current no independent watchdog in Stop mode Regulator in Low Power mode Low speed and high speed internal RC Ni oscillators and high speed oscillator OFF ki has 180 i no independent watchdog DD Low speed internal RC oscillator and 7 26 34 UA independent watchdog ON Supply current Low speed internal RC oscillator ON 24 32 Ni in Standby independent watchdog OFF i mode Low speed internal RC oscillator and independent watchdog OFF low speed 1 7 2 4 oscillator and RTC OFF lbDD_vBAT monn O Low speed oscillator and RTC ON 0 9 1 1 1 4 1 9 1 Typical values are measured at T4 25 C 2 Based on characterization not rested in production q 38 87 Doc ID 13586 Rev 14 STM32F101x8 STM32F101xB Electrical characteristics Figure 15 Typical current consumption on Vga With RTC on versus temperature at different Veat values 2 5 4 lt 15 e 2v amp price p 42 4 V 3 M ioo x 3 V 8 057 3 6 V 40 C 25 C 70 C 85 C 105 C Temperature C ai17351 Figure 16 Typical current consumption in Stop mode with regulator in Run mode versus temperature at Vpp 3 3 V and 3 6 V
15. Figure 46 Recommended footprint Seating plane C 37 A ccc 0 25 mm Gage plane 48 Pin 1 identification 5B ME onm r E E A LI A l E B n 8 Y a i A 5 80 ka ER 3 iy S w co E c c 0000000 L ai14911b 1 Drawing is not to scale 2 Dimensions are in millimeters Table 51 LQFP48 7 x 7mm 48 pin low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 c 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 500 0 2165 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 500 0 2165 0 500 0 0197 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 3 5 7 0 3 5 7 ccc 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits 76 87 Doc ID 13586 Rev 14 SI STM32F101x8 STM32F101xB Package characteristics 6 2 6 2 1 Thermal characteristics The maximum chip junction temperature T jmax must never exceed the values given in Table 8
16. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock it can operate in Stop and Standby modes It can be used as a watchdog to reset the device when a problem occurs or as a free running timer for application timeout management It is hardware or software configurable through the option bytes The counter can be frozen in debug mode 2 3 16 Window watchdog The window watchdog is based on a 7 bit downcounter that can be set as free running It can be used as a watchdog to reset the device when a problem occurs It is clocked from the main clock It has an early warning interrupt capability and the counter can be frozen in debug mode 2 3 17 SysTick timer This timer is dedicated for OS but could also be used as a standard down counter It features e A24 bit down counter e Autoreload capability e Maskable system interrupt generation when the counter reaches O e Programmable clock source 2 3 18 General purpose timers TIMx There are three synchronizable general purpose timers embedded in the STM32F 101 xx medium density access line devices These timers are based on a 16 bit auto reload up down counter a 16 bit prescaler and feature 4 independent channels each for input 18 87 Doc ID 13586 Rev 14 ky STM32F101x8 STM32F101xB Description 2 3 19 2 3 20 2 3 21 2 3 22 2 3 23 capture output compare PWM or one pulse mode output This gives up to 12 input
17. STM32F101xx pin definitions VRERINT and Tcoett added to Table 11 Embedded internal reference voltage Typical Ipp vgar value added in Table 15 Typical and maximum current consumptions in Stop and Standby modes Figure 15 Typical current consumption on VBAT with RTC on versus temperature at different VBAT values added fuse ext min modified in Table 19 High speed external user clock characteristics C 4 and C gt replaced by C in Table 21 HSE 4 16 MHz oscillator characteristics and Table 22 LSE oscillator characteristics fLSE 32 768 kHz notes modified and moved below the tables Table 23 HSI oscillator characteristics modified Conditions removed from Table 25 Low power mode wakeup timings Figure 28 Recommended NRST pin protection modified Note 1 modified below Figure 21 Typical application with an 8 MHz crystal Figure 28 Recommended NRST pin protection modified IEC 1000 standard updated to IEC 61000 and SAE J1752 3 updated to IEC 61967 2 in Section 5 3 10 EMC characteristics on page 50 Jitter added to Table 26 PLL characteristics Cape and Rain parameters modified in Table 42 ADC characteristics RAN max values modified in Table 43 RAIN max for fADC 14 MHz Small text changes Doc ID 13586 Rev 14 85 87 Revision history STM32F101x8 STM32F101xB Table 54 Document revision history continued Date Revision Changes Added STM32F101TB devices Added VFQFPNA8 package Updated note 2
18. 0 0071 0 0091 0 0118 D 6 850 7 000 7 150 0 2697 0 2756 0 2815 D2 2 250 4 700 5 250 0 0886 0 1850 0 2067 E 6 850 7 000 7 150 0 2697 0 2756 0 2815 E2 2 250 4 700 5 250 0 0886 0 1850 0 2067 e 0 450 0 500 0 550 0 0177 0 0197 0 0217 L 0 300 0 400 0 500 0 0118 0 0157 0 0197 ddd 0 080 0 0031 Values in inches are converted from mm and rounded to 4 decimal digits q STM32F101x8 STM32F101xB Package characteristics Figure 39 VFQFPN366x6mm 0 5 mm pitch package Figure 40 Recommended footprint dimensions in mm outline Seating plane Cc Pin 1 1D Drawing is not to scale 2 All leads pads should also be soldered to the PCB to improve the lead solder joint life ZR_ME 0 50 aitas7ob Table 48 VFQFPN36 6 x 6 mm 0 5 mm pitch package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 0 800 0 900 1 000 0 0315 0 0354 0 0394 Al 0 020 0 050 0 0008 0 0020 A2 0 650 1 000 0 0256 0 0394 A3 0 250 0 0098 b 0 180 0 230 0 300 0 0071 0 0091 0 0118 D 5 875 6 000 6 125 0 2313 0 2362 0 2411 D2 1 750 3 700 4 250 0 0689 0 1457 0 1673 E 5 875 6 000 6 125 0 2313 0 2362 0 2411 E2 1 750 3 700 4 250 0 0689 0 1457 0 1673 e 0 450 0 500 0 550 0 0177 0 0197 0 0217 E 0
19. 0 3 the internal pull up pull down resistors must be disabled ason Leakage could be higher than max if negative current is injected on adjacent pins PMOS NMOS contribution to the series resistance is minimum 1096 order 54 87 Doc ID 13586 Rev 14 Hysteresis voltage between Schmitt trigger switching levels Based on characterization not tested in production With a minimum of 100 mV Pull up and pull down resistors are designed with a true resistance in series with a switchable PMOS NMOS This q STM32F101x8 STM32F101xB Electrical characteristics All I Os are CMOS and TTL compliant no software configuration required Their characteristics cover more than the strict CMOS technology or TTL parameters The coverage of these requirements is shown in Figure 23 and Figure 24 for standard I Os and in Figure 25 and Figure 26 for 5 V tolerant I Os Figure 23 Standard I O input characteristics CMOS port Vip Vip V reme CMOS standard requirem Vitamin 13 dsv DD quirement Va 79 pr A as oc Vpp V ai17277b Figure 24 Standard I O input characteristics TTL port VIH YIL V TTL requirements Vj4 2V ViHmin 2 0 1 3 2 0 8 Vy 0 28 VDD i Vilmax 0 8 us i TTL requirements V 0 8V f L 1 LI Vpp V ai17278 ky Doc ID 13586 Rev 14 55 87 Electrical characteristics STM32F101x8 STM32F101xB Figure 25 5 V tolerant I O
20. 126 Pulse width of external tExTipw Signals detected by the 10 ns EXTI controller 1 The I O speed is configured using the MODEx 1 0 bits Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register The maximum frequency is defined in Figure 27 3 Guaranteed by design not tested in production 4 58 87 Doc ID 13586 Rev 14 STM32F101x8 STM32F101xB Electrical characteristics Figure 27 MO AC characteristics definition EXTERNAL t r IO out re t t10 out i OUTPUT ON 50pF 1 re Maximum frequency is achieved if t tf x 2 3 T and if the duty cycle is 45 55 when loaded by 50pF ai14131 5 3 14 NRST pin characteristics The NRST pin input driver uses CMOS technology It is connected to a permanent pull up resistor Rpy see Table 34 Unless otherwise specified the parameters given in Table 37 are derived from tests performed under the ambient temperature and Vpp supply voltage conditions summarized in Table 8 Table 37 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VinesT NRST Input low level voltage 0 5 0 8 y Vit NRST Input high level voltage 2 Vpp 0 5 NRST Schmitt trigger voltage Vhys NRST hysteresis ayy mv Rpu Weak pull up equivalent resistor Viy Vss 30 40 50 ka Verst NRST Input filtered pulse 100 ns VNE NRST NRST Input not filtered pulse 300 ns
21. 350 0 550 0 750 0 0138 0 0217 0 0295 ddd 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits Lyr Doc ID 13586 Rev 14 73 87 Package characteristics STM32F101x8 STM32F101xB Figure 41 LQFP100 14 x 14 mm 100 pin low profile Figure 42 Recommended footprint quad flat package outline 75 51 t 10100010 0000 OO 76 350 a 0 5 i M E 0 3 167 143 E E i E Xx i Mo000000000000000000000 ie _ L is Ka lt 16 7 Fr ai14906 SEATING PLANE HA T 1 Drawing is not to scale 2 Dimensions are in millimeters Table 49 LQPF100 14 x14 mm 100 pin low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 60 0 063 A1 0 05 0 15 0 002 0 0059 A2 1 35 1 40 1 45 0 0531 0 0551 0 0571 b 0 17 0 22 0 27 0 0067 0 0087 0 0106 C 0 09 0 2 0 0035 0 0079 D 15 80 16 00 16 2 0 622 0 6299 0 6378 D1 13 80 14 00 14 2 0 5433 0 5512 0 5591 D3 12 00 0 4724 E 15 80 16 00 16 2 0 622 0 6299 0 6378 E1 13 80 14 00 14 2 0 5433 0 5512 0 5591 E3 12 00 0 4724 0 50 0 0197 0 45 0 60 0 75 0 0177 0 0
22. Cycle to cycle jitter 300 ps 1 Based on device characterization not tested in production 2 Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fp our 5 3 9 Memory characteristics Flash memory The characteristics are given at T4 40 to 85 C unless otherwise specified Table 27 Flash memory characteristics Symbol Parameter Conditions Min Typ Max Unit tprog 16 bit programming time TA 40 to 85 C 40 52 5 70 us terase Page 1 KB erase time TA 7 40 to 85 C 20 40 ms tME Mass erase time Ta 7 40 to 85 C 20 40 ms Read mode fucik 36 MHz with 1 wait 20 mA state Vpp 3 3 V Ipp Supply current Write Erase modes 5 mA fHcLK 36 MHz Vop 3 3V Power down mode Halt Vop 3 0 to 3 6 V SO TuS Vbrog Programming voltage 2 3 6 V 1 Guaranteed by design not tested in production Table 28 Flash memory endurance and data retention Value Symbol Parameter Conditions Ho Unit Min Typ Max FNENp Endurance Me 40 Cto856 C 10 kcydes Ta 85 C 1 kcycle 30 Ta 55 C 10 kcycle 20 Years trer Data retention 1 Based on characterization not tested in production 2 Cycling performed over the whole temperature range 5 3 10 EMC characteristics Susceptibility tests are performed on a sample basis during device ch
23. Doc ID 13586 Rev 14 25 87 Pinouts and pin description STM32F101x8 STM32F101xB Table 4 Medium density STM32F101xx pin definitions continued Pins m Alternate functions co o Main S22 S 2 Pin name 3 function A T Ta 2 O after reset Default Remap Sg 3 5 8 gt gt 55 PD8 VO FT PD8 USART3_TX 56 PD9 VO FT PD9 USART3 RX 57 PD10 WO FT PD10 USART3 CK ka 5B os PD11 VO FT PD11 USART3_CTS 59 PD12 WO FT PD12 foes 60 PD13 WO FT PD13 TIM4 CH2 61 PD14 VO FT PD14 TIM4 CH3 ee a SE PD15 WO FT PD15 TIM4 CH4 37 63 PC6 VO FT PC6 TIM3 CH1 38 64 PC7 WO FT PC7 TIM3 CH2 39 65 PC8 VO FT PC8 TIM3 CH3 40 66 PC9 VO FT PC9 TIM3 CH4 29 41 67 20 PA8 WO FT PAS USART1_CK MCO 30 42 68 21 PAQ VO FT PA9 USART1 TX 31 43 69 22 PA10 VO FT PA10 USART1 RX 32 44 70 23 PA11 WO FT PA11 USART1 CTS 33 45 71 24 PA12 WO FT PA12 USART1 RTS 34 46 72 25 PA13 WO FT JTMS SWDIO PA13 73 Not connected 35 47 74 26 Vss 2 S Vss 2 36 48 75 27 Vop 2 S Vop 2 37 49 76 28 PA14 WO FT JTCK SWCLK PA14 38 50 77 29 PA15 WO FT JTDI L ian 51 78 PC10 WO FT PC10 USART3 TX 52 79 PC11 WO FT PC11 USART3 RX 53 80 PC12 WO FT PC12 USART3 CK 5 15 81 2 PDO WO
24. General operating conditions on page 32 The maximum chip junction temperature Tj max in degrees Celsius may be calculated using the following equation Ty max Ta max Pp max x O ya Where e Ta max is the maximum ambient temperature in C e Oy is the package junction to ambient thermal resistance in C W e Pp max is the sum of P yy max and Pyo max Pp max P yy max Pyomax e Pint max is the product of Ipp and Vpp expressed in Watts This is the maximum chip internal power Pio max represents the maximum power dissipation on output pins where Pio max Z Vo x loi Z Vpp Vou x lou taking into account the actual Vot loj and Voy lop of the I Os at low and high level in the application Table 52 Package thermal characteristics Symbol Parameter Value Unit Thermal resistance junction ambient 46 LQFP 100 14 x 14 mm 0 5 mm pitch Thermal resistance junction ambient 45 LQFP 64 10 x 10 mm 0 5 mm pitch Thermal resistance junction ambient 5 OJA LQFP 48 7 x 7 mm 0 5 mm pitch 39 GW Thermal resistance junction ambient 16 VFQFPN 48 6 x 6 mm 0 5 mm pitch Thermal resistance junction ambient 18 VFQFPN 36 6 x 6 mm 0 5 mm pitch Reference document JESD51 2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection Still Air Available from www jedec org Doc ID 13586 Rev 14 77 87 Package characteristics STM32F101x8 STM32F101xB 6 2 2
25. Output Low level voltage for an I O pin VoL when 8 pins are sunk at the same time CMOS port ga Output High level voltage for an I O pi VU 3 utput High level voltage for an I O pin 2 7 V lt Vpop lt 3 6 V v0 4 Vou wnen8 pins are sourced at the same time pp 0 1 Output low level voltage for an I O pin 2 Vou when 8 pins are sunk at the same time TTL port oS Output high level voltage for an 1 0 pi D Y 3 utput high level voltage for an pin 27N V 3 6 V VoH when 8 pins are sourced at the same time lt DD es VaL Output low level voltage for an I O pin 13 when 8 pins are sunk at the same time lio 20 mA vo 9 Output high level voltage for an I O pin 2 7 V lt Voo lt 36 V y a 3 OH when 8 pins are sourced at the same time Dor 1 Output low level voltage for an I O pin Vo 0 4 when 8 pins are sunk at the same time lio 6 mA T v8 Output high level voltage for an I O pin 2V Vpp 2 7 V Vpp 0 4 OH when8 pins are sourced at the same time 1 The lig current sunk by the device must always respect the absolute maximum rating specified in Table 6 and the sum of lig I O ports and control pins must not exceed lyss TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52 3 The lig current sourced by the device must always respect the absolute maximum rating specified in Table 6 and the sum of lig I O ports and control pins must not exceed lypp 4 Based o
26. and Vpp supply voltage conditions summarized in Table 8 Table 11 Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit VrerinT Internal reference voltage 40 C lt TA lt 85 C 1 16 1 20 1 24 V Ts vreti AA AE aa ag 51 17180 ys VRERINT pe ki on le Vpp 3 V 10 mV 10 mV Tcoeti Temperature coefficient 100 s 1 Shortest sampling time can be determined in the application by multiple iterations 2 Guaranteed by design not tested in production Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage ambient temperature I O pin loading device software configuration operating frequencies I O pin switching rate program location in memory and executed binary code The current consumption is measured as described in Figure 12 Current consumption measurement scheme All Run mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2 1 code Maximum current consumption The MCU is placed under the following conditions e AI I O pins are in input mode with a static value at Vpp or Vss no load e All peripherals are disabled except if it is explicitly mentioned e The Flash access time is adjusted to fycik frequency 0 wait state from O to 24 MHz 1 wait state from 24 to 36 MHz
27. between all the different ground 50 pins Electrostatic discharge voltage human body kise iiid me i bicis VESD HBM model maximum ratings electrical sensitivity 1 All main power Vpp Vppa and ground Vss Vasa pins must always be connected to the external power supply in the permitted range 2 Vin maximum must always be respected Refer to Table 6 Current characteristics for the maximum allowed injected current values 3 Doc ID 13586 Rev 14 31 87 Electrical characteristics STM32F101x8 STM32F101xB Table 6 Current characteristics Symbol Ratings Max Unit lypp Total current into Vpp Vppa power lines source 150 lyss Total current out of Vss ground lines sink 150 k Output current sunk by any I O and control pin 25 Output current source by any I Os and control pin 25 mA 2 Injected current on five volt tolerant pins 5 0 POE Injected current on any other pin 5 ZIiNu PIN Total injected current sum of all I O and control pins 25 1 All main power Vpp Vppa and ground Vss Vssa pins must always be connected to the external power supply in the permitted range 2 Negative injection disturbs the analog performance of the device See note in Section 5 3 17 12 bit ADC characteristics 3 Positive injection is not possible on these I Os A negative injection is induced by VinsVss l nu p in must never be exceeded Refer to Table 5 Voltage cha
28. eee 62 SPI characteristics ete tent w kn aou kn a a kn w a a won non w ka a n n kn n kn 63 ADC characteriStiCS reel tk ann kk w a w kn won ko w a a kon non a ka a kon ka n ka 66 Rain Max forfapc 14 MHZ LIL eee 67 Doc ID 13586 Rev 14 5 87 List of tables STM32F101x8 STM32F101xB Table 44 ADC accuracy limited test conditions ee e er eee eee 67 Table 45 ADC accuracy ll elu kn l slu kn ken kaa a ka kaa a ka w ka a ka koka koka knn 68 Table 46 TSCharacteriStiCS tee tee kaa kaa kaa kaa kaa koka kaa kaa konn 70 Table 47 VFQFPN48 7 x 7 mm 0 5 mm pitch package mechanical data 72 Table 48 VFQFPNS36 6 x 6 mm 0 5 mm pitch package mechanical data 73 Table 49 LQPF100 14 x14 mm 100 pin low profile quad flat package mechanical data 74 Table 50 LQFP64 10 x 10 mm 64 pin low profile quad flat package mechanical data 75 Table 51 LQFP48 7 x 7mm 48 pin low profile quad flat package mechanical data 76 Table 52 Package thermal characteristics 2l 77 Table 53 Ordering information scheme el ll l ks L kk kn ak kw a a ka w n w ka a n kk n a n ka n ka 79 Table 54 Document revision history e Gel tk ken kk ee a w kaa n w kaa n kaa n n 80 6 87 Doc ID 13586 Rev 14 ky STM32F101x8 STM32F101xB List of figures List of figures
29. gt e p SMS MEM oe disi SO MISO i H OUTPUT 8 MSB OUT BIT6 OUT LSBOUT OUT tsu si gt le gt MOSI T INPUT MSN IN BIT1 IN LEN IN ai14135 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7Vpp 4 64 87 Doc ID 13586 Rev 14 STM32F101x8 STM32F101xB Electrical characteristics Figure 32 SPI timing diagram master mode High NSS input SCK Input O T BE T o SCK Input O v T i n MI p OUTUT MT U MO th MO lt gt ai14136 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7Vpp ky Doc ID 13586 Rev 14 65 87 Electrical characteristics STM32F101x8 STM32F101xB 5 3 17 12 bit ADC characteristics Unless otherwise specified the parameters given in Table 42 are derived from tests performed under the ambient temperature fpc o frequency and Vppa supply voltage conditions summarized in Table 8 Note It is recommended to perform a calibration after each power up Table 42 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VppA Power supply 2 4 3 6 V VREF Positive reference voltage 2 4 VDDA V er sa on the Vper input 160 220 UA fapc ADC clock frequency 0 6 14 MHz fs Sampling rate 0 05 1 MHz f 14 MHz 823 kHz ftriga External trigger frequency 17 1 fapc V 3 0 Vgga OF VREF AIN Conversion voltage range tied to g
30. having an embedded ARM core is therefore compatible with all ARM tools and software Embedded Flash memory 64 or 128 Kbytes of embedded Flash is available for storing programs and data CRC cyclic redundancy check calculation unit The CRC cyclic redundancy check calculation unit is used to get a CRC code from a 32 bit data word and a fixed generator polynomial Among other applications CRC based techniques are used to verify data transmission or storage integrity In the scope of the EN IEC 60335 1 standard they offer a means of verifying the Flash memory integrity The CRC calculation unit helps compute a signature of the software during runtime to be compared with a reference signature generated at link time and stored at a given memory location Embedded SRAM Up to 16 Kbytes of embedded SRAM accessed read write at CPU clock speed with O wait states Nested vectored interrupt controller NVIC The STM32F101xx medium density access line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels not including the 16 interrupt lines of Cortex M3 and 16 priority levels e Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of ate arriving higher priority interrupts Support for tail chaining Processor state automaticall
31. in tough humidity conditions 4 tsu usg is the startup time measured from the moment it is enabled by software to a stabilized 8 MHz oscillation is reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For C 4 and Co it is recommended to use high quality external ceramic capacitors in the 5 pF to 25 pF range typ designed for high frequency applications and selected to match the requirements of the crystal or resonator see Figure 21 C 4 and C gt are usually the same size The crystal manufacturer typically specifies a load capacitance which is the series combination of C and C 2 PCB and MCU pin capacitance must be included 10 pF can be used as a rough estimate of the combined pin and board capacitance when sizing C 4 and Cj Refer to the application note AN2867 Oscillator design guide for ST microcontrollers available from the ST website www st com Figure 21 Typical application with an 8 MHz crystal Resonator with integrated capacitors ON MATYE pi resonator MES mn CLo Rex STM32F10xxx ai14128b 1 Rexr value depends on the crystal characteristics Low speed external clock generated from a crystal ceramic resonator The low speed external LSE clock can be supplied with a 32 768 kHz crystal ceramic resonator oscillator All the information given in this paragraph are based on characterization
32. input characteristics CMOS port VIH VIL V Mput range not guaranteed S standard requirmg Vpp V e A VDD ai17279b Figure 26 5 V tolerant I O input characteristics TTL port VIH VIL V TTL requirement V y 2V 20 ViHmin E i ViLmax 0 8 2 2 16 YDD v ai17280 56 87 Doc ID 13586 Rev 14 ky STM32F101x8 STM32F101xB Electrical characteristics Output driving current The GPIOs general purpose inputs outputs can sink or source up to 8 mA and sink or source up to x20 mA with a relaxed Vo Von In the user application the number of I O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5 2 e The sum of the currents sourced by all the I Os on Vpp plus the maximum Run consumption of the MCU sourced on Vpp cannot exceed the absolute maximum rating lypp see Table 6 e The sum of the currents sunk by all the I Os on Vgs plus the maximum Run consumption of the MCU sunk on Vgs cannot exceed the absolute maximum rating lvss see Table 6 Output voltage levels Unless otherwise specified the parameters given in Table 35 are derived from tests performed under the ambient temperature and Vpp supply voltage conditions summarized in Table 8 All I Os are CMOS and TTL compliant Table 35 Output voltage characteristics Symbol Parameter Conditions Min Max Unit 1
33. number of peripherals that is included For example if a device has only one SPI two USARTs and two timers they will be called SPI1 USART1 8 USART2 and TIM2 amp TIM 3 respectively Refer to Table 2 on page 11 4 If several peripherals share the same I O pin to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit in the corresponding RCC peripheral clock enable register 5 PC13 PC14 and PC15 are supplied through the power switch Since the switch only sinks a limited amount of current 3 mA the use of GPIOs PC13 to PC15 in output mode is limited the speed should not exceed 2 MHz with a maximum load of 30 pF and these lOs must not be used as a current source e g to drive an LED Main function after the first backup domain power up Later on it depends on the contents of the Backup registers even after reset because these registers are not reset by the main reset For details on how to manage these IOs refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual available from the STMicroelectronics website www st com The pins number 2 and 3 in the VFQFPN36 package and 5 and 6 in the LQFP48 and LQFP64 packages are configured as OSC IN OSC OUT after reset however the functionality of PDO and PD1 can be remapped by software on these pins For the LQFP100 package PDO and PD1 are available by defau
34. rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST pr
35. the STM32F101xx 40 lt Ty lt 105 C Figure 47 LQFP64 Pp max vs Ta 700 600 500 400 300 Suffix 6 Pp mW 65 75 85 95 105 115 Ta C Doc ID 13586 Rev 14 ky STM32F101x8 STM32F101xB Ordering information scheme 7 Ordering information scheme Table 53 Ordering information scheme Example STM32 F 101C 8 T 6 Xxx Device family STM32 ARM based 32 bit microcontroller Product type F general purpose Device subfamily 101 access line Pin count T 36 pins C 48 pins R 64 pins V 100 pins Flash memory size 8 64 Kbytes of Flash memory B 128 Kbytes of Flash memory Package T LQFP U VFQFPN Temperature range 6 Industrial temperature range 40 to 85 C Options xxx programmed parts TR tape and real 1 Although STM32F101x6 devices are not described in this datasheet orderable part numbers that do not show the A internal code after temperature range code 6 should be referred to this datasheet for the electrical characteristics The low density datasheet only covers STM32F101x6 devices that feature the A code For a list of available options speed package etc or for further information on any aspect of this device please contact your nearest ST sales office Doc ID 13586 Rev 14 79 87 Revision history STM32F101x8 STM32F101xB 8 Revision history Table 54
36. voltage into a digital value Serial wire JTAG debug port SWJ DP The ARM SWJ DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG DP and SW DP Doc ID 13586 Rev 14 ky STM32F101x8 STM32F101xB Pinouts and pin description 3 Pinouts and pin description Figure 3 STM32F101xx medium density access line LQFP100 pinout li a a o AnN ronolROQLW STAONRQLKTAMANTOCr rr 2X Qdouumgmamommaumauoaaaaaaaaaoooca x nnanuncdaannnannannzatnunacgnmurtu o PERIANA AAA y PE2L 1 75 VDD 2 PESO 2 741 VSS 2 PE40 3 73H NC PE5O 4 720 PA 13 PE6O 5 71H PA 12 VBATC 6 70 H PA 11 PC13 TAMPER RTC O 7 69 PA 10 PC14 OSC32_INC 8 68 O PA9 PC15 OSC32_OUTC 9 67 D PAB VSS 50 10 s PC9 VDD 50 11 65 n PC8 OSC INH 12 LQFP100 64 H PC7 OSC OUTH 13 63 A PC6 NRSTQ 14 621 PD15 PCOd 15 61 PD14 PC1d 16 60 PD13 PC2r 17 59h PD12 PC3d 18 58 O PD11 VSSAC 19 57 D PD10 VREF rj 20 56 n PD9 VREF 21 551 PD8 VDDAC 22 541 PB15 PAO WKUPd 23 83 B PB14 PA1r 24 5215 PB13 PA2Q 25 51 PB12 NNANAOGOOOOGODOODOSTSSSTYYSS YD 2x iee5389ng
37. 0 pF T ai14123b ai14124b Power supply scheme Figure 11 Power supply scheme Backup circuitry 1 8 3 6V A YA Power switch OSC32K RTC Wake up logic Backup registers PRERE EE E e eI E Kernel logic CPU Digital amp Memories VDD 1 2 3 4 5 5 x 100 nF Vss 1x4 7 uF ESTO v Analog 1010F ADC RCs PLL 1pgF In Figure 11 the 4 7 uF capacitor must be connected to Vpp3 Doc ID 13586 Rev 14 PH ai14125d q STM32F101x8 STM32F101xB Electrical characteristics 5 1 7 Current consumption measurement Figure 12 Current consumption measurement scheme ai14126 5 2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 5 Voltage characteristics Table 6 Current characteristics and Table 7 Thermal characteristics may cause permanent damage to the device These are stress ratings only and functional operation of the device at these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 5 Voltage characteristics Symbol Ratings Min Max Unit External main supply voltage including Vpp V 0 3 4 0 DD SS Vopa and Vpp v 2 Input voltage on five volt tolerant pin Vss 0 3 Vpp 4 0 y IN A A a RN ne Input voltage on any other pin Vss 0 3 4 0 IAV ppxl Variations between different Vpp power pins 50 e A mV IVssx Vsgl Variations
38. 00 20 0 1C 300 ns tr scL spa SDA and SCL fall time 300 300 tScL ism Start condition hold time 4 0 0 6 Repeated Start condition setu Us teu STA idi P 47 0 6 tsu sto Stop condition setup time 4 0 0 6 us Stop to Start condition time bus lw STO STA ies 4 7 1 3 ps Ch Capacitive load for each bus line 400 400 pF 1 Guaranteed by design not tested in production 2 fpcik4 must be higher than 2 MHz to achieve standard mode I C frequencies It must be higher than 4 MHz to achieve fast mode IC frequencies It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock 3 The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal 4 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL Doc ID 13586 Rev 14 61 87 Electrical characteristics STM32F101x8 STM32F101xB 62 87 Figure 29 12C bus AC waveforms and measurement circuit VDD VDD STM32F10x Start SDA PH He l SDA MAT dics T Mu OM i i Stop i gt tsu STO STA Leo Ih STA wSCHL l th SDA pou SCL 1 l LI LI L tw SCLH T l SCL gt gt t SCL su STO ai14133d 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7Vpp Table 40 SCL frequency fpc k1 36 MHz Vpp
39. 12 iex PA11 Veda PA10 PAO WKUP PA9 PA1 PA8 PA2 VDD 4 ai14654 Y Doc ID 13586 Rev 14 23 87 Pinouts and pin description STM32F101x8 STM32F101xB Table 4 Medium density STM32F101xx pin definitions Pins iS Alternate functions 2 olg 2 9 Main Sz 3 8 2 Pin name 9 9 function ch fe O after reset Default Remap 823 88 B Ehe LATI E NM NE 1 PE2 1 0 FT PE2 TRACECLK 2 PE3 1 0 FT PE3 TRACEDO 3 PE4 1 0 FT PE4 TRACED1 4 PE5 1 0 FT PE5 TRACED2 5 PE6 1 0 FT PE6 TRACED3 1 LO A VBAT S VBAT PC13 TAMPER 6 2 2 7 RTC I O Pc13 6 TAMPER RTC i PC14 6 3 8 8 Gscso ine PC14 OSC32 IN i PC15 6 4 4 9 OSC32_0UT y o PC15 OSC32 OUT eo ep Vss 5 S Vss 5 LAA Vpp 5 S Vpp 5 5 5 12 2 OSC IN OSC_IN 6 6 13 3 OSC_OUT O OSC_OUT 7 7 14 4 NRST 1 0 NRST 8 15 PCO 1 0 PCO ADC_IN10 9 16 PC1 1 0 PC1 ADC IN11 10 17 PC2 1 0 PC2 ADC_IN12 11 18 PC3 1 0 PC3 ADC_IN13 20 VREF S VREF ZR AE A VREF S VREF WKUP USART2_CTS 10 14 23 7 PAO WKUP 1 0 PAO ADC INO TIM2 CH1 ETR 8 11 15 24 8 PA1 1 0 PA1 MB EUH 8 12 16 25 9 PA2 O PA2 m 7 ea 368 8 13 17 26 10 PA3 O PA3 Ab E pesci 48 18 27 Ves 4 S Vss 4 24 87 Doc ID 13586 Rev 14 ky STM32F101x8 STM32F101xB Pinouts and pin description
40. 2 bit ADC characteristics eee eee 66 5 3 18 Temperature sensor characteristics eeeo 70 Package characteristics eee nna nn ann nannan nn nn nn 71 6 1 Package mechanical data llis 71 6 2 Thermal characteristics eee TI 6 2 1 Reference document Lo TI 6 2 2 Evaluating the maximum junction temperature for an application 78 Doc ID 13586 Rev 14 3 87 Contents STM32F101x8 STM32F101xB 4 87 Ordering information scheme nn nannan nn nn 79 Revision history mi ai aaa aca n n RE ACRCRC OR ED sd Rc e ne 80 Doc ID 13586 Rev 14 ky STM32F101x8 STM32F101xB List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 kI Device SUMMAMY kai iul ess m ena ea ena pa RISE A Ab ede Sa ee s 1 Device features and peripheral counts STM32F101xx medium density access NINE oues pp dae ee Ra RE an es pP ace eA RO DEN noe RU 11 STM32F101xxfamily tel eee kan ken kaa hh 14
41. 236 0 0295 L1 1 00 0 0394 k 0 3 5 7 0 0 3 5 7 0 ccc 0 08 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits 74 87 Doc ID 13586 Rev 14 SI STM32F101x8 STM32F101xB Package characteristics Figure 43 LQFP64 10 x 10 mm 64 pin low profile quad flat package outline Figure 44 Recommended footprint DOT CE WHERE AE O DETA AT HER d ERES ait4398t a o 00000000 7 imm OOOO o E 0 3 oono 3 m Te fr iI27 nu 53 0 3 ai14909 1 Drawing is not to scale 2 Dimensions are in millimeters Table 50 LQFP64 10 x 10 mm 64 pin low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 60 0 0630 A1 0 05 0 15 0 0020 0 0059 A2 1 35 1 40 1 45 0 0531 0 0551 0 0571 b 0 17 0 22 0 27 0 0067 0 0087 0 0106 c 0 09 0 20 0 0035 0 0079 D 12 00 0 4724 D1 10 00 0 3937 E 12 00 0 4724 E1 10 00 0 3937 e 0 50 0 0197 0 0 3 5 7 0 3 5 7 L 0 45 0 60 0 75 0 0177 0 0236 0 0295 L1 1 00 0 0394 Number of pins N 64 1 Values in inches are converted from mm and rounded to 4 decimal digits Ky Doc ID 13586 Rev 14 75 87 Package characteristics STM32F101x8 STM32F101xB Figure 45 LQFP48 7 x 7mm 48 pin low profile quad flat package outline
42. 3 VFQFPN36 1000 Maximum power dissipation 40 85 C TA Ambient temperature Low power dissipation 40 105 SE TJ Junction temperature range 40 105 C 1 When the ADC is used refer to Table 42 ADC characteristics 2 Itis recommended to power Vpp and Vppa from the same source A maximum difference of 300 mV between Vpp and Vppa can be tolerated during power up and operation 3 If T4 is lower higher Pp values are allowed as long as Tj does not exceed T ymax see Table 6 2 Thermal characteristics on page 77 4 In low power dissipation state T can be extended to this range as long as Tj does not exceed T ymax see Table 6 2 Thermal characteristics on page 77 Operating conditions at power up power down Subject to general operating conditions for Ta Table 9 Operating conditions at power up power down Symbol Parameter Conditions Min Max Unit Vpp rise time rate 0 00 tvpp us V Vpp fall time rate 20 00 Embedded reset and power control block characteristics The parameters given in Table 10 are derived from tests performed under the ambient temperature and Vpp supply voltage conditions summarized in Table 8 Doc ID 13586 Rev 14 33 87 Electrical characteristics STM32F101x8 STM32F101xB 34 87 Table 10 Embedded reset and power control block characteristics Symbol Parameter Conditi
43. 3586 Rev 14 81 87 Revision history STM32F101x8 STM32F101xB 82 87 Table 54 Document revision history continued Date 22 Nov 2007 Revision Changes Document status promoted from preliminary data to datasheet Small text changes STM32F101CB part number corrected in Table 1 Device summary Number of communication peripherals corrected for STM32F101Tx in Table 2 Device features and peripheral counts STM32F101xx medium density access line and Number of GPIOs corrected for LQFP package Power supply schemes on page 16 modified Main function and default alternate function modified for PC14 and PC15 in Table 4 Medium density STM32F101xx pin definitions Note 6 added Remap column added Figure 11 Power supply scheme modified Vpp Vss ratings modified and Note 1 modified in Table 5 Voltage characteristics Note 1 modified in Table 6 Current characteristics Note 2 added in Table 10 Embedded reset and power control block characteristics 48 and 72 MHz frequencies removed from Table 12 Table 13 and Table 14 MCU s operating conditions modified in Typical current consumption on page 41 lbp vegar typical value at 2 4 V modified and Ipp ygar maximum value added in Table 15 Typical and maximum current consumptions in Stop and Standby modes Note added in Table 16 on page 41 and Table 17 on page 42 Table 18 Peripheral current consumption modified Figure 17 Typical current consumption in Sto
44. 54 Document revision history continued Date 14 Mar 2008 Revision Changes Figure 2 Clock tree on page 13 added CRC added see CRC cyclic redundancy check calculation unit on page 9 and Figure 8 Memory map on page 28 for address Maximum Ty value given in Table 7 Thermal characteristics on page 32 Pp Ta and Ty added tprog values modified and tprog description clarified in Table 27 Flash memory characteristics on page 50 Ibp modified in Table 15 Typical and maximum current consumptions in Stop and Standby modes on page 38 ACChs modified in Table 23 HSI oscillator characteristics on page 48 note 2 removed tret modified in Table 28 Flash memory endurance and data retention VNF NRST Unit corrected in Table 37 NRST pin characteristics on page 59 Table 41 SPI characteristics on page 63 modified IvrREF added in Table 42 ADC characteristics on page 66 Table 44 ADC accuracy limited test conditions added Table 45 ADC accuracy modified LQFP100 package specifications updated see Section 6 Package characteristics on page 71 Recommended LQFP100 LQFP64 LQFP48 and VFQFPN36 footprints added see Figure 42 Figure 44 Figure 46 and Figure 40 Section 6 2 Thermal characteristics on page 77 modified Appendix A Important notes removed 21 Mar 2008 22 May 2008 Small text changes In Table 28 Flash memory endurance and data retention Nenp tested over the whol
45. 800 0x4001 3400 0x4001 3000 0x4001 2CO0 0x4001 2800 0x4001 2400 0x4001 1CO0 0x4001 1800 0x4001 1400 0x4001 1000 0x4001 OCOO0 0x4001 0800 0x4001 0400 0x4001 0000 0x4000 7400 0x4000 7000 0x4000 6CO0 0x4000 6800 0x4000 6400 0x4000 6000 Ox4000 5CO0 0x4000 5800 0x4000 5400 0x4000 4CO0 0x4000 4800 0x4000 4400 0x4000 3CO0 0x4000 3800 0x4000 3400 0x4000 3000 0x4000 2CO0 0x4000 2800 0x4000 0COO0 0x4000 0800 0x4000 0400 x4000 0000 reserved reserved reserved 4K CRC 1K reserved 3K Flash interface iK reserved 3K RCC 1K reserved 3K DMA 1K reserved 1K USART1 1K reserved 1K SPI 1K reserved 1K reserved 1K ADC1 1K reserved 2K Port E 1K Port D 1K Port C 1K Port B 1K Port A 1K EXTI 1K AFIO 1K reserved 35K PWR 1K BKP 1K reserved 1K reserved 1K reserved 1K reserved 1K 12C2 1K 12C1 1K reserved 2K USAR3 ik USART2 iK reserved 2K SPA lak reserved 1K IWDG 1K WWDG 1K RTC 1K reserved 7K TIM4 1K TIM3 1K TIM2 1K ai14379d Doc ID 13586 Rev 14 STM32F101x8 STM32F101xB Electrical characteristics 5 5 1 Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referenced to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests
46. D 13586 Rev 14 13 87 Description STM32F101x8 STM32F101xB 2 2 Full compatibility throughout the family The STM32F101xx is a complete family whose members are fully pin to pin software and feature compatible In the reference manual the STM32F101x4 and STM32F101x6 are referred to as low density devices the STM32F101x8 and STM32F101xB are referred to as medium density devices and the STM32F101xC STM32F101xD and STM32F101xE are referred to as high density devices Low and high density devices are an extension of the STM32F101x8 B devices they are specified in the STM32F101x4 6 and STM32F101xC D E datasheets respectively Low density devices feature lower Flash memory and RAM capacities and a timer less High density devices have higher Flash memory and RAM capacities and additional peripherals like FSMC and DAC while remaining fully compatible with the other members of the STM32F101xx family The STM32F101x4 STM32F101x6 STM32F101xC STM32F101xD and STM32F101xE are a drop in replacement for the STM32F101x8 B medium density devices allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle Moreover the STM32F101xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices Table 3 STM32F101xx family Memory size Low density devices Medium density devices H
47. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 ky STM32F101xx medium density access line block diagram llle 12 Glock EG PMDC m 13 STM32F101xx medium density access line LQFP100 pinout 0 21 STM32F101xx medium density access line LQFP64 pinout ooo 22 STM32F101xx medium density access line LQFP48 pinout oou 22 STM32F101xx medium density access line VFQPFN48 pinout eo 23 STM32F101xx medium density access line VFQPFN36 pinout eo 23 Memory MAN RR 28 Pin loading COnditiONS II Gel tk ee a ken eR I kon n na 30 Pin input voltages 2h as cele Bh eee ids n a tf pa ao n Ree d kk fe Aa ok 30 Power supply scheme aiioe LIL L ll L L ll n L L n n kk La kk ka kk ka n n kaa rr 30 Current consumption measurement scheme rl re enn nee n nannan nannan 31 Typical current consumption in Run mode versus frequency at 3 6 V code with data processing running from RA
48. Flash 128 KB JTDO Go 64 bit evoD as AF E PE x SRAM aK evop e L KO PaiKkie x PLL 8 XTAL OSC GP DMA lt PCLK24 Crock 4 4 16 MHz cin HCLK lt 4 7 channels FOLK MANAGT z RC8MHz g IWDG GVDDA LBC 42 kHz fr 2 8 VDDA Standby SUPPLY LL interface Fd Vit NAST SUPERVISION E VBAT E lt VDDA POR PDR Rst OSC32 IN VESA de PTA 32 kHz T oscao OUT Backup AHB2 AHB2 RTC TAMPER RTC APB2 APB1 awu 99 Backup interface 80AF m gt ZAS WAKEUP aS TIM2 lt gt 4 Channels PA 15 0 4 GPIOA KC aS TIM3 lt gt 4 Channels PBs lt cGPloB KR N aS TIM4 4Channels PQ50 47 aroc KR E Kap g c user KI RX TX CTS RTS CK SmartCard as AF PD 15 0 IZA aroo KA R 3 N V usn K gt PXTX CTS ATS PHISOIX emoe KAD J CK SmariCard as AF e x n L y E KO SPI Kep MOSIMISO SCK NSS Ww lt MOSI MISO SEn lt gt 38 KO 1201 KID SCL SDA SMBAL SCK NSS as AF z a an RX TX CTS RTS KC m Er So SpA Smart Card as AF USART1 CD VDDA 16AF VREF Ly 12bit ADO FIM lt gt wwoe VREF Temp sensor ai14385B 1 AF alternate function on I O port pin 2 TA 40 C to 85 C junction temperature up to 105 C 4 12 87 Doc ID 13586 Rev 14 STM32F101x8 STM32F101xB
49. Hz oscillator characteristics llle 46 LSE oscillator characteristics fj sg 32 768 KHz 0 0 0 eee ee 47 HSI oscillator characteristics llle 48 LSI oscillator characteristics eee te an a n a eens 49 Low power mode wakeup timings re ver n tee n n ven kn nen n nna nn nan 49 PLL characteristics tele e n n n au kk aa aa a n a w w wa kaa a a n n kk man 49 Flash memory characteriStiCS eee rt eee n n wen aw aaa n kaa nn nwa 50 Flash memory endurance and data retentiOM e eeeeo e ooo o 50 EMS characteristics et rete eu au ka a w kn a n kaa a n kon a a n kon a non nna 51 EMI characteristics s eese an vee ba ne XR e AA RON eee saad ee eee 52 ESD absolute maximum ratings tel ee ken ken ken ken ren 52 Electrical sensitivities Lel n n eee 52 I O current injection susceptibility ele er ken IR 53 WO static characteristics etre eee n ko n a n ka a non non a 54 Output voltage characteristics eee e ea nen kaa aaa nan nannan 57 I O AC characteristi6S tics scies a anan aki kk ek v l OS Osh beads vee se eG X ead bes 58 NRST pin characteristics eee ee len ken rn 59 TIMx characteristics ren ee n nannan 60 IC characteristics NEN TERT TERQUE A eaaa 61 SCL frequency fpc 42 36 MHz Vpp 3 3 V 6
50. M peripherals enabled 37 Typical current consumption in Run mode versus frequency at 3 6 V code with data processing running from RAM peripherals disabled 37 Typical current consumption on Vgar with RTC on versus temperature at different VBAT MAIUES sui dite Bwa kinan de ki bad m enan kte dok ba da aah ann a AA PETE ale DON ef a WA An on 39 Typical current consumption in Stop mode with regulator in Run mode versus temperature at Vpp 2 3 3 V and 3 6 V I LIL e eee n e enn n ven nn kenn ennan 39 Typical current consumption in Stop mode with regulator in Low power mode versus temperature at Vpp 2 3 3 V and 3 6 V e Le eee ve en n era nn kenn ennan 40 Typical current consumption in Standby mode versus temperature at Vpp 3 3 V and SOM k a e tie a tu A a da hee teams eae ates 40 High speed external clock source AC timing diagram eeeeooeo 45 Low speed external clock source AC timing diagram liiis 45 Typical application with an 8 MHz CryStal esse ee eee onon err 46 Typical application with a 32 768 kHz CryStal eee ooo oo eee ooon 48 Standard I O input characteristics CMOS pOrt ere erer eee er en noon noon 55 Standard I O input characteristics TTL pOrt eee even ee noon onon nan 55 5 V tolerant I O input characteristics CMOS port eer terre nee eee e eee 56 5 V tolerant I O input characte
51. MHz 5 3 2 3 16 MHz 3 8 1 8 8 MHz 2 1 1 2 External clock 4 MHz 1 6 1 1 2 MHZ 1 3 1 1 MHz 1 11 0 98 500 kHz 1 04 0 96 Supply 125kHz 0 98 0 95 Ipp current in mA Sleep mode 36 MHz 7 2 5 24 MHz 4 8 1 8 16 MH 2 12 Running on High 6 3 Speed Internal RC 8 MHz 1 6 0 6 HSI AHB 4 MHz 1 0 5 prescaler used to reduce the 2 MHz 0 72 0 47 f am 1 MHz 0 56 0 44 500 kHz 0 49 0 42 125 kHz 0 43 0 41 1 Typical values are measures at T4 25 C Vpp 3 3 V 2 Add an additional power consumption of 0 8 mA per ADC for the analog part In applications this consumption occurs only while the ADC is on ADON bit is set in the ADC CR2 register 3 External clock is 8 MHz and PLL is on when fuc gt 8 MHz 42 87 Doc ID 13586 Rev 14 q STM32F101x8 STM32F101xB Electrical characteristics On chip peripheral current consumption The current consumption of the on chip peripherals is given in Table 18 The MCU is placed under the following conditions e all I O pins are in input mode with a static value at Vpp or Vss no load e all peripherals are disabled unless otherwise mentioned e the given value is calculated by measuring the current consumption with all peripherals clocked off with only one peripheral clocked on e ambient operating temperature and Vpp supply voltage conditions summarized in Table 5 Table 18 Peripheral current consumption Peripheral Typical consumption
52. MHz and PLL is on when fuc gt 8 MHz 4 36 87 Doc ID 13586 Rev 14 STM32F101x8 STM32F101xB Electrical characteristics Figure 13 Typical current consumption in Run mode versus frequency at 3 6 V code with data processing running from RAM peripherals enabled 25 20 t 15 6 36MHz a t 16MHz 5 8MHz S 10 Ya a o l 5 0 40 0 25 70 85 Temperature C Figure 14 Typical current consumption in Run mode versus frequency at 3 6 V code with data processing running from RAM peripherals disabled Consumption mA 16 14 12 10 40 0 25 70 85 Temperature C Doc ID 13586 Rev 14 37 87 Electrical characteristics STM32F101x8 STM32F101xB Table 14 Maximum current consumption in Sleep mode code running from Flash or RAM Max Symbol Parameter Conditions fucik Unit TA 85 C 36 MHz 15 5 External clock all 24 MHz 11 5 peripherals enabled 4g MHz 8 5 l Supply currentin 8 MHz 5 5 DD Sleep mode 36 MHz 5 External clock all 24 MHz 4 5 peripherals disabled 16 MHz 4 8 MHz 3 1 Based on characterization tested in production at Vpp max and fyc xk max with peripherals enabled 2 External clock is 8 MHz and PLL is on when fyc gt 8 MHz Table 15 Typical and maximum current consumptions in Stop and Standby modes Typ
53. Medium density STM32F101xx pin definitiONS see eee noon oo noon 24 Voltage characteristics tel n elle kk en a w kaa nw kaa kk ka n kk kn na 31 Current characteristics s etre e wen aou au a a www a a kon n a n kon n now kn a nn 32 Thermal characteristics eee lt e eee en n n a a n n kana a n nn nn nan 32 General operating conditions el eee ken ken ken kaa kaa kaa ae 32 Operating conditions at power up power down 0 00 ccc eee eee 33 Embedded reset and power control block characteristics 34 Embedded internal reference voltage llle 35 Maximum current consumption in Run mode code with data processing running from Flash oooccccccc m rr 36 Maximum current consumption in Run mode code with data processing running from RAM 36 Maximum current consumption in Sleep mode code running from Flash ORAM MeL 38 Typical and maximum current consumptions in Stop and Standby modes 38 Typical current consumption in Run mode code with data processing running from Flash oooccccocco eh rr 41 Typical current consumption in Sleep mode code running from Flash or RAM 42 Peripheral current consumption l l Lel L l Len kk La n kk ea nn 43 High speed external user clock characteristics e eeeseeeooeon 44 Low speed external user clock characteristics llle 44 HSE 4 16 M
54. SI RC oscillator The clock source used to wake up the device depends from the current operating mode e Stopor Standby mode the clock source is the RC oscillator e Sleep mode the clock source is the clock that was set before entering Sleep mode All timings are derived from tests performed under the ambient temperature and Vpp supply voltage conditions summarized in Table 8 Table 25 Low power mode wakeup timings Symbol Parameter Typ Unit twusigep Wakeup from Sleep mode 1 8 us Wakeup from Stop mode regulator in run mode 3 6 twusrop ps Wakeup from Stop mode regulator in low power mode 5 4 twusrpev Wakeup from Standby mode 50 us 1 The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction PLL characteristics The parameters given in Table 26 are derived from tests performed under the ambient temperature and Vpp supply voltage conditions summarized in Table 8 Table 26 PLL characteristics Value Symbol Parameter Unit Min Typ Max PLL input clock 1 8 0 25 MHz pLL IN PLL input clock duty cycle 40 60 Yo fPLL OUT PLL multiplier output clock 16 36 MHZ Doc ID 13586 Rev 14 49 87 Electrical characteristics STM32F101x8 STM32F101xB Table 26 PLL characteristics Value Symbol Parameter Unit Min Typ Max tLock PLL lock time 200 us Jitter
55. Table 4 Medium density STM32F101xx pin definitions continued Pins m Alternate functions 2 olg 3 Main 2 85 9z Pin name 3 function A T n 2 O after reset Default Remap SggSg sig gt ois 49 28 Vpp 4 S Vpp 4 SPI1 NSS ADC IN4 14 20 29 11 PA4 I O PA4 USART2 CK 15 21 30 12 PA5 1 0 PA5 SPI1_SCK S ADC_IN5 SPI1 MISO ADC ING 16 22 81 13 PA6 I O PA6 TIM3_CH1 SPI1 MOSI YADC IN7 17 23 32 14 PA7 YO PA7 TIM3 CH20 24 33 PC4 I O PC4 ADC_IN14 25 34 PC5 1 0 PC5 ADC_IN15 18 26 35 15 PBO O PBO ADC IN8 TIM3 CH3 9 19 27 36 16 PB1 VO PB1 ADC IN9 TIM3 CH4 20 28 37 17 PB2 lO FT PB2 BOOT1 38 PE7 VO FT PE7 39 PE8 VO FT PES 40 PE9 VO FT PE9 a 41 PE10 VO FT PE10 42 PE11 VO FT PE11 43 PE12 VO FT PE12 44 PE13 VO FT PE13 45 PE14 O FT PE14 E 46 PE15 VO FT PE15 I2C2 SCL 21 29 47 PB10 VO FT PB10 USART3 Tx TIM2 CH3 I2C2 SDA 22 30148 PB11 VO FT PB11 USART3 Rx 9 TIM2 CH4 23 31 49 18 Vss 1 S Vss 1 24 32 50 19 Vpp 1 S Vpp 1 SPI2 NSS I2C2 SMBA 25 83 51 PB12 VO FT PB12 USART3 CK SPI2 SCK 26 34 52 PB13 VO FT PB13 USART3 CTS SPI2 MISO 27 85 53 PB14 lO FT PB14 USART3 _RTS 28 36 54 PB15 VO FT PB15 SPI2 MOSI ky
56. aces Reference Part number m DMA STM32F101C8 T channel DMA controller STM32F101xg STM32F101R8 m STM32F101V8 Peripherals supported timers ADC SPls STM32F101T8 12Cs and USARTs 1 x 12 bit 1 us A D converter up to 16 me E Ix 12 0 STM32F101VB channels STM32F101xB STM32F101CB Conversion range 0 to 3 6 V STM32F101TB Temperature sensor m Up to 80 fast I O ports 26 37 51 80 I Os all mappable on 16 external interrupt vectors and almost all 5 V tolerant April 2011 Doc ID 13586 Rev 14 1 87 www st com Contents STM32F101x8 STM32F101xB Contents 1 Introd OP uua aos Rana ee E UO ak ek n a an 9 2 D scripti h Me PST 10 2 1 Device overview a evi ae CLER T Race ee ee E Eo SO HR 11 2 2 Full compatibility throughout the family llle 14 2 3 Overview Ac TP 15 2 3 1 ARM Cortex M3 core with embedded Flash and SRAM 15 2 3 2 Embedded Flash memory Is LIL Lenn kenn eee near noon 15 2 3 3 CRC cyclic redundancy check calculation unit 15 2 3 4 Embedded SRAM 0 0c cece kan ken kaa aaa kaa kann 15 2 3 5 Nested vectored interrupt controller NVIC oeooun 15 2 3 6 External interrupt event controller EXTI eeeeeonen 16 2 9 7 Clocks and startup eee ten nen ees 16 2 3 8 BOOUMOdCS oor us cate a RR Eua RR Ee RR RUE EUR EUR dog 16 2 3 9 Power supply schemes o ooccccccc ees 16 2 3 10 Po
57. aracterization q 50 87 Doc ID 13586 Rev 14 STM32F101x8 STM32F101xB Electrical characteristics Functional EMS Electromagnetic susceptibility While a simple application is executed on the device toggling 2 LEDs through I O ports the device is stressed by two electromagnetic events until a failure occurs The failure is indicated by the LEDs e Electrostatic discharge ESD positive and negative is applied to all device pins until a functional disturbance occurs This test is compliant with the IEC 61000 4 2 standard e FTB A Burst of Fast Transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test is compliant with the IEC 61000 4 4 standard A device reset allows normal operations to be resumed The test results are given in Table 29 They are based on the EMS levels and classes defined in application note AN1709 Table 29 EMS characteristics Symbol Parameter Conditions Level Class Vpp 3 3 V TA 25 C fucLk 36 MHz 2B conforms to IEC 61000 4 2 V Voltage limits to be applied on any I O pin to FESD induce a functional disturbance Fast transient voltage burst limits to be Vpp 3 8 V Ta 25 C Verte applied through 100 pF on Vpp and Vss pins fuc_K 36 MHz 4A to induce a functional disturbance conforms to IEC 61000 4 4 Designing hardened software to avoid noise problems EMC character
58. at 25 c Unit TIM2 0 6 TIM3 0 6 TIM4 0 6 SPI2 0 08 APB1 USART2 0 21 USARTS3 0 21 I2C1 0 18 I2C2 0 18 mA GPIO A 0 21 GPIO B 0 21 GPIO C 0 21 GPIO D 0 21 APB2 GPIO E 0 21 ADC10 1 4 SPI1 0 24 USART1 0 35 1 fucik 36 MHz fapg1 fuci k 2 fapgo fici default prescaler value for each peripheral 2 Specific conditions for ADC facLk 28 MHz TAPB1 fucik 2 fAPB2 fHCLK TADCCLK fapo 2 ADON bit in the ADC_CR2 register is set to 1 5 3 6 External clock source characteristics High speed external user clock generated from an external source The characteristics given in Table 19 result from tests performed using an high speed external clock source and under the ambient temperature and supply voltage conditions summarized in Table 8 Doc ID 13586 Rev 14 43 87 Electrical characteristics STM32F101x8 STM32F101xB Table 19 High speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit User external clock source fusE ext frequency 1 8 25 MHz VuseH OSC IN input pin high level voltage 0 7Vpp Vpp y VuseL OSC IN input pin low level voltage Vss 0 3Vpp IwHSE OSC IN high or low time 5 lw HSE ns t HSE OSC IN rise or fall time 20 tise Ciniuse OSC IN input capacitance 5 pF DuCy use Duty cycle 45 55 96 IL OSC_IN Input leakage current Vss lt Vins Vpp 1 pA 1 Guaranteed by design
59. ax value added to Table 23 HSI oscillator characteristics Rpy and Rpp min and max values added to Table 34 I O static characteristics Rpy min and max values added to Table 37 NRST pin characteristics two notes removed Datasheet title corrected USB characteristics section removed Features on page 1 list optimized Small text changes 4 Doc ID 13586 Rev 14 STM32F101x8 STM32F101xB Revision history Table 54 Document revision history continued Date 18 Oct 2007 Revision Changes Vesp com Value added to Table 31 ESD absolute maximum ratings Note added below Table 10 Embedded reset and power control block characteristics and below Table 21 HSE 4 16 MHz oscillator characteristics Note added below Table 35 Output voltage characteristics and Voy parameter description modified Table 42 ADC characteristics and Table 44 ADC accuracy limited test conditions modified Figure 33 ADC accuracy characteristics modified Packages are ECOPACK compliant Tables modified in Section 5 3 5 Supply current characteristics ADC and ANTI TAMPER signal names modified see Table 4 Medium density STM32F101xx pin definitions Table 4 Medium density STM32F101xx pin definitions modified Note 4 removed and values updated in Table 21 Typical current consumption in Standby mode Vhys modified in Table 34 I O static characteristics Updated Table 29 EMS characteristics and Table 30 EMI charac
60. below Table 39 I2C characteristics Updated Figure 29 I2C bus AC waveforms and measurement circuit 1 Updated Figure 28 Recommended NRST pin protection Updated Section 5 3 12 I O current injection characteristics 20 May 2010 18 Updated footnotes below Table 5 Voltage characteristics on page 31 and Table 6 Current characteristics on page 32 Updated tw min in Table 19 High speed external user clock characteristics on page 44 TRADE 14 Updated startup time in Table 22 LSE oscillator characteristics fLSE 32 768 kHz on page 47 Added Section 5 3 12 I O current injection characteristics Updated Section 5 3 13 I O port characteristics 86 87 Doc ID 13586 Rev 14 ky STM32F101x8 STM32F101xB Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property
61. captures output compares PWMS on the largest packages The general purpose timers can work together via the Timer Link feature for synchronization or event chaining Their counter can be frozen in debug mode Any of the general purpose timers can be used to generate PWM outputs They all have independent DMA request generation These timers are capable of handling quadrature incremental encoder signals and the digital outputs from 1 to 3 hall effect sensors C bus Up to two I C bus interfaces can operate in multimaster and slave modes They can support standard and fast modes They support dual slave addressing 7 bit only and both 7 10 bit addressing in master mode A hardware CRC generation verification is embedded They can be served by DMA and they support SM Bus 2 0 PM Bus Universal synchronous asynchronous receiver transmitter USART The available USART interfaces communicate at up to 2 25 Mbit s They provide hardware management of the CTS and RTS signals support IrDA SIR ENDEC are ISO 7816 compliant and have LIN Master Slave capability The USART interfaces can be served by the DMA controller Serial peripheral interface SPI Up to two SPIs are able to communicate up to 18 Mbit s in slave and master modes in full duplex and simplex communication modes The 3 bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits The hardware CRC generation verification supports basic SD Ca
62. ceptibility Functional susceptibility Symbol Description Negative Positive Unit injection injection Injected current on OSC_IN32 0 40 OSC_OUT32 PA4 PA5 PC13 lina Injected current on all FT pins 5 0 mA Injected current on any other pin 5 5 Doc ID 13586 Rev 14 53 87 Electrical characteristics STM32F101x8 STM32F101xB 5 3 13 WO port characteristics General input output characteristics Unless otherwise specified the parameters given in Table 34 are derived from tests performed under the conditions summarized in Table 8 All Os are CMOS and TTL compliant Table 34 IO static characteristics Symbol Parameter Conditions Min Typ Max Unit Standard IO input low 03 0 28 Vpp 2 V 0 8 V V level voltage IL 0 i Ir anpublow Tel 0 3 0 32 Vpp 2V40 75 V V voltage Standard IO input high E A level voltage 0 41 Vop 2 V 1 3V Vppt0 3 V Vin 1 Vpp 2V 5 5 IO FT input high level 0 42 Vpp 2 V 1 V V voltage Vpp 2M 5 2 Standard IO Schmitt trigger Mud 200 mV ie 2 Vhys hysteresis IO FT Schmitt trigger 3 voltage hysteresis 5 VDD mv Vss lt Vin lt Vpop T Standard I Os B lika Input leakage current a LA VIN 5V 3 VO FT Weak pull up equivalent Weak pull down B Rpp equivalent resistor Vin Vop 30 lid ie ka Cio l O pin capacitance 5 pF 1 FT Five volt tolerant In order to sustain a voltage higher than Vpp
63. core operating at a 36 MHz frequency high speed embedded memories Flash memory up to 128 Kbytes and SRAM up to 16 Kbytes and an extensive range of enhanced peripherals and I Os connected to two APB buses All devices offer standard communication interfaces two 12Cs two SPIs and up to three USARTS one 12 bit ADC and three general purpose 16 bit timers The STM32F101xx medium density access line family operates in the 40 to 85 C temperature range from a 2 0 to 3 6 V power supply A comprehensive set of power saving mode allows the design of low power applications The STM32F101xx medium density access line family includes devices in four different packages ranging from 36 pins to 100 pins Depending on the device chosen different sets of peripherals are included the description below gives an overview of the complete range of peripherals proposed in this family These features make the STM32F101xx medium density access line microcontroller family suitable for a wide range of applications such as application control and user interface medical and handheld equipment PC peripherals gaming and GPS platforms industrial applications PLCs inverters printers scanners alarm systems Video intercoms and HVACS 10 87 Doc ID 13586 Rev 14 ky STM32F101x8 STM32F101xB Description 2 1 Device overview Figure 1 shows the general block diagram of the device family
64. e 1 su Si Slave mode 1 Data input hold time SPI1 1 tnu Mi Master mode SPI2 5 hs 1 Data input hold time 3 SI Slave mode ns Slave mode fpc 36 MHz 1 2 i presc 4 a ta so Data output access time Slave mode fPcLK 24 MHZ 0 4 tPcLK tasso 9 Data output disable time Slave mode 10 tso Data output valid time Slave mode after enable edge 25 two Data output valid time i apa moge AN enable 3 thso Slave mode after enable edge 25 1 Data output hold time Master mode after enable t 4 h MO edge the data the data in Hi Z Based on characterization not tested in production Doc ID 13586 Rev 14 Min time is for the minimum time to drive the output and the max time is for the maximum time to validate Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put 63 87 Electrical characteristics STM32F101x8 STM32F101xB Figure 30 SPI timing diagram slave mode and CPHA 0 NSS input A ki ta sox K th NSS CPHA 0 CPOL 0 CPHA 0 CPOL 1 SCK Input th SO le SCK tdis sO J SCK ta SO 4 MISO OUT PUT tsu Sl is Tan GNNCING QNNM INPUT Sa th SI ai14134c Figure 31 SPI timing diagram slave mode and CPHA 10 NSS input A tSU NSS lt gt SCK Input oO 33 K 7 s Z i t gt t t SCKy s t ta SO
65. e lowest power consumption while retaining the content of SRAM and registers All clocks in the 1 8 V domain are stopped the PLL the HSI RC and the HSE crystal oscillators are disabled The voltage regulator can also be put either in normal or in low power mode The device can be woken up from Stop mode by any of the EXTI line The EXTI line source can be one of the 16 external lines the PVD output or the RTC alarm e Standby mode The Standby mode is used to achieve the lowest power consumption The internal voltage regulator is switched off so that the entire 1 8 V domain is powered off The PLL the HSI RC and the HSE crystal oscillators are also switched off After entering Standby mode SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry The device exits Standby mode when an external reset NRST pin a IWDG reset a rising edge on the WKUP pin or an RTC alarm occurs The RTC the IWDG and the corresponding clock sources are not stopped by entering Stop or Standby mode DMA The flexible 7 channel general purpose DMA is able to manage memory to memory peripheral to memory and memory to peripheral transfers The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer Doc ID 13586 Rev 14 17 87 Description STM32F101x8 STM32F101xB Each channel is connected to dedicated hardware DMA requests w
66. e temperature range cycling conditions specified for tRET tggr min modified at Ty 55 C Figure 2 Clock tree corrected Figure 8 Memory map clarified Vos Avg Slope and T modified in Table 46 TS characteristics CRC feature removed Section 1 Introduction modified Section 2 2 Full compatibility throughout the family added CRC feature added Ipp vBAr removed from Table 21 Typical current consumption in Standby mode on page 42 Values added to Table 40 SCL frequency fPCLK1 36 MHz VDD 3 3 V on page 62 Figure 30 SPI timing diagram slave mode and CPHA 0 on page 64 modified Equation 1 corrected Section 6 2 2 Evaluating the maximum junction temperature for an application on page 78 added Axx option added to Table 53 Ordering information scheme on page 79 Doc ID 13586 Rev 14 83 87 Revision history STM32F101x8 STM32F101xB 84 87 Table 54 Document revision history continued Date 21 Jul 2008 24 Jul 2008 Revision Changes Small text changes Power supply supervisor on page 16 modified and Vppa added to Table 8 General operating conditions on page 32 Capacitance modified in Figure 11 Power supply scheme on page 30 Table notes revised in Section 5 Electrical characteristics Maximum value of tasrrempo modified in Table 10 Embedded reset and power control block characteristics on page 34 Values added to Table 15 Typical and maximum current consumptions
67. et error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions Typ Max Unit fPcLko 28 MHz fanc 14 MHz Ray lt 10k 18 25 VDDA 2 4Vto3 6 V Measurements made after ADC calibration 1 5 3 LSB 1 2 1 5 3 1 ADC DC accuracy values are measured after internal calibration Better performance could be achieved in restricted Vpp frequency Vpgr and temperature ranges 3 ADC Accuracy vs Negative Injection Current Injecting negative current on any of the standard non robust analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for Iiv pin and 2lin pin in Section 5 3 12 does not affect the ADC accuracy 4 Based on characterization not tested in production Figure 33 ADC accuracy characteristics 1 Example of an actual transfer curve 2 The ideal transfer curve 3 End point correlation line Ey Total Unadjusted Error maximum deviation between the actual and the ideal transfer curves Eo Offset Error deviation between the first actual transition and the first ideal one Eg Gain Error de
68. etector PVD that monitors the Vpp VppA power supply and compares it to the Vpyp threshold An interrupt can be generated when Vpp VppA drops below the Vpyp threshold and or when Vpp VppA is higher Doc ID 13586 Rev 14 ky STM32F101x8 STM32F101xB Description 2 3 11 2 3 12 Note 2 3 13 than the Vpyp threshold The interrupt service routine can then generate a warning message and or put the MCU into a safe state The PVD is enabled by software Refer to Table 10 Embedded reset and power control block characteristics for the values of Vror PDR and Vpyp Voltage regulator The regulator has three operation modes main MR low power LPR and power down e MRis used in the nominal regulation mode Run e LPR is used in the Stop mode e Power down is used in Standby mode the regulator output is in high impedance the kernel circuitry is powered down inducing zero consumption but the contents of the registers and SRAM are lost This regulator is always enabled after reset It is disabled in Standby mode providing high impedance output Low power modes The STM32F101xx medium density access line supports three low power modes to achieve the best compromise between low power consumption short startup time and available wakeup sources e Sleep mode In Sleep mode only the CPU is stopped All peripherals continue to operate and can wake up the CPU when an interrupt event occurs e Stop mode Stop mode achieves th
69. he high speed APB APB2 and the low speed APB APB1 domains The maximum frequency of the AHB and the APB domains is 36 MHz See Figure 2 for details on the clock tree Boot modes At startup boot pins are used to select one of three boot options e Boot from User Flash e Boot from System Memory e Boot from embedded SRAM The boot loader is located in System Memory It is used to reprogram the Flash memory by using USART1 For further details please refer to AN2606 Power supply schemes Vpp 2 0 to 3 6 V External power supply for I Os and the internal regulator Provided externally through Vpp pins Vsgsa Vppa 2 0 to 3 6 V External analog power supplies for ADC Reset blocks RCs and PLL minimum voltage to be applied to Vppa is 2 4 V when the ADC is used VppA and VssA must be connected to Vpp and Vss respectively Vpar 1 8 to 3 6 V Power supply for RTC external clock 32 kHz oscillator and backup registers through power switch when Vpp is not present For more details on how to connect power pins refer to Figure 11 Power supply scheme Power supply supervisor The device has an integrated power on reset POR power down reset PDR circuitry It is always active and ensures proper operation starting from down to 2 V The device remains in reset mode when Vpp is below a specified threshold Vpor ppr without the need for an external reset circuit The device features an embedded programmable voltage d
70. igh density devices Pinout 16 KB 32 KB 64 KB 128 KB 256 KB 384 KB 512 KB Flash Flash Flash Flash Flash Flash Flash 32 KB 48 KB 48 KB 4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM RAM RAM RAM 144 5 x USARTs 100 4 x 16 bit timers 2 x basic timers 3 x USARTs 8 x SPls 2 x Cs 1 x ADC 64 2 x USARTs 3 x 16 bit timers 2 x DACs FSMC 100 and 144 pins A8 2 x 16 bit timers 2 x SPls 2 x I2Cs 1 x SPI alae 1x ADC 36 1xADC 1 For orderable part numbers that do not show the A internal code after the temperature range code 6 the reference datasheet for electrical characteristics is that of the STM32F101x8 B medium density devices 14 87 Doc ID 13586 Rev 14 STM32F101x8 STM32F101xB Description 2 3 2 3 1 2 3 2 2 3 3 2 3 4 2 3 5 Overview ARM Cortex M3 core with embedded Flash and SRAM The ARM Cortex MB8 processor is the latest generation of ARM processors for embedded systems It has been developed to provide a low cost platform that meets the needs of MCU implementation with a reduced pin count and low power consumption while delivering outstanding computational performance and an advanced system response to interrupts The ARM Cortex M3 32 bit RISC processor features exceptional code efficiency delivering the high performance expected from an ARM core in the memory size usually associated with 8 and 16 bit devices The STM32F101xx medium density access line family
71. in Stop and Standby modes and Table 21 Typical current consumption in Standby mode removed fase exi modified in Table 19 High speed external user clock characteristics on page 44 fp jy modified in Table 26 PLL characteristics on page 49 fhcix corrected in Table 29 EMS characteristics Minimum SDA and SCL fall time value for Fast mode removed from Table 39 I2C characteristics on page 61 note 1 modified things Modified in Table 41 SPI characteristics on page 63 and Figure 30 SPI timing diagram slave mode and CPHA 0 on page 64 Capc modified in Table 42 ADC characteristics on page 66 and Figure 34 Typical connection diagram using the ADC modified fpc ko corrected in Table 44 ADC accuracy limited test conditions and Table 45 ADC accuracy Typical Ts temp value removed from Table 46 TS characteristics on page 70 LQFP48 package specifications updated see Table 51 Table 45 and Table 46 Axx option removed from Table 53 Ordering information scheme on page 79 First page modified Up to 2 x IPC interfaces instead of 1 x 12C interface 23 Sep 2008 10 STM32F101xx devices with 32 Kbyte Flash memory capacity removed document updated accordingly Section 2 2 Full compatibility throughout the family on page 14 updated Notes modified in Table 4 Medium density STM32F101xx pin definitions on page 24 Note 2 modified below Table 5 Voltage characteristics on page 31 IAVppxl min and lAV ppx
72. in production on 100 of the devices with an ambient temperature at Ta 25 C and Ta Tamax given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation nean 3X Typical values Unless otherwise specified typical data are based on T4 25 C Vpp 3 3 V for the 2 V lt Vpp 3 6 V voltage range They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean 2X Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 9 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10 Doc ID 13586 Rev 14 29 87 Electrical characteristics 5 1 6 Caution 30 87 Figure 9 Pin loading conditions Figure 10 Pin input voltage STM32F101x8 STM32F101xB STM32F10xxx pin STMS2F10xxx pin C 5
73. ing Table 30 EMI characteristics Monitored Max vs fuse fuci Symbol Parameter Conditions frequency band Unit kdo d 8 36 MHz 0 1 MHz to 30 MHz 7 Vpp 2 3 3 V Ta 25 C LQFP100 package 30 MHz to 130 MHz 8 dBuV Sem Peak level 3 compliant with 130 MHz to 1GHZ 18 IEC 61967 2 SAE EMI Level 3 5 Absolute maximum ratings electrical sensitivity Based on three different tests ESD LU using specific measurement methods the device is stressed in order to determine its performance in terms of electrical sensitivity Electrostatic discharge ESD Electrostatic discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts x n 1 supply pins This test conforms to the JESD22 A114 C101 standard Table 31 ESD absolute maximum ratings Symbol Ratings Conditions Class Mx Unit value V Electrostatic discharge Ta 25 C 2 2000 ESD HBM voltage human body model conforming to JESD22 A114 V Electrostatic discharge Ta 25 C l 500 ESD CDM voltage charge device model conforming to JESD22 C101 1 Based on characterization results not tested in production Static latch up Two complementary static tests are required on six parts to assess the latch up performance e A supply overvoltage is applied
74. ith support for software trigger on each channel Configuration is made by software and transfer sizes between source and destination are independent The DMA can be used with the main peripherals SPI 12C USART general purpose timers TIMx and ADC 2 3 14 RTC real time clock and backup registers The RTC and the backup registers are supplied through a switch that takes power either on Vpp supply when present or through the Vga pin The backup registers are ten 16 bit registers used to store 20 bytes of user application data when Vpp power is not present The real time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function and provides an alarm interrupt and a periodic interrupt It is clocked by a 32 768 kHz external crystal resonator or oscillator the internal low power RC oscillator or the high speed external clock divided by 128 The internal low power RC has a typical frequency of 40 kHz The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation The RTC features a 32 bit programmable counter for long term measurement using the Compare register to generate an alarm A 20 bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32 768 kHz 2 3 15 Independent watchdog The independent watchdog is based on a 12 bit downcounter and 8 bit prescaler
75. ization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application Software recommendations The software flowchart must include the management of runaway conditions such as e Corrupted program counter e Unexpected reset e Critical Data corruption control registers Prequalification trials Most of the common failures unexpected reset and program counter corruption can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Doc ID 13586 Rev 14 51 87 Electrical characteristics STM32F101x8 STM32F101xB 5 3 11 52 87 Electromagnetic Interference EMI The electromagnetic field emitted by the device is monitored while a simple application is executed toggling 2 LEDs through the I O ports This emission test is compliant with IEC61967 2 standard which specifies the test board and the pin load
76. lt so there is no need for remapping For more details refer to the Alternate function I O and debug configuration section in the STM32F10xxx reference manual The use of PDO and PD1 in output mode is limited as they can only be used at 50 MHz in output mode This alternate function can be remapped by software to some other port pins if available on the used package For more details refer to the Alternate function I O and debug configuration section in the STM32F10xxx reference manual available from the STMicroelectronics website www st com kI Doc ID 13586 Rev 14 27187 Memory mapping STM32F101x8 STM32F101xB 4 28 87 Memory mapping The memory map is shown in Figure 8 Figure 8 Memory map OxFFFF FFFF 7 OxE010 0000 0xE000 0000 Cortex M3 internal peripherals 0xC000 0000 5 OxA000 0000 0x8000 0000 0x6000 0000 0x4000 0000 Peripherals 0x2000 0000 SRAM 0x0000 0000 Reserved Ox1FFF FFFF Ox1FFF F80F Ox1FFF F800 Ox1FFF F000 0x0801 FFFF 0x0800 0000 0x0000 0000 reserved Option Bytes System memory reserved Flash memory Aliased to Flash or system memory depending on BOOT pins APB memory space OxFFFF FFF OxEO10 0000 0x6000 0000 x4002 3400 0x4002 3000 0x4002 2400 0x4002 2000 0x4002 1400 0x4002 1000 0x4002 0400 0x4002 0000 0x4001 3C00 0x4001 3
77. min removed Note 2 added to Table 8 General operating conditions on page 32 Measurement conditions specified in Section 5 3 5 Supply current characteristics on page 35 Ipp in standby mode at 85 C modified in Table 15 Typical and maximum current consumptions in Stop and Standby modes on page 38 General input output characteristics on page 54 modified Note added below Table 53 Ordering information scheme Section 7 1 Future family enhancements removed Small text changes 4 Doc ID 13586 Rev 14 STM32F101x8 STM32F101xB Revision history Table 54 Document revision history continued Date 21 Apr 2009 Revision 11 Changes I O information clarified on page 1 Figure 8 Memory map modified In Table 4 Medium density STM32F101xx pin definitions PB4 PB13 PB14 PB15 PB3 TRACESWO moved from Default column to Remap column Note modified in Table 12 Maximum current consumption in Run mode code with data processing running from Flash and Table 14 Maximum current consumption in Sleep mode code running from Flash or RAM Figure 16 Figure 17 and Figure 18 show typical curves Table 19 High speed external user clock characteristics and Table 20 Low speed external user clock characteristics modified ACChs max values modified in Table 23 HSI oscillator characteristics Small text changes 22 Sep 2009 12 Note 5 updated and Note 4 added in Table 4 Medium density
78. n characterization data not tested in production Doc ID 13586 Rev 14 57 87 Electrical characteristics STM32F101x8 STM32F101xB Input output AC characteristics The definition and values of input output AC characteristics are given in Figure 27 and Table 36 respectively Unless otherwise specified the parameters given in Table 36 are derived from tests performed under the ambient temperature and Vpp supply voltage conditions summarized in Table 8 Table 36 O AC characteristics MODEx 1 0 bit Symbol Parameter Conditions Max Unit value fmax 10 out Maximum frequency C 50 pF Vpp 2 V to 3 6 V 2 MHz Output high to low level fall 3 10 lOout time 1258 C 50 pF Vpp 2 V to 3 6 V ns Output low to high level rise 3 tojout time 125 fmax 10 out Maximum frequency C 2 50 pF Vpp 2 V to 3 6 V 10 MHz Output high to low level fall 3 01 kWojout time 256 C 50 pF Vpp 2 V to 3 6 V ns Output low to high level rise 3 tojout time 25 Ci 30 pF Vpp 2 2 7 V to 3 6 V 50 MHz Fmax 10jout Maximum Frequency C 50 pF Vpp 2 7Vto3 6V 30 MHz C 50 pF Vpp 2 V to 2 7 V 20 MHz C 30 pF Vpp2 2 7 Vto 3 6 V 58 11 t Ojout on high iedowlevelfall e cen E Voss A7 VISA a9 C 50 pF Vpp 2Vto27V 12 ns C 30 pF Vpp2 2 7 Vto3 6 V 58 Output low to high level rise traojout time g C 50 pF Vpp 27 Vto3 6 V 88 C 50 pF Vpp 2Vto2 7V
79. n n kl lk EE eee 29 5 1 4 Loading capacitor ee e venn eee 29 5 1 5 Pin input voltage cse e e a kon ga Ak lak EE f WA RYE EH 29 5 1 6 Power supply scheme II Le eee eee eee eee 30 5 1 7 Current consumption measurement 00 eee eee ee ees 31 5 2 Absolute maximum ratings leise 31 53 Operating conditions iu 3 dac Eau RE ER EET Hen e a RS E uma Els 32 5 8 1 General operating conditions eee iles 32 5 3 2 Operating conditions at power up power down 33 5 3 3 Embedded reset and power control block characteristics 33 5 3 4 Embedded reference voltage llli 35 5 3 5 Supply current characteristics llle 35 5 3 6 External clock source characteristics eoee 43 5 3 7 Internal clock source characteristics o 48 5 3 8 PLL characteristics 49 5 3 9 Memory characteristics llle 50 5 3 10 EMC characteristics teren venn n anan ee 50 5 3 41 A Absolute maximum ratings electrical sensitivity 52 5 3 12 l O current injection characteristics seeoooon 53 5 3 13 l O port characteristics lesen 54 5 3 14 NRST pin characteristics seren enn n anno nan 59 5 3 15 TIM timer characteristics eeeeoe eee 60 5 3 16 Communications interfaces ee ee enan 60 5 3 17 1
80. ne 2 eee n n konn 76 Recommended footprint Pr m 76 LEOQEP6A P 5 Tax VS TA iue tot i asd cda teu E 78 Doc ID 13586 Rev 14 ky STM32F101x8 STM32F101xB Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F101x8 and STM32F101xB medium density access line microcontrollers For more details on the whole STMicroelectronics STM32F101xx family please refer to Section 2 2 Full compatibility throughout the family The medium density STM32F101xx datasheet should be read in conjunction with the low medium and high density STM32F10xxx reference manual For information on programming erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual The reference and Flash programming manuals are both available from the STMicroelectronics website www st com For information on the Cortex MG core please refer to the Cortex M3 Technical Reference Manual available from the www arm com website at the following address http infocenter arm com help index jsp topic com arm doc ddi0337e Cortex Intelligent Processors by ARM a LLI cc Lu e a L ARM Doc ID 13586 Rev 14 9 87 Description STM32F101x8 STM32F101xB 2 Description The STM32F101xB and STM32F101x8 medium density access line family incorporates the high performance ARM Cortex M3 32 bit RISC
81. nfgmerzssi esrc ge rufum n Dea a E OUR gt gt gt gt ai14386b ky Doc ID 13586 Rev 14 21 87 Pinouts and pin description STM32F101x8 STM32F101xB Figure 4 STM32F101xx medium density access line LQFP64 pinout NrOwodct OVLOZI anmanaannnnnnnosn 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VBAT 1 48 O VDD 2 PC13 TAMPER RTC 2 47 O VSS 2 PC14 OSC32 IN 03 46 L1 PA13 PC15 OSC32 OUT 4 45 O PA12 PDO OSC IN 5 44 L1 PA11 PD1 OSC OUT 6 43 O PA10 NRST 7 42 O PA9 PCO ga 41 L1 PA8 PC1 9 LQFP64 40 O PC9 PC2 10 39 L1 PC8 PC3 11 38 O PC7 VSSA 12 37 O PC6 VDDA O 13 36 O PB15 PAO WKUP O 14 35 O PB14 PA1 15 34 O PB13 PA2 16 33 O PB12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ai14387b Figure 5 STM32F101xx medium density access line LQFP48 pinout PA15 PA14 KONM n cn cn con c aannn VBAT 01 VDD 2 PC13 TAMPER RTC 2 VSS 2 PC14 OSC32 IN 03 PA13 PC15 OSC32 OUT da PA12 PDO OSC IN l5 ine 1 PD1 OSC OUT Ce 31 PA10 NRST d7 LQFP48 soi PAS VSSA gs8 PA8 VDDA PB15 PAO WKUP PB14 PA1 PB13 PA2 PB12 VDD 1 OR ai14378d 22187 Doc ID 13586 Rev 14 4 STM32F101x8 STM32F101xB Pinouts and pin description Figure 6 STM32F101xx medium density access line VFQPFN48 pinout VFQFPN48 ai18300 Figure 7 STM32F101xx medium density access line VFQPFN36 pinout Vpp 3 Vpp 2 OSC IN PDO Mss OSC OUT PD1 PA13 NRST PA
82. not tested in production Low speed external user clock generated from an external source The characteristics given in Table 20 result from tests performed using an low speed external clock source and under the ambient temperature and supply voltage conditions summarized in Table 8 Table 20 Low speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit User external clock source fisE ext frequency 32 768 1000 kHz OSC32 IN input pin high level VLSEH voltage fa ene 0 7Vpp Vip V OSC32 IN input pin low level VLSEL voltage dna Vss 0 3Vpp IwLSE OSC32 IN high or low time 450 lw LSE ns LSE OSC32 IN rise or fall time 50 ti sE Cinase OSC32 IN input capacitance 5 pF DuCy se Duty cycle 30 70 Yo IL OSC32_IN Input leakage current Vss Viu Vpp 1 yA 1 Guaranteed by design not tested in production 44 87 Doc ID 13586 Rev 14 4 STM32F101x8 STM32F101xB Electrical characteristics Figure 19 High speed external clock source AC timing diagram External clock source JUUL ai14127b Figure 20 Low speed external clock source AC timing diagram External clock source JUUL ai14140c High speed external clock generated from a crystal ceramic resonator The high speed external HSE clock can be supplied with a 4 to 16 MHz crystal ceramic re
83. oduct or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2011 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 13586 Rev 14 87 87
84. of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark ky Doc ID 13586 Rev 14 71 87 Package characteristics STM32F101x8 STM32F101xB Figure 37 VFQFPN48 7 x 7 mm 0 5 mm pitch package Figure 38 Recommended footprint 1 72 87 Doc ID 13586 Rev 14 outline dimensions in mm Seating o Plane 9 E x q 1 B ph 5 80 25 e 8400000000008 D py Oo r1 37 48 HO Oo U UUUUUUUUU i 1 Oo 36 _ 1 L LO i gt rm O a D 3 O LI op a 3 3 gt gt C O LO Gi 2 q r3 oO i p q 5 a q BOOCOOOOQOOOOB tes D a L C 0 50 i D A 255 Cu 7 80 Dnnnnnnnnnnnn 1 aits799 Ze Bottom View pa D2 VO ME 1 Drawing is not to scale 2 Allleads pads should also be soldered to the PCB to improve the lead solder joint life Table 47 VFQFPN48 7 x 7 mm 0 5 mm pitch package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 0 800 0 900 1 000 0 0315 0 0354 0 0394 Al 0 020 0 050 0 0008 0 0020 A2 0 650 1 000 0 0256 0 0394 A3 0 250 0 0098 b 0 180 0 230 0 300
85. om tests performed under the ambient temperature and Vpp supply voltage conditions summarized in Table 8 Table 16 Typical current consumption in Run mode code with data processing running from Flash Symbol Parameter Conditions fuciK All peripherals All peripherals Unit enabled disabled 36 MHz 19 14 8 24 MHz 12 9 10 1 16 MHz 9 3 7 4 8 MHz 5 5 4 6 External clock 3 4 MHz 3 3 2 8 2 MHz 2 2 1 9 1 MHz 1 6 1 45 500 kHz 1 3 1 25 Supply 125kHz 1 08 1 06 Ipp current in mA Run mode 36 MHz 18 3 14 1 24 MHz 12 2 9 5 Running on 16 MHz 8 5 6 8 high speed internal RC 8MHz 4 9 4 SIA 4 MHz 2 7 2 2 prescaler used to 2MHz 1 6 1 4 reduce the frequency 1 MHz 1 02 0 9 500 kHz 0 73 0 67 125 kHz 0 5 0 48 1 Typical values are measures at T4 25 C Vpp 3 3 V 2 Add an additional power consumption of 0 8 mA per ADC for the analog part In applications this consumption occurs only while the ADC is on ADON bit is set in the ADC CR2 register 3 External clock is 8 MHz and PLL is on when fyc gt 8 MHz Doc ID 13586 Rev 14 41 87 Electrical characteristics STM32F101x8 STM32F101xB Table 17 Typical current consumption in Sleep mode code running from Flash or RAM Typ Typ Symbol Parameter Conditions fuciK All peripherals All peripherals Unit enabled disabled 36 MHz 7 6 3 1 24
86. ons Min Typ Max Unit PLS 2 0 000 rising edge 21 218 226 V PLS 2 0 000 falling edge 2 2 08 2 16 V PLS 2 0 001 rising edge 2 19 2 28 2 37 V PLS 2 0 001 falling edge 2 09 2 18 227 V PLS 2 0 010 rising edge 2 28 2 38 248 V PLS 2 0 010 falling edge 2 18 2 28 238 V PLS 2 0 011 rising edge 2 38 2 48 258 V T slo voltage PLS 2 0 011 falling edge 2 28 2 38 248 V etector level selection pi s 2 0 100 rising edge 2 47 2 58 2 69 V PLS 2 0 100 falling edge 2 37 2 48 2 59 V PLS 2 0 101 rising edge 2 57 2 68 2 79 V PLS 2 0 101 falling edge 2 47 2 58 269 V PLS 2 0 110 rising edge 2 66 2 78 2 9 V PLS 2 0 110 falling edge 2 56 2 68 2 8 V PLS 2 0 111 rising edge 2 76 2 88 3 V PLS 2 0 111 falling edge 2 66 2 78 2 9 V Vevphys PVD hysteresis 100 mV VPOR PDR Power on power down Falling edge 180 1 88 1 96 ka kin kr t Rising edge 184 1 92 2 0 Vepnnys PDR hysteresis 40 mV tastreMpo Reset temporization 1 5 2 5 4 5 ms 1 The product behavior is guaranteed by design down to the minimum Vpop ppg value 2 Guaranteed by design not tested in production Doc ID 13586 Rev 14 SI STM32F101x8 STM32F101xB Electrical characteristics 5 3 4 5 3 5 Embedded reference voltage The parameters given in Table 11 are derived from tests performed under the ambient temperature
87. p mode with regulator in Low power mode versus temperature at VDD 3 3 V and 3 6 V added Note removed below Figure 30 SPI timing diagram slave mode and CPHA 0 Note added below Figure 31 SPI timing diagram slave mode and CPHA 1 1 Figure 34 Typical connection diagram using the ADC modified tsu HSE and ISU LSE conditions modified in Table 21 and Table 22 respectively Maximum values removed from Table 25 Low power mode wakeup timings tret conditions modified in Table 28 Flash memory endurance and data retention Conditions modified in Table 29 EMS characteristics Impedance size specified in A 4 Voltage glitch on ADC input 0 on page 71 Small text changes in Table 35 Output voltage characteristics Section 5 3 11 Absolute maximum ratings electrical sensitivity updated Details on unused pins removed from General input output characteristics on page 54 Table 41 SPI characteristics updated Notes added and lik removed in Table 42 ADC characteristics Note added in Table 43 and Table 46 Note 3 and Note 2 added below Table 44 ADC accuracy limited test conditions Avg Slope and Vo modified in Table 46 TS characteristics O javalue for VFQFPN36 package added in Table 52 Package thermal characteristics I2C interface characteristics on page 60 modified Order codes replaced by Section 7 Ordering information scheme 4 Doc ID 13586 Rev 14 STM32F101x8 STM32F101xB Revision history Y Table
88. racteristics for the maximum allowed input voltage values 4 A positive injection is induced by Viy Vpp while a negative injection is induced by Viy Vss li jpiy must never be exceeded Refer to Table 5 Voltage characteristics for the maximum allowed input voltage values 5 When several inputs are submitted to a current injection the maximum 2l y pin is the absolute sum of the positive and negative injected currents instantaneous values Table 7 Thermal characteristics Symbol Ratings Value Unit TstG Storage temperature range 65 to 150 C Tj Maximum junction temperature 150 C 5 3 Operating conditions 5 3 1 General operating conditions Table 8 General operating conditions Symbol Parameter Conditions Min Max Unit fHcLK Internal AHB clock frequency 0 36 fPcLK1 Internal APB1 clock frequency 0 36 MHZ fPcLko Internal APB2 clock frequency 0 36 Vpp Standard operating voltage 2 3 6 V Analog operating voltage 2 3 6 Van D ADC not used Must be the same potential V 2 d Analog operating voltage as Vpp ha 36 ADC used i VBAT Backup operating voltage 1 8 3 6 V 32 87 Doc ID 13586 Rev 14 ky STM32F101x8 STM32F101xB Electrical characteristics 5 3 2 5 3 3 Y Table 8 General operating conditions continued Symbol Parameter Conditions Min Max Unit LQFP100 434 esipali LQFP64 444 P Ko ame at Ta mW 85 C LQFP48 36
89. rd MMC modes Both SPIs can be served by the DMA controller GPIOs general purpose inputs outputs Each of the GPIO pins can be configured by software as output push pull or open drain as input with or without pull up or pull down or as peripheral alternate function Most of the GPIO pins are shared with digital or analog alternate functions All GPIOs are high current capable except for analog inputs The I Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I Os registers ADC analog to digital converter The 12 bit analog to digital converter has up to 16 external channels and performs conversions in single shot or scan modes In scan mode automatic conversion is performed on a selected group of analog inputs The ADC can be served by the DMA controller Doc ID 13586 Rev 14 19 87 Description STM32F101x8 STM32F101xB 2 3 24 2 3 25 20 87 An analog watchdog feature allows very precise monitoring of the converted voltage of one some or all selected channels An interrupt is generated when the converted voltage is outside the programmed thresholds Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature The conversion range is between 2 V lt Vppa lt 3 6 V The temperature sensor is internally connected to the ADC IN16 input channel which is used to convert the sensor output
90. results obtained with typical external components specified in Table 22 In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal Doc ID 13586 Rev 14 ky STM32F101x8 STM32F101xB Electrical characteristics resonator manufacturer for more details on the resonator characteristics frequency package accuracy Table 22 LSE oscillator characteristics f se 32 768 kHz 2 Symbol Parameter Conditions Min Typ Max Unit Rr Feedback resistor 5 MO Recommended load capacitance C versus equivalent serial Rg 30 KQ 15 pF resistance of the crystal Rg lo LSE driving current E E rad 14 pA Om Oscillator transconductance 5 HAN Ta 50 C 1 5 Ta 25 C 2 5 Ta 10 C 4 tsu sE Startup time ae d s Ta 20 C 17 TA 30 C 32 TA 40 C 60 Based on characterization not tested in production 2 Refer to the note and caution paragraphs below the table and to the application note AN2867 Oscillator design guide for ST microcontrollers 3 tsu _se is the startup time measured from the moment it is enabled by software to a stabilized 32 768 kHz oscillation is reached This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer Note Caution 3
91. ristics TTL port eee elsi 56 WO AC characteristics definition lille 59 Recommended NRST pin protection ler even knn ea ee 59 12C bus AC waveforms and measurement circuit L a terre ee ee 62 SPI timing diagram slave mode and CPHA O e eee even ne enn eese 64 SPI timing diagram slave mode and CPHA dU uou pus padece 64 SPI timing diagram master model ev k thick ke n SON SAN pe ET 65 ADC accuracy characteriStiCS tete twe n w kan a n kn a n n nn a a n a n a 68 Typical connection diagram using the ADC eee eee ee n eee lees 69 Power supply and reference decoupling VREF not connected to Vppa 69 Power supply and reference decoupling VREF connected to Vppa4 lesus 70 VFQFPN48 7 x 7 mm 0 5 mm pitch package outline 8 s Recommended footprint dimensions in mm e Te VFQFPN36 6 x 6 mm 0 5 mm pitch package outline n8 a Recommended footprint dimensions in mm NP ee 73 LQFP100 14 x 14 mm 100 pin low profile quad flat package outline 74 Recommended footprint p ECCE 74 Doc ID 13586 Rev 14 7 87 List of figures STM32F101x8 STM32F101xB Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 8 87 LQFP64 10 x 10 mm 64 pin low profile quad flat package outline 75 Recommended footprint T ue ale ok HE MANDA 75 LQFP48 7 x 7mm 48 pin low profile quad flat package outli
92. round VREF V 2 A See Equation 1 and RAIN External input impedance Table 43 for details 50 kQ Ranco Sampling switch resistance 1 kQ 2 Internal sample and hold Canc capacitor 8 pF f 14 MHz 5 9 us tea Calibration time 83 Tano 4 2 Injection trigger conversion fapc 14 MHz 0 214 us lat latency 3 4 tape 1 Regular trigger conversion fapc 14 MHz 0 143 us latr latency 20 tape 0 107 17 1 us tg Sampling time fApc 14 MHz 1 5 239 5 1 fapc trag Power up time 0 0 1 us fADC 14 MHz 1 18 us t 2 Total conversion time CONV including sampling time 14 to 252 tg for sampling 12 5 for T successive approximation ADC Based on characterization results not tested in production Guaranteed by design not tested in production Vngr can be internally connected to Vppa and Vper can be internally connected to Vgga depending on the package Refer to Section 3 Pinouts and pin description tor turther details 4 For external triggers a delay of 1 fpc o must be added to the latency specified in Table 42 66 87 Doc ID 13586 Rev 14 4 STM32F101x8 STM32F101xB Electrical characteristics Equation 1 RAIN max formula S osx Rc fapc X Canc X In 2 e Rain lt The formula above Equation 1 is used to determine the maximum external impedance allowed for an error below 1 4 of LSB Here N 12 from 12 bit resolution Table 43 Ray max for fapc 14 MHz
93. rs should be ceramic good quality They should be placed them as close as possible to the chip Figure 35 Power supply and reference decoupling Vref not connected to VppA STM32F10xxx 1 uF 10 nF 1 UF 10 nF ai14380b 1 Vgpgr and Vggr inputs are available only on 100 pin packages Doc ID 13586 Rev 14 69 87 Electrical characteristics STM32F101x8 STM32F101xB Figure 36 Power supply and reference decoupling Vpgr connected to VppA STM32F10xxx VrEF VDDA 1 uF 10 nF VnEr VssA ai14381b 1 Vref and Vggr inputs are available only on 100 pin packages 5 3 18 Temperature sensor characteristics Table 46 TS characteristics Symbol Parameter Min Typ Max Unit T Vsense linearity with temperature t1 2 C Avg Slope Average slope 4 0 4 3 4 6 mv C Vos Voltage at 25 C 1 34 143 1 52 V teranT gt Startup time 4 10 us ADC sampling time when reading the 3 2 ping g TS temp temperature Uu an 1 Guaranteed by characterization not tested in production 2 Guaranteed by design not tested in production 3 Shortest sampling time can be determined in the application by multiple iterations 70 87 Doc ID 13586 Rev 14 4 STM32F101x8 STM32F101xB Package characteristics 6 Package characteristics 6 1 Package mechanical data In order to meet environmental requirements ST offers these devices in different grades
94. sonator oscillator All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 21 In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details on the resonator characteristics frequency package accuracy Doc ID 13586 Rev 14 45 87 Electrical characteristics STM32F101x8 STM32F101xB 46 87 Table 21 HSE 4 16 MHz oscillator characteristics 2 Symbol Parameter Conditions Min Typ Max Unit fosc_in Oscillator frequency 4 8 16 MHz Hr Feedback resistor 200 ka Recommended load capacitance C versus equivalent serial Rg 2300 30 pF resistance of the crystal Ra 9 Vpp 3 3 V VIN Vss lo HSE driving current with 30 pF load 1 mA Om Oscillator transconductance Startup 25 mA V tsu usE Startup time Vpp is stabilized 2 ms 1 Resonator characteristics given by the crystal ceramic resonator manufacturer Based on characterization not tested in production The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment due to the induced leakage and the bias condition change However it is recommended to take this point into account if the MCU is used
95. teristics tvpp modified in Table 9 Operating conditions at power up power down Typical values modified note 2 modified and note 3 removed in Table 25 Low power mode wakeup timings Maximum current consumption Table 12 Table 13 and Table 14 updated Values added and notes added in Table 15 Typical and maximum current consumptions in Stop and Standby modes On chip peripheral current consumption on page 43 added Package mechanical data inch values are calculated from mm and rounded to 4 decimal digits see Section 6 Package characteristics Vprog added to Table 27 Flash memory characteristics Ts temp added to Table 46 TS characteristics Ts vrefint Added to Table 11 Embedded internal reference voltage Handling of unused pins specified in General input output characteristics on page 54 All Os are CMOS and TTL compliant Table 4 Medium density STMS2F101xx pin definitions table clarified and Note 7 modified Internal LSI RC frequency changed from 32 to 40 kHz see Table 24 LSI oscillator characteristics Values added to Table 25 Low power mode wakeup timings Nenp modified in Table 28 Flash memory endurance and data retention Option byte addresses corrected in Figure 8 Memory map ACChg modified in Table 23 HSI oscillator characteristics tyrrren removed from Table 26 PLL characteristics Appendix A Important notes on page 71 added Added Figure 13 Figure 14 Figure 16 and Figure 18 Y Doc ID 1
96. to each power supply pin e Accurrent injection is applied to each input output and configurable I O pin These tests are compliant with EIA JESD 78 IC latch up standard Table 32 Electrical sensitivities Symbol Parameter Conditions Class Static latch up class TA 85 C conforming to JESD78A Il level A Doc ID 13586 Rev 14 ky STM32F101x8 STM32F101xB Electrical characteristics 5 3 12 WO current injection characteristics As a general rule current injection to the I O pins due to external voltage below Vgg or above Vpp for standard 3 V capable I O pins should be avoided during normal product operation However in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens susceptibility tests are performed on a sample basis during device characterization Functional susceptibilty to I O current injection While a simple application is executed on the device the device is stressed by injecting current into the I O pins programmed in floating input mode While current is injected into the I O pin one at a time the device is checked for functional failures The failure is indicated by an out of range parameter ADC error above a certain limit 25 LSB TUE out of spec current injection on adjacent pins or other functional failure for example reset oscillator frequency deviation The test results are given in Table 33 Table 33 I O current injection sus
97. viation between the last ideal transition and the last actual one Ep Differential Linearity Error maximum deviation between actual steps and the ideal one E Integral Linearity Error maximum deviation between any actual transition and the end point correlation line w V V 1LSBjpgA nom or 2006 depending on package A 4095 2 corn nn rann rar ra ran ee 1 4094 4 4093 4 i AH Er 1 sell A Ert LI 1 6 4 W 1 A 5 4 ZI ga Eo 7 EL 1 y 4 4 4 1 1 Y 1 3 3 1 A L E i cop oat ot Ep 2 1 po 17 z gt 1 1 uw ee 1 LSBipeAL 1 I4 p E pi 4 LES pcr 0 1 2 3 4 5 6 7 4093 4094 4095 4096 Vssa Vppa ai14395b 68 87 Doc ID 13586 Rev 14 q STM32F101x8 STM32F101xB Electrical characteristics 3 Figure 34 Typical connection diagram using the ADC STM32F10xxx Sample and hold ADC converter 1 i 1 Rain AINx Rape 12 bit n MM converter an T j Cparasitic f ai14139d Refer to Table 42 for the values of Rain Rapc and Cape 2 Coparasitic epresents the capacitance of the PCB dependent on soldering and PCB layout quality plus the pad capacitance roughly 7 pF A high Charasitic value will downgrade conversion accuracy To remedy this fapc Should be reduced General PCB design guidelines Power supply decoupling should be performed as shown in Figure 35 or Figure 36 depending on whether Vrer is connected to Vppa or not The 10 nF capacito
98. wer supply supervisor 00 e 16 2 3 11 Voltage regulator eee eee 17 2 3 12 Low power modes 0 cee nen 17 2949 DMA siii ca a ove ended SRI RENE eye eS a eee 17 2 3 14 RTC real time clock and backup registers 18 2 3 15 Independent watchdog eee eee 18 2 3 16 Window watchdog I eee re eee een 18 2 9 47 SysTick timet sessies dti eror wie E ki eee anl RE 18 2 3 18 General purpose timers TIMX eee eee eee eae 18 A e a E E EnS 19 2 3 20 Universal synchronous asynchronous receiver transmitter USART 19 2 3 21 Serial peripheral interface SPI onana naaa 19 2 3 22 GPIOs general purpose inputs outputs sasaaa anaana 19 2 3 23 ADC analog to digital converter llle 19 2 3 24 Temperature sensor erer re ee eee 20 2 3 25 Serial wire JTAG debug port SWJ DP voeooooooun 20 3 Pinouts and pin description 000 cc eee eee ee 21 2 87 Doc ID 13586 Rev 14 KII STM32F101x8 STM32F101xB Contents 4 5 Memory mapping ee su 0002 xo ck ea e Ri n a aa CCCo a ac 28 Electrical characteristics o oooooooooooomommmomoo o 29 5 1 Parameter conditions es ee es ee ka kaa eens 29 5 1 1 Minimum and maximum values sere e eooooooon 29 5 1 2 Typical values issdezeek eee ko ea oo tae Ya Po REA LEAGUE ERR Rx 29 5 1 3 Typical curves Ill L ll L
99. xcuk 36 MHz 0 0278 1820 us 65536 x 65536 trimxcLk tmax_counNT Maximum possible count FrimxcLk 36 MHz 119 2 s 1 TIMx is used as a general term to refer to the TIM1 TIM2 TIM3 and TIM4 timers Communications interfaces 12C interface characteristics Unless otherwise specified the parameters given in Table 39 are derived from tests performed under the ambient temperature fpc 1 frequency and Vpp supply voltage conditions summarized in Table 8 The STM32F101xx medium density access line I C interface meets the requirements of the standard I C communication protocol with the following restrictions the I O pins SDA and SCL are mapped to are not true open drain When configured as open drain the PMOS connected between the I O pin and Vpp is disabled but is still present The I C characteristics are described in Table 39 Refer also to Section 5 3 12 I O current injection characteristics for more details on the input output alternate function characteristics SDA and SCL Doc ID 13586 Rev 14 ky STM32F101x8 STM32F101xB Electrical characteristics 3 Table 39 1 C characteristics Standard mode I2C Fast mode 12C 2 Symbol Parameter Unit Min Max Min Max twscii SCL clock low time 4 7 1 3 tw SCLH SCL clock high time 4 0 0 6 tsu spa SDA setup time 250 100 trispa SDA data hold time 0 04 900 SDA SDA and SCL rise time 10
100. y saved Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency Doc ID 13586 Rev 14 15 87 Description STM32F101x8 STM32F101xB 2 3 6 2 3 7 2 3 8 2 3 9 2 3 10 16 87 External interrupt event controller EXTI The external interrupt event controller consists of 19 edge detector lines used to generate interrupt event requests Each line can be independently configured to select the trigger event rising edge falling edge both and can be masked independently A pending register maintains the status of the interrupt requests The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period Up to 80 GPIOs can be connected to the 16 external interrupt lines Clocks and startup System clock selection is performed on startup however the internal RC 8 MHz oscillator is selected as default CPU clock on reset An external 4 16 MHz clock can be selected in which case it is monitored for failure If failure is detected the system automatically switches back to the internal RC oscillator A software interrupt is generated if enabled Similarly full interrupt management of the PLL clock entry is available when necessary for example on failure of an indirectly used external crystal resonator or oscillator Several prescalers allow the configuration of the AHB frequency t

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