ST ST72681 handbook
Contents
1. yy ST72681 USB 2 0 high speed Flash drive controller Features USB 2 0 interface compatible with mass storage device class Integrated USB 2 0 PHY supporting USB high speed and full speed Suspend and Resume operations Not For New Design LQFP48 7 Clock management Integrated PLL for generating core USB m Mass storage controller interface MSCI 2 0 clocks f t 12 MH tal Supports 2 KB page NAND Flash devices Eng eee al including Numonyx Hynix Samsung Data protection Toshiba Micron Renesas Write protect switch control Reed Solomon encoder decoder on the fly Public private partitions support correction 4 bytes of a 512 byte block Production tool device configurability Flash identification support USB vendor ID product ID VID PID serial Upto 12 MB s for read and 8 MB s for write number and USB strings with foreign operations in single channel language support Up to 4 NAND Flash supported per channel SCSI strings m Embedded ST7 8 bit MCU Oneortwo LED outputs m Supply management Adjustable NAND Flash bus frequency to 8 3 V operation reach highest performance Integrated 3 3 1 8 V voltage regulator Code update in the NAND Flash memory m USB 2 0 low power device compliant LQFP48 7x7 ECOPACK package Less than 100 mA during write operation Development support with two NAND Flash devices Complete reference design including Less tha2. 1 5kQ pull up resistor on the device side and the 15kQ pull down resistor on the host side 2 Nottested in production guaranteed by characterization Table25 Timing characteristics Symbol Parameter Conditions Min Max Unit Full speed mode trn Rise time Cj 50 pF 4 20 ns ter Fall time Cj 2 50 pF 4 20 ns High speed mode tusr Rise time 500 1 ps tusr Fall time 5000 ps tusprat HS data rate 479 76 480 24 Mb s 1 Not tested in production guaranteed by characterization 4 29 34 Electrical characteristics ST72681 Table 26 8 USB High Speed Transmit Waveform requirements Voltage Level DP DN Time Unit Interval Ul 2 082 to 2 084 ns Level 1 475 mV Level 2 475 mV Point 1 OV 5 Ul Point 2 OV 95 UI Point 3 300 mV 35 UI Point 4 300 mV 65 UI Point 5 300 mV 35 UI Point 6 300 mV 65 UI Figure 20 USB signal eye diagram mm 400mV ses Phint4 Differential 0 Volts Differential 400mv Differential Unit Interval 0 100 30 34 ST72681 Package mechanical data 8 Package mechanical data In order to meet environmental requirements ST offers this device in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and pro
3. ST72681 can be configured through a dedicated PC software tool The NAND Flash RE and WE signals frequencies can be independently configured to 30 MHz 20 MHz 15 MHz 12 MHz and 10 MHz The logical size reduction factor can be configured to 9096 or 5096 in the event of having too many bad blocks this option resizes the used blocks part of the LUT to 900 or 500 ky 13 34 Mass storage implementation ST72681 5 5 1 5 2 5 2 1 5 2 2 5 2 3 5 3 14 34 Mass storage implementation USB characteristics The ST72681 is compliant with USB 2 0 specification It is able to operate in both high speed and full speed modes using a bidirectional control endpoint O and a bidirectional bulk endpoint 2 It automatically recognizes the speed to use on the bus by a process of negotiation with USB Host BOT SCSI implementation BOT specification The USB Mass Storage Class Bulk Only Transport BOT specification version 1 0 is implemented It allows the device to be recognized by the host as a mass storage USB device SCSI specification Moreover inside BOT transfers SCSI commands are encapsulated for mass storage operations The related specifications are SBC 2 revision 10 SCSI Block Commands 2 and SPC 4 revision 7a SCSI Primary Commands 4 Bootability specification The USB Mass Storage Specification for Bootability revision 1 0 is implemented It allows the PC host to boot the operating system from the USB
4. a a a o B a BR e a I Os pullup resistance kOhms e o 28 29 N a a ST72681 Electrical characteristics Figure 10 Two typical Applications with unused I O Pin Vpp33 Device z 10k 1 UNUSED I O PORT PORT 10kQ UNUSED I O PORT DeviceDevice 7 7 2 Output driving current Subject to general operating conditions for Vpp33 fosc and Ta unless otherwise specified Table 21 Output driving current Symbol Parameter Conditions Min Max Unit Output low level voltage for a D2 I O pin when 8 lo 22mA 300 pins are sunk at same time see Figure 11 lo 1 Output low level voltage for a D4 I O pin when 8 2 VoL pins are sunk at same time see Figure 12 lo 4mA 409 mY F gt Output low level voltage for a D8 I O pin when 8 clio 8 mA 500 pins are sunk at same time see Figure 13 o I Output high level voltage for a D2 I O pin when 8 a lo 22mA 600 pins are sourced at same time see Figure 14 8 07 Vpp33 i i ee m OH Output high level voltage for a D8 I O pin when 8 WR 600 pins are sourced at same time see Figure 16 107 1 The lo current sunk must always respect the absolute maximum rating specified in Section 7 2 2 Current characteristics and the sum of lig I O ports and control pins must not exceed lyss 2 The ljo current sourced must always respect
5. characterization 3 Data based on characterization results done with the external components specified in Section 7 5 2 Crystal oscillator not tested in production Clock and timing characteristics Subject to general operating conditions for Vpp33 fosc and Ta General timings Table 13 General timing characteristics Symbol Parameter Conditions Min Typ Max Unit 2 3 12 tepu to nsT Instruction cycle time fasc 15 MHz 133 200 800 ns CPU ST72681 Electrical characteristics Table 13 General timing characteristics continued Symbol Parameter Conditions Min Typ Max Unit Interrupt reaction time 10 22 topu NT tyr At 10 v IT Alc INST fcpu 12 MHz 0 666 1 466 Hs 1 Data based on typical application software 2 Time measured between interrupt event and interrupt vector fetch At nsr is the number of topy cycles required to finish executing the current instruction 7 5 2 Crystal oscillator 4 The ST72681 internal clock is supplied from a crystal oscillator All the information given in this paragraph are based on characterization results with specified typical external components In the application the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start up stabilization time Refer to the crystal manufacturer for more details frequency package accurac
6. one NAND Flash device with one Chip Enable signal Note that pins NAND RnB2 NAND CE2 NAND CE3 and NAND CE4 should remain unconnected 8 34 a ST72681 Application schematics ST72681 R21 can support up to four NAND Flash Chip Enable signals The application can use one of the following configurations One NAND Flash device with four Chip Enable signals NAND CE1 NAND CE2 NAND CE3 and NAND_CE4 are used One NAND Flash device with two Chip Enable signals NAND CE1 and NAND CE2 are used One NAND Flash device with one Chip Enable signal only NAND CE1 is used Two NAND Flash devices with two Chip Enable signals NAND CE1 and NAND CE2 are used to select the first NAND Flash device and NAND CES and NAND CE4 to select the second NAND Flash device Two NAND Flash devices with one Chip Enable signal NAND CE1 and NAND CE2 are used to select is used to select the first NAND Flash device and the 2nd NAND Flash device respectively 4 NAND Flash devices with 1Chip Enable signal NAND CE1 selects the first NAND Flash device NAND CE the 2nd NAND Flash device NAND CES to select the third and NAND CE4 to select the fourth NAND Flash device 9 34 NAND Flash interface ST72681 4 4 1 10 34 NAND Flash interface NAND Flash support table Table 6 Known NAND Flash compatibility guide for R20 and R21 devices 2 Number of
7. the mean value plus or minus three times the standard deviation mean 35 7 1 2 Typical values Unless otherwise specified typical data are based on Ta 25 C and Vpp33 3 3 V They are given only as design guidelines and are not tested 7 1 3 Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested 7 1 4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 4 Figure 4 Pin loading conditions p 4 DEVICE PIN C 17 34 Electrical characteristics ST72681 71 5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 5 Figure 5 Pin input voltage H DEVICE PIN Cm NN 7 2 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the Device This is a stress rating only and functional operation of the Device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability 7 2 1 Voltage characteristics Table 7 Voltage characteristics Symbol Ratings Maximum value Unit Vpp33 Vss Supply voltage 4 0 V 1 2 Vss 0 3 to Vin Input voltage on any other pin Vbpss 0 3 V VESD HBM Electrostatic discharge voltage Human Body Model See Section 7 6 3 on VESD M
8. the absolute maximum rating specified in Section 7 2 2 Current characteristics and the sum of lig I O ports and control pins must not exceed lypp33 True open drain I O pins do not have Voy Figure 11 Typical Vo at Vpp33 3 3 V I O D2 Vol I Os D2 at Vdd 3 3V Vol 2mA mV Bb a o o lol mA 4 25 34 Electrical characteristics ST72681 Figure 12 Typical Vo at Vpp33 3 3 V I O D4 Vol I Os D4 at Vdd 3 3V Vol 4mA mV lol mA Figure 13 Typical Vo at Vpp33 3 3 V I O D8 100 80 60 40 20 0 0 1 2 3 4 5 6 Vol I Os D8 at Vdd 3 3V Vol 8mA mV o o S o 0 2 4 6 8 lol mA o Figure 14 Typical Vpp33 VoH VS Vpp33 VO D2 Vdd Voh Os D2 at Vdd 3 3V N e e a o N Voh 2mA mV e 8 o 2 3 loh mA Figure 15 Typical Vpp33 VoH VS Vpp33 VO D4 Vdd Voh I Os D4 at Vdd 3 3V Voh 4mA mV 8 loh mA 140 120 100 60 40 20 0 0 1 2 3 4 5 6 26 34 a ST72681 Electrical characteristics Figure 16 Typical Vpp33 VoH VS Vpp33 VO D8 Vdd Voh I Os D8 at Vdd 3 3V Voh 8mA mV 3 o 0 2 6 8 10 loh mA 7 8 Control pin characteristics 7 8 1 Asynchronous RESET pin Ta 0 to 55 C unless oth
9. 3 O TT D4 NAND Chip Enable 3 16 NAND CE4 O TT D4 NAND Chip Enable 4 37 NAND RnB Tr D2 NAND Ready Busy 36 NAND WP O TT D2 NAND Write Protect 35 READ ONLY Ti D2 diee Ms switch 0 Read Write 1 34 EEPROM SCL O Tr D2 EEPROM serial clock 28 LED2 O TT D8 Green LED USB access 27 LED1 O TT D8 Red LED NAND memory access 7 34 Application schematics ST72681 3 Application schematics Figure 3 Application schematic aw T On Board Flash1 Vin Vout HJ Decoupling capacitors to be located close to U2 U3 U4 amp US V33 inputs ND FLASR TSOPAE E Decoupling capacitors to be located close to U1 V33 inputs 5 va Vi amp Usb vis Use m as 4 2 a w kad 72681 Qrpas OK a wp 3 1 Ter E 1 E ewm van aoeonsoa E N H E p CU READ ony 38 4 z E V55 2 E I Ne UASR TSUPR E vis USB p GND sen 7 On Board Flash 2 4 only available on ST72681 R21 ST72681 R20 only supports single NAND Flash Chip Enable configuration
10. B2 PHY OSC and PLL power supply output 1 8 V Table 3 USB 2 0 interface Pin Pin name Type Description 11 VSSBL S Ground for buffers and de serialization flip flops 1 8 V 10 USBDM lO USB2 DATA 9 USBDP I O USB2 DATA 8 VDD3 Supply voltage for the FS compliance 3 3 V 7 VDDC Supply voltage for DLL amp XOR tree 1 8 V 6 VSSC Ground for DLL amp XOR tree 1 8 V 5 RREF lO Bola paka a E process adaptation Table 4 USB 2 0 and core clock system Pin Pin name Type Description 4 VSSA S Groundforoscillator amp PLL 18V 3 OSCOUT O 12 MHz oscillator output 2 OSCIN l 12 MHZ oscillator input 1 VDDA S Supply voltage for oscillator amp PLL 1 8 V 6 34 ST72681 Pin description 4 Table 5 General purpose I O ports mass storage I Os Pin Pin name Type ace Main TuncGon Input Outputs after reset 45 NAND D 0 I O Tr D4 NAND Data 0 44 NAND D 1 I O Tr D4 NAND Data 1 43 NAND D 2 I O Tr D4 NAND Data 2 42 NAND D 3 I O Tr D4 NAND Data 3 41 NAND D 4 I O Tr D4 NAND Data 4 40 NAND D 5 I O Tr D4 NAND Data 5 39 NAND DJI6 I O Tr D4 NAND Data 6 38 NAND D 7 I O Tr D4 NAND Data 7 26 NAND ALE I O Tr D8 NAND Address Latch Enable 22 NAND CLE O TT D8 NAND Command Latch Enable 21 NAND WE O Tr D8 NAND WRite Enable 20 NAND RE O Tr D8 NAND read enable 19 NAND CE1 O Tr D4 NAND Chip Enable 1 18 NAND CE2 O Tr D4 NAND Chip Enable 2 17 NAND CE
11. M Electrostatic discharge voltage Machine Model page 23 1 Directly connecting the RESET and I O pins to Vpp33 or Vgg could damage the device if an unintentional internal reset is generated or an unexpected change of the I O configuration occurs for example due to a corrupted program counter To guarantee safe operation this connection has to be done through a pull up or pull down resistor typical 4 7kQ for RESET 10kQ for I Os For the same reason unused I O pins must not be directly tied to Vpp33 or Vss 2 When the current limitation is not possible the Vin absolute maximum rating must be respected otherwise refer to li piv specification A positive injection is induced by Vin gt Vpp33 while a negative injection is induced by Vin lt Vss 18 34 a ST72681 Electrical characteristics 7 2 2 Current characteristics Table 8 Current characteristics Symbol Ratings Maximum value Unit lvpD33 Total current into Vpp33 power lines source 200 lvss Total current out of Vgs ground lines sink 200 Output current sunk by any O type D2 25 m LG Output current sunk by any I O type D4 35 I x Output current sunk by any O type D8 50 Output current source by any I Os and control pin 25 1 All power supply Vppaa and ground Vss lines must always be connected to the external supply 2 peler to Table 5 General purpose I O ports mass stora
12. M 512 MB SLC2K Single CE 1 1 2 3or4 Hynix HY27UH084G5M 512 MB SLC2K Dual CE 10r2 Hynix HY27UH088G2M 1 GB SLC2K Single CE 1 1 2 3or4 Hynix HY27UT084G2M 512 MB MLC2K Single CE 1 1 2 3or4 Hynix HY27UU088G5M 1 GB MLC2K Dual CE 10r2 Micron 29F2G08AA 256 MB SLC2K Single CE 1 1 2 30r4 Micron 29F4G08BA 512 MB SLC2K Single CE 1 1 2 30r4 Micron 29F8G08FA 1 GB SLC2K Dual CE 10r2 1 This list is provided as a guide only as it is not possible to automatically guarantee support for all the additions and updates across the listed ranges of manufacturers devices 2 Only NAND Flash devices with 2 Kbyte pages are supported a ST72681 NAND Flash interface 4 2 NAND error correction No NAND Flash memory arrays are guaranteed by manufacturers to be error free Error occurrence depends on the Flash cell type MLC or SLC The ST72681 embeds hardware and firmware mechanisms to correct the errors 4 2 1 Hardware error correction The ST72681 embeds a Reed Solomon algorithm based hardware cell This cell directly manages 512 byte data packets on the NAND Flash I O system Based on a data packet contents the cell generates an 80 bit Error Correction Code ECC consisting of 8 words each containing 10 bits During write operations to NAND memory the 512 bytes of data and the ECC are stored together in the same page The ECC is stored in the corresponding Redundant Area RA using 10 bytes During read operations t
13. NAND devices NAND name NAND size bg hats or Gbytes supported ane R20 device R21 device Samsung K9F1G08U 128 MB SLC2K Single CE 1 2 3 0r4 Samsung K9F2G08U 256 MB SLC2K Single CE 1 1 2 3 0r4 Samsung K9F4G08U 512 MB SLC2K Single CE 1 1 2 3 0r4 Samsung KIK4G08U 512 MB SLC2K Single CE 1 1 2 3or4 Samsung KIW4G08U 512 MB SLC2K Dual CE 10r2 Samsung K9K8G08U 1 GB SLC2K Single CE 1 1 2 3or4 Samsung KIW8G08U 1 GB SLC2K Dual CE 10r2 Samsung K9WAGOSU 2 GB SLC2K Dual CE 10r2 Samsung KINBG08U 4 GB SLC2K Quad CE 1 Samsung KIG4G08U 512 MB MLC2K Single CE 1 1 2 3or4 Samsung K9L8GO8U 1 GB MLC2K Single CE 1 1 2 3or4 Samsung K9HAG08U 2 GB MLC2K Dual CE 10r2 Samsung KIMBG08U 4 GB MLC2K Quad CE 1 Toshiba TH58NVGOSS3 128 MB SLC2K Single CE il 1 2 3or4 Toshiba TH58NVG1S3 256 MB SLC2K Single CE 1 1 2 3or4 Toshiba TH58NVG2S3 512 MB SLC2K Single CE 1 1 2 3or4 Toshiba TH58NVG1D4 256 MB MLC2K Single CE 1 1 2 3or4 Toshiba TH58NVG2D4 512 MB MLC2K Single CE 1 1 2 3or4 Toshiba TH58NVG3D4 1 GB MLC2k Single CE 1 1 2 3or4 Numonyx NANDO1GW3B 128 MB SLC2K Single CE 1 1 2 30r4 Numonyx NANDO2GW3B 256 MB SLC2K Single CE 1 1 2 30r4 Numonyx NANDO4GW3B 512 MB SLC2K Single CE 1 1 2 30r4 Numonyx NANDO8GWSB 1 GB SLC2K Single CE 1 1 2 30r4 Numonyx NAND04GW3C 512 MB MLC2K Single CE 1 1 2 30r4 Hynix HY27UF081G2M 128 MB SLC2K Single CE 1 1 2 3or4 Hynix HY27UG082G2M 256 MB SLC2K Single CE 1 1 2 3or4 Hynix HY27UG084G2
14. TS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2009 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com a 34 34
15. ables are the following e Type I input O output S supply e Input level A Dedicated analog input e In Output level Cr CMOS 0 3Vpp 0 7Vpp with input trigger T TIL 0 8V 2 V with Schmitt trigger e Output level D8z 8mA drive D4 zA4mA drive D2z 2mA drive Figure 2 48 pin LQFP package pinout SENGEHEK Q O08002020200c ie anaaaaaaaa NALD ZZZZZZZZZ DOON AN NAA ZZZZZZZzzzz opoooooooonon9 48 47 46 45 44 43 42 41 40 39 38 37 VDDA Cie 36 NAND WP OSCIN 2 350 READ ONLY OSCOUT 03 340 EEPROM SCL VSSA 04 33H VSS 2 RREF 05 320 Dos 2 VSSC ge 81H NG VDDC ri ST72681 so NON VDD3 8 290 RESET USBDP U9 280 LED2 USBDM 010 270 LED1 VSSBL 011 26 NAND ALE EEPROM SDA VDDBL 12 20 VSS 3 13 14 15 16 17 18 19 20 21 VDDOUS VSS VDD33 3 FR 1 Must remain NOT connected in the application 5 34 Pin description ST72681 Table 2 Power supply Pin Pin name Type Description 48 vyssi S Goud S 47 VDD33 1 S I Os and regulator supply voltage 33 VSS 2 S Ground 32 VDD33 2 S I Os and regulator supply voltage 25 VSS_3 S Ground 24 VDD33_3 S Os and regulator supply voltage 14 VSS_4 S Ground 15 VDD33_4 S Os and regulator supply voltage 13 VDDOUSB S US
16. application life the NAND Flash memories written and erased by block many times The NAND Flash device is guaranteed for a limited number of writes about 100 000 cycles As a consequence the controller must keep write erase operations to a minimum for any individual block A method to limit these cycles is to use a Wear Levelling scheme between all NAND Flash memory blocks LUT usage The LUT is used for transfers between a logical address range and a block It contains free blocks which are used in the wear levelling scheme During write command treatment the firmware calculates the zones blocks and pages for data write access In a block write operation the firmware applies the following scheme to avoid block wearing e Theleast recently used block is chosen from the free block part of the LUT Valid data from the old block is copied to the new block New data from the write command is written to the new block The old block is erased The LUT is updated after identifying the new block in the used block part and the old block in the free block part ky ST72681 NAND Flash interface Using this scheme a logical address range doesn t correspond to a constant block A write command repeated several times to the same logical address writes physically into different blocks This method shares the wearing evenly across all blocks of the concerned zone 4 5 NAND Flash interface configuration Applications based on
17. declared bad if 1 of these 5 bytes contains 4 bits or more at 0 11 34 NAND Flash interface ST72681 4 3 2 4 3 3 4 4 4 4 1 12 34 Bad block replacement The firmware works with groups of 1024 blocks called zones A complete NAND Flash configuration can contain several zones Each zone is described in a Look Up Table LUT containing 1024 entries A LUT is composed of 3 parts used blocks free blocks and bad blocks e The bad blocks part contains as many entries as the number of bad blocks identified in that zone e The used blocks part can have a size of 1000 900 or 500 entries This size is configurable and also depends on the number of identified bad blocks e The free blocks part contains the remaining entries The used blocks part is used to do a correspondence between NAND Flash blocks and logical address ranges This system allows all bad blocks to be masked from the Host As a result bad blocks are never seen Only a range of logical addresses are visible which correspond to the sum of the used blocks part of all zones Late fail block During normal application life defects can appear in the NAND Flash memory Under certain conditions these defects are not correctable and the corresponding block is declared as bad In this case new bad blocks are identified in the bad blocks part of the LUT and replaced by new blocks from the free blocks part Wear levelling During normal
18. duct status are available at www st com ECOPACK is an ST trademark Figure 21 48 pin low profile quad flat package outline hs B 5 A E D1 A2 i HAHA af T b a a L i LI j FT i q EEZ a GE Sue EEZ r 1 d ELI mag L O en Li 1 P L 0 Table 27 48 pin low profile quad flat package dimensions mm inches Dim Min Typ Max Min Typ Max A 1 60 0 0630 A1 0 05 0 15 0 0020 0 0060 A2 1 35 1 40 1 45 0 0530 0 0550 0 0570 b 0 17 0 22 0 27 0 0070 0 0090 0 0110 C 0 09 0 20 0 0040 0 0080 D 9 00 0 3540 D1 7 00 0 2760 E 9 00 0 3540 E1 7 00 0 2760 e 0 50 0 0200 0 0 3 5 7 0 3 5 7 L 0 45 0 60 0 75 0 0180 0 0240 0 0300 L1 1 00 0 0390 Number of Pins N 48 1 Values in inches are converted from mm and rounded to 4 decimal digits 31 34 Device ordering information ST72681 9 32 34 Device ordering information Table 28 Feature comparison table Features added in the ST72681 R21 versus ST72681 R20 Support for up to 4 NAND Flash devices Description Firmware revision R21 upgrades the number of supported NAND Flash devices from 1 to 4 ina single channel Continued AutoRun CDROM partition support AutoRun runs a program when the USB Flash Drive is inse
19. ecifications that means when a device belongs to Class A it exceeds the JEDEC standard B Class strictly covers all the JEDEC criteria international standard 23 34 Electrical characteristics ST72681 7 7 7 7 1 24 34 I O port pin characteristics General characteristics Subject to general operating conditions for Vpp33 fosc and Ta unless otherwise specified Table 20 General I O port pin characteristics Symbol Parameter Conditions Min Typ Max Unit Vi Input low level voltage ln Vpp33 T Vin Input high level voltage TIE ports 983X VDD33 Vhys Schmitt trigger voltage hysteresis 1 400 mV Vss lt Vin lt Vpp33 IL Input leakage current standard I Os 1 PA Vss lt Vin lt Vppas 10 Itsy 5V tolerant input leakage current Vin 5V 25 C 30 Rpy Weak pull up equivalent resistor Viy Vss kba E 32 50 75 ka 1 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested in production 2 The Rpy pull up equivalent resistor is based on a resistive transistor This data is based on characterization results tested in production at Vpp33 max Figure 8 Typical Vj and Vjp standard I Os Vil Vih V 2 5 2 E S 15 a aia eg Hq 0 5 Nile 27 28 29 3 31 32 33 34 35 36 Vdd V Figure 9 Typical Rpy VS Vpp33 with Vin Vss I Os pullup resistance
20. electrical sensitivity Based on three different tests ESD LU and DLU using specific measurement methods the product is stressed in order to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electrostatic discharge ESD Electrostatic discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin This test conforms to the JESD22 A114A A115A standard Table 18 Absolute Maximum Ratings Symbol Ratings Conditions Max Unit Vesp HBm Electrostatic discharge voltage Human Body Model Ty 25 C 2000 V 1 Data based on characterization results not tested in production Static latch up LU 3 complementary static tests are required on 10 parts to assess the latch up performance A supply overvoltage applied to each power supply pin and a current injection applied to each input output and configurable I O pin are performed on each sample This test complies with EIA JESD 78 IC latch up specifications Table 19 Electrical sensitivity values Symbol Parameter Conditions Class LU Static latch up class Ta 25 C A 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC sp
21. erwise specified Table 22 RESET pin characteristics Symbol Parameter Conditions Min Typ Max Unit Vi Input low level voltage 916x Vppas3 y Vin Input high level voltage d Vpp33 Vhys Schmitt trigger voltage hysteresis 450 mV Vpp33 3 3 V 20 40 80 RoN Pull up equivalent resistor kQ Vpp33 2 V 100 teh RsTL External reset pulse hold time e 2 5 us tyrsTy Filtered glitch duration 200 ns tewRstL External reset pulse duration 500 us tiwRSTL Internal reset pulse duration 2 tepu 1 The level on the RESET pin must be free to go below the Vi max level specified in Section 7 8 1 Asynchronous RESET pin Otherwise the reset will not be taken into account internally 2 To guarantee the reset of the Device a minimum pulse has to be applied to the RESET pin All short pulses applied on RESET pin with a duration below ton RSTL Can be ignored Not tested in production guaranteed by design 3 The reset network protects the device against parasitic resets The external reset duration must respect this timing to guarantee a correct start up of the internal regulator at power up Not tested in production guaranteed by design 4 27 34 Electrical characteristics ST72681 Figure 17 Typical Roy on RESET pin NRESET pullup kOhms NRESET pullup kOhms 3 Vdd V 7 9 Other communication interface characteristics 7 9 1 MSCI pa
22. ge I Os for the output drive capability of each of the I Os 7 2 3 Thermal characteristics Table 9 Thermal characteristics Symbol Ratings Value Unit TsTG Storage temperature range 65 to 150 C TJMAX Maximum junction temperature 120 C 7 3 Operating conditions 7 3 1 General operating conditions Table 10 General operating conditions Symbol Parameter Conditions Min Max Unit fopy Internal clock frequency 0 30 MHz Vpp33 Power supply 3 0 3 6 V TA Ambient temperature range 0 70 C 19 34 Electrical characteristics ST72681 7 4 7 4 1 7 4 2 7 5 7 5 1 20 34 Figure 6 Guaranteed functionality range fcpu MHz FUNCTIONALITY GUARANTEED IN THIS AREA 30 FUNCTIONALITY NOT GUARANTEED 15 IN THIS AREA gt SUPPLY VOLTAGE Vpp33 2 0 2527 3 0 3 3 3 6 Supply current characteristics RUN and SUSPEND modes Table 11 RUN and SUSPEND modes Symbol Parameter Conditions Min Typ Max Unit Supply current in RUN mode fosc 12 MHz 15 25 35 mA IDD E Supply current in SUSPEND mode ibas 3 3 V Ta 60 90 190 pA Supply and clock managers Table 12 Supply and clock managers Symbol Parameter Conditions Typ Max Unit Ipp ck Supply current of crystal oscillator 3 1000 2000 pA 1 Typical data are based on T4 25 C and fopy 12 MHz 2 Not tested in production guaranteed by
23. he 512 bytes of data and the 8 ECC words are read back and are passed through the Reed Solomon cell for decoding The cell allows the correction of 4 symbols in this 520 symbol packet 512 symbols from data 8 symbols from ECC The hardware cell gives 3 possible results e No error detected the data packet can be used as it is Correctable error detected the corrected data are available in a specific 512 byte buffer in the Reed Solomon cell and are ready to use e Uncorrectable error detected data corruption is not repairable 4 2 2 Firmware error management The firmware defines the error correction possibilities with the corrected data packet When data is not repairable the block is considered as bad and replaced by another one See below for further information 4 3 Management of bad NAND Flash blocks NAND Flash device manufacturers deliver their products with factory marked bad blocks This marking depends on the manufacturer and the NAND Flash type page size memory technology etc The ST72681 supports all bad block markings currently available on the market 4 3 1 Bad block identification During firmware initialization the MCU scans the entire NAND Flash configuration to identify bad blocks A bad block is defined as follows e 5different Block Status bytes are considered 4 Status bytes from page O and 1 from an other page page 127 for MLC NAND Flash memory page 1 for SLC NAND Flash memory e The considered block is
24. his behavior is configurable through PC dedicated software ST7268x Production Tool By default LED 1 responds to NAND Flash memory access activity and LED 2 responds to USB activity Use of LED 1 is optional When this option is not active LED 2 reacts to both USB and NAND Flash activity Read only switch The READ ONLY pin of the ST72681 is an input pin to be connected to VDD or GND depending on the behavior of the device e When this pin is connected to GND no limitations are applied on the PC command received e When this pin is connected to VDD or unconnected the firmware filters all accesses to the NAND Flash which modify the NAND Flash state write erase etc and returns an error to the PC ST72681 Electrical characteristics 7 Electrical characteristics 7 1 Parameter conditions Unless otherwise specified all voltages are referred to Vas 7 1 1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the Devices with an ambient temperature at Ta 25 C and Ta Tamax given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent
25. history Xa cena eee dee AA eR Q8 OR QR ORC UNDIS Rd a 33 y 3 34 Introduction ST72681 1 Introduction The ST72681 is a USB 2 0 high speed Flash drive controller The USB 2 0 high speed interface including PHY and function supports USB 2 0 mass storage device class The mass storage controller interface MSCI combined with the Reed Solomon encoder decoder on the fly correction 4 byte on 512 byte data blocks provides a flexible high transfer rate solution for interfacing a wide of range NAND Flash memory device types The internal 60 MHz PLL driven by the 12 MHz oscillator is used to generate the 480 MHz frequency for the USB 2 0 PHY The ST7 8 bit CPU runs the application program from the internal ROM and RAM USB data and patch code are stored in internal RAM I O ports provide functions for EEPROM connection LEDs and write protect switch control The internal 3 3 to 1 8 V voltage regulator provides the 1 8 V supply voltage to the digital part of the circuit Figure 1 Device block diagram Mass USB 2 0 Storage Solomon Interface Correction 3 3 V to 1 8 V voltage regulator 434 r ST72681 Pin description 2 Pin description Figure 2 shows the LQFP48 package pinout while Table 2 Table 3 Table 4 and Table 5 give the pin description The legend and abbreviations used in these t
26. ll pins of the device until a functional disturbance occurs This test conforms with the IEC 1000 4 2 standard e FTB A Burst of Fast Transient voltage positive and negative is applied to Vpp33 and Vss33 through a 100pF capacitor until a functional disturbance occurs This test conforms with the IEC 1000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Software recommendations The software flowchart must include the management of runaway conditions such as e Corrupted program counter e Unexpected reset e Critical Data corruption control registers Prequalification trials Most of the common failures unexpected reset and program counter corruption can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the de
27. mass storage application In this case the Host uses BOT LUN 0 logical unit number A specific tool must be used to format the logical drive in order to make it bootable by programming the correct information Multi LUN device characteristics The application can be configured with a dedicated PC software tool as a multi LUN device In this case up to 3 different drives are available public drive additional drive and private drive Public and additional drives can be configured as removable drive hard disk drive or CD ROM drive ST72681 Mass storage implementation 5 3 1 5 3 2 5 3 3 5 3 4 5 4 Public drive The public drive is the default configuration in a mono LUN mode In this default case it is declared as a removable drive The public drive is mandatory and can not be removed from the configuration By customization using PC software it can be declared as a removable drive a CD ROM drive or a hard disk drive This drive is the LUN 0 in BOT commands Private drive The Private drive is optional Its type is removable drive and is not configurable This drive is protected by password and cannot be directly accessed through the PC operating system A PC software tool is necessary to send a command with the password to unlock the device The device is then open and accessible by the PC operating system until reset or reception of a new command to lock the drive This drive is the LUN 1 in BOT c
28. n 500 pA in suspend mode schematics BOM and Gerber files m AutoRun CDROM partition support Supports Windows Vista XP 2000 ME Linux and MacOS Drivers available for m Bootability support HDD mode Windows 98 SE Table 1 Device summary Orderable part numbers Features ST72681 R20 ST72681 R21 USB interface USB 2 0 high speed Number of NAND Flash devices supported up to 4 R W speed 11MB s and 7MB s 12MB s and 8MB s Operating voltage 3 0 to 3 6 V Operating temperature 0 to 70 C Package LQFP48 7x7 Die form 1 Number of NAND Flash devices supported in a single channel February 2009 Rev 6 1 34 This is information on a product still in production but not recommended for new designs www st com Contents ST72681 Contents 1 Cu go NAA PAA AA ee eae eR ed 4 2 Pin description makaka dina RR ORE RR dec cado dod oa De CRACK 5 3 Application schematics eeeeellllesees 8 4 NAND Flash interface 22 2 rene rune 10 4 1 NAND Flash support table 0 00 10 4 2 NAND error correction llle 11 4 2 1 Hardware error correction cee eee eee 11 4 2 2 Firmware error management 00 0 cee eee eee 11 4 3 Management of bad NAND Flash blocks 20005 11 4 3 1 Bad block identification 0c eee 11 4 3 2 Bad block replacement 0 0 eee 12 4 3 3 Late fail block 0 0 0 0 0 ee 12 4 4 Wear levelling ues cxx ERR bce eee e
29. ommands Additional drive The additional drive is optional Its type can be removable drive hard disk drive or CD ROM drive This drive is LUN 1 in BOT commands if the private drive option is not active and is LUN 2 if the private drive option is active CD ROM considerations When a drive is declared as CD ROM the ST72681 R21 manages this drive with a logical block size of 2 Kbytes To be correctly recognized by the host it is preferable to build a CDFS partition on this CD ROM See the ST7268x Production Tool User Manual for more information Note that the ST72681 R20 doesn t consider the CD ROM partition as a specific case The logical block size is 512 bytes and any file system can be used In both cases the CD ROM partition allows the use of the AutoRun operating system feature During device connection the CD ROM partition is recognized and the host tries to run the application corresponding to the autorun inf file present into this CD ROM partition Mass storage interface configuration In addition to the parameters already described as configurable in the previous chapters additional customizable information includes e USB parameters VID PID all string information SCSI parameters strings for inquiry commands 15 34 Human interface implementation ST72681 6 6 1 6 2 16 34 Human interface implementation LED behavior The application is designed to manage 2 LEDs T
30. r the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUC
31. rallel interface Figure 18 Timing diagrams for input mode with max load on CTRL signal 50 pF CTRL external N f DATA cs A DATA i WY UN DATA i 1 ips 1 tpgis the setup time for data sampling Figure 19 Timing diagrams for output mode with max CTRL signal 50 pF DATA CTRL external BAA d DATA i X DATA i 1 I gt ipo 1 tpo is the data output time for data sampling 28 34 Ti ST72681 Electrical characteristics Table 23 MSCI Parallel Interface DC Characteristics Symbol Parameter Conditions Min Typ Max Unit tps Data Setup Time 11 ns tpo Data Output time 6 ns Cerri CTRL line capacitance 50 pF CDATA Data line capacitance 50 pF 1 Data based on design simulation and not tested in production 7 9 2 Universal serial bus interface USB Table 24 DC characteristics Symbol Parameter Conditions Min Typ Max Unit IDDsuspend Suspend current Nara 2 HAPON 60 90 190 pA Rpy Pull up resistor 2 1 5 kQ Full speed mode Vrerm _ Termination voltage 0 8 2 0 V Vou High level output voltage 2 8 3 6 V VoL Low level output voltage 0 8 V Vors Crossover voltage 1 3 2 0 V High speed mode Vusou _ HS data signalling high 400 mV Vso HS data signalling low 5 mV 1 The values provided do not take into account the current through both the
32. rted into a computer Table 29 Ordering information Part mber Package Operating Temperature voltage range ST72681 R20 LQFP48 7x7mm 3 0 to 3 6 V 0 to 70 C ST72681 R21 latest firmware revision LQFP48 7x7mm 3 0to 3 6 V 0 to 70 C ky ST72681 Revision history 10 2 Revision history Table 30 Document revision history Date 27 May 2005 Revision 1 0 Changes Changed status of the document Changed description on 1st page Removed unconnected pins in Table 5 on page 7 Changed Table 4 on page 6 Changed pin 5 description in Table 3 on page 6 Changed section 3 on page 7 Changed Figure 3 on page 8 and Figure 4 18 Nov 2005 2 0 Electrical Characteristics section added Section 4 on page 10 Additional features listed on front page Status of document changed to Datasheet Application schematics modified Figure 4 removed Section 4 6 Memory Characteristics removed VDDOUSB marked as O output in Table 2 on page 6 06 Feb 2006 3 0 Additional features listed on front page Application schematics modified Figure 3 on page 8 Feature comparison table added for R20 firmware update Table 28 Figure 3 on page 8 updated with note added 09 Jan 2007 4 0 Additional features listed on front page related to firmware release R21 Application schematics updated for R21 Figure 3 on page 8 Feature comparison table added for R21 firmware update Table 28 IDD
33. rv cee ee 18 7 2 1 Voltage characteristics saasaa eee eee 18 7 2 2 Current characteristics 0 0 0 0 llli 19 7 2 3 Thermal characteristics llle 19 7 3 Operating conditions cvecds lt tx nes ss eaeaes Reed X RO ESO RR ERE 19 7 3 1 General operating conditions lille 19 7 4 Supply current characteristics 0 00 cece eee 20 7 4 1 RUN and SUSPEND modes sees 20 7 4 2 Supply and clock managers 2 lesse 20 7 5 Clock and timing characteristics llle 20 7 5 1 General timings eh 20 7 5 2 Crystal oscillator s scier es 21 7 6 EMC characteristics vee EE KAANAK RANA NAL HK NAE RR 22 7 6 1 Functional EMS electromagnetic susceptibility 22 7 6 2 Electromagnetic interference EMI eee ences 23 7 6 3 Absolute maximum ratings electrical sensitivity 23 7 7 I O port pin characteristics erae 24 7 7 1 General characteristics ees 24 7 7 2 Output driving current re 25 7 8 Control pin characteristics eee 27 7 8 1 Asynchronous RESET pin eee 27 7 9 Other communication interface characteristics 28 7 9 1 MSCI parallel interface llis 28 7 9 2 Universal serial bus interface USB 0 0 a 29 8 Package mechanical data eee 31 9 Device ordering information eee eee eee 32 10 Revision
34. suspend Values and note updated Table 24 30 Aug 2007 22 Jan 2009 5 0 Updated information in Table 6 Known NAND Flash compatibility guide for R20 and R21 devices on page 10 Added Section 4 2 NAND error correction on page 11 Section 4 3 Management of bad NAND Flash blocks on page 11 Section 4 4 Wear levelling on page 12 and Section 4 5 NAND Flash interface configuration on page 13 Added Section 5 Mass storage implementation on page 14 and Section 6 Human interface implementation on page 16 Added internal clock frequency fcpy value in Table 10 General operating conditions on page 19 Updated datasheet status to not recommended for new design Replaced ST by Numonyx for NAND Flash memories Updated mass storage in Section Features Added Note 2 below Table 6 Removed dynamic latch up in Section 7 6 3 Absolute maximum ratings electrical sensitivity Changed TQFP48 to LQFP48 Updated ECOPACK text in Section 8 Package mechanical data 33 34 ST72681 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible fo
35. ts RRREERE XR ER RRREEE EE 12 4 4 1 LUT Usage Less hes bw ae Yet eGR DLE EP Te XE eS ed 12 4 5 NAND Flash interface configuration llle 13 5 Mass storage implementation leeren 14 5 1 USB Felg 16 ee ctca sexys Yu on DER NG KHA MAKAKA ERESESE E 14 5 2 BOT SCSI implementation esee 14 5 2 1 BOT specification c eee 14 5 2 2 SCSI specification liliis 14 5 2 3 Bootability specification llle 14 5 3 Multi LUN device characteristics ee nn 14 5 3 1 Public driv ye RAE Rr ERR ye Reins hb ALA RU NAG 15 5 3 2 Private drive nn 15 5 3 3 Additional drive n 15 5 3 4 CD ROM considerations llle 15 5 4 Mass storage interface configuration a 15 6 Human interface implementation sss 16 6 1 LED D6NAVIOl Xia AA EMHE OA Lege on UD RAUM Y n erus 16 6 2 Read only switch iuueni dm ER EROR REGERE E SX REGE 16 7 Electrical characteristics lllleesesseee 17 2 34 ky ST72681 Contents 7 1 Parameter conditions iuda s deg E RR cb eeeereeree bak s kene 17 7 1 1 Minimum and maximum values 000 e eee ees 17 7 1 2 Typical values nee 17 7 1 3 Typical curves uessseeeseleesee eee 17 7 1 4 Loading capacitor uuideeku eu ER REG Deeks NATEN RA 17 7 1 5 Pin input voltage 2 04 bucks bees eves EESE c AERE RE X ER XE 18 7 2 Absolute maximum ratings
36. vice over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Table 16 EMC characterization and optimization values Symbol Parameter Conditions rdi V Voltage limits to be applied on any I O Vpp33 3 3 V Ta 25 C fosc 12 MHz 4B FESD pin to induce a functional disturbance complies with IEC 1000 4 2 specifications Fast transient voltage burst limits to be V applied through 100pF on Vpp33 and Vpp33 3 3 V TA 425 2G fosc 12 MHz 4A FFTB Vgs33 pins to induce a functional complies with IEC 1000 4 4 specifications disturbance ST72681 Electrical characteristics 7 6 2 Electromagnetic interference EMI Based on a simple application running on the product toggling 2 LEDs through the I O ports the product is monitored in terms of emission This emission test is in line with the norm SAE J 1752 3 which specifies the board and the loading of each pin Table 17 Electromagnetic interference aaral Monitored Max vs Symbol Parameter Conditions Frequency Band fog 12 MHz Unit 0 1 MHz to 30 MHz 20 Vppas 9 8 V TA 425 C 39 MHz to 130 MHz 25 dByV Semi Peak level complies with SAE J 1752 3 specifications 130 MHz to 1 GHz 25 SAE EMI Level 4 1 Refer to Application Note AN1709 for data on other package types 7 6 3 Absolute maximum ratings
37. y Table 14 Crystal oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fosc Oscillator frequency 12 MHz CKacc _ Total crystal oscillator accuracy abs value temp aging 60 ppm osc Crystal oscillator duty cycle 45 50 55 1 The crystal oscillator duty cycle has to be adjusted through the two C capacitors Refer to the crystal manufacturer for more details Figure 7 Typical application with a crystal oscillator Vppa CL T OSCIN e CRYSTAL CL e AN OSCOUT Device 1 Rsoscout 1 Depending on the crystal oscillator power dissipation a serial resistor R 9s5cout May be added Refer to the crystal oscillator manufacturer for more details Table 15 Typical C and Rs values by crystal oscillator Typical crystal oscillator Cj PF Rsoscout NDK AT51 or AT41 16 560 21 34 Electrical characteristics ST72681 7 6 7 6 1 22 34 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility Based on a simple running application on the product toggling 2 LEDs through I O ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negative is applied on a
Download Pdf Manuals
Related Search
ST ST72681 handbook