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ST ST7SCR1E4 ST7SCR1R4 handbook

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2. 2 Pin description Figure 2 64 LQFP package pinout NC Not Connected Q 8 gt gt aaa CQ LL LL a 222 0722 gt 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49N CRDRST Hie 48 NC H2 47 DP CRDCLK Lj3 46 O DM NC 04 45 O LEDO c4 5 44 L1 PAG O 6 H Vpp c8 O7 42 1 PC7 WAKUP1 GND 41 L1 PC6 WAKUP1 PBo L9 40 PC5 WAKUP1 PB1 O10 39 PCA WAKUP1 2 O 11 1 PB3 12 37 2 1 PB4 13 36 7 PC1 WAKUP1 5 14 35 O PCO WAKUP1 PBe 15 Hl GND PB7 16 O VDD 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 LILLILUUIUIuILHIliu I aoe aoor acosiudorzro lt lt lt lt amp 5 asaaaanonanaoaandvg ATIZAN a e JAQA o 022 Goee quo aod Figure 3 24 SO package pinout DIODEL 1 24 SELF GNDAL_ 2 23 Vpp GND 2217 CRDVCC _ 4 21 USBVcc CRDRST 5 20 DP CRDCLK 6 19 DM C4 7 18 LEDO CRDIO 17 PA6 C8 19 16 Vpp CRDDET 10 15 7 OSCOUT ICCDATA WAKUP2 PA0 7 11 14 OSCIN ICCCLK WAKUP2 PA1 12 18 NC 10 121 Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 Figure 4 24 QFN package pinout Pin description
3. 102 Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 Contents 15 16 17 14 6 Smartcard supply supervisor electrical characteristics 103 14 7 EMC characteristics 2 ikaw ene Rer Rx eee 105 14 7 1 Functional EMS Electro magnetic susceptibility 105 14 7 2 Electro magnetic interference EMI 106 14 7 3 Absolute maximum ratings electrical sensitivity 106 14 8 Communication interface characteristics 107 14 8 1 USB Universal bus interface 107 Package characteristics 109 15 1 Package mechanical data 109 15 2 Recommended reflow oven profile 110 Device configuration and ordering information 111 16 0 1 111 16 1 Device ordering information and transfer of customer code 112 16 2 Development tools 114 16 3 ST Application notes 115 16 4 Important notes 118 16 4 1 Unexpected reset fetch 118 16 4 2 Flash devices 118 16 4 3 Smartcard UART automat
4. 77 INSTTUCHON uu veu ces eee OO CR eed eae ee eae 88 13 1 addressing modes 88 134 4 Inherent sur rre ee eee Wes eee GS 89 19312 Immediate e EIS RE RERO DAE RUE de 90 13 1 3 1 tetos inrter eee eee Cete ddd e e 90 13 1 4 Indexed No Offset Short 90 13 1 5 Indirect Short 90 13 1 6 Indirect indexed Short Long 91 13 1 7 X Relative mode Direct Indirect 92 13 2 Instruction 92 Electrical characteristics 96 14 1 Absolute maximum 5 96 14 2 Recommended operating conditions 97 14 3 Supply and reset characteristics 99 14 4 Clock and timing 5 100 14 4 1 Generaltimings lesser 100 14 4 2 External clock source 100 14 4 8 Crystal resonator oscillators 101 14 5 Memory characteristics 102 14 5 1 and hardware registers 102 14 5 2
5. Table 16 ports register map Address i Register 7 6 5 4 3 2 1 0 Hex label 11 MSB LSB Reset Value 0 0 0 0 0 0 0 0 12 MSB LSB Reset Value 0 0 0 0 0 0 0 0 13 MSB LSB Reset Value 0 0 0 0 0 0 0 0 14 PAPUCR MSB LSB Reset Value 0 0 0 0 0 0 0 0 15 PBDR MSB LSB Reset Value 0 0 0 0 0 0 0 0 16 MSB LSB Reset Value 0 0 0 0 0 0 0 0 ky Doc ID 8951 Rev 6 45 121 ports ST7SCR1E4 ST7SCR1R4 Table 16 ports register map continued Add i ress Register 7 6 5 4 2 1 0 label 17 PBPUCR MSB LSB Reset Value 0 0 0 0 0 0 0 18 LSB Reset Value 0 0 0 0 0 0 0 19 PDDR MSB LSB Reset Value 0 0 0 0 0 0 0 1 MSB LSB Reset Value 0 0 0 0 0 0 0 1B PDPUCR MSB LSB Reset Value 0 0 0 0 0 0 0 46 121 Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 Miscellaneous registers 10 Miscellaneous registers Miscellaneous register 1 MISCR1 Reset Value 0000 0000 00h Read Write 7 0 ITM7 ITM6 ITM5 ITMA ITM3 ITM2 ITM1 ITMO Writing the ITIFREC register enables or disables external interrupt on Port C Each bit can be masked independently The ITMx bit masks the external interrupt on PC x Bits 7 0 ITM 7 0 Interrupt Mask 0 external interrupt disabled 1 external interrupt enabled Miscellaneous register 2 MISCR2 Reset Value 0000 0000 00h Rea
6. 33 7 5 Interrupt register description 34 8 Power saving 37 8 1 Introduction 37 8 2 Wait mode cc teeta 37 8 3 Hall mode acsi A ce sor 38 9 VO DONS tee adora E AD ED a a Riu 40 9 1 Introduction 40 9 2 Functional description 40 9 3 l O port implementation 41 9 3 1 Port Asus rU hee Cee Ba he eae aq aa ERE 41 9 3 2 Ports Band D xu a bei oat d tom t e 42 9 3 3 POM Goal e Gib ores Rede 43 9 4 Register description 43 10 Miscellaneous registers 47 11 LEDS uua dn dnd at oos de wee hn e ob d eee o UR NI E 50 12 On chip peripherals 51 12 1 Watchdog timer WDG 51 12 14 Introduction paeas aai mtaa RR RR ER Rx Rm Rosa 51 12 1 2 lt 51 12 4 3 Functional description 3 51 12 1 4 Software watchdog option 52 12 1 5 Hardware watchdog option
7. C1 C2 C7 and C8 must be located close to the chip Refer to Section 6 Supply reset and clock management and Section 14 4 3 Crystal resonator oscillators Doc ID 8951 Rev 6 15 121 Register and memory map ST7SCR1E4 ST7SCR1R4 3 16 121 Register and memory map As shown in Figure 7 the MCU is capable of addressing 64K bytes of memories and registers The available memory locations consist of 40 bytes of register locations up to 512 bytes of RAM and up to 16K bytes of user program memory The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh The highest address bytes contain the user reset and interrupt vectors IMPORTANT Memory locations noted Reserved must never be accessed Accessing a reserved area can have unpredictable effects on the device Figure 7 Memory map 0000h 003Fh 0040h 023Fh 0240h 033Fh Co00h FFDFh FFEOh FFFFh HW Registers see Table 4 RAM 512 Bytes USB RAM 256 Bytes Unused Program Memory 16K Bytes Interrupt amp Reset Vectors see Table 11 70040h OOFFh 0100h 017Fh 0180h Short Addressing RAM 192 Bytes Stack 128 Bytes 2 16 bit Addressing RAM 192 Bytes Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Register and memory map Table 4 Hardware register memory map
8. 14 6 Smartcard supply supervisor electrical characteristics TA 0 70 C 4 0 lt Vpp Vss lt 5 5V unless otherwise specified Table 35 Smartcard supply supervisor Symbol Parameter Conditions Min Typ Max Unit 5V regulator output for IEC7816 3 Class A Cards Vcnpvcc SmartCard Power Supply Voltage 4 6 5 0 5 5 V Isc SmartCard Supply Current 55 mA lovpet Current Overload Detection 120 mA pantie time on Current 170 1400 lis V Turn off Time torr cce Feu 37 Ci oADmax 4 7uF 750 Us V Turn on Time tON eos Fou re 37 Ci oADmax lt 4 7UF 150 500 us Vomovoo aab above minimum Supply 4 52 0 4760 V Vpp Supply current 2 100 regulator output for IEC7816 3 Class Cards Vcnpvcc SmartCard Power Supply Voltage 2 7 3 0 3 3 V Isc SmartCard Supply Current 50 mA lovpet Current Overload Detection 100 mA TR roa ies time on Current 170 1400 0 is V Turn off Time torr 37 lt 4 7 750 us V Turn on Time ton sco doo 37 lt 4 7UF 150 500 us 1 8V regulator output for IEC7816 3 Class C Cards Vcnpvcc SmartCard Power Supply Voltage 1 65 1 95 V Isc SmartCard Supply Current 20 mA lovper Current Overload Detection 100 0 mA ius o time on Current 1700 14000 us V Turn off Time torr eco 37 Ci oADmax 4 7uF 750 us V Turn on Time tON cee Fee 37 lt 4 7UF 150 500 us Smartcard CLKPin VoL Output Low Level Voltage
9. 29 Interrupt processing flowchart 31 Priority decision process 31 Concurrent interrupt management 33 Nested interrupt management 34 WAIT mode flow chart 2 2 2 52 24 5 5 run 38 HALT mode flow chart cece rr 39 PAO PA1 PA2 PA4 42 PAG eere serani eia wA m mr 42 Port B and D configuration kiet sriti 43 Port C configuration ett 43 Watchdog block diagram 0 52 block diagram 1 m un 54 USB block 57 Endpoint buffer size teens 58 Smartcard interface block 70 Compensation 72 Waiting time counter example 73 Card detection block ee 74 Card deactivation 5 75 Card voltage selection and power OFF block 76 Power off timing diagram
10. 76 Card clock selection block diagram 77 Smartcard I O pin 5 81 Typical application with an external clock 100 Typical application with a crystal resonator 101 Two typical applications with VPP 1 102 USB Data signal rise and 1 107 64 pin low profile quad flat package 14x14 109 24 pin plastic small outline package 300 mil width 109 Sales type coding 112 ST7SCR microcontroller option 114 Revision marking on box label and device 119 Doc ID 8951 Rev 6 7 21 Description ST7SCR1E4 ST7SCR1R4 Description The ST7SCR and ST7FSCR devices are members of the ST7 microcontroller family designed for USB applications All devices are based on a common industry standard 8 bit core featuring an enhanced instruction set The ST7SCR ROM devices are factory programmed and are not reprogrammable The ST7FSCR versions feature dual voltage Flash memory with Flash Programming capability They operate at a 4 MHz external oscillator frequency
11. UART Working Clock 12 H2cy M2cy 2 2 icy cy icy Hoy Htoy 1 1 1 T 1 1 1 1 1 F 372 D 32 Waiting time counter The Waiting Time counter is a 24 bit counter used to generate a timeout signal The elementary time unit counter acts as a prescaler to the Waiting Time counter which is incremented at the etu rate The Waiting Time Counter can be used in both UART mode and Manual mode and acts in different ways depending on the selected mode The CRDWT2 CRDWT1 and CRDWTO are load registers only the counter itself is not directly accessible UART mode The load conditions are either Start bit is detected while UART bit 21 and the WTEN bit 1 or e write access to the CRDWT2 register is performed while the UART bit 1 and the WTEN bit O In this case the Waiting Time counter can be used as a general purpose timer In UART mode if the WTEN bit of the CRDCR register is set the counter is loaded automatically on start bit detection Software can change the time out value on the fly by writing to the CRDWT registers For example in T21 mode software must load the Block Waiting Time BWT time out in the CRDWT registers before the start bit of the last transmitted character Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 On chip peripherals Then after transmission of this last character signalled by the TX
12. OSCIN PA1 NC Cio SHE p values for the external components is C1 47 pF C2 100nF 1 C3 1nF C4 4 7 yF ESR 0 5 Ohm C5 470 pF C6 100 pF 1 5kOhm L1 10 pH 2 Ohm Crystal 4 0 MHz Impedance max100 Ohm CH cio 2 M BAT42 SHOTTKY E 14 121 Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 Pin description Note Note C1 and C2 must be located close to the chip Refer to Section 6 Supply reset and clock management amp Section 14 4 3 Crystal resonator oscillators Figure 6 Smartcard interface reference application 64 Pin LQFP package gm values for the external components Es 3 4 7 uF 1 C1 C6 C8 C E 7A C4 um 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ANOakRWOND 11 48 R 3 D S 45 V i a DD 43 420 41 40 39 38 O C2 C3 C4 C5 100nF 1nF 4 7 yF ESR 0 5 Ohm 470 pF 100 pF C7 100 nF 1 5kOhm L1 10 pH 2 Ohm Crystal 4 0 MHz Impedance max100 Ohm It Cl2 2 BAT42 SHOTTKY 100 nF 1
13. ST7SCR1E4 ST7SCR1R4 8 bit low power full soeed USB MCU with 16 Kbyte Flash 768 byte RAM smartcard interface and timer Features Memories m Up to 16 Kbytes of ROM or High Density Flash HDFlash program memory with read write protection HDFlash In Circuit and In Application Programming 100 write erase cycles guaranteed data retention 40 years at 55 C m Up to 768 bytes of RAM including up to 128 bytes stack and 256 bytes USB buffer Clock reset and supply management m Low voltage reset W 2 power saving modes Halt and Wait modes m PLL for generating 48 MHz USB clock using a 4 MHz crystal Interrupt management m Nested Interrupt controller USB Universal Serial Bus interface 256 byte buffer for full speed bulk control and interrupt transfer types compliant with USB specification version 2 0 m On Chip 3 3V USB voltage regulator and transceivers with software power down m 7 USB endpoints One 8 byte Bidirectional Control Endpoint One 64 byte In Endpoint One 64 byte Out Endpoint Four 8 byte In Endpoints 35 or 4 I O ports m Upto 4 LED outputs with software programmable constant current 3 or 7 mA Datasheet production data LQFP64 14x14 024 QFN24 1507816 3 UART interface m 4 MHz clock generation m Synchronous Asynchronous protocols T 0 T 1 m Automatic retry on parity error m Programmable baud rate from 372 clock pulses up to 11 625 clock pulses
14. STAT_RX1 STAT RXO Meaning 0 0 DISABLED reception transfers cannot be executed 0 1 STALL the endpoint is stalled and all reception requests result in a STALL handshake 1 0 NAK the endpoint is naked and all reception requests result in a NAK handshake 1 1 VALID this endpoint is enabled for reception These bits are written by software but hardware sets the STAT RX bits to NAK when a correct transfer has occurred CTR 1 addressed to this endpoint so the software has the time to examine the received data before acknowledging a new transaction Reception counter register CNTORXR Read Write Reset Value 0000 0000 00h 7 0 0 0 0 0 CNT3 CNT2 CNT1 CNTO This register contains the allocated buffer size for endpoint 0 reception setting the maximum number of bytes the related endpoint can receive with the next OUT or SETUP transaction At the end of a reception the value of this register is the max size decremented by the number of bytes received to determine the number of bytes received the software must subtract the content of this register from the allocated buffer size Transmission counter register CNTOTXR CNT1TXR CNT3TXR CNT4TXR CNT5TXR Read Write Reset Value 0000 0000 00h 7 0 0 0 0 0 CNT3 CNT2 CNT1 CNTO This register contains the number of bytes to be transmitted by Endpoint 0 1 3 4 or 5 at the next IN token addressed to it Recepti
15. lt lt a a a 2 2 9 a o gt gt ne bad bad 24 23 22 21 20 19 CRDVCC 1 181 USBVcc CRDRST 2 17 DP CRDCLK 13 16 DM 77 4 15 LEDO CRDIO 5 144 C8F 76 13 GND 7 8 9 10 11 12 1 t 1 1 t 1 e 2 E Hog g Bg Q N N 8 o tr 2 72 x X o lt lt E lt a o o o 8 Legend Abbreviations Type input O output S supply In Output level CMOS 0 3Vpp 0 7Vpp with input trigger Output level HS 10mA high sink on N buffer only Port and control configuration e Input float floating wou weak pull up int interrupt ana analog e Output OD open PP push pull Refer to ports on page 40 for more details on the software configuration of the I O ports Table 3 Pin description Pin n Level Port Control amp Main x Pin name 5 5 o Input Output function Alternate function m E 2 E 5 a a Miter reset 398 o S 1 2 5 CRDRST Cr X X Smartcard Reset 2 NC Not Connected 3 3 6 CRDCLK Cr X X Smartcard Clock Doc ID 8951 Rev 6 11 121 Pin description ST7SCR1E4 ST7SCR1R4 Table 3 Pin description conti
16. Read Write Reset Value 0000 0000 00h 7 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TBO This register is used to send a byte to the smartcard Smartcard receive buffer CRDRXB Read Reset Value 0000 0000 00h 7 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO This register is used to receive a byte from the smartcard Table 24 Register map and reset values Address i Register 7 6 5 4 3 2 1 0 Hex label CRDCR CRDRS DETCN VCAR VCARD UART WTEN CREP CONV 00 Reset T F D1 0 0 0 0 0 Value 0 0 0 0 CRDSR TXBEF CRDIR IOVF WTF TXCF RXCF PARF 01 Reset 1 0 OK 0 0 0 0 Value 0 0 CRDCCR CLKSEL _ CRDC CRDC4 CRDIO CRDCL CRDRS CRDVC 02 Reset 0 0 8 x T Value 0 0 isi COMP ETU10 ETU9 ETU8 0 0 0 0 0 1 0 0 Value CRDETUO ETU7 ETU6 ETU5 ETU4 ETU3 ETU2 ETU1 ETUO 04 Reset Value 0 1 86 121 Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 On chip peripherals Table 24 Register map and reset values continued Address i Register 7 6 5 4 3 2 1 0 label Nn Se 0 0 0 0 0 0 0 0 Value yon ats GT4 0 0 0 0 1 1 0 0 Value CRDWT2 WT23 WT22 WT21 WT20 WT19 WT18 WT17 WT16 07 Reset 0 0 0 0 0 0 0 0 Value CRDWT1 WT1
17. Address Block Register Register name Remarks label status 0000h CRDCR Smartcard Interface Control Register 001 R W 0001h CRDSR Smartcard Interface Status Register 80h R W 0002h CRDCCR Smartcard Contact Control Register xxh R W 0003h CRDETU1 Smartcard Elementary Time Unit 1 01h R W 0004h CRDETUO Smartcard Elementary Time Unit 0 74h R W 0005h CRDGT1 Smartcard Guard time 1 00h R W 0006h CRD CRDGTO Smartcard Guard time 0 OCh R W 0007h CRDWT2 Smartcard Character Waiting Time 2 00h R W 0008h CRDWT1 Smartcard Character Waiting Time 1 251 R W 0009h CRDWTO Smartcard Character Waiting Time 0 80h R W 000Ah CRDIER Smartcard Interrupt Enable Register 001 R W 000Bh CRDIPR Smartcard Interrupt Pending Register 00h R 000Ch CRDTXB Smartcard Transmit Buffer Register 00h R W 00001 CRDRXB Smartcard Receive Buffer Register 00h R OOOEh Watchdog WDGCR Watchdog Control Register 00h R W 001 1h PADR Port A Data Register 00h R W 0012h Port A PADDR Port A Data Direction Register 00h R W 0013h PAOR Option Register 00h R W 0014h PAPUCR Pull up Control Register 00h R W 0015h PBDR Port B Data Register 00h R W 0016h Port B PBOR Option Register 00h R W 0017h PBPUCR Pull up Control Register 00h R W 0018h Port C PCDR Port C Data Register 00h R W 0019h PDDR Port D Data Register 00h R W 001Ah Port D PDOR Option Register 00h R W 001Bh PDPUCR Pull up Control Register 00h R W 001Ch MISCR1 Miscellaneous Register 1 00h R W 001Dh MISC MISCR2 Miscellaneous Registe
18. Read Write Reset value 0000 0110 06h 7 0 USB_ RSM 0 0 RESUME PDWN FSUSP FRES RST Bit 7 RSM Resume Detected This bit shows when a resume sequence has started on the USB port requesting the USB interface to wake up from suspend state It can be used to determine the cause of an ESUSP event 0 No resume sequence detected on USB 1 Resume sequence detected on USB Bit 6 USB_RST USB Reset detected This bit shows that a reset sequence has started on the USB It can be used to determine the cause of an ESUSP event Reset sequence 0 No reset sequence detected on USB 1 Reset sequence detected on USB Bits 5 4 Reserved forced by hardware to 0 Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 On chip peripherals Note Bit 3 RESUME Resume This bit is set by software to wake up the Host when the ST7 is in suspend mode 0 Resume signal not forced 1 Resume signal forced on the USB bus Software should clear this bit after the appropriate delay Bit 2 PDWN Power down This bit is set by software to turn off the 3 3V on chip voltage regulator that supplies the external pull up resistor and the transceiver 0 Voltage regulator on 1 Voltage regulator off After turning on the voltage regulator software should allow at least 3 us for stabilization of the power supply before using the USB interface Bit 1 FSUSP Force suspend mode This bit is set by software to enter Suspend mode The ST7 shoul
19. Symbol Ratings Value Unit Package thermal resistanceLQFP64 60 024 80 C W QFN24 42 Tine Max junction temperature 150 Targ Storage temperature range 65 to 150 C Power dissipationQFN24 600 PD max 024 i 500 nd 14 2 Recommended operating conditions GENERAL Symbol Parameter Conditions Min Typ Max Unit Supply voltage 4 0 5 5 V fOSC External clock source 4 MHz TA Ambient temperature range 0 70 C Operating conditions T 0 to 70 C unless otherwise specified Table 29 Current injection on i o port and control pins Symbol Parameter Conditions Min Typ Max Unit mes t lings Total positive injected current 1 2 aos 20 mA VeEXTERNAL gt VcRDvcc Smartcard I Os VeEXTERNAL lt Vss linu Total negative injected current 3 Digital pins 20 mA Analog pins Note Positive injection The IINJ is done through protection diodes insulated from the substrate of the die For SmartCard I Os VCRDVCC has to be considered Negative injection The is done through protection diodes NOT INSULATED from the substrate of the die The drawback is a small leakage few induced inside the die when a negative injection is performed This leakage is tolerated by the digital structure but it acts on the analog line according to the impedance versus a leakage current of few pA if the MCU has an AD converter The effect depends on th
20. This mode is fully controlled by user software This allows it to be adapted to the user application user defined strategy for entering programming mode choice of communications protocol used to fetch the data to be stored etc For example it is Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Flash program memory Note 4 6 4 7 possible to download code from the USB interface and program it in the Flash IAP mode can be used to program any of the Flash sectors except Sector 0 which is write erase protected to allow recovery in case errors occur during the programming operation Figure 9 Typical ICP interface PROGRAMMING TOOL ICC CONNECTOR je Cable ICP PROGRAMMING TOOL CONNECTOR HE10 CONNECTOR TYPE 917151311 10 8 6 4 2 APPLICATION BOARD 10kQ t gt B 1 rl OSCIN Vss Vpp ICCCLK ST7 OSCOUT ICCDATA If the ICCCLK or ICCDATA pins are only used as outputs in the application no signal isolation is necessary As soon as the Programming Tool is plugged to the board even if an ICC session is not in progress the ICCCLK and ICCDATA pins are not available for the application If they are used as inputs by the application
21. 97 PME 98 LED PINS ia e Reed E PREX eee eae ete dre a pu rc woe 99 Low voltage detector and supervisor _ 05 99 Typical crystal 101 Dual voltage flash memory 102 Smartcard supply supervisor 103 Absolute maximum 5 106 Electrical sensitivities 107 USB DC electrical 5 107 USB Full speed electrical 5 108 Ordering 113 Development tools 0 nh 114 ST7 Application notes iisssssseseee eR RR mne 115 Device identification 118 Document revision history lesse rr 120 Doc ID 8951 Rev 6 ST7SCR1EA ST7SCR1R4 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure
22. ST7SCR1E4 ST7SCR1R4 Table 27 Instruction set overview continued Mnemo Description paneten Dst Src 1 10 C Example CPL One Complement FFH A reg 1 DEC Decrement dec Y reg HALT Halt 1 0 Interrupt routine Pop CC A X PC H lo C return INC Increment inc X reg M JP Absolute Jump jp TBL w JRA Jump relative always JRT Jump relative JRF Never jump jf JRIH if ext INT pin e INT pin high JRIL dd if ext INT pin Ge INT pin low JRH Jump if H 1 H 1 JRNH Jump if H 0 H 0 JRM Jump if 11 0 11 11 0 11 JRNM Jump if 11 0 lt gt 11 1 0 lt gt 11 JRMI Jump if 1 minus N 1 JRPL Jump if N 0 plus N 0 JREQ Jump 7 1 equal Z 1 JRNE Jump if Z 0 not 2 02 equal JRC Jump if C 1 C 1 JRNC Jump if C 20 C 0 JRULT Jump if C 1 Unsigned lt JRUGE Jump if C 0 EE JRUGT Jump if C Z 0 Unsigned gt 94 121 Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Instruction set Mnemo Description E Dst Src 1 0 2 JRULE Jump if C Z 1 Unsigned lt LD Load dst lt src reg reg N 7 MUL Multiply XA X A A X Y X Y A 0 NEG Negate 2 s compl neg 10 reg M N Z NOP No Operation OR OR operat
23. 2004 2 0 Section 14 2 Clarification of read out protection Added new sales types for ROM versions based on new coding Table and Option List 31 Aug Max value added for Idd WAIT Section 14 2 2005 3 0 Flash memory data retention increased to 40 years Section 14 5 2 Reference made to the Flash Programming Reference Manual for Flash timing values Errata sheet content moved to Section 16 4 Important notes 23 Apr 40 Addition of QFN24 package first page pinouts ordering information updated 2007 Option list updated page 94 Added ST7SCR1E4 ST7SCR1R 4 part numbers in Table 2 Device summary Replaced ST7SCR by ST7SCR1E4 and ST7SCR1R4 root part numbers Changed ST7SCR1U1 xxx to ST7SCR1E4U1 xxx in Table 40 Ordering information 19 Feb Removed recommended reflow oven profile in Section 15 Package 2009 2 characteristics Added details on step up converter for 5 V card supply voltage in Section Power supply management Changed maximum value of Verpvcc to 5 5 V in Section 14 6 Smartcard supply supervisor electrical characteristics Updated option list Added ECOPACK text Updated disclaimer Updated Nested Interrupts NEST lines in Figure 47 ST7SCR microcontroller 04 Jul au 2012 6 option list Added a footnote to ST7MDTS1 EMU2B in Table 41 Development tools 120 121 Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Please Read Carefully Information in this document is provided solely in connection
24. 52 12 1 6 modes 0 c TEETE eee 52 12 1 Interrupts dogs voi wees dera 53 12 1 8 Register description 53 12 2 Time base unit TBU 53 12 2 1 Introd cllon seess se Re ACE AURA 53 12 22 54 12 2 3 Functional description 0 0 0 ee 54 12 2 4 Programming 54 ky Doc ID 8951 Rev 6 3 121 Contents ST7SCR1E4 ST7SCR1R4 13 14 4 121 12 25 Low power modes 55 12 2 6 Interrupts opie 4 Re E 55 12 2 7 Register description 0 000 ee 55 12 3 USB interface USB 56 12 3 4 Introduction eee ea eee ees 56 12 32 Mainfeatures es 56 12 8 3 Functional description 57 12 8 4 Register description 58 12 4 Smartcard interface 69 124 1 Introduction ERR ER 69 1242 Mainfeatures 4 lt 5 es 70 12 4 3 Functional description 70 12 4 4 Register description
25. Oscillator Divider No of Retries RETRY 2 Readout Protection FMP_R Disabled Enabled Date 4 ek ee ee ox ST QNAtUPE 16 2 Development tools Table 41 Development tools Development tool Sales type Remarks Emulator ST7MDTS1 EMU2B Programming Board ST7MDTS1 EPB2 1 ST7MDTS1 EMU2B order code is discontinued 114 121 Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Device configuration and ordering information 16 3 ST7 Application notes Table 42 ST7 Application notes Identification Description Application Examples AN1658 Serial Numbering Implementation AN1720 Managing the Read out Protection in Flash Microcontrollers AN1755 A High Resolution precision Thermometer Using ST7 and NE555 AN1756 Choosing a DALI Implementation Strategy with ST7DALI AN1812 A High Precision Low Cost Single Supply ADC for Positive and Negative Input Voltages Example Drivers AN 969 SCI Communication Between ST7 and PC AN 970 SPI Communication Between ST7 and EEPROM AN 971 2 Communication Between ST7 M24Cxx EEPROM AN 972 ST7 Software SPI Master Communication AN 973 SCI Software Communication with a PC Using ST72251 16 Bit Timer AN 974 Real Time Clock with ST7 Timer Output Compare AN 976 Driving a Buzzer Through ST7 Timer PWM Function AN 979 Driving an Analog Keyboard with the ST7 ADC AN 980 ST7 Keypad
26. 10 8 ETU value in card clock cycles Writing CRDETU1 register reloads the ETU counter CRDETUO Read Write Reset Value 0111 0100 74h 7 0 ETU7 ETU6 ETU5 ETU4 ETU3 ETU2 ETU1 ETUO Bits 7 0 ETU 7 0 ETU value in card clock cycles The value of ETU 10 0 must in the range 12 to 2047 To write 2048 clear all the bits Guardtime register CRDGTx CRDGT1 Read Write Reset Value 0000 0000 00h 7 0 0 0 0 0 0 0 0 GT8 CRDGTO Read Write Reset Value 0000 1100 7 0 GT7 GT6 GT5 GT4 GT3 GT2 GT1 GTO Software writes the Guardtime value in this register The value is loaded at the end of the current Guard period GT Guard Time Minimum time between two consecutive start bits in transmission mode Value expressed in Elementary Time Units from 11 to 511 The Guardtime between the last byte received from the card and the next byte transmitted by the reader must be handled by software Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 On chip peripherals Note Note Character waiting time register CRDWTx CRDWT2 Read Write Reset Value 0000 0000 00h 7 0 WT WT WT WT WT WT WT ads 22 21 20 19 18 17 16 CRDWT1 Read Write Reset Value 0010 0101 25h 7 0 WT WT WT WT WT WT WT9 WT8 15 14 13 12 11 10 CRDWTO Read Write Reset Value 1000 0000 80h
27. Endpoint 2 Buffer IN 64 Bytes Endpoint 3 Buffer IN 8 Bytes Endpoint 4 Buffer IN 8 Bytes Endpoint 5 Buffer IN 8 Bytes Register description Interrupt status register USBISTR Read Write Reset Value 0000 0000 00h 7 0 CTR 0 SOVR ERROR SUSP ESUSP RESET SOF These bits cannot be set by software When an interrupt occurs these bits are set by hardware Software must read them to determine the interrupt type and clear them after servicing The CTR bit which is an OR of all the endpoint CTR flags cannot be cleared directly only by clearing the CTR flags in the Endpoint registers Bit 7 CTR Correct Transfer This bit is set by hardware when a correct transfer operation is performed This bit is an OR of all CTR flags CTRO in the EPOR register and CTR_RX and CTR_TX in the EPnRXR and EPnTXR registers By looking in the USBSR register the type of transfer can be determined from the PID 1 0 bits for Endpoint 0 For the other Endpoints the Endpoint number on which the transfer was made is identified by the EP 1 0 bits and the type of transfer by the IN OUT bit 0 No Correct Transfer detected 1 Correct Transfer detected A transfer where the device sent a NAK or STALL handshake is considered not correct the host only sends ACK handshakes A transfer is considered correct if there are no errors in the PID and CRC fields if the DATAO DATA1 PID is sent as expected if there were no data overr
28. wrong packet timeout error These bits are set by hardware when an error interrupt occurs and are reset automatically when the error bit USBISTR bit 4 is cleared by software Endpoint 0 register EPOR Read Write Reset value 0000 0000 00h 7 0 STAT_ STAT STAT STAT CTRO DTOG TX T TXO 0 DTOG RX BX1 This register is used for controlling Endpoint 0 Bits 6 4 and bits 2 0 are also reset by a USB reset either received from the USB or forced through the FRES bit in USBCTLR Bit 7 CTRO Correct Transfer This bit is set by hardware when a correct transfer operation is performed on Endpoint 0 This bit must be cleared after the corresponding interrupt has been serviced 0 No CTR on Endpoint 0 1 Correct transfer on Endpoint 0 Doc ID 8951 Rev 6 63 121 On chip peripherals ST7SCR1E4 ST7SCR1R4 Bit 6 DTOG_TX Data Toggle for transmission transfers It contains the required value of the toggle bit OZDATAO 1 DATA1 for the next transmitted data packet This bit is set by hardware on reception of a SETUP PID DTOG TX toggles only when the transmitter has received the ACK signal from the USB host DTOG TX and also DTOG RX are normally updated by hardware on receipt of a relevant PID They can be also written by the user both for testing purposes and to force a specific DATAO or DATA1 token Bits 5 4 STAT TX 1 0 Status bits for transmission transfers These bits contain the informa
29. 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 ky ST7SCR block diagram 9 64 pin LQFP package pinout 10 24 Pin SO package 10 24 lead QFN package 11 Smartcard interface reference application 24 SO package 14 Smartcard interface reference application 64 LQFP 15 Memory eee ee Re E 16 Memory map and sector 55 20 Typical ICP 21 CPUlregiSters tb nerit Ala al ue aden aoe 24 Stack manipulation 26 Clock reset and supply block 27 External clock source 28 Crystal resonator ccc lehren 28 LYD RESET 0 cece hh 29 Watchdog RESET sequence
30. 40 I OSCINH oSCIN high or low time 1 15 tw OSCINL ns OSCIN OSCIN rise or fall time 1 15 tOSCIN IL OSCx Input leakage current Vss lt Vin lt Vpp 1 pA 1 Data based on design simulation and or technology characteristics not tested in production 100 121 Figure 40 Typical application with an external clock source 90 VosciNH 10 a VosciNLE 5 1 51 Lg tosciN tosciN tw OSCINH tw OSCINL OSCOUT fosc EXTERNAL CLOCK SOURCE OSCIN L gt ST7XXX Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Electrical characteristics 14 4 3 Crystal resonator oscillators The ST7 internal clock is supplied with one Crystal resonator oscillator All the information given in this paragraph are based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start up stabilization time Refer to the crystal resonator manufacturer for more details frequency package Symbol Parameter Conditions Min Typ Max Unit fosc Oscillator Frequency 1 MP Medium power oscillator 4 MHz Re Feedback resistor 90 15
31. 7 0 WT7 WT6 WT5 WT4 WT3 WT2 WT1 WTO WT Character waiting time value expressed ETU 0 16777215 The CRDWTO CRDWT1 and CRDWT2 registers hold the load value of the Waiting Time counter A read operation does not return the counter value This counter can be used as a general purpose timer If the WTEN bit of the CRDCR register is reset the counter is reloaded when a write access in the CRDWT2 register occurs It starts when the WTEN bit is set If the WTEN bit in the CRDCR register is set and if UART mode is activated the counter acts as an autoreload timer The timer is reloaded when a start bit is sent or detected An interrupt is generated if the timer overflows between two consecutive start bits When loaded with a 0 value the Waiting Time counter stays at 0 and the WTF bit 1 Smartcard interrupt enable register CRDIER Read Write Reset Value 0000 0000 00h 7 0 TXBEM IOVFM VCRDM WTM TXCM RXCM PARM Doc ID 8951 Rev 6 83 121 On chip peripherals ST7SCR1E4 ST7SCR1R4 84 121 Bit 7 TXBEM Transmit buffer empty interrupt mask This bit is set and cleared by software to enable or disable the TXBE interrupt 0 TXBE interrupt disabled 1 TXBE interrupt enabled Bit 6 Reserved Bit 5 IOVFM Card Overload Current Interrupt Mask This bit is set and cleared by software to enable or disable the IOVF interrupt 0 IOVF interrupt disabled
32. ALTERNATE ENABLE ALTERNATE 1 1 OUTPUT P BUFFER of DES PULL UP 1 m g LATCH i E ALTERNATE ENABLE OM LATCH PULL_UP LATCH 6 4 E N BUFFER DIODES DR SEL ALTERNATE ENABLE 4 Vss V Note 1 selectable by PAPUCR register 9 3 3 Port C Table 15 Port C description PORTC Input PC 7 0 with pull up Figure 26 Port C configuration Vop PULL UP T DR SEL A 3 2 E M HM CMOS SCHMITT TRIGGER L DIODES lt ALTERNATE INPUT 9 4 Register description Data registers PxDR Port A Data Register PADR 0011h Port B Data Register PBDR 0015h Port C Data Register PCDR 0018h ky Doc ID 8951 Rev 6 43 121 ports ST7SCR1E4 ST7SCR1R4 44 121 Port D Data Register PCDR 0019h Read Write Reset Value Port A 0000 0000 Reset Value Port B 0000 0000 Reset Value Port C 0000 0000 00h Reset Value Port 0000 0000 00h 7 0 07 06 05 04 03 02 D1 DO 00h 00h Bits 7 0 D 7 0 Data Register 8 bits The DR register has a specific behavior according to the selected input output configuration Writing the DR register is always taken in account even if the pin is configured as an input Reading the DR register returns either the DR register latch content pin configured as output or the digital value applied to the I O pin pin configured as input DATA DIRECTION REGISTER PA
33. AN 986 Using the Indirect Addressing Mode with ST7 AN 987 ST7 Serial Test Controller Programming AN 988 Starting with ST7 Assembly Tool Chain AN1039 ST7 Math Utility Routines AN1071 Half Duplex USB to Serial Bridge Using the ST72611 USB Microcontroller AN1106 Translating Assembly Code from 5 ST7 AN1179 Programming ST7 Flash Microcontrollers in Remote ISP Mode In situ Programming AN1446 Using the ST72521 Emulator to Debug an ST72324 Target Application AN1477 Emulated Data EEPROM with Xflash Memory AN1527 Developing a USB Smartcard Reader with ST7SCR AN1575 On Board Programming Methods for XFLASH and HDFLASH ST7 MCUs AN1576 In application Programming IAP Drivers for ST7 HDFLASH or XFLASH MCUs AN1577 Device Firmware Upgrade DFU Implementation for ST7 USB Applications AN1601 Software Implementation for ST7DALI EVAL AN1603 Using the ST7 USB Device Firmware Upgrade Development Kit DFU DK AN1635 ST7 Customer ROM Code Release Information AN1754 Data Logging Program for Testing ST7 Applications via ICC ky Doc ID 8951 Rev 6 117 121 Device configuration and ordering information ST7SCR1E4 ST7SCR1R4 Table 42 ST7 Application notes continued Identification Description AN1796 Field Updates for FLASH Based ST7 Applications Using a PC Comm Port AN1900 Hardware Implementation for ST7DALI EVAL AN1904 ST7MC Three phase AC Induction Motor Control Software Library AN1905 ST7MC Three phase
34. BLDC Motor Control Software Library System Optimization AN1711 Software Techniques for Compensating ST7 ADC Errors AN1827 Implementation of SIGMA DELTA ADC with ST7FLITE05 09 AN2009 PWM Management for 3 Phase BLDC Motor Drives Using the ST7FMC AN2030 Back EMF Detection During PWM On Time by ST7MC 16 4 Important notes 16 4 1 Unexpected reset fetch If an interrupt request occurs while a POP CC instruction is executed the interrupt controller does not recognise the source of the interrupt and by default passes the RESET vector address to the CPU Workaround To solve this issue a POP CC instruction must always be preceded by a SIM instruction 16 4 2 Flash devices only The behavior described in the following section Section 16 4 3 is present on Rev W ST7FSCR devices only They are identifiable e onthe device package by the last letter of the Trace Code marked on the device package e onthe box by the last 3 digits of the Internal Sales Type printed in the box label Table 43 Device identification Trace code marked on device Internal sales type on box label 7FSCR1R4T1 U6 7 Flash Devices XXXXXXXXX 7FSCR1E4M1 U6 See also Figure 48 118 121 Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 Device configuration and ordering information 16 4 3 Smart card UART automatic repetition and retry A functional limitation affects the Smart Card UART automatic repetition and r
35. Bit 1 CREP Automatic character repetition in case of parity error 0 In reception mode no parity error signal indication no retry on parity error In transmission mode no error signal processing No retransmission of a refused character on parity error 1 Automatic parity management In transmission mode up to 4 character repetitions on parity error In reception mode up to 4 retries are made on parity error The PARF parity error flag is set by hardware if a parity error is detected If the transmitted character is refused the PARF bit is set but the TXCF bit is reset and an interrupt is generated if the PARM bit is set If CREP 1 the flag is set at the 5th error after 4 character repetitions or 4 retries If CREP 0 the PARF bit is set after the first parity error Bit 0 CONV SO convention selection 0 Direct convention the BO bit LSB is sent first 1 is a level 1 on the Card I O pin the parity bit is added after the B7 bit 1 Inverse convention the B7 bit MSB is sent first a 1 is a level 0 on Card I O pin the parity bit is added after the BO bit To detect the convention used by any card apply the following rule If a card uses the convention selected by the reader an RXC event occurs at answer to reset Otherwise a parity error also occurs Smartcard interface status register CRDSR Read only Read Write on some bits Reset Value 1000 0000 80h 7 0 TXBEF pis IOVF eiu WTF TXC
36. CPU registers ACCUMULATOR RESET VALUE XXh X INDEX REGISTER RESET VALUE XXh Y INDEX REGISTER RESET VALUE XXh 15 PCH 817 PCL 0 PROGRAM COUNTER RESET VALUE RESET VECTOR FFFEh FFFFh 7 0 1 1 11 Hy 10 RESET VALUE 1 1 1 X 1 X X X 0 2 N CONDITION CODE REGISTER 15 8r STACK POINTER RESET VALUE STACK HIGHER ADDRESS X Undefined Value Condition code register CC Read Write Reset Value 111x1xxx 7 0 1 1 11 10 2 The 8 bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed This register can also be handled by the PUSH and POP instructions These bits can be individually tested and or controlled by specific instructions Arithmetic management bits Bit 4 H Half carry This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions It is reset by hardware during the same instructions 0 No half carry has occurred 1 A half carry has occurred This bit is tested using the JRH or JRNH instruction The H bit is useful in BCD arithmetic subroutines Bit 2 N Negative This bit is set and cleared by hardware It is representative of the result sign of the last arithmeti
37. D 32 F 372 m Card Insertion Removal Detection Smartcard power supply m Selectable card Voc 1 8V and 5V m Internal step up converter for 5V supplied Smartcards with a current of up to 55mA using only two external components m Programmable Smartcard Internal Voltage Regulator 1 8V to 3 0V with current overload protection and 4 KV ESD protection Human Body Model for all Smartcard Interface I Os One 8 bit timer m Time Base Unit TBU for generating periodic interrupts Development tools m Full hardware software development package ECOPACK packages Table 1 Device summary W 2 General purpose I Os programmable as interrupts Reference Part number m Up to 8 line inputs programmable as interrupts ST7SCR1R4 ST7FSCR1T1 ST7SCR1T1 m Up to 20 outputs ST7FSCRIM1 ST7SCR1M1 m 1 line assigned by default as static input after ST7SCR1U1 reset July 2012 Doc ID 8951 Rev 6 1 121 This is information on a product in full production www st com Contents ST7SCR1E4 ST7SCR1R4 Contents 1 inn i i awa a 8 2 Pin description a a CORR RC a CN US CR Ra RC UE 10 3 Register and memory map 16 4 Flash program memory 19 4 1 Introduction 19 4 2 Main features 19 4 3 cgi eseun c
38. Decoding Techniques Implementing Wake Up on Keystroke AN1017 Using the ST7 Universal Serial Bus Microcontroller AN1041 Using ST7 PWM Signal to Generate Analog Output AN1042 ST7 Routine for 2 Slave Mode Management AN1044 Multiple Interrupt Sources Management for ST7 MCUs AN1045 ST7 S W Implementation of Bus Master AN1046 UART Emulation Software AN1047 Managing Reception Errors with the ST7 SCI Peripherals AN1048 ST7 Software LCD Driver AN1078 PWM Duty Cycle Switch Implementing True 0 amp 100 Duty Cycle AN1082 Description of the ST72141 Motor Control Peripherals Registers AN1083 ST72141 BLDC Motor Control Software and Flowchart Example AN1105 ST7 pCAN Peripheral Driver AN1129 PWM Management for BLDC Motor Drives Using the ST72141 AN1130 An Introduction to Sensorless Brushless DC Motor Drive Applications with the ST72141 AN1148 Using the ST7263 for Designing a USB Mouse AN1149 Handling Suspend Mode on a USB Mouse AN1180 Using the ST7263 Kit to Implement a USB Game Pad ky Doc ID 8951 Rev 6 115 121 Device configuration and ordering information ST7SCR1E4 ST7SCR1R4 Table 42 ST7 Application notes continued Identification Description AN1276 BLDC Motor Start Routine for the ST72141 Microcontroller AN1321 Using the ST72141 Motor Control MCU in Sensor Mode AN1325 Using the ST7 US
39. Nested or concurrent interrupt management with flexible interrupt priority and level management Upto 4 software programmable nesting levels Upto 16 interrupt vectors fixed by hardware non maskable events RESET TRAP TLI This interrupt management is based on e Bit5and bit 3 of the CPU CC register 11 0 e Interrupt software priority registers ISPRX e Fixed interrupt vector addresses located at the high addresses of the memory map FFEOh to FFFFh sorted by hardware priority order This enhanced interrupt controller guarantees full upward compatibility with the standard not nested CPU interrupt controller Masking and processing flow The interrupt masking is managed by the 11 and 10 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector see Table 7 The processing flow is shown in Figure 17 When an interrupt request has to be serviced e Normal processing is suspended at the end of the current instruction execution e The PC X A and CC registers are saved onto the stack e 11 and l0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector e ThePC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched refer to Interrupt Mapping table for vector addresses The interrupt service routi
40. PENDING INTERRUPTS Different SOFTWARE PRIORITY HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED When an interrupt request is not serviced immediately it is latched and then processed when its software priority combined with the hardware priority becomes the highest one Doc ID 8951 Rev 6 31 121 Interrupts ST7SCR1E4 ST7SCR1R4 Note The hardware priority is exclusive while the software one is not This allows the previous process to succeed with only one interrupt RESET TRAP and TLI can be considered as having the highest software priority in the decision process Different interrupt vector sources Two interrupt source types are managed by the CPU interrupt controller the non maskable type RESET TLI TRAP and the maskable type external or from internal peripherals Non maskable sources These sources are processed regardless of the state of the 11 and 10 bits of the CC register see Figure 17 After stacking the PC X A and CC registers except for RESET the corresponding vector is loaded in the PC register and the 11 and 10 bits of the CC are set to disable interrupts level 3 These sources allow the processor to exit HALT mode e Top Level Hardware Interrupt This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin Caution TRAP instruction must not be used in a TLI service routine e TRAP Non M
41. ST7SCR1R4 ports Note Note 9 3 9 3 1 Output Mode The pin is configured in output mode by setting the corresponding DDR register bit see Table 7 In this mode writing 0 or 1 to the DR register applies this digital value to the I O pin through the latch Then reading the DR register returns the previously stored value In this mode the interrupt function is disabled Digital Alternate Function When an on chip peripheral is configured to use a pin the alternate function is automatically selected This alternate function takes priority over standard I O programming When the signal is coming from an on chip peripheral the I O pin is automatically configured in output mode push pull or open drain according to the peripheral When the signal is going to an on chip peripheral the I O pin has to be configured in input mode In this case the pin s state is also digitally readable by addressing the DR register Input pull up configuration can cause an unexpected value at the input of the alternate peripheral input When the on chip peripheral uses a pin as input and output this pin must be configured as an input DDR 0 Warning The alternate function must not be activated as long as the pin is configured as input with interrupt in order to avoid generating spurious interrupts port implementation The hardware implementation on each I O port depends on the settings in the DDR register and
42. Short circuit to Ground 15 mA 1 Guaranteed by design 2 Vpp 4 75 V Card consumption 55mA CRDCLK frequency 4MHz LED with a 3mA current USB in reception mode and CPU WFI mode 3 Data based on characterization results not tested in production 104 121 Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Electrical characteristics 14 7 14 7 1 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS Electro magnetic susceptibility Based on a simple running application on the product toggling 2 LEDs through ports the product is stressed by two electro magnetic events until a failure occurs indicated by the LEDs e ESD Electro Static Discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 1000 4 2 standard e FTB A Burst of Fast Transient voltage positive and negative is applied to Vpp and Vss through a 100pF capacitor until a functional disturbance occurs This test conforms with the IEC 1000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environm
43. addressing modes only CLR CPL NEG BSET BRES BTJT BTJF INC DEC RLC RRC SLL SRL SRA SWAP The ST7 Assembler optimizes the use of long and short addressing modes Table 25 CPU addressing mode overview Mode Syntax Destination Pointer Pointer size Length address Hex bytes Inherent nop 0 Immediate Id A 55 1 Short Direct Id A 10 00 FF 1 Long Direct Id A 1000 0000 FFFF 2 No Offset Direct Indexed Id A X 00 FF 0 Short Direct Indexed Id A 10 X 00 1FE 1 Long Direct Indexed 14 A 1000 X 0000 FFFF 2 Short Indirect Id A 10 00 FF 00 FF byte 2 Long Indirect Id A 10 w 0000 FFFF 00 FF word 2 Short Indirect Indexed Id A 10 X 00 1FE 00 FF byte 2 Long Indirect Indexed Id A 10 w X 0000 FFFF 00 FF word 2 88 121 Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 Instruction set Table 25 CPU addressing mode overview continued Mode Syntax Destination Pointer Pointer size Length address Hex bytes Relative Indirect jrne 10 PC 127 00 FF byte 2 Bit Direct bset 10 7 00 FF 1 Bit Indirect bset 10 7 00 FF 00 FF byte 2 Bit Direct Relative btjt 10 7 skip 00 FF 2 Bit Indirect Relative btjt 10 7 skip 00 FF 00 FF byte 3 13 1 1 Inherent 4 All Inherent instructions consist of a single byte The opcode fully specifies all the required information for the CPU to process the operation Inherent i
44. always set When a character is received with a parity error the PARF bit is also set Smartcard contact control register CRDCCR Read Write Reset Value 00xx xx00 xxh 7 0 pex CRDCLK CRDRST CRD VCC To modify the content of this register the LD instruction must be used do not use the BSET and BRES instructions Bit 7 CLKSEL Card clock selection This bit is set and cleared by software 0 The signal on the CRDCLK pin is a copy of the CRDCLK bit 1 The signal on the CRDCLK pin is a 4MHz frequency clock To start the clock at a known level the CRDCLK bit should be changed before the CLKSEL bit Bit 6 Reserved must be kept cleared Bit 5 CRDC8 CRDC8 pin control Reading this bit returns the value present on the CRDC8 pin Writing this bit outputs the bit value on the pin Bit 4 CRDC4 CRDC4 pin control Reading this bit returns the value present on the CRDC4 pin Writing this bit outputs the bit value on the pin Bit CHDIO pin control This bit is active only if the UART bit in the CRDCR Register is reset Reading this bit returns the value present on the CRDIO pin If the UART bit is reset e Writing 0 forces a low level on the CRDIO pin e Writing 1 forces the CRDIO pin to open drain Hi Z Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 On chip peripherals Note Bit 2 CRDCLK CRDCLK pin control
45. interrupt The loaded value is given by the corresponding bits in the interrupt software priority registers IXSPR They can be also set cleared by software with the RIM SIM IRET HALT WFI and PUSH POP instructions See the interrupt management chapter for more details Stack Pointer SP Read Write Reset Value 017Fh 15 8 0 0 0 0 0 0 0 1 7 0 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SPO The Stack Pointer is a 16 bit register which is always pointing to the next free location in the stack It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack see Figure 11 Doc ID 8951 Rev 6 25 121 Central processing unit ST7SCR1E4 ST7SCR1R4 Note 26 121 Since the stack is 256 bytes deep the 8 most significant bits are forced by hardware Following an MCU Reset or after a Reset Stack Pointer instruction RSP the Stack Pointer contains its reset value the SP7 to SPO bits are set which is the stack higher address The least significant byte of the Stack Pointer called S can be directly accessed by a LD instruction When the lower limit is exceeded the Stack Pointer wraps around to the stack upper limit without indicating the stack overflow The previously stored information is then overwritten and therefore lost The stack also wraps in case of an underflow The stack is used to save the return address during a subroutine call and the
46. is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register The clearing sequence resets the internal latch A pending interrupt i e waiting for being serviced will therefore be lost if the clear sequence is executed Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Interrupts 7 3 Note 7 4 Interrupts and low power modes All interrupts allow the processor to exit the WAIT low power mode On the contrary only external and other specified interrupts allow the processor to exit from the HALT modes see column Exit from HALT in Interrupt Mapping table When several pending interrupts are present while exiting HALT mode the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 18 If an interrupt that is not able to Exit from HALT mode is pending with the highest priority when exiting HALT mode this interrupt is serviced after the first one serviced Concurrent and nested management The following Figure 19 and Figure 20 show two different interrupt management modes The first is called concurrent mode and does not allow an interrupt to be interrupted unlike the nested mode in Figure 20 The interrupt hardware prior
47. level voltage Vpp 5V 0 3XVp5 V Vin Input high level voltage Vpp 5V Mu D Wave un trigger voltage hysteresis 400 mV V Output low level voltage I 5mA 1 3 OL for Standard port pins I 2mA 0 4 Vou Output high level voltage gt IL Input leakage current Vss lt Vpin lt Vpp 1 Rpy Pull up equivalent resistor 50 90 170 KO Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Electrical characteristics Table 30 port pins continued Symbol Parameter Conditions Min Typ Max Unit Output high to low level fall time tour 07 high sink I O port pins Port D 6 8 13 Output high to low level fall time ton for port pins Port A 5 18 23 ns or C 2 toy Output L H rise time Port D 2 7 9 14 Output L H rise time for standard 19 28 OLH port pins Port A B or C 2 External interrupt pulse time 1 tepu Note Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested Guaranteed by design not tested in production Table 31 LED pins Symbol Parameter Conditions Min Typ Max Unit IL sink Low current gt 2 4 2 4 gt 2 4 for ROM device 5 6 8 4 mA li si High current E Lsink 9 Vpad gt 2 4 for FLASH 5 7 84 device 14 3 Supply and reset characteristics T 0 to 7
48. specific feature of the I O port such as true open drain Port A Table 13 Port A description 1 O PORTA Input Output PA B 0 without pull up push pull or open drain with software selectable pull up without pull up Reset State Doc ID 8951 Rev 6 41 21 ports ST7SCR1E4 ST7SCR1R4 Figure 23 PA1 PA2 PA4 configuration ALTERNATE 1 ALTERNATE ENABLE T DD OUTPUT 0 D P BUFFER DR 1 9 aat d PULL UP E ALTERNATE ENABLE L g DDR j LN o LATCH PAD DDR SEL A J D e REEL 1 DIODES ALTERNATE ENABLE m 0 dis E INPUT CMOS SCHMITT TRIGGER Note 1 selectable by PAPUCR register Figure 24 PA6 configuration Vpp 5 DRSEL Tx gt 2 41 lt PAD CMOS SCHMITT TRIGGER E 9 3 2 Ports B and D Table 14 Port B and D description PORTS B ANDD Output PB 7 0 push pull or open drain with software selectable pull up PD 7 0 42 121 Reset State open drain Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 ports Figure 25 Port B and D configuration
49. supply the 5 V card voltage To enable the step up converter the user must turn on the PLL by setting the PLL_ON bit in the MISCR4 register The step up converter switching frequency is then of 750 kHz fosc 4 MHz Current Overload Detection and Card Removal For each voltage when an overload current is detected refer to section 12 4 on page 69 or when a card is removed the CRDVCC power supply output is directly connected to ground driving modes Smartcard I Os are driven in two principal modes e UART mode i e when the UART bit of the CRDCR register is set e Manual mode driven directly by software using the Smartcard Contact register i e when the UART bit of the CRDCR register is reset Card power on activation must driven by software Card deactivation is handled automatically by the Power off functional state machine hardware UART mode Two registers are connected to the UART shift register CRDTXB for transmission and CRDRXB for reception They act as buffers to off load the CPU A parity checker and generator is coupled to the shifter Character repetition and retry are supported The UART is in reception mode by default and switches automatically to transmission mode when a byte is written in the buffer Priority is given to transmission Elementary Time Unit Counter This 11 bit counter controls the working frequency of the UART The operating frequency of the clock is the same as the card clock fr
50. the microcontroller must be switched to ICC In Circuit Communication mode by an external controller or programming tool Depending on the ICP code downloaded in RAM Flash memory programming can be fully customized number of bytes to program program locations or selection serial communication interface for downloading When using an STMicroelectronics or third party programming tool that supports ICP and the specific microcontroller device the user needs only to implement the ICP hardware interface on the application board see Figure 9 For more details on the pin locations refer to the device pinout description ICP needs six signals to be connected to the programming tool These signals are Vss device power supply ground Vpp for reset by LVD OSCIN to force the clock during power up ICCCLK ICC output serial clock pin ICCDATA ICC input serial data pin Vpp ICC mode selection and programming voltage If ICCCLK or ICCDATA are used for other purposes in the application a serial resistor has to be implemented to avoid a conflict in case one of the other devices forces the signal level To develop a custom programming tool refer to the ST7 FLASH Programming and ICC Reference Manual which gives full details on the ICC protocol hardware and software IAP In application programming This mode uses a BootLoader program previously stored in Sector 0 by the user in ICP mode or by plugging the device in a programming tool
51. 0 Recommended load See Table 6 Cia capacitances versus C equivalent serial resistance kr d MHZ rati MP oscillator 22 56 pF L2 ofthe crystal resonator Re resonator on page 28 5 a Vpp 5V lo OSCOUT driving current MP oscillator 1 5 3 5 mA Vin Vss 1 The oscillator selection can be optimized in terms of supply current using an high quality resonator with small Rg value Refer to crystal resona manufacturer for more details Table 33 Typical crystal resonator t Oscil Reference Freq Characteristic 1 zd pr pF pF ms x 5 JAUCH m Aosc LsS0ppmossc s S0ppmara TYP 33 33 7 10 S 1 Resonator characteristics given by the crystal resonator manufacturer 2 from to 5V lt 50 5 Figure 41 Typical application with a crystal resonator WHEN RESONATOR WITH INTEGRATED CAPACITORS Ca OSCIN RESONATOR TE Cio T OSCOUT 4 ST7XXX tsu osc S the typical oscillator start up time measured between Vpp 2 8V and the fetch of the first instruction with a quick ramp up Doc ID 8951 Rev 6 101 121 Electrical characteristics ST7SCR1E4 ST7SCR1R4 14 5 Memory characteristics Subject to general operating conditions for Vpp fo
52. 0 C Vss 5 5V unless otherwise specified Table 32 Low voltage detector and supervisor LVDS Symbol Parameter Conditions Min Typ Max Unit Reset release threshold Vite rising 3 7 3 9 V Reset generation threshold Vir Won falling 3 3 3 5 V Hysteresis Vir Vit 200 mV Vipon Vpp tise time rate 20 ms V Note Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested Doc ID 8951 Rev 6 99 121 Electrical characteristics ST7SCR1E4 ST7SCR1R4 14 4 Clock and timing characteristics 14 4 1 General timings Operating conditions T 0 to 70 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit i 2 3 12 topu Instruction cycle time ome fopy 4MHz 500 750 3000 ns i Interrupt reaction time 2 10 22 tepu IT VID 10 fopy 4MHz 2 5 5 5 us 1 Data based on typical application software 2 Time measured between interrupt event and interrupt vector fetch is the number of topy cycles needed to finish the current instruction execution Atinst is the number of to finish the current instruction execution 14 4 2 External clock source Symbol Parameter Conditions Min Typ Max Unit VosciNH OSCIN input pin high level voltage BND Vpp D V VosciNL OSCIN input pin low level voltage Vss D see Figure
53. 00h R W 0037h ITSPRO Interrupt Software Priority Register O FFh R W 0038h ITC ITSPR1 Interrupt Software Priority Register 1 FFh R W 0039h ITSPR2 Interrupt Software Priority Register 2 FFh R W 003Ah ITSPR3 Interrupt Software Priority Register 3 FFh R W 003Eh LED CTRL LED Control Register 00h R W Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Flash program memory 4 4 1 4 2 4 3 Flash program memory Introduction The ST7 dual voltage High Density Flash HDFlash is a non volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte by Byte basis using an external Vpp supply The HDFlash devices can be programmed and erased off board plugged in a programming tool or on board using ICP In Circuit Programming or IAP In Application Programming The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors Main features e Three Flash programming modes Insertion in a programming tool In this mode all sectors including option bytes can be programmed or erased ICP In Circuit Programming In this mode all sectors including option bytes can be programmed or erased without removing the device from the application board AP In Application Programming In this mode all sectors except Sector 0 can be programmed or erased without removing the device from the application boa
54. 1 IOVF interrupt enabled Bit 4 VCRDM Card Voltage Error Interrupt Mask This bit is set and cleared by software to enable or disable the VCRD interrupt 0 VCRD interrupt disabled 1 VCRD interrupt enabled Bit 3 WTM Waiting Timer Interrupt Mask This bit is set and cleared by software to enable or disable the Waiting Timer overflow interrupt 0 WT interrupt disabled 1 WT interrupt enabled Bit 2 TXCM Transmitted Character Interrupt Mask This bit is set and cleared by software to enable or disable the TXC interrupt 0 TXC interrupt disabled 1 TXC interrupt enabled Bit 1 RXCM Received Character Interrupt Mask This bit is set and cleared by software to enable or disable the RXC interrupt 0 RXC interrupt disabled 1 RXC interrupt enabled Bit 0 PARM Parity Error Interrupt Mask This bit is set and cleared by software to enable or disable the parity error interrupt for parity error 0 PAR interrupt disabled 1 PAR error interrupt enabled Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 On chip peripherals Smartcard interrupt pending register CRDIPR Read Only Reset Value 0000 0000 00h T 0 TXBEP IOVFP VCRDP WTP TXCP RXCP PARP This register indicates the interrupt source It is cleared after a read operation Bit 7 TXBEP Transmit buffer empty interrupt pending This bit is set by hardware when a TXBE event occurs and the TXBEM bit is set 0 No TXBE interru
55. 11 0 lt gt 11 11 0 lt gt 11 POP CC Pop CC from the Stack Mem gt CC N Z C RIM Enable interrupt level 0 set Load 10 11 0 of CC 1 0 SIM Disable interrupt level set Load 11 in 1 0 of CC 1 1 Doc ID 8951 Rev 6 35 121 Interrupts ST7SCR1EA ST7SCR1R4 Table 10 Dedicated interrupt instruction set continued Instruction New description Function Example 11 H 10 ZIC TRAP Software trap Software NMI 1 1 WFI Wait for interrupt 1 0 Note During the execution of an interrupt routine the HALT POPCC RIM SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions In order not to lose the current software priority level the RIM SIM HALT WFI and POP CC instructions should never be used in an interrupt routine Table 11 Interrupt mapping Source Register Priorit Exit Address N Description 9 from block label order vector HALT FFFEh RESET Reset yes FFFFh FFFCh TRAP Software Interrupt N A FFFDh 0 ICP FLASH Start programming NMI FFFAh interrupt TLI FFFBh no 1 UART 1507816 3 UART Interrupt UIC Highest gio d Priority Xo USBIST FFF6h 2 USB USB Communication Interrupt R FFF7h FFF4h 3 WAKUP1 External Interrupt Port C yes FFF5h FFF2h 4 WAKUPZ2_ External Interrupt Port A yes FFF3h Low
56. 1Additional word 0 to 2 according to the number of bytes required to compute the effective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented They precede the opcode of the instruction in X or the instruction using direct addressing mode The prebytes are PDY 90Replace an X based instruction using immediate direct indexed or inherent addressing mode by a Y one PIX 92Replace an instruction using direct direct bit or direct relative addressing mode to an instruction using the corresponding indirect addressing mode It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode PIY 91Replace an instruction using X indirect indexed addressing mode by a Y one Table 27 Instruction set overview Mnemo Description Function Dst Src 2 Example ADC Add with Carry A A M C A M H N Z C ADD Addition A A M A M AND Logical And A A M A M N gcp Bitcompare A tst A M A M 2 BRES Bit Reset bres Byte 3 M BSET Bit Set bset Byte 3 M BTJF Jump if bit is false 0 00 Byte 3 M C Jmp1 BTJT Jump if bit is true 1 Plt Byte 3 M C Jmp1 CALL Call subroutine CALLR Call subroutine relative CLR Clear reg 1 Arithmetic Compare tst Reg M reg M N Z C Doc ID 8951 Rev 6 93 121 Instruction set
57. 30 HHHHHHEHHHHHEHEH a c L1 1 00 0 039 Number of Pins N 64 Figure 45 24 pin plastic small outline package 300 mil width D aes Bim mm inches i Min Typ Max Min Typ Max ETHER 2 35 2 65 0 093 0 104 4 1 0 10 0 30 0 004 0 012 TB Ce B 0 33 0 51 10 013 0 020 023 0 32 0 009 0 013 D 15 20 15 600 599 0 614 E 740 7 60 0 291 0 299 e 1 27 0 050 H 10 00 10 65 0 394 0 419 H 0 25 0 75 0 010 0 030 O a 0 8 0 8 L 040 1 27 0 016 0 050 T Number of Pins N 24 Doc ID 8951 Rev 6 109 121 Package characteristics ST7SCR1E4 ST7SCR1R4 15 2 Recommended reflow oven profile A 20 05 SEATING PLANE PIN 1 ID TYPE C RADIUS 1 nnn Did b ANN e e mm inches Dim Min Typ Max Min Typ Max A 0 80 0 90 1 00 0 031 0 035 0 039 A1 0 02 0 05 0 001 0 002 A3 0 20 0 008 b 0 25 0 30 0 35 0 010 0 012 0 014 5 00 0 197 02 3 50 3 60 3 70 0 138 0 142 0 146 E 5 00 0 197 E2 3 50 3 60 3 70 0 138 0 142 0 146 e 0 65 0 026 L 0 35 0 45 0 55 0 014 0 018 0 022 ddd 0 08 0 003 Number of Pins N 24 T Values in inches are converted from mm and rounded to 3 decimal digits 110 121 Refer to JEDEC specification JSTDO20D for a description of the reco
58. 5 WT14 WT13 WT12 WT11 WT10 WT9 WT8 08 Reset 0 0 1 0 0 1 0 1 Value 09 a WT7 WT6 WT5 WT4 WT3 WT2 WT1 WTO 1 0 0 0 0 0 0 0 Value CRDIER TXBEM IOVM VCRDM WTM TXCM RXCM PARM Reset 0 0 0 0 0 0 0 0 Value CRDIPR TXBEP IOVP WTP TXCP RXCP PARP Reset VCRDP 0 0 0 0 0 0 0 Value 0 7 TB6 TB5 TB4 TB3 TB2 TB1 TBO 0 0 0 0 0 0 0 0 Value oD RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO 0 0 0 0 0 0 0 0 Value Doc ID 8951 Rev 6 87 121 Instruction set ST7SCR1E4 ST7SCR1R4 13 Instruction set 13 1 CPU addressing modes The CPU features 17 different addressing modes which can be classified in 7 main groups Addressing mode Example Inherent nop Immediate Id A 55 Direct Id A 55 Indexed Id A 55 X Indirect Id 55 Relative jrne loop Bit operation bset byte 5 The CPU Instruction set is designed to minimize the number of bytes required per instruction To do so most of the addressing modes may be subdivided in two sub modes called long and short e Long addressing mode is more powerful because it can use the full 64 Kbyte address space however it uses more bytes and more CPU cycles e Short addressing mode is less powerful because it can generally only access page zero 0000h OOFFh range but the instruction size is more compact and faster All memory to memory instructions use short
59. 50uA o4 9 V Vou Output High Level Voltage I 50uA 0 5 ky Doc ID 8951 Rev 6 103 121 Electrical characteristics ST7SCR1E4 ST7SCR1R4 Table 35 Smartcard supply supervisor continued Symbol Parameter Conditions Min Typ Max Unit Output H L Fall Time Cj 30pF 20 ns Toig Output L H Rise Time C 30pF 20 ns Fyar Frequency variation 1 1 Fpury Duty cycle 45 55 96 Signal low perturbation 1 0 25 0 4 V Signal high perturbation 1 0 5 0 25 Short circuit to Ground 15 Smartcard I O Pin Vit Input Low Level Voltage 0 5 9 V Input High Level Voltage 0 6 E V VoL Output Low Level Voltage 0 5 o4 9 V Vou Output High Level Voltage I 200A 0 8VeRpvec Verpvec V IL Input Leakage Current 1 Vss lt Vin lt Vsc_Pwr 10 10 IRPU Pull up Equivalent Resistance Vin Vss 24 30 KQ Tou Output H L Fall Time Cj 30pF 0 8 us Output L H Rise Time C 30pF 0 8 us Short circuit to Ground 15 mA Smartcard RST C4 and C8 Pin Vo Output Low Level Voltage 0 5 0 4 9 V Vou Output High Level Voltage l 20uA 0 5 Vorpvec V Tou Output H L Fall Time Cj 30pF 0 8 us Output L H Rise Time C 30pF 0 8 us
60. 6 Card voltage selection and power OFF block diagram 5V SMARTCARD E LUE POWER SUPPLY L CRDVCC BLOCK Card voltage selection 21 _ 7 0 7 0 CRD CAR CARDVCARD IRF ovr Pe 1 0 CRDSR CRDCR 7 0 7 0 CRD IOVM rii VCC CRDIER CRDCCR 0 POWER OFF IOVP i BLOCK CRDIPR L VCARDOK Interrupt Request L p OVF Interrupt Request z Figure 37 Power off timing diagram vanoa 00 17 00 11 Software Power Off Voltage Error CARDOK Power O GBDVOC Le aN EE ee ee toFF PT gtorr ON VCRDP Interrupt VCARDOK gt i VCRDP Interrupt 1 Note Refer to the Electrical Characteristics section for the values of toy and torr 76 121 Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 On chip peripherals 12 4 4 Figure 38 Card clock selection block diagram osc N POWER OFF BLOCK PLL pyl 4 2 CRDCLK CRDCCR CLK CRD SEL CLK Register description Smartcard interface control register CRDCR Read Write Reset Valu
61. 7SCR1E4 ST7SCR1R4 On chip peripherals 12 12 1 12 1 1 12 1 2 12 1 3 On chip peripherals Watchdog timer WDG Introduction The Watchdog timer is used to detect the occurrence of a software fault usually generated by external interference or by unforeseen logical conditions which causes the application program to abandon its normal sequence The Watchdog circuit generates an MCU reset on expiry of a programmed time period unless the program refreshes the counter s contents before the T6 bit becomes cleared Main features Programmable free running downcounter 64 increments of 65536 CPU cycles Programmable reset Reset if watchdog activated when the T6 bit reaches zero Hardware Watchdog selectable by option byte Watchdog Reset indicated by status flag Functional description The counter value stored in the CR register bits T 6 0 is decremented every 65 536 machine cycles and the length of the timeout period can be programmed by the user in 64 increments If the watchdog is activated the WDGA bit is set and when the 7 bit timer bits T 6 0 rolls over from 40h to 3Fh T6 becomes cleared it initiates a reset cycle pulling low the reset pin for typically 500ns The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset This downcounter is free running it counts down even if the watchdog is disabled The value to be stored in the CR regis
62. AT_TX STAT_TX 0 DTOG R STAT RX STAT RX 25 Val X 1 0 X 1 0 eset Value 0 0 0 0 0 0 0 26 CNTORXR 0 0 0 CNT3 CNT2 CNT1 CNTO Reset Value 0 0 0 0 27 CNTOTXR 0 0 0 CNT3 CNT2 CNT1 CNTO Reset Value 0 0 0 0 1 CTR TX DTOG_T STAT_TX STAT_TX 28 Reset Val 0 0 0 0 X 1 0 eset Value 0 0 0 NT1TXR NT NT2 NT1 NT 29 C 0 0 0 CNT3 CNTO Reset Value 0 0 0 0 2 CTR RX DTOG R STAT RX STAT RX Reset Val 9 0 0 0 _ eset Value 0 0 0 2B CNT2RXR CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNTO Reset Value 0 0 0 0 0 0 0 68 121 Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 On chip peripherals Table 23 USB register map and reset values continued Add i Register 7 6 5 4 3 2 1 0 Hex name EP2TXR CTR TX DTOG T STAT TX STAT TX 2C Reset Val 0 0 0 0 0 X 1 0 eset value 0 0 0 CNT2TXR 0 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNTO Reset Value 0 0 0 0 0 0 0 EP3TXR CTR_TX DTOG_T STAT_TX STAT_TX 2E Reset Val 0 0 0 0 0 X 1 0 eset value 0 0 0 CNT3TXR CNT3 CNT2 CNT1 CNTO di Reset Value 0 M 0 0 0 0 EPATXR CTR_TX DTOG_T STAT_TX STAT_TX 30 Reset Val 0 0 0 0 0 X 1 0 eset value 0 0 0 CNT4TXR CNT3 CNT2 CNT1 CNTO i Reset Value a 9 0 0 0 0 EPSTXR CTR TX DTOG T STAT TX STAT TX 32 Reset Val 0 0 0 0 0 X 1 0 eset value 0 0 0 CNT3 CNT2 CNT1 CNTO 33 CNT5TXR 0 0 0 0 0 0 0 0 ERR2 ERR1 ERRO 34 ERRSR 0 0 0 0 0 0 0 0 12 4 Smartcard interface CRD 12 4 1 I
63. B LOW SPEED Firmware V4 x AN1445 Emulated 16 bit Slave SPI AN1475 Developing an ST7265X Mass Storage Application AN1504 Starting a PWM Signal Directly at High Level Using the ST7 16 bit Timer AN1602 16 bit Timing Operations Using ST7262 or ST7263B ST7 USB MCUs AN1633 Device Firmware Upgrade DFU Implementation in ST7 Non USB Applications AN1712 Generating a High Resolution Sinewave Using ST7 PWMART AN1713 SMBus Slave Driver for ST7 I2C Peripherals AN1753 Software UART Using 12 bit ART AN1947 ST7MC PMAC Sine Wave Motor Control Software Library General Purpose AN1476 Low Cost Power Supply for Home Appliances AN1526 ST7FLITEO Quick Reference Note AN1709 EMC Design for ST Microcontrollers AN1752 ST72324 Quick Reference Note Product Evaluation AN 910 Performance Benchmarking AN 990 ST7 Benefits vs Industry Standard AN1077 Overview of Enhanced CAN Controllers for ST7 and ST9 MCUs AN1086 U435 Can Do Solutions for Car Multiplexing AN1103 Improved B EMF detection for Low Speed Low Voltage with ST72141 AN1150 Benchmark ST72 vs PC16 AN1151 Performance Comparison Between ST72254 amp PC16F876 AN1278 LIN Local Interconnect Network Solutions Product Migration AN1131 Migrating Applications from ST72511 311 214 124 to ST72521 321 324 AN1322 Migrating an Application from ST7263 Rev B to ST7263B AN1365 Guidelines for Migrating ST72C254 Applications to ST72F264 AN1604 How to Use ST7MDT1 TRAIN with ST72F264 AN2200 Guidelines for Migrating ST7LITE1x Applicatio
64. C interrupt software must write the CWT value Character Waiting Time in the CRDWT registers See example in Figure 33 Manual mode The load conditions are Awrite access to the CRDWT2 register is performed while the UART bit 0 and the WTEN bit 0 In Manual mode if the WTEN bit of the CRDCR register is reset the timer acts as a general purpose timer The timer is loaded when a write access to the CRDWT2 register occurs The timer starts when the WTEN bit 1 Interrupt generator The Smartcard Interface has 2 interrupt vectors e Card Insertion Removal Interrupt CRD Interrupt The CRD interrupt is cleared when software reads the CRDIPR register The Card Insertion Removal is an external interrupt and is cleared automatically by hardware at the end of the interrupt service routine IRET instruction If an interrupt occurs while the CRDIPR register is being read the corresponding bit will be set by hardware after the read access is done Figure 33 Waiting time counter example Fare must program must program Reader CHARO CHER A TXC Interrupt i Smartcard HARO CHARI gt Start bit _ Waiting Time Counter loaded on start bit Card detection mechanism The CRDDET bit in the CRDCR Register indicates if the card presence detector card switch is open or closed whe
65. CPU context during an interrupt The user may also directly manipulate the stack by means of the PUSH and POP instructions In the case of an interrupt the PCL is stored at the first location pointed to by the SP Then the other registers are stored in the next locations as shown in Figure 11 e When an interrupt is received the SP is decremented and the context is pushed on the stack e On return from interrupt the SP is incremented and the context is popped from the stack A subroutine call occupies two locations and an interrupt five locations in the stack area Figure 11 Stack manipulation example CALL nterrupt PUSH Y POP Y IRET RET Subroutine Event or RSP 0100h SP SP gt SP Y Ld Ld CC CC A A A X X X SP PCH PCH PCH SP PCL PCL PCL PCH PCH PCH PCH PCH SP 017Fh PCL PCL PCL PCL PCL Stack Higher Address 017Fh Stack Lower Address 0100h Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Supply reset and clock management 6 Supply reset and clock management Clock system General description The MCU accepts either a 4 MHz crystal or an external clock signal to drive the internal oscillator The internal clock fep is derive
66. CR1R4 Pin description Table 3 Pin description continued Pin n Level Port Control B Output Main x Pin name 5 5 a Pu function Alternate function 2 E E 2 als after reset 2 Sasso 34 GND Ground 35 PCO WAKUP1 IC External interrupt 36 PC1 WAKUP1 X X 1 External interrupt 37 PC2 WAKUP1 C X X 2 1 External interrupt 38 PC3 WAKUP1 1 External interrupt 39 PC4 WAKUP1 Cr X X 4 1 External interrupt 40 PC5 WAKUP1 Cr X X Pcs 1 External interrupt 41 PC6 WAKUP1 pce External interrupt 42 PC7 WAKUP1 X X PC7 External interrupt e eve s ade 13 GND S Must be held low in normal operating mode 44 14 17 PA6 6 45 15 18 LEDO HS X Constant Current Output 46 16 19 DM USB Data Minus line 47 17 20 DP Cr USB Data Plus line 48 NC Not Connected 49 18 21 USBVCC Cr 3 3 V Output for USB 50 19 22 VppA 5 power Supply voltage 4V 5 5V 51 20 23 Vpp S power Supply voltage 4V 5 5V 52 LED1 HS X Constant Current Output 53 LED2 HS X Constant Current Output 54 LED3 HS Constant Current Output 55 NC Not Connected 56 NC Not Connected 57 PA4 X X X PortA4 58 X X X X Port A5 59 21 24 SELF2 An External indu
67. DDR Port A Data Direction Register PADDR 0012h Read Write Reset Value Port A 0000 0000 00h 7 0 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DDO Bits 7 0 007 000 Data Direction Register 8 bits The DDR register gives the input output direction configuration of the pins Each bits is set and cleared by software 0 Input mode 1 Output mode OPTION REGISTER PxOR Port x Option Register PxOR with x A B or D Port A Option Register PAOR 0013h Port B Option Register PBOR 0016h Port D Option Register PDOR 001Ah Read Write Reset Value 0000 0000 00h 7 0 OM7 OM6 OM5 OM4 OM2 OM1 OMO Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 ports Bits 7 0 OM 7 0 Option register 8 bits The OR register allows to distinguish in output mode if the push pull or open drain configuration is selected Each bit is set and cleared by software 0 Output open drain 1 Output push pull PULL UP CONTROL REGISTER PxPUCR Port x Pull Up Register PxPUCR with or D Port A Pull up Register PAPUCR 0014h Port B Pull up Register PBPUCR 0017h Port D Pull up Register PDPUCR 001Bh Read Write Reset Value 0000 0000 00h 7 0 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PUO Bits 7 0 PU 7 0 Pull up register 8 bits The PU register is used to control the pull up Each bit is set and cleared by software 0 Pull up inactive 1 Pull up active
68. F RXCF PAR F Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 On chip peripherals Bit 7 TxBEF Transmit Buffer Empty Flag Read only 0 Transmit buffer is not empty 1 Transmit buffer is empty Bit 6 CRDIRF Card Insertion Removal Flag Read only 0 No card is present 1 A card is present Bit 5 IOVF Card Overload Current Flag Read only 0 No card overload current 1 Card overload current Bit 4 VCARDOK Card voltage status Flag Read only 0 The card voltage is not in the specified range 1 The card voltage is within the specified range Bit 3 WTF Waiting Time Counter overflow Flag Read only 0 The WT Counter has not reached its maximum value 1 The WT Counter has reached its maximum value Bit 2 TXCF Transmitted character Flag Read Write This bit is set by hardware and cleared by software 0 No character transmitted 1 A character has been transmitted Bit 1 RXCF Received character Flag Read only This bit is set by hardware and cleared by hardware when the CRDRXB buffer is read 0 No character received 1 A character has been received ky Doc ID 8951 Rev 6 79 121 On chip peripherals ST7SCR1E4 ST7SCR1R4 Note Note Note 80 121 Bit PARF Parity Error Flag Read Write This bit is set by hardware and cleared by software 0 No parity error 1 Parity error When a character is received the RXCF bit is
69. Peripherals USB full speed 7 TBU Watchdog timer 1507816 3 interface Operating supply 4 0 to 5 5V CPU frequency 4 or 8 MHz Operating temperature 0 C to 70 C Package LQFP64 024 QFN24 8 121 Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Description Figure 1 ST7SCR block diagram OSCIN 4 4MHz OSCOUT 4 OSCILLATOR KC D soma MET Bill PORTB gt PB 7 0 48 MHz 8 MHz DIVIDER PC 7 0 USB DATA 5 lt gt porto gt PDI7 0 bytes KD 77 a gt LED gt LED S 0 USBDP 2 USBDM gt USB lt 1807816 UART USBVCC gt wo c z SUPPLY WATCHDOG lt gt Rene MANAGER amp BIT TIMER gt SELF PA6 j CONTROL cum Hum CONVERTER Vep a rie lt gt CRDDET CRDIO CRDC4 RAM 512 Bytes CRDC8 PROGRAM 3V 1 8V Vreg CRDRST MEMORY CRDCLK 16K Bytes Doc ID 8951 Rev 6 9 121 Pin description ST7SCR1E4 ST7SCR1R4
70. ST7SCR1E4 ST7SCR1R4 14 7 2 Note 14 7 3 106 121 Electro magnetic interference EMI Based on a simple application running on the product toggling 2 LEDs through the ports the product is monitored in terms of emission This emission test is in line with the norm SAE J 1752 3 which specifies the board and the loading of each pin Max vs Unit Symbol Parameter Conditions f fosc fcpu 4 8MHz 4 4MHz 0 1MHz to 30MHz 18 Vpp 5V Ta 25 C SOMHZ to 32 27 dBuV Semi Peak level conforming to SAE J 130MHz 1752 3 130MHz to 1GHz i 28 SAE EMI Level 4 3 5 Data based on characterization results not tested in production Absolute maximum ratings electrical sensitivity Based on three different tests ESD LU and DLU using specific measurement methods the product is stressed in order to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electro static discharge ESD Electro Static Discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin The Human Body Model is simulated This test conforms to the JESD22 A114A standard Table 36 Absolute maximum ratings Symbol Ratings Conditions Unit valu
71. TAT RXO Meaning DISABLED no function can be executed on this 0 0 endpoint and messages related to this endpoint are ignored STALL the endpoint is stalled and all reception requests result in a STALL handshake 64 121 Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 On chip peripherals Note Table 20 Reception status encoding STAT RX1 STAT RXO Meaning NAK the endpoint is NAKed and all reception requests 1 9 result in a NAK handshake VALID this endpoint is enabled if an address match occurs the USB interface handles the transaction These bits are written by software Hardware sets the STAT RX and TX bits to when a correct transfer has occurred CTR 1 addressed to this endpoint so the software has the time to examine the received data before acknowledging a new transaction If a SETUP transaction is received while the status is different from DISABLED it is acknowledged and the two directional status bits are set to NAK by hardware When a STALL is answered by the USB device the two directional status bits are set to STALL by hardware Endpoint transmission register EP1TXR EP2TXR EP3TXR EPATXR EP5TXR Read Write Reset value 0000 0000 00h 7 0 STAT _ STAT 0 0 0 0 CTR TX DTOG TX TX This register is used for controlling Endpoint 1 2 3 4 or 5 transmission Bits 2 0 are also reset by a USB reset either received from th
72. This bit is active only if the CLKSEL bit of the CRDCCR register is reset Reading this bit returns the value present in the register not the CRDCLK pin value When the CLKSEL bit is reset 0 Level 0 to be applied on CRDCLK pin 1 Level 1 to be applied on CRDCLK pin To ensure that the clock stops at a given value write the desired value in the CRDCLK bit prior to changing the CLKSEL bit from 1 to 0 Bit 1 CRDRST CRDRST pin control Reading this bit returns the value present on the CRDRST pin Writing this bit outputs the bit value on the pin Bit 0 CRDVCC CRDVCC Pin Control This bit is set and cleared by software and forced to 0 by hardware when no card is present CRDIRF bit 0 0 No voltage to be applied on the CRDVCC pin 1 The selected voltage must be applied on the CRDVCC pin Figure 39 Smartcard I O pin structure PIN lt CRDCCR REGISTER DATA BUS Smartcard elementary time unit register CRDETUx CRDETU1 Read Write Reset Value 0000 0001 01h 7 0 COMP 0 0 0 0 ETU10 ETU9 ETU8 Bit 7 COMP Elementary Time Unit Compensation 0 Compensation mode disabled Doc ID 8951 Rev 6 81 121 On chip peripherals ST7SCR1E4 ST7SCR1R4 Note 82 121 1 Compensation mode enabled To allow non integer value one clock cycle is subtracted from the ETU value on odd bits See Figure 32 Bit 6 3 Reserved Bits 2 0 ETU
73. UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2012 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 8951 Rev 6 121 121
74. Under software control all devices can be placed in WAIT or HALT mode reducing power consumption when the application is in idle or stand by state The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers enabling the design of highly efficient and compact application code In addition to standard 8 bit data management all ST7 microcontrollers feature true bit manipulation 8x8 unsigned multiplication and indirect addressing modes The devices include an ST7 core up to 16 Kbytes of program memory up to 512 bytes of user RAM up to 35 I O lines and the following on chip peripherals e USB full speed interface with 7 endpoints programmable in out configuration and embedded 3 3V voltage regulator and transceivers no external components are needed e 1507816 3 UART interface with programmable baud rate from 372 clock pulses up to 11 625 clock pulses e Smartcard Supply Block able to provide programmable supply voltage and voltage levels to the smartcards Low voltage reset ensuring proper power on or power off of the device selectable by option e Watchdog timer e 8 bittimer TBU Table 2 Detailed device summary ST7SCR1R4 ST7SCR1E4 Features ST7FSCR1T1 ST7SCR1T1 ST7FSCR1M1 ST7SCR1M1 ST7SCR1U1 16 Kbytes 16 Kbytes Program memory FLASH 16 Kbytes ROM FLASH 16 Kbytes ROM 16 Kbytes ROM User RAM stack 768 128 bytes
75. X or Y with a pointer value located in memory The pointer address follows the opcode The indirect indexed addressing mode consists of two sub modes Indirect indexed Short The pointer address is a byte the pointer size is a byte thus allowing 00 1FE addressing space and requires 1 byte after the opcode Indirect indexed Long The pointer address is a byte the pointer size is a word thus allowing 64 Kbyte addressing space and requires 1 byte after the opcode Table 26 Instructions supporting direct indexed indirect and indirect indexed addressing modes Long and short instructions Function LD Load CP Compare AND OR XOR Logical Operations ADC ADD SUB SBC Arithmetic Additions Subtractions operations BCP Bit Compare Short instructions only Function CLR Clear INC DEC Increment Decrement TNZ Test Negative or Zero CPL NEG 1 or 2 Complement BSET BRES Bit Operations Doc ID 8951 Rev 6 91 121 Instruction set ST7SCR1E4 ST7SCR1R4 13 1 7 13 2 92 121 BTJT BTJF Bit Test and Jump Operations SLL SRL SRA RLC RRC Shift and Rotate Operations SWAP Swap Nibbles CALL JP Call or Jump subroutine Relative mode Direct Indirect This addressing mode is used to modify the PC register value by adding an 8 bit signed offset to it Available relative direct indirect instructions Function Con
76. an Sede a be ee aie ed Mae Se ea alata ee 19 4 4 ICP In circuit programming 20 4 5 IAP In application 20 4 6 Program memory read out protection 21 4 7 Related documentation 21 4 8 Register description 22 5 Central processing unit 23 5 1 Introduction ccs RE RX AER tsa E XR REX RE eee 23 5 2 M in Galles xax eden de FRE RR OL Hee cg 23 Bo GCPUregisterS ure oe Bete 23 6 Supply reset and clock management 27 6 1 CIOCCSYSION det ERRARE CPUS MET 27 6 1 1 General description 27 6 1 2 External clock occasus ast Peden eee 28 6 2 Reset sequence manager 28 6 2 1 Introduction up OU RUN TR e RTOS aac 28 6 2 2 Functional description llle 28 7 luin Sem 30 7 1 P may eed wet eee ad 12 30 7 2 Masking and processing flow 30 7 8 Interrupts and low power modes 33 2 121 Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 Contents 7 4 Concurrent and nested
77. askable Software Interrupt This software interrupt is serviced when the TRAP instruction is executed It will be serviced according to the flowchart in Figure 17as a TLI Caution can be interrupted by TLI Note 32 121 e RESET The RESET source has the highest priority in the CPU This means that the first current routine has the highest software priority level 3 and the highest hardware priority See the RESET chapter for more details Maskable sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority in ISPRx registers is higher than the one currently being serviced 11 and IO in CC register If any of these two conditions is false the interrupt is latched and thus remains pending e External Interrupts External interrupts allow the processor to exit from HALT low power mode External interrupt sensitivity is software selectable through the register External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine If several input pins of a group connected to the same interrupt line are selected simultaneously these will be logically NANDed e Peripheral Interrupts Usually the peripheral interrupts cause the Device to exit from HALT mode except those mentioned in the Interrupt Mapping table A peripheral interrupt occurs when a specific flag
78. c logical or data manipulation It s a copy of the result 7 bit 0 The result of the last operation is positive or null 1 The result of the last operation is negative i e the most significant bit is a logic 1 This bit is accessed by the JRMI and JRPL instructions Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Central processing unit Bit 1 Z Zero This bit is set and cleared by hardware This bit indicates that the result of the last arithmetic logical or data manipulation is zero 0 The result of the last operation is different from zero 1 The result of the last operation is zero This bit is accessed by the JREQ and JRNE test instructions Bit 0 Carry borrow This bit is set and cleared by hardware and software It indicates an overflow or an underflow has occurred during the last arithmetic operation 0 No overflow or underflow has occurred 1 An overflow or underflow has occurred This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions It is also affected by the bit test and branch shift and rotate instructions Interrupt Management Bits Bit 5 3 10 Interrupt The combination of the 11 and 10 bits gives the current interrupt software priority Interrupt Software Priority 1 10 Level 0 main 1 0 Level 1 0 1 Level 2 0 0 Level 3 interrupt disable 1 1 These two bits are set cleared by hardware when entering in
79. cant PID bits have a fixed value of 01 When a CTR interrupt occurs on Endpoint 0 see register USBISTR the software should read the PID 1 0 bits to retrieve the PID name of the token received The USB specification defines PID bits as PID1 PIDO PID name 0 0 OUT 1 0 IN 1 1 SETUP Bit 5 IN OUT Last transaction direction for Endpoint 1 2 3 4 or 5 This bit is set by hardware when a CTR interrupt occurs on Endpoint 1 2 3 4 or 5 0 OUT transaction 1 IN transaction Bits 4 3 Reserved forced by hardware to 0 Bits 2 0 EP 2 0 Endpoint number These bits identify the endpoint which required attention 000 Endpoint 0 001 Endpoint 1 010 Endpoint 2 011 Endpoint 3 100 Endpoint 4 101 Endpoint 5 Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 On chip peripherals Note Error status register ERRSR Read only Reset Value 0000 0000 00h 7 0 0 0 0 0 0 ERR2 ERR1 ERRO Bits 7 3 Reserved forced by hardware to 0 Bits 2 0 ERR 2 0 Error type These bits identify the type of error which occurred ERR2 ERR1 ERRO Meaning 0 0 0 No error 0 0 1 Bitstuffing error 0 1 0 CRC error 0 1 1 EOP error unexpected end of packet or SEO not followed by J state 1 0 0 PID error PID encoding error unexpected or unknown PID 1 0 1 over underrun memory controller has not answered in time to a memory data request 1 1 1 Other error
80. ce Figure 34 Card detection block diagram SMARTCARD INTERFACE CRD Pull up EDGE DETECTOR i a CRDDET FL C 0 CARD INSERTION REMOVAL Interrupt Request 7 0 DET e RDCR 7 PAPE 0 CRD Re CRDSR 7 0 CRD IRM MISCR2 E Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 On chip peripherals Card deactivation sequence This sequence can be activated in two different ways e Automatically as soon as the card presence detector detects a card removal via the CRDIRF bit in the CRDSR register refer to Blue HT gt Section e By software writing the CRDVCC bit in the CRDCR register for example If there is a smartcard current overflow i e when the IOVFF bit in the CRDSR register is set Ifthe voltage is not within the specified range i e when the VCARDOK bit in the CRDSR register is cleared but software must clear the CRDVCC bit in the CRDCCR register to start the deactivation sequence When the CRDVCC bit is cleared this starts the deactivation sequence CRDCLK CRDIO CRDC4 and CRDC8 pins are then deactivated as shown in Figure 35 Figure 35 Card deactivation sequence 8 CPU CIk cycles lt CRDVCC pin N CRDRST pin CRDCLK pin CRDIO pin N CRDCA pin Y CRDC8 pin Doc ID 8951 Rev 6 75 121 On chip peripherals ST7SCR1E4 ST7SCR1R4 Figure 3
81. ced if unused inputs are connected to an appropriate logic voltage level Vpp or Vss Power Considerations The average chip junction temperature Tj in Celsius can be obtained from TJ PD x RthJA Where T Ambient Temperature RthJA Package thermal resistance junction to ambient Pint Peonr Pint X Vpp chip internal power Port power dissipation determined by the user Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these conditions is not implied Exposure to maximum rating for extended periods may affect device reliability Symbol Ratings Value Unit Vpp Vss Supply voltage 6 0 Vin Input voltage Vss 0 3 to Voo 0 3 V Vout Output voltage Vss 0 3 to Vbo 0 3 V ESD ESD susceptibility 2000 V ESDCard ESD susceptibility for card pads 4000 V lvpD i Total current into Vpp source 250 lvss i Total current out of Vgg sink 250 d Warning Direct connection to Vpp or Vgs of the I O pins could damage the device in case of program counter corruption due to unwanted change of the I O configuration To guarantee safe conditions this connection has to be done through a typical 10KQ pull up or pull down resistor Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 Electrical characteristics Table 28 Thermal characteristics
82. ch the internal reset is maintained 2 second delay of 512 tcpy cycles after the internal reset is generated It allows the oscillator to stabilize and ensures that recovery has taken place from the Reset state 3 Reset vector fetch duration 2 clock cycles Low voltage detector The low voltage detector generates a reset when Vpp Vir rising edge or Vpp V falling edge as shown in Figure 15 The LVD filters spikes on Vpp larger than to avoid parasitic resets See Section 14 3 Supply and reset characteristics Note It is recommended to make sure that the Vpp supply voltage rises monotonously when the device is exiting from Reset to ensure the application functions properly Figure 15 LVD RESET sequence LVD RESET DELAY 1 DELAY 2 LVD i RESET PP INTERNAL RESET ub i DELAY 1 30us 127 DELAY 2 512 j Ez FETCH VECTOR 2 tcpy Figure 16 Watchdog RESET sequence WATCHDOG RESET RUN DELAY 1 DELAY 2 WATCHDOG RESET gt WATCHDOG UNDERFLOW DELAY 1 30ys 127 tcpy DELAY 2 512 tcp l 75 FETCH VECTOR 2 tcpy ky Doc ID 8951 Rev 6 29 121 Interrupts ST7SCR1E4 ST7SCR1R4 7 7 1 7 2 Note 30 121 Interrupts Introduction The CPU enhanced interrupt management provides the following features e Hardware interrupts e Software interrupt TRAP e
83. ctance must be connected to these pins for the step up converter refer 60 21 24 SELF1 to Figure 5 to choose the right capacitance An External diode must be connected to this 61 22 1 DIODE pin for the step up converter refer to Figure 5 to choose the right component Doc ID 8951 Rev 6 13 121 Pin description ST7SCR1E4 ST7SCR1R4 Table 3 Pin description continued Pin n Level Port Control E Main 5 E Input Output function Alternate function i Ta a s 3 after reset 2 s 2 7 62 23 2 5 Ground 63 24 3 GND 5 64 1 4 CRDVCC Cr X Smartcard Supply pin 1 Keyboard interface Note It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground Figure 5 Smartcard interface reference application 24 pin SO package Vpp Co I C1 1 D1 Z7 L DIODE SELF Vpp DD H zz jCRDVCC USBVcc 1 T c2 E DP R J c4 CRDRST D C5 T CRDCLK DM D LEDO Vp T L WT C8 Vpp
84. d Write 7 0 CRD IRM ITM14 ITM13 ITM12 ITM11 ITM10 ITM9 Writing the ITIFREA register enables or disables external interrupt on port A Bit 7 Reserved Bit 6 CRDIRM CAD Insertion Removal Interrupt Mask 0 CRDIR interrupt disabled 1 CRDIR interrupt enabled Bits 5 0 ITM 14 9 nterrupt Mask Bit x of MISCR2 masks the external interrupt on port A x Bit x ITM n Interrupt Mask 0 external interrupt disabled on PA x 1 external interrupt enabled on PA x Miscellaneous register 3 MISCR3 Reset Value 0000 0000 00h Doc ID 8951 Rev 6 47 21 Miscellaneous registers ST7SCR1E4 ST7SCR1R4 48 121 Read Write 7 0 CTRL1_A CTRLO_A CTRL1_C CTRLO_C This register is used to configure the edge and the level sensitivity of the Port A and Port external interrupt This means that all bits of a port must have the same sensitivity write access modifies bits 7 4 it clears the pending interrupts CTRLO_C CTRL1_C Sensitivity on port C CTRLO_A CTRL1_A Sensitivity on port A CTRL1_X CTRLO_X External interrupt sensitivity 0 0 Falling edge amp low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge Miscellaneous register 4 MISCR4 Reset Value 0000 0000 00h Read Write 7 0 PLL_ON CLK_SEL LOCK Bit 7 Reserved Bit 6 PLL_ON PLL Activation 0 PLL
85. d also be put in Halt mode to reduce power consumption 0 Suspend mode inactive 1 Suspend mode active When the hardware detects USB activity it resets this bit it can also be reset by software Bit FRES Force reset This bit is set by software to force a reset of the USB interface just as if a RESET sequence came from the USB 0 Reset not forced 1 USB interface reset forced The USB is held in RESET state until software clears this bit at which point a USB RESET interrupt will be generated if enabled Device address register DADDR Read Write Reset Value 0000 0000 00h 7 0 0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADDO Bit 7 Reserved forced by hardware to 0 Bits 6 0 ADD 6 0 Device address 7 bits Software must write into this register the address sent by the host during enumeration Doc ID 8951 Rev 6 61 121 On chip peripherals ST7SCR1E4 ST7SCR1R4 Note Note 62 121 This register is also reset when a USB reset is received or forced through bit FRES in the USBCTLR register USB status register USBSR Read only Reset Value 0000 0000 00h 7 0 PID1 PIDO IN OUT 0 0 EP2 EP1 EPO Bits 7 6 PID 1 0 Token PID bits 1 amp 0 for Endpoint Control USB token PIDs are encoded in four bits PID 1 0 correspond to the most significant bits of the PID field of the last token PID received by Endpoint O The least signifi
86. d from the internal oscillator frequency fosc which is 4 MHz After reset the internal clock fcpy is provided by the internal oscillator 4 MHz frequency To activate the 48 MHz clock for the USB interface the user must turn on the PLL by setting the PLL_ON bit in the MISCR4 register When the PLL is locked the LOCK bit is set by hardware The user can then select an internal frequency of either 4 MHz or 8 MHz by programming the CLK_SEL bit in the MISCR4 register refer to Section 10 Miscellaneous registers The PLL provides a signal with a duty cycle of 50 The internal clock signal fcpy is also routed to the on chip peripherals The CPU clock signal consists of a square wave with a duty cycle of 50 Figure 12 Clock reset and supply block diagram PLL CLK_ ON SEL MISCR4 LOCK INTERNAL 4 MHz CLOCK fepu foso 48 MHz USB The internal oscillator is designed to operate with an AT cut parallel resonant quartz in the frequency range specified for fose The circuit shown in Figure 14 is recommended when using a crystal and Table 6 lists the recommended capacitance The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start up stabilization time The LOCK bit in the MISCR4 register can also be used to generate the
87. disabled 1 PLL enabled Note The PLL must be disabled before a HALT instruction Bit 5 CLK_SEL Clock Selection This bit is set and cleared by software 0 CPU frequency 4MHz 1 CPU frequency 8MHz Bits 4 1 Reserved Bit LOCK PLL status bit 0 PLL not locked fopy fosc external clock frequency 1 PLL locked 4 or 8 MHz depending on CLKSEL bit Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 Miscellaneous registers Table 17 Register map and reset values Add i ress Register 7 6 5 4 3 2 1 0 label 001C MISCR1 ITM7 ITM6 ITM5 ITM4 ITM3 ITM2 ITM1 ITMO Reset Value 0 0 0 0 0 0 0 0 001D MISCR2 0 0 ITM14 ITM13 ITM12 ITM11 ITM10 ITM9 Reset Value 0 0 0 0 0 0 MISCR3 CTRL1 A CTRLO_A CTRL1 C CTRLO C Reset Value 0 0 0 0 g 4 MISCR4 PLL ON RST IN CLK SE LOCK PEN Reset Value 0 0 0 OL 0 9 0 ky Doc ID 8951 Rev 6 49 121 LEDs ST7SCR1E4 ST7SCR1R4 11 50 121 LEDs Each of the four available LEDs can be selected using the LED_CTRL register Two types of LEDs are supported 3mA and 7mA LED_CTRL register Reset Value 0000 0000 00h Read Write 7 0 LD3 LD2 LD1 LDO LD3_ LD2_ LD1 LDO 1 Bits 7 4 LDx LED Enable 0 LED disabled 1 LED enabled Bits 3 0 LDx Current selection on LDx 0 3mA current on LDx pad 1 7mA current on LDx pad Doc ID 8951 Rev 6 ky ST
88. ditional Jump CALLR Call Relative The relative addressing mode consists of two sub modes Relative Direct The offset is following the opcode Relative Indirect The offset is defined in memory which address follows the opcode Instruction groups The ST7 family devices use an Instruction Set consisting of 63 instructions The instructions may be subdivided into 13 main groups as illustrated in the following table Load and Transfer LD CLR Stack operation PUSH RSP Increment Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RRC SWAP Unconditional Jump or Call JRA JRT JRF CALL CALLR NOP RET Conditional Branch JRxx Interruption management TRAP WFI HALT IRET Condition Code Flag modification SIM RIM SCF RCF Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Instruction set Using a pre byte The instructions are described with one to four opcodes In order to extend the number of available opcodes for an 8 bit CPU 256 opcodes three different prebyte opcodes are defined These prebytes modify the meaning of the instruction they precede The whole instruction becomes PC 2End of previous instruction PC 1Prebyte PCopcode PC
89. e 1 1 VALID this endpoint is enabled for transmission These bits are written by software but hardware sets the STAT TX bits to NAK when a correct transfer has occurred CTR 1 addressed to this endpoint This allows software to prepare the next set of data to be transmitted Endpoint 2 reception register EP2RXR Read Write Reset value 0000 0000 00h 7 0 STAT STAT 0 0 0 0 CTR RX DTOG RX BX1 RXO This register is used for controlling Endpoint 2 reception Bits 2 0 are also reset by a USB reset either received from the USB or forced through the FRES bit in the USBCTLR register Bits 7 4 Reserved forced by hardware to 0 Bit CTR Reception Correct Transfer This bit is set by hardware when a correct transfer operation is performed in reception This bit must be cleared after that the corresponding interrupt has been serviced Bit 2 DTOG RX Data Toggle for reception transfers It contains the expected value of the toggle bit OZDATAO 1 DATA1 for the next data packet The receiver toggles DTOG_RX only if it receives a correct data packet and the packet s data PID matches the receiver sequence bit Bits 1 0 STAT RX 1 0 Status bits for reception transfers These bits contain the information about the endpoint status which is listed below Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 On chip peripherals Table 22 Reception status encoding
90. e 0000 0000 00h 7 0 Eus CRD VCARD 1 VCARD 0 U ART WT EN C REP CO NV Bit 7 CRDRST Smartcard Interface Reset This bit is set by software to reset the UART of the Smartcard interface 0 No Smartcard UART Reset 1 Smartcard UART Reset Bit 6 CRDDET Card Presence Detector This bit is set and cleared by software to configure the card presence detector switch 0 Switch open if no card is present 1 Switch closed if no card is present Bits 5 4 VCARD 1 0 Card voltage selection These bits select the card voltage Bit 1 Bit 0 0 0 OV 0 1 1 8V 1 0 3V 1 1 5V Bit 3 UART UART Mode Selection This bit is set and cleared by software to select UART or manual mode 0 CRDIO pin is a copy of the CRDIO bit in the CRDCCR register Manual mode Doc ID 8951 Rev 6 77 121 On chip peripherals ST7SCR1E4 ST7SCR1R4 Note Note 78 121 1 CRDIO pin is the output of the smartcard UART UART mode Caution Before switching from Manual mode to UART mode software must set the CRDIO bit in the CRDCCR register Bit 2 WTEN Waiting Time Counter enable 0 Waiting Time counter stopped While WTEN 0 a write access to the CRDWT2 register loads the Waiting time counter with the load value held in the CRDWTO CRDWT1 and CRDWT2 registers 1 Start counter In UART mode the counter is automatically reloaded on start bit detection
91. e 1 Electro static discharge voltage ME VESD HBM Human Body Model 25 2090 Y 1 Data based on characterization results not tested in production Static and dynamic latch up e LU 3complementary static tests are required on 10 parts to assess the latch up performance A supply overvoltage applied to each power supply pin and a current injection applied to each input output and configurable I O pin are performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 e DLU Electro Static Discharges one positive then one negative test are applied to each pin of 3 samples when the micro is running to assess the latch up performance in Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Electrical characteristics dynamic mode Power supplies are set to the typical values the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode This test conforms to the IEC1000 4 2 and SAEJ1752 3 standards For more details refer to the application note AN1181 Table 37 Electrical sensitivities Symbol Parameter Conditions Class 1 LU Static latch up class 25 2 Vpp 5 5V fogc 4MHz DLU Dynamic latch up class 25 1 Class description A Class is STMicroelectronics internal specification All its limits are higher than the JEDEC specificatio
92. e following table Table 9 Interrupt vectors and corresponding bits Vector address ISPRx bits FFFBh FFFAh I1 O and lO Ob bits FFF9h FFF8h I1 1 and lO 1 bits FFE1h FFEOh I1 13 and lO 13 bits e Each I1_x and 10_ bit value in the ISPRx registers has the same meaning as the 11 and 10 bits in the CC register e Level 0 can not be written I1 x 1 10 x20 In this case the previously stored value is kept example previous CFh write 64h result 44h The RESET TRAP and TLI vectors have no software priorities When one is serviced the 11 and 10 bits of the CC register are both set Bits in the ISPRx registers which correspond to the TLI can be read and written but they are not significant in the interrupt process management If the I1 x and 10 x bits are modified while the interrupt x is executed the following behavior has to be considered If the interrupt x is still pending new interrupt or flag not cleared and the new software priority is higher than the previous one the interrupt x is re entered Otherwise the software priority stays unchanged up to the next interrupt request after the IRET of the interrupt x Table 10 Dedicated interrupt instruction set Instruction New description Function Example 11 H 10 N 2 C HALT Entering Halt mode 1 0 IRET Interrupt routine return Pop CC A X PC Jump if 11 0 11 11 0 11 JRNM Jump if
93. e USB or forced through the FRES bit in the USBCTLR register Bits 7 4 Reserved forced by hardware to 0 Bit 3 CTR_TX Correct Transmission Transfer This bit is set by hardware when a correct transfer operation is performed in transmission This bit must be cleared after the corresponding interrupt has been serviced 0 No CTR in transmission on Endpoint 1 2 3 4 or 5 1 Correct transfer in transmission on Endpoint 1 2 3 4 or 5 Bit 2 DTOG TX Data Toggle for transmission transfers This bit contains the required value of the toggle bit OZDATAO 1 DATA1 for the next data packet DTOG_TX toggles only when the transmitter has received the ACK signal from the USB host DTOG TX and DTOG RX are normally updated by hardware at the receipt of a relevant PID They can be also written by the user both for testing purposes and to force a specific DATAO or DATA1 token Bits 1 0 STAT TX 1 0 Status bits for transmission transfers These bits contain the information about the endpoint status which is listed below Doc ID 8951 Rev 6 65 121 On chip peripherals ST7SCR1E4 ST7SCR1R4 66 121 Table 21 Transmission status encoding STAT_TX1 STAT TXO Meaning 0 0 DISABLED transmission transfers cannot be executed 0 1 STALL the endpoint is stalled and all transmission requests result in a STALL handshake 1 0 NAK the endpoint is naked and all transmission requests result in a NAK handshak
94. e pin which is submitted to the injection Of course external digital signals applied to the component must have a maximum impedance close to 50K2 Location of the negative current injection ky Doc ID 8951 Rev 6 97 121 Electrical characteristics ST7SCR1E4 ST7SCR1R4 Note Note 98 121 Pure digital pins can tolerate 1 6mA addition the best choice is to inject the current as far as possible from the analog input pins When several inputs are submitted to a current injection the maximum lyy is the sum of the positive resp negative currents instantaneous values 0 to 70 C Vpp Vsg 5 5V unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Supply current in RUN mode 10 15 mA fosc 4MHz Supply current in WAIT mode 2 3 9 mA External OMA Supply current in suspend mode USB transceiver 500 enabled uA External OMA Supply current in HALT mode USB transceiver 50 100 disabled CPU running with memory access all I O pins in input mode with a static value at Vpp or Vss clock input OSCIN driven by external square wave All I O pins in input mode with a static value at Vpp Vss clock input OSCIN driven by external square wave T 0 70 C voltages are referred to Vgs unless otherwise specified Table 30 port pins Symbol Parameter Conditions Min Typ Max Unit Vit Input low
95. eceive and how many bytes need to be transmitted Data transfer to from USB data buffer memory When a token for a valid Endpoint is recognized by the USB interface the related data transfer takes place to from the USB data buffer At the end of the transaction an interrupt is generated Interrupts By reading the Interrupt Status register application software can know which USB event has occurred Figure 29 USB block diagram 48 ENDPOINT __ REGISTERS CPU USBDM lt L Transceiver SIE BUFFER Address USBDP aH lt INTERFACE data busss A and interrupts 3 3V USBVCC Voltage USB _ USB Regulator REGISTERS gt DATA BUFFER USBGND USB endpoint RAM buffers There are seven Endpoints including one bidirectional control Endpoint Endpoint 0 five IN Endpoints Endpoint 1 2 3 4 5 and one OUT endpoint Endpoint 2 Endpoint 0 is 2 x 8 bytes in size Endpoint 1 3 4 and Endpoint 5 are 8 bytes in size and Endpoint 2 is 2 x 64 bytes in size Doc ID 8951 Rev 6 57 121 On chip peripherals ST7SCR1E4 ST7SCR1R4 12 3 4 Note Note 58 121 Figure 30 Endpoint buffer size Endpoint 0 Buffer OUT 8 Bytes Endpoint 0 Buffer IN 8 Bytes Endpoint 1 Buffer IN 8 Bytes Endpoint 2 Buffer OUT 64 Bytes
96. ent and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Software recommendations The software flowchart must include the management of runaway conditions such as Corrupted program counter e Unexpected reset e Critical Data corruption control registers Prequalification trials Most of the common failures unexpected reset and program counter corruption can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Symbol Parameter Conditions Level Class V Voltage limits to be applied on any pin to Vpp 5V Ta 25 C fos 8MHz 2B induce a functional disturbance conforms to IEC 1000 4 2 Fast transient voltage burst limits to be Vpp 5V Ta 25 C fogc 8MHz Verte applied through 100pF on Vpp and Vpp pins DD A MUN 4B to induce a functional disturbance Sonar To 1004 4 Doc ID 8951 Rev 6 105 121 Electrical characteristics
97. equency i e 4 MHz A compensation mode can be activated via the COMP bit of the CRDETU1 register to allow a frequency granularity down to a half etu The decimal value is limited to a half clock cycle The bit duration is not fixed It alternates between n clock cycles and n 1 clock cycles where n is the value to be written in the CRDETU register The character duration 10 bits is also equal to 10 n 12 clock cycles This is precise enough to obtain the character duration specified by the ISO7816 3 standard For example if F 372 and D 32 F being the clock rate conversion factor and D the baud rate adjustment then etu 211 625 clock cycles To achieve this clock rate compensation mode must be activated and the etu duration must be programmed to 12 clock cycles The result will be an average character duration of 11 5 clock cycles for 10 bits Doc ID 8951 Rev 6 71 121 On chip peripherals ST7SCR1E4 ST7SCR1R4 72 121 See Figure 32 Guardtime counter The guardtime counter is a 9 bit counter which manages the character frame It controls the duration between two consecutive characters in transmission It is incremented at the etu rate No guardtime is inserted for the first character transmitted The guardtime between the last byte received from the card and the next byte transmitted by the reader must be handled by software Figure 32 Compensation mode Start bit Parity bit Data bits E CRDIO
98. est Ms FFFOh 5 TIM TBU Timer Interrupt TBUSR Priority no EFFih CARDDET Smartcard Insertion Removal FFEEh 1 Interrupt 1 USCUR FFEFh USBIST FFECh 7 ESUSP End suspend Interrupt R FFEDh FFEAh 8 Not used no FFEBh Note This interrupt can be used to exit from USB suspend mode 36 121 Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Power saving modes 8 8 1 8 2 Power saving modes Introduction To give a large measure of flexibility to the application in terms of power consumption two main power saving modes are implemented in the ST7 After a RESET the normal operating mode is selected by default RUN mode This mode drives the device CPU and embedded peripherals by means of a master clock which is based on the main oscillator frequency From Run mode the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status Wait mode WAIT mode places the MCU in a low power consumption mode by stopping the CPU This power saving mode is selected by calling the ST7 software instruction All peripherals remain active During WAIT mode the bit of the CC register is forced to 0 to enable all interrupts All other registers and memory remain unchanged The MCU remains in WAIT mode until an interrupt or Reset occurs whereupon the Program Counter branches to the starting address o
99. etry on parity error in reception and transmission mode This failure occurrence is systematic only 4 retries option is functional Figure 48 Revision marking on box label and device marking LAST 2 DIGITS AFTER IN INTERNAL SALES TYPE ON BOX LABEL INDICATE SILICON REV LAST LETTER OF TRACE CODE ON DEVICE INDICATES SILICON REV Doc ID 8951 Rev 6 119 121 Revision history ST7SCR1E4 ST7SCR1R4 17 Revision history Table 44 Document revision history Date Revision Changes Changed labelling of Capacitors on Figure 5 amp removed 3 Inserted note that C4 and must be close to the chip on Figure 5 Changed C from 30pF to 33pF section 14 4 3 on page 101 Added Figure 6 Smartcard interface reference application 64 Pin LQFP package Changed ILsink Min from 5 6mA to 5 p80 LED Pins Table Changed values in FLASH memory Table 11 Mar 15 For table in Section 14 5 2 FLASH memory added many references to note 1 2004 Section Section 14 7 3 Absolute maximum ratings electrical sensitivity Changed VESD Max from 1500 to 2000 V Section Section 14 8 1 USB Universal bus interface table merged notes 1 amp 2 into one note Replaced Errata sheet with Important Notes section Section 16 4 Important notes Figure 14 4 3 Values changed Min 90kQ Max 150kQ 12 Min 1 5mA 3 5 15 5 Split High Current values in LED Pins table for ROM and FLASH devices Sep
100. f the interrupt or Reset service routine The MCU will remain in WAIT mode until a Reset or an Interrupt occurs causing it to wake up Refer to Figure 21 Doc ID 8951 Rev 6 37 121 Power saving modes ST7SCR1E4 ST7SCR1R4 8 3 Note 38 121 Figure 21 WAIT mode flow chart WFI INSTRUCTION OSCILLATOR ON PERIPH CLOCK ON CPU CLOCK OFF I BIT CLEARED N N Y Y OSCILLATOR ON PERIPH CLOCK ON CPU CLOCK ON I BIT SET IF RESET 512 CPU CLOCK CYCLES DELAY FETCH RESET VECTOR OR SERVICE INTERRUPT Note Before servicing an interrupt the CC register is pushed on the stack The I Bit is set during the interrupt routine and cleared when the CC register is popped Halt mode The HALT mode is the MCU lowest power consumption mode The HALT mode is entered by executing the HALT instruction The internal oscillator is then turned off causing all internal processing to be stopped including the operation of the on chip peripherals The PLL must be disabled before a HALT instruction When entering HALT mode the I bit in the Condition Code Register is cleared Thus any of the external interrupts ITi or USB end suspend mode are allowed and if an interrupt occurs the CPU clock becomes active The MCU can exit HALT mode on reception of either an external interrupt on ITi an end suspend mode interrupt coming from USB peripheral or a reset The oscillator is then tur
101. fcpy directly from fosc if the PLL and the USB interface are not active Doc ID 8951 Rev 6 27 121 Supply reset and clock management ST7SCR1E4 ST7SCR1R4 Note 6 2 6 2 1 6 2 2 28 121 Table 6 Recommended values for 4 MHz crystal resonator Romax 200 250 700 Coscin 56pF 47pF 22pF Coscout 56pF 47pF 22pF Remax is the equivalent serial resistor of the crystal see crystal specification External clock An external clock may be applied to the OSCIN input with the OSCOUT pin not connected as shown on Figure 13 Figure 13 External clock source connections OSCIN OSCOUT NC EXTERNAL CLOCK Figure 14 Crystal resonator OSCIN OSCOUT Coscin Coscout Reset sequence manager RSM Introduction The reset sequence manager has two reset sources e Internal LVD reset Low Voltage Detection which includes both a power on and a voltage drop reset e Internal watchdog reset generated by an internal watchdog counter underflow as shown in Figure 16 Functional description The reset service routine vector is fixed at addresses FFFEh FFFFh in the ST7 memory map The basic reset sequence consists of 3 phases as shown in Figure 15 Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 Supply reset and clock management 1 A first delay of 0 127 cycles during whi
102. ic repetition and retry 119 Revision history 120 Doc ID 8951 Rev 6 5 121 List of tables ST7SCR1E4 ST7SCR1R4 List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 6 121 Device SUMMA aai rat eiere iaa iee ae bea D Ropa e E ede qe ee m e s 1 Detailed device 5 8 PIN description ssec secus cse x a ce d Ped OR e E 11 Hardware register memory 17 Sectors available in FLASH 19 Recommended values for 4 MHz crystal 28 Interrupt software priority 5 31 Current interrupt software 34 Interrupt vectors and corresponding bits 35 Dedicated interrupt instructi
103. interrupt or a reset If an external interrupt is received the WDG restarts counting after 514 CPU clocks In the case of the Software Watchdog option if a reset is generated the WDG is disabled reset state Recommendations e Make sure that an external event is available to wake up the microcontroller from Halt mode e Before executing the HALT instruction refresh the WDG counter to avoid an unexpected WDG reset immediately after waking up the microcontroller e When using an external interrupt to wake up the microcontroller reinitialize the corresponding I O as Input before executing the HALT instruction The main reason for Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 On chip peripherals 12 1 7 12 1 8 Note 12 2 12 2 1 this is that the I O may be wrongly configured due to external interference or by an unforeseen logical condition e The opcode for the HALT instruction is Ox8E To avoid an unexpected HALT instruction due to a program counter failure it is advised to clear all occurrences of the data value Ox8E from memory For example avoid defining a constant in ROM with the value Ox8E e Asthe HALT instruction clears the bit in the CC register to allow interrupts the user may choose to clear all pending interrupt bits before executing the HALT instruction This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake up event rese
104. ion A A M A M N IZ POP Pop from the Stack ER CC M 11 0 N Z PUSH Push onto the Stack 5 M ce RCF Reset carry flag C 0 0 RET Subroutine Return RIM Enable Interrupts 11 0 10 level 0 1 0 RLC Rotate left true C C lt A lt C reg M N Z RRC Rotate right true C gt gt reg N Z RSP Reset Stack Pointer S Max allowed SBC Subtract with Carry A M N Z C SCF Set carry flag C 1 1 SIM Disable Interrupts 11 0 11 level 3 1 1 SLA Shift left Arithmetic lt lt 0 N Z SLL Shift left Logic C lt A lt 0 reg N Z JC SRL Shift right Logic 0 gt gt reg 0 IZ JC SRA Shift right Arithmetic A7 gt A gt reg M N Z SUB Subtraction A A M A M N 2 SWAP SWAP nibbles c lt gt eg Z TNZ Test for Neg amp Zero tnz Ibl1 N Z TRAP S W trap S W interrupt 1 1 WFI Wait for Interrupt 1 0 XOR Exclusive OR A AXORM A M N Z ky Doc ID 8951 Rev 6 95 121 Electrical characteristics ST7SCR1E4 ST7SCR1R4 14 14 1 96 121 Electrical characteristics Absolute maximum ratings This product contains devices for protecting the inputs against damage due to high static voltages however it is advisable to take normal precautions to avoid applying any voltage higher than the specified maximum rated voltages For proper operation it is recommended that V and Vo be higher than Vss and lower than Vpp Reliability is enhan
105. isolation such as a serial resistor has to implemented in case another device forces the signal Refer to the Programming Tool documentation for recommended resistor values Program memory read out protection The read out protection is enabled through an option bit For Flash devices when this option is selected the program and data stored in the Flash memory are protected against read out including a re write protection When this protection is removed by reprogramming the Option Byte the entire Flash program memory is first automatically erased and the device can be reprogrammed Refer to the Option Byte description for more details Related documentation For details on Flash programming and ICC protocol refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual Doc ID 8951 Rev 6 21 121 Flash program memory ST7SCR1E4 ST7SCR1R4 4 8 22 121 Register description FLASH conirol status register FCSR Read Write Reset Value 0000 0000 00h 7 0 0 0 0 0 0 0 0 0 This register is reserved for use by Programming Tool software It controls the FLASH programming and erasing operations For details on customizing FLASH programming methods and In Circuit Testing refer to the ST7 FLASH Programming and ICC Reference Manual Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 Central processing unit 5 5 1 5 2 5 3 Central processing uni
106. ity is given in this order from the lowest to the highest MAIN IT4 IT3 IT2 IT1 ITO TLI The software priority is given for each interrupt Warning A stack overflow may occur without notifying the software of the failure Figure 19 Concurrent interrupt management nr GO SOFTWARE F F F amp F F amp F FE PRIORITY 11 10 4 peed eve gt ee TL eee Bee 3 11 il T E o b 3 1 1 amp tr Cin m 3 11 1 CE maze ned 2 m OPE RENDERE e 3 011 z E 3 3 11 9 jam RIM 3 11 8 COMAN MAN 11 10 10 4 Doc ID 8951 Rev 6 33 121 Interrupts ST7SCR1E4 ST7SCR1R4 7 5 Note 34 121 Figure 20 Nested interrupt management GF SOFTWARE PE PRIORITY 0 tee dd ve E cas os Aer an 3 11 ti cm DE MIN 3 1 1 a ig 2 gt dms 1 01 lt zo lE piece 3 11 9 a RIM i 1 a Besse jnre oet eis 3 11 E jenes enses 11 10 10 Interrupt register description CPU CC register interr
107. ivision Factor 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 USB interface USB Introduction The USB Interface implements a full speed function interface between the USB and the ST7 microcontroller It is a highly integrated circuit which includes the transceiver 3 3 voltage regulator SIE and USB Data Buffer interface No external components are needed apart from the external pull up on USBDP for full speed recognition by the USB host Main features USB Specification Version 1 1 Compliant Supports Full Speed USB Protocol Seven Endpoints including default endpoint CRC generation checking NRZI encoding decoding and bit stuffing USB Suspend Resume operations On Chip 3 3V Regulator On Chip USB Transceiver Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 On chip peripherals 12 3 3 Functional description The block diagram in Figure 29 gives an overview of the USB interface hardware For general information on the USB refer to the Universal Serial Bus Specifications document available at http www usb org Serial interface engine The SIE Serial Interface Engine interfaces with the USB via the transceiver The SIE processes tokens handles data transmission reception and handshaking as required by the USB standard It also performs frame formatting including CRC generation and checking Endpoints The Endpoint registers indicate if the microcontroller is ready to transmit r
108. lease refer to Chapter 7 Electrical of the USB specification version 1 1 108 121 Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Package characteristics 15 15 1 Package characteristics In order to meet environmental requirements ST offers this device in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark Package mechanical data Figure 44 64 pin low profile quad flat package 14x14 TA D eo Di F A2 Dim mm inches VBERRBRRBBRRBRHREL Aa E Min Typ Max Min Typ Max T A 1 60 0 063 m O i A1 0 05 0 15 0 002 0 006 Lj Lu bl H A2 1 35 1 40 1 45 0 053 0 055 0 057 oo En b 0 30 0 37 0 45 0 01210 01510 018 c 0 09 0 20 0 004 0 008 e D 16 00 0 630 Eu EU Di 14 00 0 551 EE E 16 00 0 630 m fo 1 14 00 0 551 0 80 0 031 Eu o 35 7 0 35 7 zz Ld L L 0 45 0 60 0 75 0 018 0 024 0 0
109. microcontroller option list Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points Figure 46 Sales type coding rules Family Version Code Sub family Number of pins ROM Size Code ST7 1 R 4 1 1 Standard 0 to 70 C T LQFP 4 16K R 64 pins No letter ROM M Plastic SO E 24pins F Flash U QFN P FASTROM Optional codes Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 Device configuration and ordering information Table 40 Ordering information 1 Program RAM Sales type memory bytes bytes Package ST7SCR1R4T1 xxx or ST7SCR1T1 xxx 2 16K ROM ST7PSCRI1R4T1 xxx 16K FASTROM LQFP64 ST7FSCR1R4T1 16K Flash 768 ST7SCR1E4M1 xxx or ST7SCR1M1 xxx 2 16K ROM ST7PSCR1E4M1 xxx 16K FASTROM S024 ST7FSCR1E4U1 16K Flash ST7SCR1E4U1 xxx 2 16K ROM QFN24 1 stands for the ROM or FASTROMcode name assigned by STMicroelectronics 2 New sales type coding rules for this device configuration exist and are shown without coding for the number of pins and ROM size Doc ID 8951 Rev 6 113 121 Device configuration and o
110. mmended reflow oven profile for these packages Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Device configuration and ordering information 16 16 0 1 Device configuration and ordering information Each device is available for production in user programmable versions High Density FLASH as well as in factory coded versions ROM FASTROM ST7SCR devices are ROM versions ST7PSCR devices are Factory Advanced Service Technique ROM FASTROM versions they are factory programmed FLASH devices ST7FSCR FLASH devices are shipped to customers with a default content FFh This implies that FLASH devices have to be configured by the customer using the Option Byte while the ROM devices are factory configured Option bytes The 8 option bits from the Flash are programmed through the static option byte SOB1 The description of each of these 8 bits is given below Static option Byte SOB1 OPT OPT 7 6 5 4 3 2 1 0 WDGSW NEST ISOCLK RETRY FMP_R OPT7 6 Reserved OPT5 WDGSW Hardware or software watchdog This option bit selects the watchdog type 0 Hardware watchdog always activated 1 Software watchdog to be activated by software OPT4 NEST nterrupt Controller This bit enables the nested Interrupt Controller 0 Nested interrupt controller disabled 1 Nested interrupt controller enabled ISOCLK Clock source selection 0 Card clock is generated by the divider 48MH
111. n Register description TBU counter value register TBUCV Read Write Reset Value 0000 0000 00h 7 0 CV7 CV6 CV5 4 CV2 CV1 CVO Bits 7 0 CV 7 0 Counter Value This register contains the 8 bit counter value which can be read and written anytime by software It is continuously incremented by hardware if TCEN 1 TBU control status register TBUCSR Read Write Reset Value 0000 0000 00h 7 0 0 0 OVF ITE TCEN PR2 PR1 PRO Bits 7 6 Reserved Forced by hardware to 0 Bit 5 OVF Overflow Flag This bit is set only by hardware when the counter value rolls over from FFh to OOh It is cleared by software reading the TBUCSR register Writing to this bit does not change the bit value 0 No overflow 1 Counter overflow Doc ID 8951 Rev 6 55 121 On chip peripherals ST7SCR1E4 ST7SCR1R4 12 3 12 3 1 12 3 2 56 121 Bit 4 ITE Interrupt enabled This bit is set and cleared by software 0 Overflow interrupt disabled 1 Overflow interrupt enabled An interrupt request is generated when OVF 1 Bit 3 TCEN TBU Enable This bit is set and cleared by software 0 TBU counter is frozen and the prescaler is reset 1 TBU counter and prescaler running Bits 2 0 PR 2 0 Prescaler Selection These bits are set and cleared by software to select the prescaling factor PR2 PR1 PRO Prescaler D
112. n a card is inserted When the CRDIRF bit of the CRDSR is set it indicates that a card is present To be able to power on the smartcard card presence is mandatory Removing the smartcard will automatically start the SO7816 3 card deactivation sequence see Section Card deactivation sequence Doc ID 8951 Rev 6 73 121 On chip peripherals ST7SCR1E4 ST7SCR1R4 74 121 There is no hardware debouncing The CRDIRF bit changes whenever the level on the CRDDET pin changes The card switch can generate an interrupt which can be used to wake up the device from suspend mode and for software debouncing Three different cases can occur e The microcontroller is in run mode waiting for card insertion Card insertion generates an interrupt and the CRDIRF bit in the CRDSR register is set Debouncing is managed by software After the time required for debouncing if the CRDIRF bit is set the CRDVCC bit in the CRDCR register is set by software to apply the selected voltage to the CRDVCC pin e Themicrocontroller is in suspend mode and a card is inserted The ST7 is woken up by the interrupt The card insertion is then handled in the same way as in the previous case e The card is removed CRDIRF bit is reset without hardware debouncing Insertion Removal interrupt is generated if enabled by the CRDIRM bit in the MISCR2 register The CRDVCC bit is immediately reset by hardware starting the card deactivation sequen
113. ne should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack As a consequence of the IRET instruction the 11 and 10 bits will be restored from the stack and the program in the previous level will resume Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Interrupts Table 7 Interrupt software priority levels Interrupt software priority Level 1 10 Level 0 main 1 0 Low Level 1 0 1 Level 2 0 0 High Level 3 interrupt disable 1 1 Figure 17 Interrupt processing flowchart Interrupt has the same ora lower software priority than current one Y FETCH NEXT THE INTERRUPT INSTRUCTION STAYS PENDING ozg SOS 255 Bor Y caa RET aso 258 N 5 25 Y Y RESTORE X A EXECUTE FROM STACK INSTRUCTION STACK PC X A CC Y Y LOAD 11 0 FROM INTERRUPT SW REG LOAD PC FROM INTERRUPT VECTOR Servicing pending interrupts As several interrupts can be pending at the same time the interrupt to be taken into account is determined by the following two step process e the highest software priority interrupt is serviced e if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first Figure 18 describes this decision process Figure 18 Priority decision process
114. ned on and a stabilization time is provided before releasing CPU operation The stabilization time is 512 CPU clock cycles Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Power saving modes After the start up delay the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up Figure 22 HALT mode flow chart HALT INSTRUCTION OSCILLATOR PERIPH CLOCK CPU CLOCK 1 INTERRUPTS EXTERNAL OFF OFF OFF CLEARED OSCILLATOR PERIPH CLOCK CPU CLOCK I BIT ON ON ON SET 512 CPU CLOCK CYCLES DELAY FETCH RESET VECTOR OR SERVICE INTERRUPT Note Before servicing an interrupt the CC register is pushed on the stack The I Bit is set during the interrupt routine and cleared when the CC register is popped Doc ID 8951 Rev 6 39 121 ports ST7SCR1E4 ST7SCR1R4 9 9 1 9 2 Note 40 121 ports Introduction The I O ports offer different functional modes e transfer of data through digital inputs and outputs and for specific pins e alternate signal input output for the on chip peripherals e external interrupt detection An I O port is composed of up to 8 pins Each pin can be programmed independently as digital input with or without interrupt generation or digital output Functional description Each port is as
115. ns that means when a device belongs to Class A it exceeds the JEDEC standard B Class strictly covers all the JEDEC criteria international standard 14 8 Communication interface characteristics 14 8 1 USB Universal bus interface Table 38 USB DC electrical characteristics Parameter Symbol Conditions Min Max Unit Input Levels Differential Input Sensitivity VDI D D 0 2 Differential Common Mode Range VCM Includes VDI range 0 8 2 5 V Single Ended Receiver Threshold VSE 1 3 2 0 Output Levels Static Output Low VOL RL of 1 5K ohms to 3 6v 0 3 V Static Output High VOH RL of 15K ohm to Vss 2 8 3 6 USBVCC voltage level USBV Vpp 5v 3 00 3 60 Note RL is the load connected on the USB drivers All the voltages are measured from the local ground potential Figure 43 USB Data signal rise and fall time Differential Data Lines VCRS Crossover aa Points d ky Doc ID 8951 Rev 6 107 121 Electrical characteristics ST7SCR1E4 ST7SCR1R4 Table 39 USB Full speed electrical characteristics Parameter Symbol Conditions Min Max Unit Driver characteristics Rise time tr CL 50 pF 4 20 ns Fall Time tf Note 1 CL 50 pF 4 20 ns Fuse Fall Te trim tr tf 90 110 matching Output signal VCRS 1 3 2 0 Crossover Voltage 1 Measured from 10 to 90 of the data signal For more detailed informations p
116. ns to ST7FLITE1xB Product Optimization AN 982 Using ST7 with Ceramic Resonator AN1014 How to Minimize the ST7 Power Consumption 116 121 Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Device configuration and ordering information Table 42 ST7 Application notes continued Identification Description AN1015 Software Techniques for Improving Microcontroller EMC Performance AN1040 Monitoring the Vbus Signal for USB Self Powered Devices AN1070 ST7 Checksum Self Checking Capability AN1181 Electrostatic Discharge Sensitive Measurement AN1324 Calibrating the RC Oscillator of the ST7FLITEO MCU Using the Mains AN1502 Emulated Data EEPROM with ST7 HDFLASH Memory AN1529 Extending the Current amp Voltage Capability on the ST7265 VDDF Supply AN1530 Accurate Timebase for Low cost ST7 Applications with Internal RC Oscillator AN1605 Using an Active RC to Wakeup the ST7LITEO from Power Saving Mode AN1636 Understanding and Minimizing ADC Conversion Errors AN1828 PIR Passive Infrared Detector Using the ST7FLITE05 09 SUPERLITE AN1946 Sensorless BLDC Motor Control and BEMF Sampling Methods with ST7MC AN1953 PFC for ST7MC Starter Kit AN1971 ST7LITEO Microcontrolled Ballast Programming and Tools AN 978 ST7 Visual DeVELOP Software Key Debugging Features AN 983 Key Features of the Cosmic ST7 C Compiler Package AN 985 Executing Code In ST7 RAM
117. nstruction Function NOP No operation TRAP S W Interrupt WFI Wait For Interrupt Low Power Mode HALT Halt Oscillator Lowest Power Mode RET Sub routine Return IRET Interrupt Sub routine Return SIM Set Interrupt Mask level 3 RIM Reset Interrupt Mask level 0 SCF Set Carry Flag RCF Reset Carry Flag RSP Reset Stack Pointer LD Load CLR Clear PUSH POP Push Pop to from the stack INC DEC Increment Decrement TNZ Test Negative or Zero CPL NEG 1 or 2 Complement MUL Byte Multiplication SLL SRL SRA RLC RRC Shift and Rotate Operations SWAP Swap Nibbles Doc ID 8951 Rev 6 89 121 Instruction set ST7SCR1E4 ST7SCR1R4 13 1 2 13 1 3 13 1 4 13 1 5 90 121 Immediate Immediate instructions have two bytes the first byte contains the opcode the second byte contains the operand value Immediate instruction Function LD Load CP Compare BCP Bit Compare AND OR XOR Logical Operations ADC ADD SUB SBC Arithmetic Operations Direct In Direct instructions the operands are referenced by their memory address The direct addressing mode consists of two sub modes Direct short The address is a byte thus requires only one byte after the opcode but only allows 00 FF addressing space Direct long The address is a word thus allowing 64 Kbyte addressing space but requires 2 bytes af
118. ntroduction The Smartcard Interface CRD provides all the required signals for acting as a smartcard interface device The interface is electrically compatible with and certifiable to the 1507816 EMV GSM and WHQL standards Both synchronous e g memory cards and asynchronous smartcards e g microprocessor cards are supported The CRD generates the required voltages to be applied to the smartcard lines The power off sequence is managed by the CRD Card insertion or card removal is detected by the CRD using a card presence switch connected to the external CRDDET pin If a card is removed the CRD automatically deactivates the smartcard using the 1507816 deactivation sequence An maskable interrupt is generated when a card is inserted or removed Doc ID 8951 Rev 6 69 121 On chip peripherals ST7SCR1E4 ST7SCR1R4 12 4 2 12 4 3 70 121 Any malfunction is reported to the microcontroller via the Smartcard Interrupt Pending Register CRDIPR and Smartcard Status CRDSR Registers Main features Support for ISO 7816 3 standard Character mode 1 transmit buffer and 1 receive buffer 4 MHz fixed card clock 11 bit etu elementary time unit counter 9 bit guardtime counter 24 bit general purpose waiting time counter Parity generation and checking Automatic character repetition on parity error detection in transmission mode Automatic retry on parity error detection in reception mode Card power off deactivation
119. nued Pin n Level Port Control amp Main x Pin name 5 input utpat function Alternate function i E E iba a after reset d s 2 7 4 NC Not Connected 5 4 7 C4 Cr X X Smartcard C4 6 5 8 CRDIO X X X Smartcard I O 6 9 C8 X X Smartcard C8 8 3 GND S Ground 9 PBO X Port Bo 10 1 X 11 2 X Port B2 12 PB3 X X 13 PB4 X X Port B4 14 PB5 X Port B5 15 PB6 X Port Be 16 PB7 X Port B7 17 7 10 CRDDET X Smartcard Detection 18 VDD S Power Supply voltage 4V 5 5V IS Be d CDATA an O Cr ee Input ape VOGT 5 qux es A eee Input 21 PA2 WAKUP2 Cy X X X PortA2 Interrupt 22 PA3 WAKUP2 VO Cr Port Interrupt 23 PDO X X Port Do 24 PD1 Cr X Port D1 25 PD2 Cr X Port D2 26 PD3 X Port 27 PD4 Cr X X PortD4 28 5 X X Port D5 29 PD6 X X Port De 30 PD7 X X PortD7 31 11 14 OSCIN Cr Input Output Oscillator pins These pins connect a 4MHz parallel resonant crystal or 32 12 15 OSCOUT an external source to the on chip oscillator 33 VDD S Power Supply voltage 4V 5 5V 12 121 Doc ID 8951 Rev 6 ST7SCR1E4 ST7S
120. on counter register CNT2RXR Read Write Reset Value 0000 0000 00h 7 0 0 CNT6 CNT5 CNT4 CNT3 CNT2 CNT CNTO This register contains the allocated buffer size for endpoint 2 reception setting the maximum number of bytes the related endpoint can receive with the next OUT transaction Doc ID 8951 Rev 6 67 121 On chip peripherals ST7SCR1E4 ST7SCR1R4 At the end of a reception the value of this register is the max size decremented by the number of bytes received to determine the number of bytes received the software must subtract the content of this register from the allocated buffer size Transmission counter register CNT2TXR Read Write Reset Value 0000 0000 00h 7 0 0 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNTO This register contains the number of bytes to be transmitted by Endpoint 2 at the next IN token addressed to it Table 23 USB register map and reset values Address i Register 6 5 4 3 2 1 0 20 USBISTR CTR 0 SOVR ERR SUSP ESUSP RESET SOF Reset Value 0 0 0 0 0 0 0 21 USBIMR CTRM 0 SOVRM ERRM SUSPM ESUSPM RESETM SOFM Reset Value 0 0 0 0 0 0 0 22 USBCTLR RSM EU 0 DM PDWN FSUSP FRES Reset Value 1 1 0 0 0 23 DADDR ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADDO Reset Value 0 0 0 0 0 0 0 24 USBSR PID1 PIDO IN OUT 0 0 2 1 Reset Value 0 0 0 0 0 EPOR CTRO DTOG_T ST
121. on set 35 Interrupt mapping IRR IRR IRA Rr 36 pin functions iiaia aaye a gie RR RR RR RR Rr 40 Port A description iue per oder beans Een rep ide eda deca Re de a 41 Port B and D description liiis re 42 Port C description 200000644008 nx Shwe Vade dese ee 43 ports register RR RIRIRIRR RR rn 45 Register map and reset 49 Watchdog timing fCPU 8 72 51 Transmission status encoding 64 Reception status 64 Transmission status encoding 66 Reception status 67 USB register map and reset values 68 Register map and reset 86 CPU addressing mode overview 88 Instructions supporting direct indexed indirect and indirect indexed addressing modes 91 Instruction set overview e A 93 Thermal 5 97 Current injection on i o port and control pins
122. pt pending 1 TXBE interrupt pending Bit 6 Reserved Bit 5 IOVF Card Overload Current interrupt pending This bit is set by hardware when a IOVF event occurs and the IOVFM bit is set 0 No IOVF interrupt pending 1 IOVF interrupt pending Bit 4 VCRDP Card Voltage Error interrupt pending This bit is set by hardware when the VCARDOK bit goes from 1 to 0 while the VCRDM bit is set 0 No VCRD interrupt pending 1 VCRD interrupt pending Bit 3 WTP Waiting Timer Overflow interrupt pending This bit is set by hardware when a WTP event occurs and the WTPM bit is set 0 No WT interrupt pending 1 WT interrupt pending Bit 2 TXCP Transmitted character interrupt pending This bit is set by hardware when a character is transmitted and the TXCM bit is set It indicates that the CRDTXB buffer can be loaded with the next character to be transmitted 0 No TXC interrupt pending 1 TXC interrupt pending Bit 1 RXCP Received character interrupt pending This bit is set by hardware when a character is received and the RXCM bit is set It indicates that the CRDRXB buffer can be read Doc ID 8951 Rev 6 85 121 On chip peripherals ST7SCR1E4 ST7SCR1R4 0 No RXC interrupt pending 1 RXC interrupt pending Bit PARP Parity Error interrupt pending This bit is set by hardware when a PAR event occurs and the PARM bit is set 0 No PAR interrupt pending 1 PAR interrupt pending Smartcard transmit buffer CRDTXB
123. r 2 00h R W 001Eh MISCR3 Miscellaneous Register 3 00h R W 001Fh MISCR4 Miscellaneous Register 4 00h R W ky Doc ID 8951 Rev 6 17 121 Register and memory map ST7SCR1E4 ST7SCR1R4 18 121 Table 4 Hardware register memory map continued Address Block Register Register name heset Remarks label status 0020h USBISTR USB Interrupt Status Register 00h R W 0021h USBIMR USB Interrupt Mask Register 00h R W 0022h USBCTLR USB Control Register 06h R W 0023h DADDR Device Address Register 00h R W 0024h USBSR USB Status Register 00h R W 0025h EPOR Endpoint 0 Register Oxh R W 0026h CNTORXR EP 0 Reception Counter Register 00h R W 0027h CNTOTXR EP 0 Transmission Counter Register 00h R W 0028h EP1TXR EP 1 Transmission Register 00h R W 0029h CNT1TXR EP 1 Transmission Counter Register 008 R W 002Ah USB EP2RXR EP 2 Reception Register 00h R W 002Bh CNT2RXR EP 2 Reception Counter Register Oxh R W 002Ch EP2TXR EP 2 Transmission Register 00h R W 002Dh CNT2TXR 2 Transmission Counter Register 00h R W 002Eh 3 Transmission Register 00h R W 002Fh CNT3TXR EP Transmission Counter Register 008 R W 0030h EP4TXR EP 4 Transmission Register 00h R W 0031h CNT4TXR 4 Transmission Counter Register 008 R W 0032h EP5TXR EP 5 Transmission Register 00h R W 0033h CNT5TXR EP 5 Transmission Counter Register 008 R W 0034h ERRSR Error Status Register 00h R W 0035h TBU TBUCV Timer counter value 00h R W 0036h TBUCSR Timer control status
124. rd and while the application is running e ICT In Circuit Testing for downloading and executing user application test patterns in RAM e Read out protection e Register Access Security System RASS to prevent accidental programming or erasing Structure The Flash memory is organized in sectors and can be used for both code and data storage Depending on the overall FLASH memory size in the microcontroller device there are up to three user sectors see Table 5 Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required The first two sectors have a fixed size of 4 Kbytes see Figure 8 They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 FOOOh FFFFh Table 5 Sectors available in FLASH devices Flash Memory Size bytes Available Sectors 4K Sector 0 8K Sectors 0 1 gt 8K Sectors 0 1 2 Doc ID 8951 Rev 6 19 121 Flash program memory ST7SCR1E4 ST7SCR1R4 4 4 Note 4 5 20 121 Figure 8 Memory map and sector address 16K USER FLASH MEMORY SIZE xe CO00h ex user program 8 Kbytes SECTOR 2 a DFFFh ex user data E000h 4 Kbytes d library EFFFh user system library 4 Kbytes 3 fra 0 IAP BootLoader FFFFh ICP In circuit programming To perform ICP
125. rdering information ST7SCR1E4 ST7SCR1R4 Figure 47 ST7SCR microcontroller option list opl_7scr txt ST7SCR MICROCONTROLLER OPTION LIST Last update July 2009 Customer Address Contact Phone No Reference ROM Code ee The ROM code name is assigned by STMicroelectronics ROM code must be sent in S19 format Hex extension cannot be processed Device Type Memory Size Package check only one option ROM Device 16K so24 1 STZSCR1E4M1 QFN24 IL ST7scRiE4U1 LQFP64 IL 1 StT7ScR1R4T1 FASTROM Device 16K SO24 1 STZPSCR1E4M1 LQFP64 IL 1 ST7PSCR1IR4T1 Conditioning check only one option Packaged Product Die Product dice tested at 25 C only PAPEL ncn Muro Pcr Ir M Tape amp Reel Tape amp Reel Tray CLQFP package only Inked wafer L Tube SO package only Sawn wafer on sticky foil Note Die product only for ROM device Special Marking No ve Authorized characters are letters digits and spaces only Maximum character count S024 13 char max QFN24 7 char max LQFP64 10 char max Watchdog WDGSW 1 Software Activation Hardware Activation Nested Interrupts NEST ENABLED Nested Interrupts DISABLED Non Nested Interrupts Iso Clock Source ISOCLK
126. sc and T4 unless otherwise specified 14 5 1 RAM and hardware registers Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode HALT mode or RESET 2 V 1 Minimum Vpp supply voltage without losing data stored in RAM in HALT mode or under RESET or in hardware registers only in HALT mode Not tested in production 14 5 2 FLASH memory Operating Conditions fcp 8 MHz Table 34 Dual voltage flash memory Symbol Parameter Conditions Min Typ Max Unit Read mode 8 Operating Frequency Write Erasemode g MHz 25 Vpp Programming Voltage 4 0V lt Vpp lt 5 5V 11 4 12 6 V Ipp Vpp Current Write Erase 30 mA typp Internal Vpp Stabilization Time 10 us Data Retention lt 55 C 40 years Naw _ Write Erase Cycles 25 100 cycles 1 Refer to the Flash Programming Reference Manual for the HDFlash typical programming and erase timing values Warning not connect 12V to Vpp before Vpp is powered on as this may damage the device Figure 42 Two typical applications with Vpp VPP PROGRAMMING eee VPP EMEN TOOL ST72XXX ST72XXX 102 121 Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Electrical characteristics
127. sequence generation Manual mode for driving the card I O directly for synchronous protocols Functional description Figure 31 gives an overview of the smartcard interface Figure 31 Smartcard interface block diagram CRDC4 4 MHz 4 CRDC8 POWER OFF LOGIC p CRDVCC a CRD CRD CRD CRD CR ETU COUNTER SEL ef 8 CLK RST VCC 4 CRDRST COMMUNICATIONS CONTROL CLOCK CRDCLK CONTROL 9 BIT GUARDTIME COUNTER 24 BIT WAITING TIME COUNTER PARITY GENERATION CHECKING CRD INTERRUPT CRDIO UART SHIFT REGISTER ban UART RECEIVE BUFFER UART TRANSMIT BUFFER CRDRXB CRDTXB CARD DETECTION CRDDET LOGIC CARD INSERTION REMOVAL INTERRUPT Power supply management Smartcard Power Supply Selection The Smartcard interface consists of a power supply output on the CRDVCC pin and a set of card interface I Os which are powered by the same rail Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 On chip peripherals Note The card voltage CRDVCC is user programmable via the VCARD 1 0 bits in the CRDCR register refer to the Smartcard Interface section Four card supply voltages can be selected 5 V 3 V 1 8 V or 0 V The internal step up converter must be activated to
128. ser can write a value at any time in the TBUCV register Programming example In this example timer is required to generate an interrupt after a delay of 1 ms Assuming that fopy is 8 MHz and a prescaler division factor of 256 will be programmed using the PR 2 0 bits in the TBUCSR register 1 ms 32 TBU timer ticks In this case the initial value to be loaded in the TBUCV must be 256 32 224 EOh ld A EOh ld TBUCV A Initialize counter value ld A 1Fh ld TBUCSR A Prescaler factor 256 interrupt enable TBU enable Figure 28 TBU block diagram MSB LSB TBU 8 BIT UPCOUNTER TBUCV REGISTER TBU PRESCALER 4 lt fopu 1 0 0 OVF PR2 PR1 PRO TBUCSR REGISTER TBU INTERRUPT REQUEST Doc ID 8951 Rev 6 ky ST7SCR1E4 ST7SCR1R4 On chip peripherals 12 2 5 12 2 6 Note 12 2 7 Low power modes Mode Description WAIT No effect on TBU HALT TBU halted Interrupts Enable control Interrupt event Event flag bit Exit from Wait Exit from Halt Counter Overflow Event OVF ITE Yes No The OVF interrupt event is connected to an interrupt vector see Interrupts chapter It generates an interrupt if the ITE bit is set in the TBUCSR register and the I bit in the CC register is reset RIM instructio
129. sociated to 4 main registers e Data Register DR e Data Direction Register DDR e Option Register OR e Pull Up Register PU Each I O pin may be programmed using the corresponding register bits in DDR register bit X corresponding to pin X of the port The same correspondence is used for the DR register Table 12 pin functions DDR MODE 0 Input 1 Output Input modes The input configuration is selected by clearing the corresponding DDR register bit In this case reading the DR register returns the digital value applied to the external All the inputs are triggered by a Schmitt trigger When switching from input mode to output mode the DR register should be written first to output the correct value as soon as the port is configured as an output Interrupt function When an is configured in Input with Interrupt an event on this can generate an external Interrupt request to the CPU The interrupt sensitivity is given independently according to the description mentioned in the ITRFRE interrupt register Each pin can independently generate an Interrupt request Each external interrupt vector is linked to a dedicated group of I O port pins see Interrupts section If more than one input pin is selected simultaneously as interrupt source this is logically ORed For this reason if one of the interrupt pins is tied low it masks the other ones Doc ID 8951 Rev 6 ST7SCR1E4
130. t Introduction This CPU has a full 8 bit architecture and contains six internal registers allowing efficient 8 bit data manipulation Main features Enable executing 63 basic instructions Fast 8 bit by 8 bit multiply 17 main addressing modes with indirect addressing mode Two 8 bit index registers 16 bit stack pointer Low power HALT and WAIT modes Priority maskable hardware interrupts Non maskable software hardware interrupts CPU registers The 6 CPU registers shown in Figure 10 are not present in the memory mapping and are accessed by specific instructions Accumulator A The Accumulator is an 8 bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data Index registers X and Y These 8 bit registers are used to create effective addresses or as temporary storage areas for data manipulation The Cross Assembler generates a precede instruction PRE to indicate that the following instruction refers to the Y register The Y register is not affected by the interrupt automatic procedures Program counter PC The program counter is a 16 bit register containing the address of the next instruction to be executed by the CPU It is made of two 8 bit registers PCL Program Counter Low which is the LSB and PCH Program Counter High which is the MSB Doc ID 8951 Rev 6 23 121 Central processing unit ST7SCR1E4 ST7SCR1R4 24 121 Figure 10
131. t or external interrupt Interrupts None Register description Control register CR Read Write Reset Value 0111 1111 7Fh 7 0 WDGA T6 T5 T4 T2 T1 TO Bit 7 WDGA Activation bit This bit is set by software and only cleared by hardware after a reset When WDGA 1 the watchdog can generate a reset 0 Watchdog disabled 1 Watchdog enabled This bit is not used if the hardware watchdog option is enabled by option byte Bit 6 0 T 6 0 7 bit timer MSB to LSB These bits contain the decremented value A reset is produced when it rolls over from 40h to 3Fh T6 becomes cleared Time base unit TBU Introduction The Timebase unit TBU can be used to generate periodic interrupts Doc ID 8951 Rev 6 53 121 On chip peripherals ST7SCR1E4 ST7SCR1R4 12 2 2 12 2 3 12 2 4 54 121 Main features 8 bit upcounter Programmable prescaler Period between interrupts 8 1ms at 8 MHz fcpy Maskable interrupt Functional description The TBU operates as a free running upcounter When the TCEN bit in the TBUCSR register is set by software counting starts at the current value of the TBUCV register The TBUCV register is incremented at the clock rate output from the prescaler selected by programming the PR 2 0 bits in the TBUCSR register When the counter rolls over from FFh to 00h the OVF bit is set and an interrupt request is generated if ITE is set The u
132. ter the opcode Indexed No Offset Short Long In this mode the operand is referenced by its memory address which is defined by the unsigned addition of an index register X or Y with an offset The indirect addressing mode consists of three sub modes Indexed No Offset There is no offset no extra byte after the opcode and allows 00 FF addressing space Indexed Short The offset is a byte thus requires only one byte after the opcode and allows 00 1FE addressing space Indexed long The offset is a word thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode Indirect Short Long The required data byte to do the operation is found by its memory address located in memory pointer Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Instruction set The pointer address follows the opcode The indirect addressing mode consists of two sub modes Indirect short The pointer address is a byte the pointer size is a byte thus allowing 00 FF addressing space and requires 1 byte after the opcode Indirect long The pointer address is a byte the pointer size is a word thus allowing 64 Kbyte addressing space and requires 1 byte after the opcode 13 1 6 Indirect indexed Short Long This is a combination of indirect and short indexed addressing modes The operand is referenced by its memory address which is defined by the unsigned addition of an index register value
133. ter must be between FFh and COh see Table 18 e The WDGA bit is set watchdog enabled e The T6 bit is set to prevent generating an immediate reset e The T 5 0 bits contain the number of increments which represents the time delay before the watchdog produces a reset Table 18 Watchdog timing 8 MHz CR register initial value WDG timeout period ms Max FFh 524 288 Min COh 8 192 Doc ID 8951 Rev 6 51 121 On chip peripherals ST7SCR1E4 ST7SCR1R4 12 1 4 12 1 5 12 1 6 52 121 Figure 27 Watchdog block diagram RESET WATCHDOG CONTROL REGISTER CR WDGA T6 T5 T4 T3 T2 T1 TO 7 BIT DOWNCOUNTER CLOCK DIVIDER f CPU 65536 Software watchdog option If Software Watchdog is selected by option byte the watchdog is disabled following a reset Once activated it cannot be disabled except by a reset The T6 bit can be used to generate a software reset the WDGA bit is set and the 6 bit is cleared Hardware watchdog option If Hardware Watchdog is selected by option byte the watchdog is always active and the WDGA bit in the CR is not used Low power modes WAIT Instruction No effect on Watchdog HALT Instruction Halt mode can be used when the watchdog is enabled When the oscillator is stopped the WDG stops counting and is no longer able to generate a reset until the microcontroller receives an external
134. the USB interface up from suspend mode This interrupt is serviced by a specific vector in order to wake up the ST7 from HALT mode 0 No End Suspend detected 1 End Suspend detected Bit 1 RESET USB reset This bit is set by hardware when the USB reset sequence is detected on the bus 0 No USB reset signal detected 1 USB reset signal detected The DADDR EPOR EP1RXR EP1TXR EP2RXR and EP2TXR registers are reset by a USB reset Doc ID 8951 Rev 6 59 121 On chip peripherals ST7SCR1E4 ST7SCR1R4 Note 60 121 Bit 0 SOF Start of frame This bit is set by hardware when a SOF token is received on the USB 0 No SOF received 1 SOF received To avoid spurious clearing of some bits it is recommended to clear them using a load instruction where all bits which must not be altered are set and all bits to be cleared are reset Avoid read modify write instructions like AND XOR Interrupt mask register USBIMR Read Write Reset Value 0000 0000 00h 7 0 0 sovam ERRM suspm SSP sorm These bits are mask bits for all the interrupt condition bits included in the USBISTR register Whenever one of the USBIMR bits is set if the corresponding USBISTR bit is set and the I bit in the CC register is cleared an interrupt request is generated For an explanation of each bit please refer to the description of the USBISTR register Control register USBCTLR
135. tion about the endpoint status which are listed below Table 19 Transmission status encoding STAT TX1 STAT TXO Meaning DISABLED no function can be executed on this 0 0 endpoint and messages related to this endpoint are ignored STALL the endpoint is stalled and all transmission 0 1 requests result in a STALL handshake 1 0 the endpoint is NAKed and all transmission requests result in handshake 1 1 VALID this endpoint is enabled if an address match occurs the USB interface handles the transaction These bits are written by software Hardware sets the STAT TX and STAT RX bits to NAK when a correct transfer has occurred CTR 1 addressed to this endpoint this allows software to prepare the next set of data to be transmitted Bit 3 Reserved forced by hardware to 0 Bit 2 DTOG RX Data Toggle for reception transfers It contains the expected value of the toggle bit OZDATAO 1 DATA1 for the next data packet This bit is cleared by hardware in the first stage Setup Stage of a control transfer SETUP transactions start always with DATAO PID The receiver toggles only if it receives a correct data packet and the packet s data PID matches the receiver sequence bit Bits 1 0 STAT RX 1 0 Status bits for reception transfers These bits contain the information about the endpoint status which are listed below Table 20 Reception status encoding STAT RX1 S
136. uns bit stuffing or framing errors Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 On chip peripherals Note Note Bit 6 Reserved forced by hardware to 0 Bit 5 SOVR Setup Overrun This bit is set by hardware when a correct Setup transfer operation is performed while the software is servicing an interrupt which occurred on the same Endpoint CTRO bit in the EPOR register is still set wnen SETUP correct transfer occurs 0 No SETUP overrun detected 1 SETUP overrun detected When this event occurs the USBSR register is not updated because the only source of the SOVR event is the SETUP token reception on the Control Endpoint Bit 4 ERR Error This bit is set by hardware whenever one of the errors listed below has occurred 0 No error detected 1 Timeout CRC bit stuffing nonstandard framing or buffer overrun error detected Refer to the ERR 2 0 bits in the USBSR register to determine the error type Bit 3 SUSP Suspend mode request This bit is set by hardware when a constant idle state is present on the bus line for more than 3 ms indicating a suspend mode request from the USB The suspend request check is active immediately after each USB reset event and is disabled by hardware when suspend mode is forced FSUSP bit in the USBCTLR register until the end of resume sequence Bit 2 ESUSP End Suspend mode This bit is set by hardware when during suspend mode activity is detected that wakes
137. upt bits Read Write Reset Value 111x 1010 xAh 7 0 1 1 11 H 10 N Bit 5 3 10 Software Interrupt Priority These two bits indicate the current interrupt software priority Table 8 Current interrupt software priority Interrupt software priority Level 1 10 Level 0 main 1 0 Low Level 1 0 1 Level 2 0 0 High Level 3 interrupt disable 1 1 These two bits are set cleared by hardware when entering in interrupt The loaded value is given by the corresponding bits in the interrupt software priority registers ISPRx They can be also set cleared by software with the RIM SIM HALT WFI IRET and PUSH POP instructions see Interrupt Dedicated Instruction Set table TLI TRAP and RESET events can interrupt a level 3 program Interrupt software priority registers ISPRX Read Write bit 7 4 of ISPR3 are read only Reset Value 1111 1111 FFh Doc ID 8951 Rev 6 ST7SCR1E4 ST7SCR1R4 Interrupts Note Caution 7 0 ISPRO 11_3 lo 3 n 2 lo 2 _1 10_1 11_0 10_0 ISPR1 11_7 10_7 11_6 10_6 11_5 10_5 11_4 10_4 ISPR2 11_11 10_11 11_10 10_10 11_9 10_9 11_8 10_8 ISPR3 1 1 1 1 11_13 10_13 11_12 10_12 These four registers contain the interrupt software priority of each interrupt vector e Each interrupt vector except RESET and TRAP has corresponding bits in these registers where its own software priority is stored This correspondence is shown in th
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139. z 12 4MHz 1 Card clock is generated by the oscillator OPT2 RETRY Number of Retries for UART ISO 0 In case of an erroneous transfer character is transmitted 4 times 1 In case of an erroneous transfer character is transmitted 5 times Doc ID 8951 Rev 6 111 121 Device configuration and ordering information ST7SCR1E4 ST7SCR1R4 16 1 112 121 OPT1 Reserved must be kept at 1 FMP_R Flash memory read out protection Readout protection when selected provides a protection against program memory content extraction and against write access to Flash memory This protection is based on read anda write protection of the memory in test modes and ICP mode Erasing the option bytes when the FMP_R option is selected induce the whole user memory erasing first and the device can be reprogrammed Refer to the ST7 Flash Programming Reference Manual and section 4 6 on page 21 for more details 0 read out protection enabled 1 read out protection disabled Device ordering information and transfer of customer code Customer code is made up of the ROM contents and the list of the selected options if any The ROM contents are to be sent on diskette or by electronic means with the hexadecimal file in S19 format generated by the development tool All unused bytes must be set to FFh The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended See Figure 47 ST7SCR

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