Home

ST ST6208C ST6209C ST6210C ST6220C handbook

1. LOW LOW 8 9 A B Cc D E F Hi 1000 1001 1010 1011 1100 1101 1110 1111 Hi 2 JRANZ 4 JP 2 JRNC 4 RES 2 JRZ 4 LDI 2 JRC 4 LD sone e abc e bO rr e rr nn e a y 0006 1 pcr 2 ext 1 per 2 b d 1 per 3 imm 1 prc 1 ind 2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD di e abc e bO rr e x e a rr cob 1 per 2 ext 1 per 2 b d 1 per 1 sd 1 pre 2 dir 2 JRANZ 4 JP 2 JRNC 4 RES 2 JRZ 4 COM 2 JRC 4 CP ocio e abc e b4 rr e a e a y ddi 1 per 2 ext 1 per 2 b d 1 per 1 prc 1 ind 2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 CP aoii e abc e b4 rr e x a e a rr adii 1 per 2 ext 1 per 2 b d 1 per 1 sd 1 prc 2 dir 2 JRANZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RETI 2 JRC 4 ADD a e abc e b2 rr e e a y dio 1 per 2 ext 1 per 2 b d 1 per 1 inh 1 prc 1 ind 2 JRANZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 ADD Sio e abc e b2 rr e y e arr mie 1 per 2 ext 1 per 2 b d 1 per 1 sd 1 prc 2 dir 2 JRANZ 4 JP 2 JRNC 4 RES 2 JRZ 2 STOP 2 JRC 4 INC dii e abc e b6 rr e e y oto 1 per 2 ext 1 per 2 b d 1 per 1 inh 1 prc 1 ind 2 JRANZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 INC dii e abc e b6 rr e y a e rr ne 1 per 2 ext 1 per 2 b d 1 per 1 sd 1 prc 2 dir 2 JRANZ 4 JP 2 JRNC 4 RES 2 JRZ 2 JRC 4 LD 3000 e abc e b1 rr e e y a 2000 1 per 2 ext 1 per 2 b d 1 per 1 prc 1 ind 2 JRANZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD iooi e abc e b1
2. 0 0 0 2 c eee eee 22 5 1 4 Register Description sperre kea toda nier eaaa ee eee 22 5 2 LOW VOLTAGE DETECTOR LVD 0 ronnie ien aA a a 23 0 RESET O A das anes 24 5 3 1 Introduction ici ee ache Bde ede ee de 24 5 3 2 RESET Sequence 2 0 2 2 cece ee ee ee ee ee 24 53 39 RESET Pils eee renee er eae a ares 25 5 3 4 Watchdog Reset 0 cee eee eee 26 5 3 5 LYD ReSet 2 22 2a fa eet a Re eee ee 26 54 INTERRUPTS 2 sence hia kd wer be ec a is 27 5 5 INTERRUPT RULES AND PRIORITY MANAGEMENT 2 20 000055 28 5 6 INTERRUPTS AND LOW POWER MODES 0000 0c eee eee ee ees 28 5 7 NON MASKABLE INTERRUPT 0 000 0c eee eee eee eee 28 5 8 PERIPHERAL INTERRUPTS 0 000 cece eee eee eens 28 5 9 EXTERNAL INTERRUPTS I O PORTS 000 cece eee eee eee 29 5 9 1 Notes on using External Interrupts 0 0 0 ee eee 29 5 10 INTERRUPT HANDLING PROCEDURE 2 0 000 cece eee ene eae 30 5 10 1 Interrupt Response Time orses oiran peie p aA E a A a o A 30 5 11 REGISTER DESCRIPTION 0000s 31 6 POWER SAVING MODES 20 0 c cece eee 32 631 ANTRODUCTION sind deen tk Acta eo we A a be eee a iso 32 2 104 ky Table of Contents 6 2 _ WAT MODE Sitio tare els Sache wvetht Ha aes hghetn es aaa a aee ala ade wt S 33 6 3 STOP MODE 4 08 cited band dale eh ha dowule ent haceth nd bhawe as rca ads nd bad 34 6 4 NOTES RELATED TO WAIT
3. 91 104 ST6208C ST6209C ST6210C ST6220C 11 2 THERMAL CHARACTERISTICS Package thermal resistance junction to ambient DIP20 60 q S020 80 GAN SSOP20 115 Notes 1 The power dissipation is obtained from the formula Pp Pint PporT where Pyr is the chip internal power IppxVpp and Ppopt is the port power dissipation determined by the user 2 The average chip junction temperature can be obtained from the formula Ty Ta Pp x RthJA 92 104 ST6208C ST6209C ST6210C ST6220C 11 3 SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only Recommended glue for SMD plastic packages as design guidelines in Figure 78 and Figure 79 Heraeus PD945 PD955 m Loctite 3615 3298 Figure 78 Recommended Wave Soldering Profile with 37 Sn and 63 Pb 250 COOLING PHASE P 200 5 sec ROOM TEMPERATURE SOLDERING 150 PHASE Temp C 109 PREHEATING 50 0 Time sec 160 Figure 79 Recommended Reflow Soldering Oven Profile MID JEDEC 2 90 Tmax 220 5 C for 25 sec 200 oo 150 150 sec above 183 C 90 sec at 125 C Temp C 100 ramp down natural ramp up 2 C sec max 50 2 C sec for 50sec 0 Time sec 400 93 104 ST6208C ST6209C ST6210C ST6220C 11 4 PACKAGE SOCKET FOOTPRINT PROPOSAL Table 23 Suggested List of DIP20 Socket Types Same Package Probe Adaptor Socket Reference Footprint Socket Type Table 24 Suggested L
4. 0 00 eee 78 10 7 3ESD Pin Protection Strategy i ee erei craie eesi K E e G 80 10 8 I O PORT PIN CHARACTERISTICS 0 0000 c eee eee eee 81 10 8 1General Characteristics 0 0 cee 81 10 8 20utput Driving Current 0 2 0 2 eee 82 10 9 CONTROL PIN CHARACTERISTICS 0 000 c eee eee 85 10 9 1Asynchronous RESET Pin eirges keien a pi eee 85 TOYO 2 NM PIM ctr ane state a pe A as aa eek 86 10 10 TIMER PERIPHERAL CHARACTERISTICS 2 000 000 cece eee eee 87 10 10 1Watchdog Timer lt s creert D aee b a eee 87 10 10 28 Bit Timer aeiu ei a e eee n a a A aN 87 10 11 8 BIT ADC CHARACTERISTICS 02 0000 anana 88 11 GENERAL INFORMATION ciae 000 cece ete eee 90 11 1 PACKAGE MECHANICAL DATA 0 0000 ccc tees 90 4 104 STA 11 2 11 3 11 4 11 5 11 6 Table of Contents THERMAL CHARACTERISTICS 00 00 00 cee eee SOLDERING AND GLUEABILITY INFORMATION 0 0 005 PACKAGE SOCKET FOOTPRINT PROPOSAL 2 00 00000008 ORDERING INFORMATION 0 00 0000 cece eee TRANSFER OF CUSTOMER CODE 00 002 cece 11 6 1 FASTROM version 11 6 2ROM VERSION 12 DEVELOPMENT TOOLS 13 ST6 APPLICATION NOTES 14 SUMMARY OF CHANGES 15 TO GET MORE INFORMATION 5 104 ST6208C ST6209C ST6210C ST6220C 1 INTRODUCTION The ST6208C 09C 10C and 20C devices are low cost members of the ST62xx 8 bit HCMOS family of microcontrollers which is targe
5. Enabled Fuse is blown by STMicroelectronics Fuse can be blown by the customer Disabled Low Voltage Detector Enabled Disabled External STOP Mode Control Enabled Disabled Identifier FASTROM only Enabled Disabled Comments Oscillator Frequency in the application Supply Operating Range in the application Notes Date Signature 97 104 Y ST6208C ST6209C ST6210C ST6220C 11 6 2 ROM VERSION ROM Readout Protection If the ROM READOUT The ST6208C 09C 10C and 20C are mask pro PROTECTION option is selected a protection grammed ROM versi n of ST62T08C TO9IC fuse can be blown to prevent any access to the T10C and T20C OTP devices program memory content They offer the same functionality as OTP devices N Case the user wants ei this fuse high volt selecting as ROM options the options defined in 298 Must be applied on the Vpp pin the programmable option byte of the OTP version Figure 82 Programming wave form Figure 81 Programming Circuit PROTECT ZPD15 15V L 14v l gt t VR02003 VR02001 Note ZPD15 is used for overvoltage protection 98 104 ST6208C ST6209C ST6210C ST6220C 12 DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware and software development tools for the ST6 micro controller family Full details of tools available for Table 26 Dedicated Third Parties Development Tools the ST6 from thir
6. 1 O PORT PIN CHARACTERISTICS Conta 10 8 2 Output Driving Current Subject to general operating conditions for Vpp fosc and Ta unless otherwise specified Parameter non Tin Ms ES _ Ot Output low level voltage for a standard I O pin lo 3mA Tast25 C 08 see Figure 63 and Figure 66 lo 5mA Ta lt 85 C fT 08 V oma se 12 lio t7MA Ta lt 125 C EAN A CES Output low level voltage for a high sink O pin 2 lio 10mMA Tas85 C see Figure 64 and Figure 67 gt lo 15mA Tast25C 13 oma 1 380 137 jo TOHA Tast25 C Voo Output high level voltage for an I O pin Ta 3mA Ta lt 125 0 Vop 15 see Figure 65 and Figure 68 lor A pea lo 5mA Tas Voos Notes 1 The lig current sunk must always respect the absolute maximum rating specified in Section 10 2 2 and the sum of lio I O ports and control pins must not exceed lyss 2 The lig current source must always respect the absolute maximum rating specified in Section 10 2 2 and the sum of lio I O ports and control pins must not exceed lypp True open drain I O pins does not have Voy Figure 63 Typical Vo at Vpp 5V standard Figure 64 Typical Vo at Vpp 5V high sink Vol mV at Vdd 5V Vol V at Vdd 5V 1000_L Ta 40 C Ta 40 C Ta 95 C H 83 gt E Ta 25 C Ta 125 C H lio mA 82 104 Y I O PORT PIN CHARACTERISTICS Cont d Figure 65 Typical Voy at Vpp 5V Voh V at Vdd 5V b Ta
7. CMOS SCHMITT TRIGGER TO INTERRUPT TO ADC Depending on device See device summary on page 1 Mode tion O O Push pull output 20mA sink when available Note x Don t care y 38 104 1 0 PORTS Cont d 7 2 5 Instructions NOT to be used to access Port Data registers SET RES INC and DEC DO NOT USE READ MODIFY WRITE INSTRUC TIONS SET RES INC and DEC ON PORT DATA REGISTERS IF ANY PIN OF THE PORT IS CONFIGURED IN INPUT MODE These instructions make an implicit read and write back of the entire register In port input mode however the data register reads from the input pins directly and not from the data register latch es Since data register information in input mode is used to set the characteristics of the input pin in terrupt pull up analog input these may be unin tentionally reprogrammed depending on the state of the input pins As a general rule it is better to only use single bit instructions on data registers when the whole 8 bit port is in output mode In the case of inputs or of mixed inputs and outputs it is advisable to keep a copy of the data register in RAM Single bit in structions may then be used on the RAM copy af ter which the whole copy register can be written to the port data register ET bit datacopy S LD a datacopy LD DRA a 7 2 6 Recommendations 1 Safe I O State Switching Sequence Switching the I O ports from one state to another should be d
8. 0 Oscillator Safeguard disabled 1 Oscillator Safeguard enabled MSB OPTION BYTE LSB OPTION BYTE 15 8 7 0 EXT PRO NMI TM WD OSG Reserved CTL LVD TECT OSC Res Res PULL PULL ACT EN Defaut y xy x lxitxi xtixtxitxtixtxitx x tx tx tx Value 16 104 1577 4 CENTRAL PROCESSING UNIT 4 1 INTRODUCTION The CPU Core of ST6 devices is independent of the l O or Memory configuration As such it may be thought of as an independent central processor communicating with on chip I O Memory and Pe ripherals via internal address data and control buses 4 2 MAIN FEATURES m 40 basic instructions 9 main addressing modes m Two 8 bit index registers Two 8 bit short direct registers m Low power modes a Maskable hardware interrupts m 6 level hardware stack 4 3 CPU REGISTERS The ST6 Family CPU core features six registers and three pairs of flags available to the programmer These are described in the following paragraphs Accumulator A The accumulator is an 8 bit general purpose register used in all arithmetic cal culations logical operations and data manipula Figure 7 CPU Registers ST6208C ST6209C ST6210C ST6220C tions The accumulator can be addressed in Data Space as a RAM location at address FFh Thus the ST6 can manipulate the accumulator just like any other register in Data Space Index Registers X Y These two registers are used in In
9. CALL abc JP abc Notes abc 12 bit address Not Affected ky Not Affected 59 104 ST6208C ST6209C ST6210C ST6220C Opcode Map Summary The following table contains an opcode map for the instructions used by the ST6 LOW LOW 0 1 2 3 4 5 6 7 iy 0000 0001 0010 0011 0100 0101 0110 0111 i 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ JRC LD sont e abc e b0 rr ee e NOP e a x 0006 1 per 2 ext 1 per 3 bt 1 per pre ind 2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC JRC LDI ooi e abc e b0 rr ee e x e a nn imi 1 per 2 ext 1 pcr 3 bt 1 per 1 sd pre imm 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ JRC CP ddio e abc e b4 rr ee e e a x ooi 1 per 2 ext 1 pcr 3 bt 1 pcr prc ind 2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD JRC CPI KR e abc e b4 rree e a x e a nn 0 1 per 2 ext 1 per 3 bt 1 per 1 sd pre imm 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ JRC ADD me e abc e b2 rr ee e e a x S00 1 per 2 ext 1 per 3 bt 1 per pre ind 2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC JRC ADDI aon e abc e b2 rr ee e y e a nn mie 1 per 2 ext 1 per 3 bt 1 per 1 sd pre imm 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ JRC INC dii e abc e b6 rr ee e e x e 1 per 2 ext 1 per 3 bt 1 per pre ind 2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD JRC dii e abc e b6 rr ee e ay e ne 1 pcr 2 ext 1 pcr 3 bt 1 per 1 sd prc 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ JRC LD iSo e abc e b
10. Port A Data Register 00h R W OCih DRB Port B Data Register 00h R W 0C2h 0C3h 0C4h O Ports DDRA Port A Direction Register 00h OC5h DDRB Port B Direction Register 00h Reserved 2 Bytes OC8h cpu OR e Interrupt Option Register Write only OC9h DRWR Data ROM Window register Write only OCAh OCBh Reserved 2 Bytes Reserved 2 Bytes OCCh VO Ports ORA 2 Port A Option Register 00h R W OCDh ORB Port B Option Register 00h R W OCEh OCFh 0DOh ADC ADR A D Converter Data Register xxh Read only OD1h ADCR A D Converter Control Register 40h Ro Wo 0D2h PSCR Timer 1 Prescaler Register 0D3h Timer1 TCR Timer 1 Downcounter Register 0D4h TSCR Timer 1 Status Control Register Reserved 2 bytes 0D5h to OD7h OD8h oe WDGR Watchdog Register OFEh Pw Reserved 3 Bytes OD9h to OFEh OFFh CPU Accumulator Legend x undefined R W Read Write Ro Read only Bit s in the register Wo Write only Bit s in the register Notes 1 The contents of the I O port DR registers are readable only in output configuration In input configura tion the values of the I O pins are returned instead of the DR register contents 2 The bits associated with unavailable pins must always be kept at their reset value 3 Do not use single bit instructions SET RES on Port Data Registers if any pin of the port is configured in input mode refer to Section 7 I O PORTS on page 37 for more details 4 Depending on device Se
11. RESET PIN INTERNAL RESET RUN 24 104 The RESET vector fetch phase duration is 2 clock cycles When a reset occurs The stack is cleared The PC is loaded with the address of the Reset vector It is located in program ROM starting at address OFFEh A jump to the beginning of the user program must be coded at this address The interrupt flag is automatically set so that the CPU is in Non Maskable Interrupt mode This prevents the initialization routine from being in terrupted The initialization routine should there fore be terminated by a RETI instruction in order to go back to normal mode RESET GGG 2048 CLOCK CYCLE fin y DELAY RESET Conta 5 3 3 RESET Pin The RESET pin may be connected to a device on the application board in order to reset the MCU if required The RESET pin may be pulled low in RUN WAIT or STOP mode This input can be used to reset the internal state of the MCU and en sure it starts up correctly The pin which is con nected to an internal pull up is active low and fea tures a Schmitt trigger input A delay 2048 clock cycles added to the external signal ensures that even short pulses on the RESET pin are accepted as valid provided Vpp has completed its rising phase and that the oscillator is running correctly normal RUN or WAIT modes The MCU is kept in the Reset state as long as the RESET pin is held low Figure 14 Reset Block Diagram 1
12. pends on the original state of the MCU normal in terrupt or non maskable interrupt mode prior to entering WAIT or STOP mode as well as on the interrupt type Normal Mode If the MCU was in the main routine when the WAIT or STOP instruction was execut ed exit from Stop or Wait mode will occur as soon as an interrupt occurs the related interrupt routine is executed and on completion the instruction which follows the STOP or WAIT instruction is then executed providing no other interrupts are pending Non Maskable Interrupt Mode If the STOP or WAIT instruction has been executed during execu tion of the non maskable interrupt routine the MCU exits from Stop or Wait mode as soon as an interrupt occurs the instruction which follows the STOP or WAIT instruction is executed and the MCU remains in non maskable interrupt mode even if another interrupt has been generated Normal Interrupt Mode If the MCU was in inter rupt mode before the STOP or WAIT instruction was executed it exits from STOP or WAIT mode 36 104 as soon as an interrupt occurs Nevertheless two cases must be considered If the interrupt is a normal one the interrupt rou tine in which the WAIT or STOP mode was en tered will be completed starting with the execution of the instruction which follows the STOP or the WAIT instruction and the MCU is still in interrupt mode At the end of this routine pending interrupts will be serviced according to the
13. EPROM Retention Time vs Temperature Retention time Years 100000 10000 1000 100 10 1 40 30 20 10 10 20 30 40 100 110 120 Temperature C Notes 1 Minimum Vpp supply voltage without losing data stored in RAM in STOP mode or under RESET or in hardware reg isters only in STOP mode Guaranteed by construction not tested in production 2 Data based on reliability test results and monitored in production For OTP devices data retention and programmability must be guaranteed by a screening procedure Refer to Application Note AN886 3 The data retention time increases when the T decreases see Figure 55 76 104 y ST6208C ST6209C ST6210C ST6220C 10 7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba a ESD Electro Static Discharge positive and sis during product characterization negative is applied on all pins of the device until 10 7 1 Functional EMS a functional disturbance occurs This test conforms with the IEC 1000 4 2 standard Bisel Magnetic Susceptibility a FTB A Burst of Fast Transient voltage positive Based on a simple running application on the and negative is applied to Vpp and Vss through product toggling 2 LEDs through I O ports the a 100pF capacitor until a functional disturbance product is stressed by two electro magnetic events occurs This test conforms with the IEC 1000 4 until a failure occurs indicated by the LEDs 4 standard A device rese
14. Note Setting the STA bit must be done by a different in struction from the instruction that powers on the ADC setting the PDS bit in order to make sure the voltage to be converted is present on the pin Each conversion has to be separately initiated by writing to the STA bit The STA bit is continuously scanned so that if the user sets it to 1 while a previous conversion is in progress a new conversion is started before com pleting the previous one The start bit STA is a write only bit any attempt to read it will show a log ical O 53 104 ST6208C ST6209C ST6210C ST6220C A D CONVERTER Cont d 8 3 4 Recommendations The following six notes provide additional informa tion on using the A D converter 1 The A D converter does not feature a sample and hold circuit The analog voltage to be meas ured should therefore be stable during the entire conversion cycle Voltage variation should not ex ceed 1 2 LSB for optimum conversion accuracy A low pass filter may be used at the analog input pins to reduce input voltage variation during con version 2 When selected as an analog channel the input pin is internally connected to a capacitor Cag of typically 9pF For maximum accuracy this capaci tor must be fully charged at the beginning of con version In the worst case conversion starts one instruction 6 5 us after the channel has been se lected The impedance of the analog voltage source ASI in
15. The V reference value for a voltage drop is lower than the Vir reference value for power on in order to avoid a parasitic reset when the MCU starts run ning and sinks current on the supply hysteresis Figure 12 Low Voltage Detector Reset The LVD Reset circuitry generates a reset when Vop is below Viz when Vpp is rising Viz when Vpp is falling The LVD function is illustrated in Figure 12 If the LVD is enabled the MCU can be in only one of two states Over the input threshold voltage it is running un der full software control Below the input threshold voltage it is in static safe reset In these conditions secure operation is guaran teed without the need for external reset hardware During a Low Voltage Detector Reset the RESET pin is held low thus permitting the MCU to reset other devices Y 23 104 ST6208C ST6209C ST6210C ST6220C 5 3 RESET 5 3 1 Introduction The MCU can be reset in three ways a A low pulse input on the RESET pin a Internal Watchdog reset a Internal Low Voltage Detector LVD reset 5 3 2 RESET Sequence The basic RESET sequence consists of 3 main phases m Internal watchdog or LVD or external Reset event m A delay of 2048 clock fint cycles RESET vector fetch The reset delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state Figure 13 RESET Sequence WATCHDOG RESET LVD RESET i
16. which are se lected by the TOUT and DOUT bits see TSCR register These three modes correspond to the two clocks which can be connected to the 7 bit prescaler finr 12 or TIMER pin signal and to the output mode The settings for the different operating modes are summarized Table 13 Table 13 Timer Operating Modes Event Counter External counter clock input source Gated input External Pulse length input measurement 1 Output 0 output output Output signal generation 8 2 4 1 Gated Mode TOUT 0 DOUT 1 In this mode the prescaler is decremented by the Timer clock input but only when the signal on the TIMER pin is held high fjy7 12 gated by TIMER pin See Figure 28 and Figure 29 This mode is selected by clearing the TOUT bit in the TSCR register i e as input and setting the DOUT bit Note In this mode if the TIMER pin is multi plexed the corresponding port control bits have to be set in input with pull up configuration through 48 104 the DDR OR and DR registers For more details please refer to the I O Ports section Figure 28 ftrimer Clock in Gated Mode PRESCALER Figure 29 Gated Mode Operation COUNTER VALUE VALUE 1 VALUE 2 TIMER PIN PULSE LENGTH AY TIMER CLOCK Y ST6208C ST6209C ST6210C ST6220C 8 BIT TIMER Conta 8 2 4 2 Event Counter Mode TOUT 0 DOUT 0 In this mode the TIMER pin is the input cl
17. 256 locations of Data space memory can be set or cleared Bit Test amp Branch Bit test and branch addressing mode is a combination of direct addressing and relative addressing Bit test and branch instruc tions are three bytes long The bit identification and the test condition are included in the opcode byte The address of the byte to be tested is given in the next byte The third byte is the jump dis placement which is in the range of 127 to 128 This displacement can be determined using a la bel which is converted by the assembler Indirect In indirect addressing mode the byte processed by the register indirect instruction is at the address pointed to by the content of one of the indirect registers X or Y 80h 81h The indirect register is selected by bit 4 of the opcode Register indirect instructions are one byte long Inherent In inherent addressing mode all the in formation necessary for executing the instruction is contained in the opcode These instructions are one byte long Y 9 3 INSTRUCTION SET The ST6 offers a set of 40 basic instructions which when combined with nine addressing modes yield 244 usable opcodes They can be di vided into six different types load store arithme tic logic conditional branch control instructions jump call and bit manipulation The following par agraphs describe the different types All the instructions belonging to a given type are presented in individual tab
18. 57 Typical Equivalent ESD Circuits C 100pF HUMAN BODY MODEL HIGH VOLTAGE PULSE GENERATOR 78 104 HIGH VOLTAGE PULSE GENERATOR UNO L A01 07 N CL 200pF MACHINE MODEL ST6208C ST6209C ST6210C ST6220C EMC CHARACTERISTICS Cont d 10 7 2 2 Static and Dynamic Latch Up LU 3 complementary static tests are required DLU Electro Static Discharges one positive then one negative test are applied to each pin on 10 parts to assess the latch up performance A supply overvoltage applied to each power supply pin a current injection applied to each input output and configurable I O pin and a power supply switch sequence are performed on each sample This test conforms to the ElA of 3 samples when the micro is running to assess the latch up performance in dynamic mode Power supplies are set to the typical values the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode This test conforms to the IEC1000 4 2 and SAEJ1752 3 standards and is described in Figure 58 For more details refer to the AN1181 application note JESD 78 IC latch up standard For more details refer to the AN1181 application note Electrical Sensitivities Ta 25 C Conditions Ta 85 C DLU Dynamic latch up class Notes 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC spec ifica
19. PC INTO THE STACK SELECT INTERRUPT FLAGS AN INTERRUPT REQUEST AND INTERRUPT MASK If a latch is present on the interrupt source line Table 7 Interrupt Response Time 11 CPU cycles Maximum One CPU cycle is 13 external clock cycles thus 11 CPU cycles 11 x 13 8M 17 875 us with an 8 MHz external quartz y 5 11 REGISTER DESCRIPTION INTERRUPT OPTION REGISTER IOR Address 0C8h Write Only Reset status 00h 7 0 Ee aes Caution This register is write only and cannot be accessed by single bit operations SET RES DEC Bit 7 Reserved must be cleared Bit 6 LES Level Edge Selection bit 0 Falling edge sensitive mode is selected for inter rupt vector 1 Table 8 Interrupt Mapping Vector Source number Block Register Exit Description opal from STOP ST6208C ST6209C ST6210C ST6220C 1 Low level sensitive mode is selected for inter rupt vector 1 Bit 5 ESB Edge Selection bit 0 Falling edge mode on interrupt vector 2 1 Rising edge mode on interrupt vector 2 Bit 4 GEN Global Enable Interrupt 0 Disable all maskable interrupts 1 Enable all maskable interrupts Note When the GEN bit is cleared the NMI inter rupt is active but cannot be used to exit from STOP or WAIT modes Bits 3 0 Reserved must be cleared Vector Priority Order Address e PERRA Vector 0 Non Maskable Interrupt FFCh FFDh migren FFAh FFBh nori NOT USED FF8h FF9h Vec
20. ST6210C ST6220C SUPPLY CURRENT CHARACTERISTICS Cont d 10 4 2 WAIT Modes fosc 32kHz fosc 1 MHz fosc 2MHz fosc 4MHz fosc 8MHz fosc 32kHz fosc 1 MHz fosc 2MHz fosc 4MHz fosc 8MHz 4 5V lt Vpp lt 6 0V fosc 32kHz fosc 1 MHz fosc 2MHz fosc 4MHz fosc 8MHz fosc 32kHz fosc 1 MHz fosc 2MHz fosc 4MHz fosc 8MHz fosc 32kHz fosc 1 MHz fosc 2MHz fosc 4MHz fosc 8MHz 3V lt Vpp lt 3 6V ROM devices OTP devices ROM devices OTP devices fosc 32kHz fosc 1 MHz fosc 2MHz fosc 4MHz fosc 8MHz Supply current in WAIT mode Option bytes not programmed see Figure 44 Supply current in WAIT mode 2 Option bytes programmed to 00H see Figure 45 Supply current in WAIT mode see Figure 46 Supply current in WAIT mode Option bytes not programmed see Figure 44 Supply current in WAIT mode Option bytes programmed to 00H see Figure 45 Supply current in WAIT mode 2 Option bytes not programmed see Figure 46 Notes 1 Typical data are based on T 25 C Vpp 5V 4 5V lt Vpp lt 6 0V range and Vpp 3 3V 3V lt Vpp lt 3 6V range 2 Data based on characterization results tested in production at Vpp max and fosc max 3 All I O pins in input with pull up mode no load all peripherals in reset state clock input OSCjj driven by external square wave OSG and LVD disabled 67 104 ST6208C ST6209C ST6210C ST6220C SUPPLY CURRENT CHARACTERISTICS Cont d Figure 44 Typical Ipp in WAIT vs fcp
21. Ta 125 C 1000 ee a VDD V VDD V 70 104 ST6208C ST6209C ST6210C ST6220C SUPPLY CURRENT CHARACTERISTICS Cont d 10 4 4 Supply and Clock System The previous current consumption specified for source current consumption To get the total de the ST6 functional operating modes over tempera vice consumption the two current values must be ture range does not take into account the clock added except for STOP mode fosc 32 kHz fosc 1 MHz fosc 2 MHz fosc 4 MHz fosc 8 MHz fosc 32 kHz fosc 1 MHz fosc 2 MHz fosc 4 MHz fosc 8 MHz fosc 32 kHz fosc 1 MHz fosc 2 MHz fosc 4 MHz fosc 8MHz fosc 32 kHz fosc 1 MHz fosc 2 MHz fosc 4 MHz fosc 8 MHz LFAO supply current Vop 5 0 V OSG supply current Vop 5 0 V LVD supply current Vpp 9 0 V 10 4 5 On Chip Peripherals pam Vpp 9 0 V 8 bit Timer supply current fosc 8 MHz ee 7y Supply current of RC oscillator lbo ck Supply current of resonator oscillator Vpp 5 0 V ADC supply current when converting fosc 8 MHz Veo 33 7 EG Notes 1 Typical data are based on T 25 C 2 Data based on characterization results not tested in production 3 Data based on a differential Ipp measurement between reset configuration OSG and LFAO disabled and LFAO run ning also includes the OSG stand alone consumption Data based on a differential Ipp measurement between reset configuration with OSG disabled and OSG enabled Data based on a different
22. Ta unless otherwise specified the input output alternate function characteristics TIMER 10 10 1 Watchdog Timer E CT Win Typ wax Uni ore 98 806 EI IO ESO me 10 10 2 8 Bit Timer Timer external clock frequency a m VDD gt 4 5V Pulse width at TIMER pin ky 87 104 ST6208C ST6209C ST6210C ST6220C 10 11 8 BIT ADC CHARACTERISTICS Subject to general operating conditions for Vpp fosc and Ta unless otherwise specified Symbol Parameter Conditions Typ Symbol Parameter Conditions Min Typ Max Unt Pam Extemalimputresistor Y X fosc 8MHz 70 tapc Total convertion time fosc 4MHz 140 us kas aciei AA A posa A ESA AD Analog input current during conver 1 0 A sion H Notes 1 Unless otherwise specified typical data are based on Ta 25 C and Vpp 5V 2 The ADC refers to Vpp and Vss 3 Any added external serial resistor will downgrade the ADC accuracy especially for resistance greater than 10kQ Data based on characterization results not tested in production 4 As a stabilization time for the AD converter is required the first conversion after the enable can be wrong Figure 72 Typical Application with ADC Gin Rain AINx 1 1500 ST62XX Note ADC not present on some devices See device summary on page 1 Y 88 104 ST6208C ST6209C ST6210C ST6220C 8 BIT ADC CHARACTERISTICS Cont d ADC Accuracy 2 fosc gt 1 2MHz 4 fosc gt 32KHz
23. Thresholds V 65 104 ky ST6208C ST6209C ST6210C ST6220C 10 4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for vice consumption the two current values must be the ST6 functional operating modes over tempera added except for STOP mode for which the clock ture range does not take into account the clock is stopped source current consumption To get the total de 10 4 1 RUN Modes STEIN AU UIT fosc 32kHz fosc 1 MHz fosc 2MHz fosc 4MHz fosc 8MHz Supply current in RUN mode 2 see Figure 42 amp Figure 43 fosc 32kHz fosc 1 MHz fosc 2MHz fosc 4MHz fosc 8MHz Supply current in RUN mode 3 see Figure 42 amp Figure 43 gt Q oO VI a a gt VI gt t9 y gt co VI a a gt VI gt 2 Notes 1 Typical data are based on T 25 C Vpp 5V 4 5V lt Vpp lt 6 0V range and Vpp 3 3V 3V lt Vpp lt 3 6V range 2 Data based on characterization results tested in production at Vpp max and fosc max 3 CPU running with memory access all I O pins in input with pull up mode no load all peripherals in reset state clock input OSC n driven by external square wave OSG and LVD disabled option bytes not programmed Figure 42 Typical Ipp in RUN vs fcpy re ay Typical Ipp in RUN vs Temperature DD IDD mA IDD mA 5 8MHz A 1MHz 4MHz Y 32KHz gt lt 2MHz 8MHz KC 1MHz A 4MHz Y 32KHz VDD V 66 104 Y ST6208C ST6209C
24. a ie ene et a ae es nS Ae 46 9 2 2 Mal Features us a adalat ena PA Maia etn Rare Be 46 8 2 3 Counter Prescaler Description 0 0 0 0 cee ee 47 8 2 4 Functional Description 0 00 tees 48 8 2 5 Low Power Modes 0000 ccc eee tenet eee 50 8 226 UNT UDS aci A a dd 50 8 2 7 Register Description 0 0 00 eee 51 8 3 A DCONVERTER ADC gametas takina maae ee eee 52 873 1 Introduction 260 de Sek Racha A ee a 52 8 3 2 Main Features 0 aiea ia a eee eee 52 8 3 3 Functional Description os dtaa iiao ee E a E A E e nE a RG a ia 53 8 3 4 Recommendations 0 54 8 3 5 Low Power Modes 0 55 853 6 INtermupts gt aa e a ata balde ata 55 8 3 7 Register Description sona ea ri ea aa eee 55 9 INSTRUCTION SET 0500000 a a o o a ee A aA 56 9 1 ST6 ARCHITECTURE 200300 ai tees a a a arar a ld Rae ee 56 9 2 ADDRESSING MODES 0 ceiu i a a E eee 56 ky 3 104 Table of Contents 9 3 INSTRUCTION SET sisine an isi an aa iaia a Aa e R aaa e T aa Aaa h 57 10 ELECTRICAL CHARACTERISTICS 20 00 62 10 1 PARAMETER CONDITIONS 000000 cece tenes 62 10 1 1Minimum and Maximum Values 0 000 eee ee 62 10 As2 Typical Values sis scat ee Seek awe Gad da pad sie ae es cae DEE RS 62 1013 Typical Curves 2 422 rot pce eee a 62 10 1 4Loading Capacitor s 080c 0dy ered ate wet a pad sea pias PEAY hes See AS 62 TOMS Pin InputVoltage st 4 0c0 a rar dara aaa any 62 10 2 ABSO
25. applied to the pins of each sample according to each pin combination The sample size depends of the number of supply pins of the device 3 parts n 1 supply pin Two models are usually simulated Human Body Model and Machine Model This test conforms to the JESD22 A114A A115A standard See Figure 57 and the following test sequences Human Body Model Test Sequence C is loaded through S1 by the HV pulse gener ator Absolute Maximum O Symbol 1 switches position from generator to R A discharge from C through R body resistance to the ST6 occurs S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST6 is not left in charge state S2 must be opened at least 10ms prior to the delivery of the next pulse Machine Model Test Sequence C is loaded through S1 by the HV pulse gener ator 1 switches position from generator to ST6 A discharge from C to the ST6 occurs S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST6 is not left in charge state S2 must be opened at least 10ms prior to the delivery of the next pulse R machine resistance in series with S2 en sures a slow discharge of the ST6 Conditions Maximum value Unit Electro static a voltage Human Body Model Ta 25 C 2090 Electro static discharge voltage Notes 1 Data based on characterization results not tested in production Figure
26. cause the device to exit from STOP mode 7 4 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR DR and OR registers see Table 9 and the GEN bit in the IOR register is set Figure 24 Diagram showing Safe I O State Transitions Interrupt p pull up Reset state Push pull Note xxx DDR OR DR Bits respectively SZA Push pull 39 104 ST6208C ST6209C ST6210C ST6220C 1 0 PORTS Cont d Table 10 I O Port Option Selections MODE AVAILABLE ON Input PAO PA3 PBO PB7 DDRx ORx DRx 0 0 1 Reset state a Input with pull up PAO PA3 PBO PB7 3 DDRx ORx DRx 0 0 0 Input with pull up PAO PA3 with interrupt PBO PB7 DDRx ORx DRx 0 1 0 PBO PB3 ST6210C 20C only PB4 PB7 DDRx ORx All devices except ST6208C Analog Input Analog Input PBO PB7 Open drain output 5mA Open drain output 20 mA PAO PA3 DDRx ORx DRx 1 0 0 1 Push pull output 5mA PBO PB7 Digital output Push pull output 20 mA PAO PA3 DDRx ORx DRx 1 1 0 1 SCHEMATIC Vop VDD i Data in A A o _ Interrupt Data in Data in Interrupt ADC P buffer disconnected A Data out Data out Note 1 Provided the correct configuration has been selected see Table 9 y 40 104 1 0 PORTS Cont d 7 5 REGISTER DESCRIPTION DATA REGISTER DR Po
27. cleared Bit 5 0 DRWR 5 0 Data read only memory Win dow Register Bits These are the Data read only memory Window bits that correspond to the upper bits of the data read only memory space Caution This register is undefined on reset it is write only therefore do not read it nor access it us ing Read Modify Write instructions SET RES INC and DEC 13 104 ST6208C ST6209C ST6210C ST6220C MEMORY MAP Cont d 3 1 6 2 Data ROM Window memory addressing In cases where some data look up tables for ex ample are stored in program memory reading these data requires the use of the Data ROM win dow mechanism To do this 1 The DRWR register has to be loaded with the 64 byte block number where the data are located in program memory This number also gives the start address of the block 2 Then the offset address of the byte in the Data ROM Window corresponding to the offset in the 64 byte block in program memory has to be load ed in a register A X When the above two steps are completed the data can be read To understand how to determine the DRWR and the content of the register please refer to the ex ample shown in Figure 6 In any case the calcula Figure 6 Data ROM Window Memory Addressing tion is automatically handled by the ST6 develop ment tools Please refer to the user manual of the correspod ing tool 3 1 6 3 Recommendations Care is required when handling the DRWR regis ter as i
28. is defined between a minimum and a maximum value and may vary depending on both Vpp and temperature For pre cise timing measurements it is not recommended to use the OSG fosc fosa MAIN OSCILLATOR RESTARTS lt INTERNAL CLOCK DRIVEN BY LFAO gt 21 104 ST6208C ST6209C ST6210C ST6220C CLOCK SYSTEM Cont d 5 13 Low Frequency Auxiliary Oscillator LFAO The Low Frequency Auxiliary Oscillator has three main purposes Firstly it can be used to reduce power consumption in non timing critical routines Secondly it offers a fully integrated system clock without any external components Lastly it acts as a backup oscillator in case of main oscillator fail ure This oscillator is available when the OSG ENA BLED option is selected in the option byte refer to the Option Bytes section of this document In this case it automatically starts one of its periods after the first missing edge of the main oscillator what ever the reason for the failure main oscillator de fective no clock circuitry provided main oscillator switched off See Figure 11 User code normal interrupts WAIT and STOP in structions are processed as normal at the re duced fl Fao frequency The A D converter accura cy is decreased since the internal frequency is be low 1 2 MHz At power on until the main oscillator starts the re set delay counter is driven by the LFAO If the main oscillator starts before the 2048 cycle
29. on using External Interrupts ESB bit Spurious Interrupt on Vector 2 If a pin associated with interrupt vector 2 is con figured as interrupt with pull up whenever vector 2 is configured to be rising edge sensitive by set ting the ESB bit in the IOR register an interrupt is latched although a rising edge may not have oc cured on the associated pin ST6208C ST6209C ST6210C ST6220C This is due to the vector 2 circuitry The worka round is to discard this first interrupt request in the routine using a flag for example Masking of One Interrupt by Another on Vector 2 When two or more port pins associated with inter rupt vector 2 are configured together as input with interrupt falling edge sensitive as long as one pin is stuck at 0 the other pin can never gen erate an interrupt even if an active edge occurs at this pin The same thing occurs when one pin is stuck at 1 and interrupt vector 2 is configured as rising edge sensitive To avoid this the first pin must input a signal that goes back up to 1 right after the falling edge Oth erwise in the interrupt routine for the first pin de activate the input with interrupt mode using the port control registers DDR OR DR An active edge on another pin can then be latched I O port Configuration Spurious Interrupt on Vector 2 If a pin associated with interrupt vector 2 is in in put with pull up state a 0 level is present on
30. or the NMI flags in stead of the Normal flags When the RETI instruc tion is executed the previously used set of flags is restored It should be noted that each flag set can only be addressed in its own context Non Maska ble Interrupt Normal Interrupt or Main routine The flags are not cleared during context switching and thus retain their status C Carry flag This bit is set when a carry or a borrow occurs dur ing arithmetic operations otherwise it is cleared The Carry flag is also set to the value of the bit tested in a bit test instruction it also participates in the rotate left instruction 0 No carry has occured 1 Acarry has occured 18 104 Z Zero flag This flag is set if the result of the last arithmetic or logical operation was equal to zero otherwise it is cleared 0 The result of the last operation is different from zero 1 The result of the last operation is zero Switching between the three sets of flags is per formed automatically when an NMI an interrupt or a RETI instruction occurs As NMI mode is auto matically selected after the reset of the MCU the ST6 core uses the NMI flags first Stack The ST6 CPU includes a true LIFO Last In First Out hardware stack which eliminates the need for a stack pointer The stack consists of six separate 12 bit RAM locations that do not belong to the data space RAM area When a subroutine call or interrupt request occurs the contents of each le
31. the pin and the ESB bit 0 when the I O pin is config ured as interrupt with pull up by writing to the DDRx ORx and DRx register bits an interrupt is latched although a falling edge may not have oc curred on the associated pin In the opposite case if the pin is in interrupt with pull up state a 0 level is present on the pin and the ESB bit 1 when the I O port is configured as input with pull up by writing to the DDRx ORx and DRx bits an interrupt is latched although a rising edge may not have occurred on the associated pin 29 104 ST6208C ST6209C ST6210C ST6220C 5 10 INTERRUPT HANDLING PROCEDURE The interrupt procedure is very similar to a call pro cedure in fact the user can consider the interrupt as an asynchronous call procedure As this is an asynchronous event the user cannot know the context and the time at which it occurred As a re sult the user should save all Data space registers which may be used within the interrupt routines The following list summarizes the interrupt proce dure When an interrupt request occurs the following actions are performed by the MCU automatically The core switches from the normal flags to the interrupt flags or the NMI flags The PC contents are stored in the top level of the stack The normal interrupt lines are inhibited NMI still active The internal latch if any is cleared The associated interruptvectoris loaded inthe PC When
32. 0 minutes using an ultraviolet lamp with 12000uW cm2 power rating The EPROM device should be placed within 2 5cm tinch of the lamp tubes during erasure 15 104 ST6208C ST6209C ST6210C ST6220C 3 3 OPTION BYTES Each device is available for production in user pro grammable versions OTP as well as in factory coded versions ROM OTP devices are shipped to customers with a default content 00h while ROM factory coded parts contain the code sup plied by the customer This implies that OTP de vices have to be configured by the customer using the Option Bytes while the ROM devices are facto ry configured The two option bytes allow the hardware configu ration of the microcontroller to be selected The option bytes have no address in the memory map and can be accessed only in programming mode for example using a standard ST6 program ming tool In masked ROM devices the option bytes are fixed in hardware by the ROM code see Section 11 6 2 ROM VERSION on page 98 It is there fore impossible to read the option bytes The option bytes can be only programmed once lt is not possible to change the selected options after they have been programmed In order to reach the power consumption value in dicated in Section 10 4 the option byte must be programmed to its default value Otherwise an over consumption will occur MSB OPTION BYTE Bits 15 10 Reserved must be always cleared Bit 9 EXTCNTL External STOP MODE
33. 1 rr ee e e x a 1 056 1 per 2 ext 1 per 3 bt 1 per pre ind 2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC JRC iooi e abc e b1 rr ee e v e 1 001 1 per 2 ext 1 per 3 bt 1 per 1 sd pre 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ JRC AND Nor e abc e b5 rr ee e e a x ane 1 per 2 ext 1 per 3 bt 1 per pre ind 2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD JRC ANDI cee e abc e b5 rr ee e av e a nn ey 1 per 2 ext 1 per 3 bt 1 per 1 sd pre imm 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ JRC SUB 1 o e abc e b3 rr ee e e a x 1 6 1 per 2 ext 1 per 3 bt 1 per pre ind 2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC JRC SUBI ay e abc e b3 rr ee e w e a nn ie 1 per 2 ext 1 per 3 bt 1 per 1 sd pre imm 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ JRC DEC 1 F 0 e abc e b7 rr ee e e x 1 de 0 1 per 2 ext 1 per 3 bt 1 per pre ind 2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD JRC 1 a 1 e abc e b7 rr ee e a w e 1 E 1 1 pcr 2 ext 1 per 3 bt 1 per 1 sd pre Abbreviations for Addressing Modes Legend dir Direct Indicates Illegal Instructions Mnemonic sd Short Direct e 5 bit Displacement Cycles imm Immediate b 3 bit Address inh Inherent rr 1 byte Data space address ra ext Extended nn 1 byte immediate data b d Bit Direct abc 12 bit address f bt Bit Test ee 8 bit displacement Addressing Mode pcr Program Counter Relative ind Indirect 60 104 Opcode Map Summary Continued ST6208C ST6209C ST6210C ST6220C
34. 20C CPU REGISTERS Cont d The 12 bit length allows the direct addressing of 4096 bytes in Program Space However if the program space contains more than 4096 bytes the additional memory in program space can be addressed by using the Program ROM Page register The PC value is incremented after reading the ad dress of the current instruction To execute relative jumps the PC and the offset are shifted through the ALU where they are added the result is then shifted back into the PC The program counter can be changed in the following ways JP Jump instruction PC Jump address CALL instruction PC Call address Relative Branch InstructionPC PC offset Interrupt PC Interrupt vector Reset PC Reset vector RET amp RETI instructions PC Pop stack Normal instruction PC PC 1 Flags C Z The ST6 CPU includes three pairs of flags Carry and Zero each pair being associated with one of the three normal modes of operation Normal mode Interrupt mode and Non Maskable Interrupt mode Each pair consists of a CARRY flag and a ZERO flag One pair CN ZN is used during Normal operation another pair is used dur ing Interrupt mode CI ZI and a third pair is used in the Non Maskable Interrupt mode CNMI ZN Ml The ST6 CPU uses the pair of flags associated with the current mode as soon as an interrupt or a Non Maskable Interrupt is generated the ST6 CPU uses the Interrupt flags
35. 210C ST6220C 10 2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as absolute maxi tions is not implied Exposure to maximum rating mum ratings may cause permanent damage to conditions for extended periods may affect device the device This is a stress rating only and func reliability tional operation of the device under these condi 10 2 1 Voltage Characteristics Symbol Rtgs YC value Un Vin Input voltage on any pin Vss 0 3 to Vpp 0 3 Output voltage on any pin 1 Vgg 0 3 to Vpp 0 3 VESD HBM Electro static discharge voltage Human Body Model 3500 10 2 2 Current Characteristics MUSIC E O MOTA Total current into Vpp power lines source 80 Total current out of Vss ground lines sink ma Tr 10 2 3 Thermal Characteristics Symbol E ee ee ee Storage temperature range 60 to 150 T Maximum junction temperature E see THERMAL CHARACTERISTICS section Notes 1 Directly connecting the RESET and I O pins to Vpp or Vgg could damage the device if an unintentional internal reset is generated or an unexpected change of the I O configuration occurs for example due to a corrupted program coun ter To guarantee safe operation this connection has to be done through a pull up or pull down resistor typical 4 7kQ for RESET 10kQ for I Os Unused I O pins must be tied in the same way to Vpp or Vgg according to their reset con figuration 2 When the current limitation is not possible the V y absolu
36. 25 C VDD V ST6208C ST6209C ST6210C ST6220C Ta 40 C Ta 95C Vol V at lio 20mA VDD V VDD V 83 104 ST6208C ST6209C ST6210C ST6220C I O PORT PIN CHARACTERISTICS Cont d Figure 68 Typical Voy VS Vpp Voh V at lio 2mA Voh V at lio 5mA VDD V VDD V 84 104 ST6208C ST6209C ST6210C ST6220C 10 9 CONTROL PIN CHARACTERISTICS 10 9 1 Asynchronous RESET Pin Subject to general operating conditions for Vpp fosc and T unless otherwise specified Schmitt trigger voltage hysteresis ee S 200 400 Vpp 5V 150 350 DD 9 ESD resistor protection t Generated reset pulse duration External pintor tepu w RSTL out P internal reset sources us Notes 1 Unless otherwise specified typical data are based on T 25 C and Vpp 5V 2 Data based on characterization results not tested in production 3 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested 4 The Ron pull up equivalent resistor is based on a resistive transistor This data is based on characterization results not tested in production 5 All short pulse applied on RESET pin with a duration below th RsTL in Can be ignored 6 The reset network protects the device against parasitic resets especially in a noisy environment 7 The output of the external reset circuit must have an open drain output to drive the ST6 reset pad Otherwise the device can be damaged when the ST6 gener
37. 52 8 Figure 53 22 870 k Notes 1 Data based on characterization results not tested in production These measurements were done with the OSCin pin unconnected only soldered on the PCB 2 Ryner Must have a positive temperature coefficient ppm C carbon resistors should therefore not be used Figure 51 Typical Application with RC Oscillator EXTERNAL RC MIRROR CURRENT Cex 9pF DISCHARGE ST62XX 74 104 ST6208C ST6209C ST6210C ST6220C CLOCK AND TIMING CHARACTERISTICS Cont d Figure 52 Typical RC Oscillator frequency vs Figure 53 Typical RC Oscillator frequency vs VDD Temperature Vpp 5V fosc MHz 7 Rnet 22KOhm fosc MHz Rnet 22KOhm gt E Rnet 47KOhm Rnet 47KOhm Et i gt Rnet 100KOhm a PY Rnet 220KOhm _ __ a ae a Low Frequency Auxiliary Oscillator Ta 25 C Vpp 5 0 V LFAO Frequency Ta 25 C Vpp 3 3 V Internal Frequency with OSG ena Ta 25 C Vpp 4 5 V bled Ta 25 C Vop 3 3 V Figure 54 Typical LFAO Frequencies fosc kHz 600 50 73 Ta 25 C 400 Ta 125 C at a AA ee VDD V Note 1 Data based on characterization results 75 104 ST6208C ST6209C ST6210C ST6220C 10 6 MEMORY CHARACTERISTICS Subject to general operating conditions for Vpp fosc and Ta unless otherwise specified 10 6 1 RAM and Hardware Registers 10 6 2 EPROM Program Memory Data retention Ta 55 C Figure 55
38. 7 2 FUNCTIONAL DESCRIPTION Each port is associated with 3 registers located in Data space Data Register DR Data Direction Register DDR Option Register OR Each I O pin may be programmed using the corre sponding register bits in the DDR DR and OR reg isters bit x corresponding to pin x of the port Table 9 illustrates the various port configurations which can be selected by user software During MCU initialization all I O registers are cleared and the input mode with pull up and no in terrupt generation is selected for all the pins thus avoiding pin conflicts 7 2 1 Digital Input Modes The input configuration is selected by clearing the corresponding DDR register bit In this case reading the DR register returns the digital value applied to the external I O pin Different input modes can be selected by software through the DR and OR registers see Table 9 External Interrupt Function Y ST6208C ST6209C ST6210C ST6220C All input lines can be individually connected by software to the interrupt system by programming the OR and DR registers accordingly The inter rupt trigger modes falling edge rising edge and low level can be configured by software for each port as described in the Interrupt section 7 2 2 Analog Inputs Some pins can be configured as analog inputs by programming the OR and DR registers according ly see Table 9 These analog inputs are connect ed to the on chip 8 bit An
39. AND STOP MODES 000002005 36 6 4 1 Exit from Wait and Stop Modes o o occococccccoo 36 6 4 2 Recommended MCU Configuration 0 0 00 eee 36 TUOPORTS ci wares pee tines ab CA ah Ca eda eae Ba A 37 T INTRODUCTION a icles da eee 37 7 2 FUNCTIONAL DESCRIPTION n era cc cece eee nena 37 7 2 1 Digital Input MOGES sated ie ed wealth edd dd a 37 1 2 2 Analog INputS s s2 cceen narra pr na aea anda pea eee nee as 37 2 3 Output Modes ica ota Aa delice stand a iy 37 1 2 4 Alternate Functions iseroossrrtr taa ara id doa ari 37 7 2 5 Instructions NOT to be used to access Port Data registers SET RES INC and DEC 39 7 26 REeCOMMENDASIONS oscense a RA AAA 39 13 EOW POWER MMODES usen aa e dae wis 39 TA INTERRUPTS sack A E bd a ain 39 7 5 REGISTER DESCRIPTION sieer tr kane e a a a OE E E 41 8 ON CHIP PERIPHERALS lt o 0 22 0 tei eee cd re ee ee ee Ge ew a 42 8 1 WATCHDOG TIMER WDG 00 0 tenet eens 42 811 Intro dUCI N vr A ae ess a en Aa ae 42 8 1 2 Main Features victor ag Be Bee a ene daa ean eS 42 8 1 3 Functional Description gt sess cade prestane iepa eee 43 8 1 4 Recommendations 000 000 ete eee 43 8 1 5 LOW Power Mod s cocidas pene aa a eee we Pew A e De aoe a kana do 44 8 1 6 Interrupts Gilda ee ae et oe peal pa Thon a Paes Se aS 44 8 1 7 Register Description 2 2 0 niri Ekerona pra ka DEEPER 45 g2 GBI TIMER 0d a Wed A dad aa e aaa OOS 46 82e INTFOGUGTIONS 2x tia
40. AY OSCILLATOR On Clock to PERIPHERALS Yes Clock to CPU Yes FETCH RESET VECTOR OR SERVICE INTERRUPT 33 104 ST6208C ST6209C ST6210C ST6220C 6 3 STOP MODE STOP mode is the lowest power consumption mode of the MCU see Figure 22 The MCU goes into STOP mode as soon as the STOP instruction is executed This has the follow ing effects Program execution is stopped the microcontrol ler can be considered as being frozen The contents of RAM and the peripheral regis ters are kept safely as long as the power supply voltage is higher than the RAM retention voltage The oscillator is stopped so peripherals cannot work except the those that can be driven by an external clock Exit from STOP Mode The MCU remains in STOP mode until one of the following events occurs RESET Watchdog LVD or RESET pin A peripheral interrupt assuming this peripheral can be driven by an external clock An external interrupt I O port NMI In all cases a delay of 2048 clock cycles fint is generated to make sure the oscillator has started properly 34 104 The Program Counter then points to the starting address of the interrupt or RESET service routine see Figure 21 STOP Mode and Watchdog When the Watchdog is active hardware or soft ware activation the STOP instruction is disabled and a WAIT instruction will be executed in its place unless the EXCTNL option bit is set to 1 in the o
41. CONVERTER ACCURACY AN673 REDUCING CURRENT CONSUMPTION AT 32KHZ WITH ST62 DESIGN IMPROVEMENTS AN420 EXPANDING A D RESOLUTION OF THE ST6 A D CONVERTER AN432 USING ST62XX I O PORTS SAFELY AN434 MOVEMENT DETECTOR CONCEPTS FOR NOISY ENVIRONMENTS AN435 DESIGNING WITH MICROCONTROLLERS IN NOISY ENVIRONMENTS AN669 SIMPLE RESET CIRCUITS FOR THE ST6 AN670 OSCILLATOR SELECTION FOR ST62 AN671 PREVENTION OF DATA CORRUPTION IN ST6 ON CHIP EEPROM AN911 ST6 MICRO IS EMC CHAMPION AN975 UPGRADING FROM ST625X 6XB TO ST625X 6XC AN1015 SOFTWARE TECHNIQUES FOR IMPROVING ST6 EMC PERFORMANCE PERIPHERAL OPERATIONS AN590 PWM GENERATION WITH ST62 AUTO RELOAD TIMER AN591 INPUT CAPTURE WITH ST62 AUTO RELOAD TIMER AN592 PLL GENERATION USING THE ST62 AUTO RELOAD TIMER AN593 ST62 IN CIRCUIT PROGRAMMING AN678 LCD DRIVING WITH ST6240 ky 101 104 ST6208C ST6209C ST6210C ST6220C IDENTIFICATION DESCRIPTION AN913 PWM GENERATION WITH ST62 16 BIT AUTO RELOAD TIMER AN914 USING ST626X SPI AS UART AN1016 ST6 USING THE ST623XB ST628XB UART AN1050 ST6 INPUT CAPTURE WITH ST62 16 BIT AUTO RELOAD TIMER AN1127 USING THE ST62T6XC 5XC SPI IN MASTER MODE GENERAL AN683 MCUS 8 16 BIT MICROCONTROLLERS MCUS APPLICATION NOTES ABSTRACTS BY TOPICS AN886 SELECTING BETWEEN ROM AND OTP FOR A MICROCONTROLLER AN887 MAKING IT EASY WITH MICROCON
42. Eh OFFFh Table 4 ST6210C Program Memory Map 0000h 087Fh Reserved 0880h OF9Fh User ROM OFAOh OFEFh Reserved OFFOh OFF7h Interrupt Vectors OFF8h OFFBh Reserved OFFCh OFFDh NMI Interrupt Vector OFFEh OFFFh Reset Vector Table 5 ST6220C Program Memory Map 0000h 007Fh Reserved 0080h OF9Fh User ROM OFAOh OFEFh Reserved Interrupt Vectors Reserved NMI Interrupt Vector Reset Vector OFFOh OFF7h OFF8h OFFBh OFFCh OFFDh OFFEh OFFFh Note OTP EPROM devices can be programmed with the development tools available from ST6208C ST6209C ST6210C ST6220C STMicroelectronics please refer to Section 12 on page 99 3 2 2 EPROM Erasing The EPROM devices can be erased by exposure to Ultra Violet light The characteristics of the MCU are such that erasure begins when the memory is exposed to light with a wave lengths shorter than approximately 4000A It should be noted that sun light and some types of fluorescent lamps have wavelengths in the range 3000 4000A It is thus recommended that the window of the MCU packages be covered by an opaque label to prevent unintentional erasure problems when test ing the application in such an environment The recommended erasure procedure is exposure to short wave ultraviolet light which have a wave length 2537A The integrated dose i e U V inten sity x exposure time for erasure should be a mini mum of 30W sec cm The erasure time with this dosage is approximately 30 to 4
43. IES Total unadjusted error 1 Notes 1 Negative injection disturbs the analog performance of the device In particular it induces leakage currents throughout the device including the analog inputs To avoid undesirable effects on the analog functions care must be taken Analog input pins must have a negative injection less than 1mA assuming that the impedance of the analog voltage is lower than the specified limits Pure digital pins must have a negative injection less than 1mA In addition it is recommended to inject the current as far as possible from the analog input pins 2 Data based on characterization results over the whole temperature range monitored in production Vpp 5V fosc 8M Hz Figure 73 ADC Accuracy Characteristics Digital Result ADCDR AA 1 Example of an actual transfer curve 2 The ideal transfer curve 3 End point correlation line 255 254 253 DDA ssa 1LS8 256 IDEAL Er Total Unadjusted Error maximum deviation 2 7 2 Er eos 5 a Vssa between the actual and the ideal transfer curves Eo Offset Error deviation between the first actual transition and the first ideal one Eg Gain Error deviation between the last ideal transition and the last actual one Ep Differential Linearity Error maximum deviation between actual steps and the ideal one E Integral Linearity Error maximum deviation between any actual transition and the end point correlation li
44. LUTE MAXIMUM RATINGS 0 00 0 cece eee 63 10 2 1 Voltage Characteristics 00 ee 63 10 2 2Current Characteristics soson 0 eee 63 10 2 3Thermal Characteristics 0 i eee 63 10 3 OPERATING CONDITIONS 000000 e eee eee 64 10 3 1General Operating Conditions 0 00 cc ee 64 10 3 20perating Conditions with Low Voltage Detector LVD 65 10 4 SUPPLY CURRENT CHARACTERISTICS 0 000 e cece eee 66 10 4 11RUNIMOdES id does Ge tae Soir Spa Reh AO 66 TO0 4 2WAIT MOd6S votes d aces Gineeagedulenndtaa ais 67 10 4 3STOP Mode cordura ras 70 10 4 4Supply and Clock System 2 0 cee eee 71 10 4 50n Chip Peripherals 0 0c cette ee 71 10 5 CLOCK AND TIMING CHARACTERISTICS 000 000 e eee eee 72 10 5 1General Timings 2 0 0 ee Er ARAA E a e PREE EREDA 72 10 5 2External Clock Source dosp kan e a a a N a E A A r EA 72 10 5 3Crystal and Ceramic Resonator Oscillators ooooooooooooooooo 73 TOSAR Oscillator erd test oe ee oe a as 74 10 5 5Oscillator Safeguard OSG and Low Frequency Auxiliary Oscillator LFAO 75 10 6 MEMORY CHARACTERISTICS 0 00 000 cece tenes 76 10 6 1RAM and Hardware Registers 0 0 eee 76 10 6 2EPROM Program Memory 0 cee et tee 76 10 7 EMC CHARACTERISTICS 0000 cece eens 77 10 7 1 Functional EMS eesis aretes ek ee ee be De Va 77 10 7 2Absolute Electrical Sensitivity
45. O O0 ST6208CBIQj 0 O ar ST6208C ST6209C YY ST6210C ST6220C 8 BIT MCUs WITH A D CONVERTER TWO TIMERS OSCILLATOR SAFEGUARD amp SAFE RESET a Memories 1K 2K or 4K bytes Program memory OTP EPROM FASTROM or ROM with read out protection 64 bytes RAM Clock Reset and Supply Management Enhanced reset system Low Voltage Detector LVD for Safe Reset Clock sources crystal ceramic resonator or RC network external clock backup oscillator LFAO Oscillator Safeguard OSG 2 Power Saving Modes Wait and Stop a Interrupt Management 4 interrupt vectors plus NMI and RESET 12 external interrupt lines on 2 vectors m 121 0 Ports 12 multifunctional bidirectional I O lines 8 alternate function lines 4 high sink outputs 20mA CDIP20W m 2 Timers Configurable watchdog timer See Section 11 5 for Ordering Information 8 bit timer counter with a 7 bit prescaler Instruction Set Analog Peripheral Bie Ae E ck Is i 8 bit data manipulation 8 bi wi or 8 input channels excep ae on ST6208C 40 basic instructions 9 addressing modes Bit manipulation Development Tools Full hardware software development package Device Summary ST62T08C OTP ST62T09C OTP ST62T10C OTP ST62T20C OTP T62E20C EPROM ST6208C ROM ST6209C ROM ST6210C ROM ST6220C ROM PARDO om ST62P08C FASTROM ST62P09C FASTROM ST62P10C FASTROM ST62P20C FASTROM Programmemo
46. ONVERTER Cont d 8 3 5 Low Power Modes Description WAIT No effect on A D Converter ADC interrupts cause the device to exit from Wait mode STOP A D Converter disabled Note The A D converter may be disabled by clear ing the PDS bit This feature allows reduced power consumption when no conversion is needed 8 3 6 Interrupts Exit TA from Stop sion Note The EOC bit is cleared only when a new conversion is started it cannot be cleared by writ ing 0 To avoid generating further EOC interrupt the EAI bit has to be cleared within the ADC inter rupt subroutine 8 3 7 Register Description A D CONVERTER CONTROL REGISTER AD CR Address 0D1h Read Write Bit 6 Read Only Bit 5 Write Only Reset value 0100 0000 40h Interrupt Event 7 0 ADCR OSC ADCR ADCR Bit 7 EAI Enable A D Interrupt 0 ADC interrupt disabled 1 ADC interrupt enabled Bit 6 EOC End of conversion Read Only When a conversion has been completed this bit is set by hardware and an interrupt request is gener ated if the EAI bit is set The EOC bit is automati Table 16 ADC Register Map and Reset Values ST6208C ST6209C ST6210C ST6220C cally cleared when the STA bit is set Data in the data conversion register are valid only when this bit is set to 1 0 Conversion is not complete 1 Conversion can be read from the ADR register Bit 5 STA Start of Conversion Write Only 0 No effect 1 Start convers
47. OR register allows to distinguish in output mode if the push pull or open drain configuration is selected Output mode 0 Open drain output with P Buffer deactivated 1 Push pull Output Input mode See Table 9 Each bit is set and cleared by software Caution Modifying this register will also modify the I O port configuration in input mode see Ta ble 9 41 104 ST6208C ST6209C ST6210C ST6220C 8 ON CHIP PERIPHERALS 8 1 WATCHDOG TIMER WDG 8 1 1 Introduction 8 1 2 Main Features The Watchdog timer is used to detect the occur m Programmable timer 64 steps of 3072 clock rence of a software fault usually generated by ex cycles ternal interference or by unforeseen logical condi Software reset tions which causes the application program to abandon its normal sequence The Watchdog cir cuit generates an MCU reset on expiry of a pro Reset if watchdog activated when the SR bit reaches zero grammed time period unless the program refresh Hardware or software watchdog activation es the counter s contents before the SR bit be selectable by option bit Refer to the option comes cleared bytes section Figure 25 Watchdog Block Diagram WATCHDOG REGISTER WDGR cee 7 BIT DOWNCOUNTER CLOCK DIVIDER f int 12 256 42 104 WATCHDOG TIMER Cont d 8 1 3 Functional Description The watchdog activation is selected through an option in the option bytes HARDWARE Watchdog o
48. OSG filters spikes from the oscillator lines and switches to the LFAO backup oscillator in the event of main oscil lator failure It also automatically limits the internal clock frequency finr as a function of Vpp in order to guarantee correct operation These functions are illustrated in Figure 10 and Figure 11 Figure 9 Clock Circuit Block Diagram ST6208C ST6209C ST6210C ST6220C Table 6 illustrates various possible oscillator con figurations using an external crystal or ceramic resonator an external clock input an external re sistor RyerT or the lowest cost solution using only the LFAO For more details on configuring the clock options refer to the Option Bytes section of this document The internal MCU clock frequency finr is divided by 12 to drive the Timer the Watchdog timer and the A D converter by 13 to drive the CPU core and the SPI and by 1 or 3 to drive the ARTIMER as shown in Figure 9 With an 8 MHz oscillator the fastest CPU cycle is therefore 1 625us A CPU cycle is the smallest unit of time needed to execute any operation for instance to increment the Program Counter An instruction may require two four or five CPU cycles for execution OSCILLATOR SAFEGUARD OSG OSG filtering MAIN OSCILLATOR OSCOFF BIT ADCR REGISTER 8 BIT TIMER WATCHDOG 8 BIT ARTIMER 8 BIT ARTIMER OSG ENABLE OPTION BIT See OPTION BYTE SECTION Y Depending on device See device summ
49. R bit while the C bit is set 8 1 4 Recommendations 1 The Watchdog plays an important supporting role in the high noise immunity of ST62xx devices and should be used wherever possible Watchdog related options should be selected on the basis of a trade off between application security and STOP ky ST6208C ST6209C ST6210C ST6220C mode availability refer to the description of the WDACT and EXTCNTL bits on the Option Bytes When STOP mode is not required hardware acti vation without EXTERNAL STOP MODE CON TROL should be preferred as it provides maxi mum security especially during power on When STOP mode is required hardware activa tion and EXTERNAL STOP MODE CONTROL should be chosen NMI should be high by default to allow STOP mode to be entered when the MCU is idle The NMI pin can be connected to an I O line see Figure 26 to allow its state to be controlled by soft ware The I O line can then be used to keep NMI low while Watchdog protection is required or to avoid noise or key bounce When no more processing is required the I O line is released and the device placed in STOP mode for lowest power consumption Figure 26 A typical circuit making use of the EXERNAL STOP MODE CONTROL feature SWITCH VRO2002 2 When software activation is selected WDACT bit in Option byte and the Watchdog is not activat ed the downcounter may be used as a simple 7 bit timer remember that the bits are in reverse
50. Register Map and Reset Values Address Register Label 7 Hex 0D2h PSCR PSCR7 PSCR6 Reset Value 0 1 PSCR5 Deae cd SCR4 PSCR3 PSCR2 PSCR1 PSCRO 1 1 1 1 1 1 TCR TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCRO 0D3h Reset Value 1 1 1 1 1 1 0D4h TSCR TMZ ETI TOUT DOUT PSI PS2 PS1 PSO Reset Value 0 0 0 0 0 0 0 0 51 104 ST6208C ST6209C ST6210C ST6220C 8 3 A D CONVERTER ADC 8 3 1 Introduction 8 3 2 Main Features The on chip Analog to Digital Converter ADC pe 8 bit conversion ripheral is a 8 bit successive approximation con Multiplexed analog input channels verter This peripheral has multiplexed analog in Linear successive approximation put channels refer to device pin out description that allow the peripheral to convert the analog volt Data register DR which contains the results End of Conversion flag age levels from different sources On Off bit to reduce consumption The result of the conversion is stored in a 8 bit Data Register The A D converter is controlled Typical conversion time 70 us with an 8 MHz through a Control Register crystal The block diagram is shown in Figure 34 Figure 34 ADC Block Diagram AD JOSC AD AD ANALOG TO DIGITAL CONVERTER A DR ADR7 ADR6 ADR5 ADR4 Be ES Ss A JJ ADR3 ADR2 ADR1 ADRO Note ADC not present on some devices See device summary on page 1 y 52 104 A D CONVERTER Cont d 8 3 3 Functional Descrip
51. Resistive ESD protection ST6208C ST6209C ST6210C ST6220C If the RESET pin is grounded while the MCU is in RUN or WAIT modes processing of the user pro gram is stopped RUN mode only the I O ports are configured as inputs with pull up resistors and the main oscillator is restarted When the level on the RESET pin then goes high the initialization se quence is executed at the end of the internal delay period If the RESET pin is grounded while the MCU is in STOP mode the oscillator starts up and all the I O ports are configured as inputs with pull up resis tors When the RESET pin level then goes high the initialization sequence is executed at the end of the internal delay period A simple external RESET circuitry is shown in Fig ure 15 For more details please refer to the appli cation note AN669 INTERNAL RESET COUNTER 2048 clock cycles WATCHDOG RESET LVD RESET Y 25 104 ST6208C ST6209C ST6210C ST6220C RESET Conta 5 3 4 Watchdog Reset The MCU provides a Watchdog timer function in order to be able to recover from software hang ups If the Watchdog register is not refreshed be fore an end of count condition is reached a Watchdog reset is generated After a Watchdog reset the MCU restarts in the same way as if a Reset was generated by the RE SET pin Note When a watchdog reset occurs the RESET pin is tied low for very short time period to flag the reset phase This ti
52. SCin OSCout EXTERNAL CLOCK Crystal Resonator Option Crystal Resonator Clock 2 ST6 LOAD CAPACITORS 3 OSCin OSCout Cia _7 c o gt 2 oO h 9 2 g o a Q cc z D gt Le O RC Network ST6 OSCin OSCout RC Network Option ST6 OSCin OSCout OSG Enabled Option Notes 1 To select the options shown in column 1 of the above table refer to the Option Byte section 2 This schematic are given for guidance only and are sub ject to the schematics given by the crystal or ceramic res onator manufacturer 3 For more details please refer to the Electrical Charac teristics Section ky CLOCK SYSTEM Cont d 5 1 2 Oscillator Safeguard OSG The Oscillator Safeguard OSG feature is a means of dramatically improving the operational integrity of the MCU It is available when the OSG ENABLED option is selected in the option byte re fer to the Option Bytes section of this document The OSG acts as a filter whose cross over fre quency is device dependent and provides three basic functions Filtering spikes on the oscillator lines which would result in driving the CPU at excessive fre quencies Management of the Low Frequency Auxiliary Oscillator LFAO useable as low cost internal clock source backup clock in case of main oscil lator failure or for low power consumption Automatically limiting the f yy clock frequency as a function o
53. ST6209C ST6210C ST6220C 8 2 8 BIT TIMER 8 2 1 Introduction 8 2 2 Main Features The 8 Bit Timer on chip peripheral is a free run Time out downcounting mode with up to 15 bit ning downcounter based on an 8 bit downcounter accuracy with a 7 bit programmable prescaler giving a max External counter clock source valid also in imum count of 215 The peripheral may be config STOP mode ured in three different operating modes Interrupt capability on counter underflow Output signal generation External pulse length measurement m Event counter The timer can be used in WAIT and STOP modes to wake up the MCU Figure 27 Timer Block Diagram 8 BIT DOWN COUNTER finT 12 COUNTER TCR TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCRO TSCR INTERRUPT fPRESCALER avo1sy j PSCR REGISTER 0 Waa PROGRAMMABLE PRESCALER 46 104 57 8 BIT TIMER Cont d 8 2 3 Counter Prescaler Description Prescaler The prescaler input can be the internal frequency fint divided by 12 or an external clock applied to the TIMER pin The prescaler decrements on the rising edge depending on the division factor pro grammed by the PS 2 0 bits in the TSCR register The state of the 7 bit prescaler can be read in the PSCR register When the prescaler reaches 0 it is automatically reloaded with 7Fh Counter The free running 8 bit downcounter is fed by the output of the programmable prescaler and is dec remented on every rising
54. TROLLERS AN898 EMC GENERAL INFORMATION AN899 SOLDERING RECOMMENDATIONS AND PACKAGING INFORMATION AN900 INTRODUCTION TO SEMICONDUCTOR TECHNOLOGY AN901 EMC GUIDE LINES FOR MICROCONTROLLER BASED APPLICATIONS AN902 QUALITY AND RELIABILITY INFORMATION AN912 A SIMPLE GUIDE TO DEVELOPMENT TOOLS AN1181 ELECTROSTATIC DISHARGE SENSITIVITY MEASUREMENT 102 104 ky ST6208C ST6209C ST6210C ST6220C 14 SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one 3 3 Removed references to 32768 clock cycle delay in Section 5 and Section 6 Changed note 2 in Section 10 6 2 on page 76 added text on data retention and program October 03 mability 15 TO GET MORE INFORMATION To get the latest information on this product please use the STMicroelectronics web server gt http mcu st com Y 103 104 ST6208C ST6209C ST6210C ST6220C Notes Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectro
55. alog to Digital Converter Caution ONLY ONE pin should be programmed as an analog input at any time since by selecting more than one input simultaneously their pins will be effectively shorted 7 2 3 Output Modes The output configuration is selected by setting the corresponding DDR register bit In this case writ ing to the DR register applies this digital value to the I O pin through the latch Then reading the DR register returns the previously stored value Two different output modes can be selected by software through the OR register push pull and open drain DR register value and output pin status DR Push pull Open drain Co vs ss Floating Note The open drain setting is not a true open drain This means it has the same structure as the push pull setting but the P buffer is deactivated To avoid damaging the device please respect the Vout absolute maximum rating described in the Electrical Characteristics section 7 2 4 Alternate Functions When an on chip peripheral is configured to use a pin the alternate function timer input output is not systematically selected but has to be config ured through the DDR OR and DR registers Re fer to the chapter describing the peripheral for more details 37 104 ST6208C ST6209C ST6210C ST6220C 1 0 PORTS Cont d Figure 23 I O Port Block Diagram Pxx I O Pin ST6 i INTERNAL BUS N BUFFER OPTION REGISTER f P BUFFER CLAMPING DIODES K
56. an interrupt request occurs the following actions must be performed by the user software User selected registers have to be saved within the interrupt service routine normally on a soft ware stack The source of the interrupt must be determined by polling the interrupt flags if more than one source is associated with the same vector The RETI RETurn from Interrupt instruction must end the interrupt service routine After the RETI instruction is executed the MCU re turns to the main routine Caution When a maskable interrupt occurs while the ST6 core is in NORMAL mode and during the execution of an Idi IOR 00h instruction disabling all maskable interrupts if the interrupt request oc curs during the first 3 cycles of the Idi instruction which is a 4 cycle instruction the core will switch to interrupt mode BUT the flags CN and ZN will NOT switch to the interrupt pair Cl and ZI 5 10 1 Interrupt Response Time This is defined as the time between the moment when the Program Counter is loaded with the in terrupt vector and when the program has jump to the interrupt subroutine and is ready to execute the code It depends on when the interrupt occurs while the core is processing an instruction 30 104 Figure 18 Interrupt Processing Flow Chart LOAD PC FROM INTERRUPT VECTOR CLEAR INTERNAL LATCH IS THE CORE ALREADY IN IORMAL MODE DISABLE MASKABLE INTERRUPT PUSH THE
57. ary on page 1 19 104 ST6208C ST6209C ST6210C ST6220C CLOCK SYSTEM Conta 5 1 1 Main Oscillator The oscillator configuration is specified by select ing the appropriate option in the option bytes refer to the Option Bytes section of this document When the CRYSTAL RESONATOR option is se lected it must be used with a quartz crystal a ce ramic resonator or an external signal provided on the OSCin pin When the RC NETWORK option is selected the system clock is generated by an ex ternal resistor the capacitor is implemented inter nally The main oscillator can be turned off when the OSG ENABLED option is selected by setting the OSCOFF bit of the ADC Control Register not available on some devices This will automatically start the Low Frequency Auxiliary Oscillator LFAO The main oscillator can be turned off by resetting the OSCOFF bit of the A D Converter Control Reg ister or by resetting the MCU When the main os cillator starts there is a delay made up of the oscil lator start up delay period plus the duration of the software instruction at a clock frequency fL Fao Caution It should be noted that when the RC net work option is selected the accuracy of the fre quency is about 20 so it may not be suitable for some applications For more details please refer to the Electrical Characteristics Section 20 104 Table 6 Oscillator Configurations EA Hardware Configuration External Clock ST6 O
58. ates an internal reset LVD or watchdog Figure 69 Typical Ron VS Vpp with Viy Vss Ron Kohm 1000 sl dt Ta 40 Ta 95 C goo e Tta250 AE Ta 125 C 700 AA ee VDD V Y 85 104 ST6208C ST6209C ST6210C ST6220C CONTROL PIN CHARACTERISTICS Cont d Figure 70 Typical Application with RESET pin INTERNAL RESET COUNTER 2048 external clock cycl EXTERNAL RESET CIRCUIT WATCHDOG RESET LVD RESET 10 9 2 NMI Pin Subject to general operating conditions for Vpp fosc and Ta unless otherwise specified C A IA Y eoatiowevervorage YT nit evelvotage dee foo w TORE AEL BES Notes 1 Unless otherwise specified typical data are based on Ty 25 C and Vpp 5V 2 Data based on characterization results not tested in production 3 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested 4 The Roul up equivalent resistor is based on a resistive transistor This data is based on characterization results not tested in production Figure 71 Typical Rpull up VS Vpop With Vin Vss Rpull up Kohm 300 Ta 40 C Ta 95 C 2507 78 Ao Ta 25 C SK Ta 125 C 200 E EA VDD V y 86 104 ST6208C ST6209C ST6210C ST6220C CONTROL PIN CHARACTERISTICS Cont d 10 10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for Vpp Refer to I O port characteristics for more details on fosc and
59. bit to output a low level Note As soon as the TOUT bit is set The timer pin is configured as output push pull regardless of the corresponding I O port control registers setting if the TIMER pin is multiplexed Figure 32 Output Mode Control Figure 33 Output Mode Operation Counter At each zero event DOUT has to be copied to the TIMER in TIMER PIN 1 downcount Default output value is 0 49 104 ST6208C ST6209C ST6210C ST6220C 8 BIT TIMER Cont d 8 2 5 Low Power Modes Description No effect on timer WAIT Timer interrupt events cause the device to exit from WAIT mode 8 2 6 Interrupts Enable oat Interrupt Event Bit from Stop Event Timer registers are frozen except in Event STOP Counter mode with external clock on TIM ER pin 50 104 8 BIT TIMER Cont d 8 2 7 Register Description PRESCALER COUNTER REGISTER PSCR Address 0D2h Read Write Reset Value 0111 1111 7Fh 7 0 PSCR PSCR PSCR PSCR PSCR PSCR PSCR PSCR 7 6 5 4 3 2 1 0 Bit 7 PSCR7 Not used always read as 0 Bits 6 0 PSCR 6 0 Prescaler LSB TIMER COUNTER REGISTER TCR Address 0D3h Read Write Reset Value 1111 1111 FFh 7 0 TCR7 TCR6 TCRS TCR4 TCR3 TCR2 TCR1 TCRO Bits 7 0 TCR 7 0 Timer counter bits TIMER STATUS CONTROL REGISTER TSCR Address 0D4h Read Write Reset Value 0000 0000 00h 7 0 ee Forfa Tm Bit 7 TMZ Timer Zero bit A low t
60. control 0 EXTCNTL mode not available STOP mode is not available with the watchdog active 1 EXTCNTL mode available STOP mode is avail able with the watchdog active by setting NMI pin to one Bit 8 LVD Low Voltage Detector on off This option bit enable or disable the Low Voltage Detector LVD feature 0 Low Voltage Detector disabled 1 Low Voltage Detector enabled LSB OPTION BYTE Bit 7 PROTECT Readout Protection This option bit enables or disables external access to the internal program memory 0 Program memory not read out protected 1 Program memory read out protected Bit 6 OSC Oscillator selection This option bit selects the main oscillator type 0 Quartz crystal ceramic resonator or external clock 1 RC network Bit 5 Reserved must be always cleared Bit 4 Reserved must be always set Bit 3 NMI PULL NMI Pull Up on off This option bit enables or disables the internal pull up on the NMI pin 0 Pull up disabled 1 Pull up enabled Bit 2 TIM PULL T MER Pull Up on off This option bit enables or disables the internal pull up on the TIMER pin 0 Pull up disabled 1 Pull up enabled Bit 1 WDACT Hardware or software watchdog This option bit selects the watchdog type 0 Software watchdog to be enabled by software 1 Hardware watchdog always enabled Bit 0 OSGEN Oscillator Safeguard on off This option bit enables or disables the oscillator Safeguard OSG feature
61. d party manufacturers can be ob tain from the STMicroelectronics Internet site http mcu st com Third Party Designation ST Sales Type Web site address ACTUM ST REALIZER II Graphical Schematic based Development available from STMicroelectronics STREALIZER II http www actum com CEIBO Low cost emulator available from CEI BO http Awww ceibo com RAISONANCE This tool includes in the same environ ment an assembler linker C compiler debugger and simulator The assembler package plus limited C compiler is free and can be downloaded from raisonance web site The full version is available both from STMicroelectronics and Raiso nance ST6RAIS SWC PC http www raisonance com SOFTEC High end emulator available from SOFTEC Gang programmer available from SOFTEC http www softecmicro com ADVANCED EQUIPMENT ADVANCED TRANSDATA BP MICROSYSTEMS DATA I O DATAMAN EE TOOLS ELNEC HI LO SYSTEMS ICE TECHNOLOGY LEAP LLOYD RESEARCH LOGICAL DEVICES MQP ELECTRONICS NEEDHAMS ELECTRONICS STAG PROGRAMMERS SYSTEM GENERAL CORP TRIBAL MICROSYSTEMS XELTEK Single and gang programmers http www aec com tw http www adv transdata com http www bpmicro com http Awww data io com http Awww dataman com http Awww eetools com ht
62. delay has elapsed it takes over 22 104 The Low Frequency Auxiliary Oscillator is auto matically switched off as soon as the main oscilla tor starts 5 1 4 Register Description ADC CONTROL REGISTER ADCR Address 0D1h Read Write Reset value 0100 0000 40h 7 0 ADCR ADCR ADCR ADCR ADCR OSC ADCR ADCR 7 6 5 4 3 OFF 1 0 Bit 7 3 1 0 ADCR 7 3 ADCR 1 0 ADC Control Register These bits are used to control the A D converter if available on the device otherwise they are not used Bit 2 OSCOFF Main Oscillator Off 0 Main oscillator enabled 1 Main oscillator disabled Note The OSG must be enabled using the OS GEN option in the Option Byte otherwise the OS COFF setting has no effect ST6208C ST6209C ST6210C ST6220C 5 2 LOW VOLTAGE DETECTOR LVD The on chip Low Voltage Detector is enabled by setting a bit in the option bytes refer to the Option Bytes section of this document The LVD allows the device to be used without any external RESET circuitry In this case the RESET pin should be left unconnected If the LVD is not used an external circuit is manda tory to ensure correct Power On Reset operation see figure in the Reset section For more details please refer to the application note AN669 The LVD generates a static Reset when the supply voltage is below a reference value This means that it secures the power up as well as the power down keeping the ST6 in reset
63. dif ferent address spaces are available Program space Data space and Stack space Program space contains the instructions which are to be ex ecuted plus the data for immediate mode instruc tions Data space contains the Accumulator the X Y V and W registers peripheral and Input Output registers the RAM locations and Data ROM loca tions for storage of tables and constants Stack space contains six 12 bit RAM cells used to stack the return addresses for subroutines and inter rupts Immediate In immediate addressing mode the operand of the instruction follows the opcode loca tion As the operand is a ROM byte the immediate addressing mode is used to access constants which do not change during program execution e g a constant used to initialize a loop counter Direct In direct addressing mode the address of the byte which is processed by the instruction is stored in the location which follows the opcode Di rect addressing allows the user to directly address the 256 bytes in Data Space memory with a single two byte instruction Short Direct The core can address the four RAM registers X Y V W locations 80h 81h 82h 83h in short direct addressing mode In this case the instruction is only one byte and the selection of the location to be processed is contained in the op code Short direct addressing is a subset of direct addressing mode Note that 80h and 81h are also indirect registers Extended In exte
64. direct addressing mode as pointers to memory locations in Data Space They can also be accessed in Direct Short Direct or Bit Direct addressing modes They are mapped in Data Space at addresses 80h X and 81h Y and can be accessed like any other memory location Short Direct Registers V W These two regis ters are used in Short Direct addressing mode This means that the data stored in V or W can be accessed with a one byte instruction four CPU cy cles V and W can also be accessed using Direct and Bit Direct addressing modes They are mapped in Data Space at addresses 82h V and 83h W and can be accessed like any other mem ory location Note The X and Y registers can also be used as Short Direct registers in the same way as V and W Program Counter PC The program counter is a 12 bit register which contains the address of the next instruction to be executed by the core This ROM location may be an opcode an operand or the address of an operand 7 0 RESET VALUE xxh 7 0 RESET VALUE xxh 7 0 RESET VALUE xxh 7 0 RESET VALUE xxh 7 0 RESET VALUE xxh 41 0 RESET VALUE RESET VECTOR OFFEh OFFFh ACCUMULATOR X INDEX REGISTER Y INDEX REGISTER V SHORT INDIRECT REGISTER W SHORT INDIRECT REGISTER PROGRAM COUNTER SIX LEVEL STACK E CNMI ZNMI NORMAL FLAGS INTERRUPT FLAGS NMI FLAGS x Undefined value ky 17 104 ST6208C ST6209C ST6210C ST62
65. dog enabled and EXTCNTL option disabled If a STOP instruction is encountered it is interpreted as a WAIT 3 Watchdog and EXTCNTL option enabled ters STOP mode When the MCU exits STOP mode i e when an interrupt is generated the Watchdog resumes its activity 8 1 6 Interrupts None 44 104 ST6208C ST6209C ST6210C ST6220C WATCHDOG TIMER Cont d 8 1 7 Register Description WATCHDOG REGISTER WDGR Address 0D8h Read Write Reset Value 1111 1110 FEh 7 0 Bits 7 2 T 5 0 Downcounter bits Caution These bits are reversed and shifted with respect to the physical counter bit 7 TO is the LSB of the Watchdog downcounter and bit 2 T5 is the MSB Bit 1 SR Software Reset bit Software can generate a reset by clearing this bit while the C bit is set When C 0 Watchdog de activated the SR bit is the MSB of the 7 bit timer 0 Generate write 1 No software reset generated MSB of 7 bit timer Bit 0 C Watchdog Control bit If the hardware option is selected WDACT bit in Option byte this bit is forced high and cannot be changed by the user the Watchdog is always ac tive When the software option is selected WDACT bit in Option byte the Watchdog func tion is activated by setting the C bit and cannot then be deactivated except by resetting the MCU When C is kept cleared the counter can be used as a 7 bit timer 0 Watchdog deactivated 1 Watchdog activated 45 104 ST6208C
66. e 8 bit counter can be initialized separately by writing to the TCR register 8 2 3 1 8 bit Counting and Interrupt Capability on Counter Underflow Whatever the division factor defined for the pres caler the Timer Counter works as an 8 bit down counter The input clock frequency is user selecta ble using the PS 2 0 bits When the downcounter decrements to zero the TMZ Timer Zero bit in the TSCR is set If the ETI Enable Timer Interrupt bit in the TSCR is also set an interrupt request is generated The Timer interrupt can be used to exit the MCU from WAIT or STOP mode The TCR can be written at any time by software to define a time period ending with an underflow event and therefore manage delay or timer func tions TMZ is set when the downcounter reaches zero however it may also be set by writing 00h in the TCRregister or by setting bit 7 of the TSCR register The TMZ bit must be cleared by user software when servicing the timer interrupt to avoid unde sired interrupts when leaving the interrupt service routine Note A write to the TCR register will predominate over the 8 bit counter decrement to 00h function i e if a write and a TCR register decrement to 00h occur simultaneously the write will take prece dence and the TMZ bit is not set until the 8 bit counter underflows again 47 104 ST6208C ST6209C ST6210C ST6220C 8 BIT TIMER Cont d 8 2 4 Functional Description There are three operating modes
67. e device summary on page 1 Reserved 38 Bytes 12 104 ky MEMORY MAP Conta 3 1 6 Data ROM Window The Data read only memory window is located from address 0040h to address 007Fh in Data space lt allows direct reading of 64 consecutive bytes located anywhere in program memory be tween address 0000h and OFFFh There are 64 blocks of 64 bytes in a 4K device Block 0 is related to the address range 0000h to 003Fh Block 1 is related to the address range 0040h to 007Fh and so on All the program memory can therefore be used to store either instructions or read only data The Data ROM window can be moved in steps of 64 bytes along the program memory by writing the appropriate code in the Data ROM Window Regis ter DRWR Figure 5 Data ROM Window PROGRAM 0000h SPACE 000h DATA SPACE DATA ROM WINDOW ST6208C ST6209C ST6210C ST6220C 3 1 6 1 Data ROM Window Register DRWR The DRWR can be addressed like any RAM loca tion in the Data Space This register is used to select the 64 byte block of program memory to be read in the Data ROM win dow from address 40h to address 7Fh in Data space The DRWR register is not cleared on re set therefore it must be written to before access ing the Data read only memory window area for the first time Address 0C9h Write Only Reset Value xxh undefined 7 0 jones DRWR4 DRWR3 DRWR2 DRWR1 DRWRO Bits 7 6 Reserved must be
68. ecified all voltages are re ferred to Vss 10 1 1 Minimum and Maximum Values Unless otherwise specified the minimum and max imum values are guaranteed in the worst condi tions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at T 25 C and T T max given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the min imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 32 10 1 2 Typical Values Unless otherwise specified typical data are based on Ta 25 C Vpp 5V for the 4 5V lt Vpp lt 6 0V voltage range and Vpp 3 3V for the 3V lt Vpp lt 3 6V voltage range They are given only as design guidelines and are not tested 10 1 3 Typical Curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested 10 1 4 Loading Capacitor The loading conditions used for pin parameter measurement is shown in Figure 36 62 104 Figure 36 Pin Loading Conditions Lo CL 1 ST6 PIN 10 1 5 Pin Input Voltage The input voltage measurement on a pin of the de vice is described in Figure 37 Figure 37 Pin Input Voltage ST6 PIN ST6208C ST6209C ST6
69. ed at the quartz crystal frequency 2 When the OSG is disabled operation in this area is guaranteed at the crystal frequency When the OSG is enabled operation in this area is guaranteed at a frequency of at least fosa Min 3 When the OSG is disabled operation in this area is guaranteed at the quartz crystal frequency When the OSG is enabled access to this area is prevented The internal frequency is kept at fosa 64 104 ST6208C ST6209C ST6210C ST6220C OPERATING CONDITIONS Cont d 10 3 2 Operating Conditions with Low Voltage Detector LVD Subject to general operating conditions for Vpp fosc and Ta V Reset release threshold dea Vpp rise V Reset generation threshold E Vpp fall g LVD voltage threshold hysteresis Filtered glitch delay on Vpp Not detected by the LVD Notes 1 LVD typical data are based on Ta 25 C They are given only as design guidelines and are not tested 2 The minimum Vpp rise time rate is needed to insure a correct device power on and LVD reset Not tested in production 3 Data based on characterization results not tested in production Figure 39 LVD Threshold Versus Vpp and fosc FUNCTIONALITY fosc MHz NOT GUARANTEED IN THIS AREA DEVICE UNDER 7 RESET IN THIS AREA 4 _ FUNCTIONAL AREA SUPPLY 0 VOLTAGE V Figure 40 Typical LVD Thresholds Versus Figure 41 Typical LVD thresholds vs Temperature for OTP devices Temperature for ROM devices Thresholds V
70. edge of the fcounTer clock signal coming from the prescaler It is possible to read or write the contents of the counter on the fly by reading or writing the timer counter register TCR When the downcounter reaches 0 it is automati cally reloaded with the value OFFh Counter Clock and Prescaler The counter clock frequency is given by PS 2 0 fcounter fpRescaLer 2000 where fpRESCALER can be finy 12 fexr input on TIMER pin finr 12 gated by TIMER pin The timer input clock feeds the 7 bit programma ble prescaler The prescaler output can be pro grammed by selecting one of the 8 available pres caler taps using the PS 2 0 bits in the Status Con trol Register TSCR Thus the division factor of the prescaler can be set to 2 where n equals 0 to 7 See Figure 27 The clock input is enabled by the PSI Prescaler Initialize bit in the TSCR register When PSI is re set the counter is frozen and the prescaler is load ed with the value 7Fh When PSI is set the pres Y ST6208C ST6209C ST6210C ST6220C caler and the counter run at the rate of the select ed clock source Counter and Prescaler Initialization After RESET the counter and the prescaler are in itialized to OFFh and 7Fh respectively The 7 bit prescaler can be initialized to 7Fh by clearing the PSI bit Direct write access to the prescaler is also possible when PSI 1 Then any value between 0 and 7Fh can be loaded into it Th
71. ernal components Refer to the crystal ceramic Only parallel resonant crystals can be used All the resonator manufacturer for more details frequen information given in this paragraph are based on cy package accuracy Parameter Feedback resistor Recommended load capacitances versus equiva lent crystal or ceramic resonator frequency Typical Crystal or Ceramic Resonators Reference Freq Characteristic SSBS Afosc 0 5 tolerance 0 3 14Ta 0 3 aging Notes 1 Resonator characteristics given by the crystal ceramic resonator manufacturer 2 tsy og S the typical oscillator start up time measured between Vpp 2 8V and the fetch of the first instruction with a quick Vhp ramp up from 0 to 5V lt 50us 3 The oscillator selection can be optimized in terms of supply current using an high quality resonator with small Rg value Refer to crystal ceramic resonator manufacturer for more details Figure 50 Typical Application with a Crystal or Ceramic Resonator ST62XX 73 104 Y ST6208C ST6209C ST6210C ST6220C CLOCK AND TIMING CHARACTERISTICS Cont d 10 5 4 RC Oscillator The ST6 internal clock can be supplied with an external RC oscillator Depending on the Ryner value the accuracy of the frequency is about 20 so it may not be suitable for some applications Symb Parameter Conditions win Typ Max Unt RC oscillator frequency 1 0 5 0 55 0 6 RC Oscillator external resistor see Figure
72. f supply voltage to ensure correct operation even if the power supply drops 5 1 2 1 Spike Filtering Spikes on the oscillator lines result in an effectively increased internal clock frequency In the absence of an OSG circuit this may lead to an over fre quency for a given power supply voltage The OSG filters out such spikes as illustrated in Figure 10 In all cases when the OSG is active the max Figure 10 OSG Filtering Function foscsfose MAIN OSCILLATOR STOPS ST6208C ST6209C ST6210C ST6220C imum internal clock frequency fint is limited to fosa which is supply voltage dependent 5 1 2 2 Management of Supply Voltage Variations Over frequency at a given power supply level is seen by the OSG as spikes it therefore filters out some cycles in order that the internal clock fre quency of the device is kept within the range the particular device can stand depending on Vpp and below fosa the maximum authorised frequen cy with OSG enabled 5 1 2 3 LFAO Management When the OSG is enabled the Low Frequency Auxiliary Oscillator can be used see Section 5 1 3 Note The OSG should be used wherever possible as it provides maximum security for the applica tion lt should be noted however that it can in crease power consumption and reduce the maxi mum operating frequency to fosa see Electrical Characteristics section Caution Care has to be taken when using the OSG as the internal frequency
73. ial Ipp measurement between reset configuration with LVD disabled and LVD enabled Data based on a differential Ipp measurement between reset configuration timer disabled and timer running Data based on a differential Ipp measurement between reset configuration and continuous A D conversions NOOA Y 71 104 ST6208C ST6209C ST6210C ST6220C 10 5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for Vpp fosc and Ta 10 5 1 General Timings Instruction cycle time t Interrupt reaction time 2 D tvm AtegnsT 6 10 5 2 External Clock Source V OSC input pin high level voltage OSCINH IN p p g g ee Figure 49 VoscinL OSCy input pin low level voltage S I OSCx Input leakage current Notes 1 Data based on typical application software 2 Time measured between interrupt event and interrupt vector fetch At msr is the number of tcpy cycles needed to finish the current instruction execution Figure 49 Typical Application with an External Clock Source 90 VoscinH L JE TT A Jf VoscinL Not connected fosc EXTERNAL CLOCK SOURCE SLL ST62XX 72 104 ST6208C ST6209C ST6210C ST6220C CLOCK AND TIMING CHARACTERISTICS Cont d 10 5 3 Crystal and Ceramic Resonator Oscillators The ST6 internal clock can be supplied with sever characterization results with specified typical ex al different Crystal Ceramic resonator oscillators t
74. ion Note Setting this bit automatically clears the EOC bit If the bit is set again when a conversion is in progress the present conversion is stopped and a new one will take place This bit is write only any attempt to read it will show a logical zero Bit 4 PDS Power Down Selection 0 A D converter is switched off 1 A D converter is switched on Bit 3 ADCR3 Reserved must be cleared Bit 2 OSCOFF Main Oscillator off 0 Main Oscillator enabled 1 Main Oscillator disabled Note This bit does not apply to the ADC peripher al but to the main clock system Refer to the Clock System section Bits 1 0 ADCR 1 0 Reserved must be cleared A D CONVERTER DATA REGISTER ADR Address 0DOh Read only Reset value xxxx xxxx xxh 7 0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADRO Bits 7 0 ADR 7 0 8 Bit A D Conversion Result 55 104 ST6208C ST6209C ST6210C ST6220C 9 INSTRUCTION SET 9 1 ST6 ARCHITECTURE The ST6 architecture has been designed for max imum efficiency while keeping byte usage to a minimum in short to provide byte efficient pro gramming The ST6 core has the ability to set or clear any register or RAM location bit in Data space using a single instruction Furthermore pro grams can branch to a selected address depend ing on the status of any bit in Data space 9 2 ADDRESSING MODES The ST6 has nine addressing modes which are described in the following paragraphs Three
75. ipheral interrupt routines The Non Maskable Interrupt request has the highest priority and can interrupt any peripheral interrupt routine at any time but cannot interrupt another NMI interrupt No peripheral interrupt can interrupt another If more than one interrupt request is pending these are processed by the processor core according to their priority level vector 1 has the highest priority while vector 4 the lowest The priority of each interrupt source is fixed by hardware see Interrupt Mapping table 5 6 INTERRUPTS AND LOW POWER MODES All interrupts cause the processor to exit from WAIT mode Only the external and some specific interrupts from the on chip peripherals cause the processor to exit from STOP mode refer to the Exit from STOP column in the Interrupt Mapping Table 28 104 5 7 NON MASKABLE INTERRUPT This interrupt is triggered when a falling edge oc curs on the NMI pin regardless of the state of the GEN bit in the IOR register An interrupt request on NMI vector 0 is latched by a flip flop which is automatically reset by the core at the beginning of the NMI service routine 5 8 PERIPHERAL INTERRUPTS Different peripheral interrupt flags in the peripheral control registers are able to cause an interrupt when they are active if both The GEN bit of the IOR register is set The corresponding enable bit is set in the periph eral control register Peripheral interrupts are linked to
76. ir priority In the event of a non maskable interrupt the non maskable interrupt service routine is proc essed first then the routine in which the WAIT or STOP mode was entered will be completed by executing the instruction following the STOP or WAIT instruction The MCU remains in normal in terrupt mode 6 4 2 Recommended MCU Configuration For lowest power consumption during RUN or WAIT modes the user software must configure the MCU as follows Configure unused I Os as output push pull low mode Place all peripherals in their power down modes before entering STOP mode Select the Low Frequency Auxiliary Oscillator provided this runs at a lower frequency than the main oscillator The WAIT and STOP instructions are not execut ed if an enabled interrupt request is pending 71 0 PORTS 7 1 INTRODUCTION Each I O port contains up to 8 pins Each pin can be programmed independently as digital input with or without pull up and interrupt generation digital output open drain push pull or analog in put when available The I O pins can be used in either standard or al ternate function mode Standard I O mode is used for Transfer of data through digital inputs and out puts on specific pins External interrupt generation Alternate function mode is used for Alternate signal input output for the on chip peripherals The generic I O block diagram is shown in Figure 23
77. iskette or by electronic means with the hexadecimal file generated by the development tool All unused bytes must be set to FFh The selected options are communicated to STMicroelectronics using the correctly filled OP TION LIST appended See page 97 The STMicroelectronics Sales Organization will be pleased to provide detailed information on con tractual points Listing Generation and Verification When STMicroelectronics receives the user s ROM con tents a computer listing is generated from it This listing refers exactly to the ROM contents and op tions which will be used to produce the specified MCU The listing is then returned to the customer who must thoroughly check complete sign and return it to STMicroelectronics The signed listing forms a part of the contractual agreement for the production of the specific customer MCU 96 104 11 6 1 FASTROM version The ST62P08C P09C P10C and P20C are the Factory Advanced Service Technique ROM FAS TROM versions of ST62T08C TO9C T10C and T20C OTP devices They offer the same functionality as OTP devices but they do not have to be programmed by the customer The customer code must be sent to STMicroelectronics in the same way as for ROM devices The FASTROM option list has the same options as defined in the programmable option byte of the OTP version It also offers an identifier option If this option is enabled each FASTROM device is programmed with a unique 5 byte n
78. ist of SO20 Socket Types Same Package Probe Adaptor Socket Reference Footprint Socket Type ENPLAS OTS 20 1 27 04 5020 PENPLAS OTS 20 12704 Open Top YAMAICHI 1C51 0202 714 Clamshell EMU PROBE Adapter from 020 to DIP20 footprint x SMD to DIP delivered with emulator Programming F Adapter Logical Systems PA20S01 08H 6 Open Top Table 25 Suggested List of SSOP20 Socket Types Same Package Probe Adaptor Socket Reference Footprint Socket Type SSOP20 ENPLAS OTS 20 0 65 01 Open Top Programming BT Adapter Logical Systems PA20SS OT 6 Open Top 94 104 ST6208C ST6209C ST6210C ST6220C 11 5 ORDERING INFORMATION The following section deals with the procedure for and also details the ST6 factory coded device transfer of customer codes to STMicroelectronics type Figure 80 ST6 Factory Coded Device Types ST62T20CB6 CCC ROM code Temperature code 1 Standard 0 to 70 C 3 Automotive 40 to 125 C 6 Industrial 40 to 85 C Package type B Plastic DIP D Ceramic DIP M Plastic SOP N Plastic SSOP T Plastic TQFP Revision index B C Product Definition change L Low Voltage Device ST6 Sub family Version Code No char ROM E EPROM P FASTROM T OTP Family 95 104 ST6208C ST6209C ST6210C ST6220C 11 6 TRANSFER OF CUSTOMER CODE Customer code is made up of the ROM contents and the list of the selected FASTROM options The ROM contents are to be sent on d
79. les Table 17 Load amp Store Instructions Instruction Addressing Mode ST6208C ST6209C ST6210C ST6220C Load amp Store These instructions use one two or three bytes depending on the addressing mode For LOAD one operand is the Accumulator and the other operand is obtained from data memory using one of the addressing modes For Load Immediate one operand can be any of the 256 data space bytes while the other is always immediate data LD A X LD A Y LD A V LD A W LD X A LD Y A LD V A LD W A LD A rr LD rr A LD A X LD A Y LD X LD Y Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Indirect Indirect A A LDI A N LDI rr N Immediate Immediate Legend X Y Index Registers V W Short Direct Registers Immediate data stored in ROM memory rr Data space register A Affected id Not Affected Y O nrpml a a pop a a a a o do RRR RRR RRP HRHPHRHPHR A DibD gt Dp gt gt D gt DDPOODODO ON 57 104 ST6208C ST6209C ST6210C ST6220C INSTRUCTION SET Cont d Arithmetic and Logic These instructions are either a data space memory location or an imme used to perform arithmetic calculations and logic diate value In CLR DEC INC instructions the op operations In AND ADD CP SUB instructions erand can be any of the 256 data space address one operand is always the accu
80. me is not long enough to reset external circuits For more details refer to the Watchdog Timer chapter 5 3 5 LVD Reset Two different RESET sequences caused by the in ternal LVD circuitry can be distinguished m Power On RESET Voltage Drop RESET During an LVD reset the RESET pin is pulled low when Vop lt V r rising edge or Vpp lt V falling edge For more details refer to the LVD chapter Caution Do not externally connect directly the RESET pin to Vpp this may cause damage to the component in case of internal RESET Watchdog or LVD Figure 15 Simple External Reset Circuitry Typical R 10K C 10nF 26 104 Figure 16 Reset Processing 2048 CLOCK CYCLE DELAY INTERNAL RESET NMI MASK SET INT LATCH CLEARED IF PRESENT SELECT NMI MODE FLAGS PUT FFEh ON ADDRESS BUS IS RESET STILL PRESENT NO LOAD PC FROM RESET LOCATIONS FFEh FFFh FETCH INSTRUCTION 5 4 INTERRUPTS The ST6 core may be interrupted by four maska ble interrupt sources in addition to a Non Maska ble Interrupt NMI source The interrupt process ing flowchart is shown in Figure 18 Maskable interrupts must be enabled by setting the GEN bit in the IOR register However even if they are disabled GEN bit 0 interrupt events are latched and may be processed as soon as the GEN bit is set Each source is associated with a specific Interrupt Vector located in Program space see Table 8 In the vector l
81. mulator while de es In COM RLC SLA the operand is always the pending on the addressing mode the other can be accumulator Table 18 Arithmetic amp Logic Instructions O ADD A X Indirect 1 4 A A ADD A Y Indirect 1 4 A A ADD A rr Direct 2 4 A A ADDI A N Immediate 2 4 A A AND A X Indirect 1 4 A A AND A Y Indirect 1 4 A A AND A rr Direct 2 4 A A ANDI A N Immediate 2 4 A A CLRA Short Direct 2 4 A A CLRr Direct 3 4 hi COM A Inherent 1 4 A A CP A X Indirect 1 4 A A CP A Y Indirect 1 4 A A CP A rr Direct 2 4 A A CPI A N Immediate 2 4 A A DEC X Short Direct 1 4 A E DEC Y Short Direct 1 4 A DEC V Short Direct 1 4 A DEC W Short Direct 1 4 A DECA Direct 2 4 A DEC rr Direct 2 4 A DEC X Indirect 1 4 A DEC Y Indirect 1 4 A INC X Short Direct 1 4 A INC Y Short Direct 1 4 A INC V Short Direct 1 4 A INC W Short Direct 1 4 A INC A Direct 2 4 A INC rr Direct 2 4 A INC X Indirect 1 4 A INC Y Indirect 1 4 A RLC A Inherent 1 4 A SLA A Inherent 2 4 A SUB A X Indirect 1 4 A SUB A Y Indirect 1 4 A SUB A rr Direct 2 4 A SUBI A N Immediate 2 4 A Notes X Y Index Registers Immediate data stored in ROM memory V W Short Direct Registers Not Affected A Affected rr Data space register 58 104 ky INSTRUCTION SET Cont d Conditional Branch Branch instructions perform a branch in the program when the selected condi tion is met Bit Manipulation In
82. nded addressing mode the 12 bit address needed to define the instruction is ob tained by concatenating the four least significant bits of the opcode with the byte following the op code The instructions JP CALL which use ex 56 104 tended addressing mode are able to branch to any address in the 4 Kbyte Program space Extended addressing mode instructions are two bytes long Program Counter Relative Relative addressing mode is only used in conditional branch instruc tions The instruction is used to perform a test and if the condition is true a branch with a span of 15 to 16 locations next to the address of the relative instruction If the condition is not true the instruc tion which follows the relative instruction is execut ed Relative addressing mode instructions are one byte long The opcode is obtained by adding the three most significant bits which characterize the test condition one bit which determines whether it is a forward branch when it is 0 or backward branch when it is 1 and the four least significant bits which give the span of the branch Oh to Fh which must be added or subtracted from the ad dress of the relative instruction to obtain the branch destination address Bit Direct In bit direct addressing mode the bit to be set or cleared is part of the opcode and the byte following the opcode points to the address of the byte in which the specified bit must be set or cleared Thus any bit in the
83. ne fff Vin LSBipeaL 253 254 255 256 VDDA Note ADC not present on some devices See device summary on page 1 Y 89 104 ST6208C ST6209C ST6210C ST6220C 11 GENERAL INFORMATION 11 1 PACKAGE MECHANICAL DATA Figure 74 20 Pin Plastic Dual In Line Package 300 mil Width oa ere AN f UO O O O UU O AU A IL she Number of Pins Figure 75 20 Pin Ceramic Side Brazed Dual In Line Package e sse oas ose o 1ao ooralo ne Cer 1 14 1270 176 ooss osooJo 07 o 2 695 225 970 990 o00f 020 Cor eso foso er ese 740 500 o2rsozsjosia ef ese oro 7 Le 535550538 0 250 o 260 0270 Cen e47 875 e98 josrajossalo sa five pos 7 s peno pao o f pr coireow Number ofPins 90 104 PACKAGE MECHANICAL DATA Cont d Figure 76 20 Pin Plastic Small Outline Package 300 mil Width ST6208C ST6209C ST6210C ST6220C OOOO N OM O BAS h x 45x m f me Pa a a z eeso fotoa ar oro 020 Joos oor Pe oss fost oora foso e o2s osz jooo fosil o frase frsoofoas ost E r A 760 Jozei LE re pa p n oo frossjosea foars n 02s 07s foor fool afe fejo e Pe fea eroe feo E Number oF Pins Number of Pins PN Figure 77 20 Pin Plastic Shrink Small Outline Package Paz res 175 85 0065 068 0073 rs foel E foss as ors oa rezos Pf Number of Pins ee ON
84. nics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2003 STMicroelectronics All rights reserved STMicroelectronics GROUP OF COMPANIES Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States www st com y 104 104
85. o high transition indicates that the timer count register has underflowed It means that the TCR value has changed from 00h to FFh This bit must be cleared by user software 0 Counter has not underflowed 1 Counter underflow occurred Bit 6 ETI Enable Timer Interrupt When set enables the timer interrupt request If ST6208C ST6209C ST6210C ST6220C ETI 0 the timer interrupt is disabled If ETl 1 and TMZ 1 an interrupt request is generated 0 Interrupt disabled reset state 1 Interrupt enabled Bit 5 TOUT Timer Output Control When low this bit selects the input mode for the TIMER pin When high the output mode is select ed 0 Input mode reset state 1 Output mode the TIMER pin is configured as push pull output Bit 4 DOUT Data Output Data sent to the timer output when TMZ is set high output mode only Input mode selection input mode only Bit 3 PSI Prescaler Initialize bit Used to initialize the prescaler and inhibit its count ing When PSI 0 the prescaler is set to 7Fh and the counter is inhibited When PSI 1 the prescal er is enabled to count downwards As long as PSE 1 both counter and prescaler are not run ning 0 Counting disabled 1 Counting enabled Bits 1 0 PS 2 0 Prescaler Mux Select These bits select the division ratio of the prescaler register Table 14 Prescaler Division Factors Ps2 Pst PSO Divided by 1 220000 Table 15 8 Bit Timer
86. ocation the user must write a Jump in Figure 17 Interrupts Block Diagram LATCH E ST6208C ST6209C ST6210C ST6220C struction to the associated interrupt service rou tine When an interrupt source generates an interrupt request the PC register is loaded with the address of the interrupt vector which then causes a Jump to the relevant interrupt service routine thus serv icing the interrupt Interrupt are triggered by events either on external pins or from the on chip peripherals Several events can be ORed on the same interrupt vector On chip peripherals have flag registers to deter mine which event triggered the interrupt VECTOR 0 CLEARED BY H W AT START OF VECTOR 0 ROUTINE 1 0 PORT REGISTER PAO PA3 INPUT WITH INTERRUPT EH LATCH CONFIGURATION t VECTOR 1 CLEARED BY H W AT START OF VECTOR 1 ROUTINE gt o VO PORT REGISTER INPUT WITH INTERRUPT CONFIGURATION IOR REGISTER t ESB BIT CLEARED ME BY H W AT START OF LES BIT IOR REGISTER EXIT FROM STOP WAIT VECTOR 2 VECTOR 2 ROUTINE TMZ BIT TIMER etipit _ TSCR REGISTER EAIBIT A D CONVERTER EOC BIT ADCR REGISTER VECTOR 3 VECTOR 4 GEN BIT IOR REGISTER Depending on device See device summary on page 1 27 104 ST6208C ST6209C ST6210C ST6220C 5 5 INTERRUPT RULES AND PRIORITY MANAGEMENT A Reset can interrupt the NMI and per
87. ock of the Timer prescaler which is decremented on eve ry rising edge of the input clock allowing event count See Figure 30 and Figure 31 This mode is selected by clearing the TOUT bit in the TSCR register i e as input and clearing the DOUT bit Note In this mode if the TIMER pin is multi plexed the corresponding port control bits have to be set in input with pull up configuration Figure 30 frimer Clock in Event Counter Mode PRESCALER Figure 31 Event Counter Mode Operation COUNTER VALUE VALUE 1 VALUE 2 TIMER PIN 8 2 4 3 Output Mode TOUT 1 DOUT data out In Output mode the TIMER pin is connected to the DOUT latch hence the Timer prescaler is clocked by the prescaler clock input fy 7 12 See Figure 32 The user can select the prescaler division ratio us ingthe PS 2 0 bitsinthe TSCR register When TCR decrements to zero it sets the TMZ bitinthe TSCR The TMZ bit can be tested under program control to perform a timer function whenever it goes high and has to be cleared by the user The low to high TMZ bit transition is used to latch the DOUT bit in the TSCR ana if the TOUT bit is set DOUT is trans ferred to the TIMER pin This operating mode allows external signal generation on the TIMER pin See Figure 33 This mode is selected by setting the TOUT bit in the TSCR register i e as output and setting the DOUT bit to output a high level or clearing the DOUT
88. on PA0 20mA Sink Pin AO IPU Legend Abbreviations for Table 1 Depending on device Please refer to Section 7 I O PORTS on page 37 input O output S supply IPU input with pull up The input with pull up configuration reset state is valid as long as the user software does not change it Refer to Section 7 I O PORTS on page 37 for more details on the software configuration of the I O ports 8 104 ST6208C ST6209C ST6210C ST6220C 3 MEMORY MAPS PROGRAMMING MODES AND OPTION BYTES 3 1 MEMORY AND REGISTER MAPS 3 1 1 Introduction The MCU operates in three separate memory spaces Program space Data space and Stack space Operation in these three memory spaces is described in the following paragraphs Figure 3 Memory Addressing Diagram Briefly Program space contains user program code in OTP and user vectors Data space con tains user data in RAM and in OTP and Stack space accommodates six levels of stack for sub routine and interrupt service routine nesting PROGRAM SPACE 000h PROGRAM MEMORY see Figure 4 on page 10 OFFOh INTERRUPT amp RESET VECTORS OFFFh DATA SPACE 000h RESERVED 03Fh 040h DATA ROM WINDOW 07Fh 080h X REGISTER 081h Y REGISTER 082h V REGISTER 083h W REGISTER 084h OBFh 0COh HARDWARE CONTROL REGISTERS see Table 2 OFFh ACCUMULATOR 9 104 ST6208C ST6209C ST6210C ST6220C MEMORY MAP Cont d Figure 4 P
89. one in a sequence which ensures that no unwanted side effects can occur The recom mended safe transitions are illustrated in Figure 24 The Interrupt Pull up to Input Analog transition and vice vesra is potentially risky and should be avoided when changing the I O operating mode ST6208C ST6209C ST6210C ST6220C 2 Handling Unused Port Bits On ports that have less than 8 external pins con nected Leave the unbonded pins in reset state and do not change their configuration Do not use instructions that act on a whole port register INC DEC or read operations Unavail able bits must be masked by software AND in struction Thus when a read operation performed on an incomplete portis followed by a comparison use a mask 3 High Impedance Input On any CMOS device it is not recommended to connect high impedance on input pins The choice of these impedance has to be done with respect to the maximum leakage current defined in the da tasheet The risk is to be close or out of specifica tion on the input levels applied to the device 7 3 LOW POWER MODES The WAIT and STOP instructions allow the ST62xx to be used in situations where low power consumption is needed The lowest power con sumption is achieved by configuring I Os in output push pull low mode Description WAIT No effect on I O ports External interrupts cause the device to exit from WAIT mode STOP No effect on I O ports External interrupts
90. or der The software activation option should be chosen only when the Watchdog counter is to be used as a timer To ensure the Watchdog has not been un expectedly activated the following instructions should be executed jrr 0 WDGR 3 If C 0 jump to next 1di WDGR OFDH SR 0 gt reset next 43 104 ST6208C ST6209C ST6210C ST6220C WATCHDOG TIMER Cont d These instructions test the C bit and reset the MCU i e disable the Watchdog if the bit is set i e if the Watchdog is active thus disabling the Watchdog For more information on the use of the watchdog please read application note AN1015 8 1 5 Low Power Modes Mode Description 22 WAIT No effect on Watchdog Note This note applies only when the watchdog is used as a standard timer It is recommended to read the counter twice as it may sometimes return an invalid value if the read is performed while the counter is decremented counter bits in transient state To validate the return value both values read must be equal The counter decrements eve ry 384 us at 8 MHZ fosc If a STOP instruction is encountered when the NMI pin is low it is interpreted as a WAIT If however the STOP instruction is encountered when the NMI pin is high the Watchdog counter is frozen and the CPU en STOP Behaviour depends on the EXTCNTL option in the Option bytes 1 Watchdog disabled The MCU will enter Stop mode if a STOP instruction is executed 2 Watch
91. p tion bytes and a a high level is present on the NMI pin In this case the STOP instruction will be exe cuted and the Watchdog will be frozen Figure 21 STOP Mode Timing Overview 2048 CLOCK CYCLE RUN STOP DELAY RUN STOP INSTRUCTION FETCH VECTOR INTERRUPT ST6208C ST6209C ST6210C ST6220C STOP MODE Conta Figure 22 STOP Mode Flowchart STOP INSTRUCTION ENABLE DISABLE OSCILLATOR Off Clock to PERIPHERALS No Clock to CPU OSCILLATOR On Clock to PERIPHERALS Yes Clock to CPU No OSCILLATOR Clock to PERIPHERALS Yes Clock to CPU Yes 2048 CLOCK CYCLE DELAY OSCILLATOR On Clock to PERIPHERALS Yes Clock to CPU Yes Notes FETCH RESET VECTOR OR SERVICE INTERRUPT 1 EXCTNL is an option bit See option byte section for more details 2 Peripheral clocked with an external clock source can still be active 3 Only some specific interrupts can exit the MCU from STOP mode such as external interrupt Refer to the Interrupt Mapping table for more details STA 35 104 ST6208C ST6209C ST6210C ST6220C 6 4 NOTES RELATED TO WAIT AND STOP MODES 6 4 1 Exit from Wait and Stop Modes 6 4 1 1 NMI Interrupt It should be noted that when the GEN bit in the IOR register is low interrupts disabled the NMI interrupt is active but cannot cause a wake up from STOP WAIT modes 6 4 1 2 Restart Sequence When the MCU exits from WAIT or STOP mode it should be noted that the restart sequence de
92. ption After reset the watchdog is permanently active the C bit in the WDGR is forced high and the user can not change it However this bit can be read equally as 0 or 1 SOFTWARE Watchdog option After reset the watchdog is deactivated The func tion is activated by setting C bit in the WDGR reg ister Once activated it cannot be deactivated The counter value stored in the WDGR register bits SR TO is decremented every 3072 clock cy cles The length of the timeout period can be pro grammed by the user in 64 steps of 3072 clock cy cles If the watchdog is activated by setting the C bit and when the SR bit is cleared the watchdog initi ates a reset cycle pulling the reset pin low for typi cally 500ns The application program must write in the WDGR register at regular intervals during normal opera tion to prevent an MCU reset The value to be stored in the WDGR register must be between FEh and 02h see Table 12 To run the watchdog function the following conditions must be true The C bit is set watchdog activated The SR bit is set to prevent generating an imme diate reset The T 5 0 bits contain the number of decre ments which represent the time delay before the watchdog produces a reset Table 12 Watchdog Timing fosc 8 MHz WDGR Register WDG timeout period initial value ms 24 578 i 8 1 3 1 Software Reset The SR bit can be used to generate a software re set by clearing the S
93. r in series with the pad 1 A diode to Vpp 2a and a diode from Vss 2b A protection device between Vpp and Vss 4 Figure 59 Positive Stress on a Standard Pad vs Vss Main path gt gt Path to avoid 80 104 y ST6208C ST6209C ST6210C ST6220C 10 8 I O PORT PIN CHARACTERISTICS 10 8 1 General Characteristics Subject to general operating conditions for Vpp fosc and T unless otherwise specified 200 200 t dojout Output high to low level fall time C 50pF tr IOjout_ Output low to high level rise time gt Between 10 and 90 Rpu Khom 350 Ta 40 C 300 A gt Ta 25 C 250 gt Ta 95 C SK Ta 125 C VDD V Notes 1 Unless otherwise specified typical data are based on Ty 25 C and Vpp 5V 2 Data based on characterization results not tested in production 3 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested 4 The Rpy pull up equivalent resistor is based on a resistive transistor This data is based on characterization results not tested in production 5 Data based on characterization results not tested in production 6 To generate an external interrupt a minimum pulse width has to be applied on an I O port pin configured as an external interrupt source Figure 62 Two typical Applications with unused I O Pin ST62XX UNUSED l O PORT UNUSED I O PORT ST62XX Y 81 104 ST6208C ST6209C ST6210C ST6220C
94. rd Complete T62GP EM ST6208C ST6209C ST6210C ST622XC KIT S G U2 ST62E2XC EPB and ST6220C Dedication board ST62GP DBE 100 104 y ST6208C ST6209C ST6210C ST6220C 13 ST6 APPLICATION NOTES IDENTIFICATION DESCRIPTION MOTOR CONTROL AN392 MICROCONTROLLER AND TRIACS ON THE 110 240V MAINS AN414 CONTROLLING A BRUSH DC MOTOR WITH AN ST6265 MCU AN416 SENSORLESS MOTOR DRIVE WITH THE ST62 MCU TRIAC AN422 IMPROVES UNIVERSAL MOTOR DRIVE AN863 IMPROVED SENSORLESS CONTROL WITH THE ST62 MCU FOR UNIVERSAL MOTOR BATTERY MANAGEMENT AN417 FROM NICD TO NIMH FAST BATTERY CHARGING AN433 ULTRA FAST BATTERY CHARGER USING ST6210 MICROCONTROLLER AN859 AN INTELLIGENT ONE HOUR MULTICHARGER FOR Li lon NiMH and NiCd BATTERIES HOME APPLIANCE AN674 MICROCONTROLLERS IN HOME APPLIANCES A SOFT REVOLUTION AN885 ST62 MICROCONTROLLERS DRIVE HOME APPLIANCE MOTOR TECHNOLOGY GRAPHICAL DESIGN AN676 BATTERY CHARGER USING THE ST6 REALIZER AN677 PAINLESS MICROCONTROLLER CODE BY GRAPHICAL APPLICATION DESCRIPTION AN839 ANALOG MULTIPLE KEY DECODING USING THE ST6 REALIZER AN840 CODED LOCK USING THE ST6 REALIZER AN841 A CLOCK DESIGN USING THE ST6 REALIZER AN842 7 SEGMENT DISPLAY DRIVE USING THE ST6 REALIZER COST REDUCTION AN431 USING ST6 ANALOG INPUTS FOR MULTIPLE KEY DECODING AN594 DIRECT SOFTWARE LCD DRIVE WITH ST621X AND ST626X AN672 OPTIMIZING THE ST6 A D
95. rogram Memory Map ST6208C 09C ST6210C ST6220C RESERVED a NOT IMPLEMENTED Vp NOTIMPLEMENTED RESERVED USER PROGRAM MEMORY RESERVED 3872 BYTES USER PROGRAM MEMORY USER 1824 BYTES PROGRAM MEMORY 1024 BYTES RESERVED RESERVED RESERVED INTERRUPT VECTORS INTERRUPT VECTORS INTERRUPT VECTORS RESERVED RESERVED RESERVED NMI VECTOR NMI VECTOR NMI VECTOR USER RESET VECTOR USER RESET VECTOR USER RESET VECTOR Reserved areas should be filled with OFFh 10 104 MEMORY MAP Cont d 3 1 2 Program Space Program Space comprises the instructions to be executed the data required for immediate ad dressing mode instructions the reserved factory test area and the user vectors Program Space is addressed via the 12 bit Program Counter register PC register Thus the MCU is capable of ad dressing 4K bytes of memory directly 3 1 3 Readout Protection The Program Memory in OTP EPROM or ROM devices can be protected against external readout of memory by setting the Readout Protection bit in the option bytes Section 3 3 on page 16 In the EPROM parts Readout Protection option can be desactivated only by U V erasure that also results in the whole EPROM context being erased Note Once the Readout Protection is activated it is no longer possible even for STMicroelectronics to gain access to the OTP or ROM contents Re turned parts can therefore not be accepted if the Readout Protection bit is se
96. rr e v e rr a 1 001 1 per 2 ext 1 per 2 b d 1 per 1 sd 1 prc 2 dir 2 JRANZ 4 JP 2 JRNC 4 RES 2 JRZ 4 RCL 2 JRC 4 AND Nor e abc e b5 rr e a e a y T00 1 per 2 ext 1 per 2 b d 1 per 1 inh 1 prc 1 ind 2 JRANZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 AND cee e abc e b5 rr e va e a rr io 1 per 2 ext 1 per 2 b d 1 per 1 sd 1 prc 2 dir 2 JRANZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RET 2 JRC 4 SUB 1 o e abc e b3 rr e e a y 1 6 1 per 2 ext 1 per 2 b d 1 per 1 inh 1 pre 1 ind 2 JRANZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 SUB 1 Pi e abc e b3 rr e w e a rr 4 ioi 1 per 2 ext 1 per 2 b d 1 per 1 sd 1 prc 2 dir 2 JRANZ 4 JP 2 JRNC 4 RES 2 JRZ 2 WAIT 2 JRC 4 DEC Ad e abc e b7 rr e e y IRo 1 per 2 ext 1 per 2 b d 1 per 1 inh 1 prc 1 ind 2 JRANZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 DEC 1 a 1 e abc e b7 rr e wa e rr 4 E 1 1 per 2 ext 1 per 2 b d 1 per 1 sd 1 prc 2 dir Abbreviations for Addressing Modes Legend dir Direct Indicates Illegal Instructions sd Short Direct e 5 bit Displacement Cycles Mnemonic imm Immediate b 3 bit Address Operands inh Inherent rr 1 byte Data space address Bytes ext Extended nn 1 byte immediate data b d Bit Direct abc 12 bit address i bt Bit Test ee 8 bit Displacement Addressing Mode pcr Program Counter Relative ind Indirect ky 61 104 ST6208C ST6209C ST6210C ST6220C 10 ELECTRICAL CHARACTERISTICS 10 1 PARAMETER CONDITIONS Unless otherwise sp
97. rt x Data Register DRx with x A or B Address DRA 0COh Read Write Address DRB 0C1h Read Write Reset Value 0000 0000 00h 7 0 D7 D6 D5 D4 D3 D2 D1 DO Bits 7 0 D 7 0 Data register bits Reading the DR register returns either the DR reg ister latch content pin configured as output or the digital value applied to the I O pin pin configured as input Caution In input mode modifying this register will modify the I O port configuration see Table 9 Do not use the Single bit instructions on I O port data registers See Section 7 2 5 DATA DIRECTION REGISTER DDR Port x Data Direction Register DDRx with x A or B Address DDRA 0C4h Read Write Address DDRB 0C5h Read Write Reset Value 0000 0000 00h 7 0 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DDO Table 11 I O Port Register Map and Reset Values Address Hex ST6208C ST6209C ST6210C ST6220C Bits 7 0 DD 7 0 Data direction register bits The DDR register gives the input output direction configuration of the pins Each bit is set and cleared by software 0 Input mode 1 Output mode OPTION REGISTER OR Port x Option Register ORx with x A or B Address ORA 0CCh Read Write Address ORB OCDh Read Write Reset Value 0000 0000 00h 7 0 O7 06 O5 04 03 02 O1 00 Bits 7 0 O 7 0 Option register bits The
98. ry 1K 2K 4K bytes RAM bytes Operating Supply 3 0V to 6V Clock Frequency 8MHz Max Operating ARS 5 PDIP20 SO20 SSOP20 CDIP20W Rev 3 3 October 2003 1 104 Table of Contents TINTRODUCTION 202000 A ee Ee A is ee es 6 2 PIN DESGRIPTION ii ee Lee ek Si ee a Se ee Pe i ee et a ae 7 3 MEMORY MAPS PROGRAMMING MODES AND OPTION BYTES oo oooooocooooo 9 3 1 MEMORY AND REGISTER MAPS 00 0c eee eee eee ee 9 Ss Weel ONOI ot tat teat AAA panes E ee ee ba eee AA 9 34112 Programi SPACE cian ea 11 3 1 3 Readout Procion riire Ri o a A 11 3914 Data Space dh o he ds eee ea ae 11 Sidi STACK PACO ira A AA AR A RA 11 3 1 6 Data ROM Window Totana e e a eee eee 13 3 2 PROGRAMMING MODES 00 000 e cece eee eens 15 3 2 1 Program Memory e sissa eei aa e E Rae eee 15 3 2 2 EPROM Erasing im ee he ee EA ROE E ETG 15 3 3 OPTION BYTES Mireka i a O A ree be N 16 4 CENTRAL PROCESSING UNIT 00 cece eee eee 17 4 1 INTRODUCTION 02ec43 cece ia c Sen ee OP ba PE Se ae Be ee 17 4 2 MAIN FEATURES ideer hs bok Rie dl DA bea 17 43 GCRUNREGIS TERS migena peste aa daa 17 5 CLOCKS SUPPLY AND RESET 0 00 c cece eee eee eee 19 5 1 CLOCK SYSTEM mita iiir 22a ed ewe ind dae ye eae Bede ey eS 19 5 1 1 Main Oscillator osen eseu eee Gea yee Sea eee ee oe ea ge ele 20 5 1 2 Oscillator Safeguard OSG 0 cet tee 21 5 1 3 Low Frequency Auxiliary Oscillator LFAO
99. s and peripheral registers are pre served as long as the power supply voltage is higher than the RAM retention voltage The oscillator is kept running to provide a clock to the peripherals they are still active WAIT mode can be used when the user wants to reduce the MCU power consumption during idle periods while not losing track of time or the ability to monitor external events WAIT mode places the MCU in a low power consumption mode by stop ping the CPU The active oscillator main oscillator or LFAO is kept running in order to provide a clock signal to the peripherals If the power consumption has to be further re duced the Low Frequency Auxiliary Oscillator LFAO can be used in place of the main oscillator if its operating frequency is lower If required the LFAO must be switched on before entering WAIT mode Exit from Wait mode The MCU remains in WAIT mode until one of the following events occurs RESET Watchdog LVD or RESET pin A peripheral interrupt timer ADC An external interrupt I O port NMI The Program Counter then branches to the start ing address of the interrupt or RESET service rou tine Refer to Figure 20 See also Section 6 4 1 ST6208C ST6209C ST6210C ST6220C Figure 20 WAIT Mode Flowchart OSCILLATOR On Clock to PERIPHERALS Yes Clock to CPU No WAIT INSTRUCTION OSCILLATOR Restart Clock to PERIPHERALS Yes Clock to CPU Yes 2048 CLOCK CYCLE DEL
100. structions These instruc tions can handle any bit in Data space memory One group either sets or clears The other group see Conditional Branch performs the bit test branch operations Table 19 Conditional Branch Instructions JRCe JRNC e JRZ e JRNZ e JRR b rr ee JRS b rr ee Notes b 3 bitaddress e 5bitsigned displacement in the range 15 to 16 ST6208C ST6209C ST6210C ST6220C Control Instructions Control instructions control microcontroller operations during program execu tion Jump and Call These two instructions are used to perform long 12 bit jumps or subroutine calls to any location in the whole program space Data space register Affected The tested bit is shifted into carry ee 8 bit signed displacement in the range 126 to 129 Not Affected Table 20 Bit Manipulation Instructions Flags Instruction Addressing Mode Bytes Cycles z g C SET b rr Bit Direct 2 4 bl RES b rr Bit Direct 2 4 Notes b 3 bitaddress tr Data space register Not Affected Bit Manipulation Instructions should not be used on Port Data Registers and any registers with read only and or write only bits see I O port chapter Table 21 Control Instructions Inherent Inherent Inherent Inherent Inherent Notes 1 This instruction is deactivated and a WAIT is automatically executed instead of a STOP if the watchdog function is selected A Affected Table 22 Jump amp Call Instructions
101. t 3 1 4 Data Space Data Space accommodates all the data necessary for processing the user program This space com prises the RAM resource the processor core and peripheral registers as well as read only data ST6208C ST6209C ST6210C ST6220C such as constants and look up tables in OTP EPROM 3 1 4 1 Data ROM All read only data is physically stored in program memory which also accommodates the Program Space The program memory consequently con tains the program code to be executed as well as the constants and look up tables required by the application The Data Space locations in which the different constants and look up tables are addressed by the processor core may be thought of as a 64 byte window through which it is possible to access the read only data stored in OTP EPROM 3 1 4 2 Data RAM The data space includes the user RAM area the accumulator A the indirect registers X Y the short direct registers V W the I O port regis ters the peripheral data and control registers the interrupt option register and the Data ROM Win dow register DRWR register 3 1 5 Stack Space Stack space consists of six 12 bit registers which are used to stack subroutine and interrupt return addresses as well as the current program counter contents 11 104 ST6208C ST6209C ST6210C ST6220C MEMORY MAP Cont d Table 2 Hardware Register Map Register Reset 080h X Y index registers 0COh O Ports DRA
102. t allows normal operations to be re sumed Voltage limits to be applied on any I O pin Vpp 5V Ta 25 C fosc 8MHz FESD to induce a functional disturbance conforms to IEC 1000 4 2 Fast transient voltage burst limits to be ap Vpp 5V Ta 25 C fosc 8MHz Verte plied through 100pF on Vpp and Vpp pins SS lo IEC 100084 to induce a functional disturbance Notes 1 Data based on characterization results not tested in production 2 The suggested 10 uF and 0 1 uF decoupling capacitors on the power supply lines are proposed as a good price vs EMC performance tradeoff They have to be put as close as possible to the device power supply pins Other EMC rec ommendations are given in other sections I Os RESET OSCx pin characteristics Figure 56 EMC Recommended Star Network Power Supply Connection 2 ST62XX 10 uF 0 1 uF ST6 POWER SUPPLY 1 DIGITAL NOISE FILTERING y RCE SOURCE 1 close to the MCU VDD i Vss 77 104 ST6208C ST6209C ST6210C ST6220C EMC CHARACTERISTICS Cont d 10 7 2 Absolute Electrical Sensitivity Based on three different tests ESD LU and DLU using specific measurement methods the product is stressed in order to determine its performance in terms of electrical sensitivity For more details re fer to the AN1181 application note 10 7 2 1 Electro Static Discharge ESD Electro Static Discharges 3 positive then 3 nega tive pulses separated by 1 second are
103. t is write only For this reason the DRWR contents should not be changed while executing an interrupt service routine as the service routine cannot save and then restore the register s previ ous contents If it is impossible to avoid writing to the DRWR during the interrupt service routine an image of the register must be saved in a RAM lo cation and each time the program writes to the DRWR it must also write to the image register The image register must be written first so that if an interrupt occurs between the two instructions the DRWR is not affected PROGRAM SPACE 0000h 0400h OFFSET 0421h DATA address in Program memory 421h DATA SPACE 000h 040h OFFSET 21h 061h 07Fh DRWR content 421h 3Fh 64 10H data is located in 64 bytes window number 10h 64 byte window start address 10h x 3Fh 400h Register A X content Offset 421h 400h 40h Data ROM Window start address in data space 61h 14 104 3 2 PROGRAMMING MODES 3 2 1 Program Memory EPROM OTP programming mode is set by a 12 5V voltage applied to the TEST Vpp pin The programming flow of the ST62T08C T09C T10C T20C and E20C is described in the User Manual of the EPROM Programming Board Table 3 ST6208C 09C Program Memory Map 0000h OB9Fh OBAOh OF9Fh OFAOh OFEFh Reserved User ROM Reserved Interrupt Vectors Reserved NMI Interrupt Vector Reset Vector OFFOh OFF7h OFF8h OFFBh OFFCh OFFDh OFF
104. te maximum rating must be respected otherwise refer to Iny en Specification A positive injection is induced by Viy gt Vpp while a negative injection is induced by Viy lt Vss 3 Power Vpp and ground Vss lines must always be connected to the external supply 4 Negative injection disturbs the analog performance of the device In particular it induces leakage currents throughout the device including the analog inputs To avoid undesirable effects on the analog functions care must be taken Analog input pins must have a negative injection less than 1mA assuming that the impedance of the analog voltage is lower than the specified limits Pure digital pins must have a negative injection less than 1mA In addition it is recommended to inject the current as far as possible from the analog input pins Y 63 104 ST6208C ST6209C ST6210C ST6220C 10 3 OPERATING CONDITIONS 10 3 1 General Operating Conditions 1 Suffix Version 0 70 6 Suffix Version 3 Suffix Version Notes 1 An oscillator frequency above 1 2MHz is recommended for reliable A D results 2 Operating conditions with T 40 to 125 C Figure 38 fosc Maximum Operating Frequency Versus Vpp Supply Voltage for OTP amp ROM devices fosc MHz 1 amp 6 suffix version eaten 6 NOT GUARANTEED FUNCTIONALITY IN THIS AREA 1 1 1 AA 1 a a gt SUPPLY 2 5 3 3 6 4 4 5 VOLTAGE Vpp 1 In this area operation is guarante
105. ted at low to me dium complexity applications All ST62xx devices are based on a building block approach a com mon core is surrounded by a number of on chip peripherals The ST62E20C is the erasable EPROM version of the ST62T08C TO9C T10C and T20C devices which may be used during the development phase for the ST62T08C TO9C T10C and T20C target devices as well as the respective ST6208C 09C 10C and 20C ROM devices OTP and EPROM devices are functionally identi cal OTP devices offer all the advantages of user programmability at low cost which make them the ideal choice in a wide range of applications where frequent code changes multiple code versions or last minute programmability are required The ROM based versions offer the same function ality selecting the options defined in the program Figure 1 Block Diagram mable option bytes of the OTP EPROM versions in the ROM option list See Section 11 6 on page 96 The ST62P08C P09C P10C P20C are the Factory Advanced Service Technique ROM FASTROM versions of ST62T08C TO9C T10C and T20C OTP devices They offer the same functionality as OTP devices but they do not have to be programmed by the customer See Section 11 on page 90 These compact low cost devices feature a Timer comprising an 8 bit counter with a 7 bit program mable prescaler an 8 bit A D Converter with up to 8 analog inputs depending on device and a Dig ital Watchdog timer making them well sui
106. ted for a wide range of automotive appliance and industrial applications For easy reference all parametric data are located in Section 11 on page 90 DATA ROM USER SELECTABLE PROGRAM MEMORY 1K 2K or 4K Bytes DATA RAM 64 Bytes STACK LEVEL 1 8 BIT CORE OSCILLATOR cle VppVss OSCin OSCout RESET Depending on device Please refer to I O Port section lt gt lt q E gt PAO PAS 20mA Sink lt Y E gt PBO PB7 Ain LL TIMER WATCHDOG gt TIMER 6 104 ST6208C ST6209C ST6210C ST6220C 2 PIN DESCRIPTION Figure 2 20 Pin Package Pinout Voo 1 Vss TIMER g 2 PA0 20mA Sink OSCin 93 E PA1 20mA Sink OSCout 4 PA2 20mA Sink NMI 5 PA3 20mA Sink Vpp 16 PBO Ain RESET 7 PB1 Ain Ain PB7 8 l PB2 Ain Ain PB6 9 PB3 Ain Ain PB5 J 10 PB4 Ain itX associated interrupt vector Depending on device Please refer to I O Port section Table 1 Device Pin Description Main Function after Reset os fonera e foson MN ESTE A A ME CES 1 Non maskable interrupt falling edge sensitive Must be held at Vss for normal operation if a 12 5V level is applied to the pin during the reset phase the device enters EPROM programming mode Alternate Function RESET o I O Top priority non maskable interrupt active low prs fie i pa ase Ce popes e 7 104 ST6208C ST6209C ST6210C ST6220C Main Functi
107. theless the WAIT instruction should be executed as soon as possible after the beginning of the conversion because execution of the WAIT instruction may cause a small variation of the Vpp voltage The negative effect of this var iation is minimized at the beginning of the conver sion when the converter is less sensitive rather than at the end of conversion when the least sig nificant bits are determined The best configuration from an accuracy stand point is WAIT mode with the Timer stopped In this case only the ADC peripheral and the oscilla tor are then still working The MCU must be woken up from WAIT mode by the ADC interrupt at the end of the conversion The microcontroller can also be woken up by the Timer interrupt but this means the Timer must be running and the result ing noise could affect conversion accuracy Caution When an I O pin is used as an analog in put A D conversion accuracy will be impaired if negative current injections Vin lt Vss occur from adjacent I O pins with analog input capability Re fer to Figure 35 To avoid this Use another I O port located further away from the analog pin preferably not multiplexed on the A D converter Increase the input resistance Rin y to reduce the current injections and reduce Rape to preserve conversion accuracy Figure 35 Leakage from Digital Inputs I O Port Digital I O salad Current if Ving lt Vss A D Converter ky A D C
108. tion 8 3 3 1 Analog Power Supply The high and low level reference voltage pins are internally connected to the Vpp and Vss pins Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines 8 3 3 2 Digital A D Conversion Result The conversion is monotonic meaning that the re sult never decreases if the analog input does not and never increases if the analog input does not If the input voltage Vain is greater than or equal to Vppa high level voltage reference then the conversion result in the DR register is FFh full scale without overflow indication If input voltage Vam is lower than or equal to Vssa low level voltage reference then the con version result in the DR register is 00h The A D converter is linear and the digital result of the conversion is stored in the ADR register The accuracy of the conversion is described in the par ametric section Rain is the maximum recommended impedance for an analog input signal If the impedance is too high this will result in a loss of accuracy due to leakage and sampling not being completed in the allocated time Refer to the electrical characteris tics chapter for more details With an oscillator clock frequency less than 1 2MHz conversion accuracy is decreased 8 3 3 3 Analog Input Selection Selection of the input pin is done by configuring the related I O line as an analog input
109. tions that means when a device belongs to Class A it exceeds the JEDEC standard B Class strictly covers all the JEDEC criteria international standard 2 Schaffner NSG435 with a pointed test finger Figure 58 Simplified Diagram of the ESD Generator for DLU Roy 50MQ DISCHARGE TIP L Cs 150pF HV RELAY ESD GENERATOR 2 DISCHARGE RETURN CONNECTION 79 104 ST6208C ST6209C ST6210C ST6220C EMC CHARACTERISTICS Cont d 10 7 3 ESD Pin Protection Strategy To protect an integrated circuit against Electro Static Discharge the stress must be controlled to prevent degradation or destruction of the circuit el ements The stress generally affects the circuit el ements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress The elements to be pro tected must not receive excessive current voltage or heating within their structure An ESD network combines the different input and output ESD protections This network works by al lowing safe discharge paths for the pins subjected to ESD stress Two critical ESD stress cases are presented in Figure 59 and Figure 60 for standard pins Standard Pin Protection To protect the output structure the following ele ments are added A diode to Vpp 3a and a diode from Vss 3b A protection device between Vpp and Vss 4 To protect the input structure the following ele ments are added A resisto
110. tor 1 Ext Interrupt Port A FF6h FF7h Vector 2 Ext Interrupt Port B Vector 3 TIMER Timer underflow TSCR FF2h FF3h Lowest Vector 4 End Of Conversion ADCR Fron Frin Priority Depending on device See device summary on page 1 31 104 ST6208C ST6209C ST6210C ST6220C 6 POWER SAVING MODES 6 1 INTRODUCTION To give alarge measure of flexibility to the applica tion in terms of power consumption two main pow er saving modes are implemented in the ST6 see Figure 19 In addition the Low Frequency Auxiliary Oscillator LFAO can be used instead of the main oscillator to reduce power consumption in RUN and WAIT modes After a RESET the normal operating mode is se lected by default RUN mode This mode drives the device CPU and embedded peripherals by means of a master clock which is based on the main oscillator frequency From Run mode the different power saving modes may be selected by calling the specific ST6 software instruction or for the LFAO by setting the relevant register bit For more information on the LFAO please refer to the Clock chapter Figure 19 Power Saving Mode Transitions POWER CONSUMPTION 32 104 6 2 WAIT MODE The MCU goes into WAIT mode as soon as the WAIT instruction is executed This has the follow ing effects Program execution is stopped the microcontrol ler software can be considered as being in a fro zen state RAM content
111. tp Awww elnec com http www hilosystems com tw http Awww icetech com http Awww leap com tw http Awww lloyd research com http www chipprogram mers com http www mqp com http Awww needhams com http Awww stag co uk http Awww sg com tw http www tribalmicro com http www xeltek com Note 1 For latest information on third party tools please visit our Internet site Y gt http mcu st com 99 104 ST6208C ST6209C ST6210C ST6220C DEVELOPMENT TOOLS Conta STMicroelectronics Tools Four types of development tool are offered by ST all of them connect to a PC via a parallel or serial port see Table 27 and Table 28 for more details Table 27 STMicroelectronics Tool Features Po Emulation Type Programming Capability Software Included Device simulation limited MCU CD ROM with ST6 Starter Kit emulation as interrupts are Yes DIP packages only Rkit ST6 from Raisonance not supported ST6 Assembly toolchain In circuit powerful emula WGDB6 powerful Source Level ST6 HDS2 Emulator tion features including Debugger for Win 3 1 Win 95 trace logic analyzer and NT Various software demo ver ST6 EPROM sions Programmer Board Windows Programming Tools for Win 3 1 Win 95 and NT Table 28 Dedicated STMicroelectronics Development Tools Supported Products ST6 Starter Kit ST6 HDS2 Emulator ST6 Programming Boa
112. umber which is mapped at addresses OF9Bh OF9Fh The user must therefore leave these bytes blanked The identification number is structured as follows DE JE 09D OFER OF9Fh Test ID with TO T1 T2 T3 time in seconds since 01 01 1970 and Test ID Tester Identifier y ST6208C ST6209C ST6210C ST6220C TRANSFER OF CUSTOMER CODE Cont d ST6208C 09C 10C 20C P08C P09C P10C P20C MICROCONTROLLER OPTION LIST Customer Address Contact Phone Reference STMicroelectronics references ST6208C ST6209C ST6210C ST6220C ST62P08C ST62P09C ST62P10C ST62P20C Device 1K 4K 1 4 Package Dual in Line Plastic Small Outline Plastic with conditioning Shrink Small Outline Plastic with conditioning Conditioning option Standard Tube Tape amp Reel Temperature Range 0 C to 70 C 40 C to 85 C 40 C to 125 C Marking Standard marking Special marking ROM only PDIP20 10 char max 020 8 char max SSOP20 11 char max Authorized characters are letters digits and spaces only Oscillator Safeguard Enabled Disabled Watchdog Selection Software Activation Hardware Activation Timer pull up Enabled Disabled NMI pull up Enabled Disabled Oscillator Selection Quartz crystal Ceramic resonator RC network Readout Protection FASTROM Enabled Disabled ROM
113. vectors 3 and 4 Interrupt requests are flagged by a bit in their corresponding control register This means that a request cannot be lost because the flag bit must be cleared by user software 5 9 EXTERNAL INTERRUPTS I O Ports External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the GEN bit is set These interrupts allow the processor to exit from STOP mode The external interrupt polarity is selected through the IOR register External interrupts are linked to vectors 1 and 2 Interrupt requests on vector 1 can be configured either as edge or level sensitive using the LES bit in the IOR Register Interrupt requests from vector 2 are always edge sensitive The edge polarity can be configured us ing the ESB bit in the IOR Register In edge sensitive mode a latch is set when a edge occurs on the interrupt source line and is cleared when the associated interrupt routine is started So an interrupt request can be stored until com pletion of the currently executing interrupt routine before being processed If several interrupt re quests occurs before completion of the current in terrupt routine only the first request is stored Storing of interrupt requests is not possible in level sensitive mode To be taken into account the low level must be present on the interrupt pin when the MCU samples the line after instruction execution 5 9 1 Notes
114. vel are shifted into the next level down while the content of the PC is shifted into the first level the original contents of the sixth stack level are lost When a subroutine or interrupt return oc curs RET or RETI instructions the first level reg ister is shifted back into the PC and the value of each level is popped back into the previous level Figure 8 Stack manipulation PROGRAM COUNTER ON RETURN ON FROM LEVEL 1 INTERRUPT INTERRUPT OR OR LEVEL 2 SUBROUTINE CALL SUBROUTINE Since the accumulator in common with all other data space registers is not stored in this stack management of these registers should be per formed within the subroutine Caution The stack will remain in its deepest po sition if more than 6 nested calls or interrupts are executed and consequently the last return ad dress will be lost It will also remain in its highest position if the stack is empty and a RET or RETI is executed In this case the next instruction will be executed ky 5 CLOCKS SUPPLY AND RESET 5 1 CLOCK SYSTEM The main oscillator of the MCU can be driven by any of these clock sources external clock signal external AT cut parallel resonant crystal external ceramic resonator external RC network Ryner In addition an on chip Low Frequency Auxiliary Oscillator LFAO is available as a back up clock system or to reduce power consumption An optional Oscillator Safeguard
115. via the Data Direction Option and Data registers refer to I O ports description for additional information Caution Only one I O line must be configured as an analog input at any time The user must avoid any situation in which more than one I O pin is se lected as an analog input simultaneously because they will be shorted internally ST6208C ST6209C ST6210C ST6220C 8 3 3 4 Software Procedure Refer to the Control register ADCR and Data reg ister ADR in Section 8 3 7 for the bit definitions Analog Input Configuration The analog input must be configured through the Port Control registers DDRx ORx and DRx Re fer to the I O port chapter ADC Configuration In the ADCR register Reset the PDS bit to power on the ADC This bit must be set at least one instruction before the beginning of the conversion to allow stabilisation of the A D converter Set the EAI bit to enable the ADC interrupt if needed ADC Conversion In the ADCR register Set the STA bit to start a conversion This auto matically clears resets to 0 the End Of Con version Bit EOC When a conversion is complete The EOC bit is set by hardware to flag that con version is complete and that the data in the ADC data conversion register is valid An interrupt is generated if the EAI bit was set Setting the STA bit will start a new count and will clear the EOC bit thus clearing the interrupt con dition
116. worst case conditions is calculat ed using the following formula 6 5us 9 x Cag X ASI capacitor charged to over 99 9 i e 30 KQ in cluding a 50 guardband The ASI can be higher if Cag has been charged for a longer period by adding instructions before the start of conversion adding more than 26 CPU cy cles is pointless 3 Since the ADC is on the same chip as the micro processor the user should not switch heavily load ed output signals during conversion if high preci sion is required Such switching will affect the sup ply voltages used as analog references 4 Conversion accuracy depends on the quality of the power supplies Vpp and Vss The user must take special care to ensure a well regulated refer ence voltage is present on the Vpp and Vgg pins power supply voltage variations must be less than 0 1V ms This implies in particular that a suitable decoupling capacitor is used at the Vpp pin The converter resolution is given by Vpp Yss 256 The Input voltage Ain which is to be converted must be constant for 1us before conversion and remain constant during conversion 5 Conversion resolution can be improved if the power supply voltage Vpp to the microcontroller is lowered 6 In order to optimize the conversion resolution the user can configure the microcontroller in WAIT mode because this mode minimises noise distur 54 104 bances and power supply variations due to output switching Never
117. y and Temperature for OTP devices with option bytes not programmed IDD uA IDD uA 700 8MHz AC 1M 8MHz AC 1MHz A 4MHz Y 32KHz gt 4MHz Y 32KHz pe 2MHz Ly E 2MHz VDD V Figure 45 Typical Ipp in WAIT vs fcpy and Temperature for OTP devices with option bytes programmed to 00H IDD A IDD pA 120 8MHz A 1M 8MHz AC 1MHz A 4MHz Y 32KHz A 4MHz Y 32KHz ee VDD V 68 104 ST6208C ST6209C ST6210C ST6220C SUPPLY CURRENT CHARACTERISTICS Cont d Figure 46 Typical Ipp in WAIT vs fcpy and Temperature for ROM devices IDD pA IDD pA 8MHz X 1MHz A 4MHz Y 32KHz VDD V 69 104 ST6208C ST6209C ST6210C ST6220C SUPPLY CURRENT CHARACTERISTICS Cont d 10 4 3 STOP Mode 10 TP i 2 0 4 see igure amp igure 8 R i M vi 1 Typical data are based on Vpp 5 0V at Ta 25 C 2 All I O pins in input with pull up mode no load all peripherals in reset state OSG and LVD disabled option bytes programmed to 00H Data based on characterization results tested in production at Vpp max and fcpy max 3 Maximum STOP consumption for 40 C lt Ta lt 90 C 4 Maximum STOP consumption for 40 C lt Ta lt 125 C Figure 47 Typical Ipp in STOP vs Temperature Figure 48 Typical Ipp in STOP vs Temperature for OTP devices for ROM devices IDD nA IDD nA 1200 Ta 40 0 4 Ta 95 C Ta 400 Ta 95 C A Ao Ta 25 C WE Ta 125 C 1500 Ta 25 C 4

ST ST6208C ST6209C ST6210C ST6220C handbook

Contents

Download Pdf Manuals

Related Search

Related Contents