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ST M95320-W M95320-R M95320-DR 32-Kbit serial SPI bus EEPROM with high-speed clock handbook

1. Table 21 TSSOPS 8 lead thin shrink small outline package mechanical data millimeters inches Symbol Typ Min Max Typ Min Max A 1 200 0 0472 A1 0 050 0 150 0 0020 0 0059 A2 1 000 0 800 1 050 0 0394 0 0315 0 0413 b 0 190 0 300 0 0075 0 0118 C 0 090 0 200 0 0035 0 0079 CP 0 100 0 0039 D 3 000 2 900 3 100 0 1181 0 1142 0 1220 0 650 0 0256 E 6 400 6 200 6 600 0 2520 0 2441 0 2598 E1 4 400 4 300 4 500 0 1732 0 1693 0 1772 L 0 600 0 450 0 750 0 0236 0 0177 0 0295 L1 1 000 0 0394 a 0 8 0 8 N 8 8 1 Values in inches are converted from mm and rounded to four decimal digits Doc ID 5711 Rev 14 q M95320 W M95320 R M95320 DR Part numbering 11 Part numbering Table 22 Ordering information scheme Example Device type M95320 M95 SPI serial access EEPROM Device function 320 32 Kbit 4096 x 8 320 D 32 Kbit plus Identification page Operating voltage W MN 6 T W Vcc 2 5 to5 5V R Vec 1 8 to 5 5 V Package MN SO8 150 mil width DW TSSOP8 169 mil width MB or MC MLP8 2 x 3 mm Device grade 6 Industrial temperature range 40 to 85 C Device tested with standard test flow Option blank Standard packing T Tape and reel packing Plating technology P G or P RoHS compliant and halogen free ECOPACK Process P P or K Manufacturing technology cod
2. Symbol Parameter Min Max Unit C Load capacitance 30 pF Input rise and fall times 25 ns Input pulse voltages 0 2 Voc to 0 8 Voc V Input and output timing reference voltages 0 3 Voc to 0 7 Voc Figure 18 AC measurement I O waveform Input voltage levels Input and output timing reference levels 0 8 Vcc 0 2 Vcc Al00825C Doc ID 5711 Rev 14 ky M95320 W M95320 R M95320 DR DC and AC parameters Table 12 Capacitance Symbol Parameter Test conditions Min Max Unit Cour Output capacitance Q Vout 20V 8 pF Input capacitance D Vin 20V 8 pF Cin Input capacitance other pins Vi 20V 6 pF 1 Sampled only not 100 tested at T4 25 C and a frequency of 5 MHz Table 13 Cycling performance by groups of four bytes Symbol Parameter Test conditions Min Max Unit Write cycle TA S25 C 1 8 V lt Vcc lt 5 5 V 4 000 000 write Nevele endurance Z 85 cycle TA 85 C 1 8 V lt Voc lt 5 5 V 1 200 000 y 1 Cycling performance for products identified by process letter K 2 The Write cycle endurance is defined for groups of four data bytes located at addresses 4 N 4 N 1 4 N 2 4 N 3 where N is an integer The Write cycle endurance is defined by characterization and qualification 3 A Write cycle is executed when either a Page Write a Byte Write a WRSR a WRID or an LID instruction is decoded Wh
3. Section 6 10 Lock ID Figure 16 Read Lock Status sequence Figure 17 Lock ID sequence Updated Features Section 1 Description Section 6 4 Write Status Register WRSR Section 6 6 Write to Memory Array WRITE Table 8 Absolute maximum ratings Table 40 UFDFPN8 MLP8 8 lead ultra thin fine pitch dual flat package no lead 2 x 3 mm data All tables in Section 9 DC and AC parameters Section 11 Part numbering Figure 27 UFDFPN8 MLP8 8 lead ultra thin fine pitch dual flat no lead package outline Doc ID 5711 Rev 14 ky M95320 W M95320 R M95320 DR Revision history Table 23 Document revision history continued Date Revision Changes Datasheet split into 29 May 2012 14 M95320 W M95320 R M95320 DR this datasheet for standard products range 6 M95320 125 datasheet for automotive products range 3 Doc ID 5711 Rev 14 47 48 M95320 W M95320 R M95320 DR Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use o
4. Small text changes 23 Jun 2008 10 Section 4 1 Supply voltage Vcc updated Table 19 DC characteristics M95640 DF device grade 6 modified Figure 23 Serial input timing Figure 20 Hold timing and Figure 21 Serial output timing modified 17 Feb 2009 11 Section 4 1 Supply voltage Voc and Section 6 4 Write Status Register WRSR updated Note added to Section 6 6 Write to Memory Array WRITE Section 7 2 Initial delivery state specified Note modified in Table 14 Capacitance lcc at 10 MHz added to Table 16 DC characteristics M95080 device grade 3 Vres parameter added to DC characteristics tables 16 16 17 and 19 Note added to tc ay in AC characteristics tables 26 32 29 and 21 Note added to Table 20 AC characteristics M95320 R and Table 21 AC characteristics M95640 R Process letter modified in Table 45 Ordering information scheme 07 Dec 2009 12 64 Kbit densities removed from datasheet ECOPACK status of packages specified in Features and in Table 45 Ordering information scheme lo and lop added to Table 8 Absolute maximum ratings Note 2 added below Figure 27 UFDFPN8 MLP8 8 lead ultra thin fine pitch dual flat no lead package outline Small text changes 13 May 2011 13 Added part number M95320 DR and related explanations Table 4 M95320 DR instruction set Section 6 7 Read Identification Page Section 6 9 Read Lock Status
5. 17 M95320 W M95320 R M95320 DR 32 Kbit serial SPI bus EEPROM with high speed clock Features Compatible with the Serial Peripheral Interface SPI bus Memory array 32 Kb 4 Kbytes of EEPROM Page size 32 bytes Write Byte Write within 5 ms Page Write within 5 ms Additional Write lockable page Identification page Write Protect quarter half or whole memory array m High speed clock 20 MHz May 2012 Single supply voltage 2 5V to 5 5 V for M95320 W 1 8 V to 5 5 V for M95320 R and M95320 DR Operating temperature range from 40 C up to 85 C Enhanced ESD protection More than 4 million Write cycles More than 200 year data retention Packages RoHS compliant and halogen free ECOPACK Datasheet production data SO8 MN 150 mil width TSSOP8 DW 169 mil width s UFDFPN8 MB MC 2 x 3 mm MLP Doc ID 5711 Rev 14 1 48 This is information on a product in full production www st com Contents M95320 W M95320 R M95320 DR Contents 1 Description Wc a alas RA 6 2 Memory organization eeeeeee n n n nn 8 3 Signal description sos cece anas n RR Ann RER RR ER eens eee 9 3 1 Serial Data Output Q isses RR rA ER ERRERREER ES 9 3 2 Serial Data Input D 322945 sss AR ERE midea daia EAR o dd 9 3 3 Seal Clock C uicceoutetacia dd ideae pO eode Edd eod oes 9 84 Chip Select B i end epacsios OR
6. 2 5 V and lop 0 4 mA or Vou Output high voltage Voc 5 V and lop 2 mA 0 8 Voc V 2 Internal reset 4 5 VRES threshold voltage s 169 Y Or mc Nm oc Only for the device identified by process letter K Characterized only not tested in production 2 pA with the device identified by process letter K 0 7 V with the device identified by process letter K 1 3 V with the device identified by process letter K Doc ID 5711 Rev 14 4 M95320 W M95320 R M95320 DR DC and AC parameters Table 16 DC characteristics M95320 R M95320 DR device grade 6 Symbol Parameter Test conditions Min Max Unit Input leakage li ms Vin Vss Or Vcc 2 uA ILo Haput Ieakags S Vcc voltage applied on Q Vgs or Voc 2 UA current Vec 1 8 V max clock frequency fc 2 Supply current C 0 1V c 0 9Vcc Q open lcc Read mA Read Voc 1 8 V fc 5 MHz 2 C 0 1Vcc 0 9Vcc Q open Supply current lcco Write Voc 21 8 V during tw S Voc 5 mA Supply current lcc1 Standby Voc 1 8 V S Voc Vin Vss or Voc 1 pA ViL Input low voltage 1 8 V Voc lt 2 5 V 0 45 0 25 Voc V Vin Input high voltage 1 8 V Vcc 2 5 V 0 75 Voc Voct1 V VoL Output low voltage loj 0 15 mA Voc 1 8 V 0 3 V VoH Output high voltage lo 2 0 1 mA Vcc 1 8 V 0 8 Vcc V 8 _ Internal reset 4 5 VRES threshold voltage 10 Ten Y 1 If the application uses the
7. 5 5 1 5 1 2 Operating features Supply voltage Vcc Operating supply voltage Vcc Prior to selecting the memory and issuing instructions to it a valid and stable Vcc voltage within the specified Vcc min Vcc max range must be applied see Operating conditions in Section 9 DC and AC parameters This voltage must remain stable and valid until the end of the transmission of the instruction and for a Write instruction until the completion of the internal write cycle ty In order to secure a stable DC supply voltage it is recommended to decouple the Vcc line with a suitable capacitor usually of the order of 10 nF to 100 nF close to the Vcc Vss device pins Device reset In order to prevent erroneous instruction decoding and inadvertent Write operations during power up a power on reset POR circuit is included At power up the device does not respond to any instruction until VCC reaches the POR threshold voltage This threshold is lower than the minimum Vcc operating voltage see Operating conditions in Section 9 DC and AC parameters At power up when Vcc passes over the POR threshold the device is reset and is in the following state e in Standby Power mode e deselected e Status Register values The Write Enable Latch WEL bit is reset to 0 The Write In Progress WIP bit is reset to O The SRWD BP1 and BPO bits remain unchanged non volatile bits It is important to note that the device must not
8. It receives instructions addresses and the data to be written Values are latched on the rising edge of Serial Clock C Serial Clock C This input signal provides the timing of the serial interface Instructions addresses or data present at Serial Data Input D are latched on the rising edge of Serial Clock C Data on Serial Data Output Q change from the falling edge of Serial Clock C Chip Select S When this input signal is high the device is deselected and Serial Data Output Q is at high impedance The device is in the Standby Power mode unless an internal Write cycle is in progress Driving Chip Select S low selects the device placing it in the Active Power mode After power up a falling edge on Chip Select S is required prior to the start of any instruction Hold HOLD The Hold HOLD signal is used to pause any serial communications with the device without deselecting the device During the Hold condition the Serial Data Output Q is high impedance and Serial Data Input D and Serial Clock C are Don t Care To start the Hold condition the device must be selected with Chip Select S driven low Doc ID 5711 Rev 14 9 48 Signal description M95320 W M95320 R M95320 DR 3 6 3 7 3 8 10 48 Write Protect W The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions as specified by the values in the BP1 and
9. Serial input timing 0 2 0 0 teeta 38 MOMIN pP Rewind Weed Seren EE EREE G EEDE EEI Bees 38 Serial output timing aaaea aaea 39 SO8N 8 lead plastic small outline 150 mils body width package outline 40 UFDFPNS MLP8 8 lead ultra thin fine pitch dual flat no lead package on c Dm 41 TSSOPS 8 lead thin shrink small outline package outline llis 42 Doc ID 5711 Rev 14 5 48 Description M95320 W M95320 R M95320 DR 1 Description The M95320 devices are Electrically Erasable PROgrammable Memories EEPROMs organized as 4096 x 8 bits accessed through the SPI bus The M95320 devices can operate with a supply range from 1 8 V up to 5 5 V and are guaranteed over the 40 C 85 C temperature range The M95320 D offers an additional page named the Identification Page 32 bytes The Identification Page can be used to store sensitive application parameters which can be later permanently locked in Read only mode Figure 1 Logic diagram Voce D Q C S q M95xxx W q HOLD q Vss Al01789C The SPI bus signals are C D and Q as shown in Figure 1 and Table 1 The device is selected when Chip Select S is driven low Communications with the device can be interrupted when the HOLD is driven low Table 1 Signal names Signal name Function Direction C Serial Clock Input D Serial Data Input Input Q Serial Data Output Output S Chip Select Input W Write Prot
10. b In the specific case where the device has shifted in a Write command Inst Address data bytes each data byte being exactly 8 bits deselecting the device also triggers the Write cycle of this decoded command Doc ID 5711 Rev 14 ky M95320 W M95320 R M95320 DR Operating features 5 4 5 5 The Hold condition ends when the Hold HOLD signal is driven high when Serial Clock C is already low Figure 6 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock C being low Status Register The Status Register contains a number of status and control bits that can be read or set as appropriate by specific instructions See Section 6 3 Read Status Register RDSR for a detailed description of the Status Register bits Data protection and protocol control The device features the following data protection mechanisms e Before accepting the execution of the Write and Write Status Register instructions the device checks whether the number of clock pulses comprised in the instructions is a multiple of eight e Allinstructions that modify data must be preceded by a Write Enable WREN instruction to set the Write Enable Latch WEL bit e The Block Protect BP1 BPO bits in the Status Register are used to configure part of the memory as read only e The Write Protect W signal is used to protect the Block Protect BP1 BPO bits in the Status Register For any instruction
11. Eat y E RE Ra en OR qb E 9 3 5 Bed ddobD ss es Apes cates RE pEEE EACUS DC AR EE AS 9 3 6 White Protect W nnana aaa exor Xn t3 Pete ep UP Ee ones 10 3 7 Voo Supply voltage ias ace e ea Cac cie o dee e ae 8 10 SK Mee ground sse aox ane kie re RO UR Secu Geet Seeded yee aee be f 10 4 Connecting to the SPI bus Leeesseleeessse 11 4 1 suus CP mmm 12 5 Operating features i iius re Lea ox ai RO ca Ro Ra ed RC RC 13 5 1 Supply voltage Voe iz2smac3 kd e eevee eek Eo ER RR ade Rd dc 13 5 1 1 Operating supply voltage Voc isis 18 5 1 2 Device reset 2 soletis iR sete aver I Re RA Ex YR ed ee ved 13 5 1 3 Power up conditions sseeeeee eh 13 5 1 4 Power down ssslleeleeele hr eee 14 5 2 Active Power and Standby Power modes 000 0 ee eeee 14 5 8 Hold condition PT 14 54 Status Register og anaa 15 5 5 Data protection and protocol control llle 15 6 INSTUCHONS siaceddnbadacuetsssacn Geeseesadbene cea taaa Enn 16 6 1 Write Enable WREN 2c4 lt c20tec4sicegeteteeidgedcsdiscdediads 17 62 Write Disable WADI 22221304 vicengece Se eeu ERR RE RA Ea EE eda 18 6 3 Read Status Register RDSR 0 02 cee eee 19 6 3 1 WIP DIE sie tiaau 4 aha eke ae ee ee eae be be eh Pe EE oo 19 2 48 Doc ID 5711 Rev 14 ky M95320 W M95320 R M95320 DR Contents 11 12 6 3 2 WELDE 22c4 0 eR rereset terden ro eyer ee Same ade Kp 19 6 3 3 BP1 BPO DIS coss d RE ere
12. M95320 R device at 2 5 V Vcc 5 5 V and 40 C lt T a lt 85 C please refer to Table 15 DC characteristics M95320 W device grade 6 rather than to the above table 2 Forthe device identified by process letter K 3 Characterized only not tested in production 4 0 7 V with the device identified by process letter K 5 1 3V with the device identified by process letter K y Doc ID 5711 Rev 14 35 48 DC and AC parameters M95320 W M95320 R M95320 DR Table 17 AC characteristics M95320 W device grade 6 Test conditions specified in Table 10 and Table 11 Min Max Min Max Symbol Alt Parameter New products Unit Vcc 22 5 to 5 5 V Veo 4 5 to 5 5 V fc fsck Clock frequency D C 10 D C 20 MHz tsicH tessi S active setup time 30 15 ns isucH tess2 S not active setup time 30 15 ns tsHsL tcs S deselect time 40 20 ns tcHsH tcsy_ S active hold time 30 15 ns tcHsL S not active hold time 30 15 ns toy tei Clock high time 42 20 ns to teL Clock low time 40 20 ns tecu tac Clock rise time 2 2 us tcuci tre Clock fall time 2 2 us tpvcH tosu Data in setup time 10 5 ns tcupx tp Data in hold time 10 10 ns tHHCH Clock low hold time after HOLD not active 30 15 ns tu cH Clock low hold time after HOLD active 30 15 ns cLHL Clock low set up time before HOLD active 0 0 ns cLHH Clock low set up time before HOLD not active 0 0 ns teuoz tpig
13. Output disable time 40 20 ns tci ov ty Clock low to output valid 40 20 ns tci ox tho Output hold time 0 0 ns taroh tro Output rise time 40 20 ns tahal tro Output fall time 40 20 ns tHHav tz HOLD high to output valid 40 20 ns tuiaz tyz HOLD low to output high Z 40 20 ns tw twc Write time 5 5 ms 1 toy tg must never be lower than the shortest possible clock period 1 fc max Characterized only not tested in production tci ay must be compatible with tc clock low time if the SPI bus master offers a Read setup time tsu 0 ns te can be equal to or greater than tc gy in all other cases tc must be equal to or greater than teLav tsu 36 48 Doc ID 5711 Rev 14 q M95320 W M95320 R M95320 DR DC and AC parameters Table 18 AC characteristics M95320 R M95320 DR device grade 6 Test conditions specified in Table 10 and Table 1100 Symbol Alt Parameter Min Max Unit fc fsck Clock frequency D C 5 MHz tsicH tcss1 S active setup time 60 ns tsHcH tesge S not active setup time 60 ns tsHs__ tcs S deselect time 90 ns icusH tes S active hold time 60 ns tcHsL S not active hold time 60 ns tcu tory Clock high time 90 ns to tel Clock low time 90 ns tci cu tac Clock rise time 2 us tcuci 9 tro Clock fall time 2 us tpvcH tpsu Data in setup time 20
14. Serial Data Input D Address bit A10 must be 0 upper address bits are Don t Care and the data byte pointed to by the lower address bits A4 A0 is shifted out on Serial Data Output Q If Chip Select S continues to be driven low the internal address register is automatically incremented and the byte of data at the new address is shifted out The number of bytes to read in the ID page must not exceed the page boundary otherwise unexpected data is read e g when reading the ID page from location 10d the number of bytes should be less than or equal to 22d as the ID page boundary is 32 bytes The read cycle is terminated by driving Chip Select S high The rising edge of the Chip Select S signal can occur at any time during the cycle The first byte addressed can be any byte within any page The instruction is not accepted and is not executed if a write cycle is currently in progress Figure 14 Read Identification Page sequence 26 48 High impedance Ai15966 Doc ID 5711 Rev 14 ky M95320 W M95320 R M95320 DR Instructions 6 8 Write Identification Page available only in M95320 DR devices The Identification Page 32 bytes is an additional page which can be written and later permanently locked in Read only mode Writing this page is achieved with the Write Identification Page instruction see Table 4 The Chip Select signal S is first driven low The bits of the instruction byte address b
15. address counter rolls over to the beginning of the page and the previous data there are overwritten with the incoming data The page size of these devices is 32 bytes Doc ID 5711 Rev 14 23 48 Instructions M95320 W M95320 R M95320 DR The instruction is not accepted and is not executed under the following conditions e ifthe Write Enable Latch WEL bit has not been set to 1 by executing a Write Enable instruction just before e if a Write cycle is already in progress e ifthe device has not been deselected by driving high Chip Select S at a byte boundary after the eighth bit bO of the last data byte that has been latched in e ifthe addressed page is in the region protected by the Block Protect BP1 and BPO bits Note The self timed write cycle ty is internally executed as a sequence of two consecutive events Erase addressed byte s followed by Program addressed byte s An erased bit is read as 0 and a programmed bit is read as 1 Figure 13 Page Write WRITE sequence SON e 012 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 16 Bit Address Data Byte 1 ol Al01796D 1 Depending on the memory size as shown in Table 5 the most significant address bits are Don t Care 24 48 Doc ID 5711 Rev 14 ky M95320 W M95320 R M95320 DR Instructions 6 6 1 Cycling with Error Correction Code ECC M95320 D devices offer an Error Correction Code ECC
16. be accessed until Vcc reaches a valid and stable level within the specified Vcc min Vec max range as defined under Operating conditions in Section 9 DC and AC parameters Power up conditions When the power supply is turned on Vcc rises continuously from Vss to Vcc During this time the Chip Select S line is not allowed to float but should follow the Vgc voltage It is therefore recommended to connect the S line to Vcc via a suitable pull up resistor see Figure 4 In addition the Chip Select S input offers a built in safety feature as the S input is edge sensitive as well as level sensitive after power up the device does not become selected until a falling edge has first been detected on Chip Select S This ensures that Chip Select S must have been high prior to going low to start the first operation The Vcc voltage has to rise continuously from 0 V up to the minimum Voc operating voltage defined under Operating conditions in Section 9 DC and AC parameters and the rise time must not vary faster than 1 V us Doc ID 5711 Rev 14 13 48 Operating features M95320 W M95320 R M95320 DR 5 1 4 5 2 5 3 14 48 Power down During power down continuous decrease of the Vcc supply voltage below the minimum Vcc operating voltage defined under Operating conditions in Section 9 DC and AC parameters the device must be e deselected Chip Select S should be allowed to follow the voltage applied on Vcc e
17. pull up resistor R represented in Figure 4 ensures that a device is not selected if the Bus Master leaves the S line in the high impedance state In applications where the Bus Master may leave all SPI bus lines in high impedance at the same time for example if the Bus Master is reset during the transmission of an instruction the clock line C must be connected to an external pull down resistor so that if all inputs outputs become high impedance the C line is pulled low while the S line is pulled high this ensures that S and C do not become high at the same time and so that the tsucH requirement is met The typical value of R is 100 kQ Doc ID 5711 Rev 14 11 48 Connecting to the SPI bus M95320 W M95320 R M95320 DR 4 1 12 48 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the following two modes e CPOL 0 CPHA 0 e CPOL 1 CPHA 1 For these two modes input data is latched in on the rising edge of Serial Clock C and output data is available from the falling edge of Serial Clock C The difference between the two modes as shown in Figure 5 is the clock polarity when the bus master is in Stand by mode and not transferring data e Cremains at 0 for CPOL 0 CPHA 0 e Cremains at 1 for CPOL 1 CPHA 1 Figure 5 SPI modes supported CPOL CPHA Al01438B Doc ID 5711 Rev 14 ky M95320 W M95320 R M95320 DR Operating features
18. to be accepted and executed Chip Select S must be driven high after the rising edge of Serial Clock C for the last bit of the instruction and before the next rising edge of Serial Clock C Two points should be noted in the previous sentence e The last bit of the instruction can be the eighth bit of the instruction code or the eighth bit of a data byte depending on the instruction except for Read Status Register RDSR and Read READ instructions e The next rising edge of Serial Clock C might or might not be the next bus transaction for some other device on the SPI bus Table 2 Write protected block size Status Register bits Protected block Protected array addresses BP1 BPO 0 0 none none 0 1 Upper quarter 0COOh OFFFh 1 0 Upper half 0800h OFFFh 1 1 Whole memory 0000h OFFFh Doc ID 5711 Rev 14 15 48 Instructions M95320 W M95320 R M95320 DR 6 Instructions Each instruction starts with a single byte code as summarized in Table 3 If an invalid instruction is sent one not contained in Table 3 the device automatically deselects itself Table 3 Instruction set Instruction Description Instruction format WREN Write Enable 0000 0110 WRDI Write Disable 0000 0100 RDSR Read Status Register 0000 0101 WRSR Write Status Register 0000 0001 READ Read from Memory Array 0000 0011 WRITE W
19. 4 25 26 27 28 29 30 31 Oo 16 bit address Data byte e 3 High impedance Ai15967 Doc ID 5711 Rev 14 29 48 Power up and delivery state M95320 W M95320 R M95320 DR 7 7 1 7 2 30 48 Power up and delivery state Power up state After power up the device is in the following state Standby power mode deselected after power up a falling edge is required on Chip Select S before any instructions can be started not in the Hold condition the Write Enable Latch WEL is reset to 0 Write In Progress WIP is reset to 0 The SRWD BP1 and BPO bits of the Status Register are unchanged from the previous power down they are non volatile bits Initial delivery state The device is delivered with the memory array set to all 1s each byte FFh The Status Register Write Disable SRWD and Block Protect BP1 and BPO bits are initialized to O Doc ID 5711 Rev 14 ky M95320 W M95320 R M95320 DR Maximum rating 8 4 Maximum rating Stressing the device outside the ratings listed in Table 8 may cause permanent damage to the device These are stress ratings only and operation of the device at these or any other conditions outside those indicated in the operating sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Table 8 Absolute maximum ratin
20. A1 ZW MEe Drawing is not to scale 2 The central pad the area E2 by D2 in the above illustration is internally pulled to Vas It must not be connected to any other voltage or signal line on the PCB for example during the soldering process Table 20 UFDFPN8 MLP8 8 lead ultra thin fine pitch dual flat package no lead 2x3mm data millimeters inches Symbol Typ Min Max Typ Min Max A 0 550 0 450 0 600 0 0217 0 0177 0 0236 A1 0 020 0 000 0 050 0 0008 0 0000 0 0020 b 0 250 0 200 0 300 0 0098 0 0079 0 0118 D 2 000 1 900 2 100 0 0787 0 0748 0 0827 D2 rev MB 1 600 1 500 1 700 0 0630 0 0591 0 0669 D2 rev MC 1 200 1 600 0 0472 0 0630 E 3 000 2 900 3 100 0 1181 0 1142 0 1220 E2 rev MB 0 200 0 100 0 300 0 0079 0 0039 0 0118 E2 rev MC 1 200 1 600 0 0472 0 0630 e 0 500 0 0197 K rev MB 0 800 0 0315 K rev MC 0 300 0 0118 L 0 300 0 500 0 0118 0 0197 L1 0 150 0 0059 L3 0 300 0 0118 eee 0 080 0 0031 1 Values in inches are converted from mm and rounded to four decimal digits 2 Applied for exposed die paddle and terminals Exclude embedding part of exposed die paddle from measuring Doc ID 5711 Rev 14 41 48 Package mechanical data M95320 W M95320 R M95320 DR 42 48 Figure 24 TSSOPS 8 lead thin shrink small outline package outline D CP TSSOP8AM 1 Drawing is not to scale
21. AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2012 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 48 48 Doc ID 5711 Rev 14 ki
22. BPO bits of the Status Register This pin must be driven either high or low and must be stable during all Write instructions Vcc supply voltage Voc is the supply voltage Vss ground Vss is the reference for all signals including the Vcc supply voltage Doc ID 5711 Rev 14 ky M95320 W M95320 R M95320 DR Connecting to the SPI bus 4 Connecting to the SPI bus All instructions addresses and input data bytes are shifted in to the device most significant bit first The Serial Data Input D is sampled on the first rising edge of the Serial Clock C after Chip Select S goes low All output data bytes are shifted out of the device most significant bit first The Serial Data Output Q is latched on the first falling edge of the Serial Clock C after the instruction such as the Read from Memory Array and Read Status Register instructions have been clocked into the device Figure 4 Bus master and memory devices on the SPI bus CPOL CPHA 0 0 or 1 1 SPI Bus Master SPI Memory SPI Memory SPI Memory Device Device Device CS3 CS2 C Al12836b 1 The Write Protect W and Hold HOLD signals should be driven high or low as appropriate Figure 4 shows an example of three memory devices connected to an SPI bus master Only one memory device is selected at a time so only one memory device drives the Serial Data Output Q line at a time The other memory devices are high impedance The
23. Changes Document converted to new ST template Packages are ECOPACK compliant PDIP package removed SO8N package specifications updated see Table 23 and Figure 22 M95640 S and M95320 S part numbers removed DC and AC parameters updated accordingly How to identify previous current and new products by the Process identification letter Table removed Figure 9 SPI modes supported updated and Note 2 added First three paragraphs of Section 4 Operating features replaced by Section 4 1 Supply voltage Vcc Ta added to Table 8 Absolute maximum ratings loc and I 1 updated in Table 13 Table 16 Table 16 and Table 19 Vo and Vo updated in Table 16 loc updated in Table 17 Data in Table 19 is no longer preliminary tcp updated in Table 32 Table 21 AC characteristics M95640 R added Timing line of tsyqz modified in Figure 21 Serial output timing Process letter added to Table 45 Ordering information scheme Note 2 removed Note 2 removed from Figure 2 09 Oct 2007 JEDEC standard revision updated to D in Note 1 below Table 8 Absolute maximum ratings Note 2 removed below Figure 8 and explanatory paragraph added Section 4 1 Supply voltage Vcc updated Table 5 Address range bits corrected Products operating at Vcc 4 5 V to 5 5 V are no longer available in the device grade 6 T4 temperature range Icc and lcc4 parameters modified in Table 16 DC characteristics M95320 W device grade 6 Maximum frequency
24. ERROR a ee DER ERR we 19 6 3 4 SBWD Dit ebbe ex ERE E RR ARX ED ER U RES 20 6 4 Write Status Register WRSR 02000 e eee eee 20 6 5 Read from Memory Array READ 0 000 e eee eee 22 6 6 Write to Memory Array WRITE anaana annae 23 6 6 1 Cycling with Error Correction Code ECC 000e ae ee 25 6 7 Read Identification Page available only in M95320 DR devices 26 6 8 Write Identification Page available only in M95320 DR devices 27 6 9 Read Lock Status available only in M95320 DR devices 28 6 10 Lock ID available only in M95320 DR devices 05 29 Power up and delivery state 2 0c eee eee 30 7 1 POWSIUP State 2 ssa di thee ep ches Exeter dad at 30 7 2 Initial delivery state 2 0 0 00 ee 30 Maximum rating uuu sarda i RR ROB OR eee eee een eee ee 31 DC and AC parameters 00 ce eee ees 32 Package mechanical data Lleeee 40 Part numbering 6 6 cnese as di RR RR need ee ee Re 43 REVISION history iiuacacoexsc a Suan es R RCACRCRCRCR eee wee m he ea pane es 44 Doc ID 5711 Rev 14 3 48 List of tables M95320 W M95320 R M95320 DR List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 4 48 Si
25. e 1 The process letters appear on the device package marking and on the shipment box Please contact your nearest ST Sales Office Doc ID 5711 Rev 14 43 48 Revision history M95320 W M95320 R M95320 DR 12 44 48 Revision history Table 23 Document revision history Date 13 Jul 2000 Revision 1 2 Changes Human Body Model meets JEDEC std Table 2 Minor adjustments on pp 1 11 15 New clause on p7 Addition of TSSOP8 package on pp 1 2 Ordering Info Mechanical Data 16 Mar 2001 1 3 Test condition added l and l o and specification of tp py and tpypL removed tci cp tcucL tpr pa and tpypL changed to 50ns for the V range V Voltage range changed to 2 7V to 3 6V throughout Maximum lead soldering time and temperature conditions updated Instruction sequence illustrations updated Bus Master and Memory Devices on the SPI bus illustration updated Package Mechanical data updated 19 Jul 2001 1 4 M95160 and M95080 devices removed to their own data sheet 06 Dec 2001 18 Dec 2001 1 5 2 0 Endurance increased to 1M write erase cycles Instruction sequence illustrations updated Document reformatted using the new template No parameters changed 08 Feb 2002 2 1 Announcement made of planned upgrade to 10MHz clock for the 5V 40 to 85 C range Endurance set to 100K write erase cycles 18 Dec 2002 2 2 10MHz 5MHz 2MHz cl
26. ect Input HOLD Hold Input Voc Supply voltage Vss Ground 6 48 Doc ID 5711 Rev 14 ki M95320 W M95320 R M95320 DR Description Figure 2 8 pin package connections top view M95xxx Al01790D 1 See Section 10 Package mechanical data section for package dimensions and how to identify pin 1 Doc ID 5711 Rev 14 7 48 Memory organization M95320 W M95320 R M95320 DR 2 8 48 Memory organization The memory is organized as shown in the following figure Figure 3 Block diagram High voltage Control logic generator o aa OU Address register Data and counter register Size of the S Read only o EEPROM area o gt Identification page MS19733V1 Doc ID 5711 Rev 14 q M95320 W M95320 R M95320 DR Signal description 3 3 1 3 2 3 3 3 4 3 5 Signal description During all operations Vcc must be held stable and within the specified valid range Vcc min to Vcc max All of the input and output signals must be held high or low according to voltages of Vip Vou Vit or VoL as specified in Section 9 DC and AC parameters These signals are described next Serial Data Output Q This output signal is used to transfer data serially out of the device Data is shifted out on the falling edge of Serial Clock C Serial Data Input D This input signal is used to transfer data serially into the device
27. en using the Byte Write the Page Write or the WRID instruction refer also to Section 6 6 1 Cycling with Error Correction Code ECC Table 14 Memory cell data retention Parameter Test conditions Min Unit Data retention TA 55 C 200 Year 1 For products identified by process letter K The data retention behavior is checked in production The 200 year limit is defined from characterization and qualification results Doc ID 5711 Rev 14 33 48 DC and AC parameters M95320 W M95320 R M95320 DR 34 48 Table 15 DC characteristics M95320 W device grade 6 Symbol Parameter Test conditions Min Max Unit Input leakage li pie i Vin Vss OF Vcc 2 pA Output leakage z ILo nan d S Vcc Vout Vss 0r Vcc 2 pA Vec 2 5 V fc 5 MHz 3 C 0 1 Voc 0 9 Voc Q open Voc 2 5 V fc 10 MHz 2 1 i Supply current C 0 1 Vcc 0 9 Vcc Q open AR CC Read Voc 3 0 V fC 10 MHz 4 C 0 1 Voc 0 9 Voc Q open Voc 5 5 V fo 20 MHz 5 1 C 0 1 Voc 0 9 Voc Q open loco wa current During tw 8 Voc 2 5 V lt Vee lt 5 5 V 5 mA S Vcc Vec 5 5 V a0 Vin Vss Or Vcc Supply current S Vec Vec 5 0 V CC YCC A cet Standby Vin Vss or Voc n S Voc Vec 25 V 4 3 Vin Vss Or Vcc ViL Input low voltage 0 45 0 3Vcc V Vin Input high voltage 0 7 Voc Vect Voi Output low voltage lo 1 5 mA Vcc 2 5 V 0 4 V Voc
28. ence SN o 0123456 7 C Instruction D High Impedance Q AI02281E Doc ID 5711 Rev 14 17 48 Instructions M95320 W M95320 R M95320 DR 6 2 18 48 Write Disable WRDI One way of resetting the Write Enable Latch WEL bit is to send a Write Disable instruction to the device As shown in Figure 8 to send this instruction to the device Chip Select S is driven low and the bits of the instruction byte are shifted in on Serial Data Input D The device then enters a wait state It waits for a the device to be deselected by Chip Select S being driven high The Write Enable Latch WEL bit in fact becomes reset by any of the following events e Power up e WhDl instruction execution e WRSR instruction completion e WRITE instruction completion Figure 8 Write Disable WRDI sequence S NL 0123 45 6 7 C Instruction D High Impedance Q AI03750D Doc ID 5711 Rev 14 ky M95320 W M95320 R M95320 DR Instructions 6 3 6 3 1 6 3 2 6 3 3 Read Status Register RDSR The Read Status Register RDSR instruction is used to read the Status Register The Status Register may be read at any time even while a Write or Write Status Register cycle is in progress When one of these cycles is in progress it is recommended to check the Write In Progress WIP bit before sending a new instruction to the device It is also possible to read the Status Registe
29. ens 44 Doc ID 5711 Rev 14 ky M95320 W M95320 R M95320 DR List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Logic diagram seed aa Gawd Due pem a ker beled un AR e v 6 8 pin package connections top view lllselleee II 7 Block diagram i e Rh ees Bie an ee oad wale aper nae e s CORR end 8 Bus master and memory devices on the SPI bus 0 0000 elles 11 SPI modes supported 1 0 0 0 ccc tetas 12 Hold condition activation 0 0 0 0 0 ce m rn 14 Write Enable WREN sequence 00 0 cece tent eh 17 Write Disable WRDI sequence 00 00 cece rn 18 Read Status Register RDSR sequence 0 00 c eee eee 19 Write Status Register WRSR sequence 0 0 cece eee 20 Read from Memory Array READ sequence 600e cece eee eee ee 22 Byte Write WRITE sequence 0 00 c cette ee 23 Page Write WRITE sequence 000 ccc eet tee 24 Read Identification Page sequence 0 cee eee 26 Write Identification Page sequence 0 cee eee 27 Read Lock Status sequence 000 c eect eee 28 Lock ID sequence 0 ee tees 29 AC measurement I O waveform 0 0 cette 32
30. ext rising edge of Serial Clock C Otherwise the Write Status Register WRSR instruction is not executed The instruction sequence is shown in Figure 10 Figure 10 Write Status Register WRSR sequence 0123 4 5 6 7 8 9 10 11 12 13 14 15 Status Register In High Impedance MSB Al02282D 20 48 Doc ID 5711 Rev 14 ky M95320 W M95320 R M95320 DR Instructions Driving the Chip Select S signal high at a byte boundary of the input data triggers the self timed Write cycle that takes ty to complete as specified in AC tables under Section 9 DC and AC parameters While the Write Status Register cycle is in progress the Status Register may still be read to check the value of the Write in progress WIP bit the WIP bit is 1 during the self timed Write cycle ty and O when the Write cycle is complete The WEL bit Write Enable Latch is also reset at the end of the Write cycle ty The Write Status Register WRSR instruction enables the user to change the values of the BP1 BPO and SRWD bits e The Block Protect BP1 BPO bits define the size of the area that is to be treated as read only as defined in Table 2 e The SRWD Status Register Write Disable bit in accordance with the signal read on the Write Protect pin W enables the user to set or reset the Write protection mode of the Status Register itself as defined in Table 7 When in Write protected mode the Write Status Register WRSR instruction
31. f the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS
32. for M95320 W and M95640 W upgraded from 5 MHz to 10 MHz in the device grade 6 T4 temperature range Table 32 AC characteristics M95080 W device grade 6 modified accordingly Table 27 Available M95640x products package voltage range temperature grade PB process letter added P process letter removed Blank option removed below Plating technology in Table 45 Ordering information scheme Table 25 and Table 27 added Small text changes Table 24 UFDFPN8 MLP8 8 lead ultra thin fine pitch dual flat no lead package mechanical data updated Package mechanical inch values calculated from mm and rounded to 4 decimal digits in Section 10 Package mechanical data 17 Dec 2007 Section 3 8 Vss ground added Device behavior when Vcc passes over the POR threshold updated see Section 4 1 2 Device reset and Section 4 1 4 Power down Vi and Vi modified in Table 19 DC characteristics M95640 DF device grade 6 tw write time modified in Table 20 AC characteristics M95320 R and Table 21 AC characteristics M95640 R Small text changes Doc ID 5711 Rev 14 45 48 Revision history M95320 W M95320 R M95320 DR 46 48 Table 23 Document revision history continued Date 20 Mar 2008 Revision Changes Section 4 1 Supply voltage Vcc updated 10 MHz frequencies added to Table 26 AC characteristics M95080 device grade 3 and Table 29 AC characteristics M95080 W device grade 3
33. gnal names ous peru a deba e Pared AP Ped dad e abee a eate det vas 6 Write protected block size l lelseeeeeeee RR I Ih 15 annie Ec DC 16 M95320 DR instruction set 0 rn 16 Address range bits 0 0 0 ee nnn 16 Status Register format esasa 000 ccc teeta 20 Protection modes 000 eee eee 21 Absolute maximum ratings llle eh 31 Operating conditions M95320 W device grade 6 00 cece eee 32 Operating conditions M95320 R and M95320 DR device grade 6 32 AC measurement conditions llle 32 Capacitance eys sapuna aaya ae A eser hn 33 Cycling performance by groups of four byteS 6 0 eese 33 Memory cell data retention llle I 33 DC characteristics M95320 W device grade 6 0 00 c eee eee 34 DC characteristics M95320 R M95320 DR device grade 6 00 0005 35 AC characteristics M95320 W device grade 6 00 e eee eee 36 AC characteristics M95320 R M95320 DR device grade 6 00055 37 SO8N 8 lead plastic small outline 150 mils body width mechanical data 40 UFDFPN8 MLP8 8 lead ultra thin fine pitch dual flat package no lead 2 3 mmi data u asap oret ies do boe iit Debe e Eee b danda a ae 41 TSSOPS 8 lead thin shrink small outline package mechanical data 42 Ordering information scheme 00 ccc eet e 43 Document revision history 0 0 0 te
34. gs Symbol Parameter Min Max Unit Ambient operating temperature 40 130 C TsTG Storage temperature 65 150 C TLEAp Lead temperature during soldering See note C Vo Output voltage 0 50 Vcc 0 6 V Vi Input voltage 0 50 6 5 Voc Supply voltage 0 50 6 5 V lo DC output current Q 0 5 mA loH DC output current Q 1 5 mA VEsp Electrostatic discharge voltage human body model 4000 V 1 Compliant with JEDEC Std J STD 020 for small body Sn Pb or Pb assembly with the ST ECOPACK 7191395 specification and with the European directive on Restrictions on Hazardous Substances RoHS 2002 95 EU 2 Positive and negative pulses applied on pin pairs according to AEC Q100 002 compliant with JEDEC Std JESD22 A114 C1 100 pF R121500 Q R2 500 Doc ID 5711 Rev 14 31 48 DC and AC parameters M95320 W M95320 R M95320 DR 9 32 48 DC and AC parameters This section summarizes the operating conditions and the DC AC characteristics of the device Table 9 Operating conditions M95320 W device grade 6 Symbol Parameter Min Max Unit Voc Supply voltage 2 5 5 5 V TA Ambient operating temperature 40 85 C Table 10 Operating conditions M95320 R and M95320 DR device grade 6 Symbol Parameter Min Max Unit Vec Supply voltage 1 8 5 5 V TA Ambient operating temperature 40 85 C Table 11 AC measurement conditions
35. he Status Register Write Disable SRWD bit in the Status Register is set to 1 two cases should be considered depending on the state of the Write Protect W input pin e If Write Protect W is driven high it is possible to write to the Status Register provided that the WEL bit has previously been set by a WREN instruction e If Write Protect W is driven low it is not possible to write to the Status Register even if the WEL bit has previously been set by a WREN instruction Attempts to write to the Status Register are rejected and are not accepted for execution As a consequence all the data bytes in the memory area which are Software protected SPM by the Block Protect BP1 BPO bits in the Status Register are also hardware protected against data modification Regardless of the order of the two events the Hardware protected mode HPM can be entered by e either setting the SRWD bit after driving the Write Protect W input pin low e ordriving the Write Protect W input pin low after setting the SRWD bit Once the Hardware protected mode HPM has been entered the only way of exiting it is to pull high the Write Protect W input pin If the Write Protect W input pin is permanently tied high the Hardware protected mode HPM can never be activated and only the Software protected mode SPM using the Block Protect BP1 BPO bits in the Status Register can be used Read from Memory Array READ As shown in Figu
36. in Standby Power mode there should not be any internal write cycle in progress Active Power and Standby Power modes When Chip Select S is low the device is selected and in the Active Power mode The device consumes lcc When Chip Select S is high the device is deselected If a Write cycle is not currently in progress the device then goes into the Standby Power mode and the device consumption drops to Icoc as specified in DC characteristics see Section 9 DC and AC parameters Hold condition The Hold HOLD signal is used to pause any serial communications with the device without resetting the clocking sequence To enter the Hold condition the device must be selected with Chip Select S low During the Hold condition the Serial Data Output Q is high impedance and the Serial Data Input D and the Serial Clock C are Don t Care Normally the device is kept selected for the whole duration of the Hold condition Deselecting the device while it is in the Hold condition has the effect of resetting the state of the device and this mechanism can be used if required to reset any processes that had been in progress 9 b Figure 6 Hold condition activation Condition Condition Al02029D The Hold condition starts when the Hold HOLD signal is driven low when Serial Clock C is already low as shown in Figure 6 a This resets the internal logic except the WEL and WIP bits of the Status Register
37. is not executed The contents of the SRWD and BP1 BPO bits are updated after the completion of the WRSR instruction including the tw Write cycle The Write Status Register WRSR instruction has no effect on the b6 b5 b4 b1 bO bits in the Status Register Bits b6 b5 b4 are always read as O Table 7 Protection modes W SRWD Mode Write protection of the Memory content signal bit Status Register Protected area Unprotected areal 1 0 Status Register is 0 0 writable if the WREN Software instruction has set the Heady toaccept protected WEL bit Write protected Wie EN aa 1 1 SPM The values in the BP1 and BPO bits can be changed Status Register is Hardware Hardware write protected Ready to accept 0 1 protected Write protected D HPM The values in the BP1 Write instructions and BPO bits cannot be changed 1 As defined by the values in the Block Protect BP1 BPO bits of the Status Register See Table 2 The protection features of the device are summarized in Table 7 When the Status Register Write Disable SRWD bit in the Status Register is O its initial delivery state it is possible to write to the Status Register provided that the WEL bit has previously been set by a WREN instruction regardless of the logic level applied on the Write Protect W input pin Doc ID 5711 Rev 14 21 48 Instructions M95320 W M95320 R M95320 DR 6 5 Figure 11 When t
38. iven low The bits of the instruction byte address byte and at least one data byte are then shifted in on Serial Data Input D The instruction is terminated by driving Chip Select S high at a byte boundary of the input data The self timed Write cycle triggered by the Chip Select S rising edge continues for a period tw as specified in AC characteristics in Section 9 DC and AC parameters at the end of which the Write in Progress WIP bit is reset to O Figure 12 Byte Write WRITE sequence NI LLL l LT 0123 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 Oo 16 Bit Address D ORT AAA ASA ASAS Ae AAAA High Impedance Data Byte Al01795D 1 Depending on the memory size as shown in Table 5 the most significant address bits are Don t Care In the case of Figure 12 Chip Select S is driven high after the eighth bit of the data byte has been latched in indicating that the instruction is being used to write a single byte However if Chip Select S continues to be driven low as shown in Figure 13 the next byte of input data is shifted in so that more than a single byte starting from the given address towards the end of the same page can be written in a single internal Write cycle Each time a new data byte is shifted in the least significant bits of the internal address counter are incremented If the number of data bytes sent to the device exceeds the page boundary the internal
39. logic The ECC is an internal logic function which is transparent for the SPI communication protocol The ECC logic is implemented on each group of four EEPROM bytes 9 Inside a group if a single bit out of the four bytes happens to be erroneous during a Read operation the ECC detects this bit and replaces it with the correct value The read reliability is therefore much improved Even if the ECC function is performed on groups of four bytes a single byte can be written cycled independently In this case the ECC function also writes cycles the three other bytes located in the same group As a consequence the maximum cycling budget is defined at group level and the cycling can be distributed over the four bytes of the group the sum of the cycles seen by byteO byte1 byte2 and byte3 of the same group must remain below the maximum value defined in Table 13 c A group of four bytes is located at addresses 4 N 4 N 1 4 N 2 4 N 3 where N is an integer Doc ID 5711 Rev 14 25 48 Instructions M95320 W M95320 R M95320 DR 6 7 Read Identification Page available only in M95320 DR devices The Identification Page 32 bytes is an additional page which can be written and later permanently locked in Read only mode Reading this page is achieved with the Read Identification Page instruction see Table 4 The Chip Select signal S is first driven low the bits of the instruction byte and address bytes are then shifted in on
40. ns tcupx tpp Data in hold time 20 ns tHHCH Clock low hold time after HOLD not active 60 ns tu cH Clock low hold time after HOLD active 60 ns toLHL Clock low set up time before HOLD active 0 ns tcLHH Clock low set up time before HOLD not active 0 ns tsHaz tpig Output disable time 80 ns tcLav ty Clock low to output valid 80 ns tciox tHo Output hold time 0 ns toon tao Output rise time 80 ns tga tro Output fall time 80 ns tuHav ttz HOLD high to output valid 80 ns tuiaz thz HOLD low to output high Z 80 ns tw twc Write time 5 ms 1 If the application uses the M95320 R at 2 5 V lt Vcc 5 5 V and 40 C lt T4 lt 85 C please refer t to Table 17 AC characteristics M95320 W device grade 6 rather than to the above table 2 tcp tc must never be lower than the shortest possible clock period 1 fc max 3 Characterized only not tested in production Doc ID 5711 Rev 14 37 48 DC and AC parameters M95320 W M95320 R M95320 DR Figure 19 Serial input timing tCHSH High impedance Al01447d Figure 20 Hold timing tCLHL A tHLQZ Q eae HOLD Al01448c 38 48 Doc ID 5711 Rev 14 M95320 W M95320 R M95320 DR DC and AC parameters Figure 21 Serial output timing Al01449f ky Doc ID 5711 Rev 14 39 48 Package mechanical data M95320 W M95320 R M95320 DR 10 Package mechanical data In order to mee
41. oc ID 5711 Rev 14 ky M95320 W M95320 R M95320 DR Instructions 6 10 Lock ID available only in M95320 DR devices The Lock ID instruction permanently locks the Identification Page in read only mode Before this instruction can be accepted a Write Enable WREN instruction must have been executed The Lock ID instruction is issued by driving Chip Select S low sending the instruction code the address and a data byte on Serial Data Input D and driving Chip Select S high In the address sent A10 must be equal to 1 all other address bits are Don t Care The data byte sent must be equal to the binary value xxxx xx1x where x Don t Care Chip Select S must be driven high after the rising edge of Serial Clock C that latches in the eighth bit of the data byte and before the next rising edge of Serial Clock C Otherwise the Lock ID instruction is not executed Driving Chip Select S high at a byte boundary of the input data triggers the self timed write cycle whose duration is ty as specified in AC characteristics in Section 9 DC and AC parameters The instruction sequence is shown in Figure 17 The instruction is discarded and is not executed under the following conditions e If a Write cycle is already in progress e If the Block Protect bits BP1 BPO 1 1 Ifa rising edge on Chip Select S happens outside of a byte boundary Figure 17 Lock ID sequence s Nf 012 3 4 5 6 7 8 9 10 20 21 22 23 2
42. ock 5ms 10ms Write Time 100K 1M erase write cycles distinguished on front page and in the DC and AC Characteristics tables 26 Mar 2003 2 3 Process identification letter corrected in footnote to AC Characteristics table for temp range 3 26 Jun 2003 2 4 S voltage range upgraded by removing it and inserting R voltage range in its place 15 Oct 2003 3 0 Table of contents and Pb free options added Vi min improved to 0 45V 21 Nov 2003 3 1 Vi min and Vo min corrected improved to 0 45V 28 Jan 2004 24 May 2005 4 0 5 0 TSSOP8 connections added to DIP and SO connections M95320 S and M95640 S root part numbers 1 65 to 5 5V Supply and related characteristics added 20MHz Clock rate added TSSOP14 package removed and MLP8 package added Description of Power On Reset VCC Lock Out Write Protect updated Product List summary table added Absolute Maximum Ratings for Vio min and Vcc min improved Soldering temperature information clarified for RoHS compliant devices Device Grade 3 clarified with reference to HRCF and automotive environments AEC Q100 002 compliance teyH min and toyyH min is toy for products under S process tyyax corrected to tyHay Figure 20 Hold timing updated q Doc ID 5711 Rev 14 M95320 W M95320 R M95320 DR Revision history Table 23 Document revision history continued Date 07 Jul 2006 Revision
43. r continuously as shown in Figure 9 Figure 9 Read Status Register RDSR sequence 012 3 45 6 7 8 9 10 t1 12 13 14 15 c N Instruction B ee o moe DESERT ign Impedance u n CASAS ASA AEA AGAT ASASAS SAEC AN MSB MSB Al02031E The status and control bits of the Status Register are as follows WIP bit The Write In Progress WIP bit indicates whether the memory is busy with a Write or Write Status Register cycle When set to 1 such a cycle is in progress when reset to 0 no such cycle is in progress WEL bit The Write Enable Latch WEL bit indicates the status of the internal Write Enable Latch When set to 1 the internal Write Enable Latch is set When set to 0 the internal Write Enable Latch is reset and no Write or Write Status Register instruction is accepted The WEL bit is returned to its reset state by the following events e Power up e Write Disable WRDI instruction completion e Write Status Register WRSR instruction completion e Write WRITE instruction completion BP1 BPO bits The Block Protect BP1 BPO bits are non volatile They define the size of the area to be software protected against Write instructions These bits are written with the Write Status Register WRSR instruction When one or both of the Block Protect BP1 BPO bits is set to 1 the relevant memory area as defined in Table 2 becomes protected against Write WRITE instructions The Block Protect BP1 BPO bi
44. re 11 to send this instruction to the device Chip Select S is first driven low The bits of the instruction byte and address bytes are then shifted in on Serial Data Input D The address is loaded into an internal address register and the byte of data at that address is shifted out on Serial Data Output Q Read from Memory Array READ sequence SON 012 3 45 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 Instruction 16 Bit Address Data Out 2 High Impedance Al01793D 1 Depending on the memory size as shown in Table 5 the most significant address bits are Don t Care 22 48 If Chip Select S continues to be driven low the internal address register is incremented automatically and the byte of data at the new address is shifted out Doc ID 5711 Rev 14 ky M95320 W M95320 R M95320 DR Instructions 6 6 When the highest address is reached the address counter rolls over to zero allowing the Read cycle to be continued indefinitely The whole memory can therefore be read with a single READ instruction The Read cycle is terminated by driving Chip Select S high The rising edge of the Chip Select S signal can occur at any time during the cycle The instruction is not accepted and is not executed if a Write cycle is currently in progress Write to Memory Array WRITE As shown in Figure 12 to send this instruction to the device Chip Select S is first dr
45. rite to Memory Array 0000 0010 Table 4 M95320 DR instruction set Instruction Description instruction format WREN Write Enable 0000 0110 WRDI Write Disable 0000 0100 RDSR Read Status Register 0000 0101 WRSR Write Status Register 0000 0001 READ Read from Memory Array 0000 0011 WRITE Write to Memory Array 0000 0010 E Identification Roads the page dedicated to identification 1000 0011 a Identification Writes the page dedicated to identification 1000 00100 Read Lock Status Reads the lock status of the Identification Page 1000 0011 Lock ID Locks the Identification page in read only mode 1000 00102 1 Address bit A10 must be O all other address bits are Don t Care 2 Address bit A10 must be 1 all other address bits are Don t Care Table 5 Address range bits Address significant bits A11 A0 1 Upper MSBs are Don t Care 16 48 Doc ID 5711 Rev 14 4 M95320 W M95320 R M95320 DR Instructions 6 1 Write Enable WREN The Write Enable Latch WEL bit must be set prior to each WRITE and WRSR instruction The only way to do this is to send a Write Enable instruction to the device As shown in Figure 7 to send this instruction to the device Chip Select S is driven low and the bits of the instruction byte are shifted in on Serial Data Input D The device then enters a wait state It waits for the device to be deselected by Chip Select S being driven high Figure 7 Write Enable WREN sequ
46. t environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark Figure 22 SO8N 8 lead plastic small outline 150 mils body width package outline A2 e hx 45 0 25 mm GAUGE PLANE SO A 1 Drawing is not to scale Table 19 SO8N 8 lead plastic small outline 150 mils body width mechanical data millimeters inches Symbol Typ Min Max Typ Min Max A 1 750 0 0689 Al 0 100 0 250 0 0039 0 0098 A2 1 250 0 0492 b 0 280 0 480 0 0110 0 0189 c 0 170 0 230 0 0067 0 0091 ccc 0 100 0 0039 D 4 900 4 800 5 000 0 1929 0 1890 0 1969 E 6 000 5 800 6 200 0 2362 0 2283 0 2441 E1 3 900 3 800 4 000 0 1535 0 1496 0 1575 e 1 270 0 0500 h 0 250 0 500 0 0098 0 0197 k 0 8 0 8 L 0 400 1 270 0 0157 0 0500 L1 1 040 0 0409 1 Values in inches are converted from mm and rounded to four decimal digits 40 48 Doc ID 5711 Rev 14 M95320 W M95320 R M95320 DR Package mechanical data 4 Figure 23 UFDFPNS MLP 8 8 lead ultra thin fine pitch dual flat no lead package outline MB MC D L3 E A A 4 O eee
47. ts can be written provided that the Hardware Protected mode has not been set Doc ID 5711 Rev 14 19 48 Instructions M95320 W M95320 R M95320 DR 6 3 4 SRWD bit The Status Register Write Disable SRWD bit is operated in conjunction with the Write Protect W signal The Status Register Write Disable SRWD bit and Write Protect W signal enable the device to be put in the Hardware Protected mode when the Status Register Write Disable SRWD bit is set to 1 and Write Protect W is driven low In this mode the non volatile bits of the Status Register SRWD BP1 BPO become read only bits and the Write Status Register WRSR instruction is no longer accepted for execution Table 6 Status Register format b7 bO SRWD 0 0 0 BP1 BPO WEL WIP Status Register Write Protect Block Protect bits Write Enable Latch bit Write In Progress bit 6 4 Write Status Register WRSR The Write Status Register WRSR instruction is used to write new values to the Status Register Before it can be accepted a Write Enable WREN instruction must have been previously executed The Write Status Register WRSR instruction is entered by driving Chip Select S low followed by the instruction code the data byte on Serial Data input D and Chip Select S driven high Chip Select S must be driven high after the rising edge of Serial Clock C that latches in the eighth bit of the data byte and before the n
48. ytes and at least one data byte are then shifted in on Serial Data Input D Address bit A10 must be 0 upper address bits are Don t Care the lower address bits A4 A0 address bits define the byte address inside the identification page The instruction sequence is shown in Figure 15 Figure 15 Write Identification Page sequence S 012 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 Oo 16 bit address Data byte e S High impedance Ai15967 Doc ID 5711 Rev 14 27 48 Instructions M95320 W M95320 R M95320 DR 6 9 Read Lock Status available only in M95320 DR devices The Read Lock Status instruction see Table 4 is used to check whether the Identification Page is locked or not in Read only mode The Read Lock Status sequence is defined with the Chip Select S first driven low The bits of the instruction byte and address bytes are then shifted in on Serial Data Input D Address bit A10 must be 1 all other address bits are Don t Care The Lock bit is the LSB least significant bit of the byte read on Serial Data Output Q It is at 1 when the lock is active and at 0 when the lock is not active If Chip Select S continues to be driven low the same data byte is shifted out The read cycle is terminated by driving Chip Select S high The instruction sequence is shown in Figure 16 Figure 16 Read Lock Status sequence High impedance Ai15966 28 48 D

ST M95320-W M95320-R M95320-DR 32-Kbit serial SPI bus EEPROM with high-speed clock handbook

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