ST M95256-125 Automotive 256-Kbit serial SPI bus EEPROM handbook
Contents
1. 0 00 ete 12 Hold condition activation 14 Write Enable WREN sequence 0 0 0 cece te teen en 16 Write Disable WRDI seguence 17 Read Status Register RDSR seguence 18 Write Status Register WRSR seguence 20 Read from Memory Array READ seguence 22 Byte Write WRITE seguence 23 Page Write WRITE sequence 24 AC measurement I O waveform 27 Serial input timing 0 2 0 0 a a a hh 32 Holditiming 222 oes dra IIIA Ere xa ee dave m ween eee es anes 32 Serial output MIN sirda rea IAEA KUIA Wa EIA 33 SO8N 8 lead plastic small outline 150 mils body width package outline 34 TSSOPS 8 lead thin shrink small outline package outline 35 Doc ID 022582 Rev 1 ky M95256 125 Description Description The M95256 devices are Electrically Erasable PROgrammable Memories EEPROMs organized as 32768 x 8 bits accessed through the SPI bus The M95256 devices can operate with a supply range from 2 5 V up to 5 5 V and are guaranteed over the 40 C 125 C temperature range They are compliant with the Automotive standard AEC Q100 Grade 1 Figure 1 Logi2. AC measurement conditions 27 Tableti Capacitance KA eh 27 Table 12 DC characteristics M95256 device grade 3 28 Table 13 DC characteristics M95256 W device grade 3 29 Table 14 AC characteristics M95256 device grade 3 30 Table 15 AC characteristics M95256 W device grade 3 31 Table 16 SO8N 8 lead plastic small outline 150 mils body width mechanical data 34 Table 17 TSSOPS 8 lead thin shrink small outline package mechanical data 35 Table 18 Orderinginformationscheme 36 Table 19 Document revision history 37 ky Doc ID 022582 Rev 1 4 38 List of figures M95256 125 List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 5 38 Logic diagram seed aa Gawd Due pem a ker beled un AR e v 6 8 pin package connections top view 7 Block diagram i e Rh ees Bie an ee oad wale aper nae e s CORR end 8 Bus master and memory devices on the SPIbus 11 SPI modes supported
3. The device then enters a wait state It waits for a the device to be deselected by Chip Select S being driven high The Write Enable Latch WEL bit in fact becomes reset by any of the following events e Power up e WRDI instruction execution e WRSR instruction completion e WRITE instruction completion Figure 8 Write Disable WRDI sequence S NL 0123 45 6 7 C Instruction D High Impedance Q AI03750D Doc ID 022582 Rev 1 ky M95256 125 Instructions 6 3 Read Status Register RDSR The Read Status Register RDSR instruction is used to read the Status Register The Status Register may be read at any time even while a Write or Write Status Register cycle is in progress When one of these cycles is in progress it is recommended to check the Write In Progress WIP bit before sending a new instruction to the device It is also possible to read the Status Register continuously as shown in Figure 9 Figure 9 Read Status Register RDSR sequence 012 3 45 6 7 8 9 10 t1 12 13 14 15 c N Instruction B NAA moe Kaa DESERT igh Impedance u n CASAS ASA AEA AGAT ASASAS SAEC AN MSB MSB Al02031E The status and control bits of the Status Register are as follows 6 3 1 WIP bit The Write In Progress WIP bit indicates whether the memory is busy with a Write or Write Status Register cycle When set to 1 such a cycle is in progress when reset to 0 no such cycle is in p
4. 17 M95256 125 Automotive 256 Kbit serial SPI bus EEPROM Features m Compatible with the Serial Peripheral Interface SPI bus m Memory array 256 Kb 32 Kbytes of EEPROM Page size 64 bytes m Write Byte Write within 5 ms Page Write within 5 ms m Write Protect quarter half or whole memory array m High speed clock 5 MHz m Single supply voltage 4 5 V to 5 5 V for M95256 2 5V to 5 5 V for M95256 W m Operating temperature range from 40 C up to 125 C Enhanced ESD protection More than 1 million Write cycles More than 40 year data retention Packages RoHS compliant and halogen free ECOPACK January 2012 Doc ID 022582 Rev 1 SO8 MN 150 mil width TSSOP8 DW 169 mil width 1 38 www st com M95256 125 Contents Contents 1 Description Wc a alas RA 6 2 Memory organization 8 3 Signal description 9 3 1 Serial Data Output Q 9 3 2 Serial Data Input D 322945 sss AR ERE midea daia EAR o dd 9 3 3 Seal Clock AUA dd ideae pO eode Edd eod oes 9 84 Chip Select B i end epacsios OR Eat y E RE Ra en OR qb E 9 235 AAA sek sarsan rnnr Khe hehe RPG SEAHORSES ERR RO d 9 3 6 White Protect W 10 3 7 Voo supply voltage 10 SK V
5. mode the non volatile bits of the Status Register SRWD BP1 BPO become read only bits and the Write Status Register WRSR instruction is no longer accepted for execution Table 5 Status Register format b7 bO SRWD 0 0 BP1 BPO WEL WIP Status Register Write Protect Doc ID 022582 Rev 1 Block Protect bits Write Enable Latch bit Write In Progress bit M95256 125 Instructions 6 4 Write Status Register WRSR The Write Status Register WRSR instruction is used to write new values to the Status Register Before it can be accepted a Write Enable WREN instruction must have been previously executed The Write Status Register WRSR instruction is entered by driving Chip Select S low followed by the instruction code the data byte on Serial Data input D and Chip Select S driven high Chip Select S must be driven high after the rising edge of Serial Clock C that latches in the eighth bit of the data byte and before the next rising edge of Serial Clock C Otherwise the Write Status Register WRSR instruction is not executed The instruction sequence is shown in Figure 10 Figure 10 Write Status Register WRSR sequence 0123 4 5 6 7 8 9 10 11 12 13 14 15 Status Register In High Impedance MSB Al02282D Driving the Chip Select S signal high at a byte boundary of the input data triggers the self timed Write cycle that takes tyy
6. 5 Read from Memory Array READ 22 6 6 Write to Memory Array WRITE 22 6 6 1 ECC error correction code and write cycling 24 7 Power up and delivery state 25 7 1 POWGSIUPSIAIG 1 isis xr REA eu E RR RR AA KAA awed AUR 25 7 2 Initial delivery Stale 25 8 Makimumrating 26 9 DC and AC parameters 27 10 Package mechanicaldata 34 11 Part numbering uua eem n In ORC OR e n Rn n 6 Sw oe Oa 36 12 Revision history 37 3 38 Doc ID 022582 Rev 1 ky M95256 125 List of tables List of tables Table 1 Signal a are Ped Pace epus doe baa Parra acd PRG eee Dabo E 6 Table 2 Write protected block size 15 Table 3 INStruCtION SOl CR 16 Table 4 Address range bits 0 0 0 cc teens 16 Table 5 Status Register format 19 Table 6 Protection modes IAA IAA aa 21 Table 7 Absolute makimumratings 26 Table 8 Operating conditions M95256 device grade 3 27 Table 9 Operating conditions M95256 W device grade 3 27 Table 10
7. Clock low time 90 ns tc cu tnc Clock rise time 1 us tehel tec Clock fall time 1 us tpvcH tpsu Data in setup time 20 ns tcupx toy Data in hold time 30 ns tHHCH Clock low hold time after HOLD not active 70 ns tu cH Clock low hold time after HOLD active 40 ns tcLHL Clock low set up time before HOLD active 0 ns lci HH Clock low set up time before HOLD not active 0 ns tsuoz tois Output disable time 100 ns tcLav ty Clock low to output valid 60 ns tcLax tho Output hold time 0 ns tarah ipo Output rise time 50 ns tahal tro Output fall time 50 ns tHHav tz HOLD high to output valid 50 ns tui oz taz HOLD low to output high Z 100 ns tw twc Write time 5 ms 1 tcp tc must never be lower than the shortest possible clock period 1 fc max 2 Characterized only not tested in production Doc ID 022582 Rev 1 30 38 DC and AC parameters M95256 125 Table 15 AC characteristics M95256 W device grade 3 Test conditions specified in Table 10 and Table 9 Symbol Alt Parameter Min Max Unit fo fsck Clock frequency D C 5 MHz tsi cH tcssi S active setup time 90 ns tsHCH tcsso S not active setup time 90 ns tsHSL tcs S deselect time 100 ns tcHsH tesu S active hold time 90 ns tchsL S not active hold time 90 ns tcu tet Clock high time 90 ns to teu Clock low time 90 ns tc cu tac Clock rise time 1 us tcuci tec Clock fall time 1 us tpvcH tosu Data
8. Register are rejected and are not accepted for execution As a consequence all the data bytes in the memory area which are Software protected SPM by the Block Protect BP1 BPO bits in the Status Register are also hardware protected against data modification Regardless of the order of the two events the Hardware protected mode HPM can be entered by e either setting the SRWD bit after driving the Write Protect W input pin low e ordriving the Write Protect W input pin low after setting the SRWD bit Once the Hardware protected mode HPM has been entered the only way of exiting it is to pull high the Write Protect W input pin If the Write Protect W input pin is permanently tied high the Hardware protected mode HPM can never be activated and only the Software protected mode SPM using the Block Protect BP1 BPO bits in the Status Register can be used Doc ID 022582 Rev 1 ky M95256 125 Instructions 6 5 Read from Memory Array READ As shown in Figure 11 to send this instruction to the device Chip Select S is first driven low The bits of the instruction byte and address bytes are then shifted in on Serial Data Input D The address is loaded into an internal address register and the byte of data at that address is shifted out on Serial Data Output Q Figure 11 Read from Memory Array READ sequence s Noo 012 34567 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 Data Out 2 Hig
9. Symbol Parameter Min Max Unit Vec Supply voltage 2 5 5 5 V TA Ambient operating temperature 40 125 C Table 10 AC measurement conditions Symbol Parameter Min Max Unit C Load capacitance 100 pF Input rise and fall times 25 ns Input pulse voltages 0 2 Vcc to 0 8 Vec Input and output timing reference voltages 0 3 Voc to 0 7 Voc V Figure 14 AC measurement I O waveform Input voltage levels Input and output timing reference levels 0 8 Vcc 0 2 Vcc AI00825C Table 11 Capacitance Symbol Parameter Test condition Min Max Unit Cour Output capacitance Q Vout 20V 8 pF B Input capacitance D Vin 20V 8 pF IN Input capacitance other pins Vi 20V 6 pF 1 Sampled only not 100 tested at T4 25 C and a frequency of 5 MHz Doc ID 022582 Rev 1 M95256 125 DC and AC parameters Table 12 DC characteristics M95256 device grade 3 Symbol Parameter Test conditions Min Max Unit Input leakage lui ere 9 Vin Vss or Voc 2 pA Output leakage z ILo RUNE 9 S Vcc Vout Vss Or Vcc 2 HA C 0 1 Voc 0 9 Voc at5 MHz lec Supply current Vec 5 V Q open 4 mA Supply current a loct Bid S Voc Voc 5 V Vin Vss Or Vcc 5 HA ViL Input low voltage 0 45 0 3 Voc V Vin Input high voltage 0 7 Vcc Vect V Vg Output low voltage loL 2 mA Voc 2 5 V 0 4 V Vou Output high voltage lop 2 mA Voc 5 V 0 8 Vcc V 1 Forall 5 V r
10. b 0 190 0 300 0 0075 0 0118 C 0 090 0 200 0 0035 0 0079 CP 0 100 0 0039 D 3 000 2 900 3 100 0 1181 0 1142 0 1220 0 650 0 0256 E 6 400 6 200 6 600 0 2520 0 2441 0 2598 E1 4 400 4 300 4 500 0 1732 0 1693 0 1772 L 0 600 0 450 0 750 0 0236 0 0177 0 0295 L1 1 000 0 0394 a 0 8 0 8 N 8 8 1 Values in inches are converted from mm and rounded to four decimal digits Doc ID 022582 Rev 1 q M95256 125 Part numbering 11 Part numbering Table 18 Ordering information scheme Example M95256 W MN 3 T PA Device type M95 SPI serial access EEPROM Device function 256 256 Kbit Operating voltage blank Vcc 4 5 to 5 5 V W Vec 2 5t0 5 5 V Package MN SO8 150 mil width DW TSSOP8 169 mil width Device grade 3 Device tested with high reliability certified flow Automotive temperature range 40 to 125 C Option blank Standard packing T Tape and reel packing Plating technology P RoHS compliant and halogen free ECOPACK Process A or AB Manufacturing technology code ky Doc ID 022582 Rev 1 36 38 Revision history M95256 125 12 37 88 Revision history Table 19 Document revision history Date Revision Changes 05 Jan 2012 1 Initial release Doc ID 022582 Rev 1 M95256 125 Please Read Carefully Information in this document is provided solely in connection with ST products
11. maximum rating conditions for extended periods may affect device reliability Table 7 Absolute maximum ratings Symbol Parameter Min Max Unit Ambient operating temperature 40 130 C TsTG Storage temperature 65 150 C TLEAp Lead temperature during soldering See note 1 C Vo Output voltage 0 50 Vcc 0 6 V Vi Input voltage 0 50 6 5 Voc Supply voltage 0 50 6 5 V lo DC output current Q 0 5 mA loH DC output current Q 1 5 mA VEsp Electrostatic discharge voltage human body model 4000 V 1 Compliant with JEDEC Std J STD 020 for small body Sn Pb or Pb assembly with the ST ECOPACK 7191395 specification and with the European directive on Restrictions on Hazardous Substances RoHS 2002 95 EU 2 Positive and negative pulses applied on pin pairs according to AEC Q100 002 compliant with JEDEC Std JESD22 A114 C1 100 pF R121500 Q R2 500 Doc ID 022582 Rev 1 26 38 DC and AC parameters M95256 125 9 27 38 DC and AC parameters This section summarizes the operating conditions and the DC AC characteristics of the device Table 8 Operating conditions M95256 device grade 3 Symbol Parameter Min Max Unit Voc Supply voltage 4 5 5 5 V TA Ambient operating temperature 40 125 C Table 9 Operating conditions M95256 W device grade 3
12. 1 V us Doc ID 022582 Rev 1 ky M95256 125 Operating features 5 1 4 5 2 5 3 Power down During power down continuous decrease of the Vcc supply voltage below the minimum Vcc operating voltage defined under Operating conditions in Section 9 DC and AC parameters the device must be e deselected Chip Select S should be allowed to follow the voltage applied on Vgc e in Standby Power mode there should not be any internal write cycle in progress Active Power and Standby Power modes When Chip Select S is low the device is selected and in the Active Power mode The device consumes lcc When Chip Select S is high the device is deselected If a Write cycle is not currently in progress the device then goes into the Standby Power mode and the device consumption drops to Icoc as specified in DC characteristics see Section 9 DC and AC parameters Hold condition The Hold HOLD signal is used to pause any serial communications with the device without resetting the clocking sequence To enter the Hold condition the device must be selected with Chip Select S low During the Hold condition the Serial Data Output Q is high impedance and the Serial Data Input D and the Serial Clock C are Don t Care Normally the device is kept selected for the whole duration of the Hold condition Deselecting the device while it is in the Hold condition has the effect of resetting the state of the device and
13. IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2012 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 022582 Rev 1 38 38
14. ITE sequence S 012 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 c 16 Bit Address Data Byte D CRAY 0 0 0 0 0 0 0 0 0 0 0 0 High Impedance Q Al01795D 1 Depending on the memory size as shown in Table 4 the most significant address bits are Don t Care In the case of Figure 12 Chip Select S is driven high after the eighth bit of the data byte has been latched in indicating that the instruction is being used to write a single byte However if Chip Select S continues to be driven low as shown in Figure 13 the next byte of input data is shifted in so that more than a single byte starting from the given address towards the end of the same page can be written in a single internal Write cycle Each time a new data byte is shifted in the least significant bits of the internal address counter are incremented If the number of data bytes sent to the device exceeds the page boundary the internal address counter rolls over to the beginning of the page and the previous data there are overwritten with the incoming data The page size of these devices is 64 bytes The instruction is not accepted and is not executed under the following conditions e ifthe Write Enable Latch WEL bit has not been set to 1 by executing a Write Enable instruction just before e if a Write cycle is already in progress e ifthe device has not been deselected by driving high Chip Select S at a byte boun
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16. ange devices the device meets the output requirements for both TTL and CMOS standards Doc ID 022582 Rev 1 28 38 DC and AC parameters M95256 125 29 38 Table 13 DC characteristics M95256 W device grade 3 Symbol Parameter Test conditions Min Max Unit Input leakage lui ere 9 Vin Vss or Voc 2 pA Output leakage z ILo miena 9 S Voc Vout Vss Or Vcc 2 HA Supply current C 0 1 Vcc 0 9 Vec at 5 MHz Icc Read Voc 2 5 V Q open 3 MA Supply current During tw S Vcc Icco write 25V lt Vec 55 V a ums Supply current S Voc Vin Vss or Voc lcc1 Standby 2 5 V lt Voc lt 5 5 V 5 pA ViL Input low voltage 0 45 V 0 3 Voc V Vin Input high voltage 0 7 Voc Vcctl V Voi Output low voltage lo 1 5 mA Vcg 2 5 V 0 4 V Vou Output high voltage lop 0 4 mA Voc 2 5 V 0 8 Voc V Doc ID 022582 Rev 1 q M95256 125 DC and AC parameters q Table 14 AC characteristics M95256 device grade 3 Test conditions specified in Table 10 and Table 8 Symbol Alt Parameter Min Max Unit fo fsck Clock frequency D C 5 MHz tsi cH tcssi S active setup time 90 ns tsHCH tcss2 S not active setup time 90 ns tsHsL tcs S deselect time 100 ns tcHsH tcsh S active hold time 90 ns tcHsL S not active hold time 90 ns toy tetu Clock high time 90 ns to teu
17. c diagram Vcc D Q C S q M95xxx W q HOLD q Vss Al01789C The SPI bus signals are C D and Q as shown in Figure 1 and Table 1 The device is selected when Chip Select S is driven low Communications with the device can be interrupted when the HOLD is driven low Table 1 Signal names Signal name Function Direction C Serial Clock Input D Serial Data Input Input Q Serial Data Output Output S Chip Select Input W Write Protect Input HOLD Hold Input Voc Supply voltage Vss Ground Doc ID 022582 Rev 1 6 38 Description M95256 125 7 38 Figure 2 8 pin package connections top view M95xxx Al01790D 1 See Section 10 Package mechanical data section for package dimensions and how to identify pin 1 Doc ID 022582 Rev 1 x M95256 125 Memory organization 2 Memory organization The memory is organized as shown in the following figure Figure 3 Block diagram High voltage Control logic generator I O shift register Address register Data and counter register Status Register Size of the read only EEPROM area 5 S BLosssssssrezszkiEIBRERASEERSUs IAA EA 3 gt Alo1272d ky Doc ID 022582 Rev 1 8 38 Signal description M95256 125 3 3 1 3 2 3 3 3 4 3 5 9 38 Signal description During all operations Vcc must be held stable and within the specifi
18. dary after the eighth bit bO of the last data byte that has been latched in e ifthe addressed page is in the region protected by the Block Protect BP1 and BPO bits The self timed write cycle ty is internally executed as a sequence of two consecutive events Erase addressed byte s followed by Program addressed byte s An erased bit is read as 0 and a programmed bit is read as 1 Doc ID 022582 Rev 1 ky M95256 125 Instructions Figure 13 Page Write WRITE sequence PN Lm 012 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 16 Bit Address Data Byte 1 ol Al01796D 1 Depending on the memory size as shown in Table 4 the most significant address bits are Don t Care 6 6 1 ECC error correction code and write cycling M95256 and M95256 W devices offer an ECC error correction code logic which compares each 4 byte word with 6 EEPROM bits of ECC As a result if a single bit out of 4 bytes of data happens to be erroneous during a read operation the ECC detects it and replaces it by the correct value The read reliability is therefore improved by the use of this feature Note however that even if a single byte has to be written 4 bytes are internally modified plus the ECC bits that is the addressed byte is cycled together with the three other bytes making up the word It is therefore recommended to write by packets of 4 bytes in order to benefit from the larger amount of
19. ed valid range Vcc min to Vcc max All of the input and output signals must be held high or low according to voltages of Vip Vou Vit or VoL as specified in Section 9 DC and AC parameters These signals are described next Serial Data Output Q This output signal is used to transfer data serially out of the device Data is shifted out on the falling edge of Serial Clock C Serial Data Input D This input signal is used to transfer data serially into the device It receives instructions addresses and the data to be written Values are latched on the rising edge of Serial Clock C Serial Clock C This input signal provides the timing of the serial interface Instructions addresses or data present at Serial Data Input D are latched on the rising edge of Serial Clock C Data on Serial Data Output Q change from the falling edge of Serial Clock C Chip Select S When this input signal is high the device is deselected and Serial Data Output Q is at high impedance The device is in the Standby Power mode unless an internal Write cycle is in progress Driving Chip Select S low selects the device placing it in the Active Power mode After power up a falling edge on Chip Select S is required prior to the start of any instruction Hold HOLD The Hold HOLD signal is used to pause any serial communications with the device without deselecting the device During the Hold condition the Serial Data O
20. gs ground aox ane kie re RO UR Secu Geet Seeded yee aee be f 10 4 Connecting to the SPI bus 11 4 1 suus CP mmm 12 5 Operating features 13 5 1 Supply voltage Voe iz2smac3 kd e eevee eek Eo ER RR ade Rd dc 13 5 1 1 Operating supply voltage Voc 18 5 1 2 DEVICE reset auars redak riii Ree n EAE RR eR AC ORE AE VR eR Re Red 13 5 1 3 Power up conditions 13 5 1 4 Power down 14 5 2 Active Power and Standby Power modes 14 5 8 Hold condition 14 54 StatusRegister 15 5 5 Data protection and protocol control 15 6 INSTFUCHIONS ose rotuesebRha ask cre SPAGSEEERR IE MEE aes 16 6 1 Write Enable WREN 16 6 2 WrteDisable WRDI 17 6 3 Read Status Register RDSR 18 6 3 1 WIP DiE ste 18 ky Doc ID 022582 Rev 1 2 38 Contents M95256 125 6 3 2 WEL bit 22s Reo bmx REI ERE ee Fae EER RI ERE 18 6 3 3 BP1 BPO DIIS oss dE LEER RENE Ea ER EE RS 18 6 3 4 SBWD Dit 1e babe ex a RR RR WX EE ERES 19 6 4 Write Status Register WRSR 20 6
21. h Impedance Al01793D 1 Depending on the memory size as shown in Table 4 the most significant address bits are Don t Care If Chip Select S continues to be driven low the internal address register is incremented automatically and the byte of data at the new address is shifted out When the highest address is reached the address counter rolls over to zero allowing the Read cycle to be continued indefinitely The whole memory can therefore be read with a single READ instruction The Read cycle is terminated by driving Chip Select S high The rising edge of the Chip Select S signal can occur at any time during the cycle The instruction is not accepted and is not executed if a Write cycle is currently in progress 6 6 Write to Memory Array WRITE As shown in Figure 12 to send this instruction to the device Chip Select S is first driven low The bits of the instruction byte address byte and at least one data byte are then shifted in on Serial Data Input D The instruction is terminated by driving Chip Select S high at a byte boundary of the input data The self timed Write cycle triggered by the Chip Select S rising edge continues for a period tw as specified in AC characteristics in Section 9 DC and AC parameters at the end of which the Write in Progress WIP bit is reset to 0 ky Doc ID 022582 Rev 1 22 38 Instructions M95256 125 Note 23 38 Figure 12 Byte Write WR
22. ilable at www st com ECOPACK is an ST trademark Figure 18 SO8N 8 lead plastic small outline 150 mils body width package outline A2 hx 45 0 25 mm GAUGE PLANE SO A 1 Drawing is not to scale Table 16 SO8N 8 lead plastic small outline 150 mils body width mechanical data millimeters inches Symbol Typ Min Max Typ Min Max A 1 750 0 0689 Al 0 100 0 250 0 0039 0 0098 A2 1 250 0 0492 b 0 280 0 480 0 0110 0 0189 c 0 170 0 230 0 0067 0 0091 ccc 0 100 0 0039 D 4 900 4 800 5 000 0 1929 0 1890 0 1969 E 6 000 5 800 6 200 0 2362 0 2283 0 2441 E1 3 900 3 800 4 000 0 1535 0 1496 0 1575 e 1 270 0 0500 h 0 250 0 500 0 0098 0 0197 k 0 8 0 8 L 0 400 1 270 0 0157 0 0500 L1 1 040 0 0409 1 Values in inches are converted from mm and rounded to four decimal digits Doc ID 022582 Rev 1 34 38 Package mechanical data M95256 125 35 88 Figure 19 TSSOPS 8 lead thin shrink small outline package outline CP D TSSOP8AM 1 Drawing is not to scale Table 17 TSSOPS 8 lead thin shrink small outline package mechanical data millimeters inches Symbol Typ Min Max Typ Min Max A 1 200 0 0472 A1 0 050 0 150 0 0020 0 0059 A2 1 000 0 800 1 050 0 0394 0 0315 0 0413
23. in setup time 20 ns tcupx tp Data in hold time 30 ns tHHCH Clock low hold time after HOLD not active 70 ns tui cH Clock low hold time after HOLD active 40 ns tcLHL Clock low set up time before HOLD active 0 ns tcLHH Clock low set up time before HOLD not active 0 ns tsHoz ipis Output disable time 100 ns tcLav ty Clock low to output valid 60 ns tcLax tuo Output hold time 0 ns tarah ipo Output rise time 50 ns toua tro Output fall time 50 ns tyHav tz HOLD high to output valid 50 ns tui oz tz HOLD low to output high Z 100 ns tw twc Write time 5 ms 31 88 1 tcp tc must never be lower than the shortest possible clock period 1 fc max 2 Characterized only not tested in production Doc ID 022582 Rev 1 q M95256 125 DC and AC parameters Figure 15 Serial input timing tCHSH High impedance Al01447d Figure 16 Hold timing ol tCLHL A Al01448c 4 Doc ID 022582 Rev 1 32 38 DC and AC parameters M95256 125 Figure 17 Serial output timing Al01449f x 33 38 Doc ID 022582 Rev 1 M95256 125 Package mechanical data 10 Package mechanical data In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are ava
24. le from the falling edge of Serial Clock C The difference between the two modes as shown in Figure 5 is the clock polarity when the bus master is in Stand by mode and not transferring data e Cremains at 0 for CPOL 0 CPHA 0 e Cremains at 1 for CPOL 1 CPHA 1 Figure 5 SPI modes supported CPOL CPHA Al01438B Doc ID 022582 Rev 1 12 38 Operating features M95256 125 5 5 1 5 1 2 13 38 Operating features Supply voltage Vcc Operating supply voltage Vcc Prior to selecting the memory and issuing instructions to it a valid and stable Vcc voltage within the specified Vcc min Vcc max range must be applied see Operating conditions in Section 9 DC and AC parameters This voltage must remain stable and valid until the end of the transmission of the instruction and for a Write instruction until the completion of the internal write cycle ty In order to secure a stable DC supply voltage it is recommended to decouple the Vcc line with a suitable capacitor usually of the order of 10 nF to 100 nF close to the Vcc Vss device pins Device reset In order to prevent erroneous instruction decoding and inadvertent Write operations during power up a power on reset POR circuit is included At power up the device does not respond to any instruction until VCC reaches the POR threshold voltage This threshold is lower than the minimum Vcc operating voltage see Operating conditions in Secti
25. multiple of eight e Allinstructions that modify data must be preceded by a Write Enable WREN instruction to set the Write Enable Latch WEL bit e The Block Protect BP1 BPO bits in the Status Register are used to configure part of the memory as read only e The Write Protect W signal is used to protect the Block Protect BP1 BPO bits in the Status Register For any instruction to be accepted and executed Chip Select S must be driven high after the rising edge of Serial Clock C for the last bit of the instruction and before the next rising edge of Serial Clock C Two points should be noted in the previous sentence e The last bit of the instruction can be the eighth bit of the instruction code or the eighth bit of a data byte depending on the instruction except for Read Status Register RDSR and Read READ instructions e The next rising edge of Serial Clock C might or might not be the next bus transaction for some other device on the SPI bus Table 2 Write protected block size Status Register bits Protected block Protected array addresses BP1 BPO 0 0 none none 0 1 Upper quarter 6000h 7FFFh 1 0 Upper half 4000h 7FFFh 1 1 Whole memory 0000h 7FFFh Doc ID 022582 Rev 1 Ey M95256 125 Instructions 6 6 1 Instructions Each instruction starts with a single byte code as summarized in Table 3 If an invalid instruction is sent one not contai
26. ned in Table 3 the device automatically deselects itself Table 3 Instruction set Instruction Description Instruction format WREN Write Enable 0000 0110 WRDI Write Disable 0000 0100 RDSR Read Status Register 0000 0101 WRSR Write Status Register 0000 0001 READ Read from Memory Array 0000 0011 WRITE Write to Memory Array 0000 0010 Table 4 Address range bits Address significant bits A14 A0 1 Upper MSBs are Don t Care Write Enable WREN The Write Enable Latch WEL bit must be set prior to each WRITE and WRSR instruction The only way to do this is to send a Write Enable instruction to the device As shown in Figure 7 to send this instruction to the device Chip Select S is driven low and the bits of the instruction byte are shifted in on Serial Data Input D The device then enters a wait state It waits for the device to be deselected by Chip Select S being driven high Figure 7 Write Enable WREN sequence S A 0123456 7 C Instruction D High Impedance Q Al02281E Doc ID 022582 Rev 1 16 38 Instructions M95256 125 6 2 17 38 Write Disable WRDI One way of resetting the Write Enable Latch WEL bit is to send a Write Disable instruction to the device As shown in Figure 8 to send this instruction to the device Chip Select S is driven low and the bits of the instruction byte are shifted in on Serial Data Input D
27. on 9 DC and AC parameters At power up when Vcc passes over the POR threshold the device is reset and is in the following state e in Standby Power mode e deselected e Status Register values The Write Enable Latch WEL bit is reset to 0 The Write In Progress WIP bit is reset to O The SRWD BP1 and BPO bits remain unchanged non volatile bits It is important to note that the device must not be accessed until Vcc reaches a valid and stable level within the specified Vcc min Vec max range as defined under Operating conditions in Section 9 DC and AC parameters Power up conditions When the power supply is turned on Vcc rises continuously from Vss to Vcc During this time the Chip Select S line is not allowed to float but should follow the Vgc voltage It is therefore recommended to connect the S line to Vcc via a suitable pull up resistor see Figure 4 In addition the Chip Select S input offers a built in safety feature as the S input is edge sensitive as well as level sensitive after power up the device does not become selected until a falling edge has first been detected on Chip Select S This ensures that Chip Select S must have been high prior to going low to start the first operation The Vcc voltage has to rise continuously from 0 V up to the minimum Voc operating voltage defined under Operating conditions in Section 9 DC and AC parameters and the rise time must not vary faster than
28. protected area 1 0 Status Register is writable if the WREN g 2 Software instruction has set the Ready to accept protected WEL bit Write protected Write instructions 1 1 SPM The values in the BP1 and BPO bits can be changed Status Register is Hardware Hardware write protected Ready to accept 0 1 protected Th in the BP1 Write protected Write instruction HPM e values in the e instructions and BPO bits cannot be changed 1 As defined by the values in the Block Protect BP1 BPO bits of the Status Register See Table 2 The protection features of the device are summarized in Table 6 When the Status Register Write Disable SRWD bit in the Status Register is O its initial delivery state it is possible to write to the Status Register provided that the WEL bit has previously been set by a WREN instruction regardless of the logic level applied on the Write Protect W input pin When the Status Register Write Disable SRWD bit in the Status Register is set to 1 two cases should be considered depending on the state of the Write Protect W input pin e If Write Protect W is driven high it is possible to write to the Status Register provided that the WEL bit has previously been set by a WREN instruction e If Write Protect W is driven low it is not possible to write to the Status Register even if the WEL bit has previously been set by a WREN instruction Attempts to write to the Status
29. rogress 6 3 2 WEL bit The Write Enable Latch WEL bit indicates the status of the internal Write Enable Latch When set to 1 the internal Write Enable Latch is set When set to 0 the internal Write Enable Latch is reset and no Write or Write Status Register instruction is accepted The WEL bit is returned to its reset state by the following events e Power up e Write Disable WRDI instruction completion e Write Status Register WRSR instruction completion e Write WRITE instruction completion 6 3 3 BP1 BPO bits The Block Protect BP1 BPO bits are non volatile They define the size of the area to be software protected against Write instructions These bits are written with the Write Status Register WRSR instruction When one or both of the Block Protect BP1 BPO bits is set to 1 the relevant memory area as defined in Table 5 becomes protected against Write WRITE instructions The Block Protect BP1 BPO bits can be written provided that the Hardware Protected mode has not been set ki Doc ID 022582 Rev 1 18 38 Instructions M95256 125 6 3 4 19 38 SRWD bit The Status Register Write Disable SRWD bit is operated in conjunction with the Write Protect W signal The Status Register Write Disable SRWD bit and Write Protect W signal enable the device to be put in the Hardware Protected mode when the Status Register Write Disable SRWD bit is set to 1 and Write Protect W is driven low In this
30. ster SPI Memory SPI Memory SPI Memory Device Device Device CS3 CS2 C Al12836b 1 The Write Protect W and Hold HOLD signals should be driven high or low as appropriate Figure 4 shows an example of three memory devices connected to an SPI bus master Only one memory device is selected at a time so only one memory device drives the Serial Data Output Q line at a time The other memory devices are high impedance The pull up resistor R represented in Figure 4 ensures that a device is not selected if the Bus Master leaves the S line in the high impedance state In applications where the Bus Master may leave all SPI bus lines in high impedance at the same time for example if the Bus Master is reset during the transmission of an instruction the clock line C must be connected to an external pull down resistor so that if all inputs outputs become high impedance the C line is pulled low while the S line is pulled high this ensures that S and C do not become high at the same time and so that the tsucH requirement is met The typical value of R is 100 kQ Doc ID 022582 Rev 1 ky M95256 125 Connecting to the SPI bus 4 1 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the following two modes e CPOL 0 CPHA 0 e CPOL 1 CPHA 1 For these two modes input data is latched in on the rising edge of Serial Clock C and output data is availab
31. this mechanism can be used if required to reset any processes that had been in progress Figure 6 Hold condition activation Condition Condition Al02029D The Hold condition starts when the Hold HOLD signal is driven low when Serial Clock C is already low as shown in Figure 6 a This resets the internal logic except the WEL and WIP bits of the Status Register b In the specific case where the device has shifted in a Write command Inst Address data bytes each data byte being exactly 8 bits deselecting the device also triggers the Write cycle of this decoded command Doc ID 022582 Rev 1 14 38 Operating features M95256 125 5 4 5 5 15 38 The Hold condition ends when the Hold HOLD signal is driven high when Serial Clock C is already low Figure 6 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock C being low Status Register The Status Register contains a number of status and control bits that can be read or set as appropriate by specific instructions See Section 6 3 Read Status Register RDSR for a detailed description of the Status Register bits Data protection and protocol control The device features the following data protection mechanisms e Before accepting the execution of the Write and Write Status Register instructions the device checks whether the number of clock pulses comprised in the instructions is a
32. to complete as specified in AC tables under Section 9 DC and AC parameters While the Write Status Register cycle is in progress the Status Register may still be read to check the value of the Write in progress WIP bit the WIP bit is 1 during the self timed Write cycle tw and 0 when the Write cycle is complete The WEL bit Write Enable Latch is also reset at the end of the Write cycle ty The Write Status Register WRSR instruction enables the user to change the values of the BP1 BPO and SRWD bits e The Block Protect BP1 BPO bits define the size of the area that is to be treated as read only as defined in Table 2 e The SRWD Status Register Write Disable bit in accordance with the signal read on the Write Protect pin W enables the user to set or reset the Write protection mode of the Status Register itself as defined in Table 6 When in Write protected mode the Write Status Register WRSR instruction is not executed The contents of the SRWD and BP1 BPO bits are updated after the completion of the WRSR instruction including the tyy Write cycle The Write Status Register WRSR instruction has no effect on the b6 b5 b4 b1 bO bits in the Status Register Bits b6 b5 b4 are always read as O Doc ID 022582 Rev 1 20 38 Instructions M95256 125 21 38 Table 6 Protection modes Memory content W SRWD Write protection of the Mode signal bit Status Reglster Protected area Un
33. utput Q is high impedance and Serial Data Input D and Serial Clock C are Don t Care To start the Hold condition the device must be selected with Chip Select S driven low Doc ID 022582 Rev 1 ky M95256 125 Signal description 3 6 Write Protect W The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions as specified by the values in the BP1 and BPO bits of the Status Register This pin must be driven either high or low and must be stable during all Write instructions 3 7 Vcc supply voltage Voc is the supply voltage 3 8 Vss ground Vss is the reference for all signals including the Vcc supply voltage ki Doc ID 022582 Rev 1 10 38 Connecting to the SPI bus M95256 125 4 11 38 Connecting to the SPI bus All instructions addresses and input data bytes are shifted in to the device most significant bit first The Serial Data Input D is sampled on the first rising edge of the Serial Clock C after Chip Select S goes low All output data bytes are shifted out of the device most significant bit first The Serial Data Output Q is latched on the first falling edge of the Serial Clock C after the instruction such as the Read from Memory Array and Read Status Register instructions have been clocked into the device Figure 4 Bus master and memory devices on the SPI bus CPOL CPHA 0 0 or 1 1 SPI Bus Ma
34. write cycles The maximum number of write cycles is qualified at 1 million 1 000 000 write cycles using a cycling routine that writes to the device by multiples of 4 byte packets c The word of 4 bytes is located at addresses 4 N 4 N 1 4 N 2 4 N 3 where N is an integer ky Doc ID 022582 Rev 1 24 38 Power up and delivery state M95256 125 7 7 1 7 2 25 38 Power up and delivery state Power up state After power up the device is in the following state Standby power mode deselected after power up a falling edge is required on Chip Select S before any instructions can be started not in the Hold condition the Write Enable Latch WEL is reset to 0 Write In Progress WIP is reset to 0 The SRWD BP1 and BPO bits of the Status Register are unchanged from the previous power down they are non volatile bits Initial delivery state The device is delivered with the memory array set to all 1s each byte FFh The Status Register Write Disable SRWD and Block Protect BP1 and BPO bits are initialized to O Doc ID 022582 Rev 1 ky M95256 125 Maximum rating 8 4 Maximum rating Stressing the device outside the ratings listed in Table 7 may cause permanent damage to the device These are stress ratings only and operation of the device at these or any other conditions outside those indicated in the operating sections of this specification is not implied Exposure to absolute
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ST M95256 125 Automotive 256 Kbit serial SPI bus EEPROM handbook