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ST ST72311R ST72511R ST72512R ST72532R 8-BIT MCU WITH NESTED INTERRUPTS EEPROM ADC 16-BIT TIMERS 8-BIT PWM ART SPI SCI CAN INTERFACES handbook

Contents

1. 1 11 2 EPROM PROGRAM MEMORY 15 3S DATA EEPROM eec Pr 16 3 1 1 0 1 16 9 2 MAINFEATURES sh kadenge ox RES eee ade 16 3 8 MEMORY ACCESS 17 34 POWER SAVING MODES ERES 18 35 ACCESS ERROR HANDLING 2 4 18 36 REGISTER 19 4 CENTRAL PROCESSING UNIT 20 41 NITRODUCTION mra 20 42 MAIN FEATURES t ee UR e 20 4 3 HEGISTEHS 20235 dns Deoa Egan RO DR AC a s 20 5 SUPPLY RESET AND CLOCK MANAGEMENT 23 51 LOW VOLTAGE DETECTOR 24 5 2 RESET SEQUENCE MANAGER 25 5 2 1 Introd ction e 25 5 2 2 Asynchronous External RESET pin 26 5 2 3 Internal Low Voltage Detection RESET 26 5 2 4 Internal Watchdog RESET 26 53 LOW CONSUMPTION OGCILLATOR sn 27 6 INTERRUPTS uie RR xe egere a
2. 53 10 26 ur e De 53 10 3 PWM AUTO RELOAD TIMER 54 10 3 1 Introduction ALE d Ee EE E 54 10 3 2 Furictiorial Description ke BRS RE Ar been 55 10 3 3 Register Description 58 10 4 1G BI EE 61 10 4 1 Introduction asia erati a 61 10 4 2 Features eme 64 io wha Xe RS Ad ce RR 61 10 4 3 Functional Description 61 10 4 4 Low Power Modes 73 10 4 5 Interr ptS iu des RR CER oem Ron E ae CR ahs e 73 10 4 6 Summary of Timer modes 73 10 4 7 Register Description 74 10 5 SERIAL PERIPHERAL INTERFACE SPI 79 10 5 1 ache eR APR RR BR RR 79 10 5 2 cscs s RODA UR e eo E 79 10 5 3 General 79 10 5 4 Functional Description 1 81 1055 Low Power Modes ue emper ER RT Kon a wt
3. 132 12 2 3 Thermal Characteristics 132 12 8 OPERATING CONDITIONS 1 133 12 3 1 General Operating Conditions 133 12 3 2 Operating Conditions with Low Voltage Detector LVD 134 12 4 SUPPLY CURRENT CHARACTERISTICS 135 12 4 1 RUN SLOW Modes 1 135 12 4 2 WAIT SLOW WAIT Modes 136 4 164 7 ST72311R ST72511R ST72512R ST72532R 12 4 3 HALT and ACTIVE HALT Modes 137 12 4 4 Supply and Clock 5 137 12 4 5 On Chip Peripheral 2 525542 piai a mi p ma Be SEN 137 12 5 CLOCK AND TIMING CHARACTERISTICS 138 1254 General Timings d Meek are edema 138 12 5 2 External Clock Source 138 12 5 3 Crystal Ceramic Resonator Oscillators 138 12 6 MEMORY CHARACTERISTICS 139 12 6 1 RAM and Hardware Registers 139 12 6 2 EEPROM Data Memory 139 12 6 3 EPROM Program Memory said see Moons RE ER EEN NE ca
4. 152 13 PACKAGE CHARACTERISTICS 154 131 PACKAGE MECHANICAL DATA 154 13 2 THERMAL 5 155 13 3 SOLDERING AND GLUEABILITY 156 13 4 PACKAGE SOCKET FOOTPRINT PROPOSAL 157 14 DEVICE CONFIGURATION AND ORDERING INFORMATION 158 14a OPTIONIBVIES e rex Ra CE ev ES a ee ea eae ew batted 158 14 2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE 159 14 8 DEVELOPMENT OO 161 15 ST7 GENERIC APPLICATION NOTE 162 16 SUMMARY OF CHANGES 163 5 5 164 ST72311R ST72511R ST72512R ST72532R 1 GENERAL DESCRIPTION 1 1 INTRODUCTION The ST72311R ST72511R 577251298 and ST72532R devices are members of the ST7 mi crocontroller family They can be grouped as fol lows ST725xxR devices are designed for mid range applications with a CAN bus interface Controller Area Network ST72311R devices target the same range of ap plications but without CAN interface All devices are based on a common industry standard 8 bit core featuring an enhanced instruc tion set Figure 1 Device Block Diagram 8 BIT CORE ALU CONTROL
5. 5 1 5 RECEIVER 97 164 ST72311R ST72511R 577 25127 ST72532R SERIAL COMMUNICATIONS INTERFACE Cont d 10 6 4 4 Conventional Baud Rate Generation The baud rate for the receiver and transmitter Rx and Tx are set independently and calculated as follows fopu Rx 32 PR TR 32 with PR 1 3 4 13 see SCPO amp 5 1 bits TR 1 2 4 8 16 32 64 128 see SCTO SCT1 amp SCT2 bits RR 1 2 4 8 16 32 64 128 see SCRO SCR1 amp SCR2 bits All this bits are in the BRR register Example If is 8 MHz normal mode and if PR 13 and TR RR 1 the transmit and receive baud rates are 19200 baud Note the baud rate registers MUST NOT be changed while the transmitter or the receiver is en abled 10 6 4 5 Extended Baud Rate Generation The extended prescaler option gives a very fine tuning onthe baud rate using a 255 value prescal er whereas the conventional Baud Rate Genera tor retains industry standard software compatibili ly The extended baud rate generator block diagram is described in the Figure 54 The output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the ERPR or the ETPR register Note the extended prescaler is activated by set ting the ETPR or ERPR register to a value other 98 164 than zero The baud rate
6. ve te enun et tem aote n e 42 8 5 1 Register Description eR ehe den ed ador wale EE Rae EORR 43 9 MISCELLANEOUS REGISTERS 45 l O PORT INTERRUPT SENSITIVITY ERR AE ead ees 45 9 2 PORT ALTERNATE FUNCTIONS 45 9 9 MISCELLANEOUS REGISTERS at eb NNN tad 46 10 PERIPHERALS bu RI ee 49 101 WATCHDOG TIMER WDG menns emo seed ene RR Eb 49 10 1 1 Introducnon 49 Main Features POs 49 10 1 3 Functional Description yamie eek AE 49 10 1 4 Hardware Watchdog Option 50 10 15 Low Power MOTOS bee Xx EUR hx 50 10 1 6 ntert pts x sz 50 10 1 7 Register Description iusso iL RR Enc ch dE Y x eee ees 50 10 2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER MCC RTO 52 10 2 1 Programmable CPU Clock Prescaler 52 10 2 2 Clock out Capability 52 10 2 3 Real Time Clock Timer RTC 52 10 2 4 Register Description uso Reno see Roe anu e ee ees 53 10 2 5 Low Power Modes
7. 191519 o L5 89 164 ST72311R ST72511R ST72512R ST72532R SERIAL PERIPHERAL INTERFACE Cont d STATUS REGISTER SR Read Only Reset Value 0000 0000 00h 7 0 Bit 7 SPIF Serial Peripheral data transfer flag This bit is set by hardware when a transfer has been completed An interrupt is generated if SPIE 1 in the CR register It is cleared by a soft ware sequence an access to the SR register fol lowed by a read or write to the DR register 0 Data transfer is in progress or has been ap proved by a clearing sequence 1 Data transfer between the device and an exter nal device has been completed Note While the SPIF bit is set all writes to the DR register are inhibited Bit 6 WCOL Write Collision status This bit is set by hardware when a write to the DR register is done during a transmit sequence It is cleared by a software sequence see Figure 50 0 No write collision occurred 1 A write collision has been detected Bit 5 Unused Bit 4 Mode Fault flag m This bit is set by hardware when the SS pin is pulled low in master mode see Section 10 5 4 5 Master Mode Fault on page 85 An SPI interrupt can be generated if SPIE 1 in the CR register This bit is cleared by a software sequence An ac cess to the SR register while MODF 1 followed by a write to the CR register 0 No master mode fault detected 1 A fault in master mode has been detected Bits
8. IST Lag tor SINT pisci Lm Lm noone _ ESCHER noen _ ESCHER ES EECHER n arco 2 17 fe ES ES fe amoro uses II aeren reiege ESCHER 1 129 164 ST72311R ST72511R ST72512R ST72532R INSTRUCTION SET OVERVIEW Cont d Bessnion WEG wee scm wor Fon onoeaion mr Je Lm Ene meras mS rome etme oho ma Emo fot antine m 6 won O mr sw paoe merge sa ea smenuse ____ ou sm enra ocase en Fs ars Ass en omar swine Pine 130 164 7572 12 ELECTRICAL CHARACTERISTICS 12 1 PARAMETER CONDITIONS Unless otherwise specified all voltages are re ferred to Vgg 12 1 1 Minimum and Maximum values Unless otherwise specified the minimum and max imum values are guaranteed in the worst condi tions of ambient te
9. Note The number of pins AND the channel selec tion varies according to the device Refer to the de vice pinout r Bit 7 0 D 7 0 Analog Converted Value This register contains the converted analog value in the range 00h to FFh Note Reading this register reset the COCO flag 123 164 ST72311R ST72511R ST72512R ST72532R 8 BIT A D CONVERTOR Cont d Table 24 ADC Register Map and Reset Values Address Register 7 Hex Label ADCDR D7 ER Reset Value 0 ADCCSR 0071h Standard Reset Value 4 124 164 ST72311R ST72511R ST72512R ST72532R 11 INSTRUCTION SET 11 1 ST7 ADDRESSING MODES so most of the addressing modes may be subdi lled hort The ST7 Core features 17 different addressing in Wo SUD odes ca Swor modes which can be classified in 7 main groups Long addressing mode is more powerful be cause itcan use the full 64 Kbyte address space Addressing Mode Example however it uses more bytes and more CPU cy cles Short addressing mode is less powerful because it can generally only access page zero 00001 s OOFFh range but the instruction size is more compact and faster All memory to memory in A 55 X structions use short addressing modes only CLR CPL NEG BSET p The ST7 Assembler optimizes the use of long and short addressing modes The ST7 Instruction set is designed to minimize the num
10. OCRx FFh 56 164 3 ST72311R ST72511R ST72512R ST72532R PWM AUTO RELOAD TIMER Cont d Output compare and Time base interrupt On overflow the OVF flag of the CSR register is set and an overflow interrupt request is generated if the overflow interrupt enable bit OIE in the CSR register is set The OVF flag must be reset by the user software This interrupt can be used as a time base in the application External clock and event detector mode Using the fgxr external prescaler input clock the auto reload timer can be used as an external clock event detector In this mode the ARR register is used to select the neyeynt number of events to be counted before setting the OVF flag Nevent 256 ARR When entering HALT mode while 1 is selected all the timer control registers are frozen but the counter continues to increment If the OIE bit is set the next overflow of the counter will generate an interrupt which wakes up the MCU Figure 34 External Event Detector Example 3 counts fext fcoUNTER ee ARR FDh 1 LI COUNTER INTERRUPT IF 1 CSR READ V CSR READ INTERRUPT IF OIE 1 57 164 ST72311R ST72511R ST72512R ST72532R PWM AUTO RELOAD TIMER Cont d 10 3 3 Register Description CONTROL STATUS REGISTER CSR Read Write Reset Value 0000 0000 00h COUNTER ACCESS REGISTER CAR Read Write Reset Value 0000 0000 00h 7 0 7 0 Bit 7 EXCL Extern
11. ___________ 122 10 8 6 Register Description 123 11 INSTRUCTIONSET eek eee xx wee er s pF 125 11 1 577 ADDRESSING MODES 125 14 1 4 Inherent 5e seb dane AN 126 11 12 Immediate RE Y UE dames 126 11 13 DCC quo 126 11 1 4 Indexed No Offset Short Long 126 111 5 Indirect Short Long eed ond AE ee ee ea 126 11 1 6 Indirect Indexed Short Long 127 11 1 7 Relative mode Direct Indirect 127 11 2 INSTRUCTION GROUPS 1 128 12 ELECTRICAL CHARACTERISTICS 131 12 1 PARAMETER 1 131 12 1 1 Minimum and Maximum values 131 12 1 2 Typical values SA 131 12 1 3 Typical a ses RR E eS bx deed RR UE RR RN 131 12 1 4 Loading capacitor 131 12 1 5 Pin input voltage 131 12 2 ABSOLUTE MAXIMUM RATINGS 132 12 2 1 Voltage Characteristics 132 12 2 2 Current Characteristics
12. Main Supply Voltage Digital Ground Voltage Timer Output 2 XTX Timer Output Compare 1 __ 2 Input X X PotC8 Time Input Capture 1 H X X oc SPI astern Slave Gut Dara x x X SPI Master out Sive In Data Px x Pon C7 SP Stave Select aet on Dres T TX DECIR xps T XT p e e rT _ Port 6 Must be tied low in user mode In programming mode when available this pin acts as the pro gramming voltage input Vpp Top priority non maskable interrupt active low Not Connected SR E 4 1 EE External clock mode input pull up or crystal ce ramic resonator oscillator inverter output External clock input or crystal ceramic resona tor oscillator inverter input 9 164 ST72311R ST72511R ST72512R ST72532R function PEDTOO x Pon 89 Sor Trane Data out CLE PE S6 Receive Dare n io 6r x GAN Transmit Data vol er es CAN Receive Daa Notes 1 In the interrupt input column eiX defines the associated
13. 88 10 5 6 lu e CEET 88 10 5 7 Register ANE Rem EE EE ieee de 89 3 164 ST72311R ST72511R ST72512R ST72532R 10 6 SERIAL COMMUNICATIONS INTERFACE 50 92 10 621 INMOGUCIION eege xs x nep quite eed ear tenue x om x Ko is atc ind 92 10 6 2 bx 92 10 6 3 General Description 92 10 6 4 Functional Description 94 10 6 5 Low Power Modes eas 99 10 6 6 Initerr pts edes e m _______ et hak 99 10 6 7 Register Description 100 10 7 CONTROLLER AREA NETWORK 104 10 7 1 Introduction eer PR deg 104 10 7 2 Main Features borea bes E EELER ea 105 10 7 3 Functional Description 4 105 10 7 4 Register Description 111 10 8 8 BIT A D CONVERTER ADC 121 10 8 1 Introd Cllr ce cx S 121 10 8 2 Main Features a dre RU RUE E AUR 121 10 8 3 Functional Description piede Re REPRE pee eed 121 10 8 4 Low Power Modes 122 10 8 5 Int rrupts
14. and Vgga pins are not available on the pinout the ADC refer to Vpp and Vss 3 Any added external serial resistor will downgrade the ADC accuracy especially for resistance greater than 10kQ Data based on characterization results not tested in production 4 The stabilization time of the AD converter is masked by the first hoan The first conversion after the enable is then always valid 4 152 164 ST72311R ST72511R ST72512R ST72532R ADC CHARACTERISTICS Cont d ADC Accuracy with Vpp 5 0V Symbol Fame ______ Conditions Win Unit Differential linearity error Integral linearity error Figure 92 ADC Accuracy Characteristics Digital Result ADCDR 255 1 Example of an actual transfer curve 2 The ideal transfer curve 254 3 End point correlation line 253 Er Total Unadjusted Error maximum deviation between the actual and the ideal transfer curves Eo Offset Error deviation between the first actual transition and the first ideal one Eg Gain Error deviation between the last ideal transition and the last actual one Ep Differential Linearity Error maximum deviation between actual steps and the ideal one E Integral Linearity Error maximum deviation between any actual transition and the end point 1 1 1 D 1 1 1 1 1 1 1 1 1 1 1 h correlation line 1 1 444 Vin LSBipgAD 253 254 255 256 DDA Notes 1 Data based on characterization results
15. drain output 0 PA3 PB4 PB3 PF2 without pull up on 9 Posting interup input 9 opendmouput 9 True Open Drain Ports 7 6 floating input 0 open high sink ports Pull up Input Port CANTX requirement PE2 pull up input 41 164 ST72311R ST72511R ST72512R ST72532R PORTS 8 4 LOW POWER MODES 8 5 INTERRUPTS The external interrupt event generates an interrupt e if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in CAUSE SE vice LO EXI MOUS the CC register is not active RIM instruction No effect on I O ports External interrupts cause the device to exit from HALT mode Interrupt Event External interrupt on selected external event Table 11 Port Configuration ne woe Se Port E EE Port F Note when the CANTX alternate function is selected the IO port operates in output push pull mode 3 42 164 PORTS Cont d 8 5 1 Register Description DATA REGISTER DR Port x Data Register PxDR with x A B C D E or F Read Write Reset Value 0000 0000 00h 7 0 ST72311R ST72511R ST72512R ST72532R OPTION REGISTER OR Port x Option Register PxOR with D E or F Read Write Reset Value 0000 0000 00h 7 0 Bit 7 0 D 7 0 Data register 8 bits The DR register has
16. 5 722308611 ST72311R ST72511R 77 51725128 ST72532R 8 MCU WITH NESTED INTERRUPTS EEPROM ADC 16 BIT TIMERS 8 BIT PWM ART SPI SCI CAN INTERFACES DATASHEET m Memories 16K to 60K bytes A ROM OTP and EPROM with read out KE 256 bytes E7PROM Data memory only on ST72532R4 1024 to 2048 bytes RAM m Clock Reset and Supply Management Enhanced reset system Low voltage supply supervisor Clock sources crystal ceramic resonator os cillator or external clock Beep and Clock out capability 4 Power SCH Modes Halt Active Halt Wait and Slow Interrupt Management Nested interrupt controller 13 interrupt vectors plus TRAP and RESET TQFP64 14 x 14 m 3 Communications Interfaces SPI synchronous serial interface SCI asynchronous serial interface 15 external interrupt lines on 4 vectors CAN interface except on ST72311Rx TLI dedicated top level interrupt pin 1 Analog peripheral Ports mE 8 51 ADC with 8 input channels 48 multifunctional bidirectional I O lines Instruction Set 32 alternate function lines 12 high sink outputs m 5 Timers Configurable watchdog timer Real time clock timer 8 bit data manipulation 63 basic instructions 17 main addressing modes 8 8 unsigned multiply instruction True bit manipulation One 8 bit auto reload
17. 0 ICIEJOCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL 1 Bit 7 ICIE nput Capture Interrupt Enable 0 Interrupt is inhibited 1 timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set Bit 6 OCIE Output Compare Interrupt Enable 0 Interrupt is inhibited 1 A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set Bit 5 TOIE Timer Overflow Interrupt Enable 0 Interrupt is inhibited 1 timer interrupt is enabled whenever the TOF bit of the SR register is set 74 164 Bit 4 FOLV2 Forced Output Compare 2 This bit is set and cleared by software 0 No effect on the OCMP2 pin 1 the OLVL2 bit to be copied to the 2 pin if the OC2E bit is set and even if there is no successful comparison Bit 3 FOLV1 Forced Output Compare 1 This bit is set and cleared by software 0 No effect on the 1 pin 1 Forces OLVL 1 to be copied to the 1 pin if the OC1E bit is set and even if there is no suc cessful comparison Bit 2 OLVL2 Output Level 2 This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R reg ister and is set in the CR2 register This val ue is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode Bit 1 IEDG1 nput Edge 1 This bit determines which type of level transition on the pin will trigger the capture 0 A falling e
18. Power On RESET Voltage Drop RESET The device RESET pin acts as an output that is pulled low when Vpp Vir rising edge or falling edge as shown in Figure 13 The LVD filters spikes on Vpp larger than to avoid parasitic resets 5 2 4 Internal Watchdog RESET The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 13 Starting from the Watchdog counter underflow the device RESET pin acts as an output that is pulled low during tw RSTL out CAUTION this output signal as not enought ener gy to be used to drive external devices WATCHDOG RESET SHORT EXT RESET DELAY E WATCHDOG UNDERFLOW 4 INTERNAL 4096 Topu FETCH VECTOR 4 ST72311R ST72511R ST72512R ST72532R 5 3 LOW CONSUMPTION OSCILLATOR The fosc main clock of the ST7 be generated Table 4 517 Clock Sources by two different source types y We Hardware Configuration an external source m acrystal ceramic resonator oscillators The associated hardware configuration are shown ST7 in Table 4 Refer to the electrical characteristics 0501 0 2 section for more details External Clock Source In this external clock mode a clock signal Square EXTERNAL sinus or triangle with 50 duty cycle has to drive SOURCE the OSC1 pin while the OSC2 pin is tied to ground ST7 0 1 OSC2 L Crystal Ceramic Oscillator This oscillator based on c
19. REES Leen sl Generated reset puse duran Watchdog resersouce 1 f e ESCH Figure 86 Typical Application with RESET 5 ST72XXX INTERNAL RESET CONTROL EXTERNAL RESET CIRCUIT WATCHDOG RESET LVD RESET 12 9 2 Vpp Pin Subject to general operating condition for fosc and unless otherwise specified Symbol LEE LIST vu ow level voltage Vi high level voltage ______________ 026 1 Unless otherwise specified typical data are based on 25 and Vpp 5V Figure 87 Two typical Applications with Vpp Pin Vpp ST72XXX 2 Data based on characterization results not tested in production 3 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested 4 The Ron pull up equivalent resistor is based on a resistive transistor This data is based on characterization results not tested in production 5 The reset network protects the device against parasitic resets especially in a noisy environment 6 Data based on design simulation and or technology characteristics not tested in production 7 When the in circuit programming mode is not required by the application Vpp pin must be tied to Vss Notes 437 147 164 ST72311R ST72511R ST72512R ST72532R 12 10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating condition for Vpp fo Refer to I O port characteristics for more details on
20. Supply current in RUN mode 3 see Figure 69 Supply current in SLOW mode 4 see Figure 70 3 lt lt 3 6 4 5 lt lt 5 5 Figure 69 Typical Ipp in RUN vs Figure 70 Typical Ipp SLOW vs feu IDD 20 Notes 1 Typical data are based on 25 Vpp 5V 4 5V lt Vpps5 5V range and Vpp 3 3V 3 lt lt 3 6 range 2 Data based on characterization results tested in production at Vpp max and 3 CPU running with memory access all I O pins in input mode with a static value at Vpp or no load all peripherals switched off clock input OSC1 driven by external square wave LVD disabled 4 SLOW mode selected with fopy based on fogc divided by 32 All I O pins in input mode with a static value at Vpp or Vss no load all peripherals switched off clock input OSC1 driven by external square wave LVD disabled 437 135 164 ST72311R ST72511R ST72512R ST72532R SUPPLY CURRENT CHARACTERISTICS Cont d 12 4 2 WAIT and SLOW WAIT Modes Sym e fosc 1MHz fopy 500kHz 1 25 fosc 4MHz fcpy 2MHz 3 2 fosc 16MHZ fopy 8MHz 5 2 Supply current in WAIT mode 3 see Figure 71 fogc 1MHz fopy 31 25kHz fosc 4M Hz fcpu 1 25kHz fosc 16MHz fcpy 500kHz fosc 1 MHz 500 2 fosc 4MHz 2 2 fosc 1 6MHz fcpy 8MHz fosc 1 MHz fcpy 31 25kHz fogc 4MHz fopy 125kHz fosc 1 6MHz 500 2 Supply current in
21. CENTRAL PROCESSING UNIT Cont d Condition Code Register CC Read Write Reset Value 111x1xxx The 8 bit Condition Code register contains the in terrupt masks and four flags representative of the result of the instruction just executed This register can also be handled by the PUSH and POP in structions These bits can be individually tested and or con trolled by specific instructions Arithmetic management bits Bit 4 H Half carry This bit is set by hardware when a carry occurs be tween bits 3 and 4 of the ALU during an ADD or ADC instructions It is reset by hardware during the same instructions 0 No half carry has occurred 1 An half carry has occurred This bit is tested using the JRH or JRNH instruc tion The H bit is useful in BCD arithmetic subrou tines Bit 2 N Negative This bit is set and cleared by hardware It is repre sentative of the result sign of the last arithmetic logical or data manipulation It s a copy of the re sult 7 bit 0 The result of the last operation is positive or null 1 The result of the last operation is negative i e the most significant bit is a logic 1 This bit is accessed by the JRMI and JRPL instruc tions ST72311R ST72511R ST72512R ST72532R Bit 1 2 Z Zero This bit is set and cleared by hardware This bit in dicates that the result of the last arithmetic logical or data manipulation is zero 0 The result of the last operation is
22. defines the location of the sample point It includes the PROP SEG and PHASE SEG ofthe CAN standard Its duration is programmable between 1 and 16 time quanta but may be automatically lengthened to compen sate for positive phase drifts due to differences in the frequency of the various nodes of the net work Bit segment 2 BS2 defines the location of the transmit point It represents the PHASE SEG2 of the CAN standard Its duration is programma ble between 1 and8 time quanta but may also be automatically shortened to compensate for neg ative phase drifts Figure 59 Bit Timing The resynchronization jump width RJW defines an upper bound to the amount of lengthening or shortening of the bit segments It is programmable between 1 and 4 time quanta A valid edge is defined as the first transition in a bit time from dominant to recessive bus level provid ed the controller itself does not send a recessive bit If a valid edge is detected in BS1 instead of SYNC SEG BS1 is extended by up to RJW so that the sample point is delayed Conversely if a valid edge is detected in BS2 in stead of SYNC SEG BS2 is shortened by up to RJW so that the transmit point is moved earlier As a safeguard against programming errors the configuration of the Bit Timing Register is only possible while the device is in STANDBY mode NOMINAL BIT TIME BIT SEGMENT 1 BS1 110 164 BIT SEGMENT 2 BS2 SAMPLE POINT TRAN
23. 79 164 ST72311R ST72511R ST72512R ST72532R SERIAL PERIPHERAL INTERFACE Cont d Figure 47 Serial Peripheral Interface Block Diagram Internal Bus IT request ite E SPI STATE ES T SS Em FX ER FX SERIAL CLOCK GENERATOR 80 164 137 SERIAL PERIPHERAL INTERFACE Cont d 10 5 4 Functional Description Figure 46 shows the serial peripheral interface SPI block diagram This interface contains 3 dedicated registers A Control Register CR A Status Register SR A Data Register DR Refer to the CR SR and DR registers in Section 10 5 7for the bit definitions 10 5 4 1 Master Configuration In a master configuration the serial clock is gener ated on the SCK pin Procedure Select the SPRO amp SPR1 bits to define the se rial clock baud rate see CR register Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock see Figure 49 The 55 pin must be connected to a high level signal during the complete byte transmit se quence The MSTR and SPE bits must be set they re main set only if the SS pin is connected to a high level signal ST72311R ST72511R ST72512R ST72532R In this configuration the MOSI pin is a data output and to the MISO pin is a data input Transmit sequence The transmit sequence begins when a byte is writ ten the DR register The data byte i
24. OCMP2 A PF3 HS 20 high sink capability eix associated external interrupt vector 7 164 ST72311R ST72511R ST72512R ST72532R PIN DESCRIPTION Cont d For external pin connection guidelines refer to Section 12 ELECTRICAL CHARACTERISTICS on page 131 Legend Abbreviations for Table 1 Type input output 5 supply Input level A Dedicated analog input In Output level CMOS 0 3Vpp 0 7Vpp CMOS 0 3Vpp 0 7Vpp with input trigger Output level HS 20mA high sink on N buffer only Port and control configuration Input float floating wpu weak pull up int interrupt analog Output OD open drain 2 PP push pull Refer to Section 8 PORTS page 38 for more details on the software configuration of the I O ports The RESET configuration of each is shown in bold This configuration is valid as long as the device is in reset state Table 1 Device Pin Description bevel pn Alternate function ew x x xps x pwwouw2 xf Pon t X x Pot es x Jes x Pot e PWHEART extemal Cio SS x x em CS X X X roroo ADC Analog TnputO X X X Por bi X X
25. ST72532R 12 8 PORT PIN CHARACTERISTICS 12 8 1 General Characteristics Subject to general operating condition for Vpp fosc and T4 unless otherwise specified a LT mp Mm PT 1222777 E Ed curent State current consumption 7 Feating input mode 200 _ Eeer E REESE BERENS NU Output low to high level rise time Between 10 and 90 Bema mert peime __ ___ ST72XXX UNUSED I O PORT UNUSED I O PORT ST72XXX Notes 1 Unless otherwise specified typical data are based 25 and Vpp 5V 2 Data based on characterization results not tested in production 3 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested 4 Configuration not recommended all unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor see Figure 82 Data based on design simulation and or technology characteristics not tested in production 5 The pull up equivalent resistor is based on resistive transistor This data is based on characterization results not tested in production 6 To generate an external interrupt a minimum pulse width has to be applied on an port pin configured as an external interrupt source 145 164 ST72311R ST72511R
26. is rising when is falling The LVD function is illustrated in Figure 10 Provided the minimum Vpp value guaranteed for the oscillator frequency is below Vr the MCU can only be in two modes Figure 10 Low Voltage Detector vs Reset under full software control in static safe reset In these conditions secure operation is always en sured for the application without the need for ex ternal reset hardware During a Low Voltage Detector Reset the RESET pin is held low thus permitting the MCU to reset other devices Notes The LVD allows the device to be used without any external RESET circuitry The LVD is an optional function which can be se lected when ordering the device ordering informa tion 24 164 4 5 2 SEQUENCE MANAGER RSM 5 2 1 Introduction The reset sequence manager includes three RE SET sources as shown in Figure 12 External RESET source pulse Internal LVD RESET Low Voltage Detection Internal WATCHDOG RESET These sources act on the RESET pin and it is al ways kept low during the delay phase The RESET service routine vector is fixed at ad dresses FFFEh FFFFh in the ST7 memory map The basic RESET sequence consists of 3 phases as shown in Figure 11 Delay depending on the RESET source 4096 CPU clock cycle delay RESET vector fetch Figure 12 Reset Block Diagram ST72311R ST72511R ST72512R ST72532R The 4096 CPU cloc
27. the software write will be unsuccessful Write collisions can occur both in master and slave mode Note a read collision will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU oper ation In Slave mode When the CPHA bit is set The slave device will receive a clock SCK edge prior to the latch of the first data transfer This first clock edge will freeze the data in the slave device DR register and output the MSBit on to the exter nal MISO pin of the slave device The SS pin low state enables the slave device but the output of the MSBit onto the MISO pin does not take place until the first data transfer clock edge ST72311R ST72511R ST72512R ST72532R When the CPHA bit is reset Data is latched on the occurrence of the first clock transition The slave device does not have any way of knowing when that transition will occur therefore the slave device collision occurs when software attempts to write the DR register after its SS pin has been pulled low For this reason the SS pin must be high between each data byte transfer to allow the CPU to write in the DR register without generating a write colli sion In Master mode Collision in the master device is defined as a write of the DR register while the internal serial clock SCK is in the process of transfer The SS pin signal must be always high on the master device WCOL bit The WCOL
28. 2550580 121 164 ST72311R ST72511R ST72512R ST72532R 8 BIT A D CONVERTER ADC Cont d 10 8 3 2 Digital A D Conversion Result The conversion is monotonic meaning that the re sult never decreases if the analog input does not and never increases if the analog input does not If the input voltage is greater than or equal to Vppa high level voltage reference then the conversion result in the DR register is FFh full scale without overflow indication If input voltage Vain is lower than or equal to Vssa low level voltage reference then the con version result in the DR register is OOh The A D converter is linear and the digital result of the conversion is stored in the ADCDR register The accuracy of the conversion is described in the parametric section Rain is the maximum recommended impedance for an analog input signal If the impedance is too high this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time 10 8 3 3 A D Conversion Phases The A D conversion is based on two conversion phases as shown in Figure 63 m Sample capacitor loading duration During this phase the input voltage to be measured is loaded into the sample capacitor m A D conversion duration During this phase the A D conversion is computed 8 successive approximations cycles and the Capc sample capacitor is disconnected from the analo
29. 3 0 Unused 90 164 DATA I O REGISTER DR Read Write Reset Value Undefined 7 0 os oe The DR register is used to transmit and receive data on the serial bus In the master device only a write to this register will initiate transmission re ception of another byte Notes During the last clock cycle the SPIF bit is set a copy of the received data byte in the shift register is moved to a buffer When the user reads the serial peripheral data I O register the buffer is actually being read Warning A write to the DR register places data directly into the shift register for transmission A write to the the DR register returns the value lo cated in the buffer and not the contents of the shift register See Figure 47 4 ST72311R ST72511R ST72512R ST72532R SERIAL PERIPHERAL INTERFACE Table 21 SPI Register Map and Reset Values Address Register Hex Label SPIDR MSB Reset Value aes SPICR SE SE 0022h Reset Value SPISR SPIF WCOL MODF 91 164 ST72311R ST72511R ST72512R ST72532R 10 6 SERIAL COMMUNICATIONS INTERFACE SCI 10 6 1 Introduction The Serial Communications Interface SCI offers a flexible means of full duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format The SCI of fers a very wide range of baud rates using two baud rate generat
30. 577 and E PROM TO GET MORE INFORMATION To get the updated information on that product please refer to STMicroelectronics web server http st7 st com 4 162 164 ST72311R ST72511R ST72512R ST72532R 16 SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one Section 8 4 LOW POWER MODES on page 42 and Section 8 5 5 on page 42 added in Section 8 PORTS on page 38 Section 10 2 5 Low Power Modes on page 53and Section 10 2 6 Interrupts on page 53 added in Section 10 2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER MCC RTC on page 52 ESD absolute maximum rating modified in Section 12 2 on page 132 EMC characteristics corrected in Section 12 7 on page 140 163 164 ST72311R ST72511R 87725128 ST72532R Notes Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of useof such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied S TMicroelectronics products are not authorized for use as critical component
31. AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode On the contrary only external and other specified interrupts allow the processor to exit the HALT modes see column Exit from HALT in Interrupt Mapping table When several pending interrupts are present while exiting HALT mode the first one serviced can only be an inter rupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 15 Note If an interrupt that is not able to Exit from HALT mode is pending with the highest priority when exiting HALT mode this interrupt is serviced after the first one serviced Figure 16 Concurrent interrupt management 30 164 6 4 CONCURRENT amp NESTED MANAGEMENT The following Figure 16 and Figure 17 show two different interrupt management modes The first is called concurrent mode and does not allow an in terrupt to be interrupted unlike the nested mode in Figure 17 The interrupt hardware priority is given in this order from the lowest to the highest MAIN IT4 113 IT2 IT1 ITO TLI The software priority is given for each interrupt Warning A stack overflow may occur without no tifying the software of the failure SOFTWARE PRIORITY L LEVEL D 1 1 1 1 1 1 N gt lt N e 22 SOFTWARE PRIORITY 20 BYTES woo o C USED STACK 4 INTERRUPTS Cont d 6 5
32. CPU I 1 0 BITS OSCILLATOR ON PERIPHERALS ON CPU ON I 1 0 BITS XX 4 FETCH RESET VECTOR OR SERVICE INTERRUPT Notes 1 WDGHALT is an option bit See option byte sec tion for more details 2 Peripheral clocked with an external clock source can still be active 3 Only some specific interrupts can exit the MCU from HALT mode such as external interrupt Re fer to Table 7 Interrupt Mapping page 32 for more details 4 Before servicing an interrupt the CC register is pushed on the stack The 1 1 0 bits of the CC reg ister are set to the current software priority level of the interrupt routine and recovered when the CC register is popped 37 164 ST72311R ST72511R ST72512R ST72532R 8 PORTS 8 1 INTRODUCTION The ports offer different functional modes transfer of data through digital inputs and outputs and for specific pins external interrupt generation alternate signal input output for the on chip pe ripherals An port contains up to 8 pins Each pin can be programmed independently as digital input with or without interrupt generation or digital output 8 2 FUNCTIONAL DESCRIPTION Each port has 2 main registers Data Register DR Data Direction Register DDR and one optional register Option Register OR Each pin may be programmed using the corre sponding register bits in the DDR and OR regis ters bit X corresponding to pin
33. Single Master System A typical single master system may be configured using an MCU as the master and four MCUs as slaves see Figure 51 The master device selects the individual slave de vices by using four pins of a parallel port to control the four SS pins of the slave devices The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time thus disabling the slave devices Note To prevent a bus conflict on the MISO line the master allows only one active slave device during a transmission Figure 51 Single Master Configuration For more security the slave device may respond to the master with the received data byte Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are con nected and the slave has not written its DR regis ter Other transmission security methods can use ports for handshake lines or data bytes with com mand fields Multi master System A multi master system may also be configured by the user Transfer of master control could be im plemented using a handshake method through the ports or by an exchange of code messages through the serial peripheral interface system The multi master system is principally handled by the MSTR bit in the CR register and the bit in the SR register 87 164 57723118 ST72511R ST72512R ST72532R SERIAL PERIPHERAL INTERFACE Cont d 10 5 5 Low P
34. Table 12 I O Port Register Map and Reset Values ale LE CEET Hex Label 6 of IO port registers Ws 0006h PCOR 0008h PBDR ooon Pen Toe Peon 0011h 0015h PFDDR 4 44 164 9 MISCELLANEOUS REGISTERS The miscellaneous registers allow control over several features such as the external interrupts or the l Oalternate functions 9 1 I O PORT INTERRUPT SENSITIVITY The external interrupt sensitivity is controlled by the IPA IPB and ISxx bits of the Miscellaneous registers Figure 27 This control allows to have up to 4 fully independent external interrupt source sensitivities Each external interrupt source can be generated on four or five different events on the pin m Falling edge m Rising edge m Falling and rising edge m Falling edge and low level m Rising edge and high level only for ei0 and ei2 To guarantee correct functionality the sensitivity bits in the MISCR registers must be modified only when the 11 and 10 bits of the CC register are both set to 1 level 3 See I O port register and Miscel laneous register descriptions for more details on the programming Figure 27 External Interrupt Sources vs MISCR SOURCES MISCR2 IPA SOURCES MISCR2 IPB SOURCES ST72311R ST72511R ST72512R ST72532R 9 2 PORT ALTERNATE FUNCTIONS The MISCR registers allow to manage four I O port miscellaneous alternate functions Main cl
35. Threshold Versus Vand fosc for ROM devices 2 FUNCTIONALITY NOT GUARANTEED IN THIS AREA DEVICE UNDER RESET IN THIS AREA P FUNCTIONAL AREA SUPPLY VOLTAGE V Notes 1 LVD typical data are based on 25 They are given only as design guidelines and are not tested 2 The minimum rise time rate is needed to insure a correct device power on and LVD reset Not tested in production 134 164 4 ST72311R ST72511R ST72512R ST72532R 12 4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for vice consumption the two current values must be the ST7 functional operating modes over tempera added except for HALT mode for which the clock ture range does not take into account the clock is stopped source current consumption To get the total de Symb Condoms us Supply current variation vs temperature Constant and 12 4 1 RUN and SLOW Modes Ust 5 4 fosc 1 MHz fcpu 500kHz 2 fosc 4MHz 2 2 9 fosc 1 6MHz fcpy 8MHz 20 fosc 1MHz fcpu 31 25kHz 0 5 fosc 4MHz fopy 125kHz 2 0 fogc 16MHz 500 2 3 0 fosc 1MHz 500 2 2 4 fosc 4MHz 2 2 5 4 fosc 16MHz fopy 8MHz 12 fosc 1 MHz fcpu 31 25kHz fosc 4MHz fcpu 1 25kHz fosc 1 6MHz fcpu 500kHz Supply current in RUN mode 3 see Figure 69 Supply current in SLOW mode see Figure 70
36. Value CANBCSRx nos i id ar a 1103 Reset Value 120 164 3 10 8 8 BIT A D CONVERTER ADC 10 8 1 Introduction The on chip Analog to Digital Converter ADC pe ripheral is a 8 bit successive approximation con verter with internal sample and hold circuitry This peripheral has up to 16 multiplexed analog input channels refer to device pin out description that allow the peripheral to convert the analog voltage levels from up to 16 different sources The result of the conversion is stored in a 8 bit Data Register The A D converter is controlled through a Control Status Register 10 8 2 Main Features m 8 bit conversion Up to 16 channels with multiplexed input Linear successive approximation Data register DR which contains the results Conversion complete status flag bit to reduce consumption The block diagram is shown in Figure 62 Figure 62 ADC Block Diagram ST72311R ST72511R ST72512R ST72532R 10 8 3 Functional Description 10 8 3 1 Analog Power Supply VppA Vssa are the high and low level refer ence voltage pins In some devices refer to device pin out description they are internally connected to the Vss pins Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines See electrical characteristics section for more de tails ANALOG TO DIGITAL CONVERTER gt eee
37. Vpp fosc and T4 unless otherwise specified 12 6 1 RAM and Hardware Registers Data retention mode 1 HALT mode or RESET 12 6 2 EEPROM Data Memory t Programming time 40 CST lt 85 for 1 up to 16 bytes at time 40 lt lt 125 NEU Write erase cycles 3 25 300 000 12 6 3 EPROM Program Memory Symbor Parameter Conatons Typ Max Unit UV lamp is placed 1 inch Y from the device window terase Erase Time without any interposed s 20 filters Data retention EE Notes 1 Minimum Vpp supply voltage without losing data stored into RAM in in HALT mode or under RESET or into hardware registers only in HALT mode Guaranteed by construction not tested in production 2 The data retention time increase when the T4 decreases 3 Data based on reliability test results and monitored in production 4 Data given only as guidelines E 139 164 ST72311R ST72511R ST72512R ST72532R 12 7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba sis during product characterization 12 7 1 Functional EMS Electro Magnetic Susceptibility Based on a simple running application on the product toggling 2 LEDs through UO ports the product is stressed by two electro magnetic events until a failure occurs indicated by the LEDs m ESD Electro Static Discharge positive and negative is applied on all pins
38. X of the port The same correspondence is used for the DR register The following description takes into account the OR register for specific ports which do not pro vide this register refer to the Port Implementa tion section The generic I O block diagram is shown in Figure 25 8 2 1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit In this case reading the DR register returns the digital value applied to the external I O pin Different input modes can be selected by software through the OR register Notes 1 Writing the DR register modifies the latch value but does not affect the pin status 2 When switching from input to output mode the DR register has to be written first to drive the cor rect level on the pin as soon as the port is config ured as an output External interrupt function When an is configured as Input with Interrupt an event on this I O can generate an external inter rupt request to the CPU Each pin can independently generate an interrupt request The interrupt sensitivity is independently 38 164 programmable using the sensitivity bits in the Mis cellaneous register Each external interrupt vector is linked to a dedi cated group of I O port pins see pinout description and interrupt section If several input pins are se lected simultaneously as interrupt source these are logically ANDed For this reason if one of the interru
39. a frame integrity check for detecting bit errors r ST72311R ST72511R ST72512R ST72532R The acknowledgement ACK field comprises the ACK slot and the ACK delimiter The bit in the ACK slot is placed on the bus by the transmitter as a re cessive bit logical 1 It is overwritten as a domi nant bit logical 0 by those receivers which have at this time received the data correctly In this way the transmitting node can be assured that at least one receiver has correctly received its message Note that messages are acknowledged by the re ceivers regardless of the outcome of the accept ance test The end of the message is indicated by the End Of Frame EOF The intermission field defines the minimum number of bit periods separating con secutive messages If there is no subsequent bus access by any station the bus remains idle 10 7 3 2 Hardware Blocks The CAN controller contains the following func tional blocks refer to Figure 55 ST7 Interface buffering of the ST7 internal bus and address decoding of the CAN registers TX RX Buffers three 10 byte buffers for trans mission and reception of maximum length mes sages ID Filters two 12 bit compare and don t care masks for message acceptance filtering PSR page selection register see memory map BRPR clock divider for different data rates BTR bit timing register ICR interrupt control register ISR interrupt status reg
40. after data has been pushed onto the stack and incremented before data is popped from the stack see Figure 8 Since the stack is 256 bytes deep the 8 most sig nificant bits are forced by hardware Following an MCU Reset or after a Reset Stack Pointer instruc tion RSP the Stack Pointer contains its reset val ue the SP7 to SPO bits are set which is the stack higher address Figure 8 Stack Manipulation Example CALL Interrupt Subroutine Event Stack Higher Address 01FFh Stack Lower Address 0100h 22 164 The least significant byte of the Stack Pointer called S can be directly accessed by a LD in struction Note When the lower limit is exceeded the Stack Pointer wraps around to the stack upper limit with out indicating the stack overflow The previously stored information is then overwritten and there fore lost The stack also wraps in case of an under flow The stack is used to save the return address dur ing a subroutine call and the CPU context during an interrupt The user may also directly manipulate the stack by means of the PUSH and POP instruc tions In the case of an interrupt the PCL is stored at the first location pointed to by the SP Then the other registers are stored in the next locations as shown in Figure 8 When an interrupt is received the SP is decre mented and the context is pushed on the stack On return from interrupt the SP is incremented and the context is po
41. conversion resets the COCO bit and starts a new conversion Figure 63 ADC Conversion Timings ADCCSR WRITE OPERATION HOLD CONTROL LOAD L COCOBIT SET 10 8 4 Low Power Modes WAIT No effect on A D Converter A D Converter disabled After wakeup from Halt mode the A D Con HALT Kee verter requires a stabilisation time before curate conversions can be performed Note The A D converter may be disabled by reset ting the ADON bit This feature allows reduced power consumption when no conversion is needed and between single shot conversions 10 8 5 Interrupts None 3 8 BIT A D CONVERTER ADC Cont d 10 8 6 Register Description CONTROL STATUS REGISTER CSR Read Write Reset Value 0000 0000 00h ST72311R ST72511R ST72512R ST72532R DATA REGISTER DR Read Only Reset Value 0000 0000 00h 7 0 7 0 Bit 7 COCO Conversion Complete This bit is set by hardware It is cleared by soft ware reading the result in the DR register or writing to the CSR register 0 Conversion is not complete 1 Conversion can be read from the DR register Bit 6 Reserved must always be cleared Bit 5 ADON A D Converter On This bit is set and cleared by software 0 A D converter is switched off 1 A D converter is switched on Bit 4 Reserved must always be cleared Bit 3 0 CH 3 0 Channel Selection These bits are set and cleared by software They select the analog input to convert
42. in Figure 35 Note Some timer pins may not available not bonded in some ST7 devices Refer to the device pin out description When reading an input signal on a non bonded pin the value will always be 1 r ST72311R ST72511R ST72512R ST72532R 10 4 3 Functional Description 10 4 3 1 Counter The main block of the Programmable Timer is a 16 bit free running upcounter and its associated 16 bit registers The 16 bit registers are made up of two 8 bit registers called high amp low Counter Register CR Counter High Register CHR is the most sig nificant byte MS Byte Counter Low Register CLR is the least sig nificant byte LS Byte Alternate Counter Register ACR Alternate Counter High Register ACHR is the most significant byte MS Byte Alternate Counter Low Register ACLR is the least significant byte LS Byte These two read only 16 bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit Timer overflow flag located in the Status register SR see note at the end of paragraph titled 16 bit read sequence Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value Both counters have a reset value of FFFCh this is the only value which is reloaded in the 16 bit tim er The reset value of both counters is also FFFCh in One Pulse mode and PWM mode The timer clock depends
43. on the clock control bits of the CR2 register as illustrated in Table 18 Clock Control Bits The value in the counter register re peats every 131 072 262 144 or 524 288 CPU clock cycles depending on the CC 1 0 bits The timer frequency can be 2 fcpu 4 fep 8 or an external frequency 61 164 ST72311R ST72511R ST72512R ST72532R 16 BIT TIMER Cont d Figure 35 Timer Block Diagram ST7 INTERNAL BUS MCU PERIPHERAL INTERFACE OUTPUT OUTPUT INPUT COUNTER compare COMPARE CAPTURE CAPTURE REGISTER REGISTER REGISTER REGISTER REGISTER 2 1 2 ALTERNATE pin COUNTER A REGISTER CC 1 0 TIMER INTERNAL BUS mE an UT COMPARE DETECT an EDGE DETECT CIRCUIT2 LL LATCH tidy perd o 0 im 2 LATCH2 Status SR OVERFLOW DETECT CIRCUIT Control Register 1 CR1 Control Register 2 CR2 note TIMER INTERRUPT Note If IC OC and TO interrupt requests have separate vectors then the last OR is not present See device Interrupt Vector Table 62 164 4 16 BIT TIMER Cont d 16 bit read sequence from either the Counter Register or the Alternate Counter Register LS Byte is buffered Beginning of the sequence Read MS Byte r At t0 Other 7 instructions Read Returns the buffered At 10 At S Byte LS Byte value at t0 Sequence completed The user must read the MS Byte first then t
44. over the whole temperature range monitored in production 2 ADC Accuracy vs Negative Injection Current For 0 8 the typical leakage induced inside the die is 1 6 and the effect on the ADC accuracy is a loss of 1 LSB for each 10KQ increase of the external analog source impedance This effect on the ADC accuracy has been observed under worst case conditions for injection negative injection injection to an Input with analog capability adjacent to the enabled Analog Input at 5V Vpp supply and worst case temperature 153 164 ST72311R ST72511R ST72512R ST72532R 13 PACKAGE CHARACTERISTICS 13 1 PACKAGE MECHANICAL DATA Figure 93 64 Pin Thin Quad Flat Package m Pv Tr T T D pep p pee Far oos fors jooo Lo KLEES oso os norapors rore Pe feo aka ke fo For el RTE Pe xx Fer Teo i per peo Lk Pe foe T L3 Ft oss 0807507902405 rp pep Number of Pins N 64 16 NE 16 II Bee me ves pas me Pat pss PL CC Ke ozs 038 050 sso preoo re sso sos Fe oso a LIES
45. performance in terms of electrical sensitivity For more details re fer to the AN1181 ST7 application note 12 7 2 1 Electro Static Discharge ESD Electro Static Discharges 3 positive then 3 nega tive pulses separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends of the number of supply pins of the device 3 parts n 1 supply pin Two models are usually simulated Human Body Model and Machine Model This test conforms to the JESD22 A114A A115A standard See Figure 75 and the following test sequences Human Body Model Test Sequence C is loaded through S1 by the HV pulse gener ator 51 switches position from generator to Adischarge from C through R bogy resistance to the ST7 occurs 52 must be closed 10 to 100ms after the pulse delivery period to ensure the ST7 is not left in charge state S2 must be opened least 10ms prior to the delivery of the next pulse Absolute Maximum Symbol ST72311R ST72511R ST72512R ST72532R Machine Model Test Sequence is loaded through S1 by the HV pulse gener ator 51 switches position from generator to ST7 A discharge from C to the ST7 occurs S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST7 is not left in charge state S2 must be opened at least 10ms prior to the delivery of the next pulse R machine resistance in seri
46. pin is in low state during the start bit The TDO pin is in high state during the stop bit An Idle character is interpreted as an entire frame of 1 s followed by the start bit of the next frame which contains data A Break character is interpreted on receiving Oe for some multiple of the frame period At the end of the last break frame the transmitter inserts an ex tra 1 bit to acknowledge the start bit Transmission and reception are driven by their own baud rate generator Possible Parity Bit i Next Next Data Frame Start Start Start Idle Frame Bit Break Frame SCH 8 bit Word length M bit is reset Data Frame Start Bit Idle Frame Possible Next Data Frame Break Frame Extra i 94 164 3 SERIAL COMMUNICATIONS INTERFACE Cont d 10 6 4 2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status When the M bit is set word length is 9 bits and the 9th bit the MSB has to be stored in the T8 bit in the CR1 reg ister Character Transmission During an SCI transmission data shifts out least significant bit first on the TDO pin In this mode the DR register consists of a buffer TDR between the internal bus and the transmit shift register see Figure 52 Procedure Select the M bit to define the word length Selectthe desired baud rate using the BRR and the ETPR registers Setthe TE bit to assign the TDO pi
47. port pins do not accept positive injection 132 164 STA ST72311R ST72511R ST72512R ST72532R 12 3 OPERATING CONDITIONS 12 3 1 General Operating Conditions Vpp Supply voltage see Figure 66 and Figure 67 Vpp23 5V without EEPROM 07 16 Vpp24 5V with EEPROM MHz 1 Suffix Version 70 6 Suffix Version 40 85 6 Suffix Version 4 85 0 7 Suffix Version 3 Suffix Version FUNCTIONALITY GUARANTEE D IN THIS AREA FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR SUPPLY VOLTAGE V FUNCTIONALITY NOT GUARANTEED IN THIS AREA FOR TEMPERATURE HIGHER THAN 85 C FUNCTIONALITY GUARANTEE D IN THIS AREA FUNCTIONALITY NOT GUARANTEED IN THIS AREA 1 FUNCTIONALITY NOT GUARANTEE D IN THIS AREA WITH RESONATOR 1 SUPPLY VOLTAGE V Notes 1 Guaranteed by construction A D operation is not guaranteed below 1MHz 2 Operating conditions with 40 to 125 C 437 133 164 ST72311R ST72511R ST72512R ST72532R OPERATING CONDITIONS Cont d 12 3 2 Operating Conditions with Low Voltage Detector LVD Subject to general operating condition for Vpp fosc and T4 Symbol Parameter Conditons min Typ umi Reset release threshold Reset generation threshold g LVD votage threshoid hysteresis ICH Lt Vicon Or aveo Fitered delay on Voo Figure 68 LVD
48. register while RDRF 1 An interrupt is generated if RIE 1 in the CR2 reg ister It is cleared by hardware when RE 0 by a software sequence an access to the SR register followed by a read to the DR register 0 No Overrun error 1 Overrun error is detected Note When this bit is set RDR register content will not be lost but the shift register will be overwritten Bit 2 NF Noise flag This bit is set by hardware when noise is detected on a received frame It is cleared by hardware when RE 0 by a software sequence an access to the SR register followed by a read to the DR regis ter 0 No noise is detected 1 Noise is detected Note This bit does not generate interrupt as it ap pears at the same time as the RDRF bit which it self generates an interrupt Bit 1 FE Framing error This bit is set by hardware when a de synchroniza tion excessive noise or a break character is de tected It is cleared by hardware when RE 0 by a software sequence an access to the SR register followed by a read to the DR register 0 No Framing error is detected 1 Framing error or break character is detected Note This bit does not generate interrupt as it ap pears at the same time as the bit which it self generates an interrupt If the word currently being transferred causes both frame error and overrun error it will be transferred and only the OR bit will be set Bit 0 Unused 3 SERIAL COMMUNICATIONS INTERFACE
49. test conforms to the IEC1000 4 2 and SAEJ1752 3 standards and is described in Figure 76 For more details refer to the AN1181 ST7 application note 25 85 Vpp 5 5V fosc 4MHz 25 Figure 76 Diagram of the ESD Generator for DLU Cg 150pF ESD GENERATOR 2 HV RELAY DISCHARGE RETURN CONNECTION Notes 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the spec ifications that means when a device belongs to Class A it exceeds the JEDEC standard B Class strictly covers all the criteria international standard 2 Schaffner NSG435 with a pointed test finger 142 164 4 CHARACTERISTICS Cont d 12 7 3 ESD Pin Protection Strategy To protect an integrated circuit against Electro Static Discharge the stress must be controlled to prevent degradation or destruction of the circuit el ements The stress generally affects the circuit el ements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress The elements to be pro tected must not receive excessive current voltage or heating within their structure An ESD network combines the different input and output ESD protections This network works by al lowing safe discharge paths for the pins subjected to ESD stress Two critical ESD stress cases are presented in Figure 77 and Figure 78 f
50. to enable or disable the TLI capabil ity on the dedicated pin It is set and cleared by software 0 TLI disabled 1 TLI enabled Note a parasitic interrupt can be generated when clearing the TLIE bit Bit 1 SSM SS mode selection This bit is set and cleared by software _ 0 Normal mode the level of the SPI SS signal is input from the external SS pin m 1 mode PC7 the level ofthe SPI 55 signal is read from the SSI bit Bit 0 SSI SS internal mode This bit replaces pin SS ofthe SPI when bit SSM is set to 1 see SPI description It is set and cleared by software 47 164 ST72311R ST72511R ST72512R ST72532R MISCELLANEOUS REGISTERS Cont d Table 13 Miscellaneous Register Map and Reset Values Address Register 7 Hex Label 0020h MIS CR1 1511 1510 1521 1520 SMS Reset Value 0 0 0 0 0 0 0 0 0040h MISCR2 IPA IPB BC1 BCO TLIS TLIE SSM SSI Reset Value 0 0 0 0 0 0 0 0 4 48 164 10 ON CHIP PERIPHERALS 10 1 WATCHDOG TIMER WDG 10 1 1 Introduction The Watchdog timer is used to detect the occur rence of a software fault usually generated by ex ternal interference or by unforeseen logical condi tions which causes the application program to abandon its normal sequence The Watchdog cir cuit generates an MCU reset on expiry of a pro grammed time period unless the program refresh es the counter s contents before the T6 bit be comes cleared 10 1 2 Main Feature
51. value was higher than 128 When the counter value exceeds 127 the CAN controller enters the error passive state IDENTIFIER HIGH REGISTERS IDHRx Read Write Reset Value Undefined 7 0 ID 10 3 the most significant 8 bits of the 11 bit message identifier The identifier acts as the mes sage s name used for bus access arbitration and acceptance filtering 115 164 ST72311R ST72511R ST72512R ST72532R CONTROLLER AREA NETWORK Cont d IDENTIFIER LOW REGISTERS IDLRx Read Write Reset Value Undefined BUFFER CONTROL STATUS REGs BCSRx Read Write Reset Value 00h 7 0 7 0 ID 2 0 the least significant 3 bits of the 11 bit message identifier RTR is the Remote Transmission Request bit It is set to indicate a remote frame and reset to indicate a data frame DLC 3 0 is the Data Length Code It gives the number of bytes in the data field of the mes sage The valid range is O to 8 DATA REGISTERS DATAO 7x Read Write Reset Value Undefined 7 0 DATA DATA DATA DATA DATA 7 6 5 4 3 2 1 0 7 0 is amessage data byte Upto eight such bytes may be part of a message Writing to byte DATA7 initiates a transmit request and should al ways be done even when DATA7 is not part of the message 116 164 Bit 3 ACC Acceptance Code Read Only Set by hardware with the id of the highest
52. value when the MCU is woken up by a RESET 10 4 5 Interrupts Interrupt Event Input Capture 1 event Counter reset in PWM mode ICF1 Input Capture 2 event ICF2 Output Compare 1 event not available in PWM mode OCF1 OCIE ee Output Compare 2 event not available in PWM mode OCF2 Yes TmerOwrowswm Note The 16 bit Timer interrupt events are connected to the same interrupt vector see Interrupts chap ter These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset RIM instruction 10 4 6 Summary of Timer modes AVAILABLE RESOURCES Input Capture 1 Input Capture2 Output Compare 1 Output Compare 2 input Capture and or 2 Compare 2 One Pulse Mode Not Recommended Partially PWM Mode Not Recommended 1 See note 4 in Section 10 4 3 5 One Pulse Mode on page 69 See note 5 in Section 10 4 3 5 One Pulse Mode on page 69 3 See note 4 in Section 10 4 3 6 Pulse Width Modulation Mode on page 71 73 164 ST72311R ST72511R ST72512R ST72532R 16 BIT TIMER 10 4 7 Register Description Each Timer is associated with three control and status registers and with six pairs of data registers 16 bit values relating to the two input captures the two output compares the counter and the al ternate counter CONTROL REGISTER 1 CR1 Read Write Reset Value 0000 0000 00h 7
53. 18 164 ST72311R ST72511R ST72512R ST72532R CONTROLLER AREA NETWORK Figure 61 Page Maps DATA61 DATA62 DATA63 DATA71 DATA72 DATA73 Reserved Reserved Reserved Reserved BCSR1 BCSR2 BCSR3 Diagnosis Buffer 1 Buffer 2 Buffer 3 Acceptance Filters 119 164 ST72311R ST72511R ST72512R ST72532R CONTROLLER AREA NETWORK Table 23 CAN Register Map and Reset Values Address Register 5A CANISR RXIF3 RXIF2 RXIF1 TXIF SCIF ORIF TEIF EPND Reset Value 0 0 0 0 0 0 0 0 5B CANICR ESCI RXIE TXIE SCIE ORIE TEIE ETX Reset Value 0 0 0 0 0 0 0 CANCSR BOFF EPSV SRTE NRTX FSYN WKPS RUN Reset Value 0 0 0 0 0 0 0 CANBRPR RJW1 RJWO 5 BRP3 BRP2 BRP1 BRPO Reset Value 0 0 0 0 0 0 0 0 CANBTR BS22 BS21 BS20 BS13 BS12 BS11 BS10 Reset Value 0 1 0 0 0 1 1 CANPSR 2 PAGE1 PAGEO Reset Value 0 0 0 CANLIDHR LID10 409 108 407 LID6 LID5 LID4 LID3 Reset Value x x x x x x x CANIDHRx Po P a p P Es 1 to 3 Reset Value CANFHRx ii GE ius ies ix ju is 60 64 Reset Value CANLIDLR pes E ped E m SC Reset Value CANIDLRx P5 ge E e 1103 Reset Value 61 65 4 CANFLRx FIL3 FIL2 FIL1 FILO Reset Value x X x 621069 1103 CANDRx Reset Value x x D x x x x CANMHRx MSK11 MSK10 MSK9 MSK8 MSK7 MSK6 MSK5 MSK4 62 66 4 Reset Value X X X D x x x x CANMLRx in ie MSK1 MSKO 63 67 4 Reset Value x CANTECR KS E Reset Value CANRECR Ca r Reset
54. 2512R ST72532R Register e Reset 002Ah WDGCR Watchdog Control Register 7Fh 002Bh WDGSR Watchdog Status Register 000x 000x 002Ch EEPROM EECSR Data Data EEPROM ControlStatus Register Control Status Data EEPROM ControlStatus Register Reserved Area 4 Bytes TACR2 Timer A Control Register 2 R W TACR1 Timer A Control Register 1 R W TASR Timer A Status Register Read Only TAIC1HR Timer A Input Capture 1 High Register Read Only TAIC1LR Timer A Input Capture 1 Low Register Read Only Timer A Output Compare 1 High Register R W TAOC1LR Timer A Output Compare 1 Low Register R W TIMER A TACHR Timer A Counter High Register Read Only TACLR Timer A Counter Low Register Read Only TAACHR Timer A Alternate Counter High Register Read Only TAACLR Timer A Alternate Counter Low Register Read Only TAIC2HR Timer A Input Capture 2 High Register Read Only TAIC2LR Timer A Input Capture 2 Low Register Read Only TAOC2HR Timer A Output Compare 2 High Register R W TAOC2LR Timer A Output Compare 2 Low Register R W 0040h MISCR2 Miscellaneous Register 2 TBCR2 Timer B Control Register 2 R W TBCR1 Timer B Control Register 1 R W TBSR Timer B Status Register Read Only TBIC1HR Timer B Input Capture 1 High Register Read Only TBIC1LR Timer B Input Capture 1 Low Register Read Only TBOC1HR_ Timer B Output Compare 1 High Register R W TBOC1LR Timer B Output Compare 1 Low Register R W TIMER B TBCHR Timer B Counter High Register Read Onl
55. 6 ST72T311R7 ST72T311R9 ST72T511R6 ST72T511R7 ST72T511R9 ST72T512RA4 ST72T532R4 159 164 ST72311R ST72511R ST72512R ST72532R TRANSFER OF CUSTOMER CODE Cont d MICROCONTROLLER OPTION LIST Customer Address Contact Phone N Reference STMicroelectronics references Device ST72311R9 ST72511R9 ST72512R4 ST72311R7 ST72511R7 ST72532R4 ST72311R6 ST72511R6 Package TQFP64 Temperature Range 0 C 10 70 C 40 C to 85 C 40 to 105 40 to 125 C Oscillator Source Selection Quartz Crystal Ceramic resonator External Clock Watchdog Selection Software Activation Hardware Activation Disabled Watchdog Reset on Halt Enabled Readout Protection Disabled Enabled LVD Reset Disabled Enabled Comments Supply Operating Range in the application Notes Signature 3 160 164 14 3 DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware and software development tools for the ST7 micro controller family Full details of tools available for Third Party Tools ACTUM BP COSMIC CMX DATA I O m HITEX STMicroelectronics Tools ST72311R ST72511R ST72512R ST72532R the ST7 from third party manufacturers can be ob tain from the STMicroelectronics Internet site http st7 st com HIWARE ISYSTEM KANDA m LEAP Tools from these manufacturers include C compli ers emulators an
56. 8 164 Bit 7 0 CA 7 0 Counter Access Data These bits can be set and cleared either by hard ware or by software The CAR register is used to read or write the auto reload counter on the fly while it is counting AUTO RELOAD REGISTER ARR Read Write Reset Value 0000 0000 00h 7 0 Bit 7 0 AR 7 0 Counter Auto Reload Data These bits are set and cleared by software They are used to hold the auto reload value which is au tomatically loaded in the counter when an overflow occurs At the same time the PWM output levels are changed according to the corresponding OPx bit in the PWMCR register This register has two PWM management func tions Adjusting the PWM frequency Setting the PWM duty cycle resolution PWM Frequency vs Resolution 9 oae 312682 3 PWM AUTO RELOAD TIMER Cont d PWM CONTROL REGISTER PWMCR Read Write Reset Value 0000 0000 00h ST72311R ST72511R ST72512R ST72532R DUTY CYCLE REGISTERS DCRx Read Write Reset Value 0000 0000 00h 0 7 0 ora om Bit 7 4 OE 3 0 PWM Output Enable These bits are set and cleared by software They enable or disable the PWM output channels inde pendently acting on the corresponding 0 PWM output disabled 1 PWM output enabled Bit 3 0 OP 3 0 PWM Output Polarity These bits are set and cleared by software They independently select the polari
57. CTIVE HALT mode is the lowest power con sumption mode of the MCU with a real time clock available It is entered by executing the HALT in struction when the OIE bit of the Main Clock Con troller Status register MCCSR is set see Section 10 2 on page 52 for more details on the MCCSR register The MCU can exit ACTIVE HALT mode on recep tion of either an MCC RTC interrupt a specific in terrupt see Table 7 Interrupt Mapping on page 32 or a RESET When exiting ACTIVE HALT mode by means of a RESET or an interrupt a 4096 CPU cycle delay occurs After the start up delay the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up see Figure 22 When entering ACTIVE HALT mode the I 1 0 bits in the CC register are forced to 10 to enable inter rupts Therefore if an interrupt is pending the MCU wakes up immediately In ACTIVE HALT mode only the main oscillator and its associated counter MCC RTC are run ning to keep a wake up time base All other periph erals are not clocked except those which get their clock supply from another clock generator such as external or auxiliary oscillator The safeguard against staying locked in ACTIVE HALT mode is provided by the oscillator interrupt Note As soon as the interrupt capability of one of the oscillators is selected MCCSR OIE bit set entering ACTIVE HALT mode while the Watchdog is active does not generate a RESET T
58. Cont d CONTROL REGISTER 1 CR1 Read Write Reset Value Undefined 7 0 Bit 7 R8 Receive data bit 8 This bit is used to store the 9th bit of the received word when 1 Bit 6 T8 Transmit data bit 8 This bit is used to store the 9th bit of the transmit ted word when M 1 Bit 4 M Word length This bit determines the word length It is set or cleared by software 0 1 Start bit 8 Data bits 1 Stop bit 1 1 Start bit 9 Data bits 1 Stop bit Bit 3 WAKE Wake Up method This bit determines the SCI Wake Up method it is set or cleared by software 0 ldle Line 1 Address Mark CONTROL REGISTER 2 CR2 Read Write Reset Value 0000 0000 00h 7 0 Bit 7 TIE Transmitter interrupt enable This bit is set and cleared by software 0 interrupt is inhibited 1 An SCI interrupt is generated whenever 1 in the SR register Bit 6 TCIE Transmission complete interrupt ena ble This bit is set and cleared by software 0 interrupt is inhibited ST72311R ST72511R ST72512R ST72532R 1 SCI interruptis generated whenever TC 1 in the SR register Bit 5 RIE Receiver interrupt enable This bit is set and cleared by software 0 interrupt is inhibited 1 An interrupt is generated whenever OR 1 or RDRF 1 in the SR register Bit 4 ILIE dle line interrupt enable This bit is set and cleared by software 0 interrupt is inhibited 1 An SCI interrupt is generated whenever IDL
59. D IN 7 DR REGISTER ACCESS TRUE OPEN DRAIN VOPORTS PULL UP DR REGISTER DATABUS R ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE eix INTERRUPT POLARITY CONDITION SELECTION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN DR REGISTER ACCESS PORTS 2 DR REGISTER DATABUS ALTERNATE ALTERNATE ENABLE OUTPUT a 5 lt oc a 2 D IMPLEMENTED IN TRUE OPEN DRAIN DR REGISTER ACCESS VOPORTS DR REGISTER DATABUS PUSH PULL OUTPUT 2 ALTERNATE ALTERNATE ENABLE OUTPUT Notes 1 When the port is in input configuration and the associated alternate function is enabled as an output reading the DR register will read the alternate function output status 2 When the I O port is in output configuration and the associated alternate function is enabled as an input the alternate function reads the pin status given by the DR register content 40 164 4 PORTS Cont d CAUTION The alternate function must not be ac tivated as long as the pin is configured as input with interrupt in order to avoid generating spurious interrupts Analog alternate function When the pin is used as an ADC input the must be configured as floating input The analog multiplexer controlled by the ADC registers switches the analog voltage present on the select ed pin to the common analog r
60. E EDGE DETECT CIRCUIT2 CIRCUIT1 IC2R Register IC1R Register Status Register SR Control Register 2 CR2 Geen TIT ileje COUNTER Figure 40 Input Capture Timing Diagram Timer clock COUNTER REGISTER DEZ DEE ICAPi PIN Se Ss 3 ICAPi FLAG ICAPi REGISTER FF03 Note Active edge is rising edge 3 66 164 16 BIT TIMER Cont d 10 4 3 4 Output Compare In this section the index may be 1 or 2 because there are 2 output compare functions in the 16 bit timer This function can be used to control an output waveform or indicate when a period of time has elapsed When a match is found between the Output Com pare register and the free running counter the out put compare function Assigns pins with a programmable value if the OCIE bit is set Sets a flag in the status register Generates an interrupt if enabled Two 16 bit registers Output Compare Register 1 OC1R and Output Compare Register 2 OC2R contain the value to be compared to the counter register each timer clock cycle MS Byte LS Byte OCiHR These registers are readable and writable and not affected by the timer hardware A reset event changes the value to 8000h Timing resolution is one count of the free running counter fcpu ccrt 0 OCiR Procedure To use the output compare function select the fol lowing in the CR2 register Set the bit if an out
61. E gt Ko 64 CR Note QUALIFICATION OR VOLUME PRODUCTION OF DEVICES USING EPOXY PACKAGES ESO EDIL EQF P IS NOT AUTHORIZED Itis expressly specified that qualification and or volume production of devices using the package E in any applications is not authorized Usage in any application is strictly restricted to development purpose Similar devices are available in plastic package mechanically compatible to the epoxy package for qualification and volume production 154 164 STA ST72311R ST72511R ST72512R ST72532R 13 2 THERMAL CHARACTERISTICS CL ME E NM R Package thermal resistance junction to ambient C W mA TQFP64 Notes 1 The power dissipation is obtained from the formula where is the chip internal power IppxVpp and is the port power dissipation determined by the user 2 The average chip junction temperature can be obtained from the formula Ty T4 Pp x 155 164 ST72311R ST72511R ST72512R ST72532R 13 3 SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only as design guidelines Figure 95 Recommended Wave Soldering Profile with 37 Sn and 63 Pb COOLING PHASE ege ROOM TEMPERATURE SOLDERING 150 Temp C 100 50 Time sec 220 5 for 25 sec 150 sec above 183 C 90 sec at 125 C Temp C ramp down natural ramp u
62. E 1 in the SR register Bit 3 TE Transmitter enable This bit enables the transmitter and assigns the TDO pin to the alternate function It is set and cleared by software 0 Transmitter is disabled the TDO pin is back to the I O port configuration 1 Transmitter is enabled Note during transmission a 0 pulse on the TE bit followed by 1 sends a preamble after the current word Bit 2 RE Receiver enable This bit enables the receiver It is set and cleared by software 0 Receiver is disabled it resets the RDRF IDLE OR NF and FE bits of the SR register 1 Receiver is enabled and begins searching for a start bit Bit 1 RWU Receiver wake up This bit determines if the SCI is in mute mode or not It is set and cleared by software and can be cleared by hardware when a wake up sequence is recognized 0 Receiver in active mode 1 Receiver in mute mode Bit 0 SBK Send break This bit set is used to send break characters It is set and cleared by software 0 No break character is transmitted 1 Break characters are transmitted Note If the SBK bit is set 1 and then to 0 the transmitter will send a BREAK word at the end of the current word 101 164 ST72311R ST72511R ST72512R ST72532R SERIAL COMMUNICATIONS INTERFACE Cont d DATA REGISTER DR Read Write Reset Value Undefined Contains the Received or Transmitted data char acter depending on whether it is r
63. ENTIFIER LOW REGISTER LIDLR Read Write Reset Value Undefined 7 0 LID2 LID1 LIDO LRTR p P peu LID 2 0 are the least significant 3 bits of the last Identifier read on the CAN bus LRTR is the last Remote Transmission Request bit read on the CAN bus LDLC 3 0 is the last Data Length Code read on the CAN bus ST72311R ST72511R ST72512R ST72532R TRANSMIT ERROR COUNTER REG TECR Read Only Reset Value 00h 7 0 TEC6 5 TEC4 2 1 TECO 7 0 is the least significant byte of the 9 bit Transmit Error Counter implementing part of the fault confinement mechanism of the CAN protocol In case of an error during transmission this counter is incremented by 8 It is decremented by 1 after every successful transmission When the counter value exceeds 127 the CAN controller enters the error passive state When avalue of 256 is reached the CAN controller is disconnected from the bus RECEIVE ERROR COUNTER REG RECR Page 00h Read Only Reset Value 00h 0 REC6 5 REC4 REC2 REC1 RECO REC 7 0 is the Receive Error Counter implement ing part of the fault confinement mechanism of the CAN protocol In case of an error during reception this counter is incremented by 1 or by 8 depending on the error condition as defined by the CAN stand ard After every successful reception the counter is decremented by 1 or reset to 120 if its
64. EPROM area occurs the value is latched inside the 16 data latches ac cording to its address ST72311R ST72511R ST72512R ST72532R When PGM bit is set by the software all the previ ous bytes written in the data latches up to 16 are programmed in the EEPROM cells The effective high address row is determined by the last EEP ROM write sequence To avoid wrong program ming the user must take care that all the bytes written between two programming sequences have the same high address only the four Least Significant Bits of the address can change At the end of the programming cycle the PGM and LAT bits are cleared simultaneously and an inter rupt is generated if the IE bitis set The Data EEP ROM interrupt request is cleared by hardware when the Data EEPROM interrupt vector is fetched Note Care should be taken during the program ming cycle Writing to the same memory location will over program the memory logical AND be tween the two write access data result because the data latches are only cleared at the end of the programming cycle and by the falling edge of LAT bit It is not possible to read the latched data This note is ilustrated by the Figure 6 Figure 5 Data EEPROM Programming Flowchart READ MODE LAT 0 PGM 0 READ BYTES IN EEPROM AREA INTERRUPT GENERATION IF 1 1 WRITE MODE LAT 1 PGM 0 WRITE UP TO 16 BYTES EEPROM AREA with the same 12 MSB of the address START PROGRAMMING CYC
65. GISTER IC1LR Read Only Reset Value Undefined This is an 8 bit read only register that contains the low part of the counter value transferred by the in put capture 1 event 7 0 pec OUTPUT COMPARE 1 HIGH REGISTER OC1HR Read Write Reset Value 1000 0000 80h This is an 8 bit register that contains the high part of the value to be compared to the CHR register 7 0 _ _ _ OUTPUT COMPARE 1 LOW REGISTER OC1LR Read Write Reset Value 0000 0000 00h This is an 8 bit register that contains the low part of the value to be compared to the CLR register 7 0 4 16 BIT TIMER Cont d OUTPUT COMPARE 2 HIGH REGISTER OC2HR Read Write Reset Value 1000 0000 80h This is an 8 bit register that contains the high part of the value to be compared to the CHR register 7 0 peu qo OUTPUT COMPARE 2 LOW REGISTER OC2LR Read Write Reset Value 0000 0000 00h This is an 8 bit register that contains the low part of the value to be compared to the CLR register 7 0 COUNTER HIGH REGISTER CHR Read Only Reset Value 1111 1111 FFh This is an 8 bit register that contains the high part of the counter value 7 0 ml 1111 COUNTER LOW REGISTER CLR Read Only Reset Value 1111 1100 FCh This is an 8 bit register that contains the low part of the counter value A write to this register resets t
66. INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read Write Reset Value 111x 1010 xAh 7 0 2 Bit 5 3 11 10 Software Interrupt Priority These two bits indicate the current interrupt soft ware priority Interrupt Software Priority Level 0 main Level 1 Level 2 Level 3 interrupt disable High These two bits are set cleared by hardware when entering in interrupt The loaded value is given by the corresponding bits in the interrupt software pri ority registers ISPRx They can be also set cleared by software with the RIM SIM HALT WFI IRET and PUSH POP in structions see Interrupt Dedicated Instruction Set table Note TLI TRAP and RESET events are non maskable sources and can interrupt a level 3 pro gram ST72311R ST72511R ST72512R ST72532R INTERRUPT SOFTWARE PRIORITY REGIS TERS ISPRX Read Write bit 7 4 of ISPR3 are read only Reset Values 1111 1111 FFh 7 0 pe ee eee peee ee These four registers contain the interrupt software priority of each interrupt vector Each interrupt vector except RESET and TRAP has corresponding bits in these registers where its own software priority is stored This corre spondance is shown in the following table FFFBh FFFAh I1 O and 10_0 bits FFF9h FF F8h I1 1 and 10 1 bits FFE1h FFEOh I1 13 and 10 13 bits Each 1_ and 10 x bit value in the ISPRx regis ters has the sa
67. LE LAT 1 PGM 1 set by software CLEARED BY HARDWARE 17 164 ST72311R ST72511R ST72512R ST72532R DATA EEPROM Cont d 3 4 POWER SAVING MODES Wait mode The DATA EEPROM can enter WAIT mode on ex ecution of the instruction of the microcontrol ler The DATA EEPROM will immediately enter this mode if there is no programming in progress otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode Halt mode The DATA EEPROM immediatly enters HALT mode if the microcontroller executes the HALT in struction Therefore the EEPROM will stop the function in progress and data may be corrupted Figure 6 Data EEPROM Programming Cycle READ OPERATION NOT POSSIBLE 3 5 ACCESS ERROR HANDLING If a read access occurs while 1 then the data bus will not be driven If a write access occurs while LAT 0 then the data on the bus will not be latched If a programming cycle is interrupted by software RESET action the memory data will not be guar anteed READ OPERATION POSSIBLE lt lt lt INTERNAL PROGRAMMING VOLTAGE ERASE CYCLE 1 WRITEOF 1DATA LATCHES 18 164 WRITE CYCLE IN EEPROM INTERRUPT r DATA EEPROM Cont d 3 6 REGISTER DESCRIPTION CONTROL STATUS REGISTER CSR Read Write Reset Value 0000 0000 00h 7 0 Bit 7 3 Reserved forced by hardware to 0 Bit 2 IE nterrupt enable This bitis set and cleared by softwa
68. Only Memory can be used as a non volatile back up for storing data Using the EEPROM requires a basic access protocol described in this chapter Up to 16 Bytes programmed in the same cycle EEPROM mono voltage charge pump Chained erase and programming cycles Internal control of the global programming cycle duration End of programming cycle interrupt flag m WAIT mode management Figure 4 EEPROM Block Diagram FALLING EEPROM INTERRUPT EDGE DETECTOR X HIGH VOLTAGE PUMP RESERVED EEPROM m eoo e MEMORY MATRIX 1 ROW 16 BITS ADDRESS ROW DECODER DECODER DATA 16x 8 BITS MULTIPLEXER DATA LATCHES ADDRESS BUS 3 16 164 DATA EEPROM Cont d 3 3 MEMORY ACCESS The Data EEPROM memory read write access modes are controlled by the LAT bit of the EEP ROM Control Status register EECSR The flow chart in Figure 5 describes these different memory access modes Read Operation LAT 0 The EEPROM can be read as a normal ROM loca tion when the LAT bit of the EECSR register is cleared Ina read cycle the byte to be accessed is put on the data bus in less than 1 CPU clock cycle This means that reading data from EEPROM takes the same time as reading data from EPROM but this memory cannot be used to exe cute machine code Write Operation LAT 1 To access the write mode the LAT bit has to be set by software the PGM bit remains cleared When awrite access to the E
69. Other wise the interrupt remains pending until both conditions become true Clearing the Input Capture interrupt request i e clearing the bit is done two steps 1 Reading the SR register while the ICF bit is set 2 An access read or write to the register Notes 1 After reading the IC HR register transfer of input capture data is inhibited and ICFi will never be set until the register is also read 2 The register contains the free running counter value which corresponds to the most recent input capture 3 The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions 4 n One pulse Mode and PWM mode only the input capture 2 can be used 5 The alternate inputs ICAP1 amp ICAP2 are always directly connected to the timer So any transitions on these pins activate the input cap ture function Moreover if one of the ICAP pin is configured as an input and the second one as an output an interrupt can be generated if the user toggle the output pin and if the ICIE bit is set This can be avoided if the input capture func tion disabled by reading the IC HR see note 1 6 The TOF bit can be used with interrupt in order to measure event that go beyond the timer range FFFFh 65 164 ST72311R ST72511R ST72512R ST72532R 16 BIT TIMER Cont d Figure 39 Input Capture Block Diagram Control Register 1 CR1 EDG
70. PORT E 6 164 Under software control all devices can be placed in WAIT SLOW ACTIVE HALT or HALT mode reducing power consumption when the application is in idle or standby state The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers enabling the design of highly efficient and compact application code In addition to standard 8 bit data management all ST7 micro controllers feature true bit manipulation 8x8 un signed multiplication and indirect addressing modes PROGRAM MEMORY 16K 60K Bytes EEPROM 256 Bytes 3 ST72311R ST72511R ST72512R ST72532R 1 2 PIN DESCRIPTION Figure 2 64 Pin TQFP Package Pinout CANRX 2 CANTX PE1 RDI PEO o ez Vss 1 Vpp 1 PA2 PA1 PAO 7 55 PC6 SCK 5 MOSI 4 MISO HS ICAP 1_B PC2 HS ICAP2_B PC1 1_ PCO OCMP2 Vss_o 5 7 PWM3 PWM2 PWM 1 PB2 PWMO PB3 ARTCLK PB5 PB6 PB7 AINO PDO PD1 AIN2 PD2 AIN3 Jo Om WD 10 11 12 13 14 15 16 1 N PD4 O AIN5 PD5 AIN6 PD6 AIN7 PD7 D PF1 2 PF5 D HS PF6 D HS 1 1_ 1_ 4 O EXTCLK A
71. Pot be _ X X X Pot ps ADCAnabginput3 x x X X x Pot Dt anaona x x x Potps ADC Analog ius x x x Potoe ADC Analog iue Pon 07 ADC Analog input 1 Power Supply 0 LL I T LL man Supply ERC T o ol v m m 7 HS PBO PWM3 PB1 PWM2 PB2 PWM1 PB3 PWMO PBA ARTCLK T 2 o 5 ER derr 5 PB7 PDO AINO PD1 AIN1 PD2 AIN2 PD3 AIN3 PD4 AIN4 PD5 AIN5 PD6 AIN6 PD7 AIN7 Vssa 3 5 3 4 EE ER 8 S Bur 5 Ea ES RES 0 U 00 UJ 4 8 164 9 8 9 Em OO Co o ol NJ ot ol A PO OQ ot BY Po l OO oy 55 3 _ PC2 HS ICAP2_B PC6 SCK 70 ST72311R ST72511R ST72512R ST72532R Oo function HEBERE 1 REEL VENEN EE 7 77 7 8 20 oi 0 o Px x Timer A Input Capture 2 x X Potre Timer X X Potr7 Timer A External Clock Source T T T
72. Prescaler Rate vs Standard Conventional Mode TR or RR 64 PR 13 TR or RR 16 PR 13 di or RR 8 PR 13 or RR 0 16 RR 2 PR 13 Communication frequency 8MHz TR or RR 8 PR 3 fex TR or RR 1 PR 13 19200 19230 77 E ETPR or ERPR 14400 14285 71 12 11 3 CAN Controller Area Network Interface Subject to general operating condition for Vpp fo the input output alternate function characteristics sc and T4 unless otherwise specified CANTX and CANRX Refer to port characteristics for more details on Fee met E r 151 164 ST72311R ST72511R ST72512R ST72532R 12 12 8 BIT ADC CHARACTERISTICS Subject to general operating condition for Vpp fosc and T4 unless otherwise specified Symbol Parameter J Typ wex Um Conversion range Raw emaa internal sample andholacapactor Stabilization time after ADC enable 0 t Sample capacitor loading time l HS LOAD por 9 fopy 8MHz fapc 4MHz 4 Kane conversion time Figure 91 Typical Application with ADC SAMPLING SWITCH ST72XXX Notes 1 Unless otherwise specified typical data are based on 25 and Vpp Vss 5V They are given only as design guide lines and are not tested 2 When
73. RFACE Cont d 10 5 4 3 Data Transfer Format During an SPI transfer data is simultaneously transmitted shifted out serially and received shifted in serially The serial clock is used to syn chronize the data transfer during a sequence of eight clock pulses The SS pin allows individual selection of a slave device the other slave devices that are not select ed do not interfere with the SPI transfer Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software using the CPOL and CPHA bits The CPOL clock polarity bit controls the steady state value of the clock when no data is being transferred This bit affects both master and slave modes The combination between the CPOL and CPHA clock phase bits selects the data capture clock edge Figure 49 shows an SPI transfer with the four combinations of the CPHA and CPOL bits The di agram may be interpreted as a master or slave timing diagram where the SCK pin the MISO pin the MOSI pin are directly connected between the master and the slave device The SS pin is the slave device select input and can be driven by the master device Figure 48 CPHA SS Timing Diagram MOSI MISO Master SS Slave SS CPHA 0 ST72311R ST72511R ST72512R ST72532R The master device applies data to its MOSI pin clock edge before the capture clock edge CPHA bit is set The second edge on the SCK pin falling edge if the CPOL bit is reset risin
74. Reload Timer Auto Reload Register Reserved Area 6 Bytes Legend x undefined R W read write Notes 1 The contents of the port DR registers are readable only in output configuration In input configura tion the values of the I O pins are returned instead of the DR register contents 2 The bits associated with unavailable pins must always keep their reset value 14 164 4 2 EPROM PROGRAM MEMORY The program memory of the OTP and EPROM de vices can be programmed with EPROM program ming tools available from STMicroelectronics EPROM Erasure EPROM devices are erased by exposure to high intensity UV light admitted through the transparent window This exposure discharges the floating gate to its initial state through induced photo cur rent It is recommended that the EPROM devices be kept out of direct sunlight since the UV content of ST72311R ST72511R ST72512R ST72532R sunlight can be sufficient to cause functional fail ure Extended exposure to room level fluorescent lighting may also cause erasure An opaque coating paint tape label etc should be placed over the package window if the product is to be operated under these lighting con ditions Covering the window also reduces lpp in power saving modes due to photo diode leakage currents 15 164 ST72311R ST72511R ST72512R ST72532R 3 DATA EEPROM 3 1 INTRODUCTION 3 2 MAIN FEATURES The Electrically Erasable Programmable Read
75. Reserved always read as 0 Bit 3 2 TB 1 0 Time base control These bits select the programmable divider time base They are set and cleared by software Time Base Counter Prescaler fosc 8MHz 52000 9m A modification of the time base is taken into ac count at the end of the current period previously set to avoid an unwanted time shift This allows to use this time base as a real time clock Bit 1 OIE Oscillator interrupt enable This bit set and cleared by software 0 Oscillator interrupt disabled 1 Oscillator interrupt enabled This interrupt can be used to exit from ACTIVE HALT mode When this bit is set calling the ST7 software HALT instruction enters the ACTIVE HALT power saving mode Bit 0 OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the CSR register It indicates when set that the main oscillator has reached the selected elapsed time TB1 0 0 Timeout not reached 1 Timeout reached CAUTION The BRES and BSET instructions must not be used on MCCSR register to avoid unintentionally clearing the OIF bit 10 2 5 Low Power Modes MCC RTC interrupt cause the device to exit from WAIT mode No effect on MCC RTC counter OIE bit is ACTIVE set the registers are frozen HALT MCC RTC interrupt cause the device to exit WAIT from ACTIVE HALT mode MCC RTC counter a
76. Reset Value 0000 0000 00h 7 0 Bit 0 WDOGF Watchdog This bit is set by a watchdog reset and cleared by software or a power on off reset This bit is useful for distinguishing power on off or external reset and watchdog reset 0 No Watchdog reset occurred 1 Watchdog reset occurred Only by software and power on off reset Note This register is not used in versions without LVD Reset 4 ST72311R ST72511R ST72512R ST72532R WATCHDOG TIMER Cond t Table 15 Watchdog Timer Register Map and Reset Values Address Register Hex Label WDGCR WDGA Reset Value on WDGSR 002Bh Reset Value x 51 164 ST72311R ST72511R ST72512R ST72532R 10 2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER MCC RTC The Main Clock Controller consists of three differ ent functions m a programmable CPU clock prescaler m clock out signal to supply external devices m realtime clock timer with interrupt capability Each function can be used independently and si multaneously 10 2 1 Programmable CPU Clock Prescaler The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal periph erals It manages SLOW power saving mode See Section 7 2 SLOW on page 34 for more details The prescaler selects the main clock frequen cy and is controlled by three bits in the MISCR1 register CP 1 0 and SMS CAUTION The prescaler does not act on t
77. S10 RJW 1 0 determine the maximum number of time quanta by which a bit period may be shortened or lengthened to achieve resynchronization truw tcan IW 1 BRP 5 0 determine the CAN system clock cycle time or time quanta which is used to build up the in dividual bit timing tcan topu BRP 1 Where tcpy time period of the CPU clock The resulting baud rate can be computed by the for mula 1 BR _ tcpy X BRP 1 x BS1 BS2 3 Note Writing to this register is allowed only in Standby mode to prevent any accidental CAN pro tocol violation through programming errors 114 164 BS2 2 0 determine the length of Bit Segment 2 1352 tcan 52 1 BS1 3 0 determine the length of Bit Segment 1 tcan 1 Note Writing to this register is allowed only Standby mode to prevent any accidental CAN pro tocol violation through programming errors PAGE SELECTION REGISTER PSR Read Write Reset Value 00h 7 0 PAGE PAGE PAGE 2 1 0 PAGE 2 0 determine which buffer or filter page is mapped at addresses 0010h to 001Fh ee a 4 CONTROLLER AREA NETWORK Cont d 10 7 4 2 Paged Registers LAST IDENTIFIER HIGH REGISTER LIDHR Read Write Reset Value Undefined 7 0 LID10 1109 108 106 LID5 LID4 LID3 LID 10 3 are the most significant 8 bits of the last Identifier read on the CAN bus LAST ID
78. SLOW WAIT mode 4 see Figure 72 Supply current in WAIT mode 3 see Figure 71 Supply current in SLOW WAIT mode 4 see Figure 72 3VSVpps3 6V 4 5 lt lt 5 5 Figure 71 Typical Ipp in WAIT vs fepy Figure 72 Typical Ipp SLOW WAIT vs fcpy IDD mA IDD mA 1 5 2MHz muc 500kHz 125kHz 31 25kHz uM 5 4 4 5 5 5 5 VDD V 3 3 Notes 1 Typical data are based on 25 Vpp 5V 4 5 lt ppx5 5V range and Vpp 3 3V 3 lt lt 3 6 range 2 Data based on characterization results tested in production at Vpp max and max 3 All UO pins in input mode with a static value at or Vas no load all peripherals switched off clock input OSC 1 driven by external square wave LVD disabled 4 SLOW WAIT mode selected with based on fosc divided by 32 All I O pins in input mode with a static value at Vpp Vss no load all peripherals switched off clock input OSC1 driven by external square wave LVD disabled 3 136 164 ST72311R ST72511R ST72512R ST72532R SUPPLY CURRENT CHARACTERISTICS Cont d 12 4 3 HALT and ACTIVE HALT Modes Symbol 2 Paameer Conditions Supply current in ACTIVE HALT mode CTT Fe Supply current in HALT mode 2 Vpps5 5V 40 lt lt 125 pw 12 4 4 Supply and Clock Managers The previous current consumption specified for source current consumption To get the tot
79. SMIT POINT 4 CONTROLLER AREA NETWORK Cont d 10 7 4 Register Description The CAN registers are organized as 6 general pur pose registers plus 5 pages of 16 registers span ning the same address space and primarily used for message and filter storage The page actually selected is defined by the content of the Page Se lection Register Refer to Figure 60 10 7 4 1 General Purpose Registers INTERRUPT STATUS REGISTER ISR Read Write Reset Value 00h 7 0 RXIF2 SCIF ORIF EPND Bit 7 RXIF3 Receive Interrupt Flag for Buffer 3 Read Clear Set by hardware to signal that a new error free mes sage is available in buffer 3 Cleared by software to release buffer 3 Also cleared by resetting bit RDY of BCSR3 Bit 6 RXIF2 Receive Interrupt Flag for Buffer 2 Read Clear Set by hardware to signal that a new error free message is available in buffer 2 Cleared by software to release buffer 2 Also cleared by resetting bit RDY of BCSR2 Bit 5 RXIF1 Receive Interrupt Flag for Buffer 1 Read Clear Set by hardware to signal that a new error free mes sage is available in buffer 1 Cleared by software to release buffer 1 Also cleared by resetting bit RDY of BCSR1 ST72311R ST72511R ST72512R ST72532R Bit 4 Transmit Interrupt Flag Read Clear Set by hardware to signal that the highest priority message queued for transmission has been suc cessf
80. ST72512R ST72532R PORT PIN CHARACTERISTICS Cont d 12 8 2 Output Driving Current Subject to general operating condition for Vpp fosc and T4 unless otherwise specified Output low level voltage for a standard I O pin 5 when 8 pins are sunk at same time Output low level voltage for a high sink I O pin 10 20 13 when 4 pins are sunk at same time Output high level voltage for an I O pin 5 Vpp20 when 8 pins are sourced at same time Figure 83 Typical Vo at Vpp 5V standard Figure 85 Typical Vpp Voy at 5 Vol V P Vdd Voh V Ta 40 C Vdd 5V Vdd 5V 1 5 Ta 25 C 85 125 a lio mA Vol Vdd 5V mA Notes 1 The ljo current sunk must always respect the absolute maximum rating specified in Section 12 2 2 and the sum of lig I O ports and control pins must not exceed lyss 2 The ljo current sourced must always respect the absolute maximum rating specified in Section 12 2 2 and the sum of I O ports and control pins must not exceed lypp True open drain pins does not have 146 164 7 71 ST72311R ST72511R ST72512R ST72532R 12 9 CONTROL PIN CHARACTERISTICS 12 9 1 Asynchronous RESET Pin Subject to general operating condition for Vpp fosc and T4 unless otherwise specified EE E
81. Section 10 2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER MCC RTC on page 52 for more details 3 MISCELLANEOUS REGISTERS Cont d MISCELLANEOUS REGISTER 2 MISCR2 Read Write Reset Value 0000 0000 00h 7 0 P Bit 7 IPA nterrupt polarity for port A This bit is used to invert the sensitivity of the port A 3 0 external interrupts It is set and cleared by software 0 No sensitivity inversion 1 Sensitivity inversion See Section 9 1 PORT INTERRUPT SENSI TIVITY on page 45 and the description of the IS2x bits of the MISCR1 register for more details Bit 6 IPB nterrupt polarity for port B This bit is used to invert the sensitivity of the port B 3 0 external interrupts It is set and cleared by software 0 No sensitivity inversion 1 Sensitivity inversion See Section 9 1 I O PORT INTERRUPT SENSI TIVITY on page 45 and the description of the IS1x bits of the MISCR1 register for more details Bit 5 4 BC 1 0 Beep control These 2 bits select the PF1 pin beep capability Output Beep signal 50 duty cycle The beep output signal is available in ACTIVE HALT mode but has to be disabled to reduce the consumption ST72311R ST72511R ST72512R ST72532R Bit 3 TLIS TLI sensitivity This bit allows to toggle the TLI edge sensitivity It can be set and cleared by software only when TLIE bit is cleared 0 Falling edge 1 Rising edge Bit 2 TLIE 70 enable This bit allows
82. Software Priority Levels Interrupt software priority Level 10 Level 0 main Lw 1 0 Level 3 interrupt disable Interrupt has the same lower software priority than current one THE INTERRUPT STAYS PENDING priority an current one software th i x 2 7 bai 5 5 STACK X A CC LOAD 11 0 FROM INTERRUPT SW LOAD PC FROM INTERRUPT VECTOR 4 INTERRUPTS Cont d Servicing Pending Interrupts As several interrupts can be pending at the same time the interrupt to be taken into account is deter mined by the following two step process the highest software priority interrupt is serviced if several interrupts have the same software pri ority then the interrupt with the highest hardware priority is serviced first Figure 15 describes this decision process Figure 15 Priority Decision Process PENDING INTERRUPTS SOFTWARE Different PRIORITY HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED When an interrupt request is not serviced immedi ately it is latched and then processed when its software priority combined with the hardware pri ority becomes the highest one Note 1 The hardware priority is exclusive while the software one is not This allows the previous process to succeed with only one interrupt Note 2 RESET TRAP and TLI are non maskable a
83. TERRUPT 3 54 164 PWM AUTO RELOAD TIMER Cont d 10 3 2 Functional Description Counter The free running 8 bit counter is fed by the output of the prescaler and is incremented on every ris ing edge of the clock signal It is possible to read or write the contents of the counter on the fly by reading or writing the Counter Access register CAR When a counter overflow occurs the counter is automatically reloaded with the contents of the ARR register the prescaler is not affected Counter clock and prescaler The counter clock frequency is given by fcouNrER finput 200120 The timer counter s input clock feeds the 7 bit programmable prescaler which selects one of the 8 available taps of the prescaler as defined by 2 0 bits in the Control Status Register CSR Thus the division factor of the prescaler be set to 2 where n 0 1 7 This frequency source is selected through the EXCL bit of the CSR register and can be either the or an external input frequency The clock input to the counter is enabled by the TCE Timer Counter Enable bit in the CSR regis ter When TCE is reset the counter is stopped and the prescaler and counter contents are frozen Figure 31 Output compare control ST72311R ST72511R ST72512R ST72532R When TCE is set the counter runs at the rate of the selected clock source Counter and Prescaler Initialization After RESET t
84. a byte thus requires only one byte after the opcode but only allows 00 FF address ing space Direct long The address is a word thus allowing 64 Kbyte ad dressing space but requires 2 bytes after the op code 11 1 4 Indexed No Offset Short Long In this mode the operand is referenced by its memory address which is defined by the unsigned addition of an index register X or Y with an offset The indirect addressing mode consists of three sub modes Indexed No Offset There is no offset no extra byte after the opcode and allows 00 FF addressing space Indexed Short The offset is a byte thus requires only one byte af ter the opcode and allows 00 1FE addressing space Indexed long The offset is a word thus allowing 64 Kbyte dressing space and requires 2 bytes after the op code 11 1 5 Indirect Short Long The required data byte to do the operation is found by its memory address located in memory point er The pointer address follows the opcode The indi rect addressing mode consists of two sub modes Indirect short The pointer address is a byte the pointer size is a byte thus allowing 00 FF addressing space and requires 1 byte after the opcode Indirect long The pointer address is a byte the pointer size is a word thus allowing 64 Kbyte addressing space and requires 1 byte after the opcode r INSTRUCTION SET OVERVIEW 11 1 6 Indirect Index
85. a specific behaviour accord ing to the selected input output configuration Writ ing the DR register is always taken into account even ifthe pin is configured as an input this allows to always have the expected level on the pin when toggling to output mode Reading the DR register returns either the DR register latch content pin configured as output or the digital value applied to the I O pin pin configured as input DATA DIRECTION REGISTER DDR Port x Data Direction Register PxDDR with x A B C D Eor F Read Write Reset Value 0000 0000 00h T 0 Bit 7 0 DD 7 0 Data direction register 8 bits The DDR register gives the input output direction configuration of the pins Each bits is set and cleared by software 0 Input mode 1 Output mode Bit 7 0 O 7 0 Option register 8 bits For specific I O pins this register is not implement ed In this case the DDR register is enough to se lect the I O pin configuration The OR register allows to distinguish in input mode if the pull up with interrupt capability or the basic pull up configuration is selected in output mode if the push pull or open drain configuration is selected Each bit is set and cleared by software Input mode 0 floating input 1 pull up input with or without interrupt Output mode 0 output open drain with P Buffer unactivated 1 output push pull 43 164 ST72311R ST72511R ST72512R ST72532R PORTS Cont d
86. agement as described in the CAN protocol is completely handled by hard ware using 2 error counters which get increment ed or decremented according to the error condition Both of them may be read by the appli Figure 58 CAN Error State Diagram ST72311R ST72511R ST72512R ST72532R cation to determine the stability of the network Moreover as one of the node status bits EPSV or BOFF of the CSR register changes an inter rupt is generated if the SCIE bit is set in the ICR Register Refer to Figure 58 When TECR or RECR gt 127 the EPSV bit gets set ERROR ACTIVE ERROR PASSIVE When TECR and RECR 128 the EPSV bit gets cleared When 128 11 recessive bits occur the BOFF bit gets cleared the TECR register gets cleared the RECR register gets cleared When TECH gt 255 the BOFF bit gets set and the EPSV bit gets cleared 109 164 57723118 ST72511R ST72512R ST72532R CONTROLLER AREA NETWORK Cont d 10 7 3 4 Bit Timing Logic The bit timing logic monitors the serial bus line and performs sampling and adjustment of the sample point by synchronizing on the start bit edge and re synchronizing on following edges lts operation may be explained simply when the nominal bit time is divided into three segments as follows Synchronisation segment SYNC SEQ a bit change is expected to lie within this time seg ment It has a fixed length of one time quanta 1 X tcan Bit segment 1 BS1
87. ail which is connect ed to the ADC input It is recommended not to change the voltage level or loading on any port pin while conversion is in progress Furthermore it is recommended not to have clocking pins located close to a selected an alog pin WARNING The analog input voltage level must be within the limits stated in the absolute maxi mum ratings 8 3 PORT IMPLEMENTATION The hardware implementation on each I O port de pends onthe settings in the DDR and OR registers and specific feature of the I O port such as ADC In put or true open drain Switching these ports from one state to anoth er should be done in a sequence that prevents un wanted side effects Recommended safe transi tions are illustrated in Figure 26 Other transitions are potentially risky and should be avoided since they are likely to present unwanted side effects such as spurious interrupt generation Figure 26 Interrupt UO Port State Transitions INPUT INPUT OUTPUT OUTPUT floating open drain push pull reset state Ox DDR OR The I O port register configurations are summa rized as follows floating pull up interrupt ST72311R ST72511R ST72512R ST72532R Standard Ports PA5 4 PC7 0 PD7 0 PE7 3 PE1 0 PF7 3 wor fofo C fopen drain 0 Interrupt Ports PA2 0 PB7 5 PB2 0 PF1 0 with pull up pull up ineroptinpat
88. al Clock This bitis set and cleared by software It selects the input clock for the 7 bit prescaler 0 CPU clock 1 External clock Bit 6 4 CC 2 0 Counter Clock Control These bits are set and cleared by software They determine the prescaler division ratio from Where 0 0 fiNPUT 8 MHz fiNPUT 12 4 MHz 14 2 MHz 1 MHz 500 KHz 250 KHz 125 KHz 62 5 KHz finput 8 16 finput 32 finput 64 finput 128 000 3 TCE Timer Counter Enable This bit is set and cleared by software It puts the timer in the lowest power consumption mode 0 Counter stopped prescaler and counter frozen 1 Counter running Bit 2 FCRL Force Counter Re Load This bit is write only and any attempt to read it will yield a logical zero When set it causes the contents of ARR register to be loaded into the counter and the content of the prescaler register to be cleared order to initialize the timer before starting to count Bit 1 OIE Overflow Interrupt Enable This bit is set and cleared by software It allows to enable disable the interrupt which is generated when the OVF bit is set 0 Overflow Interrupt disable 1 Overflow Interrupt enable Bit 0 OVF Overflow Flag This bit is set by hardware and cleared by software reading the CSR register It indicates the transition of the counter from FFh to the ARR value 0 New transition not yet reached 1 Transition reached 5
89. al de the ST7 functional operating modes over tempera vice consumption the two current values must be ture range does not take into account the clock added except for HALT mode LVD supply current HALT mode 12 4 5 On Chip Peripheral Symbol Pamameter 0000 16 bit Timer supply current 8 fopy 8MHz Vos v Von 50V Voo 33V SPI supply current fcpu 8MHz 5 6 Vpp 3 3V 800 ADC supply current when converting 19 fApc 4MHz Notes 1 Typical data are based on 25 2 All I O pins in input mode with a static value at Vpp or Vgs no load LVD disabled 3 Data based on design simulation and or technology characteristics not tested in production All UO pins in input mode with a static value at Vss no load clock input OSC1 driven by external square wave LVD disabled 4 Typical data are based 25 Vpp 5V 5 Data based on characterization results not tested in production 6 Data based on characterization results done with the typical external components not tested in production 7 As the oscillator is based on a current source the consumption does not depend on the voltage 8 Data based on a differential Ion measurement between reset configuration timer counter running at fopy 4 and timer counter stopped selecting external clock capability Data valid for one timer 9 Data based on a differential Ipp
90. art Of RECEPTION Once the CAN controller has syn Frame appears on the CAN bus or the DATA7 chronized itself onto the bus activity itis ready register of the currently active page is written to for reception of new messages Every incoming TRANSMISSION the LOCK bit of a Buffer Message gets Its identifier compared to the ac Control Status Register BCSRx has been set ceptance filters If the bitwise comparison of the and read back as such a transmit job can be selected bits ends up with a match for at least submitted by writing to the DATA7 register The one of the filters then that message is elected for message with the highest priority will be transmit reception and a target buffer is searched for This ted as soon as the CAN bus becomes idle buffer will be the first one order is 1 to 3 that Among those messages with a pending trans has the LOCK and RDY bits of its BCSRx regis mission request the highest priority is given to ter reset Buffer 3 then 2 and 1 If the transmission fails due When no such buffer exists then an overrun to a lost arbitration or to an error while the NRTX generated bit of the CSR register is reset then new trans er of the last message is made available in the mission attempt is performed This goes on until Last Identifier Register LIDHR and LIDLR at the transmission ends successfully or until the least until it gets overwritten by a new identifi job is cancelle
91. ber of bytes required per instruction To do Table 25 ST7 Addressing Mode Overview Hex Bytes Inherent _ EE Ee 9 eem e I Haw foa ie Dwome oes mee wam Se oe JE um mew wer ie Sm erm p How 2 exse IJ ow __ rara wr we m foe eme er m ____ mr m wer wr 125 164 ST72311R ST72511R ST72512R ST72532R INSTRUCTION SET OVERVIEW 11 1 1 Inherent All Inherent instructions consist of a single byte The opcode fully specifies all the required informa tion for the CPU to process the operation TRAP S W Interrupt Wait For Interrupt Low Pow er Mode HALT Halt Oscillator Lowest Power Mode NO WF Siv scr RCF ASP GR PUSHIPOP SLL SRL SRA RLC RRC SWAP Swap Nibbles 11 1 2 Immediate Immediate instructions have two bytes the first byte contains the opcode the second byte con tains the operand value Leger Fia Shift and Rotate Operations ADC ADD SUB SBC Arithmetic Operations 126 164 11 1 3 Direct In Direct instructions the operands are referenced by their memory address The direct addressing mode consists of two sub modes Direct short The address is
92. bit in the SR register is set if a write collision occurs No SPI interrupt is generated when the WCOL bit is set the WCOL bit is a status flag only Clearing the WCOL bit is done through a software sequence see Figure 50 Figure 50 Clearing the WCOL bit Write Collision Flag Software Sequence Clearing sequence after SPIF z 1 end of a data byte transfer ist Step Read SR 2nd Step Read DR WCOLCO Read SR Write DR SPIF 0 WCOL 0 if no transfer has started WCOL 1 if a transfer has started before the 2nd step Clearing sequence before SPIF 1 during a