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ST ST72311R ST72511R ST72512R ST72532R 8-BIT MCU WITH NESTED INTERRUPTS EEPROM ADC 16-BIT TIMERS 8-BIT PWM ART SPI SCI CAN INTERFACES handbook

1. 79 10 5 4 Functional Description 1 81 10 5 5 Low Power Modes ue emper ER RT Kon ee 88 10 5 6 Interi pts RARE RUIT 88 10 5 7 Register DescrptiOn 22 5555 56559650 EE EE ieee Ee 89 3 164 ST72311R ST72511R ST72512R ST72532R 10 6 SERIAL COMMUNICATIONS INTERFACE 5 92 10 621 eege xs x nep quite eed ear tenue x om x Ko is atc ind 92 10 6 2 bx EURO ei xb E tee eee ad 92 10 6 3 General Description 92 10 6 4 Functional Description 94 10 6 5 Low Power 66 5 usid ET dee wae ented prd eas 99 10 6 6 Initerr pts edes e m _______ et di 99 10 6 7 Register Description 100 10 7 CONTROLLER AREA NETWORK CAN 104 10 7 1 Introduction eer PR deg 104 10 7 2 Main Features bes E EELER ea 105 10 7 3 Functional Description 4 105 10 7 4 Register Description 111 10 8 8 BIT A D CONVERTER ADC
2. 138 12 5 3 Crystal and Ceramic Resonator Oscillators 138 12 6 MEMORY CHARACTERISTICS 139 12 6 1 RAM and Hardware Registers 139 12 6 2 EEPROM Data Memory 139 12 6 3 EPROM Program Memory said see tiu RE ER RR RR cae ee 139 127 CHARACTERISTICS 140 12271 Functional EMS cite Dade E 140 12 7 2 Absolute Electrical Sensitivity 141 12 7 3 ESD Pin Protection Strategy 143 12 8 I O PORT PIN CHARACTERISTICS 145 12 8 1 General Characteristics 145 12 8 2 Output Driving Current 146 12 9 CONTROL PIN CHARACTERISTICS 1 147 12 9 1 Asynchronous RESET Pin 147 12 9 2 VPP PIN daaa aeg 147 12 10 TIMER PERIPHERAL 148 12 10 1Watchdog Timer 4 2 E ethene EE Ee 148 12 10 28 Bit PWM ART Auto Reload Timer 148 12 10 31 6 TIMET ode
3. 1 42 85 INTERRUPTS ve te enun et tem aote n e 42 8 5 1 Register Description eR ehe den ed ador wale EE Rae EORR 43 9 MISCELLANEOUS REGISTERS 45 l O PORT INTERRUPT SENSITIVITY ERR AE ead ees 45 9 2 I OPORT ALTERNATE FUNCTIONS 45 9 9 MISCELLANEOUS REGISTERS 55252522555 lt 82524 dea 46 10 15 2 2 2 22 2 2 49 10 WATCHDOG TIMER WDG i 55525555 emo 49 10 1 1 Introducnon 49 10 1 2 Main Features x 25 udo gt 49 10 1 3 Functional Description eek 49 10 1 4 Hardware Watchdog Option 4 50 10 1 5 Low Power MOTOS bee Xx EUR hx 50 10 1 6 ntert pts x sz vede eru y eme 50 10 1 7 Register Description iusso iL RR Enc ch Ree eee ee 50 10 2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER MCC RTO 52 10 2 1 Programmable CPU Clock Prescaler 52 10 2 2 Clock out Capability 52 10 2 3 Real Time Clock Time
4. 1 11 2 EPROM PROGRAM MEMORY 15 3S DATA EEPROM Pr 16 3 1 NITRODUCTION 16 9 2 MAINFEATURES sh pintaa ue 16 33 MEMORY 55 17 34 POWER SAVING MODES 555555555 18 35 ACCESS ERROR HANDLING 2 4 18 36 REGISTER DESGSCHIPTION 19 4 CENTRAL PROCESSING UNIT 20 41 NITRODUCTION 20 42 MAIN FEATURES risans in 20 4 3 HEGISTEHS iiris emata dns Deoa Egan Re Seated RO DR AC a 20 5 SUPPLY RESET AND CLOCK MANAGEMENT 23 51 LOW VOLTAGE DETECTOR 24 5 2 RESET SEQUENCE MANAGER 25 5 2 1 Introd ction e 25 5 2 2 Asynchronous External RESET pin 26 5 2 3 Internal Low Voltage Detection RESET 26 5 2 4 Internal Watchdog RESET 26 53 LOW
5. INPUT INPUT OUTPUT OUTPUT floating open drain push pull reset state Ox DDR OR The I O port register configurations are summa rized as follows floating pull up interrupt ST72311R ST72511R ST72512R ST72532R Standard Ports PA5 4 PC7 0 PD7 0 PE7 3 PE1 0 PF7 3 wor 9 0 tee a drain 0 Interrupt Ports PA2 0 PB7 5 PB2 0 PF1 0 with pull up pull up ineroptinpat 9 drain output 1 9 4 PB3 PF2 without pull up on A Posting weng input 9 opendmouput f e True Open Drain Ports 7 6 floating input open drain high sink ports Pull up Input Port CANTX requirement PE2 pull up input 41 164 ST72311R ST72511R ST72512R ST72532R PORTS 8 4 LOW POWER MODES 8 5 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in CAUSE SE vice LO EXI MOUS the CC register is not active RIM instruction No effect on I O ports External interrupts cause the device to exit from HALT mode Interrupt Event External interrupt on selected external event Table 11 Port Configuration ne woe Se Port E Pot
6. 121 10 8 1 Introd Cllr ce cx S 121 10 8 2 Main Features a dre ee deed ee aed RU RUE E AUR 121 10 8 3 Functional Description piede Re REPRE pee eed 121 10 8 4 Low Power Modes 122 10 8 5 Int rrupts ___________ 122 10 8 6 Register Description 123 11 INSTRUCTIONSET see eee s pF 125 111 577 ADDRESSING MODES 125 14 1 4 Inherent 5e aed dane AN 126 11 12 Immediate RE 4 Y UE dames 126 11 13 DCC ecebue quo bee 126 11 1 4 Indexed No Offset Short Long 126 111 5 Indirect Short Long See eed ond AE ee ee ea 126 11 1 6 Indirect Indexed Short Long 127 11 1 7 Relative mode Direct Indirect 127 11 2 INSTRUCTION GROUPS 1 128 12 ELECTRICAL CHARACTERISTICS 131 12 1 PARAMETER CONDITIONS 1 131 12 1 1 Minimum and Maximum values 131 12 1 2 Typical values x toes daa 131 12 1 3 Typical
7. sa ea Seier ou sm sanies en Para nit ars Ass en omar swine Pine swap 130 164 7572 12 ELECTRICAL CHARACTERISTICS 12 1 PARAMETER CONDITIONS Unless otherwise specified all voltages are re ferred to Vas 12 1 1 Minimum and Maximum values Unless otherwise specified the minimum and max imum values are guaranteed in the worst condi tions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at 25 and given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the min imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation 3 gt 12 1 2 Typical values Unless otherwise specified typical data are based on 25 Vpp 5V for the 4 5V lt Vpp lt 5 5V voltage range and Vpp 3 3V for the 3V lt Vpp lt 4V voltage range They are given only as design guidelines and are not tested 12 1 3 Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not te
8. a ses RR E eS bx deed RR UE RR RN 131 12 1 4 Loading capacitor 131 12 1 5 Pin input voltage 1 131 12 2 ABSOLUTE MAXIMUM RATINGS 132 12 2 1 Voltage Characteristics 132 12 2 2 Current Characteristics 132 12 2 3 Thermal Characteristics 132 12 8 OPERATING CONDITIONS 1 133 12 3 1 General Operating Conditions 133 12 3 2 Operating Conditions with Low Voltage Detector LVD 134 12 4 SUPPLY CURRENT CHARACTERISTICS 135 12 4 1 RUN SLOW Modes 1 135 12 4 2 WAIT SLOW WAIT Modes 136 4 164 57 ST72311R ST72511R ST72512R ST72532R 12 4 3 HALT and ACTIVE HALT Modes 137 12 4 4 Supply and Clock Managers 137 12 4 5 On Chip Peripheral 2 525542 p ma ees 137 12 5 CLOCK AND TIMING CHARACTERISTICS 138 1254 General TIMINGS csse AE d d are edema 138 12 5 2 External Clock Source
9. These 2 bits can be written only when 11 and 10 of the CC register are both set to 1 level 3 Bit 2 1 CP 1 0 CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes Their action is conditioned by the setting of the SMS bit These two bits are set and cleared by software 0 Bit 0 SMS S ow mode select This bit is set and cleared by software 0 Normal mode fopy fosc 2 1 Slow mode fcpy is given by CP1 CPO See Section 7 2 SLOW MODE on page 34 and Section 10 2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER MCC RTC on page 52 for more details 3 MISCELLANEOUS REGISTERS Cont d MISCELLANEOUS REGISTER 2 MISCR2 Read Write Reset Value 0000 0000 00h 7 0 P Bit 7 IPA nterrupt polarity for port A This bit is used to invert the sensitivity of the port A 3 0 external interrupts It is set and cleared by software 0 No sensitivity inversion 1 Sensitivity inversion See Section 9 1 PORT INTERRUPT SENSI TIVITY on page 45 and the description of the IS2x bits of the MISCR1 register for more details Bit 6 IPB nterrupt polarity for port B This bit is used to invert the sensitivity of the port B 3 0 external interrupts It is set and cleared by software 0 No sensitivity inversion 1 Sensitivity inversion See Section 9 1 I O PORT INTERRUPT SENSI TIVITY on page 45 and
10. 12 4 1 RUN and SLOW Modes Parameter Ust 5 4 fosc 1 MHz fcpu 500kHz 2 fosc 4MHz 2 2 9 fosc 1 6MHz fcpy 8MHz 20 fosc 1MHz fcpu 31 25kHz 0 5 fosc 4MHz fopy 125kHz 2 0 fogc 16MHz 500 2 3 0 fosc 1MHz 500 2 24 fosc 4MHz 2 2 54 fosc 16MHz fopy 8MHz 12 fosc 1 MHz fcpu 31 25kHz fosc 4MHz fcpu 1 25kHz fosc 1 6MHz fcpu 500kHz Supply current in RUN mode 3 see Figure 69 Supply current in SLOW mode see Figure 70 Supply current in RUN mode 3 see Figure 69 Supply current in SLOW mode 4 see Figure 70 3 lt lt 3 6 4 5 lt lt 5 5 Figure 69 Typical Ipp in RUN vs Figure 70 Typical Ipp SLOW vs feu IDD mA 20 Notes 1 Typical data are based on 25 Vpp 5V 4 5V lt Vpps5 5V range and Vpp 3 3V 3 lt lt 3 6 range 2 Data based on characterization results tested in production at Vpp max and fcpy 3 CPU running with memory access all I O pins in input mode with a static value at Vpp or no load all peripherals switched off clock input OSC1 driven by external square wave LVD disabled 4 SLOW mode selected with fopy based on fogc divided by 32 All I O pins in input mode with a static value at Vpp or Vss no load all peripherals switched off clock input OSC1 driven by external square wave LVD disabled 437 135 164 ST
11. 5 _ faan cP compare A meron sra fa fw fares __ bee w mer arse eme Ferr eur amp iors me stre same cu onum oar sawone eae am om D on wan oec 2099 08 _ fromen gt eran ar eere IST Lag tor SINT pisci Lm BNT pno Lm S Lm noone Lmw puwerno s noen ESCHER EELER EECHER n arco 2 17 meros fe O fe amoro uses aeren ESCHER 1 129 164 ST72311R ST72511R ST72512R ST72532R INSTRUCTION SET OVERVIEW Cont d Bessnion quee WEG _ negate scm ram wor Fon onoeaion pee mr Je semaemun J Ene meras mS rome etme oho ma Emo fot antine m ase _ Sack Ponte alowed mr sw sabe
12. INPUT CAPTURE 2 LOW REGISTER 2 Read Only Reset Value Undefined This is an 8 bit read only register that contains the low part of the counter value transferred by the In put Capture 2 event 7 0 77 164 ST72311R ST72511R ST72512R ST72532R 16 BIT TIMER Cont d Table 19 16 Bit Timer Register Map and Reset Values pa ird icd S E pa Address Register Hex Label Timer A 32 CR1 Ge Timer B 42 Reset Value Timer A 31 CR2 i Timer B 41 Reset Value Timer A 33 ICF1 Timer B 43 Reset Value Timer A 34 ICHR1 Timer B 44 Reset Value Timer 35 ICLR1 Timer B 45 Reset Value Timer A 36 OCHR1 Timer B 46 Reset Value Timer A 37 OCLR1 Timer 47 Reset Value Timer OCHR2 Timer B 4 Reset Value Timer A OCLR2 Timer B 4F Reset Value Timer A 38 CHR Timer B 48 Reset Value Timer A 39 CLR Timer B 49 Reset Value Timer ACHR Timer 4 Reset Value Timer A 3B ACLR M Timer B 4 Reset Value Timer A 3C ICHR2 Timer B 40 Reset Value Timer A 3D ICLR2 Timer B 4D Reset Value OCIE 0 OC2E 0 OCF1 Ee 15 i 78 164 3 10 5 SERIAL PERIPHERAL INTERFACE SPI 10 5 1 Introduction The Serial Peripheral Interface SPI allows full duplex synchronous serial communication with external devices An SPI system may consist of a master and one or more slaves or a system in which de
13. 27 6 INTERRUPTS uie RR xe egere ase wan om x e ene 28 6 1 INTRODUGTION oe So ore Seba Ta 28 6 2 MASKING AND PROCESSING 28 6 3 INTERRUPTS AND LOW POWER MODES 30 6 4 CONCURRENT 8 NESTED MANAGEMENT 30 6 5 INTERRUPT REGISTER DESCRIPTION 31 POWER SAVING MODES tite edhe ee tee 34 7 1 INTRODUCTION ace eed Reate ol ee oh ee dee 34 7 2 SLOW MODE 34 OC NM EE 35 7 4 AND HALT MODES 36 7 4 4 ACTIVE HALT 36 1 4 2 MODE uge evi Ce A epi 37 8 VO PORTS ee 38 8 1 INTRODUCTION edad 38 8 2 FUNCTIONAL DESCRIPTION 1 38 8 2 T MPU MOES RU ech a lk 38 8 2 2 Output Modes 1 1 2 1 38 8 2 3 Alternate Functions 38 2 164 5 Table of Contents 8 3 I O PORT IMPLEMENTATION 41 84 LOW POWER MODES
14. 1 Reading the SR register while the TOF bit is set 2 An access read or write to the CLR register Notes The TOF bit is not cleared by accesses to ACLR register The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times for example to measure elapsed time with out the risk of clearing the TOF bit erroneously The timer is not affected by WAIT mode In HALT mode the counter stops counting until the mode is exited Counting then resumes from the previous count MCU awakened by an interrupt or from the reset count MCU awakened by a Reset 10 4 3 2 External Clock The external clock where available is selected if 1 and CC1 1 in CR2 register The status of the EXEDG bit in the CR2 register determines the type of leveltransition on the exter nal clock pin EXTCLK that will trigger the free run ning counter The counter is synchronised with the falling edge of the internal CPU clock A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock thus the external clock fre quency must be less than a quarter of the CPU clock frequency 63 164 ST72311R ST72511R ST72512R ST72532R 16 BIT TIMER Cont d Figure 36 Counter Timing Diagram internal clock divided by 2 INTERN
15. 577 23156 11 Ga ST72311R ST72511R 77 ST72512R ST72532R 8 BIT MCU WITH NESTED INTERRUPTS EEPROM ADC 16 BIT TIMERS 8 BIT PWM ART SPI SCI CAN INTERFACES DATASHEET m Memories 16K to 60K bytes A ram memory ROM OTP and EPROM with read out KE 256 bytes E7PROM Data memory only on ST72532R4 1024 to 2048 bytes RAM m Clock Reset and Supply Management Enhanced reset system Low voltage supply supervisor Clock sources crystal ceramic resonator os cillator or external clock Beep and Clock out capability 4 Power paving Modes Halt Active Halt Wait and Slow m Interrupt Management Nested interrupt controller 13 interrupt vectors plus TRAP and RESET TQFP64 14 x 14 m 3 Communications Interfaces SPI synchronous serial interface SCI asynchronous serial interface 15 external interrupt lines on 4 vectors CAN interface except on ST72311Rx TLI dedicated top level interrupt pin 1 Analog peripheral Ports mE 8 bit ADC with 8 input channels 48 multifunctional bidirectional I O lines Instruction Set 32 alternate function lines 12 high sink outputs m 5 Timers Configurable watchdog timer Real time clock timer 8 bit data manipulation 63 basic instructions 17 main addressing modes 8 8 unsigned multiply instruction True bit manipulation One 8 bit auto reload timer with 4
16. 0 Interrupt is inhibited 1 An SPI interrupt is generated whenever SPIF 1 or MODF 1 in the SR register Bit 6 SPE Serial peripheral output enable This bit is set and cleared by software It is also cleared by hardware when in master mode 55 0 see Section 10 5 4 5 Master Mode Fault on page 85 0 I O port connected to pins 1 SPI alternate functions connected to pins The SPE bit is cleared by reset so the SPI periph eral is not initially connected to the external pins Bit 5 SPR2 Divider Enable this bit is set and cleared by software and it is cleared by reset It is used with the SPR 1 0 bits to set the baud rate Refer to Table 20 0 Divider by 2 enabled 1 Divider by 2 disabled Bit 4 MSTR Master This bit is set and cleared by software It is also cleared by hardware when in master mode 55 0 see Section 10 5 4 5 Master Mode Fault on page 85 0 Slave mode is selected 1 Master mode is selected the function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are re versed ST72311R ST72511R ST72512R ST72532R Bit 3 CPOL Clock polarity This bit is set and cleared by software This bit de termines the steady state of the serial Clock The CPOL bit affects both the master and slave modes 0 The steady state is a low value at the SCK pin 1 The steady state is a high value at the SCK pin Bit 2 CPHA Clock phase This bit i
17. HW Registers see Table 2 1024 Bytes RAM 1536 Bytes RAM 2048 Bytes RAM Reserved Optional EEPROM 256 Bytes Program Memory 60K 48K 32K 16K Bytes Interrupt amp Reset Vectors see Table 7 on page 32 ST72311R ST72511R ST72512R ST72532R 60Kbytes of user program memory The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh The highest address bytes contain the user reset and interrupt vectors 0080h Short Addressing RAM zero page OOFFh 0100h Stack 256 Bytes 0200h 16 bit Addressing 047Fh or 067Fh 40 087Fh 60 KBytes 48 KBytes 16 KBytes 11 164 ST72311R ST72511R ST72512R ST72532R Table 2 Hardware Register Map Register Address Label Register Name Port A Data Register Port A Data Direction Register Port A Option Register Reserved Area 1 Byte Port C Data Register ooh Port C Data Direction Register 00h R W Port C Option Register 00h R W Reserved Area 1 Byte Port B Data Register ooh Port B Data Direction Register 00h R W Port B Option Register 00h R W Reserved Area 1 Byte Port E Data Register 00h 1 Port E Data Direction Register 00h Port E Option Register 00h Reserved Area 1 Byte Port D Data Register Ooh Port D Data Direction Register 00h R W Port D Option Register 00h R W Reserved Area 1 Byte Port F Data Register ooh Port F Data Direction Register 00h R W Port
18. Lo Note this TR factor is used only when the ETPR fine tuning factor is equal to 00h otherwise TR is replaced by the ETPR dividing factor Bit 2 0 SCR 2 0 SC Receiver rate divisor These 3 bits in conjunction with the SCP1 amp SCPO bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode RR dividi factor SCR2 SCR1 SCRO Note this RR factor is used only when the ERPR fine tuning factor is equal to 00h otherwise RR is replaced by the ERPR dividing factor 3 SERIAL COMMUNICATIONS INTERFACE Cont d EXTENDED RECEIVE PRESCALER DIVISION REGISTER ERPR Read Write Reset Value 0000 0000 00h Allows setting of the Extended Prescaler rate divi sion factor for the receive circuit 7 0 ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR 7 6 5 4 3 2 1 0 Bit 7 1 ERPR 7 0 8 bit Extended Receive Pres caler Register The extended Baud Rate Generator is activated when a value different from is stored in this register Therefore the clock frequency issued from the 16 divider see Figure 54 is divided by the binary factor set in the ERPR register in the range 1 to 255 The extended baud rate generator is not used af ter a reset Table 22 SCI Register Map and Reset Values SCISR TC RDRF Reset Value 1 SCIDR MSB ST72311R ST72511R ST72512R ST72532R EXTENDED TRANSMIT PRESCALER DIVISION REGISTER
19. Reset by hardware when all error interrupt flags have been cleared Caution Interrupt flags are reset by writing a 0 to the cor responding bit position The appropriate way con sists in writing an immediate mask or the one s com plement of the register content initially read by the interrupt handler Bit manipulation instruction BRES should never be used due to its read modify write nature 111 164 ST72311R ST72511R ST72512R ST72532R CONTROLLER AREA NETWORK Cont d INTERRUPT CONTROL REGISTER ICR Read Write Reset Value 00h 7 0 Cal ESCI RXIE TXIE SCIE ORIE erc Bit 6 ESCI Extended Status Change Interrupt Read Set Clear Set by software to specify that SCIF is to be set on receive errors also Cleared by software to set SCIF only on status changes and wake up but not on all receive errors Bit 5 RXIE Receive Interrupt Enable Read Set Clear Set by software to enable an interrupt request whenever a message has been received free of er rors Cleared by software to disable receive interrupt re quests Bit 4 2 TXIE Transmit Interrupt Enable Read Set Clear Set by software to enable an interrupt request whenever a message has been successfully trans mitted Cleared by software to disable transmit interrupt requests 112 164 Bit 3 SCIE Status Change Interrupt Enable Read Set Clear Set by software to enable an interrupt request whenever the node s status ch
20. These two read only 16 bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit Timer overflow flag located in the Status register SR see note at the end of paragraph titled 16 bit read sequence Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value Both counters have a reset value of FFFCh this is the only value which is reloaded in the 16 bit tim er The reset value of both counters is also FFFCh in One Pulse mode and PWM mode The timer clock depends on the clock control bits of the CR2 register as illustrated in Table 18 Clock Control Bits The value in the counter register re peats every 131 072 262 144 or 524 288 CPU clock cycles depending on the CC 1 0 bits The timer frequency can be 2 fcpu 4 fep 8 or an external frequency 61 164 ST72311R ST72511R ST72512R ST72532R 16 BIT TIMER Cont d Figure 35 Timer Block Diagram ST7 INTERNAL BUS MCU PERIPHERAL INTERFACE OUTPUT OUTPUT INPUT COUNTER compare COMPARE CAPTURE CAPTURE REGISTER REGISTER REGISTER REGISTER REGISTER 2 1 2 ALTERNATE pin COUNTER A A REGISTER CC 1 0 TIMER INTERNAL BUS mE UT COMPARE E DETECT EDGE DETECT CIRCUIT2 LHL P LATCH tidy perd o 0 im 2 LATCH2 Status EUN SR OVERFLOW DETECT CIRCUIT Control Register
21. This frequency source is selected through the EXCL bit of the CSR register and can be either the or an external input frequency The clock input to the counter is enabled by the TCE Timer Counter Enable bit in the CSR regis ter When TCE is reset the counter is stopped and the prescaler and counter contents are frozen Figure 31 Output compare control ST72311R ST72511R ST72512R ST72532R When TCE is set the counter runs at the rate of the selected clock source Counter and Prescaler Initialization After RESET the counter and the prescaler are cleared and fiNPUT fopu The counter can be initialized by Writing to the ARR register and then setting the FCRL Force Counter Re Load and the TCE Timer Counter Enable bits in the CSR register Writing to the CAR counter access register In both cases the 7 bit prescaler is also cleared whereupon counting will start from a known value Direct access to the prescaler is not possible Output compare control The timer compare function is based on four differ ent comparisons with the counter one for each output Each comparison is made be tween the counter value and an output compare register OCRx value This OCRx register can not be accessed directly it is loaded from the duty cy cle register DCRx at each overflow of the coun ter This double buffering method avoids glitch gener ation when changing the d
22. 2 The suggested 10nF 0 1uF decoupling capacitors on the power supply lines are proposed as a good price vs EMC performance tradeoff They have to be put as close as possible to the device power supply pins Other EMC recommen dations are given in other sections 5 RESET OSCx pin characteristics 140 164 4 CHARACTERISTICS Cont d 12 7 2 Absolute Electrical Sensitivity Based on three different tests ESD LU and DLU using specific measurement methods the product is stressed in order to determine its performance in terms of electrical sensitivity For more details re fer to the AN1181 ST7 application note 12 7 2 1 Electro Static Discharge ESD Electro Static Discharges 3 positive then 3 nega tive pulses separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends of the number of supply pins of the device 3 parts n 1 supply pin Two models are usually simulated Human Body Model and Machine Model This test conforms to the JESD22 A114A A115A standard See Figure 75 and the following test sequences Human Body Model Test Sequence C is loaded through S1 by the HV pulse gener ator 51 switches position from generator to Adischarge from C through R bogy resistance to the ST7 occurs 52 must be closed 10 to 100ms after the pulse delivery period to ensure the ST7 is not left in charge state S2 must be opened leas
23. 0 No effect on the 1 pin 1 Forces OLVL 1 to be copied to the pin if the OC1E bit is set and even if there is no suc cessful comparison Bit 2 OLVL2 Output Level 2 This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R reg ister and is set in the CR2 register This val ue is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode Bit 1 IEDG1 nput Edge 1 This bit determines which type of level transition on the pin will trigger the capture 0 A falling edge triggers the capture 1 A rising edge triggers the capture Bit 0 OLVL1 Output Level 1 The OLVL1 bit is copied to the pin when ever a successful comparison occurs with the register and the OC1E bit is set in the CR2 register 3 16 BIT Cont d CONTROL REGISTER 2 CR2 Read Write Reset Value 0000 0000 00h 7 0 Bit 7 OC1E Output Compare 1 Pin Enable This bit is used only to output the signal from the timer on the OCMP1 pin OLV1 in Output Com pare mode both OLV1 and OLV2 in PWM and one pulse mode Whatever the value ofthe OC1E bit the Output Compare 1 function of the timer re mains active 0 1 pin alternate function disabled I O pin free for general purpose 1 OCMP1 pin alternate function enabled Bit 6 OC2E Output Compare 2 Pin Enable This bit is used only to output the signal from the
24. 10 1 7 Register Description CONTROL REGISTER CR Read Write Reset Value 0111 1111 7Fh 7 0 Bit 7 WDGA Activation bit This bit is set by software and only cleared by hardware after a reset When WDGA 1 the watchdog can generate a reset 0 Watchdog disabled 1 Watchdog enabled Note This bit is not used if the hardware watch dog option is enabled by option byte Bit 6 0 T 6 0 7 bit timer MSB to LSB These bits contain the decremented value A reset is produced when it rolls over from 40h to 3Fh T6 becomes cleared STATUS REGISTER SR Read Write Reset Value 0000 0000 00h 7 0 Bit 0 WDOGF Watchdog flag This bit is set by a watchdog reset and cleared by software or a power on off reset This bit is useful for distinguishing power on off or external reset and watchdog reset 0 No Watchdog reset occurred 1 Watchdog reset occurred Only by software and power on off reset Note This register is not used in versions without LVD Reset 3 ST72311R ST72511R ST72512R ST72532R WATCHDOG TIMER Cond t Table 15 Watchdog Timer Register Map and Reset Values Address Register Hex Label WDGCR WDGA Spann Reset Value A WDGSR 002Bh Reset Value x 51 164 ST72311R ST72511R ST72512R ST72532R 10 2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER MCC RTC The Main Clock Controller consists of three differ ent functions m a programmable CPU clock presc
25. ble This bit is set and cleared by software 0 interrupt is inhibited ST72311R ST72511R ST72512R ST72532R 1 SCI interruptis generated whenever TC 1 in the SR register Bit 5 RIE Receiver interrupt enable This bit is set and cleared by software 0 interrupt is inhibited 1 An interrupt is generated whenever OR 1 or RDRF 1 in the SR register Bit 4 ILIE dle line interrupt enable This bit is set and cleared by software 0 interrupt is inhibited 1 An SCI interrupt is generated whenever IDLE 1 in the SR register Bit 3 TE Transmitter enable This bit enables the transmitter and assigns the TDO pin to the alternate function It is set and cleared by software 0 Transmitter is disabled the TDO pin is back to the I O port configuration 1 Transmitter is enabled Note during transmission a 0 pulse on the TE bit followed by 1 sends a preamble after the current word Bit 2 RE Receiver enable This bit enables the receiver It is set and cleared by software 0 Receiver is disabled it resets the RDRF IDLE OR NF and FE bits of the SR register 1 Receiver is enabled and begins searching for a start bit Bit 1 RWU Receiver wake up This bit determines if the SCI is in mute mode or not It is set and cleared by software and can be cleared by hardware when a wake up sequence is recognized 0 Receiver in active mode 1 Receiver in mute mode Bit 0 SBK
26. idle frame is detected there is the same procedure as a data received character plus an in terrupt if the ILIE bit is set and the bit is cleared in the CCR register 96 164 Overrun Error An overrun error occurs when a character is re ceived when RDRF has not been reset Data can not be transferred from the shift register to the TDR register as long as the RDRF bit is not cleared When overrun error occurs The OR bit is set The RDR content will not be lost The shift register will be overwritten Aninterrupt is generated if the RIE bitis set and the bit is cleared in the CCR register The OR bit is reset by an access to the SR register followed by a DR register read operation Noise Error Oversampling techniques are used for data recov ery by discriminating between valid incoming data and noise When noise is detected in a frame The NF 15 set at the rising edge of the RDRF bit Data is transferred from the Shift register to the DR register No interrupt is generated However this bit rises at the same time as the bit which itself generates an interrupt The NF bit is reset by a SR register read operation followed by a DR register read operation Framing Error A framing error is detected when The stop bit is not recognized on reception at the expected time following either a de synchroni zation or excessive noise A break is received When the fra
27. located in memory point er The pointer address follows the opcode The indi rect addressing mode consists of two sub modes Indirect short The pointer address is a byte the pointer size is a byte thus allowing 00 FF addressing space and requires 1 byte after the opcode Indirect long The pointer address is a byte the pointer size is a word thus allowing 64 Kbyte addressing space and requires 1 byte after the opcode r INSTRUCTION SET OVERVIEW 11 1 6 Indirect Indexed Short Long This is a combination of indirect and short indexed addressing modes The operand is referenced by its memory address which is defined by the un signed addition of an index register value X or Y with a pointer value located in memory The point er address follows the opcode The indirect indexed addressing mode consists of two sub modes Indirect Indexed Short The pointer address is a byte the pointer size is a byte thus allowing 00 1FE addressing space and requires 1 byte after the opcode Indirect Indexed Long The pointer address is a byte the pointer size is a word thus allowing 64 Kbyte addressing space and requires 1 byte after the opcode Table 26 Instructions Supporting Direct Indexed Indirect and Indirect Indexed Addressing Modes dmn ge Instructions ADC ADD SUB SBC Arithmetic Additions Sub stractions operations D P Bir Compare Short Instructions Only BTJT
28. timer on the OCMP2 pin OLV2 in Output Com pare mode Whatever the value of the OC2E bit the Output Compare 2 function of the timer re mains active 0 2 pin alternate function disabled I O pin free for general purpose 1 OCMP2 pin alternate function enabled Bit 5 OPM One Pulse Mode 0 One Pulse Mode is not active 1 One Pulse Mode is active the ICAP1 pin can be used to trigger one pulse on the pin the active transition is given by the IEDG1 bit The length of the generated pulse depends on the contents of the register ST72311R ST72511R ST72512R ST72532R Bit 4 PWM Pulse Width Modulation 0 PWM mode is not active 1 PWM mode is active the OCMP1 pin outputs a programmable cyclic signal the length of the pulse depends on the value of OC1R register the period depends on the value of OC2R regis ter Bit 3 2 CC 1 0 Clock Control The timer clock mode depends on these bits Table 18 Clock Control Bits External Clock where available Note If the external clock pin is not available pro gramming the external clock configuration stops the counter Bit 1 IEDG2 Input Edge 2 This bit determines which type of level transition on the ICAP2 pin will trigger the capture 0 A falling edge triggers the capture 1 A rising edge triggers the capture Bit 0 EXEDG External Clock Edge This bit determines which type of level transition on the exter
29. war wer Conction Fag moa sm nw scr mr Using a pre byte The instructions are described with one to four op codes These prebytes enable instruction in Y as well as indirect addressing modes to be implemented In order to extend the number of available op codes for an 8 bit CPU 256 opcodes three differ ent prebyte opcodes are defined These prebytes modify the meaning of the instruction they pre cede The whole instruction becomes PC 2 End of previous instruction PC 1 Prebyte PC opcode PC 1 Additional word 0 to 2 according to the number of bytes required to compute the ef fective address 128 164 They precede the opcode of the instruction in X or the instruction using direct addressing mode The prebytes are PDY 90 Replace an X based instruction using immediate direct indexed or inherent ad dressing mode by a Y one PIX 92 Replace an instruction using di rect direct bit or direct relative addressing mode to an instruction using the corresponding indirect addressing mode It also changes an instruction using X indexed ad dressing mode to an instruction using indirect X in dexed addressing mode PIY 91 Replace an instruction using X in direct indexed addressing mode by a Y one 3 ST72311R ST72511R ST72512R ST72532R INSTRUCTION SET OVERVIEW Cont d Seier sre Iren _ a x00 fanon
30. when executed while the Watchdog system is en abled can generate a Watchdog RESET see Section 14 1 on page 158 for more details Figure 23 HALT Timing Overview RUN HALT 4096 CPU CYCLE HALT INTERRUPT INSTRUCTION MCCSR OIE 0 FETCH VECTOR ST72311R ST72511R ST72512R ST72532R Figure 24 HALT Mode Flow chart HALT INSTRUCTION MCCSR OIE 0 ENABLE DISABLE OSCILLATOR OFF PERIPHERALS 2 OFF CPU OFF I 1 0 BITS 10 CPU I 1 0 BITS OSCILLATOR ON PERIPHERALS ON CPU ON I 1 0 BITS XX 4 FETCH RESET VECTOR OR SERVICE INTERRUPT Notes 1 WDGHALT is an option bit See option byte sec tion for more details 2 Peripheral clocked with an external clock source can still be active 3 Only some specific interrupts can exit the MCU from HALT mode such as external interrupt Re fer to Table 7 Interrupt Mapping on page 32 for more details 4 Before servicing an interrupt the CC register is pushed on the stack The I 1 0 bits of the CC reg ister are set to the current software priority level of the interrupt routine and recovered when the CC register is popped 37 164 ST72311R ST72511R ST72512R ST72532R 8 PORTS 8 1 INTRODUCTION The ports offer different functional modes transfer of data through digital inputs and outputs and for specific pins external interrupt generation alternate signal input output for the on chip pe ripherals
31. 0 The result of the last operation is positive or null 1 The result of the last operation is negative i e the most significant bit is a logic 1 This bit is accessed by the JRMI and JRPL instruc tions ST72311R ST72511R ST72512R ST72532R Bit 1 2 Z Zero This bit is set and cleared by hardware This bit in dicates that the result of the last arithmetic logical or data manipulation is zero 0 The result of the last operation is different from Zero 1 The result of the last operation is zero This bit is accessed by the JREQ and JRNE test instructions Bit 0 C Carry borrow This bit is set and cleared by hardware and soft ware It indicates an overflow or an underflow has occurred during the last arithmetic operation 0 No overflow or underflow has occurred 1 An overflow or underflow has occurred This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions It is also affected by the bit test and branch shift and rotate instructions Interrupt management bits Bit 5 3 10 nterrupt The combination of the land 10 bits gives the cur rent interrupt software priority interrupt Software Priority n 0 _____ Level 2 Level 3 interrupt disable These two bits are set cleared by hardware when entering in interrupt The loaded value is given by the corresponding bits in the interrupt software pri ority registers IXSPR They
32. 002Ch Es Reset Value 19 164 ST72311R ST72511R ST72512R ST72532R 4 CENTRAL PROCESSING UNIT 4 1 INTRODUCTION This CPU has a full 8 bit architecture and contains six internal registers allowing efficient 8 bit data manipulation 4 2 MAIN FEATURES m Enable executing 63 basic instructions m Fast 8 bit by 8 bit multiply 17 main addressing modes addressing mode Two 8 bit index registers 16 bit stack pointer Low power HALT and WAIT modes Priority maskable hardware interrupts Non maskable software hardware interrupts indirect with Figure 7 CPU Registers RESET VALUE XXh 7 0 RESET VALUE XXh 7 RESET VALUE XXh 115 8 7 0 RESET VALUE RESET VECTOR FFFEh FFFFh 7 0 1 1 2 lt RESET VALUE 1 1 1 X 1 X X X 15 8i7 0 RESET VALUE STACK HIGHER ADDRESS 20 164 4 3 CPU REGISTERS The 6 CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions Accumulator A The Accumulator is an 8 bit general purpose reg ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data Index Registers X and Y These 8 bit registers are used to create effective addresses or as temporary storage areas for data manipulation The Cross Assembler generates a precede instruction PRE to indicate that the fol lowing instruction refers to the Y register The Y register is not
33. An I O port contains up to 8 pins Each pin can be programmed independently as digital input with or without interrupt generation or digital output 8 2 FUNCTIONAL DESCRIPTION Each port has 2 main registers Data Register DR Data Direction Register DDR and one optional register Option Register OR Each may be programmed using the corre sponding register bits in the DDR and OR regis ters bit X corresponding to pin X of the port The same correspondence is used for the DR register The following description takes into account the OR register for specific ports which do not pro vide this register refer to the I O Port Implementa tion section The generic block diagram is shown in Figure 25 8 2 1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit In this case reading the DR register returns the digital value applied to the external pin Different input modes can be selected by software through the OR register Notes 1 Writing the DR register modifies the latch value but does not affect the pin status 2 When switching from input to output mode the DR register has to be written first to drive the cor rect level on the pin as soon as the port is config ured as an output External interrupt function When an is configured as Input with Interrupt an event on this I O can generate an external inter rupt request t
34. BTJF Bit Test and Jump Opera tions SLL SRL SRA RLC Shift and Rotate Opera RRC tions SWAP Swap Nibbles CALL JP Call or Jump subroutine ST72311R ST72511R ST72512R ST72532R 11 1 7 Relative mode Direct Indirect This addressing mode is used to modify the PC register value by adding an 8 bit signed offset to it Available Relative Direct Indirect Instructions Conditional Jump CALLR Call Relative The relative addressing mode consists of two sub modes Relative Direct The offset is following the opcode Relative Indirect The offset is defined in memory which address follows the opcode 127 164 ST72311R ST72511R ST72512R ST72532R INSTRUCTION SET OVERVIEW Cont d 11 2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions The instructions may toad and Im eR J Stack operation Push pop asp IncremenvDecrememt wc oc p _ be subdivided into 13 main groups as illustrated the following table Compare and Tests 0 PT eer J Logical operations AND jor cre NG Bit Operation Leer eres cona mur operators sus sec wx Sinara noes sm sm arc ow s Condon trance managemen Jg we
35. Bit Timing Register R W CANPSR CAN Page Selection Register R W First address See CAN to Description Last address of CAN page X PWMDCR3 PWM AR Timer Duty Cycle Register 3 PWMDCR2 PWM AR Timer Duty Cycle Register 2 PWMDCR1 PWM AR Timer Duty Cycle Register 1 PWMDCRO PWM AR Timer Duty Cycle Register 0 PWM ART pwMcR AR Timer Control Register ARTCSR Auto Reload Timer Control Status Register ARTCAR Auto Reload Timer Counter Access Register ARTARR Auto Reload Timer Auto Reload Register Reserved Area 6 Bytes Legend x undefined R W read write Notes 1 The contents of the port DR registers are readable only in output configuration In input configura tion the values of the pins are returned instead of the DR register contents 2 The bits associated with unavailable pins must always keep their reset value 14 164 3 2 EPROM PROGRAM MEMORY The program memory of the OTP and EPROM de vices can be programmed with EPROM program ming tools available from STMicroelectronics EPROM Erasure EPROM devices are erased by exposure to high intensity UV light admitted through the transparent window This exposure discharges the floating gate to its initial state through induced photo cur rent It is recommended that the EPROM devices be kept out of direct sunlight since the UV content of ST72311R ST72511R ST72512R ST72532R sunlight can be sufficient to cause functional fail ure Exte
36. CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i OCR COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i OCF OLVLi 1 2 2ED3 69 164 ST72311R ST72511R ST72512R ST72532R 16 BIT TIMER Cont d 10 4 3 5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs This mode is selected via the OPM bit in the CR2 register The one pulse mode uses the Input Capture function and the Output Compare function Procedure To use one pulse mode 1 Load the register with the value corre sponding to the length of the pulse see the for mula in the opposite column 2 Select the following in the CR1 register Using the OLVL 1 bit select the level to be ap plied to the pin after the pulse Using the OLVL2 bit select the level to be ap plied to the pin during the pulse Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit the ICAP1 pin must be configured as floating input 3 Select the following in the CR2 register Set the OC1E bit the pin is then ded icated to the Output Compare 1 function Set the OPM bit Select the timer clock CC 1 0 see Table 18 Clock Control Bits One pulse mode cycle When event occurs on ICAP1 1 OLVL2 Counter is reset to FFFCh ICF1 bit is set OCMP1 OLVL1 Then on a
37. F Note when the CANTX alternate function is selected the IO port operates in output push pull mode 3 42 164 PORTS Cont d 8 5 1 Register Description DATA REGISTER DR Port x Data Register PxDR with x A B C D E or F Read Write Reset Value 0000 0000 00h 7 0 ST72311R ST72511R ST72512R ST72532R OPTION REGISTER OR Port x Option Register PxOR with D or F Read Write Reset Value 0000 0000 00h 7 0 Bit 7 0 D 7 0 Data register 8 bits The DR register has a specific behaviour accord ing to the selected input output configuration Writ ing the DR register is always taken into account even ifthe pin is configured as an input this allows to always have the expected level on the pin when toggling to output mode Reading the DR register returns either the DR register latch content pin configured as output or the digital value applied to the I O pin pin configured as input DATA DIRECTION REGISTER DDR Port x Data Direction Register PxDDR with x A B C D E or F Read Write Reset Value 0000 0000 00h 0 Bit 7 0 DD 7 0 Data direction register 8 bits The DDR register gives the input output direction configuration of the pins Each bits is set and cleared by software 0 Input mode 1 Output mode Bit 7 0 O 7 0 Option register 8 bits For specific I O pins this register is not implement ed In this case the DDR register is en
38. Figure 53 TDO Transmit Data Output When the transmit ter is disabled the output pin returns to its port configuration When the transmitter is ena bled and nothing is to be transmitted the TDO pin is at high level RDI Receive Data Input is the serial data input Oversampling techniques are used for data re covery by discriminating between valid incoming data and noise Through this pins serial data is transmitted and re ceived as frames comprising An Idle Line prior to transmission or reception A start bit A data word 8 or 9 bits least significant bit first A Stop bit indicating that the frame is complete This interface usestwo types ofbaud rate generator A conventional type for commonly used baud rates An extended type with a prescaler offering a very wide range of baud rates even with non standard oscillator frequencies 3 ST72311R ST72511R ST72512R ST72532R SERIAL COMMUNICATIONS INTERFACE Cont d Figure 52 SCI Block Diagram DATA REGISTER DR D ved Shift Regi p E 5 E AKE UP NIT W TRANSMIT RECEIVER RECEIVER CONTROL U CONTROL CLOCK zm i SCI INTERRUPT CONTROL TRANSMITTER CLOCK 437 93 164 ST72311R ST72511R ST72512R ST72532R SERIAL COMMUNICATIONS INTERFACE Cont d 10 6 4 Functional Description The block diagram of the Serial Control Interface is shown in Figure 52 It contains 6 dedicated re
39. Generates an interrupt if enabled Two 16 bit registers Output Compare Register 1 OC1R and Output Compare Register 2 OC2R contain the value to be compared to the counter register each timer clock cycle MS Byte LS Byte OCiHR These registers are readable and writable and are not affected by the timer hardware A reset event changes the value to 8000h Timing resolution is one count of the free running counter 1 OCiR Procedure To use the output compare function select the fol lowing in the CR2 register Set the bit if an output is needed then the OCMPi pin is dedicated to the output compare signal Select the timer clock CC 1 0 see Table 18 Clock Control Bits And select the following in the CR1 register Select OLVL ibit to applied to the pins after the match occurs Set the OCIE bit to generate an interrupt if it is needed When a match is found between OCRi register and CR register OCFibit is set ST72311R ST72511R ST72512R ST72532R The OCMP pin takes OLVLi bit value pin latch is forced low during reset A timer interrupt is generated if the OCIE bit is set in the CR2 register and the bit is cleared the CC register CC register value required for a specific tim ing application can be calculated using the follow ing formula At f PRE
40. IPB BC1 BCO TLIS TLIE SSM SSI Reset Value 0 0 0 0 0 0 0 0 3 48 164 10 PERIPHERALS 10 1 WATCHDOG TIMER WDG 10 1 1 Introduction The Watchdog timer is used to detect the occur rence of a software fault usually generated by ex ternal interference or by unforeseen logical condi tions which causes the application program to abandon its normal sequence The Watchdog cir cuit generates an MCU reset on expiry of a pro grammed time period unless the program refresh es the counters contents before the bit be comes cleared 10 1 2 Main Features m Programmable timer 64 increments of 12288 CPU cycles m Programmable reset m Reset if watchdog activated after a HALT instruction or when the T6 bit reaches zero Figure 28 Watchdog Block Diagram ST72311R ST72511R ST72512R ST72532R m Hardware Watchdog selectable by option byte m Watchdog Reset indicated by status flag in versions with Safe Reset option only 10 1 3 Functional Description The counter value stored in the CR register bits T 6 0 is decremented every 12 288 machine cy cles and the length of the timeout period can be programmed by the user in 64 increments If the watchdog is activated the WDGA bit is set and when the 7 bit timer bits T 6 0 rolls over from 40h to 3Fh T6 becomes cleared it initiates a reset cycle pulling low the reset pin for typically 500ns WATCHDOG CONTROL REGISTER CR 7 DOW
41. MCU from prescaler clock source WAIT and HALT modes These resources allow three possible operating modes Generation of up to 4 independent PWM signals Output compare and Time base interrupt External event detector Figure 30 PWM Auto Reload Timer Block Diagram OCRx DCRx REGISTER REGISTER LOAD PORT ALTERNATE POLARITY COMPARE FUNCTION CONTROL 8 COUNTER CAR REGISTER ARR i REGISTER fext ARTCLK fcpu fCOUNTER PROGRAMMABLE PRESCALER zl ee ocr oon s en o m OVF INTERRUPT 3 54 164 PWM AUTO RELOAD Cont d 10 3 2 Functional Description Counter The free running 8 bit counter is fed by the output of the prescaler and is incremented on every ris ing edge of the clock signal It is possible to read or write the contents of the counter on the fly by reading or writing the Counter Access register CAR When a counter overflow occurs the counter is automatically reloaded with the contents of the ARR register the prescaler is not affected Counter clock and prescaler The counter clock frequency is given by fcouNrER finput 200120 The timer counter s input clock feeds the 7 bit programmable prescaler which selects one of the 8 available taps of the prescaler as defined by 2 0 bits in the Control Status Register CSR Thus the division factor of the prescaler be set to 2 where n 0 1 7
42. RCF ASP GR PUSHIPOP SLL SRL SRA RLC RRC SWAP Swap Nibbles 11 1 2 Immediate Immediate instructions have two bytes the first byte contains the opcode the second byte con tains the operand value Leger Fia Shift and Rotate Operations ADC ADD SUB SBC Arithmetic Operations 126 164 11 1 3 Direct In Direct instructions the operands are referenced by their memory address The direct addressing mode consists of two sub modes Direct short The address is a byte thus requires only one byte after the opcode but only allows 00 FF address ing space Direct long The address is a word thus allowing 64 Kbyte ad dressing space but requires 2 bytes after the op code 11 1 4 Indexed No Offset Short Long In this mode the operand is referenced by its memory address which is defined by the unsigned addition of an index register X or Y with an offset The indirect addressing mode consists of three sub modes Indexed No Offset There is no offset no extra byte after the opcode and allows 00 FF addressing space Indexed Short The offset is a byte thus requires only one byte af ter the opcode and allows 00 1FE addressing space Indexed long The offset is a word thus allowing 64 Kbyte ad dressing space and requires 2 bytes after the op code 11 1 5 Indirect Short Long The required data byte to do the operation is found by its memory address
43. Send break This bit set is used to send break characters It is set and cleared by software 0 No break character is transmitted 1 Break characters are transmitted Note If the SBK bit is set to 1 and then to 0 the transmitter will send a BREAK word at the end of the current word 101 164 ST72311R ST72511R ST72512R ST72532R SERIAL COMMUNICATIONS INTERFACE Cont d DATA REGISTER DR Read Write Reset Value Undefined Contains the Received or Transmitted data char acter depending on whether it is read from or writ ten to 7 0 The Data register performs a double function read and write since it is composed of two registers one for transmission TDR and one for reception RDR The TDR register provides the parallel interface between the internal bus and the output shift reg ister see Figure 52 The RDR register provides the parallel interface between the input shift register and the internal bus see Figure 52 BAUD RATE REGISTER BRR Read Write Reset Value 00xx xxxx XXh 7 0 Bit 7 62 SCP 1 0 First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges 102 164 Bit 5 3 SCT 2 0 SC Transmitter rate divisor These 3 bits in conjunction with the SCP1 amp SCPO bits define the total division applied to the bus clock to yield the transmit rate clock in convention al Baud Rate Generator mode pm qe Lo op 1
44. TUVO TT 13s 10 vs asa praes oos oso os norapors rore Fe es aka ke For el RTE xx Fer Teo i per Pe Joel T L3 Ft oss oso nara wea 000 rp pep Number of Pins N 64 ND 16 NE t6 a me ves pas me Pat pss PL CC Ke ozs 038 050 joojoo sso preoo re sso sos Fe oso e ew Fu poo a pa gt pal 64 EN Note QUALIFICATION OR VOLUME PRODUCTION OF DEVICES USING EPOXY PACKAGES ESO EDIL EQF P IS NOT AUTHORIZED Itis expressly specified that qualification and or volume production of devices using the package E in any applications is not authorized Usage in any application is strictly restricted to development purpose Similar devices are available in plastic package mechanically compatible to the epoxy package for qualification and volume production 154 164 437 ST72311R ST72511R ST72512R ST72532R 13 2 THERMAL CHARACTERISTICS CL ME a S NM R Package thermal resistance junction to ambient C W mA TQFP64 Notes 1 The power dissipation is obtained from the formula where is the ch
45. activated when enter ring the WAIT mode while the device is already in SLOW mode Figure 19 SLOW Mode Clock Transitions NORMAL RUN MODE REQUEST NEW SLOW FREQU ENCY REQUEST 3 34 164 ST72311R ST72511R ST72512R ST72532R POWER SAVING MODES Cont d 7 3 WAIT MODE Figure 20 WAIT Mode Flow chart WAIT mode places the MCU in a low power con OSCILLATOR ON sumption mode by stopping the CPU PERIPHERALS ON This power saving mode is selected by calling the WEI INSTRUCTION CPU OFF WEI instruction I 1 0 BITS 10 All peripherals remain active During WAIT mode the I 1 0 bits of the CC register are forced to 10 to enable all interrupts All other registers and memory remain unchanged The MCU remains in WAIT mode until an interrupt or RESET occurs whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine The MCU will remain in WAIT mode until a Reset or an Interrupt occurs causing it to wake up OSCILLATOR ON PERIPHERALS OFF Refer to Figure 20 CPU ON I 1 0 BITS 10 OSCILLATOR ON PERIPHERALS ON FETCH RESET VECTOR OR SERVICE INTERRUPT Note 1 Before servicing an interrupt the CC register is pushed on the stack The 1 1 0 bits of the CC reg ister are set to the current software priority level of the interrupt routine and recovered when the CC register is popped 35 164 ST72311R ST72511R ST72512R ST72532R POWER SAVI
46. affected by the interrupt auto matic procedures Program Counter PC The program counter is a 16 bit register containing the address of the next instruction to be executed by the CPU It is made of two 8 bit registers PCL Program Counter Low which is the LSB and PCH Program Counter High which is the MSB ACCUMULATOR X INDEX REGISTER Y INDEX REGISTER PROGRAM COUNTER CONDITION CODE REGISTER STACK POINTER X Undefined Value 3 CENTRAL PROCESSING UNIT Cont d Condition Code Register CC Read Write Reset Value 111x1xxx The 8 bit Condition Code register contains the in terrupt masks and four flags representative of the result ofthe instruction just executed This register can also be handled by the PUSH and POP in structions These bits can be individually tested and or con trolled by specific instructions Arithmetic management bits Bit 4 H Half carry This bitis set by hardware when a carry occurs be tween bits 3 and 4 of the ALU during an ADD or instructions It is reset by hardware during the same instructions 0 No half carry has occurred 1 An half carry has occurred This bit is tested using the JRH or JRNH instruc tion The H bit is useful in BCD arithmetic subrou tines Bit 2 N Negative This bit is set and cleared by hardware It is repre sentative of the result sign of the last arithmetic logical or data manipulation It s a copy of the re sult 7 bit
47. as a normal ROM loca tion when the LAT bit of the EECSR register is cleared In a read cycle the byte to be accessed is put on the data bus in less than 1 CPU clock cycle This means that reading data from EEPROM takes the same time as reading data from EPROM but this memory cannot be used to exe cute machine code Write Operation LAT 1 To access the write mode the LAT bit has to be set by software the PGM bit remains cleared When a write access to the EEPROM area occurs the value is latched inside the 16 data latches ac cording to its address ST72311R ST72511R ST72512R ST72532R When PGM bit is set by the software all the previ ous bytes written in the data latches up to 16 are programmed in the EEPROM cells The effective high address row is determined by the last EEP ROM write sequence To avoid wrong program ming the user must take care that all the bytes written between two programming sequences have the same high address only the four Least Significant Bits of the address can change At the end of the programming cycle the PGM and LAT bits are cleared simultaneously and an inter rupt is generated if the IE bitis set The Data EEP ROM interrupt request is cleared by hardware when the Data EEPROM interrupt vector is fetched Note Care should be taken during the program ming cycle Writing to the same memory location will over program the memory logical AND be tween the two write access data res
48. bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit the ICAP1pin must be configured as floating input ST72311R ST72511R ST72512R ST72532R When an input capture occurs ICF bit is set The register contains the value of the free running counter on the active transition on the ICAPi pin see Figure 40 timer interrupt is generated if the ICIE bit is set and the bit is cleared in the CC register Other wise the interrupt remains pending until both conditions become true Clearing the Input Capture interrupt request i e clearing the bit is done two steps 1 Reading the SR register while the ICF bit is set 2 An access read or write to the register Notes 1 After reading the IC HR register transfer of input capture data is inhibited and ICFi will never be set until the register is also read 2 The register contains the free running counter value which corresponds to the most recent input capture 3 The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions 4 n One pulse Mode and PWM mode only the input capture 2 can be used 5 The alternate inputs ICAP1 amp ICAP2 are always directly connected to the timer So any transitions on these pins acti
49. control pin Output current sunk by any standard HO and control 2 INJ PIN 5 Total injected current sum of all I O and control pins 20 12 2 3 Thermal Characteristics Storage temperature range 65 to 150 Maximum junction temperature see Section 13 2 THERMAL CHARACTERISTICS on page 155 Notes 1 Directly connecting the RESET and I O pins to Vpp or Vgg could damage the device if an unintentional internal reset is generated or an unexpected change of the I O configuration occurs for example due to a corrupted program counter To guarantee safe operation this connection has to be done through a pull up or pull down resistor typical 4 7kQ for RESET 10kQ for I Os Unused I O pins must tied in the same way to Vpp or Vgg according to their reset configuration 2 When the current limitation is not possible the Vu absolute maximum rating must be respected otherwise refer to IiNJ PIN Specification A positive injection is induced by gt while a negative injection is induced Viy V ss 3 All power Vpp and ground Vss lines must always be connected to the external supply 4 Negative injection disturbs the analog performance of the device In particular it induces leakage currents throughout the device including the analog inputs To avoid undesirable effect on analog part care must be taken Analog input pins must have a negative injection less than 0 8 mA assuming that the impeda
50. data are based 25 Vpp 5V 5 Data based on characterization results not tested in production 6 Data based on characterization results done with the typical external components not tested in production 7 As the oscillator is based on a current source the consumption does not depend on the voltage 8 Data based on a differential Ion measurement between reset configuration timer counter running at fopy 4 and timer counter stopped selecting external clock capability Data valid for one timer 9 Data based on a differential Ipp measurement between reset configuration and a permanent SPI master communica tion data sent equal to 55h 10 Data based on a differential Ipp measurement between reset configuration and continuous A D conversions 137 164 ST72311R ST72511R ST72512R ST72532R 12 5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating condition for Vpp fosc and Ta 12 5 1 General Timings Ape _ 08561 input pin high level voltage OSC1 input pin low level voltage TU wOsctH OSC1 high or low time 3 see Figure 73 o OSC1 rise or fall time 12 5 3 Crystal and Ceramic Resonator Oscillators Symb Parameer Max Unit Hos we Lond capacitance SE Oscillator start up time Depends on resonator quality A typical value is 10ms Notes 1 Data based on typical application software 2 Time mea
51. detailed information on con tractual points Figure 98 ROM Factory Coded Device Types TEMP DEVICE PACKAGE RANGE X umm Code name defined by STMicroelectronics LVD disabled S LVD enabled 1 standard 0 to 70 C 6 industrial 40 to 85 C 7 automotive 40 to 105 C 3 automotive 40 to 125 C T TQFP ST72311R6 ST72311R7 ST72311R9 ST72511R6 ST72511R7 ST72511R9 ST72512R4 ST72532R4 Figure 99 OTP User Programmable Device Types TEMP DEVICE PACKAGE RANGE D LVD disabled S LVD enabled 1 standard 0 to 70 C 6 industrial 40 to 85 C 7 automotive 40 to 105 C 3 automotive 40 to 125 C ST72T311R6 ST72T311R7 ST72T311R9 ST72T511R6 ST72T511R7 ST72T511R9 ST72T512RA4 ST72T532R4 159 164 ST72311R ST72511R ST72512R ST72532R TRANSFER OF CUSTOMER CODE Cont d MICROCONTROLLER OPTION LIST Customer Address Contact Phone N Reference STMicroelectronics references Device ST72311R9 ST72511R9 ST72512R4 ST72311R7 ST72511R7 ST72532R4 ST72311R6 ST72511R6 Package 64 Temperature Range 0 C to 70 C 40 C 85 C 40 105 C 40 C to 125 C Oscillator Source Selection Quartz Crystal Ceramic resonator External Clock Watchdog Selection Software Activation Hardware Activation Disabled Watchdog Reset on Halt Enabled Readout Protec
52. during an interrupt The user may also directly manipulate the stack by means of the PUSH and POP instruc tions In the case of an interrupt the PCL is stored at the first location pointed to by the SP Then the other registers are stored in the next locations as shown in Figure 8 When an interrupt is received the SP is decre mented and the context is pushed on the stack On return from interrupt the SP is incremented and the context is popped from the stack A subroutine call occupies two locations and an in terrupt five locations in the stack area 4 ST72311R ST72511R ST72512R ST72532R 5 SUPPLY RESET AND CLOCK MANAGEMENT The ST72311R ST72511R ST72512RH and ST72532R microcontrollers include a range of util ity features for securing the application in critical situations for example in case of a power brown out and reducing the number of external compo nents An overview is shown in Figure 9 Main features m Main supply low voltage detection LVD m RESET Manager RSM m Low consumption resonator oscillator Figure 9 Clock RESET Option and Supply Management Overview TO OSCILLATOR MAIN CLOCK CONTROLLER FROM WATCHDOG PERIPHERAL LOW VOLTAGE DETECTOR LVD 23 164 ST72311R ST72511R ST72512R ST72532R 5 1 LOW VOLTAGE DETECTOR LVD To allow the integration of power management features in the application the Low Voltage Detec tor function LVD generate
53. independ ent PWM output channels 2 input captures Development Tools utput compares and external clock with Full hardware software development package t detector t on ST725x2R4 event detector except on D Two 16 bittimers with 2 input captures 2 out put co external clock input on one tim er PWM and Pulse generator modes Device Summary Features ST72511R9 ST72511R7 ST72511R6 ST72311R9 ST72311R7 ST72311R6 ST72512R4 ST72532R4 Program memory bytes 60K 32K 16K 16K RAM stack bytes m BE erem 256 meer Tm Der mm err m erem 256 mener ES EEPROM byles DL ws Peripherals watchdog two 16 bit timers 8 bit ER two n bit timers 8 bit d two 16 timers p ART SPI SCI CAN ADC ART SPI SCI ADC SPI SCI CAN ADC Operating Supply 3 0V to 5 5V 3 0 to 5 13 0 to 5 5V 7 CPU Frequency 2 to 8 MHz with 4 to 16 MHz oscillator 2104 ILIUM Operating Temperature 40 C to 85 C 40 C to 105 125 C optional TGFP64 Note 1 See Section 12 3 1 on page 133 for more information on Vpp versus fosc Rev 2 1 February 2000 1 164 Table of Contents 1 GENERAL DESCRIPTION y Re xxm e 6 13 INTRODUCTION 2 utm doeet d edes 6 12 DESCRIPTION 41 7 1 3 REGISTER
54. new transmit job pending by the end of the cur rent transmission while always leaving two buff ers available for reception An uninterrupted stream of messages may be transmitted in this way at no overrun risk Up to three messages can be automatically received without intervention from the CPU because each buffer has its own set of status bits greatly reducing the reactiveness require ments in the processing of the receive inter rupts 3 108 164 CONTROLLER AREA NETWORK Cont d ERROR The error management as described in the CAN protocol is completely handled by hard ware using 2 error counters which get increment ed or decremented according to the error condition Both of them may be read by the appli Figure 58 CAN Error State Diagram ST72311R ST72511R ST72512R ST72532R cation to determine the stability of the network Moreover as one of the node status bits EPSV or BOFF of the register changes an inter rupt is generated if the SCIE bit is set in the ICR Register Refer to Figure 58 When TECR or RECR gt 127 the EPSV bit gets set ERROR ACTIVE ERROR PASSIVE When TECR and RECR 128 the EPSV bit gets cleared When 128 11 recessive bits occur the BOFF bit gets cleared the TECR register gets cleared the RECR register gets cleared When TECR gt 255 the BOFF bit gets set and the EPSV bit gets cleared 109 164 ST72311R ST72511R ST72512R ST72532R CONTROLL
55. of the four relationships between the data transfer and the serial clock see Figure 49 The SS pin must be connected to a high level signal during the complete byte transmit se quence The MSTR and SPE bits must be set they re main set only if the SS pin is connected to a high level signal ST72311R ST72511R ST72512R ST72532R In this configuration the MOSI pin is a data output and to the MISO pin is a data input Transmit sequence The transmit sequence begins when a byte is writ ten the DR register The data byte is parallel loaded into the 8 bit shift register from the internal bus during a write cycle and then shifted out serially to the MOSI pin most significant bit first When data transfer is complete The SPIF bit is set by hardware An interrupt is generated if the SPIE bit is set and the I bit in the CCR register is cleared During the last clock cycle the SPIF bit is set a copy of the data byte received in the shift register is moved to a buffer When the DR register is read the SPI peripheral returns this buffered value Clearing the SPIF bit is performed by the following software sequence 1 An access to the SR register while the SPIF bit is set 2 A write or a read of the DR register Note While the SPIF bit is set all writes to the DR register are inhibited until the SR register is read 81 164 ST72311R ST72511R ST72512R ST72532R SERIAL PERIPHERAL INTERFACE
56. or Overload Frame 44 Arbitration Field Control Field CRC Field Ack Field Of Frame 2 16 Data Frame or Inter Frame Space Remote Frame Error Frame or Overload Frame Data Frame or Notes Any Frame Inter Frame Space Remote Frame ef lt lt 8 e SOF Start Of Frame eID Identifier eRTR Remote Transmission Request e IDE Identifier Extension Bit 0 Reserved Bit End Of Frame or DLC Data Length Code Error Delimiter or Inter Frame Space e CRC Cyclic Redundancy Code Overload Delimiter Overload Frame or Error Frame flag 6 dominant bits if node is error active else 6 recessive bits e Suspend transmission applies to error passive nodes only EOF End of Frame ACK Acknowledge bit 4 106 164 ST72311R ST72511R ST72512R ST72532R CONTROLLER AREA NETWORK Cont d 10 7 3 3 Modes of Operation Register ICR is set The STANDBY mode is left by setting the RUN The Core Unit ee br Mie seven bit If the WKPS bit is set in the CSR register states described below then the controller passes through WAKE UP STANDBY Standby mode is entered either ona otherwise it enters RESYNC directly chip reset or on resetting the RUN bit in the Con Itis important to note that the wake up mecha trol Status Register CSR Any on going trans nism is software driven and therefore carries a mission or reception operation is not interrupted significant time overhead Al
57. peripheral control register The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register Note The clearing sequence resets the internal latch A pending interrupt i e waiting for being serviced will therefore be lost if the clear se quence is executed 29 164 ST72311R ST72511R ST72512R ST72532R INTERRUPTS Cont d 6 3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode On the contrary only external and other specified interrupts allow the processor to exit the HALT modes see column Exit from HALT in Interrupt Mapping table When several pending interrupts are present while exiting HALT mode the first one serviced can only be an inter rupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 15 Note If an interrupt that is not able to Exit from HALT mode is pending with the highest priority when exiting HALT mode this interrupt is serviced after the first one serviced Figure 16 Concurrent interrupt management 30 164 6 4 CONCURRENT amp NESTED MANAGEMENT The following Figure 16 and Figure 17 show two different interrupt management modes The first is called concurrent mode and does not allow an in terrupt to be interrupted unlike the nested mode in Figure 17 The interrupt hardware priority is given in
58. priority is given to ter reset Buffer 3 then 2 and 1 If the transmission fails due When no such buffer exists then an overrun to a lost arbitration or to an error while the NRTX generated bit of the CSR register is reset then a new trans er of the last message is made available in the mission attempt is performed This goes on until Last Identifier Register LIDHR and LIDLR at the transmission ends successfully or until the least until it gets overwritten by a new identifi job is cancelled by unlocking the buffer by set er picked up from the bus ting the NRTX bit or if the node ever enters bus When a buffer does exist the accepted mes off or if a higher priority message becomes pend sage gets written into it the ACC bit in the ing The RDY bit in the BCSRx register which Si fhe number macn was set since the job was submitted gets reset interrupt is generated if the RXIE bit in the ISR When atransmission is in progress the BUSY bit register is set in the BCSRx register is set If it ends successful ly then the TXIF bit in the Interrupt Status Regis ter ISR is set else the TEIF bit is set An interrupt is generated in either case provided the TXIE and TEIE bits of the ICR register are set The ETX bitin the same register is used to get an early transmit interrupt and to automatically un lock the transmitting buffer upon successful com pletion of its job This enables the CPU to get a
59. that the main oscillator has reached the selected elapsed time TB1 0 0 Timeout not reached 1 Timeout reached CAUTION The BRES and BSET instructions must not be used onthe MCCSR register to avoid unintentionally clearing the OIF bit 10 2 5 Low Power Modes No effect on MCC RTC peripheral MCC RTC interrupt cause the device to exit from WAIT mode No effect on MCC RTC counter OIE bit is ACTIVE set the registers are frozen HALT MCC RTC interrupt cause the device to exit WAIT from ACTIV E HALT mode MCC RTC counter and registers are frozen MCC RTC operation resumes when the MCU is woken up by an interrupt with exit from HALT capability 10 2 6 Interrupts The MCC RTC interrupt event generates an inter rupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active RIM instruction Note 1 The MCC RTC interrupt allows to exit from AC TIVE HALT mode not from HALT mode Table 16 MCC RTC Register Map and Reset Values Address Register Hex Label MCCSR Es Es a E 53 164 ST72311R ST72511R ST72512R ST72532R 10 3 PWM AUTO RELOAD TIMER ART 10 3 1 Introduction The Pulse Width Modulated Auto Reload Timer The two first modes can be used together with a on chip peripheral consists of an 8 bit auto reload single counter frequency counter with compare capabilities and of a 7 bit The timer can be used to wake up the
60. the analog channel to be converted ADC Conversion In the CSR register Set the ADON bit to enable the A D converter and to start the first conversion From this time on the ADC performs a continuous conver sion of the selected channel When a conversion is complete The COCO bit is set by hardware No interrupt is generated The result is in the DR register and remains valid until the next conversion has ended A write to the CSR register with ADON set aborts the current conversion resets the COCO bit and starts a new conversion Figure 63 ADC Conversion Timings ADCCSR WRITE OPERATION HOLD CONTROL LOAD L COCOBIT SET 10 8 4 Low Power Modes WAIT No effect on A D Converter A D Converter disabled After wakeup from Halt mode the A D Con HALT Kee verter requires a stabilisation time before curate conversions can be performed Note The A D converter may be disabled by reset ting the ADON bit This feature allows reduced power consumption when no conversion is needed and between single shot conversions 10 8 5 Interrupts None 3 8 BIT A D CONVERTER ADC Cont d 10 8 6 Register Description CONTROL STATUS REGISTER CSR Read Write Reset Value 0000 0000 00h ST72311R ST72511R ST72512R ST72532R DATA REGISTER DR Read Only Reset Value 0000 0000 00h 7 0 7 0 Bit 7 Conversion Complete This bit is set by hardware It is cleared by
61. the description of the IS1x bits of the MISCR1 register for more details Bit 5 4 BC 1 0 Beep control These 2 bits select the PF1 pin beep capability Output Beep signal 50 duty cycle The beep output signal is available in ACTIVE HALT mode but has to be disabled to reduce the consumption ST72311R ST72511R ST72512R ST72532R Bit 3 TLIS TLI sensitivity This bit allows to toggle the TLI edge sensitivity It can be set and cleared by software only when TLIE bit is cleared 0 Falling edge 1 Rising edge Bit 2 TLIE 70 enable This bit allows to enable or disable the TLI capabil ity on the dedicated pin It is set and cleared by software 0 TLI disabled 1 TLI enabled Note a parasitic interrupt can be generated when clearing the TLIE bit Bit 1 SSM SS mode selection This bit is set and cleared by software _ 0 Normal mode the level of the SPI SS signal is input from the external SS pin m 1 mode PC7 the level ofthe SPI 55 signal is read from the SSI bit Bit 0 SSI SS internal mode This bit replaces pin SS ofthe SPI when bit SSM is set to 1 see SPI description It is set and cleared by software 47 164 ST72311R ST72511R ST72512R ST72532R MISCELLANEOUS REGISTERS Cont d Table 13 Miscellaneous Register Map and Reset Values Address Register 7 Hex Label 0020h MIS CR1 1511 1510 1521 1520 CPO SMS Reset Value 0 0 0 0 0 0 0 0 0040h MISCR2 IPA
62. x x x x CANIDHRx Po P SS a p P Es 1 to 3 Reset Value CANFHRx ii GE Pes ius ies ix ju is 60 64 Reset Value CANLIDLR pes E ped E m SC Reset Value CANIDLRx P5 ge E e 1103 Reset Value 61 65 4 CANFLRx FIL3 FIL2 FIL1 FILO Reset Value x X x 621069 1103 CANDRx Reset Value x x D x x x x CANMHRx MSK11 MSK10 5 9 MSK8 MSK7 MSK6 MSK5 MSK4 62 66 4 Reset Value X X X D x x x x CANMLRx in ie MSK1 MSKO 63 67 4 Reset Value x CANTECR d E Reset Value CANRECR Ca r Reset Value CANBCSRx nos i id ar a 1103 Reset Value 120 164 3 10 8 8 BIT A D CONVERTER ADC 10 8 1 Introduction The on chip Analog to Digital Converter ADC pe ripheral is a 8 bit successive approximation con verter with internal sample and hold circuitry This peripheral has up to 16 multiplexed analog input channels refer to device pin out description that allow the peripheral to convert the analog voltage levels from up to 16 different sources The result of the conversion is stored in a 8 bit Data Register The A D converter is controlled through a Control Status Register 10 8 2 Main Features m 8 bit conversion Up to 16 channels with multiplexed input Linear successive approximation Data register DR which contains the results Conversion complete status flag On off bit to reduce consumption The block diagram is shown in Figure 62 Figure 62 ADC Block Diagram ST72311R ST72511R ST725
63. 0 4 3 5 One Pulse Mode on page 69 See note 5 in Section 10 4 3 5 One Pulse Mode on page 69 3 See note 4 in Section 10 4 3 6 Pulse Width Modulation Mode on page 71 73 164 ST72311R ST72511R ST72512R ST72532R 16 BIT TIMER 10 4 7 Register Description Each Timer is associated with three control and status registers and with six pairs of data registers 16 bit values relating to the two input captures the two output compares the counter and the al ternate counter CONTROL REGISTER 1 CR1 Read Write Reset Value 0000 0000 00h 7 0 ICIEJOCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL 1 Bit 7 ICIE Input Capture Interrupt Enable 0 Interrupt is inhibited 1 timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set Bit 6 OCIE Output Compare Interrupt Enable 0 Interrupt is inhibited 1 A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set Bit 5 TOIE Timer Overflow Interrupt Enable 0 Interrupt is inhibited 1 A timer interrupt is enabled whenever the TOF bit of the SR register is set 74 164 Bit 4 FOLV2 Forced Output Compare 2 This bit is set and cleared by software 0 No effect on the OCMP2 pin 1 Forces the OLVL2 bit to be copied to the 2 pin if the OC2E bit is set and even if there is no successful comparison Bit 3 FOLV1 Forced Output Compare 1 This bit is set and cleared by software
64. 1 CR1 Control Register 2 CR2 note TIMER INTERRUPT Note If IC OC and TO interrupt requests have separate vectors then the last OR is not present See device Interrupt Vector Table 62 164 4 16 BIT TIMER Cont d 16 bit read sequence from either the Counter Register or the Alternate Counter Register LS Byte is buffered Beginning of the sequence Read MS Byte r At t0 Other 7 instructions Read Returns the buffered At 10 At S Byte LS Byte value at t0 Sequence completed The user must read the MS Byte first then the LS Byte value is buffered automatically This buffered value remains unchanged until the 16 bit read sequence is completed even if the user reads the MS Byte several times After a complete reading sequence if only the CLR register or ACLR register are read they re turn the LS Byte of the count value at the time of the read Whatever the timer mode used input capture out put compare one pulse mode or PWM mode an overflow occurs when the counter rolls over from FFFFh to 0000h then The TOF bit of the SR register is set A timer interrupt is generated if TOIE bit of the CR1 register is set and bit of the CC register is cleared If one of these conditions is false the interrupt re mains pending to be issued as soon as they are both true ST72311R ST72511R ST72512R ST72532R Clearing the overflow interrupt request is done in two steps
65. 12R ST72532R 10 8 3 Functional Description 10 8 3 1 Analog Power Supply VppA Vssa are the high and low level refer ence voltage pins In some devices refer to device pin out description they are internally connected to the Vss pins Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines See electrical characteristics section for more de tails ANALOG TO DIGITAL CONVERTER 2550580 121 164 ST72311R ST72511R ST72512R ST72532R 8 BIT A D CONVERTER ADC Cont d 10 8 3 2 Digital A D Conversion Result The conversion is monotonic meaning that the re sult never decreases if the analog input does not and never increases if the analog input does not If the input voltage is greater than or equal to Vppa high level voltage reference then the conversion result in the DR register is FFh full scale without overflow indication If input voltage Vain is lower than or equal to Vssa low level voltage reference then the con version result in the DR register is OOh The A D converter is linear and the digital result of the conversion is stored in the ADCDR register The accuracy of the conversion is described in the parametric section Rain is the maximum recommended impedance for an analog input signal If the impedance is too high this will result in a loss of accuracy due to leakage and
66. 2 HS ICAP2 HS ICAP1 PC6 SCK 70 ST72311R ST72511R ST72512R ST72532R Oo function HEBERE SERGE REEL VENEN EE T 7 77 7 8 20 oi Co 0 o Px Timer A Input Capture 2 x X Potre Timer Capture X X Potr7 Timer A External Clock Source Pit Main Supply Voltage Digital Ground Voltage Timer Output Compare 2 XTX X X PotC Output Compare 1 __ 2 Timer Input Capture2 x x Time Input Capture 1 ES Fon ca x x X Po Pon 65 SPI Master out Sive Data Px x Pon C7 SP Stave Select aet on Dres p TTF Rasta win Vote CITT 3 fna rT _ Port Must be tied low in user mode In programming mode when available this pin acts as the pro gramming voltage input Vpp TX Top priority non maskable interrupt active low Not Connected SR E S en L 4 1 EE External clock mode input pull up or crystal ce ramic resonator oscillator inverter output External
67. 2 LOW REGISTER OC2LR Read Write Reset Value 0000 0000 00h This is an 8 bit register that contains the low part of the value to be compared to the CLR register 7 0 COUNTER HIGH REGISTER CHR Read Only Reset Value 1111 1111 FFh This is an 8 bit register that contains the high part of the counter value 7 0 gp jJ COUNTER LOW REGISTER CLR Read Only Reset Value 1111 1100 FCh This is an 8 bit register that contains the low part of the counter value A write to this register resets the counter An access to this register after accessing the SR register clears the TOF bit 7 0 ST72311R ST72511R ST72512R ST72532R ALTERNATE COUNTER HIGH REGISTER ACHR Read Only Reset Value 1111 1111 FFh This is an 8 bit register that contains the high part of the counter value 7 0 per ee ALTERNATE COUNTER LOW REGISTER ACLR Read Only Reset Value 1111 1100 FCh This is an 8 bit register that contains the low part of the counter value A write to this register resets the counter An access to this register after an access to SR register does not clear the TOF bit in SR register 7 0 CAPTURE 2 HIGH REGISTER IC2HR Read Only Reset Value Undefined This is an 8 bit read only register that contains the high part of the counter value transferred by the Input Capture 2 event 7 0
68. 2311R ST72511R ST72512R ST72532R SERIAL COMMUNICATIONS INTERFACE Cont d 10 6 4 3 Receiver The SCI can receive data words of either 8 or 9 bits When the M bit is set word length is 9 bits and the MSB is stored in the R8 bit in the CR1 reg ister Character reception During SCI reception data shifts in least signifi cant bit first through the RDI pin In this mode DR register consists in a buffer RDR between the in ternal bus and the received shift register see Fig ure 52 Procedure Select the M bit to define the word length Selectthe desired baud rate using the BRR and the ERPR registers Set the RE bit this enables the receiver which begins searching for a start bit When a character is received The bit is set It indicates that the content of the shift register is transferred to the RDR Aninterrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register The error flags can be set if a frame error noise or an overrun error has been detected during re ception Clearing the RDRF bit is performed by the following software sequence done by 1 An access to the SR register 2 A read to the DR register The bit must be cleared before the end of the reception of the next character to avoid an overrun error Break Character When a break character is received the SPI han dles it as a framing error Idle Character When
69. 4 ST72311R ST72511R ST72512R ST72532R 7 POWER SAVING MODES 7 1 INTRODUCTION To give a large measure of flexibility to the applica tion in terms of power consumption four main power saving modes are implemented in the ST7 see Figure 18 SLOW WAIT SLOW WAIT AC TIVE HALT and HALT After a RESET the normal operating mode is se lected by default RUN mode This mode drives the device CPU and embedded peripherals by means of a master clock which is based on the main oscillator frequency divided by 2 From RUN mode the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the the oscil lator status Figure 18 Power Saving Mode Transitions RUN SLOW WAIT SLOW WAIT ACTIVE HALT HALT Low POWER CONSUMPTION 7 2 SLOW MODE This mode has two targets Toreduce power consumption by decreasing the internal clock in the device To adapt the internal clock frequency to the available supply voltage SLOW mode is controlled by three bits in the MISCR1 register the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency fep In this mode the oscillator frequency can be divid ed by 4 8 16 or 32 instead of 2 in normal operat ing mode The CPU and peripherals are clocked at this lower frequency Note SLOW WAIT mode is
70. 7 PWM3 PBO PWM2 PB1 PWM 1 PB2 PWMO PB3 ARTCLK PB4 PB5 PB6 PB7 AINO PDO PD1 AIN2 PD2 AIN3 Jo Om WD 10 11 12 13 14 15 16 1 N PD4 5 PD5 AIN6 PD6 AIN7 PD7 D PF1 2 PF5 D HS PF6 D HS 7 ICAP1 OCMP1 EXTCLK A OCMP2 A PF3 HS 20 high sink capability eix associated external interrupt vector 7 164 ST72311R ST72511R ST72512R ST72532R PIN DESCRIPTION Cont d For external pin connection guidelines refer to Section 12 ELECTRICAL CHARACTERISTICS on page 131 Legend Abbreviations for Table 1 Type input O output S supply Input level A Dedicated analog input In Output level C CMOS 0 3Vpp 0 7 Vpp CMOS 0 3Vpp 0 7Vpp with input trigger Output level HS 20mA high sink on N buffer only Port and control configuration Input float floating wpu weak pull up int interrupt analog Output OD open drain 2 PP push pull Refer to Section 8 PORTS on page 38 for more details on the software configuration of the I O ports The RESET configuration of each is shown in bold This configuration is valid as long as the device is in reset state Table 1 Device Pin Description bevel pn Alternate functi
71. 72311R ST72511R ST72512R ST72532R SUPPLY CURRENT CHARACTERISTICS Cont d 12 4 2 WAIT and SLOW WAIT Modes Sym e fosc 1MHz fcpu 500kHz 1 25 fosc 4MHz fcpy 2MHz 3 2 fosc 16MHZ fopy 8MHz 5 2 Supply current in WAIT mode 3 see Figure 71 fosc 1MHz fcpu 31 25kHz fosc 4M Hz fcpu 1 25kHz fosc 16MHz fcpy 500kHz fosc 1 MHz fcpu 500kHz fosc 4MHz 2 2 fosc 1 6MHz fcpy 8MHz fosc 1 MHz fcpy 31 25kHz fogc 4MHz fopy 125kHz fosc 1 6MHz 500 2 Supply current SLOW WAIT mode 4 see Figure 72 Supply current in WAIT mode 3 see Figure 71 Supply current in SLOW WAIT mode 4 see Figure 72 3VSVpps3 6V 4 5 lt lt 5 5 Figure 71 Typical Ipp in WAIT vs fepy Figure 72 Typical Ipp in SLOW WAIT vs fcpy IDD mA IDD mA 1 5 2 2 muc 500kHz 125kHz 31 25kHz uM 5 4 4 5 5 5 5 VDD V 3 3 Notes 1 Typical data are based on 25 Vpp 5V 4 5 lt lt 5 range and Vpp 3 3V 3 lt lt 3 6 range 2 Data based on characterization results tested in production at Vpp max and max 3 All I O pins in input mode with a static value at or Vas no load all peripherals switched off clock input OSC 1 driven by external square wave LVD disabled 4 SLOW WAIT mode selected with based on fosc divided by 32 All I O pins in input mode with a static value at Vpp Vss no loa
72. AL RESET menooc hl fL JL IL IL IL IL TIL COUNTER REGISTER FFFD 0000 0001 A 0002 0003 TIMER OVERFLOW FLAG TOF _______ Figure 37 Counter Timing Diagram internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG TOF CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG TOF Note The MCU is in reset state when the internal reset signal is high when it is low the MCU is running 4 64 164 16 BIT Cont d 10 4 3 3 Input Capture In this section the index may be 1 or 2 because there are 2 input capture functions in the 16 bit timer The two input capture 16 bit registers IC1R and IC2R are used to latch the value of the free run ning counter after a transition detected by the ICAP pin see figure 5 MS Byte LS Byte ICiR register is a read only register The active transition is software programmable through the IEDGi bit of Control Registers Timing resolution is one count of the free running counter fcpu CC 1 0 Procedure To use the input capture function select the follow ing in the CR2 register Select the timer clock CC 1 0 see Table 18 Clock Control Bits Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit the ICAP2 pin must be configured as floating input And select the following in the CR1 register Set the ICIE
73. CMPi are set while the counter value equals the register value see Figure 42 on page 68 This behaviour is the same in OPM or PWM mode When the timer clock is fopy 4 fopy 8 or in external clock mode OCF and OCMPi are set while the counter value equals the regis ter value plus 1 see Figure 43 on page 68 The output compare functions can be used both for generating external events on the OCMP pins even if the input capture mode is also used The value in the 16 bit register and the OLVi bit should be changed after each suc cessful comparison in order to control an output waveform or establish a new elapsed timeout Figure 41 Output Compare Block Diagram Forced Compare Output capability When the FOLVi bit is set by software the OLVLi bit is copied to the OCMP pin The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled bit 1 The OCFi bit is then not set by hardware and thus no interrupt request is generated FOLVLi bits have no effect in both one pulse mode and PWM mode fooie FOLV2 FOLV1OLVL2 68 164 Status Register SR 3 16 BIT TIMER Cont d Figure 42 Output Compare Timing Diagram ftjmer 2 ST72311R ST72511R ST72512R ST72532R nmn oos UU UU UUUUL TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i OCR OUTPUT COMPARE FLAG i OLVLi 1 INTERNAL CPU
74. CPU clock frequency in hertz PRESC Timer prescaler factor 2 4 or 8 depend ing on CC 1 0 bits see Table 18 Clock Control Bits If the timer clock is an external clock the formula is OCR t fgyxT 5 Where t Signal or pulse period seconds External timer clock frequency in hertz The Output Compare 2 event causes the counter to be initialized to FFFCh See Figure 45 Notes 1 After a write instruction to the OC HR register the output compare function is inhibited until the register is also written 2 The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited 3 The ICF1 bitis set by hardware when the coun ter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared 4 PWM mode the ICAP1 can not be used to perform input capture because it is discon nected to the timer The ICAP2 pin can be used to perform input capture ICF2 can be set and IC2R can be loaded but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set 5 When the Pulse Width Modulation PWM and One Pulse Mode OPM bits are both set the PWM mode is the only active one 3 ST72311R ST72511R ST72512R ST72532R 16 TIMER Cont d 10 4 4 Low Power Modes Description WAIT No effect on 16 bit Timer Timer interrupts cause the devic
75. Cont d 10 5 4 2 Slave Configuration In slave configuration the serial clock is received on the SCK pin from the master device The value of the SPRO amp SPR1 bits is not used for the data transfer Procedure For correct data transfer the slave device must be in the same timing mode as the mas ter device CPOL and CPHA bits See Figure 49 The SS pin must be connected to a low level signal during the complete byte transmit se quence Clear the MSTR bit and set the SPE bit to as sign the pins to alternate function In this configuration the MOSI pin is a data input and the MISO pin is a data output Transmit Sequence The data byte is parallel loaded into the 8 bit shift register from the internal bus during a write cycle and then shifted out serially to the MISO pin most significant bit first The transmit sequence begins when the slave de vice receives the clock signal and the most signifi cant bit of the data on its MOSI pin 82 164 When data transfer is complete The SPIF bit is set by hardware An interrupt is generated if SPIE bit is set and bitin CCR register is cleared During the last clock cycle the SPIF bit is set a copy of the data byte received in the shift register is moved to a buffer When the DR register is read the SPI peripheral returns this buffered value Clearing the SPIF bit is performed by the following software sequence 1 An access to the SR register whil
76. DC7 DC6 DC5 DC4 DC3 DC2 DC1 DCO Reset Value 0 0 0 0 0 0 0 0075h PWMDCRO DC7 DC6 DC5 DC4 DC3 DC2 DC1 DCO Reset Value 0 0 0 0 0 0 0 0 OE1 OEO 2 OP1 PWMCR OE3 OE2 76h 0077h ARTCSR EXCL CC2 CC1 CCO TCE FCRL OIE OVF Reset Value 0 0 0 0 0 0 0 0 0078h ARTCAR CA7 CA6 5 4 2 1 CAO Reset Value 0 0 0 0 0 0 0 0 0079h ARTARR AR7 AR6 AR5 AR4 AR3 AR2 AR1 ARO Reset Value 0 0 0 0 0 0 0 0 4 60 164 10 4 16 BIT 10 4 1 Introduction The timer consists of a 16 bit free running counter driven by a programmable prescaler It may be used for a variety of purposes including pulse length measurement of up to two input sig nals input capture or generation of up to two out put waveforms output compare and PWM Pulse lengths and waveform periods can be mod ulated from a few microseconds to several milli seconds using the timer prescaler and the CPU clock prescaler Some ST7 devices have two on chip 16 bit timers They are completely independent and do not share any resources They are synchronized after a MCU reset as long as the timer clock frequen cies are not modified This description covers one or two 16 bit timers In ST7 devices with two timers register names are prefixed with TA Timer A or TB Timer B 10 4 2 Main Features m Programmable prescaler fopy divided by 2 4 or 8 m Overflow status flag and maskable interrupt m External clock input must be at least 4 ti
77. DES on page 36 for more details Figure 29 Main Clock Controller MCC RTC Block Diagram PORT CLOCK TO CAN PERIPHERAL ALTERNATE FUNCTION _ o MCC RTC INTERRUPT 52 164 CPU CLOCK TO CPU AND PERIPHERALS 3 ST72311R ST72511R ST72512R ST72532R MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER Cont d 10 2 4 Register Description MISCELLANEOUS REGISTER 1 MISCR1 See MISCELLANEOUS REGISTERS Section MAIN CLOCK CONTROL STATUS REGISTER MCCSR Read Write Reset Value 0000 0001 01h 7 0 Bit 7 4 Reserved always read as 0 Bit 3 2 TB 1 0 Time base control These bits select the programmable divider time base They are set and cleared by software Time Base Counter Prescaler fosc 8MHz 9m A modification of the time base is taken into count at the end of the current period previously set to avoid an unwanted time shift This allows to use this time base as a real time clock Bit 1 OIE Oscillator interrupt enable This bit set and cleared by software 0 Oscillator interrupt disabled 1 Oscillator interrupt enabled This interrupt can be used to exit from ACTIVE HALT mode When this bit is set calling the ST7 software HALT instruction enters the ACTIVE HALT power saving mode Bit 0 OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the CSR register It indicates when set
78. ER PSR Read Write Reset Value 00h 7 0 PAGE PAGE PAGE 2 1 0 PAGE 2 0 determine which buffer or filter page is mapped at addresses 0010h to 001Fh Lc p e9 ee a Le 3 CONTROLLER AREA NETWORK Cont d 10 7 4 2 Paged Registers LAST IDENTIFIER HIGH REGISTER LIDHR Read Write Reset Value Undefined 7 0 LID10 1109 108 LID6 LID5 LID4 LID3 LID 10 3 are the most significant 8 bits of the last Identifier read on the CAN bus LAST IDENTIFIER LOW REGISTER LIDLR Read Write Reset Value Undefined 7 0 LID2 LID1 LIDO LRTR p P peu LID 2 0 are the least significant 3 bits of the last Identifier read on the CAN bus LRTR is the last Remote Transmission Request bit read on the CAN bus LDLC 3 0 is the last Data Length Code read on the CAN bus ST72311R ST72511R ST72512R ST72532R TRANSMIT ERROR COUNTER REG TECR Read Only Reset Value 00h 7 0 TEC6 5 TEC4 2 1 TECO 7 0 is the least significant byte of the 9 bit Transmit Error Counter implementing part of the fault confinement mechanism of the CAN protocol In case of an error during transmission this counter is incremented by 8 It is decremented by 1 after every successful transmission When the counter value exceeds 127 the CAN controller enters the error passive state When avalue of 256 is reached the CAN controller is d
79. ER AREA NETWORK 10 7 3 4 Bit Timing Logic The bit timing logic monitors the serial bus line and performs sampling and adjustment of the sample point by synchronizing on the start bit edge and re synchronizing on following edges Its operation may be explained simply when the nominal bit time is divided into three segments as follows Synchronisation segment SYNC SEQ a bit change is expected to lie within this time seg ment It has a fixed length of one time quanta 1 X tcan Bit segment 1 BS1 defines the location of the sample point It includes the PROP SEG and PHASE SEG ofthe CAN standard Its duration is programmable between 1 and 16 time quanta but may be automatically lengthened to compen sate for positive phase drifts due to differences in the frequency of the various nodes of the net work Bit segment 2 BS2 defines the location of the transmit point It represents the PHASE SEG2 of the CAN standard Its duration is programma ble between 1 and8 time quanta but may also be automatically shortened to compensate for neg ative phase drifts Figure 59 Bit Timing The resynchronization jump width RJW defines an upper bound to the amount of lengthening or shortening of the bit segments It is programmable between 1 and 4 time quanta A valid edge is defined as the first transition in a bit time from dominant to recessive bus level provid ed the controller itself does not send a recess
80. ETPR Read Write Reset Value 0000 0000 00h Allows setting of the External Prescaler rate divi sion factor for the transmit circuit 7 0 ETPR ETPR ETPR ETPR ETPR ETPR ETPR 7 6 5 4 3 2 1 0 Bit 7 1 ETPR 7 0 8 bit Extended Transmit Pres caler Register The extended Baud Rate Generator is activated when a value different from is stored in this register Therefore the clock frequency issued from the 16 divider see Figure 54 is divided by the binary factor set in the ETPR register in the range 1 to 255 The extended baud rate generator is not used af ter a reset IDLE 0 0 0 LSB D D D D D 0052h SCIBRR SCP1 SCPO SCT2 SCT1 SCTO SCR2 SCR1 SCRO Reset Value 0 0 0 0 0 0 0 0 SCICR1 R8 T8 M WAKE 0054h SCICR2 TIE TCIE RIE ILIE TE RE RWU SBK Reset Value 0 0 0 0 0 0 0 0 SCIERPR MSB LSB SCIETPR MSB LSB 103 164 ST72311R ST72511R ST72512R ST72532R 10 7 CONTROLLER AREA NETWORK CAN 10 7 1 Introduction are checked for correctness and acknowledged This peripheral is designed to support serial data exchanges using a multi master contention based priority scheme as described in CAN specification Rev 2 0 part A It can also be connected to a 2 0 B network without problems since extended frames Figure 55 CAN Block Diagram ST7 Internal Bus m ST7 Interface TX RX TX RX TX RX ID Buffer 1 Buffer 2 Buffer 3 Filter 0 Filter 1 10 Bytes 10 Bytes 10 Bytes 4 Bytes 4 B
81. F Option Register 00h R W Reserved Area 9 Bytes SPI Data I O Register xxh R W SPI Control Register Oxh R W SPI Status Register 00h Read Only Interrupt Software Priority Register 0 FFh R W Interrupt Software Priority Register 1 FFh R W Interrupt Software Priority Register 2 FFh R W Interrupt Software Priority Register 3 FFh R W Reserved Area 1 Byte 0029h MCCSR Main Clock Control Status Register 12 164 437 ST72311R ST72511R ST72512R ST72532R Register e Reset 002Ah WDGCR Watchdog Control Register 7Fh 002Bh WDGSR Watchdog Status Register 000x 000x 002Ch EEPROM EECSR Data Data EEPROM ControlStatus Register Control Status Data EEPROM ControlStatus Register Reserved Area 4 Bytes TACR2 Timer A Control Register 2 R W TACR1 Timer A Control Register 1 R W TASR Timer A Status Register Read Only TAIC1HR Timer A Input Capture 1 High Register Read Only TAIC1LR Timer A Input Capture 1 Low Register Read Only Timer A Output Compare 1 High Register R W TAOC1LR Timer A Output Compare 1 Low Register R W TIMER A TACHR Timer A Counter High Register Read Only TACLR Timer A Counter Low Register Read Only TAACHR Timer A Alternate Counter High Register Read Only TAACLR Timer A Alternate Counter Low Register Read Only TAIC2HR Timer A Input Capture 2 High Register Read Only TAIC2LR Timer A Input Capture 2 Low Register Read Only TAOC2HR Timer A Output Compare 2 High Register R W TAOC2LR Timer A Outp
82. Floating 8 2 3 Alternate Functions When an on chip peripheral is configured to use a pin the alternate function is automatically select ed This alternate function takes priority over the standard I O programming When the signal is coming from an on chip periph eral the I O pin is automatically configured in out put mode push pull or open drain according to the peripheral When the signal is going to an on chip peripheral the I O pin must be configured in input mode In this case the pin state is also digitally readable by addressing the DR register Note Input pull up configuration can cause unex pected value at the input of the alternate peripheral input When an on chip peripheral use a pin as in put and output this pin has to be configured in in put floating mode r ST72311R ST72511R ST72512R ST72532R PORTS Cont d Figure 25 I O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS P BUFFER see table below Vpp e 3 ALTERNATE ENABLE PULL UP see table below A PULL UP CONDITION sna viva N BUFFER DIODES see table below ANALOG CMOS INPUT SCHMITT TRIGGER ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE ei POLARITY SELECTION Table 9 Port Mode Options Diodes Configuration Mode Floating with without Interrupt Off Pull up with without Interrupt On Push pull Off Output O
83. Master fopy 128 f 8MHz 0 0625 SPI clock frequency CPUT Slave fopy 8MHz AECH SPI clock rise and fall time see port pin description _ E Lm SS SS hold time Save 120 SE E 2 MI Master 100 Data input setup time Slave 100 th Master 100 Data input hold time Slave 100 Data output disable time sx fa t Dat tput valid ti 120 em ________ Slave after enable edge _ Data output hold time 5 Data output valid time 2 Master before capture edge 7 MO Data output hold time Figure 88 SPI Slave Timing Diagram with CPHA 0 3 thsi 0 4 en wn ee Notes 1 Data based on design simulation and or characterisation results not tested in production 2 When no communication is on going the data output line of the SPI MOSI in master mode MISO in slave mode has its alternate function capability released In this case the pin status depends on the I O port configuration 3 Measurement points are done at CMOS levels 0 3xVpp and 0 7xVpp 437 149 164 ST72311R ST72511R ST72512R ST72532R COMMUNICATIONS INTERFACE CHARACTERISTICS Cont d Figure 89 SPI Slave Timing Diagram with CPHA 1 CPOL 0 0 CPOL 1 TT rte 2 1 thst eet EI woes OXON XXX XXX Notes 1 Measurement points are done at CMOS levels 0 3xVpp and 0 7xVpp 2 When no communicatio
84. NCOUNTER DIVIDER 12288 49 164 ST72311R ST72511R ST72512R ST72532R WATCHDOG TIMER Cont d The application program must write in the CR reg ister at regular intervals during normal operation to prevent an MCU reset The value to be stored in the CR register must be between FFh and COh see Table 14 Watchdog Timing fCPU 8 MHz The WDGA bit is set watchdog enabled The T6 bit is set to prevent generating an imme diate reset The T 5 0 bits contain the number of increments which represents the time delay before the watchdog produces a reset Table 14 Watchdog Timing fcpy 8 MHz CR Register WDG timeout period initial value ms Max FFh Min COh 98 304 1 536 Notes Following a reset the watchdog is disa bled Once activated it cannot be disabled except by areset The T6 bit can be used to generate a software re set the WDGA bit is set and the T6 bit is cleared If the watchdog is activated the HALT instruction will generate a Reset 10 1 4 Hardware Watchdog Option If Hardware Watchdog is selected by option byte the watchdog is always active and the WDGA bit in the CR is not used Refer to the device specific Option Byte descrip tion 10 1 5 Low Power Modes No effect on Watchdog Immediate reset generation as soon as the HALT instruction is executed if the Watchdog is activated WDGA bit is set 10 1 6 Interrupts None 50 164
85. NG MODES Cont d 7 4 ACTIVE HALT AND HALT MODES ACTIVE HALT and HALT modes are the two low est power consumption modes of the MCU They are both entered by executing the HALT instruc tion The decision to enter either in ACTIVE HALT or HALT mode is given by the MCC RTC interrupt enable flag OIE bit in MCCSR register MCCSR Power Saving Mode entered when HALT OIE bit instruction is executed HALT mode ACTIVE HALT mode 7 4 1 ACTIVE HALT MODE ACTIVE HALT mode is the lowest power con sumption mode of the MCU with a real time clock available It is entered by executing the HALT in struction when the OIE bit of the Main Clock Con troller Status register MCCSR is set see Section 10 2 on page 52 for more details on the MCCSR register The MCU can exit ACTIVE HALT mode on recep tion of either an MCC RTC interrupt a specific in terrupt see Table 7 Interrupt Mapping on page 32 or a RESET When exiting ACTIVE HALT mode by means of a RESET or an interrupt a 4096 CPU cycle delay occurs After the start up delay the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up see Figure 22 When entering ACTIVE HALT mode the I 1 0 bits in the CC register are forced to 10 to enable inter rupts Therefore if an interrupt is pending the MCU wakes up immediately In ACTIVE HALT mode only the main oscillator and its associated counter MCC RTC are run ning to
86. OFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED When an interrupt request is not serviced immedi ately it is latched and then processed when its software priority combined with the hardware pri ority becomes the highest one Note 1 The hardware priority is exclusive while the software one is not This allows the previous process to succeed with only one interrupt Note 2 RESET TRAP and TLI are non maskable and they can be considered as having the highest software priority in the decision process Different Interrupt Vector Sources Two interrupt source types are managed by the ST7 interrupt controller the non maskable type RESET TLI TRAP and the maskable type ex ternal or from internal peripherals Non Maskable Sources These sources are processed regardless of the state of the 11 and 10 bits of the CC register see Figure 14 After stacking the PC X A and CC registers except for RESET the corresponding vector is loaded in the PC register and the 1 and r ST72311R ST72511R ST72512R ST72532R 10 bits of the CC are set to disable interrupts level 3 These sources allow the processor to exit HALT mode m ILI Top Level Hardware Interrupt This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin Its de tailed specification is given in the Miscellaneous register chapter m TRAP Non Maskable Software Interrupt This software interrupt is service
87. OLVL1 OLVL2 a continuous signal will be seen on the pin 4 The ICAP1 pin not be used to perform input capture The ICAP2 pin can be used to perform input capture ICF2 can be set and IC2R can be loaded but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set 5 When one pulse mode is used is dedi cated to this mode Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an out put waveform because the level OLVL2 is dedi cated to the one pulse mode r ST72311R ST72511R ST72512R ST72532R 16 BIT TIMER Cont d Figure 44 One Pulse Mode Timing Example comparet Note IEDG1 1 OC1R 2ED0h OLVL1 0 OLVL2 1 Figure 45 Pulse Width Modulation Mode Timing Example COUNTER 34E2KFFFC FFFDYFFFE 2ED0 2ED 1X2E D2 34E2 OCMP1 OLVL2 OLVL1 compare2 comparet compare2 Note OC1R22bEDOh OC2R 34E2 OLVL1 0 OLVL2 1 71 164 ST72311R ST72511R ST72512R ST72532R 16 BIT TIMER Cont d 10 4 3 6 Pulse Width Modulation Mode Pulse Width Modulation PWM mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers The pulse width modulation mode uses the com plete Output Compare 1 function plus the OC2R register and so these functional
88. Red Dc det eqs se n Peg ode da 148 12 11 COMMUNICATIONS INTERFACE CHARACTERISTICS 149 12 11 1SPI Serial Peripheral Interface 149 12 11 2SCI Serial Communications Interface 151 12 11 3CAN Controller Area Network Interface 151 12 12 8 ADC CHARACTERISTICS 152 13 PACKAGE CHARACTERISTICS 154 13 1 PACKAGE MECHANICAL DATA 154 13 2 THERMAL 5 155 13 3 SOLDERING AND GLUEABILITY 156 13 4 PACKAGE SOCKET FOOTPRINT PROPOSAL 157 14 DEVICE CONFIGURATION AND ORDERING INFORMATION 158 14a OPTIONIBVIES e rex Ra CE ev ES ea eae ew Kendra 158 14 2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE 159 14 8 DEVELOPMENT TOOLS 1 161 15 ST7 GENERIC APPLICATION NOTE 162 16 SUMMARY OF CHANGES 163 5 5 164 ST72311R ST72511R ST72512R ST72532R 1 GENERAL DESCRIPTION 1 1 INTRODUCTION The ST72311R ST72511R 577251298 and ST72532R devices a
89. SC Where At Output compare period in seconds CPU clock frequency in hertz PRESC Timer prescaler factor 2 4 or 8 de pending on CC 1 0 bits see Table 18 Clock Control Bits If the timer clock is an external clock the formula is A OCR At fex Where At Output compare period in seconds fexr External timer clock frequency in hertz Clearing the output compare interrupt request i e clearing the OCFi bit is done by 1 Reading the SR register while the OCFi bit is set 2 An access read or write to the register The following procedure is recommended to pre vent the OCFi bit from being set between the time it is read and the write to the register Write to the OC HR register further compares are inhibited Read the SR register first step of the clearance of the OCFi bit which may be already set Write to the register enables the output compare function and clears the OCFi bit 67 164 ST72311R ST72511R ST72512R ST72532R 16 BIT TIMER Cont d Notes 1 After a processor write cycle to the OC HR reg ister the output compare function is inhibited until the register is also written If the bit is not set the pin is a general I O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set When the timer clock is fopy 2 OCFi and O
90. T These sources act on the RESET pin and it is al ways kept low during the delay phase The RESET service routine vector is fixed at ad dresses FFFEh FFFFh in the ST7 memory map The basic RESET sequence consists of 3 phases as shown in Figure 11 m Delay depending on the RESET source m 4096 CPU clock cycle delay m RESET vector fetch Figure 12 Reset Block Diagram ST72311R ST72511R ST72512R ST72532R The 4096 CPU clock cycle delay allows the oscil lator to stabilise and ensures that recovery has taken place from the Reset state The RESET vector fetch phase duration is 2 clock cycles Figure 11 RESET Sequence Phases RESET DELAY INTERNAL RESET FETCH 4096 CLOCK CYCLES VECTOR INTERNAL RESET COUNTER WATCHDOG RESET LVD RESET 25 164 ST72311R ST72511R ST72512R ST72532R RESET SEQUENCE MANAGER Cont d 5 2 2 Asynchronous External RESET pin The RESET pin is both an input and an open drain output with integrated Row weak pull up resistor This pull up has no fixed value but varies in ac cordance with the input voltage It can be pulled low by external circuitry to reset the device See electrical characteristics section for more details A RESET signal originating from an external source must have a duration of at least th RsTLyin In order to be recognized as shown in Figure 13 this detection is asynchronous and therefore the MCU can enter reset state even in HALT mode The RESE
91. T pin is an asynchronous signal which plays a major role in EMS performance In a noisy environment it is recommended to follow the guidelines mentioned in the electrical characteris tics section Figure 13 RESET Sequences EXTERNAL RESET SOURCE 1 WATCHDOG RESET 26 164 5 2 3 Internal Low Voltage Detection RESET Two different RESET sequences caused by the in ternal LVD circuitry can be distinguished m Power On RESET m Voltage Drop RESET The device RESET pin acts as an output that is pulled low when Vpp Vir rising edge or Vpp lt V r falling edge as shown in Figure 13 The LVD filters spikes on Vpp larger than to avoid parasitic resets 5 2 4 Internal Watchdog RESET The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 13 Starting from the Watchdog counter underflow the device RESET pin acts as an output that is pulled low during tw RSTL out CAUTION this output signal as not enought ener gy to be used to drive external devices WATCHDOG RESET SHORT EXT RESET DELAY E WATCHDOG UNDERFLOW 4 INTERNAL RESET 4096 Topu EL FETCH VECTOR 4 ST72311R ST72511R ST72512R ST72532R 5 3 LOW CONSUMPTION OSCILLATOR The fosc main clock of the ST7 be generated Table 4 517 Clock Sources by two different source types y Hardware Configuration m an external source m acrystalor ceramic resonato
92. T72512R ST72532R SERIAL PERIPHERAL INTERFACE Cont d Figure 49 Data Clock Timing Diagram SCLK with CPOL 1 SCLK with Note This figure should not be used as a replacement for parametric information Refer to the Electrical Characteristics chapter VR02131B 4 84 164 SERIAL PERIPHERAL INTERFACE Cont d 10 5 4 4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is tak ing place with an external device When this hap pens the transfer continues uninterrupted and the software write will be unsuccessful Write collisions can occur both in master and slave mode Note a read collision will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU oper ation In Slave mode When the CPHA bit is set The slave device will receive a clock SCK edge prior to the latch of the first data transfer This first clock edge will freeze the data in the slave device DR register and output the MSBit on to the exter nal MISO pin of the slave device The SS pin low state enables the slave device but the output of the MSBit onto the MISO pin does not take place until the first data transfer clock edge ST72311R ST72511R ST72512R ST72532R When the CPHA bit is reset Data is latched on the occurrence of the first clock transition The slave device does not have any way of knowing when t
93. a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor see Figure 82 Data based on design simulation and or technology characteristics not tested in production 5 The Rpy pull up equivalent resistor is based on a resistive transistor This data is based on characterization results not tested in production 6 To generate an external interrupt a minimum pulse width has to be applied on an I O port pin configured as an external interrupt source 145 164 ST72311R ST72511R ST72512R ST72532R PORT PIN CHARACTERISTICS Cont d 12 8 2 Output Driving Current Subject to general operating condition for Vpp fosc and T4 unless otherwise specified Output low level voltage for a standard I O pin 5 13 when 8 pins are sunk at same time Output low level voltage for a high sink I O pin 10 20 13 when 4 pins are sunk at same time Output high level voltage for an I O pin 5 Vpp20 when 8 pins are sourced at same time Figure 83 Typical Vo at Vpp 5V standard Figure 85 Typical at Vpp 5V Vol V P Vdd Voh V Ta 40 C Vdd 5V Vdd 5V 1 5 Ta 25 C 85 125 a lio mA Vol V Vdd 5V mA Notes 1 The ljo current sunk must always respect the absolute maximum rating specified in Section 12 2 2 and the sum of lig I O ports and control pins must not exceed lys
94. aler m clock out signal to supply external devices m realtime clock timer with interrupt capability Each function can be used independently and si multaneously 10 2 1 Programmable CPU Clock Prescaler The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal periph erals It manages SLOW power saving mode See Section 7 2 SLOW MODE on page 34 for more details The prescaler selects the main clock frequen cy and is controlled by three bits in the MISCR1 register CP 1 0 and SMS CAUTION The prescaler does not act on the CAN peripheral clock source This peripheral is always supplied by the fosc 2 clock source 10 2 2 Clock out Capability The clock out capability is an alternate function of an I O port pin that outputs a fosc 2 clock to drive external devices It is controlled by the MCO bit in the MISCR1 register CAUTION When selected the clock out pin sus pends the clock during ACTIVE HALT mode 10 2 3 Real Time Clock Timer RTC The counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock Four different time bases depend ing directly on fosc are available The whole func tionality is controlled by four bits of the MCCSR register TB 1 0 OIE and OIF When the RTC interrupt is enabled OIE bit set the ST7 enters ACTIVE HALT mode when the HALT instruction is executed See Section 7 4 ACTIVE HALT AND HALT MO
95. and Reset Values Address Register Hex Label SPIDR MSB Reset Value Cas SPICR mE E He 0022h Reset Value SPISR SPIF WCOL MODF 91 164 ST72311R ST72511R ST72512R ST72532R 10 6 SERIAL COMMUNICATIONS INTERFACE SCI 10 6 1 Introduction The Serial Communications Interface SCI offers a flexible means of full duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format The SCI of fers a very wide range of baud rates using two baud rate generator systems 10 6 2 Main Features m Full duplex asynchronous communications m NRZ standard format Mark Space m Dual baud rate generator systems Independently programmable transmit and receive baud rates up to 250K baud Programmable data word length 8 or 9 bits Receive buffer full Transmit buffer empty and End of Transmission flags Two receiver wake up modes Address bit MSB Idle line m Muting function for multiprocessor configurations Separate enable bits for Transmitter and Receiver Three error detection flags Overrun error Noise error Frame error Five interrupt sources with flags Transmit data register empty Transmission complete Receive data register full Idle line received Overrun error detected 92 164 10 6 3 General Description The interface is externally connected to another device by two pins see
96. andard For more details refer to the AN1181 ST7 application note Electrical Sensitivities Symbol Parameter SS Static latch up class DLU Dynamic latch up class m DLU Electro Static Discharges one positive then one negative test are applied to each pin of 3 samples when the micro is running to assess the latch up performance in dynamic mode Power supplies are set to the typical values the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode This test conforms to the IEC1000 4 2 and SAEJ1752 3 standards and is described in Figure 76 For more details refer to the AN1181 ST7 application note 25 85 Vpp 5 5V fosc 4MHz 25 Figure 76 Diagram of the ESD Generator for DLU Cg 150pF ESD GENERATOR 2 HV RELAY DISCHARGE RETURN CONNECTION Notes 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the spec ifications that means when a device belongs to Class A it exceeds the JEDEC standard B Class strictly covers all the JEDEC criteria international standard 2 Schaffner NSG435 with a pointed test finger 142 164 3 CHARACTERISTICS Cont d 12 7 3 ESD Pin Protection Strategy To protect an integrated circuit against Electro Static Discharge the stress must be controlled to prevent degradation or destruction of the circuit
97. anges in run mode or whenever a dominant pulse is received in standby mode Cleared by software to disable status change inter rupt requests Bit 2 ORIE Overrun Interrupt Enable Read Set Clear Set by software to enable an interrupt request whenever a message should be stored and no re ceive buffer is avalaible Cleared by software to disable overrun interrupt re quests Bit 1 TEIE Transmit Error Interrupt Enable Read Set Clear Set by software to enable an interrupt whenever an error has been detected during transmission of a message Cleared by software to disable transmit error inter rupts Bit 0 ETX Early Transmit Interrupt Read Set Clear Set by software to request the transmit interrupt to occur as soon as the arbitration phase has been passed successfully Cleared by software to request the transmit inter rupt to occur at the completion of the transfer 3 CONTROLLER AREA NETWORK Cont d CONTROL STATUS REGISTER CSR Read Write Reset Value 00h 7 0 EX EPSV SRTE NRTX FSYN wees nu Bit 6 BOFF Bus Off State Read Only Set by hardware to indicate that the node is in bus off state i e the Transmit Error Counter exceeds 255 Reset by hardware to indicate that the node is in volved in bus activities Bit 5 EPSV Error Passive State Read Only Set by hardware to indicate that the node is error passive Reset by hardware to indicate that the node is eith
98. ault occurs when the master device has its SS pin pulled low then the MODF bit is set Master mode fault affects the SPI peripheral in the following ways The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set The SPE bit is reset This blocks all output from the device and disables the SPI periph eral The MSTR bit is reset thus forcing the device into slave mode Clearing the MODF bit is done through a software sequence 1 A read or write access to the SR register while the MODF bit is set 2 A write to the CR register Notes To avoid any multiple slave conflicts in the case of a system comprising several MCUs the SS pin must be pulled high during the clearing se quence of the MODF bit The SPE and MSTR bits 86 164 may be restored to their original state during or af ter this clearing sequence Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence In a slave device the MODF bit can not be set but in a multi master configuration the device can be in slave mode with this MODF bit set The MODF bit indicates that there might have been amulti master conflict for system control and allows a proper exit from system operation to a re set or default system state using an interrupt rou tine 10 5 4 6 Overrun Condition An overrun condition occurs when the master de vice has sent several data bytes an
99. ble interrupt priority level management Up to 4 software programmable nesting levels Up to 16 interrupt vectors fixed by hardware 8 non maskable events TLI RESET TRAP This interrupt management is based on Bit 5 and bit 3 of the CPU CC register 11 0 Interrupt software priority registers ISPRx Fixed interrupt vector addresses located at the high addresses of the memory map FFEOh to FFFFh sorted by hardware priority order This enhanced interrupt controller guarantees full upward compatibility with the standard not nest ed ST7 interrupt controller 6 2 MASKING AND PROCESSING FLOW The interrupt masking is managed by the 11 and 10 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector see Table 5 The process ing flow is shown in Figure 14 Figure 14 Interrupt Processing Flowchart PENDING INTERRUPT FETCH NEXT INSTRUCTION RESTORE PC X A CC FROM STACK 28 164 EXECUTE INSTRUCTI ON When an interrupt request has to be serviced Normal processing is suspended at the end of the current instruction execution The PC X A and CC registers are saved onto the stack 11 and 10 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector The PC isthen loaded with the interrupt vector of the interrupt to service and the firs
100. can be also set cleared by software with the RIM SIM HALT WFI and PUSH POP instructions See the interrupt management chapter for more details IRET 21 164 ST72311R ST72511R ST72512R ST72532R CENTRAL PROCESSING UNIT Cont d Stack Pointer SP Read Write Reset Value 01 FFh 15 8 DESS H 0 ell The Stack Pointer is a 16 bit register which is al ways pointing to the next free location in the stack It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack see Figure 8 Since the stack is 256 bytes deep the 8 most sig nificant bits are forced by hardware Following an MCU Reset or after a Reset Stack Pointer instruc tion RSP the Stack Pointer contains its reset val ue the SP7 to SPO bits are set which is the stack higher address Figure 8 Stack Manipulation Example CALL Interrupt Subroutine Event Stack Higher Address 01FFh Stack Lower Address 0100h 22 164 The least significant byte of the Stack Pointer called S can be directly accessed by a LD in struction Note When the lower limit is exceeded the Stack Pointer wraps around to the stack upper limit with out indicating the stack overflow The previously stored information is then overwritten and there fore lost The stack also wraps in case of an under flow The stack is used to save the return address dur ing a subroutine call and the CPU context
101. clock input or crystal ceramic resona tor oscillator inverter input 9 164 ST72311R ST72511R ST72512R ST72532R function FEUTDO TX DX P9 89 Sor Trane Data CLE PE S6 Receive Dare n io 6r x GAN Transmit Data 11 Pon es CAN Receive Data Notes 1 In the interrupt input column eiX defines the associated external interrupt vector If the weak pull up column is merged with the interrupt column int then the I O configuration is pull up interrupt input else the configuration is floating interrupt input 2 Inthe open drain output column defines a true open I O P Buffer and protection diode to V not implemented See Section 8 PORTS on page 38 and Section 12 8 PORT PIN CHAR ACTERISTICS on page 145 for more details 3 OSC1 and OSC2 pins connect a crystal ceramic resonator or an external source to the on chip oscillator see Section 1 2 PIN DESCRIPTION on page 7 and Section 12 5 CLOCK AND TIMING CHARACTER ISTICS on page 138 for more details 4 10 164 1 3 REGISTER amp MEMORY As shown in the Figure 3 the MCU is capable of addressing 64K bytes of memories and regis ters The available memory locations consist of 128 bytes of register location up to 2Kbytes of RAM up to 256 bytes of data EEPROM and up to Figure 3 Memory Map
102. d all peripherals switched off clock input 05 1 driven by external square wave LVD disabled 3 136 164 ST72311R ST72511R ST72512R ST72532R SUPPLY CURRENT CHARACTERISTICS Cont d 12 4 3 HALT and ACTIVE HALT Modes Symbol 2 Paameer Conditions Supply current in ACTIVE HALT mode CTT IE Supply current in HALT mode Vpps5 5V 40 lt lt 125 12 4 4 Supply and Clock Managers The previous current consumption specified for source current consumption To get the total de the ST7 functional operating modes over tempera vice consumption the two current values must be ture range does not take into account the clock added except for HALT mode LVD supply current HALT mode 12 4 5 Symbol Parameter 0000 16 bit Timer supply current 8 fopy 8MHz Vos v Von 50V Voo 33V SPI supply current 9 fcpu 8MHz 5 6 Vpp 3 3V 800 Ipp Apc ADC supply current when converting 19 fApc 4MHz Notes 1 Typical data are based on 25 2 All I O pins in input mode with a static value at Vpp or Vgs no load LVD disabled 3 Data based on design simulation and or technology characteristics not tested in production All I O pins in input mode with a static value at Vss no load clock input OSC1 driven by external square wave LVD disabled 4 Typical
103. d back as 1 in the meantime to enable proper signalling ofthe standby state The CPU clock may therefore be safely switched OFF whenever RUN is read as O 113 164 ST72311R ST72511R ST72512R ST72532R CONTROLLER AREA NETWORK Cont d BAUD RATE PRESCALER REGISTER BRPR Read Write in Standby mode Reset Value 00h BIT TIMING REGISTER BTR Read Write in Standby mode Reset Value 23h 7 0 T 0 RJW1 5 BRP4 BRP2 1 8522 BS21 BS20 513 12 11 BS10 RJW 1 0 determine the maximum number of time quanta by which a bit period may be shortened or lengthened to achieve resynchronization Ion RJW 1 BRP 5 0 determine the CAN system clock cycle time or time quanta which is used to build up the in dividual bit timing tcan topu BRP 1 Where tcpy time period of the CPU clock The resulting baud rate can be computed by the for mula 1 BR _ tcpy X BRP 1 x BS1 BS2 3 Note Writing to this register is allowed only in Standby mode to prevent any accidental CAN pro tocol violation through programming errors 114 164 BS2 2 0 determine the length of Bit Segment 2 1352 tcan 52 1 BS1 3 0 determine the length of Bit Segment 1 1851 tcan 1 Note Writing to this register is allowed only in Standby mode to prevent any accidental CAN pro tocol violation through programming errors PAGE SELECTION REGIST
104. d the slave de vice has not cleared the SPIF bit issuing from the previous data byte transmitted In this case the receiver buffer contains the byte sent after the SPIF bit was last cleared A read to the DR register returns this byte All other bytes are lost This condition is not detected by the SPI peripher al 3 SERIAL PERIPHERAL INTERFACE Cont d ST72311R ST72511R ST72512R ST72532R 10 5 4 7 Single Master and Multimaster Configurations There are two types of SPI systems Single Master System Multimaster System Single Master System A typical single master system may be configured using an MCU as the master and four MCUs as slaves see Figure 51 The master device selects the individual slave de vices by using four pins of a parallel port to control the four SS pins of the slave devices The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time thus disabling the slave devices Note To prevent a bus conflict on the MISO line the master allows only one active slave device during a transmission Figure 51 Single Master Configuration For more security the slave device may respond to the master with the received data byte Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are con nected and the slave has not written its DR regis ter Other transmission security methods can use ports fo
105. d when the TRAP instruction is executed It will be serviced accord ing to the flowchart on Figure 14 as a TLI m RESET The RESET source has the highest priority in the ST7 This means that the first current routine has the highest software priority level 3 and the high est hardware priority See the RESET chapter for more details Maskable Sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority in ISPRx registers is higher than the one currently being serviced 1 and 10 in CC register If any of these two condi tions is false the interrupt is latched and thus re mains pending m External Interrupts External interrupts allow the processor to exit from HALT low power mode External interrupt sensitivity is software selectable through the Miscellaneous registers MISCRx External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine If several input pins of a group connected to the same interrupt line are selected simultaneously these will be logically ORed m Peripheral Interrupts Usually the peripheral interrupts cause the MCU to exit from HALT mode except those mentioned in the Interrupt Mapping table A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the
106. e Reset Value 0000 0000 00h ST72311R ST72511R ST72512R ST72532R DUTY CYCLE REGISTERS DCRx Read Write Reset Value 0000 0000 00h 0 7 0 ora om Bit 7 4 OE 3 0 PWM Output Enable These bits are set and cleared by software They enable or disable the PWM output channels inde pendently acting on the corresponding 0 PWM output disabled 1 PWM output enabled Bit 3 0 OP 3 0 PWM Output Polarity These bits are set and cleared by software They independently select the polarity of the four PWM output signals PWMx output level Note When an OPx bit is modified the PWMx out put signal polarity is immediately reversed Bit 7 0 DC 7 0 Duty Cycle Data These bits are set and cleared by software A DCRx register is associated with the OCRx reg ister of each PWM channel to determine the sec ond edge location of the PWM signal the first edge location is common to all channels and given by the ARR register These DCR registers allow the duty cycle to be set independently for each PWM channel 59 164 ST72311R ST72511R ST72512R ST72532R PWM AUTO RELOAD TIMER Cont d Table 17 PWM Auto Reload Timer Register Map and Reset Values Address Register 7 Hex Label 0072h PWMDCR3 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DCO Reset Value 0 0 0 0 0 0 0 0 0 0 0073h PWMDCR2 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DCO Reset Value 0 0 0 0 0 0 0 0074h PWMDCR1
107. e the SPIF bit is set 2 A write or a read of the DR register Notes While the SPIF bit is set all writes to the DR register are inhibited until the SR register is read The SPIF bit can be cleared during a second transmission however it must be cleared before the second SPIF bit in order to prevent an overrun condition see Section 10 5 4 6 Depending on the CPHA bit the SS pin has to be set to write to the DR register between each data byte transfer to avoid a write collision see Section 10 5 4 4 3 SERIAL PERIPHERAL INTERFACE Cont d 10 5 4 3 Data Transfer Format During an SPI transfer data is simultaneously transmitted shifted out serially and received shifted in serially The serial clock is used to syn chronize the data transfer during a sequence of eight clock pulses The SS pin allows individual selection of a slave device the other slave devices that are not select ed do not interfere with the SPI transfer Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software using the CPOL and CPHA bits The CPOL clock polarity bit controls the steady state value of the clock when no data is being transferred This bit affects both master and slave modes The combination between the CPOL and CPHA clock phase bits selects the data capture clock edge Figure 49 shows an SPI transfer with the four combinations of the CPHA and CPOL bits The di agram may be interp
108. e to exit from WAIT mode If an input capture event occurs on the ICAP pin the input capture detection circuitry is armed Consequent ly when the MCU is woken up by an interrupt with exit from HALT mode capability the ICF bit is set and the counter value present when exiting from HALT mode is captured into the register 16 bit Timer registers are frozen In HALT mode the counter stops counting until Halt mode is exited Counting resumes from the previous count when the MCU is woken up by an interrupt with exit from HALT mode capability or from the counter HALT reset value when the MCU is woken up by a RESET 10 4 5 Interrupts Interrupt Event Input Capture 1 event Counter reset in PWM mode ICF1 Input Capture 2 event ICF2 Output Compare 1 event not available in PWM mode OCF1 OCIE ee Output Compare 2 event not available in PWM mode OCF2 Yes ves Note The 16 bit Timer interrupt events are connected to the same interrupt vector see Interrupts chap ter These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset RIM instruction 10 4 6 Summary of Timer modes AVAILABLE RESOURCES Input Capture 1 Input Capture2 Output Compare 1 Output Compare 2 input Capture and or 2 Compare 2 One Pulse Mode Not Recommended Partially PWM Mode Not Recommended 1 See note 4 in Section 1
109. eared by software to release buffer 2 Also cleared by resetting bit RDY of BCSR2 Bit 5 RXIF1 Receive Interrupt Flag for Buffer 1 Read Clear Set by hardware to signal that a new error free mes sage is available in buffer 1 Cleared by software to release buffer 1 Also cleared by resetting bit RDY of BCSR1 ST72311R ST72511R ST72512R ST72532R Bit 4 TXIF Transmit Interrupt Flag Read Clear Set by hardware to signal that the highest priority message queued for transmission has been suc cessfully transmitted ETX 0 or that it has passed successfully the arbitration ETX 1 Cleared by software Bit 3 SCIF Status Change Interrupt Flag Read Clear Set by hardware to signal the reception of a domi nant bit while in standby or a change from error ac tive to error passive and bus off while in run Also signals any receive error when ESCI 1 Cleared by software Bit 2 ORIF Overrun Interrupt Flag Read Clear Set by hardware to signal that a message could not be stored because no receive buffer was available Cleared by software Bit 1 TEIF Transmit Error Interrupt Flag Read Clear Set by hardware to signal that an error occurred dur ing the transmission ofthe highest priority message queued for transmission Cleared by software Bit 0 EPND Error Interrupt Pending Read Only Set by hardware when at least one of the three error interrupt flags SCIF ORIF or TEIF is set
110. ecognised an Idle Frame Then the RWU bit is reset by hardware but the IDLE bit is not set Receiver wakes up by Address Mark detection when it received 1 as the most significant bit of a word thus indicating that the message is an ad dress The reception of this particular word wakes up the receiver resets the RWU bit and sets the RDREF bit which allows the receiver to receive this word normally and to use it as an address word 3 ST72311R ST72511R ST72512R ST72532R SERIAL COMMUNICATIONS INTERFACE Cont d 10 6 5 Low Power Modes Mode Description WAIT No effect on SCI SCI interrupts cause the device to exit from Wait mode SCI registers are frozen In Halt mode the SCI stops transmitting receiving until Halt mode is exited 10 6 6 Interrupts Enable Interrupt Event Control Bit Transmit Data Register Empty TDRE Transmission Complete TCIE i RDRF Y N Received Data Ready to be Read RDRF RIE Overrrun Error Detected OR Idle Line Detected IDLE ILIE The SCI interrupt events are connected to the These events generate an interrupt if the corre same interrupt vector see Interrupts chapter sponding Enable Control Bit is set and the inter rupt mask in the CC register is reset RIM instruc tion 99 164 ST72311R ST72511R ST72512R ST72532R SERIAL COMMUNICATIONS INTERFACE Cont d 10 6 7 Register Description STATUS REGISTER SR Read Only Reset Value 1100 0000 CO
111. ed It is cleared by hardware when RE 0 by a software sequence an access to the SR register followed by a read to the DR register 0 No Framing error is detected 1 Framing error or break character is detected Note This bit does not generate interrupt as it ap pears at the same time as the bit which it self generates an interrupt If the word currently being transferred causes both frame error and overrun error it will be transferred and only the OR bit will be set Bit 0 Unused 3 SERIAL COMMUNICATIONS INTERFACE Cont d CONTROL REGISTER 1 CR1 Read Write Reset Value Undefined 7 0 Bit 7 R8 Heceive data bit 8 This bit is used to store the 9th bit of the received word when 1 Bit 6 T8 Transmit data bit 8 This bit is used to store the 9th bit of the transmit ted word when M21 Bit 4 M Word length This bit determines the word length It is set or cleared by software 0 1 Start bit 8 Data bits 1 Stop bit 1 1 Start bit 9 Data bits 1 Stop bit Bit 3 WAKE Wake Up method This bit determines the SCI Wake Up method it is set or cleared by software 0 ldle Line 1 Address Mark CONTROL REGISTER 2 CR2 Read Write Reset Value 0000 0000 00h 7 0 Bit 7 TIE Transmitter interrupt enable This bit is set and cleared by software 0 interrupt is inhibited 1 An SCI interrupt is generated whenever TDRE 1 in the SR register Bit 6 TCIE Transmission complete interrupt ena
112. efines which bits of the acceptance filter should match the identifier and the RTR bit of the incoming mes sage MSK 0 don t care 1 match required MASK LOW REGISTERS MLRx Read Write Reset Value Undefined 7 0 e e MSK 3 0 are the least significant 4 bits of a 12 bit message mask 117 164 ST72311R ST72511R ST72512R ST72532R CONTROLLER AREA NETWORK Figure 60 CAN Register Map 2 Pagol adged ect 806860 Paged Reg15 4 118 164 ST72311R ST72511R ST72512R ST72532R CONTROLLER AREA NETWORK Figure 61 Page Maps DATA61 DATA62 DATA63 DATA71 DATA72 DATA73 Reserved Reserved Reserved Reserved BCSR1 BCSR2 BCSR3 Diagnosis Buffer 1 Buffer 2 Buffer 3 Acceptance Filters 119 164 ST72311R ST72511R ST72512R ST72532R CONTROLLER AREA NETWORK Table 23 CAN Register Map and Reset Values Address Register 5A CANISR RXIF3 RXIF2 RXIF1 TXIF SCIF ORIF TEIF EPND Reset Value 0 0 0 0 0 0 0 0 5B CANICR ESCI RXIE TXIE SCIE ORIE TEIE ETX Reset Value 0 0 0 0 0 0 0 CANCSR BOFF EPSV SRTE NRTX FSYN WKPS RUN Reset Value 0 0 0 0 0 0 0 CANBRPR RJW1 RJWO BRP5 BRP4 BRP3 BRP2 BRP1 BRPO Reset Value 0 0 0 0 0 0 0 0 CANBTR BS22 BS21 BS20 BS13 BS12 BS11 BS10 Reset Value 0 1 0 0 0 1 1 CANPSR 2 PAGE1 PAGEO Reset Value 0 0 0 CANLIDHR LID10 LID9 LID8 LID7 LID6 LID5 LID4 LID3 Reset Value x x x
113. el ements The stress generally affects the circuit el ements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress The elements to be pro tected must not receive excessive current voltage or heating within their structure An ESD network combines the different input and output ESD protections This network works by al lowing safe discharge paths for the pins subjected to ESD stress Two critical ESD stress cases are presented in Figure 77 and Figure 78 for standard pins and in Figure 79 and Figure 80 for true open drain pins ST72311R ST72511R ST72512R ST72532R Standard Pin Protection To protect the output structure the following ele ments are added A diode to Vpp and a diode from Vas 3b A protection device between Vpp and Vss 4 To protect the input structure the following ele ments are added A resistor in series with the pad 1 A diode to Vpp 2a and a diode from Vss 2b A protection device between Vpp Vss 4 Figure 77 Positive Stress a Standard Pad vs Vss Main path Path to avoid 143 164 ST72311R ST72511R ST72512R ST72532R EMC CHARACTERISTICS Cont d True Open Drain Pin Protection The centralized protection 4 is not involved in the discharge of the ESD stresses applied to true open drain pads due to the fact that a P Buffer and diode to Vpp are not implemented An additional loca
114. elines E 139 164 ST72311R ST72511R ST72512R ST72532R 12 7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba sis during product characterization 12 7 1 Functional EMS Electro Magnetic Susceptibility Based on a simple running application on the product toggling 2 LEDs through UO ports the product is stressed by two electro magnetic events until a failure occurs indicated by the LEDs m ESD Electro Static Discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 1000 4 2 standard m Burst of Fast Transient voltage positive and negative is applied to Vpp and Vss through a 100pF capacitor until a functional disturbance occurs This test conforms with the IEC 1000 4 4 standard A device reset allows normal operations to be re sumed Conditions Vpp 5V ENT M fosc 8BMHz conforms to IEC 1000 4 2 Paameer Voltage limits to be applied on any to induce a functional disturbance Fast transient voltage burst limits to be ap plied through 100pF on Vpp and Vpp pins to induce a functional disturbance Vpp 5V Ta 25 C fogo 8MHz conforms to IEC 1000 4 4 ST72XXX ST7 DIGITAL NOISE FILTERING POWER SUPPLY SOURCE NOISE FILTERING Notes 1 Data based on characterization results not tested in production
115. elow 1MHz 2 Operating conditions with 40 to 125 C 437 133 164 ST72311R ST72511R ST72512R ST72532R OPERATING CONDITIONS Cont d 12 3 2 Operating Conditions with Low Voltage Detector LVD Subject to general operating condition for Vpp fosc and T4 Symbol Parameter Conditons min Typ umi Reset release threshold Reset generation threshold g Vus 00 votage threshoid hysteresis Vive Lt Vicon Ci Or aveo Fitered atch delay on Voo Figure 68 LVD Threshold Versus Von and fosc for ROM devices 2 FUNCTIONALITY NOT GUARANTEED IN THIS AREA DEVICE UNDER RESET IN THIS AREA P FUNCTIONAL AREA SUPPLY VOLTAGE V Notes 1 LVD typical data are based on 25 They are given only as design guidelines and are not tested 2 The minimum Vpp rise time rate is needed to insure a correct device power on LVD reset Not tested in production 134 164 3 ST72311R ST72511R ST72512R ST72532R 12 4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for vice consumption the two current values must be the ST7 functional operating modes over tempera added except for HALT mode for which the clock ture range does not take into account the clock is stopped source current consumption To get the total de Symb Condoms us Supply current variation vs temperature Constant Vpp and
116. er error active BOFF 0 or bus off Bit 4 SRTE Simultaneous Receive Transmit En able Read Set Clear Set by software to enable simultaneous transmis sion and reception of a message passing the ac ceptance filtering Allows to check the integrity of the communication path Reset by software to discard all messages trans mitted by the node Allows remote and data frames to share the same identifier ST72311R ST72511R ST72512R ST72532R Bit NRTX No Retransmission Read Set Clear Set by software to disable the retransmission of un successful messages Cleared by software to enable retransmission of messages until success is met Bit 2 FSYN Fast Synchronization Read Set Clear Set by software to enable a fast resynchronization when leaving standby mode i e wait foronly 11 re cessive bits in a row Cleared by software to enable the standard resyn chronization when leaving standby mode i e wait for 128 sequences of 11 recessive bits Bit 1 WKPS Wake up Pulse Read Set Clear Set by software to generate a dominant pulse when leaving standby mode Cleared by software for no dominant wake up pulse Bit 0 RUN CAN Enable Read Set Clear Set by softwareto leave standby mode after 128 se quences of 11 recessive bits or just 11 recessive bits if FSYN is set Cleared by software to request a switch to the standby or low power mode as soon as any on go ing transfer is complete Rea
117. esistor is based on a resistive transistor This data is based on characterization results not tested in production 5 The reset network protects the device against parasitic resets especially in a noisy environment 6 Data based on design simulation and or technology characteristics not tested in production 7 When the in circuit programming mode is not required by the application Vpp pin must be tied to Vss Notes 7574 147 164 ST72311R ST72511R ST72512R ST72532R 12 10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating condition for Vpp fo Refer to I O port characteristics for more details on sc and T4 unless otherwise specified the input output alternate function characteristics outpu compare input capture external clock PWM 12 10 1 Watchdog Timer Fee Cordons win me Watchdog time out duration ___ E 12 10 2 8 Bit PWM ART Auto Reload Timer CR EE 148 164 3 ST72311R ST72511R ST72512R ST72532R 12 11 COMMUNICATIONS INTERFACE CHARACTERISTICS 12 11 1 SPI Serial Peripheral Interface Refer to I O port characteristics for more details on Subject to general operating condition for fo the input output alternate function characteristics and T4 unless otherwise specified SS SCK MOSI MISO Max Unit
118. est priority and with a pending transmis tored unless the node is not bus off and the sion request is always transmitted When the FSYN bit inthe CSR register is set in which case ETX bitis set once a buffer participates in the ar a single sequence of 11 recessive bits needs to bitration phase it is sent until it wins the arbitra be monitored tion even if another transmission is requested IDLE The CAN controller looks for one of the fol from a buffer with a higher priority lowing events the RUN bit is reset a Start Of RECEPTION Once the CAN controller has syn Frame appears on the CAN bus or the DATA7 chronized itself onto the bus activity itis ready register of the currently active page is written to for reception of new messages Every incoming TRANSMISSION the LOCK bit of a Buffer Message gets Its identifier compared to the ac Control Status Register BCSRx has been set ceptance filters If the bitwise comparison of the and read back as such a transmit job can be selected bits ends up with a match for at least submitted by writing to the DATA7 register The one of the filters then that message is elected for message with the highest priority will be transmit reception and a target buffer is searched for This ted as soon as the CAN bus becomes idle buffer will be the first one order is 1 to 3 that Among those messages with a pending trans has the LOCK and RDY bits of its BCSRx regis mission request the highest
119. et by software to lock a buffer No more message can be received into the buffer thus preserving its content and making it available for transmission Cleared by software to make the buffer available for reception Cancels any pending transmission request Cleared by hardware once a message has been successfully transmitted provided the early trans mit interrupt mode is on Left untouched otherwise Note that in order to prevent any message corrup tion or loss of context LOCK cannot be set nor re set while BUSY is set Trying to do so will result in LOCK not changing state r CONTROLLER AREA NETWORK Cont d FILTER HIGH REGISTERS FHRx Read Write Reset Value Undefined 7 0 FIL11 FIL10 FIL9 FIL8 FIL7 FIL6 FILS FIL4 FIL 11 3 are the most significant 8 bits of a 12 bit message filter The acceptance filter is compared bit by bit with the identifier and the RTR bit of the incoming message If there is a match for the set of bits specified by the acceptance mask then the message is stored in a receive buffer FILTER LOW REGISTERS FLRx Read Write Reset Value Undefined 7 0 pepe e T2 T2 FIL 3 0 are the least significant 4 bits of a 12 bit message filter ST72311R ST72511R ST72512R ST72532R MASK HIGH REGISTERS MHRx Read Write Reset Value Undefined 7 0 iu MM MSK9 MSK8 MSK7 MSK6 MSK5 MSK4 MSK 11 3 are the most significant 8 bits of a 12 bit message mask The acceptance mask d
120. f the prescaler register to be clearedin order to initialize the timer before starting to count Bit 1 OIE Overflow Interrupt Enable This bit is set and cleared by software It allows to enable disable the interrupt which is generated when the OVF bit is set 0 Overflow Interrupt disable 1 Overflow Interrupt enable Bit 0 OVF Overflow Flag This bit is set by hardware and cleared by software reading the CSR register It indicates the transition of the counter from FFh to the ARR value 0 New transition not yet reached 1 Transition reached 58 164 Bit 7 0 CA 7 0 Counter Access Data These bits can be set and cleared either by hard ware or by software The CAR register is used to read or write the auto reload counter on the fly while it is counting AUTO RELOAD REGISTER ARR Read Write Reset Value 0000 0000 00h 7 0 Bit 7 0 AR 7 0 Counter Auto Reload Data These bits are set and cleared by software They are used to hold the auto reload value which is au tomatically loaded in the counter when an overflow occurs At the same time the PWM output levels are changed according to the corresponding OPx bit in the PWMCR register This register has two PWM management func tions Adjusting the PWM frequency Setting the PWM duty cycle resolution PWM Frequency vs Resolution oae 312682 3 PWM AUTO RELOAD TIMER PWM CONTROL REGISTER PWMCR Read Writ
121. func tional blocks refer to Figure 55 ST7 Interface buffering of the ST7 internal bus and address decoding of the CAN registers TX RX Buffers three 10 byte buffers for trans mission and reception of maximum length mes sages ID Filters two 12 bit compare and don t care masks for message acceptance filtering PSR page selection register see memory map BRPR clock divider for different data rates BTR bit timing register ICR interrupt control register ISR interrupt status register CSR general purpose control status register TECR transmit error counter register RECR receive error counter register BTL bit timing logic providing programmable bit sampling and bit clock generation for synchroni zation of the controller BCDL bit coding logic generating a NRZ coded datastream with stuff bits SHREG 8 bit shift register for serialization of data to be transmitted and parallelisation of re ceived data CRC 15 bit CRC calculator and checker EML error detection and management logic CAN Core CAN 2 0B passive protocol control ler 105 164 ST72311R ST72511R ST72512R ST72532R CONTROLLER AREA NETWORK Figure 56 CAN Frames Inter Frame Space Inter Frame Space Data Frame or Overload Frame 44 8 Arbitration Field Control Field Data Field CRC Field 7 16 Inter Frame Space Inter Frame Space Remote Frame
122. g isters Two control registers CR1 amp CR2 A status register SR A baud rate register BRR An extended prescaler receiver register ERPR Anextendedprescalertransmitter register ETPR Refer to the register descriptions in Section 10 6 7for the definitions of each bit Figure 53 Word length programming 9 bit Word length M bit is set Data Frame 10 6 4 1 Serial Data Format Word length may be selected as being either 8 or 9 bits by programming the M bit in the CR1 register see Figure 52 The TDO pin is in low state during the start bit The TDO pin is in high state during the stop bit An Idle character is interpreted as an entire frame of 175 followed by the start bit of the next frame which contains data A Break character is interpreted on receiving Oe for some multiple of the frame period At the end of the last break frame the transmitter inserts an ex tra 1 bit to acknowledge the start bit Transmission and reception are driven by their own baud rate generator Possible Parity Bit i Next Next Data Frame Start Start Start Idle Frame Bit Break Frame SCH 8 bit Word length M bit is reset Data Frame Start Bit Idle Frame Possible Next Data Frame Break Frame Fal i 94 164 3 SERIAL COMMUNICATIONS INTERFACE Cont d 10 6 4 2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit sta
123. h 7 0 Bit 7 TDRE Transmit data register empty This bit is set by hardware when the content of the TDR register has been transferred into the shift register An interrupt is generated if the TIE 1 in the CR2 register It is cleared by a software se quence an access to the SR register followed by a write to the DR register 0 Data is not transferred to the shift register 1 Data is transferred to the shift register Note data will not be transferred to the shift regis ter as long as the TDRE bit is not reset Bit 6 TC Transmission complete This bit is set by hardware when transmission of a frame containing Data a Preamble or a Break is complete An interrupt is generated if TCIE 1 in the CR2 register It is cleared by a software se quence an access to the SR register followed by a write to the DR register 0 Transmission is not complete 1 Transmission is complete Bit 5 RDRF Received data ready flag This bit is set by hardware when the content of the RDR register has been transferred into the DR register An interrupt is generated if RIE 1 in the CR2 register It is cleared by hardware when RE 0 or by a software sequence an access to the SR register followed by a read to the DR register 0 Data is not received 1 Received data is ready to be read Bit 4 IDLE dle line detect This bit is set by hardware when a Idle Line is de tected An interrupt is generated if the ILIE 1 in the CR2 register It i
124. h both data out and data in synchronized with the same clock signal which is provided by the master de vice via the SCK pin Thus the byte transmitted is replaced by the byte received and eliminates the need for separate transmit empty and receiver full bits A status flag is used to indicate that the operation is com plete Four possible data clock timing relationships may be chosen see Figure 49 but master and slave must be programmed with the same timing mode SLAVE MSBit 4 LSBit 7 8 BIT SHIFT REGISTER 79 164 ST72311R ST72511R ST72512R ST72532R SERIAL PERIPHERAL INTERFACE Cont d Figure 47 Serial Peripheral Interface Block Diagram Internal Bus IT request ite E SPI STATE ES T SS Em FX ER FX SERIAL CLOCK GENERATOR 80 164 ky SERIAL PERIPHERAL INTERFACE Cont d 10 5 4 Functional Description Figure 46 shows the serial peripheral interface SPI block diagram This interface contains 3 dedicated registers A Control Register CR A Status Register SR A Data Register DR Refer to the CR SR and DR registers in Section 10 5 7for the bit definitions 10 5 4 1 Master Configuration In a master configuration the serial clock is gener ated on the SCK pin Procedure Select the SPRO amp SPR1 bits to define the se rial clock baud rate see CR register Select the CPOL and CPHA bits to define one
125. hat transition will occur therefore the slave device collision occurs when software attempts to write the DR register after its SS pin has been pulled low For this reason the SS pin must be high between each data byte transfer to allow the CPU to write in the DR register without generating a write colli sion In Master mode Collision in the master device is defined as a write of the DR register while the internal serial clock SCK is in the process of transfer The SS pin signal must be always high on the master device WCOL bit The WCOL bit in the SR register is set if a write collision occurs No SPI interrupt is generated when the WCOL bit is set the WCOL bit is a status flag only Clearing the WCOL bit is done through a software sequence see Figure 50 Figure 50 Clearing the WCOL bit Write Collision Flag Software Sequence Clearing sequence after SPIF z 1 end of a data byte transfer ist Step Read SR 2nd Step Read DR WCOLCO Read SR Write DR SPIF 0 WCOL 0 if no transfer has started WCOL 1 if a transfer has started before the 2nd step Clearing sequence before SPIF 1 during data byte transfer Read SR Read DR 1st Step 2nd Step WCOL 0 Note Writing in DR register in stead of reading in it do not reset WCOL bit 85 164 ST72311R ST72511R ST72512R ST72532R SERIAL PERIPHERAL INTERFACE Cont d 10 5 4 5 Master Mode Fault Master mode f
126. he mes sage The valid range is O to 8 DATA REGISTERS DATAO 7x Read Write Reset Value Undefined 7 0 DATA DATA DATA DATA DATA 7 6 5 4 3 2 1 0 DATA 7 0 is amessage data byte Upto eight such bytes may be part of a message Writing to byte DATA7 initiates a transmit request and should al ways be done even when DATA7 is not part of the message 116 164 Bit 3 ACC Acceptance Code Read Only Set by hardware with the id of the highest priority filter which accepted the message stored in the buffer 0 Match for Filter Mask0 Possible match for Filter Mask1 ACC 1 No match for Filter Mask0 and match for Filter Mask1 Reset by hardware when either RDY or RXIF gets reset Bit 2 RDY Message Ready Read Clear Set by hardware to signal that a new error free message is available LOCK 0 or that a trans mission request is pending LOCK 1 Cleared by software when LOCK 0 to release the buffer and to clear the corresponding RXIF bit in the Interrupt Status Register Cleared by hardware when LOCK 1 to indicate that the transmission request has been serviced or cancelled Bit 1 BUSY Busy Buffer Read Only Set by hardware when the buffer is being filled LOCK 0 or emptied LOCK 1 Reset by hardware when the buffer is not ac cessed by the CAN core for transmission nor re ception purposes Bit 0 LOCK Lock Buffer Read Set Clear S
127. ices Table 28 STMicroelectronics Development Tools Supported Products Development Kit HDS2Emulator Programming Board ST7MDT2 EPB2 EU ST7MDT2 EPB2 US ST7MDT2 EPB2 UK ST72311R6 ST72311R7 ST72311R9 ST72511R6 ST72511R7 ST72511R9 ST7MDT2 DVP2 ST7MDT2 EMU2B ST72512R4 ST72532R4 r 161 164 ST72311R ST72511R ST72512R ST72532R 15 ST7 GENERIC APPLICATION NOTE PROGRAMMING AND TOOLS AN989 Starting with ST7 Hiware C AN1039 ST7 math utility routines AN1064 Writing optimized hiware C language for ST7 EXAMPLE DRIVERS AN969 ST7 SCI communication between the ST7 and a PC AN970 ST7 SPI communication between the ST7 and E PROM 971 ST7 C communication between the ST7 and E PROM TO GET MORE INFORMATION To get the updated information on that product please refer to STMicroelectronics web server http st7 st com 4 162 164 ST72311R ST72511R ST72512R ST72532R 16 SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one Section 8 4 LOW POWER MODES on page 42 and Section 8 5 5 on page 42 added in Section 8 PORTS on page 38 Section 10 2 5 Low Power Modes on page 53and Section 10 2 6 Interrupts on page 53 added in Section 10 2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER MCC RTC on page 52 ESD absolute maximum rating modified in Section 12 2 on page 132 EMC characteristics co
128. ip internal power IppxVpp and is the port power dissipation determined by the user 2 The average chip junction temperature can be obtained from the formula Ty T4 Pp x 155 164 ST72311R ST72511R ST72512R ST72532R 13 3 SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only as design guidelines Figure 95 Recommended Wave Soldering Profile with 37 Sn and 63 Pb COOLING PHASE ege ROOM TEMPERATURE SOLDERING 150 Temp C 100 50 Time sec 220 5 for 25 sec 150 sec above 183 C 90 sec at 125 C Temp C ramp down natural ramp up 2 C sec max 2 C sec for 50sec Time sec 400 Recommended glue for SMD plastic packages dedicated to molding compound with silicone Heraeus PD945 PD955 Loctite 3615 3298 156 164 4 ST72311R ST72511R ST72512R ST72532R 13 4 PACKAGE SOCKET FOOTPRINT PROPOSAL To solder the TQFP64 device directly on the appli YAMAICHI 1C149 064 008 S5 socket soldering cation board or to solder a socket for connecting to plug either the emulator probe or an adaptor the emulator probe the application board should board with an TQFP64 clamshell socket provide the footprint described in Figure 97 This This socket is not compatible with TQFP64 footprint allows both configurations package m Direct TQFP64 soldering Figure 97 64 Device And Emulator Probe Compatible Footprint
129. isconnected from the bus RECEIVE ERROR COUNTER REG RECR Page 00h Read Only Reset Value 00h 0 REC6 5 REC4 REC2 REC1 RECO REC 7 0 isthe Receive Error Counter implement ing part of the fault confinement mechanism of the CAN protocol In case of an error during reception this counter is incremented by 1 or by 8 depending on the error condition as defined by the CAN stand ard After every successful reception the counter is decremented by 1 or reset to 120 if its value was higher than 128 When the counter value exceeds 127 the CAN controller enters the error passive state IDENTIFIER HIGH REGISTERS IDHRx Read Write Reset Value Undefined 7 0 ID 10 3 are the most significant 8 bits ofthe 11 bit message identifier The identifier acts as the mes sage s name used for bus access arbitration and acceptance filtering 115 164 ST72311R ST72511R ST72512R ST72532R CONTROLLER AREA NETWORK Cont d IDENTIFIER LOW REGISTERS IDLRx Read Write Reset Value Undefined BUFFER CONTROL STATUS REGs BCSRx Read Write Reset Value 00h 7 0 7 0 ID 2 0 are the least significant 3 bits of the 11 bit message identifier RTR is the Remote Transmission Request bit It is set to indicate a remote frame and reset to indicate a data frame DLC 3 0 is the Data Length Code It gives the number of bytes in the data field of t
130. ity the sensitivity bits in the MISCR registers must be modified only when the 11 and 10 bits of the CC register are both set to 1 level 3 See I O port register and Miscel laneous register descriptions for more details on the programming Figure 27 External Interrupt Sources vs MISCR SOURCES MISCR2 IPA SOURCES MISCR2 IPB SOURCES ST72311R ST72511R ST72512R ST72532R 9 2 PORT ALTERNATE FUNCTIONS The MISCR registers allow to manage four I O port miscellaneous alternate functions Main clock signal fogc 2 output on PFO m A Beep signal output on PF1 with three selectable audio frequencies m ATLI management on a dedicated A SPI SS pin internal control to use the PC7 I O port function while the SPI is active These functions are described in details in the Section 9 3 MISCELLANEOUS REGISTERS on page 46 0 INTERRUPT SOURCE MISCR1 SENSITIVITY NTROL INTERRUPT SOURCE ei2 INTERRUPT SOURCE MISCR1 1510 IS11 SENSITIVITY CONTROL ei3 INTERRUPT SOURCE 45 164 ST72311R ST72511R ST72512R ST72532R MISCELLANEOUS REGISTERS Cont d 9 3 MISCELLANEOUS REGISTERS MISCELLANEOUS REGISTER 1 MISCR1 Read Write Reset Value 0000 0000 00h 7 0 Ter Bit 7 6 IS1 1 0 ei2 and ei3 sensitivity The interrupt sensitivity defined using the IS1 1 0 bits is applied to the following external interrupts ei2 port B3 0 Externa
131. ity can not be used when the PWM mode is activated Procedure To use pulse width modulation mode 1 Load the OC2R register with the value corre sponding to the period of the signal using the formula in the opposite column 2 Load the OC1R register with the value corre sponding to the period of the pulse if OLVL1 0 and OLVL2 1 using the formula in the oppo site column 3 Select the following in the CR1 register Using the OLVL 1 bit select the level to be ap plied to the OCMP1 pin after a successful comparison with OC1R register Using the OLVL2 bit select the level to be ap plied to the 1 pin after a successful comparison with OC2R register 4 Select the following in the CR2 register Set bit the 1 pin is then dedicat ed to the output compare 1 function Set the PWM bit Select the timer clock CC 1 0 see Table 18 Clock Control Bits If OLVL1 1 and OLVL2 0 the length of the tive pulse is the difference between the OC2R and registers If OLVL1 OLVL2 a continuous signal will be seen on the 1 pin Pulse Width Modulation cycle OCMP 1 OLVL1 OCMP1 OLVL2 Counter is reset to FFFCh ICF1 bit is set 72 164 OCR register value required for a specific tim ing application can be calculated using the follow ing formula t f OCR Value CPU 5 PRESC Where t Signal or pulse period in seconds
132. ive bit If a valid edge is detected in BS1 instead of SYNC SEG BS1 is extended by up to RJW so that the sample point is delayed Conversely if a valid edge is detected in BS2 in stead of SYNC SEG BS2 is shortened by up to RJW so that the transmit point is moved earlier As a safeguard against programming errors the configuration of the Bit Timing Register is only possible while the device is in STANDBY mode NOMINAL BIT TIME BIT SEGMENT 1 BS1 110 164 BIT SEGMENT 2 BS2 SAMPLE POINT TRANSMIT POINT 4 CONTROLLER AREA NETWORK Cont d 10 7 4 Register Description The CAN registers are organized as 6 general pur pose registers plus 5 pages of 16 registers span ning the same address space and primarily used for message and filter storage The page actually selected is defined by the content of the Page Se lection Register Refer to Figure 60 10 7 4 1 General Purpose Registers INTERRUPT STATUS REGISTER ISR Read Write Reset Value 00h 7 0 RXIF2 SCIF ORIF EPND Bit 7 RXIF3 Receive Interrupt Flag for Buffer 3 Read Clear Set by hardware to signal that a new error free mes sage is available in buffer 3 Cleared by software to release buffer 3 Also cleared by resetting bit RDY of BCSR3 Bit 6 RXIF2 Receive Interrupt Flag for Buffer 2 Read Clear Set by hardware to signal that a new error free message is available in buffer 2 Cl
133. iven by the DR register content 40 164 4 PORTS Cont d CAUTION The alternate function must not be ac tivated as long as the pin is configured as input with interrupt in order to avoid generating spurious interrupts Analog alternate function When the pin is used as an ADC input the must be configured as floating input The analog multiplexer controlled by the ADC registers switches the analog voltage present on the select ed pin to the common analog rail which is connect ed to the ADC input It is recommended not to change the voltage level or loading on any port pin while conversion is in progress Furthermore it is recommended not to have clocking pins located close to a selected an alog pin WARNING The analog input voltage level must be within the limits stated in the absolute maxi mum ratings 8 3 PORT IMPLEMENTATION The hardware implementation on each I O port de pends onthe settings in the DDR and OR registers and specific feature of the I O port such as ADC In put or true open drain Switching these ports from one state to anoth er should be done in a sequence that prevents un wanted side effects Recommended safe transi tions are illustrated in Figure 26 Other transitions are potentially risky and should be avoided since they are likely to present unwanted side effects such as spurious interrupt generation Figure 26 Interrupt Port State Transitions
134. keep a wake up time base All other periph erals are not clocked except those which get their clock supply from another clock generator such as external or auxiliary oscillator The safeguard against staying locked in ACTIVE HALT mode is provided by the oscillator interrupt Note As soon as the interrupt capability of one of the oscillators is selected MCCSR OIE bit set entering ACTIVE HALT mode while the Watchdog is active does not generate a RESET This means that the device cannot spend more than a defined delay in this power saving mode 36 164 Figure 21 ACTIVE HALT Timing Overview ACTIVE d E 4096 CPU CYCLE HALT DELAY icd HALT INSTRUCTION MCCSR OIE 1 INTERRUPT VECTOR Figure 22 ACTIVE HALT Mode Flow chart OSCILLATOR ON HALT INSTRUCTIONS PERIPHERALS OFF MCCSR OIE 1 OSCILLATOR ON PERIPHERALS OFF CPU ON 1 0 BITS xx 9 4096 CPU CLOCK CYCLE DELAY OSCILLATOR ON PERIPHERALS ON CPU ON I 1 0 BITS XX 3 FETCH RESET VECTOR OR SERVICE INTERRUPT Notes 1 Peripheral clocked with an external clock source can still be active 2 Only the MCC RTC interrupt and some specific interrupts can exit the MCU from ACTIVE HALT mode such as external interrupt Refer to Table 7 Interrupt Mapping on page 32 for more details 3 Before servicing an interrupt the CC register is pushed on the stack The I 1 0 bits of the CC reg ister are set to the current software priority
135. l Interrupt Sensitivity MISCR2 IPB 0 MISCR2 IPB 1 Falling edge amp Rising edge low level amp high level Rising edge only Falling edge only Falling edge only Rising edge only Rising and falling edge ei3 port B7 4 1811 1510 External Interrupt Sensitivity Falling edge amp low level Lo C Rising ede ony aSo These 2 bits be written only when 11 and 10 of the CC register are both set 1 level 3 Bit 5 MCO Main clock out selection This bit enables the MCO alternate function on the PFO I O port It is set and cleared by software 0 MCO alternate function disabled pin free for general purpose 1 alternate function enabled fog 2on I O port Note To reduce power consumption the MCO function is not active in ACTIVE HALT mode 46 164 Bit 4 3 IS2 1 0 ei0 and eit sensitivity The interrupt sensitivity defined using the IS2 1 0 bits is applied to the following external interrupts 0 port A3 0 External Interrupt Sensitivity MISCR2 IPA 0 0 MISCR2 IPA 1 1 ELLA edge amp EIN edge low level amp high level 0 1 Rising edge only Falling edge only 1 0 Falling edge only Rising edge only Rising and falling edge 1 port F2 0 sei 20 Send interrupt Sensttiviy oo Rising edge ony
136. l messages received and completes normally before the Bit Time Log after the wake up bit and before the controller is mum power consumption This state is signalled are ignored by the RUN bit being read back as 0 Once in standby the only event monitored is the WAKE UP The CAN bus line is forced to domi reception of a dominant bit which causes a wake nant for one bit time signalling the wake up con up interrupt ifthe SCIE bit of the Interrupt Control dition to all other bus members Figure 57 CAN Controller State Diagram ARESET RUN amp WKPS STANDBY RUN amp WKPS FSYN amp BOFF amp 11 Recessive bits FSYN BOFF amp 128 11 Recessive bits Write to DATA7 TX Error amp NRTX TX OK RX OK menson Arbitration lost TX Error ERROR 107 164 ST72311R ST72511R ST72512R ST72532R CONTROLLER AREA NETWORK Cont d RESYNC The resynchronization mode is used Note 1 Setting the SRTE bit of the CSR register to find the correct entry point for starting trans allows transmitted messages to be simultane mission or reception after the node has gone ously received when they pass the acceptance asynchronous either by going into the STANDBY filtering This is particularly useful for checking or bus off states the integrity of the communication path Resynchronization is achieved when 128 se Note 2 When the ETX bit is reset the buffer with quences of 11 recessive bits have been moni the high
137. l protection between the pad and Vss 5a 4 5b is implemented to completly absorb the posi tive ESD discharge Multisupply Configuration When several types of ground Vss Vas and power supply are available for any reason better noise immunity the structure shown in Figure 81 is implemented to protect the device against ESD Figure 79 Positive Stress on a True Open Drain Pad vs Main path il Path to avoid BENE 144 164 3 ST72311R ST72511R ST72512R ST72532R 12 8 PORT PIN CHARACTERISTICS 12 8 1 General Characteristics Subject to general operating condition for Vpp fosc and T4 unless otherwise specified O mites niae E Ed X inputteakage curent State current consumption 7 Foto input mode 200 _ E 1 E REESE Sa TTT Tou Output high to Tow eve aime 7 0 NU Output low to high level rise time Between 10 and 90 Bema mert peime ST72XXX UNUSED I O PORT UNUSED I O PORT ST72XXX Notes 1 Unless otherwise specified typical data are based 25 and Vpp 5V 2 Data based on characterization results not tested in production 3 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested 4 Configuration not recommended all unused pins must be at
138. level of the interrupt routine and restored when the CC register is popped r POWER SAVING MODES Cont d 7 4 2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU It is entered by executing the HALT instruction when the OIE bit of the Main Clock Controller Status register MCCSR is cleared see Section 10 2 on page 52 for more de tails on the MCCSR register The MCU can exit HALT mode on reception of ei ther a specific interrupt see Table 7 Interrupt Mapping on page 32 or a RESET When exiting HALT mode by means of a RESET or an interrupt the oscillator is immediately turned on and the 4096 CPU cycle delay is used to stabilize the os cillator After the start up delay the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up see Figure 24 When entering HALT mode the I bit in the CC reg ister is forced to 0 to enable interrupts Therefore if an interrupt is pending the MCU wakes immedi ately In HALT mode the main oscillator is turned off causing all internal processing to be stopped in cluding the operation of the on chip peripherals All peripherals are not clocked except the ones which get their clock supply from another clock generator such as an external or auxiliary oscilla tor The compatibility of Watchdog operation with HALT mode is configured by the WDGHALT op tion bit of the option byte The HALT instruction
139. low of the counter will generate an interrupt which wakes up the MCU Figure 34 External Event Detector Example 3 counts fext fcoUNTER P ae ARR FDh 1 LI COUNTER INTERRUPT IF 1 CSR READ CSR READ INTERRUPT IF OIE 1 57 164 ST72311R ST72511R ST72512R ST72532R PWM AUTO RELOAD TIMER Cont d 10 3 3 Register Description CONTROL STATUS REGISTER CSR Read Write Reset Value 0000 0000 00h COUNTER ACCESS REGISTER CAR Read Write Reset Value 0000 0000 00h 7 0 7 0 Bit 7 EXCL External Clock This bitis set and cleared by software It selects the input clock for the 7 bit prescaler 0 CPU clock 1 External clock Bit 6 4 CC 2 0 Counter Clock Control These bits are set and cleared by software They determine the prescaler division ratio from Where 0 0 fiNPUT 8 MHz fiNPUT 2 4 MHz 4 2 MHz 1 2 500 2 250 2 125 2 62 5 2 8 16 finput 32 finput 64 finput 128 000 Bit 3 TCE Timer Counter Enable This bit is set and cleared by software It puts the timer in the lowest power consumption mode 0 Counter stopped prescaler and counter frozen 1 Counter running Bit 2 FCRL Force Counter Re Load This bit is write only and any attempt to read it will yield a logical zero When set it causesthe contents of ARR register to be loaded into the counter and the content o
140. m omm epp pe ors oso nas loss ee Number of Pins 64 4 16 SK Plastic socket overall dimensions Table 27 Suggested List of TQFP64 Socket Types Package Probe Adaptor Socket Reference Socket type ENPLAS 0706108102 TQFP64 s E 51 0644 1240 5 14584 Clamshell EMU PROBE YAMAICHI IC 149 064 008 S5 r 157 164 ST72311R ST72511R ST72512R ST72532R 14 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro grammable versions OTP as well as in factory coded versions ROM OTP devices are shipped to customers with a default content FFh while ROM factory coded parts contain the code sup plied by the customer This implies that OTP de vices have to be configured by the customer using the Option Bytes while the ROM devices are facto ry configured 14 1 OPTION BYTES The option byte allows the hardware configuration of the microcontroller to be selected The option byte has no address in the memory map and can be accessed only in programming mode for example using a standard ST7 program ming tool The default content of the OTP is fixed to FFh This means that all the options have 1 as their default value In masked ROM devices the option bytes are fixed in hardware by the ROM code see opti
141. mes slower thanthe CPU clock speed with the choice of active edge m Output compare functions with 2 dedicated 16 bit registers 2 dedicated programmable signals 2 dedicated status flags 1 dedicated maskable interrupt m Input capture functions with 2 dedicated 16 bit registers 2 dedicated active edge selection signals 2 dedicated status flags 1 dedicated maskable interrupt m Pulse width modulation mode PWM m One pulse mode m 5 alternate functions on ports ICAP1 ICAP2 1 2 EXTCLK The Block Diagram is shown in Figure 35 Note Some timer pins may not available not bonded in some ST7 devices Refer to the device pin out description When reading an input signal on a non bonded pin the value will always be 1 r ST72311R ST72511R ST72512R ST72532R 10 4 3 Functional Description 10 4 3 1 Counter The main block of the Programmable Timer is a 16 bit free running upcounter and its associated 16 bit registers The 16 bit registers are made up of two 8 bit registers called high amp low Counter Register CR Counter High Register CHR is the most sig nificant byte MS Byte Counter Low Register CLR is the least sig nificant byte LS Byte Alternate Counter Register ACR Alternate Counter High Register ACHR is the most significant byte MS Byte Alternate Counter Low Register ACLR is the least significant byte LS Byte
142. ming error is detected the FE bit is set by hardware Data is transferred from the Shift register to the DR register No interrupt is generated However this bit rises at the same time as the RDRF bit which itself generates an interrupt The FE bit is reset by a SR register read operation followed by a DR register read operation 4 ST72311R ST72511R ST72512R ST72532R SERIAL COMMUNICATIONS INTERFACE Cont d Figure 54 SCI Baud Rate and Extended Prescaler Block Diagram TRANSMITTER 5 2 5 5 1 5 RECEIVER 97 164 ST72311R ST72511R ST72512R ST72532R SERIAL COMMUNICATIONS INTERFACE Cont d 10 6 4 4 Conventional Baud Rate Generation The baud rate for the receiver and transmitter Rx and Tx are set independently and calculated as follows fopu Rx 82 PR TR 32 with PR 1 3 4 13 see SCPO amp 5 1 bits TR 1 2 4 8 16 32 64 128 see SCTO SCT1 amp 5 2 bits RR 1 2 4 8 16 32 64 128 see SCRO SCR1 amp SCR2 bits All this bits are in the BRR register Example If is 8 MHz normal mode and if PR 13 and TR RR 1 the transmit and receive baud rates are 19200 baud Note the baud rate registers MUST NOT be changed while the transmitter or the receiver is en abled 10 6 4 5 Extended Baud Rate Generation The extended prescaler option gives a very fine tuning on
143. n is on going the data output line of the SPI MOSI in master mode MISO in slave mode has its alternate function capability released In this case the pin status depends of the I O port configuration 3 150 164 ST72311R ST72511R ST72512R ST72532R COMMUNICATIONS INTERFACE CHARACTERISTICS Cont d 12 11 2 SCI Serial Communications Interface Refer to I O port characteristics for more details on Subject to general operating condition for Vpp fo the input output alternate function characteristics sc and T unless otherwise specified RDI and Conditions Symbol Parameter Standard inn EN I M Prescaler Rate vs Standard Conventional Mode TR or RR 64 PR 13 TR or RR 16 PR 13 di or RR 8 PR 13 R or RR 0 16 or RR 2 PR 13 Communication frequency 8MHz TR or RR 8 PR 3 fex TR or RR 1 PR 13 19200 19230 77 E ETPR or ERPR 14400 14285 71 12 11 3 CAN Controller Area Network Interface Subject to general operating condition for Vpp fo the input output alternate function characteristics sc and T4 unless otherwise specified CANTX and CANRX Refer to I O port characteristics for more details on Fee Sees met r 151 164 ST72311R ST72511R ST72512R ST72532R 12 12 8 BIT ADC CHARACTERISTICS Subject to general operating condition for Vpp fosc and T4 unless otherwise specified Symbol Parame
144. nal clock pin EXTCLK will trigger the counter register 0 A falling edge triggers the counter register 1 A rising edge triggers the counter register 75 164 ST72311R ST72511R ST72512R ST72532R 16 BIT TIMER Cont d STATUS REGISTER SR Read Only Reset Value 0000 0000 00h The three least significant bits are not used 7 0 Pepe Te eT Bit 7 ICF1 Input Capture Flag 1 0 No input capture reset value 1 An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode To clear this bit first read the SR register then read or write the low byte of the IC1R IC1LR register Bit 6 OCF1 Output Compare Flag 1 match reset value 1 The content of the free running counter has matched the content of the register clear this bit first read the SR register then read or write the low byte of the OC1R OC1LR reg ister Bit 5 TOF Timer Overflow Flag 0 No timer overflow reset value 1 The free running counter rolled over from FFFFh to 0000h To clear this bit first read the SR reg ister then read or write the low byte of the CR CLR register Note Reading or writing the ACLR register does not clear TOF Bit 4 ICF2 Input Capture Flag 2 0 No input capture reset value 1 An input capture has occurred on the ICAP2 pin To clear this bit first read the SR register then read or write the low byte of the IC2R IC2LR regi
145. nce of the analog voltage is lower than the specified limits Pure digital pins must have a negative injection less than 1 6mA In addition it is recommended to inject the current as far as possible from the analog input pins 5 When several inputs are submitted to a current injection the maximum li is the absolute sum of the positive and negative injected currents instantaneous values These results are based on characterisation with Xy maxi mum current injection on four port pins of the device 6 True open drain I O port pins do not accept positive injection 132 164 STA ST72311R ST72511R ST72512R ST72532R 12 3 OPERATING CONDITIONS 12 3 1 General Operating Conditions Vpp Supply voltage see Figure 66 and Figure 67 Vpp23 5V without EEPROM 07 16 Vpp24 5V with EEPROM MHz 1 Suffix Version 70 6 Suffix Version 40 85 6 Suffix Version 4 85 0 7 Suffix Version 3 Suffix Version FUNCTIONALITY GUARANTEE D IN THIS AREA FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR SUPPLY VOLTAGE V FUNCTIONALITY NOT GUARANTEED IN THIS AREA FOR TEMPERATURE HIGHER THAN 85 C FUNCTIONALITY GUARANTEE D IN THIS AREA FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR 1 SUPPLY VOLTAGE V Notes 1 Guaranteed by construction A D operation is not guaranteed b
146. nded exposure to room level fluorescent lighting may also cause erasure An opaque coating paint tape label etc should be placed over the package window if the product is to be operated under these lighting con ditions Covering the window also reduces lpp in power saving modes due to photo diode leakage currents 15 164 ST72311R ST72511R ST72512R ST72532R 3 DATA EEPROM 3 1 INTRODUCTION 3 2 MAIN FEATURES The Electrically Erasable Programmable Read Only Memory can be used as a non volatile back up for storing data Using the EEPROM requires a basic access protocol described in this chapter Up to 16 Bytes programmed in the same cycle EEPROM mono voltage charge pump Chained erase and programming cycles Internal control of the global programming cycle duration End of programming cycle interrupt flag m WAIT mode management Figure 4 EEPROM Block Diagram FALLING EEPROM INTERRUPT EDGE DETECTOR X HIGH VOLTAGE PUMP RESERVED EEPROM m eoo e EEPROM MEMORY MATRIX 1 ROW 16 x 8 BITS ADDRESS ROW DECODER DECODER DATA 16x 8 BITS MULTIPLEXER DATA LATCHES ADDRESS BUS 3 16 164 DATA EEPROM Cont d 3 3 MEMORY ACCESS The Data EEPROM memory read write access modes are controlled by the LAT bit of the EEP ROM Control Status register EECSR The flow chart in Figure 5 describes these different memory access modes Read Operation LATzO The EEPROM can be read
147. ng Mode Example however it uses more bytes and more CPU cy cles Short addressing mode is less powerful because it can generally only access page zero 0000h s OOFFh range but the instruction size is more compact and faster All memory to memory in A 55 X structions use short addressing modes only CLR CPL NEG BSET BRES p The ST7 Assembler optimizes the use of long and short addressing modes The ST7 Instruction set is designed to minimize the number of bytes required per instruction To do Table 25 ST7 Addressing Mode Overview Bytes Inherent _ EE Ee 9 eem e foa ECG oes mee wam Se ome um wer ie Sm erm p How 2 exse oore IJ ow meee wr we _ m foe eme er m ____ mr m wer wr e 125 164 ST72311R ST72511R ST72512R ST72532R INSTRUCTION SET OVERVIEW 11 1 1 Inherent All Inherent instructions consist of a single byte The opcode fully specifies all the required informa tion for the CPU to process the operation TRAP S W Interrupt Wait For Interrupt Low Pow er Mode HALT Halt Oscillator Lowest Power Mode NO WF Siv scr
148. no transmission is taking place a write in struction to the DR register places the data directly in the shift register the data transmission starts and the TDRE bit is immediately set ST72311R ST72511R ST72512R ST72532R When frame transmission is complete after the stop bit or after the break frame the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register Clearing the TC bit is performed by the following software sequence 1 An access to the SR register 2 A write to the DR register Note The TDRE and bits are cleared by the same software sequence Break Characters Setting the SBK bit loads the shift register with a break character The break frame length depends on the M bit see Figure 53 As long as the SBK bit is set the SCI send break frames to the TDO pin After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame Idle Characters Setting the TE bit drives the SCI to send an idle frame before the first data frame Clearing and then setting the TE bit during a trans mission sends an idle frame after the current word Note Resetting and setting the TE bit causes the data in the TDR register to be lost Therefore the best time to toggle the TE bit is when the TDRE bit is set i e before writing the next byte in the DR 95 164 ST7
149. o the CPU Each pin can independently generate an interrupt request The interrupt sensitivity is independently 38 164 programmable using the sensitivity bits in the Mis cellaneous register Each external interrupt vector is linked to a dedi cated group of I O port pins see pinout description and interrupt section If several input pins are se lected simultaneously as interrupt source these are logically ANDed For this reason if one of the interrupt pins is tied low it masks the other ones In case of a floating input with interrupt configura tion special care must be taken when changing the configuration see Figure 26 The external interrupts are hardware interrupts which means that the request latch not accessible directly by the application is automatically cleared when the corresponding interrupt vector is fetched To clear an unwanted pending interrupt by software the sensitivity bits in the Miscellane ous register must be modified 8 2 2 Output Modes The output configuration is selected by setting the corresponding DDR register bit In this case writ ing the DR register applies this digital value to the I O pin through the latch Then reading the DR reg ister returns the previously stored value Two different output modes can be selected by software through the OR register Output push pull and open drain DR register value and output pin status __ _ Open drain vs
150. on ew x x Pot so xps x xf ez x x mns X x Pot es PWHEART extemal Cio SS x Pot 0 X X X Pot be _ X X X Pot ps ADCAnabginput3 Pot Dt mou x x x Potps ADC Analog ius x x x Potoe ADC Analog iue Pono ADC Analog input L aaoo Power Suppy Voas LL I T LL Distal Supply ERC T o m m e P PE6 PE7 HS PBO PWM3 PB1 PWM2 PB2 PWM1 PB3 PWMO PBA ARTCLK T 2 o EE derr E PB7 PDO AINO PD1 AIN1 PD2 AIN2 PD3 AIN3 PD4 AIN4 PD5 AIN5 PD6 AIN6 PD7 AIN7 Vssa Vpp 3 E 3 4 EE EE 8 Bur 5 Ea ES RES Ul U 00 UJ 4 8 164 9 8 9 Em OO Co NJ ot ol A PO OQ ot BY Po l OO oy 55 3 PF6 HSJICAP1 A PC
151. on list USER OPTION BYTE USER OPTION BYTE Bit 7 6 4 Reserved must always be 1 Bit 5 Reserved must always be 0 Bit 3 FMP Full memory protection This option bit allows the protection of the software contents against piracy program or data When the protection is activated read out of the EPROM or data EEPROM contents is prevented by hard ware 0 Read out protection enabled 1 Read out protection disabled Bit 2 Reserved must always be 1 158 164 Bit 1 WDG HALT Watchdog and HALT mode This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active 0 No Reset generation when entering Halt mode 1 Reset generation when entering Halt mode Bit 0 WDG SW Hardware or software watchdog This option bit selects the watchdog type 0 Hardware watchdog always enabled 1 Software watchdog to be enabled by software 3 ST72311R ST72511R ST72512R ST72532R 14 2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE Customer code is made up of the ROM contents and the list of the selected options if any The ROM contents are to be sent on diskette or by electronic means with the S19 hexadecimal file generated by the development tool All unused bytes must be set to FFh The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended The STMicroelectronics Sales Organization will be pleased to provide
152. ontain the interrupt software priority of each interrupt vector Eachinterrupt vector except RESET and TRAP has corresponding bits in these registers where its own software priority is stored This corre spondance is shown in the following table FFFBh FFFAh I1 O and IO 0 bits FFF9h FF F8h I1 1 10 1 bits FFE1h FFEOh I1 13 and 10 13 bits Each I1_x and 10 x bit value in the ISPRx regis ters has the same meaning as the 1 and 10 bits in the CC register Level 0 can not be written 11 x21 10 x20 In this case the previously stored value is kept ex ample previous CFh write 64h result 44h The RESET TRAP and TLI vectors have no soft ware priorities When one is serviced the and 10 bits of the CC register are both set Note Bits in the ISPRx registers which corre spond to the TLI can be read and written but they are not significant in the interrupt process man agement Caution If the 1 x and IO x bits are modified while the interrupt x is executed the following be haviour has to be considered If the interrupt x is still pending new interrupt or flag not cleared and the new software priority is higher than the previ ous one the interrupt x is re entered Otherwise the software priority stays unchanged up to the next interrupt request after the IRET of the inter rupt x 31 164 ST72311R ST72511R ST72512R ST72532R INTERRUPTS Cont d Table 6 Dedicated Inter
153. ory data will not be guar anteed READ OPERATION POSSIBLE lt lt lt INTERNAL PROGRAMMING VOLTAGE ERASE CYCLE 1 WRITEOF 1DATA LATCHES 18 164 WRITE CYCLE IN EEPROM INTERRUPT r DATA EEPROM Cont d 3 6 REGISTER DESCRIPTION CONTROL STATUS REGISTER CSR Read Write Reset Value 0000 0000 00h 7 0 Bit 7 3 Reserved forced by hardware to 0 Bit 2 IE nterrupt enable This bitis set and cleared by software Itenables the Data EEPROM interrupt capability when the PGM bit is cleared by hardware The interrupt request is automatically cleared when the software enters the interrupt routine 0 Interrupt disabled 1 Interrupt enabled ST72311R ST72511R ST72512R ST72532R Bit 1 LAT Latch Access Transfer This bit is set by software It is cleared by hard ware at the end of the programming cycle It can only be cleared by software if PGM bit is cleared 0 Read mode 1 Write mode Bit 0 PGM Programming control and status This bit is set by software to begin the programming cycle At the end of the programming cycle this bit is cleared by hardware and an interrupt is generated if the ITE bitis set 0 Programming finished or not yet started 1 Programming cycle is in progress Note if the PGM bit is cleared during the program ming cycle the memory data is not guaranteed Table 3 DATA EEPROM Register Map and Reset Values Address Register Hex Label EECSR
154. ough to se lect the I O pin configuration The OR register allows to distinguish in input mode if the pull up with interrupt capability or the basic pull up configuration is selected in output mode if the push pull or open drain configuration is selected Each bit is set and cleared by software Input mode 0 floating input 1 pull up input with or without interrupt Output mode 0 output open drain with P Buffer unactivated 1 output push pull 43 164 ST72311R ST72511R ST72512R ST72532R PORTS Cont d Table 12 I O Port Register Map and Reset Values ale LE CEET Hex Label 6 of IO port registers Ws 0006h PCOR 0008h PBDR Lo Lo 0011h 0015h PFDDR 3 44 164 9 MISCELLANEOUS REGISTERS The miscellaneous registers allow control over several features such as the external interrupts or the l Oalternate functions 9 1 I O PORT INTERRUPT SENSITIVITY The external interrupt sensitivity is controlled by the IPA IPB and ISxx bits of the Miscellaneous registers Figure 27 This control allows to have up to 4 fully independent external interrupt source sensitivities Each external interrupt source can be generated on four or five different events on the pin m Falling edge m Rising edge m Falling and rising edge m Falling edge and low level m Rising edge and high level only for ei0 and ei2 To guarantee correct functional
155. pen Drain logic level True Open Drain Legend NI not implemented Note The diode to Vpp is not implemented in the Off implemented not activated true open drain pads A local protection between On implemented and activated the pad and is implemented to protect the de vice against positive stress 39 164 ST72311R ST72511R ST72512R ST72532R PORTS Cont d Table 10 Port Configurations Hardware Configuration NOT IMPLEMENTED IN 7 DR REGISTER ACCESS TRUE OPEN DRAIN _ VOPORTS PULL UP DR REGISTER DATA BUS R ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE eix INTERRUPT POLARITY CONDITION SELECTION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN DR REGISTER ACCESS PORTS 2 DR REGISTER DATABUS ALTERNATE ALTERNATE ENABLE OUTPUT a a 5 lt oc a 2 D IMPLEMENTED IN TRUE OPEN DRAIN DR REGISTER ACCESS VOPORTS DR REGISTER DATABUS PUSH PULL OUTPUT 2 ALTERNATE ALTERNATE ENABLE OUTPUT Notes 1 When the port is in input configuration and the associated alternate function is enabled as an output reading the DR register will read the alternate function output status 2 When the I O port is in output configuration and the associated alternate function is enabled as an input the alternate function reads the pin status g
156. quence see Figure 50 0 No write collision occurred 1 A write collision has been detected Bit 5 Unused Bit 4 MODF Mode Fault flag m This bit is set by hardware when the SS pin is pulled low in master mode see Section 10 5 4 5 Master Mode Fault on page 85 An SPI interrupt be generated if SPIE 1 in the CR register This bit is cleared by a software sequence An ac cess to the SR register while MODF 1 followed by a write to the CR register 0 No master mode fault detected 1 A fault in master mode has been detected Bits 3 0 Unused 90 164 DATA I O REGISTER DR Read Write Reset Value Undefined 7 0 o os oo oe The DR register is used to transmit and receive data on the serial bus In the master device only a write to this register will initiate transmission re ception of another byte Notes During the last clock cycle the SPIF bit is set a copy of the received data byte in the shift register is moved to a buffer When the user reads the serial peripheral data I O register the buffer is actually being read Warning A write to the DR register places data directly into the shift register for transmission A write to the the DR register returns the value lo cated in the buffer and not the contents of the shift register See Figure 47 4 ST72311R ST72511R ST72512R ST72532R SERIAL PERIPHERAL INTERFACE Table 21 SPI Register Map
157. r RTC 52 10 2 4 Register Description uso Reno see Roe anu e obe ees 53 10 2 5 Low Power Modes 53 10 2 6 Interr pts s xs ex EE E ERREUR ERE eee 53 10 3 PWM AUTO RELOAD TIMER ART 54 10 3 1 Introduction RR REOR X Re XU dee 54 10 3 2 Furictiorial Description RR RE ceed BRS RE ERR 55 10 3 3 Register Description 58 10 4 1G BI eur 61 10 4 1 61 10 4 2 Main Features cc eme nent Ro wha Xe ok RS be ce RR en 61 10 4 3 Functional Description 61 10 4 4 Low Power Modes 73 10 4 5 Interr ptS iu des RR CER oem Ron E eg CR ahs 73 10 4 6 Summary of Timer modes 73 10 4 7 Register Description 74 10 5 SERIAL PERIPHERAL INTERFACE SPI 79 10 5 1 IntrOduCtlOFi es ache eR APR RR BR RR 79 10 5 2 Main cscs s Pie e ee ee eS 79 10 5 3 General
158. r handshake lines or data bytes with com mand fields Multi master System A multi master system may also be configured by the user Transfer of master control could be im plemented using a handshake method through the ports or by an exchange of code messages through the serial peripheral interface system The multi master system is principally handled by the MSTR bit in the CR register and the MODF bit in the SR register 87 164 ST72311R ST72511R ST72512R ST72532R SERIAL PERIPHERAL INTERFACE 10 5 5 Low Power Modes Description WAIT No effect on SPI SPI interrupt events cause the device to exit from WAIT mode SPI registers are frozen HALT In HALT mode the is inactive SPI operation resumes when the MCU is woken up by an interrupt with exit from HALT mode capability 10 5 6 Interrupts Enable Interrupt Event Control Bit SPI End of Transfer Event SPIF SPIE Master Mode Fault Event MODF Note The SPI interrupt events are connected to the same interrupt vector see Interrupts chapter They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset RIM instruction 4 88 164 SERIAL PERIPHERAL INTERFACE 10 5 7 Register Description CONTROL REGISTER CR Read Write Reset Value 0000xxxx Oxh 7 0 Bit 7 SPIE Serial peripheral interrupt enable This bit is set and cleared by software
159. r oscillators The associated hardware configuration are shown 5 7 in Table 4 Refer to the electrical characteristics 0501 OSC2 section for more details External Clock Source In this external clock mode a clock signal square EXTERNAL sinus or triangle with 50 duty cycle has to drive SOURCE the OSC1 pin while the OSC2 pin is tied to ground ST7 OSC1 OSC2 L Crystal Ceramic Oscillator This oscillator based on constant current source LOAD CAPACITORS External Clock is optimized in terms of consumption and has the advantage of producing a very accurate rate on the main clock of the ST7 When using this oscillator the resonator and the load capacitances have to be connected as shown in Table 4 and have to be mounted as close as possible to the oscillator pins in order to minimize output distortion and start up stabilization time This oscillator is not stopped during the RESET phase to avoid losing time in the oscillator start up phase These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start up phase 7 g G o o wn 27 164 ST72311R ST72511R ST72512R ST72532R 6 INTERRUPTS 6 1 INTRODUCTION The ST7 enhanced interrupt management pro vides the following features m Hardware interrupts m Software interrupt TRAP m Nested or concurrent interrupt management with flexi
160. re members of the ST7 mi crocontroller family They can be grouped as fol lows ST725xxR devices are designed for mid range applications with a CAN bus interface Controller Area Network ST72311R devices target the same range of ap plications but without CAN interface All devices are based on a common industry standard 8 bit core featuring an enhanced instruc tion set Figure 1 Device Block Diagram 8 BIT CORE ALU CONTROL PORT E 6 164 Under software control all devices can be placed in WAIT SLOW ACTIVE HALT or HALT mode reducing power consumption when the application is in idle or standby state The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers enabling the design of highly efficient and compact application code In addition to standard 8 bit data management all ST7 micro controllers feature true bit manipulation 8x8 un signed multiplication and indirect addressing modes PROGRAM MEMORY 16K 60K Bytes EEPROM 256 Bytes 3 ST72311R ST72511R ST72512R ST72532R 1 2 PIN DESCRIPTION Figure 2 64 Pin TQFP Package Pinout CANRX CANTX PE1 RDI PEO o ez Vss 1 Vpp 1 2 1 PAO 7 55 PC6 SCK PC5 MOSI 4 MISO HS 1 2 HS ICAP2 B PC1 OCMP1 B PCO OCMP2 B Vss 0 Vpp 0 HS PE
161. reted as a master or slave timing diagram where the SCK pin the MISO pin the MOSI pin are directly connected between the master and the slave device The SS pin is the slave device select input and can be driven by the master device Figure 48 CPHA SS Timing Diagram MOSI MISO Master SS Slave SS CPHA 0 ST72311R ST72511R ST72512R ST72532R The master device applies data to its MOSI pin clock edge before the capture clock edge CPHA bit is set The second edge on the SCK pin falling edge if the CPOL bit is reset rising edge if the CPOL bit is set is the MSBit capture strobe Data is latched on the occurrence of the second clock transition No write collision should occur even if the SS pin stays low during a transfer of several bytes see Figure 48 CPHA bit is reset The firstedge on the SCK pin falling edge if CPOL bit is set rising edge if CPOL bit is reset is the MSBit capture strobe Data is latched on the oc currence of the first clock transition The SS pin must be toggled high and low between each byte transmitted see Figure 48 To protect the transmission from a write collision a low value on the SS pin of a slave device freezes the data in its DR register and does not allow it to be altered Therefore the SS pin must be high to write a new data byte in the DR without producing a write collision Slave SS CPHA 1 VR02131A 83 164 ST72311R ST72511R S
162. rrected in Section 12 7 on page 140 163 164 ST72311R ST72511R ST72512R ST72532R Notes Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of useof such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied S TMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics All Rights Reserved Purchase of PC Components by STMicroelectronics conveys a license under the Philips Patent Rights to use these components in system is granted provided that the system conforms to the Standard Specification as defined by Philips STMicroelectronics Group of Companies Australia Brazil China Finland France Germany Hong Kong India Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom U S A http www st com 4 164 164
163. rupt Instruction Set nstruction we Description FunctionExampie Rer memptowme um eoe Td Pop from the Stack Mem gt CC Sv Disabie 75 wer 01 Note During the execution of an interrupt routine the HALT POPCC RIM SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions In order not to lose the current software priority level the RIM SIM HALT WFI and POP CC instructions should never be used in an interrupt routine Table 7 Interrupt Mapping Source VR Register Priority i Address nmm ss __ e ow CAN Peripheral Interrupts CANISR FFEEh FFE Fh ER A TIMER A Peripheral TASR 9 TIMER B TIMER Peripheral erupts TBSR Pet 3 32 164 ST72311R ST72511R ST72512R ST72532R INTERRUPTS Cont d Table 8 Nested Interrupts Register Map and Reset Values Address Register Hex Label 0024h ISPRO Reset Value 0025h ISPR1 Reset Value 0026h Reset Value PWMART NotUsed Used 0027h 11 4 0 i 11 27 0 Reset Value r 33 16
164. s 2 The ljo current sourced must always respect the absolute maximum rating specified in Section 12 2 2 and the sum of I O ports and control pins must not exceed lypp True open drain pins does not have 146 164 7 71 ST72311R ST72511R ST72512R ST72532R 12 9 CONTROL PIN CHARACTERISTICS 12 9 1 Asynchronous RESET Pin Subject to general operating condition for Vpp fosc and T4 unless otherwise specified Em eR De mites tae ___ Vins Seit ger Tyres T wepia saam esr Wares Leen sl Generated reset puse duran Watchdog reset source 1 f e serus Exeralresetpusehogtme Figure 86 Typical Application with RESET 5 ST72XXX INTERNAL RESET CONTROL EXTERNAL RESET CIRCUIT WATCHDOG RESET LVD RESET 12 9 2 Vpp Pin Subject to general operating condition for Vpp fosc and T4 unless otherwise specified Symbol S LIST vu input ow evel voltage Vi Input high level voltage 6 1 Unless otherwise specified typical data are based on 25 and Vpp 5V Figure 87 Two typical Applications with Vpp Pin 7 Vpp ST72XXX 2 Data based on characterization results not tested in production 3 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested 4 The Roy pull up equivalent r
165. s a static reset when the Vpp supply voltage is below a Vir reference value This means that it secures the power up as well as the power down keeping the ST7 in reset The Vir reference value for a voltage drop is lower than the Vir reference value for power on in order to avoid a parasitic reset when the MCU starts run ning and sinks current on the supply hysteresis The LVD Reset circuitry generates a reset when Vpp is below Vit when is rising when is falling The LVD function is illustrated in Figure 10 Provided the minimum Vpp value guaranteed for the oscillator frequency is below Vr the MCU can only be in two modes Figure 10 Low Voltage Detector vs Reset under full software control in static safe reset In these conditions secure operation is always en sured for the application without the need for ex ternal reset hardware During a Low Voltage Detector Reset the RESET pin is held low thus permitting the MCU to reset other devices Notes The LVD allows the device to be used without any external RESET circuitry The LVD is an optional function which can be se lected when ordering the device ordering informa tion 24 164 4 5 2 RESET SEQUENCE MANAGER RSM 5 2 1 Introduction The reset sequence manager includes three RE SET sources as shown in Figure 12 m External RESET source pulse m Internal LVD RESET Low Voltage Detection m Internal WATCHDOG RESE
166. s cleared by hardware when 0 by a software sequence an access to the SR register followed by a read to the DR register 0 No ldle Line is detected 1 Idle Line is detected 100 164 Note The IDLE bit will not be set again until the RDREF bit has been set itself i e a new idle line oc curs This bit is not set by an idle line when the re ceiver wakes up from wake up mode Bit 3 OR Overrun error This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF 1 An interrupt is generated if RIE 1 in the CR2 reg ister It is cleared by hardware when RE 0 by a software sequence an access to the SR register followed by a read to the DR register 0 No Overrun error 1 Overrun error is detected Note When this bit is set RDR register content will not be lost but the shift register will be overwritten Bit 2 NF Noise flag This bit is set by hardware when noise is detected on a received frame It is cleared by hardware when RE 0 by a software sequence an access to the SR register followed by a read to the DR regis ter 0 No noise is detected 1 Noise is detected Note This bit does not generate interrupt as it ap pears at the same time as the RDRF bit which it self generates an interrupt Bit 1 FE Framing error This bit is set by hardware when a de synchroniza tion excessive noise or a break character is de tect
167. s set and cleared by software 0 The first clock transition is the first data capture edge 1 The second clock transition is the first capture edge Bit 1 0 SPR 1 0 Serial peripheral rate These bits are set and cleared by software Used with the SPR2 bit they select one of six baud rates to be used as the serial clock when the device is a master These 2 bits have no effect in slave mode Table 20 Serial Peripheral Baud Rate Stage SPm2 sPmi seno wh oo ofofo 191519 89 164 ST72311R ST72511R ST72512R ST72532R SERIAL PERIPHERAL INTERFACE Cont d STATUS REGISTER SR Read Only Reset Value 0000 0000 00h 7 0 Bit 7 SPIF Serial Peripheral data transfer flag This bit is set by hardware when a transfer has been completed An interrupt is generated if SPIE 1 in the CR register It is cleared by a soft ware sequence an access to the SR register fol lowed by a read or write to the DR register 0 Data transfer is in progress or has been ap proved by a clearing sequence 1 Data transfer between the device and an exter nal device has been completed Note While the SPIF bit is set all writes to the DR register are inhibited Bit 6 WCOL Write Collision status This bit is set by hardware when a write to the DR register is done during a transmit sequence It is cleared by a software se
168. sampling not being completed in the alloted time 10 8 3 3 A D Conversion Phases The A D conversion is based on two conversion phases as shown in Figure 63 m Sample capacitor loading duration During this phase the input voltage to be measured is loaded into the sample capacitor m A D conversion duration During this phase the A D conversion is computed 8 successive approximations cycles and the Capc sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy While the ADC is on these two phases are contin uously repeated At the end of each conversion the sample capaci tor is kept loaded with the previous measurement load The advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement 10 8 3 4 Software Procedure Refer to the control status register CSR and data register DR in Section 10 8 6 for the bit defini tions and to Figure 63 for the timings ADC Configuration The total duration of the A D conversion is 12 ADC clock periods 1 fapc 2 fopy 122 164 The analog input ports must be configured as in put no pull up no interrupt Refer to the I O ports chapter Using these pins as analog inputs does not affect the ability of the port to be read as a logic input In the CSR register Select the CH 3 0 bits to assign
169. soft ware reading the result in the DR register or writing to the CSR register 0 Conversion is not complete 1 Conversion can be read from the DR register Bit 6 Reserved must always be cleared Bit 5 ADON A D Converter On This bit is set and cleared by software 0 A D converter is switched off 1 A D converter is switched on Bit 4 Reserved must always be cleared Bit 3 0 CH 3 0 Channel Selection These bits are set and cleared by software They select the analog input to convert Note The number of pins AND the channel selec tion varies according to the device Refer to the de vice pinout r Bit 7 0 D 7 0 Analog Converted Value This register contains the converted analog value the range 00h to FFh Note Reading this register reset the COCO flag 123 164 ST72311R ST72511R ST72512R ST72532R 8 A D CONVERTOR ADC Cont d Table 24 ADC Register Map and Reset Values Address Register 7 Hex Label ADCDR D7 ER Reset Value 0 ADCCSR 0071h Standard Reset Value 4 124 164 ST72311R ST72511R ST72512R ST72532R 11 INSTRUCTION SET 11 1 ST7 ADDRESSING MODES so most of the addressing modes may be subdi lled hort The ST7 Core features 17 different addressing in Wo SUD odes ca Swor modes which be classified in 7 main groups Long addressing mode is more powerful be cause itcan use the full 64 Kbyte address space Addressi
170. sted 12 1 4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 64 Figure 64 Pin loading conditions ST7 PIN ST72311R ST72511R ST72512R ST72532R 12 1 5 Pin input voltage The input voltage measurement on a pin of the de vice is described in Figure 65 Figure 65 Pin input voltage PIN 131 164 ST72311R ST72511R ST72512R ST72532R 12 2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as absolute maxi tions is not implied Exposure to maximum rating mum ratings may cause permanent damage to conditions for extended periods may affect device the device This is a stress rating only and func reliability tional operation of the device under these condi 12 2 1 Voltage Characteristics Analog reference voltage Vpp2VppA AVppy and Variations between different digital power pins IVssa Vgsxl Variations between digital and analog ground pins Input voltage on Vpp pin IN 1117 amp 2 Input voltage on any other pin Electro static discharge voltage Human Body Model see Section 12 7 2 Absolute Electri Electro static discharge voltage Machine Model cal Sensitivity on page 141 12 2 2 Current Characteristics Symbol 7 Mexmumvelue Total current into Vpp power lines source 3 Total current out of Vgs ground lines sink 3 mA Output current sunk by any high sink UO pin Output current source by any l Os and
171. ster Bit 3 OCF2 Output Compare Flag 2 0 No match reset value 1 The content of the free running counter has matched the content of the OC2R register To clear this bit first read the SR register then read or write the low byte of the OC2R OC2LR reg ister Bit 2 0 Reserved forced by hardware to 0 76 164 INPUT CAPTURE 1 HIGH REGISTER IC1HR Read Only Reset Value Undefined This is an 8 bit read only register that contains the high part of the counter value transferred by the input capture 1 event 7 0 INPUT CAPTURE 1 LOW REGISTER IC1LR Read Only Reset Value Undefined This is an 8 bit read only register that contains the low part of the counter value transferred by the in put capture 1 event 7 0 pec pes OUTPUT COMPARE 1 HIGH REGISTER OC1HR Read Write Reset Value 1000 0000 80h This is an 8 bit register that contains the high part of the value to be compared to the CHR register 7 0 1 OUTPUT COMPARE 1 LOW REGISTER OC1LR Read Write Reset Value 0000 0000 00h This is an 8 bit register that contains the low part of the value to be compared to the CLR register 7 0 m 1 4 16 BIT TIMER Cont d OUTPUT COMPARE 2 HIGH REGISTER OC2HR Read Write Reset Value 1000 0000 80h This is an 8 bit register that contains the high part of the value to be compared to the CHR register 7 0 peu qo OUTPUT COMPARE
172. sured between interrupt event and interrupt vector fetch is the number of kou cycles needed to finish the current instruction execution 3 Data based on design simulation and or technology characteristics not tested in production 4 2 is load capacitance on OSC1 resp OSC2 pin 5 Rgis the equivalent serial resistance of the crystal or ceramic resonator 3 138 164 ST72311R ST72511R ST72512R ST72532R 12 6 MEMORY CHARACTERISTICS Subject to general operating condition for Vpp fosc and T4 unless otherwise specified 12 6 1 RAM and Hardware Registers Data retention mode 1 HALT mode or RESET 12 6 2 EEPROM Data Memory t Programming time 40 lt lt 85 prog for 1 up to 16 bytes at a time 40 lt lt 125 ZE Write erase cycles 3 25 300 000 12 6 3 EPROM Program Memory Symbor Parameter Conatons min Mex UV lamp is placed 1 inch Y from the device window terase Erase Time without any interposed s 20 filters Data retention EE Notes 1 Minimum Vpp supply voltage without losing data stored into RAM in in HALT mode or under RESET or into hardware registers only in HALT mode Guaranteed by construction not tested in production 2 The data retention time increase when the T4 decreases 3 Data based on reliability test results and monitored in production 4 Data given only as guid
173. t 10ms prior to the delivery of the next pulse Absolute Maximum Symbol ST72311R ST72511R ST72512R ST72532R Machine Model Test Sequence is loaded through S1 by the HV pulse gener ator 51 switches position from generator to ST7 A discharge from C to the ST7 occurs S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST7 is not left in charge state S2 must be opened at least 10ms prior to the delivery of the next pulse R machine resistance in series with S2 en sures a slow discharge ofthe ST7 Conditions Maximum value Unit Electro static NENNT NN voltage Human Body Model Jess 2900 Electro static discharge voltage Figure 75 Typical Equivalent ESD Circuits B C 100pF HUMAN BODY MODEL HIGH VOLTAGE PULSE GENERATOR Notes HIGH VOLTAGE PULSE GENERAT OR C 200pF MACHINE MODEL 1 Data based on characterization results not tested in production r 141 164 ST72311R ST72511R ST72512R ST72532R EMC CHARACTERISTICS 12 7 2 2 Static and Dynamic Latch Up LU 3 complementary static tests are required on 10 parts to assess the latch up performance A supply overvoltage applied to each power supply pin a current injection applied to each input output and configurable I O pin and power supply switch sequence are performed on each sample This test conforms to the EIA JESD 78 latch up st
174. t instruction of the interrupt service routine is fetched refer to Interrupt Mapping table for vector addresses The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack Note As a consequence of the IRET instruction the 1 and 10 bits will be restored from the stack and the program in the previous level will resume Table 5 Interrupt Software Priority Levels Interrupt software priority Level 10 Level 0 main Lw 1 0 High Level 3 interrupt disable Interrupt has the same ora lower software priority than current one THE INTERRUPT STAYS PENDING priority an current one software th i x 2 7 3 5 STACK X A CC LOAD 11 0 FROM INTERRUPT SW LOAD PC FROM INTERRUPT VECTOR 3 INTERRUPTS Cont d Servicing Pending Interrupts As several interrupts can be pending at the same time the interrupt to be taken into account is deter mined by the following two step process the highest software priority interrupt is serviced if several interrupts have the same software pri ority then the interrupt with the highest hardware priority is serviced first Figure 15 describes this decision process Figure 15 Priority Decision Process PENDING INTERRUPTS SOFTWARE Different PRIORITY HIGHEST S
175. ter J Typ wex Umi ME Conversion range Vesa Yona v Raw emaa internal sample andholacapactor Stabilization time after ADC enable 0 t Sample capacitor loading time l HS LOAD por 9 fopy 8MHz fapc 4MHz 4 Kane Hold conversion time Figure 91 Typical Application with ADC SAMPLING SWITCH ST72XXX Notes 1 Unless otherwise specified typical data are based on 25 and Vpp Vss 5V They are given only as design guide lines and are not tested 2 When and Vgga pins are not available on the pinout the ADC refer to Vpp and Vss 3 Any added external serial resistor will downgrade the ADC accuracy especially for resistance greater than 10kQ Data based on characterization results not tested in production 4 The stabilization time of the AD converter is masked by the first hoan The first conversion after the enable is then always valid 3 152 164 ST72311R ST72511R ST72512R ST72532R ADC CHARACTERISTICS Cont d ADC Accuracy with Vpp 5 0V Symbol Fame ______ Conditions Win Unit Differential linearity error Integral linearity error Figure 92 ADC Accuracy Characteristics Digital Result ADCDR 255 1 Example of an actual transfer curve 2 The ideal transfer curve 254 3 End point correla
176. the arbitration field which contains the 11 bit identifier ID and the Remote Transmission Request bit RTR The bit indicates whether it is a data frame or a re mote request frame A remote request frame does not have any data byte The control field contains the Identifier Extension bit IDE which indicates standard or extended format a reserved bit ro and in the last four bits a count of the data bytes DLC The data field ranges from zero to eight bytes and is followed by the Cyclic Redundancy Check CRC used as a frame integrity check for detecting bit errors r ST72311R ST72511R ST72512R ST72532R The acknowledgement ACK field comprises the ACK slot and the ACK delimiter The bit in the ACK slot is placed on the bus by the transmitter as a re cessive bit logical 1 It is overwritten as a domi nant bit logical 0 by those receivers which have at this time received the data correctly In this way the transmitting node can be assured that at least one receiver has correctly received its message Note that messages are acknowledged by the re ceivers regardless of the outcome of the accept ance test The end of the message is indicated by the End Of Frame EOF The intermission field defines the minimum number of bit periods separating con secutive messages If there is no subsequent bus access by any station the bus remains idle 10 7 3 2 Hardware Blocks The CAN controller contains the following
177. the baud rate using a 255 value prescal er whereas the conventional Baud Rate Genera tor retains industry standard software compatibili ly The extended baud rate generator block diagram is described in the Figure 54 The output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the ERPR or the ETPR register Note the extended prescaler is activated by set ting the ETPR or ERPR register to a value other 98 164 than zero The baud rates are calculated as fol lows cPU Sa fcpu 16 ERPR 16 ETPR with ETPR 1 255 see ETPR register ERPR 1 255 See ERPR register 10 6 4 6 Receiver Muting and Wake up Feature In multiprocessor configurations it is often desira ble that only the intended message recipient should actively receive the full message contents thus reducing redundant SCI service overhead for all non addressed receivers The non addressed devices may be placed in sleep mode by means of the muting function Setting the RWU bit by software puts the SCI in sleep mode All the reception status bits can not be set All the receive interrupt are inhibited A muted receiver may be awakened by one of the following two ways by Idle Line detection if the WAKE bit is reset by Address Mark detection if the WAKE bit is set Receiver wakes up by Idle Line detection when the Receive line has r
178. this order from the lowest to the highest MAIN IT4 IT3 IT2 IT1 ITO TLI The software priority is given for each interrupt Warning A stack overflow may occur without no tifying the software of the failure SOFTWARE PRIORITY L LEVEL D 1 1 1 1 1 1 N a lt N e 22 SOFTWARE PRIORITY 20 BYTES woo o C USED STACK 4 INTERRUPTS Cont d 6 5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read Write Reset Value 111x 1010 xAh 7 0 2 Bit 5 3 11 10 Software Interrupt Priority These two bits indicate the current interrupt soft ware priority Interrupt Software Priority Level 0 main Level 1 Level 2 Level 3 interrupt disable High These two bits are set cleared by hardware when entering in interrupt The loaded value is given by the corresponding bits in the interrupt software pri ority registers ISPRx They can be also set cleared by software with the RIM SIM HALT WFI IRET and PUSH POP in structions see Interrupt Dedicated Instruction Set table Note TLI TRAP and RESET events are non maskable sources and can interrupt a level 3 pro gram ST72311R ST72511R ST72512R ST72532R INTERRUPT SOFTWARE PRIORITY REGIS TERS ISPRX Read Write bit 7 4 of ISPR3 are read only Reset Values 1111 1111 FFh 7 0 These four registers c
179. tion Disabled Enabled LVD Reset Disabled Enabled Comments Supply Operating Range in the application Notes Signature 3 160 164 14 3 DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware and software development tools for the ST7 micro controller family Full details of tools available for Third Party Tools m ACTUM BP COSMIC CMX DATA I O HITEX STMicroelectronics Tools ST72311R ST72511R ST72512R ST72532R the ST7 from third party manufacturers can be ob tain from the STMicroelectronics Internet site gt http st7 st com HIWARE ISYSTEM KANDA m LEAP Tools from these manufacturers include C compli ers emulators and gang programmers Four types of development tool are offered by ST all of which connect to a PC via a parallel LPT port NENNEN In Circuit Emulation Programming Capability Software Inclu ded Yes Same features as ST7 CD ROM with ST7 Development Kit HDS2 emulator but no trace Yes DIP packages only ST7 Assembly toolchain logic analyzer WGDB7 powerful Source Level Yes powerful emulation fea Debugger for Win 3 1 Win 95 ST7 HDS2 Emulator tures including trace logic an No and NT alyzer C compiler demo versions ST7 Programming Board Note Yes All packages ST Realizer for Win 3 1 and Win 95 Windows Programming Tools for Win 3 1 Win 95 and NT 1 In Situ Programming ISP interface for FLASH dev
180. tion line 253 Er Total Unadjusted Error maximum deviation between the actual and the ideal transfer curves Eg Offset Error deviation between the first actual transition and the first ideal one Eg Gain Error deviation between the last ideal transition and the last actual one Ep Differential Linearity Error maximum deviation between actual steps and the ideal one E Integral Linearity Error maximum deviation between any actual transition and the end point 1 1 1 D 1 1 1 1 1 1 1 D 1 1 1 h correlation line 1 1 444 Vin LSBipgAD 253 254 255 256 DDA Notes 1 Data based on characterization results over the whole temperature range monitored in production 2 ADC Accuracy vs Negative Injection Current For 0 8 the typical leakage induced inside the die is 1 6 and the effect on the ADC accuracy is a loss of 1 LSB for each 10KQ increase of the external analog source impedance This effect on the ADC accuracy has been observed under worst case conditions for injection negative injection injection to an Input with analog capability adjacent to the enabled Analog Input at 5V Vpp supply and worst case temperature 153 164 ST72311R ST72511R ST72512R ST72532R 13 PACKAGE CHARACTERISTICS 13 1 PACKAGE MECHANICAL DATA Figure 93 64 Pin Thin Quad Flat Package m Pv Tr T T D pep pee BILL Far oos fors foal Lo
181. tus When the M bit is set word length is 9 bits and the 9th bit the MSB has to be stored in the T8 bit in the CR1 reg ister Character Transmission During an SCI transmission data shifts out least significant bit first on the TDO pin In this mode the DR register consists of a buffer TDR between the internal bus and the transmit shift register see Figure 52 Procedure Select the M bit to define the word length Selectthe desired baud rate using the BRR and the registers Setthe TE bit to assign the TDO pin to the alter nate function and to send a idle frame as first transmission Access the register and write the data to send in the DR register this sequence clears the TDRE bit Repeat this sequence for each data to be transmitted Clearing the TDRE bit is always performed by the following software sequence 1 An access to the SR register 2 A write to the DR register The TDRE bit is set by hardware and it indicates The TDR register is empty The data transfer is beginning The next data can be written in the DR register without overwriting the previous data This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register When a transmission is taking place a write in struction to the DR register stores the data in the TDR register and which is copied in the shift regis ter at the end of the current transmission When
182. ult because the data latches are only cleared at the end of the programming cycle and by the falling edge of LAT bit It is not possible to read the latched data This note is ilustrated by the Figure 6 Figure 5 Data EEPROM Programming Flowchart READ MODE LAT 0 PGM 0 READ BYTES IN EEPROM AREA INTERRUPT GENERATION IF 1 1 WRITE MODE LAT 1 PGM 0 WRITE UP TO 16 BYTES EEPROM AREA with the same 12 MSB of the address START PROGRAMMING CYCLE LAT 1 PGM 1 set by software CLEARED BY HARDWARE 17 164 ST72311R ST72511R ST72512R ST72532R DATA EEPROM Cont d 3 4 POWER SAVING MODES Wait mode The DATA EEPROM can enter WAIT mode on ex ecution of the WFI instruction of the microcontrol ler The DATA EEPROM will immediately enter this mode if there is no programming in progress otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode Halt mode The DATA EEPROM immediatly enters HALT mode if the microcontroller executes the HALT in struction Therefore the EEPROM will stop the function in progress and data may be corrupted Figure 6 Data EEPROM Programming Cycle READ OPERATION NOT POSSIBLE 3 5 ACCESS ERROR HANDLING If a read access occurs while LAT 1 then the data bus will not be driven If a write access occurs while LAT 0 then the data on the bus will not be latched If a programming cycle is interrupted by software RESET action the mem
183. ut Compare 2 Low Register R W 0040h MISCR2 Miscellaneous Register 2 TBCR2 Timer B Control Register 2 R W TBCR1 Timer B Control Register 1 R W TBSR Timer B Status Register Read Only TBIC1HR Timer B Input Capture 1 High Register Read Only TBIC1LR Timer B Input Capture 1 Low Register Read Only TBOC1HR_ Timer B Output Compare 1 High Register R W Timer B Output Compare 1 Low Register R W TIMER B TBCHR Timer B Counter High Register Read Only TBCLR Timer B Counter Low Register Read Only TBACHR Timer B Alternate Counter High Register Read Only TBACLR Timer B Alternate Counter Low Register Read Only TBIC2HR Timer B Input Capture 2 High Register Read Only TBIC2LR Timer B Input Capture 2 Low Register Read Only 2 Timer B Output Compare 2 High Register R W TBOC2LR Timer B Output Compare 2 Low Register R W SCISR SCI Status Register COh Read Only SCIDR SCI Data Register xxh R W SCIBRR SCI Baud Rate Register 00xx xxxx R W SCICR1 SCI Control Register 1 xxh R W SCICR2 SCI Control Register 2 00h R W SCIERPR SCI Extended Receive Prescaler Register 00h R W Reserved area SCIETPR SCI Extended Transmit Prescaler Register 00h R W 13 164 ST72311R ST72511R ST72512R ST72532R Register Reset Reserved Area 2 Bytes CANISR CAN Interrupt Status Register R W CANICR CAN Interrupt Control Register R W CANCSR CAN Control Status Register R W CAN Baud Rate Prescaler Register R W CANBTR CAN
184. uty cycle on the fly coUNTER 1 1 LI COUNTER OCRx DCRx 55 164 ST72311R ST72511R ST72512R ST72532R PWM AUTO RELOAD TIMER Cont d Independent PWM signal generation This mode allows up to four Pulse Width Modulat ed signals to be generated on the PWMx output pins with minimum core processing overhead This function is stopped during HALT mode Each PWMXx output signal can be selected inde pendently using the corresponding OEx bit in the PWM Control register PWMCR When this bit is set the corresponding I O pin is configured as out put push pull alternate function The PWM signals all have the same frequency which is controlled by the counter period and the ARR register value couren 256 ARR When a counter overflow occurs the PWMx pin level is changed depending on the corresponding Figure 32 PWM Auto reload Timer Function DUTY CYCLE REGISTER DCRx COUNTER AUTO RELOAD REGISTER ARR 000 WITH OEx 1 AND OPx 0 WITH OEx 1 AND 1 PWMx OUTPUT OPx output polarity bit in the PWMCR register When the counter reaches the value contained in one of the output compare register OCRx the corresponding PWMx pin level is restored It should be noted that the reload values will also affect the value and the resolution of the duty cycle of the PWM output signal To obtain a signal on a pin the contents of the OCR
185. valid event on the ICAP1 the coun ter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP 1 pin the ICF1 bit is set and the val ue FFFDh is loaded in the IC1R register Because the ICF1 bit is set when an active edge occurs an interrupt can be generated if the ICIE bit is set 70 164 Clearing the Input Capture interrupt request i e clearing the bit is done in two steps 1 Reading the SR register while the ICF bit is set 2 An access read or write to the register The register value required for a specific timing application can be calculated using the fol lowing formula t f OCR PRESC Where t Pulse period in seconds CPU clock frequency hertz PRESC Timer prescaler factor 2 4 8 depend ing on the CC 1 0 bits see Table 18 Clock Control Bits If the timer clock is an external clock the formula is OCR t fgyxT 5 Where t fexT Pulse period in seconds External timer clock frequency in hertz When the value of the counter is equal to the value of the contents of the register the OLVL1 bit is output on the OCMP1 pin See Figure 44 Notes 1 The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt 2 When the Pulse Width Modulation PWM and One Pulse Mode OPM bits are both set the PWM mode is the only active one 3
186. vate the input cap ture function Moreover if one of the ICAP pin is configured as an input and the second one as an output an interrupt can be generated if the user toggle the output pin and if the ICIE bit is set This can be avoided if the input capture func tion jis disabled by reading the IC HR see note 1 6 The TOF bit can be used with interrupt in order to measure event that go beyond the timer range FFFFh 65 164 ST72311R ST72511R ST72512R ST72532R 16 BIT TIMER Cont d Figure 39 Input Capture Block Diagram Control Register 1 CR1 EDGE EDGE DETECT CIRCUIT2 CIRCUIT1 IC2R Register IC1R Register Status Register SR Control Register 2 CR2 TIT ileje COUNTER Figure 40 Input Capture Timing Diagram Timer clock COUNTER REGISTER X o XC ICAPi PIN Se Ss 3 ICAPi FLAG REGISTER FF03 Note Active edge is rising edge 3 66 164 16 BIT Cont d 10 4 3 4 Output Compare In this section the index may be 1 or 2 because there are 2 output compare functions in the 16 bit timer This function can be used to control an output waveform or indicate when a period of time has elapsed When match is found between the Output Com pare register and the free running counter the out put compare function Assigns pins with a programmable value if the OCIE bit is set Sets a flag in the status register
187. vices may be either masters or slaves The SPI is normally used for communication be tween the microcontroller and external peripherals or another microcontroller Refer to the Pin Description chapter for the device specific pin out 10 5 2 Main Features m Full duplex three wire synchronous transfers Master or slave operation Four master mode frequencies Maximum slave mode frequency fCPU 2 Four programmable master bit rates Programmable clock polarity and phase End of transfer interrupt flag Write collision flag protection Master mode fault protection capability Figure 46 Serial Peripheral Interface Master Slave MASTER MSBit 4 LSBit 8 SHIFT SPI CLOCK GENERATOR ST72311R ST72511R ST72512R ST72532R 10 5 3 General description The SPI is connected to external devices through 4 alternate pins MISO Master In Slave Out pin MOSI Master Out Slave In pin SCK Serial Clock pin SS Slave select pin A basic example of interconnections between a single master and a single slave is illustrated on Figure 46 The MOSI pins are connected together as are MISO pins In this way data is transferred serially between master and slave most significant bit first When the master device transmits data to a slave device via MOSI pin the slave device responds by sending data to the master device via the MISO pin This implies full duplex transmission wit
188. x register must be greater than the contents of the ARR register The maximum available resolution for the PWMx duty cycle is Resolution 1 256 ARR Note To get the maximum resolution 1 256 the ARR register must be 0 With this maximum reso 0 and 100 can be obtained by changing the polarity Figure 33 PWM Signal from 0 to 100 Duty Cycle fCOUNTER ARR FDh m EE aa 1 1 1 1 LI 1 D D 1 LI D 1 LI LI LI OCRx FCh 1 1 OCRx FDh 1 1 0 OCRx FEh 2 296 a SES lt OCRx FFh 56 164 3 ST72311R ST72511R ST72512R ST72532R PWM AUTO RELOAD TIMER Cont d Output compare and Time base interrupt On overflow the OVF flag of the CSR register is set and an overflow interrupt request is generated if the overflow interrupt enable bit OIE in the CSR register is set The OVF flag must be reset by the user software This interrupt can be used as a time base in the application External clock and event detector mode Using the fgxr external prescaler input clock the auto reload timer can be used as an external clock event detector In this mode the ARR register is used to select the neyeynt number of events to be counted before setting the OVF flag Nevent 256 ARR When entering HALT mode while 1 is selected all the timer control registers are frozen but the counter continues to increment If the OIE bit is set the next overf
189. ytes CAN 2 0B passive Core 104 164 accordingly although such frames cannot be trans mitted nor received The same applies to overload frames which are recognized but never initiated 3 CONTROLLER AREA NETWORK Cont d 10 7 2 Main Features Support of CAN specification 2 0A and 2 0B pas sive Three prioritized 10 byte Transmit Receive mes sage buffers Two programmable global 12 bit message ac ceptance filters Programmable baud rates up to 1 MBit s Buffer flip flopping capability in transmission Maskable interrupts for transmit receive one per buffer error and wake up Automatic low power mode after 20 recessive bits or on demand standby mode Interrupt driven wake up from standby mode upon reception of dominant pulse Optional dominant pulse transmission on leaving standby mode Automatic message queuing for transmission upon writing of data byte 7 Programmable loop back mode for self test op eration Advanced error detection and diagnosis func tions Software efficient buffer mapping ata unique ad dress space Scalable architecture 10 7 3 Functional Description 10 7 3 1 Frame Formats A summary of all the CAN frame formats is given in Figure 56 for reference It covers only the stand ard frame format since the extended one is only acknowledged A message begins with a start bit called Start Of Frame SOF This bit is followed by

ST ST72311R ST72511R ST72512R ST72532R 8-BIT MCU WITH NESTED INTERRUPTS EEPROM ADC 16-BIT TIMERS 8-BIT PWM ART SPI SCI CAN INTERFACES handbook

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