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ST ST72104G ST72215G ST72216G ST72254G handbook

1. 2ED3 50 140 4 16 BIT Cont d 12 2 3 5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs This mode is selected via the OPM bit in the CR2 register The One Pulse mode uses the Input Capture1 function and the Output Compare1 function Procedure To use One Pulse mode 1 Load the OC1R register with the value corre sponding to the length of the pulse see the for mula in the opposite column 2 Select the following in the CR1 register Using the OLVL 1 bit select the level to be ap plied to the OCMP1 pin after the pulse Using the OLVL2 bit select the level to be ap plied to the OCMP1 pin during the pulse Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit the ICAP1 pin must be configured as floating input 3 Select the following in the CR2 register Set the OC1E bit the OCMP1 pin is then ded icated to the Output Compare 1 function Set the OPM bit Select the timer clock CC 1 0 see Table 13 Clock Control Bits One Pulse mode cycle When event occurs on ICAP1 OCMP 1 OLVL2 Counter is reset to FFFCh ICF1 bit is set OCMP1 OLVL1 When Counter OCAR Then on a valid event on the ICAP1 pin the coun ter is initialized to FFFCh and the OLVL2 bit is loaded on the pin the ICF1 bit is set and the value FFFDh is loaded in t
2. PY 7 bit Master receiver 9 nie T Pani e Se Legend S Start S Repeated Start P Stop A Acknowledge NA Non acknowledge EVx Event with interrupt if ITE 1 EVF 1 ADSL 1 cleared by reading SR1 register 2 EVF 1 1 cleared by reading SR1 register followed by reading DR register EV3 EVF 1 BTF 1 cleared by reading SR1 register followed by writing DR register EV3 1 EVF 1 AF 1 BTF 1 AF is cleared by reading SR1 register BTF is cleared by releasing the lines STOP 1 STOP 0 or by writing DR register DR FFh Note If lines are released by STOP 1 STOP 0 the subsequent EV4 is not seen 4 EVF 1 STOPF 1 cleared by reading SR2 register EV5 EVF 1 SB 1 cleared by reading SR1 register followed by writing DR register EV6 EVF 1 cleared by reading SR1 register followed by writing CR register for example PE 1 EV7 EVF 1 BTF 1 cleared by reading SR1 register followed by reading DR register 8 EVF 1 BTF 1 cleared by reading SR1 register followed by writing DR register 9 EVF 1 ADD10 1 cleared by reading SR1 register followed by writing DR register 78 140 4 57721046 ST72215G ST72216G 57722546 2 5 12 4 5 Low Power Modes Description No effect on I C interface 2 interrupts cause the device to exit from WAIT mode registers are frozen In HAL
3. 2 See Lead Detail pwep pee 1 pe VR01725J Ut N 2 Number of Pins Figure 98 28 Pin Plastic Small Outline Package 300 mil Width zesose foto m foro os oooso e oss nos fosa o2s ose oors 74 e pep pe w es fosos o7 ooo oos falon foo e ew oo 5028 4 130 140 57721046 ST72215G ST72216G 57722546 15 2 THERMAL CHARACTERISTICS Package thermal resistance junction to ambient SDIP32 60 C W 5028 75 Notes 1 The power dissipation is obtained from the formula where Pyr is the chip internal power IppxVpp and is the port power dissipation determined by the user 2 The average chip junction temperature can be obtained from the formula Ty T4 Pp x RthJA 131 140 4 ST72104G ST72215G ST72216G 57722549 15 3 SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only Recommended glue for SMD plastic packages as design guidelines in Figure 99 and Figure 100 dedicated to molding compound with silicone m Heraeus PD945 PD955 m Loctite 3615 3298 Figure 99 Recommended
4. SOFTWARE INTERRUPT 25 82 EXIERNAL INTERRUPTS gt sisi xe RR ERR E E eam ERAT 25 8 amp 3 PERIPHERAL INTERRUPTS 25 9 POWER SAVINGMODES 27 9 1 INTRODUCTION ben reu BR TEE ea es 27 92 SEOW MODE ru XR du lena ee E e 27 953 WAIT MODE 1 AREE RE be E IgE iue dtd 28 94 LHAET MODE i EE UR e expe dc deed 29 10 OL PORTS evil Nes 30 10 1 INTRODUCTION 3 eet TES GR eee ee ERE 30 10 2 FUNCTIONAL DESCRIPTION 30 10 21 Input Modes neire ie oc RERO SUR EH URS UR 30 10 2 20utpUt MOGeS 45 2 3 orae do E b dp doe un Riu b EDU Udo 30 2 140 Table of Contents 10 2 3Alternate Functions 30 10 3 PORT IMPLEMENTATION 33 10 4 LOW POWER MODES 34 10 5 INTERRUPTS ttt bee ee eel beds edita tc 34 10 6 REGISTER 34 11 MISCELLANEOUS REGISTERS 36 11 1 PORT INTERRUPT SENSITIVITY 36 11 2 VO PORT A
5. wee Exclusive OR A AXORM N Z 95 140 4 ST72104G ST72215G ST72216G ST72254G 14 ELECTRICAL CHARACTERISTICS 14 1 PARAMETER CONDITIONS Unless otherwise specified all voltages are re ferred to 14 1 1 Minimum and Maximum values Unless otherwise specified the minimum and max imum values are guaranteed in the worst condi tions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at 25 and Ta T amax given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the min imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation meant3 14 1 2 Typical values Unless otherwise specified typical data are based on TA 25 C Vpp 5V for the 4 5 lt lt 5 5 voltage range and Vpp 3 3V for the 3 lt lt 4 voltage range They are given only as design guidelines and are not tested 14 1 3 Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested 14 1 4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 49 Figure 49 P
6. e ere fo o para mG EE ERE BU E c ee ed fens po ees x meson folors p Joo r a Not Connected 7 E N ER o x 0 malu IIS TID In situ programming selection Should be tied low in standard user mode LL T eo s lll wmewm 7 Notes 1 In the interrupt input column eiX defines the associated external interrupt vector If the weak pull up column wpu is merged with the interrupt column int then the I O configuration is pull up interrupt input else the configuration is floating interrupt input 2 In the open drain output column T defines a true open drain I O P Buffer and protection diode to are not implemented See Section 10 O PORTS on page 30 and Section 14 8 I O PORT PIN CHAR ACTERISTICS on page 118 for more details 3 OSC1 and OSC2 pins connect a crystal or ceramic resonator an external RC or an external source to the on chip oscillator see Section 2 PIN DESCRIPTION on page 7 and Section 14 5 CLOCK AND TIM ING CHARACTERISTICS on page 105 for more details 4 9 140 ST72104G ST72215G ST72216G ST72254G 3 REGISTER amp MEMORY MAP As shown in the Figure 4 the MCU is capable of addressing 64K bytes of memories and regis ters The available memory loca
7. o WAIT No effect on A D Converter A D Converter disabled After wakeup from Halt mode the A D Con HALT REANO verter requires a stabilisation time before ac curate conversions can be performed Note The A D converter may be disabled by reset ting the ADON bit This feature allows reduced power consumption when no conversion is needed and between single shot conversions 12 5 5 Interrupts None 87 140 ST72104G ST72215G ST72216G ST72254G 8 A D CONVERTER ADC Cont d 12 5 6 Register Description CONTROL STATUS REGISTER CSR Read Write Reset Value 0000 0000 00h 7 0 Bit 7 Conversion Complete This bit is set by hardware It is cleared by soft ware reading the result in the DR register or writing to the register 0 Conversion is not complete 1 Conversion can be read from the DR register Bit 6 Reserved must always be cleared Bit 5 ADON A D Converter On This bit is set and cleared by software 0 A D converter is switched off 1 A D converter is switched on Bit 4 Reserved must always be cleared Bits 3 0 CH 3 0 Channel Selection These bits are set and cleared by software They select the analog input to convert Channel Pin CH3 ANO 0 Of 9 9 AIN4 AIN5 AIN6 Note The number of pins AND the channel selec tion varies according to the device Refer to the de vice pinout 88 140 DATA REGISTER DR Read Only Reset Value
8. KZ 16 BIT TIMER B WATCHDOG V1VG 554 6 140 4 2 PIN DESCRIPTION Figure 2 28 Pin SO Package Pinout ST72104G ST72215G ST72216G ST72254G RESET rj OSC1 OSC2 r3 SS PB7 C ISPCLK SCK PB6 4 ISPDATA MISO PB5 4 MOSI PB4 4 OCMP2_A PB3 ICAP2_A PB2 OCMP1_A PB1 ICAP1_A PBO AIN5 EXTCLK_A PC5 AIN4 0CMP2_B PC4 rj AIN3 ICAP2_B PC3 Da OON ei or 171 1 PC1 OCMP1 B AIN1 153 PC2 MCO AIN2 HS 20 high sink capability eiX associated external interrupt vector Figure 3 32 Pin SDIP Package Pinout RESET OSC1 OSC2 SS PB7 ISPCLK SCK PB6 ISPDATA MISO PB5 MOSI PB4 NC NC OCMP2 ICAP2 A PB2 OCMP1 A PB1 ICAP1 A PBO AINS EXTCLK A PC5 2 4 AINS ICAP2 B PC3 1 2 3 4 5 6 7 8 c eiO ei1 PA7 HS PCO ICAP1 B AINO PC1 OCMP1 B AIN1 PC2 MCO AIN2 HS 20 high sink capability eiX associated external interrupt vector 4 ST72104G ST72215G ST72216G ST72254G PIN DESCRIPTION Cont d For external pin connection guidelines refer to Section 14 ELECTRICAL CHARACTERISTICS on page 96 Legend Abbreviations for Table 1 Type input output S supply Input level A Dedicated analog input In Output level C CMOS 0 3Vpp 0 7Vpp CMOS 0 3Vpp 0 7Vpp with input trigger Output level HS 20
9. register contains the value of the free running counter on the active transition on the see Figure 31 A timer interrupt is generated if the ICIE bit is set and the bit is cleared in the CC register Other wise the interrupt remains pending until both conditions become true Clearing the Input Capture interrupt request i e clearing the ICF bit is done in two steps 1 Reading the SR register while the ICFi bit is set 2 An access read or write to the register Notes 1 After reading the IC HR register the transfer of input capture data is inhibited and ICF will never be set until the register is also read 2 The IC R register contains the free running counter value which corresponds to the most recent input capture 3 The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions 4 One Pulse mode and PWM mode only the input capture 2 function can be used 5 The alternate inputs ICAP1 amp ICAP2 always directly connected to the timer So any transitions on these pins activate the input cap ture function Moreover if one of the ICAP pin is configured as an input and the second one as an output an interrupt can be generated if the user tog gles the output pin and if the ICIE bit is set This can be avoided if the input capture func tion is disabled by reading the see note 6 The TOF
10. Bit 2 CPHA Clock phase This bit is set and cleared by software 0 The first clock transition is the first data capture edge 1 The second clock transition is the first capture edge Bit 1 0 SPR 1 0 Serial peripheral rate These bits are set and cleared by software Used with the SPR2 bit they select one of six baud rates to be used as the serial clock when the device is a master These 2 bits have no effect in slave mode Table 15 Serial Peripheral Baud Rate Serial Clock SPR2 SPR1 SPRO fopu 4 fcpu 8 fopy 16 fopy 32 fcpu 64 o o ololo fopy 128 4 SERIAL PERIPHERAL INTERFACE Cont d STATUS REGISTER SR Read Only Reset Value 0000 0000 00h 7 0 SPIF WCOL MODF Bit 7 SPIF Serial Peripheral data transfer flag This bit is set by hardware when a transfer has been completed An interrupt is generated if SPIE 1 in the CR register It is cleared by a soft ware sequence an access to the SR register fol lowed by a read or write to the DR register 0 Data transfer is in progress or has been ap proved by a clearing sequence 1 Data transfer between the device and an exter nal device has been completed Note While the SPIF bit is set all writes to the DR register are inhibited Bit 6 WCOL Write Collision status This bit is set by hardware when a write t
11. Figure 101 ROM Factory Coded Device Types TEMP DEVICE PACKAGE RANGE iS Code name defined by STMicroelectronics 1 standard 0 to 70 C 5 extended 10 to 85 C 6 industrial 40 to 85 C 7 automotive 40 to 105 C 3 automotive 40 to 125 C B Plastic DIP M Plastic SOIC ST72104G1 ST72104G2 ST72215G2 ST72216G1 577225401 ST72254G2 Figure 102 FLASH User Programmable Device Types TEMP DEVICE PACKAGE RANGE m 1 standard 0 to 70 C 5 extended 10 to 85 C 6 industrial 40 to 85 C 7 automotive 40 to 105 C 3 automotive 40 to 125 C B Plastic DIP Plastic SOIC ST72C104G1 ST72C104G2 ST72C215G2 ST72C216G1 4 134 140 57721046 ST72215G ST72216G 57722546 TRANSFER OF CUSTOMER CODE Cont d MICROCONTROLLER OPTION LIST Customer Address Contact Phone No Reference Device ST72104G1 4KB ST72215G2 4 ST72254G1 4KB ST72104G2 BKB ST72216G1 8KB ST72254G2 8KB Package S028 Tape amp Reel Tube SDIP32 Marking Standard Marking Special Marking 5028 max 13 Chars SDIP32 max 15 Chars Authorized characters are letters digits and spaces only Please consult your lo cal STMicroelectronics sales office for other marking details if required External Interrupt ITO interrupt vector Port A IT1 interrupt vector Port B amp C 1 ITO interrupt vector
12. port configuration 4 126 140 57721046 ST72215G ST72216G 57722546 COMMUNICATION INTERFACE CHARACTERISTICS Cont d 14 11 2 Inter IC Control Interface Refer to I O port characteristics for more details on the input output alternate function characteristics for V T atherwite spocified and SCLI The ST7 C interface meets the 9567 requirements of the Standard 2 communication protocol described in the following table wenn SOL ciockhionime 9 1 uson SOAsctiptine SDA and SCL fall time mm 2 10 3 wer STOP eoon STOP to START condition time bus free i Figure 94 Typical Application with IC Bus and Timing Diagram SDAI SCLI ST72XXX REPEATED START 22 twSTO STA DE d ds 1 tsu SDA 1 e o thistay tw SCKH w SCKL tysck Notes 1 Data based on standard 12 protocol requirement not tested in production 2 The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL 3 The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal 4 Measurement points are done at CMOS levels 0 3xVpp 0 7xVpp 127 140 ST72104G ST72215G ST72216G ST72254G 14 12 8 BIT ADC CHARACTE
13. An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine If several input pins connected to the same inter rupt vector are configured as interrupts their sig nals are logically ANDed before entering the edge level detection block Caution The type of sensitivity defined in the Mis cellaneous or Interrupt register if available ap plies to the ei source In case of an ANDed source as described on the I O ports section a low level on an I O pin configured as input with interrupt masks the interrupt request even in case of rising edge sensitivity 8 3 PERIPHERAL INTERRUPTS Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both The bit of the CC register is cleared The corresponding enable bit is set in the control register If any of these two conditions is false the interrupt is latched and thus remains pending Clearing an interrupt request is done by Writing 0 to the corresponding bit in the status register or Access to the status register while the flag is set followed by a read or write of an associated reg ister Note the clearing sequence resets the internal latch A pending interrupt i e waiting for being en abled will therefore be lost if the clear sequence is executed 25 140 ST72104G ST72215G ST72216G S
14. 7 0 BE JE EE INPUT CAPTURE 2 LOW REGISTER IC2LR Read Only Reset Value Undefined This is an 8 bit read only register that contains the low part of the counter value transferred by the In put Capture 2 event 7 0 57721046 ST72215G ST72216G 57722546 16 Cont d Table 14 16 Bit Timer Register and Reset Values Address Register 7 1 Hex Label Timer A 32 CR1 Ed d zs i pr id Timer B 42 Reset Value Timer A 31 CR2 P s do rds Timer B 41 Reset Value Timer A 33 SR 2 37 Timer 43 Reset Value Timer 34 ICHR1 Timer 44 Reset Value Timer A 35 ICLR1 Timer B 45 Reset Value Timer A 36 OCHR1 Timer B 46 Reset Value Timer A 37 OCLR1 Timer 47 Reset Value Timer A OCHR2 Timer B 4E Reset Value Timer OCLR2 Timer 4F Reset Value Timer A 38 Timer B 48 Reset Value Timer A 39 Timer B 49 Reset Value Timer A 3A Timer B 4A Reset Value Timer A 3B Timer B 4B Reset Value Timer A 3C ICHR2 Timer B 4C Reset Value Timer A 3D ICLR2 Timer B 4D Reset Value 59 140 4 ST72104G ST72215G ST72216G ST72254G 12 3 SERIAL PERIPHERAL INTERFACE SPI 12 3 1 Introduction The Serial Peripheral Interface SPI allows full duplex synchronous serial communication with external devices An SPI system may consist of a master and one or more slaves or a system
15. Bit 1 EXTIT External Interrupt Configuration This option bit allows the external interrupt map ping to be configured as shown in Table 24 Table 24 External Interrupt Configuration External ITO External IT1 EXTIT Ports PB7 PBO Ports PA7 PAO Ports PC5 PCO 1 Ports PA7 PAO Ports PC5 PCO Ports PB7 PBO 0 Bit 0 FMP Full memory protection This option bit enables or disables external access to the internal program memory read out protec tion Clearing this bit causes the erasing to 00 of the whole memory including the option byte 0 Program memory not read out protected 1 Program memory read out protected USER OPTION BYTE 1 Bit 7 CFC Clock filter control on off This option bit enables or disables the clock filter CF features 0 Clock filter enabled 1 Clock filter disabled Bit 6 4 OSC 2 0 Oscillator selection These three option bits can be used to select the main oscillator as shown in Table 25 Bit 3 2 LVD 1 0 Low voltage detection selection These option bits enable the LVD block with a se lected threshold as shown in Table 26 Bit 1 WDG HALT Watchdog and halt mode This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active 0 No Reset generation when entering Halt mode 1 Reset generation when entering Halt mode Bit 0 WDG SW Hardware or software watchdog This option bit selects the watchdog type 0 Hardware watchdog a
16. A OCR At Where At Output compare period in seconds fexr External timer clock frequency hertz Clearing the output compare interrupt request i e clearing the OCFi bit is done by 1 Reading the SR register while the OCFi bit is set 2 An access read or write to the register The following procedure is recommended to pre vent the OCFi bit from being set between the time itis read and the write to the register Write to the OC HR register further compares are inhibited Read the SR register first step of the clearance of the OCFi bit which may be already set Write to the register enables the output compare function and clears the OCFi bit 4 16 Notes 1 After a processor write cycle to the OC HR reg ister the output compare function is inhibited until the register is also written If the bit is not set the OCMP pin is general I O port and the OLVL bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set When the timer clock is 2 and OCMPi are set while the counter value equals the register value see Figure 33 on page 53 This behaviour is the same in OPM or PWM mode When the timer clock is fepy 4 fopy 8 or in external clock mode and are set while the counter value equals the OC R re
17. ADDO Address direction bit This bit is don t care the interface acknowledges either 0 or 1 It is not cleared when the interface is disabled PE 0 Note Address 01h is always ignored 10 bit Addressing Mode Bit 7 0 ADD7 ADDO nterface adaress These are the least significant bits of the 2 bus address of the interface They are not cleared when the interface is disabled 0 84 140 Bit 7 6 FR1 FRO Frequency bits These bits are set by software only when the inter face is disabled 0 To configure the interface to 1 C specifed delays select the value corre sponding to the microcontroller frequency Fepy Bit 5 3 Reserved Bit 2 1 ADD9 ADDS nterface address These are the most significant bits of the 2 bus address of the interface 10 bit mode only They are not cleared when the interface is disabled 0 Bit 0 Reserved 4 57721046 ST72215G ST72216G 57722546 BUS INTERFACE Contd Table 17 2 Register Map and Reset Values Address Register 1 Hex Label 0028h I2CCR ENGC START ACK STOP Reset Value 0 0 0 0029h I2CSR1 EVF BUSY BTF ADSL M SL Reset Value 0 0 0 0 0 0 0 0 0 I2CSR2 STOPF ARLO BERR GCAL 02Bh I2CCCR FM SM CC6 5 CC4 CC3 CC2 CCO Reset Value 0 0 0 0 0 0 0 0 02Ch I2COAR1 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADDO Reset Value 0 0 0 0 0 0 0 0 2 2 FR1 ADD9 ADD8 4 85 140 ST72104G ST72215G ST72216G ST72254G 12 5 8
18. TBOC2LR TIMER B Timer B Control Register 2 Timer B Control Register 1 Timer B Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register Reserved 32 Bytes R W R W Read Only Read Only Read Only R W R W Read Only Read Only Read Only Read Only Read Only Read Only R W R W 0070h ADC ADCDR Data Register 00h Read Only 0071h ADCCSR Control Status Register 00h R W Reserved 14 Bytes Legend x undefined R W read write Notes 1 The contents of the I O port DR registers are readable only in output configuration In input configura tion the values of the I O pins are returned instead of the DR register contents 2 The bits associated with unavailable pins must always keep their reset value 4 12 140 4 FLASH PROGRAM MEMORY 4 1 INTRODUCTION FLASH devices have a single voltage non volatile FLASH memory that may be programmed in situ or plugged in a programming tool on a byte by byte basis 4 2 MAIN FEATURES Remote In Situ Programming ISP mode Up to 16 bytes programmed in the same cycle MTP memo
19. high sink on N buffer only Port and control configuration Input float floating wpu weak pull up int interrupt ana analog Output OD open drain 2 PP push pull Refer to Section 10 PORTS page 30 for more details on the software configuration of the I O ports The RESET configuration of each pin is shown in bold This configuration is valid as long as the device is in reset state Table 1 Device Pin Description Port Control Main Function Alternate Function Wiese S External clock input or Resonator oscillator in verter input or resistor input for RC hee ep ar fe e Poner onsec x x SPI Serial Clock or ISP Clock Serial Clock or ISP Clock Sta re Not Connected E E sr X R Pores swerkouaeomvasz secar s o p TinerA pu Capnre A x er X fett PBO ICAP1 vof et X PotBO BO Timer A Input Timer A Input Capture 1 12 PC5 EXTCLK_A AIN5 eid eit Port C5 A Input 2 Analog Input 5 Timer B Output Compare 2 or T Timer B Input Capture 2 or aj O g 8 140 57721046 ST72215G ST72216G 57722546 Port Control Main Function Alternate Function adis Main clock output or vene mme jio o
20. is cleared By default an interrupt routine is not interruptable 4 57721046 ST72215G ST72216G 57722546 because the bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine If the bit is cleared by software in the interrupt routine pending interrupts are serviced regardless of the priority level of the cur rent interrupt routine Bit 2 N Negative This bit is set and cleared by hardware It is repre sentative of the result sign of the last arithmetic logical or data manipulation It is a copy of the 7 bit of the result 0 The result of the last operation is positive or null 1 The result of the last operation is negative i e the most significant bit is a logic 1 This bit is accessed by the JRMI and JRPL instruc tions Bit 1 Z Zero This bit is set and cleared by hardware This bit in dicates that the result of the last arithmetic logical or data manipulation is zero 0 The result of the last operation is different from Zero 1 The result of the last operation is zero This bit is accessed by the JREQ and JRNE test instructions Bit 0 C Carry borrow This bit is set and cleared by hardware and soft ware It indicates an overflow or an underflow has occurred during the last arithmetic operation 0 No overflow or underflow has occurred 1 An overflow or underflow has occurred This bit is driven by the SCF and RCF instruction
21. pF OSC2 driving current 14 5 3 1 Typical Crystal Resonators Option Byte Reference Config S 200 30 30 50 Afogc 30pPM5 430ppM Rg 2000 MP 5 lt x mJ Characteristic 1 553 400 30 30 30 Afosc 30ppmos c 30ppm r4 Typ Rg 602 553 800 30 30 30 30 lt 30 250 553 1600 30 30 30 16 2 Afosc t30ppmos c 30ppmaAral Typ Rs 1 5Q Figure 64 Typical Application with a Crystal Resonator RESONATOR ST72XXX Notes 1 Resonator characteristics given by the crystal manufacturer 2 tsu gsc S the typical oscillator start up time measured between Vpp 2 8V and the fetch of the first instruction with a quick NE ramp up from 0 to 5V 50 5 3 The oscillator selection can be optimized in terms of supply current using an high quality resonator with small Rs value Refer to crystal manufacturer for more details 4 106 140 57721046 ST72215G ST72216G 57722546 CLOCK AND TIMING CHARACTERISTICS Cont d 14 5 3 2 Typical Ceramic Resonators Symb Conditions Ceramic resonator start up time ms tsu oso is the typical oscillator start up time measured between Vpp 2 8V and the fetch of the first instruction with a quick Vpp ramp up from 0 to 5V 50us Table 21 Typical Ceramic Resonators for General Purpose Applications CSTS0200MG06 CSTCC2 00MG0H6 CSTS0200MG06 CSTCC2 00MG0H6 CSTS04
22. 1 Watchdog Timer Symbol Parameter Conditions 4 12 288 786 432 Watchdog time out duration co SE a EY 14 10 2 16 Bit Timer Parameter Condos Typ TTL evt M Pme Resa pmen 4 124 140 57721046 ST72215G ST72216G 57722546 14 11 COMMUNICATION INTERFACE CHARACTERISTICS 14 11 1 SPI Serial Peripheral Interface Refer to I O port characteristics for more details on input output alternate function characteristics Subject to general operating conditions for V pp tne fosc and T4 unless otherwise specified SS SCK MOSI MISO Symbol Parameter Conditions Min Max Unit Master 1 28 4 fcpu 8MHz 0 0625 2 SPI clock frequency SEM MHz c SCK Slave Sun 0 epu CPU 2 60 SPI clock rise and fall time see I O port pin description f SCK tsuss 55 setup time Slave 120 88 SS hold time Slave 120 SCK high and low time Hae 2 w SCKL Data input setup time ge su Sl ns Data input hold time h Sl ta so Data output access time Slave 0 120 tdis SO Data output disable time Slave 240 t Dat tput valid ti 120 50 ihc nue sonia Slave after enable edge th so Data output hold time 0 t Data output valid
23. 140 ST72104G ST72215G ST72216G ST72254G SERIAL PERIPHERAL INTERFACE Cont d Table 16 SPI Register Map and Reset Values Address Register 7 1 Hex Label 0021h SPIDR MSB LSB Reset Value x x x x x x SPICR SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPRO 0022h Reset Value 0 0 0 0 SPISR SPIF WCOL MODF ky 72 140 12 4 IPC BUS INTERFACE I2C 12 4 1 Introduction The I C Bus Interface serves as an interface be tween the microcontroller and the serial 2 bus It provides both multimaster and slave functions and controls all 1 C bus specific sequencing pro tocol arbitration and timing It supports fast 12 mode 400kHz 12 4 2 Main Features Parallel bus I2C protocol converter Multi master capability 7 bit 10 bit Addressing Transmitter Receiver flag End of byte transmission flag Transfer problem detection Master Features Clock generation 2 bus busy flag Arbitration Lost Flag End of byte transmission flag Transmitter Receiver Flag Start bit detection flag Start and Stop generation Slave Features Stop bit detection 2 bus busy flag Detection of misplaced start or stop condition Programmable 2 Address detection Transfer problem detection End of byte transmission flag m Transmitter Receiver flag 12 4 3 General Description In addition to receiving and transmitting data this interface converts it from serial to parallel format and vice versa using either a
24. 16 BIT TIMER 12 2 1 Introduction The timer consists of a 16 bit free running counter driven by a programmable prescaler It may be used for a variety of purposes including measuring the pulse lengths of up to two input sig nals input capture or generating up to two output waveforms output compare and Pulse lengths and waveform periods can be mod ulated from a few microseconds to several milli seconds using the timer prescaler and the CPU clock prescaler Some ST7 devices have two on chip 16 bit timers They are completely independent and do not share any resources They are synchronized after a MCU reset as long as the timer clock frequen cies are not modified This description covers one or two 16 bit timers In ST7 devices with two timers register names are prefixed with TA Timer A or TB Timer B 12 2 2 Main Features m Programmable prescaler fopy divided by 2 4 or 8 m Overflow status flag and maskable interrupt m External clock input must be at least 4 times slowerthan the CPU clock speed with the choice of active edge m Output compare functions with 2 dedicated 16 bit registers 2 dedicated programmable signals 2 dedicated status flags 1 dedicated maskable interrupt m Input capture functions with 2 dedicated 16 bit registers 2 dedicated active edge selection signals 2 dedicated status flags 1 dedicated maskable interrupt m Pulse Width Modulation mode PWM m
25. 8 depend ing on CC 1 0 bits see Table 13 Clock Control Bits If the timer clock is an external clock the formula is OCR t fexr 5 Where t Signal or pulse period in seconds fexr External timer clock frequency in hertz The Output Compare 2 event causes the counter to be initialized to FFFCh See Figure 36 Notes 1 After a write instruction to the register the output compare function is inhibited until the register is also written 2 The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited 3 The ICF1 bit is set by hardware when the coun ter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared 4 PWM mode the ICAP1 pin not be used to perform input capture because it is discon nected from the timer The ICAP2 pin can be used to perform input capture ICF2 can be set and IC2R can be loaded but the user must take care that the counter is reset after each period and ICF1 can also generate an interrupt if ICIE is set 5 When the Pulse Width Modulation PWM and One Pulse mode OPM bits are both set the PWM mode is the only active one 53 140 ST72104G ST72215G ST72216G ST72254G 16 TIMER Cont d 12 2 4 Low Power Modes Mode Description WAIT No effect on 16 bit Timer Timer interrupts cause the device to exit from WAIT mode 16 bit Ti
26. HALT mode the I bit in the CC reg ister is forced to 0 to enable interrupts Therefore if an interrupt is pending the MCU wakes immedi ately In the HALT mode the main oscillator is turned off causing all internal processing to be stopped in cluding the operation of the on chip peripherals All peripherals are not clocked except the ones which get their clock supply from another clock generator such as an external or auxiliary oscilla tor The compatibility of Watchdog operation with HALT mode is configured by the WDGHALT op tion bit of the option byte The HALT instruction when executed while the Watchdog system is en abled can generate a Watchdog RESET see Section 16 1 OPTION BYTES on page 133 for more details Figure 19 HALT Mode Timing Overview RUN HALT HALT 4096 CPU CYCLE DELAY INSTRUCTION RESET FETCH OR VECTOR INTERRUPT 4 57721046 ST72215G ST72216G 57722546 Figure 20 HALT Mode Flow chart HALT INSTRUCTION ENABLE DISABLE OSCILLATOR OFF PERIPHERALS 2 OFF OSCILLATOR ON PERIPHERALS OFF ON 1 4096 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU BIT FETCH RESET VECTOR OR SERVICE INTERRUPT Notes 1 WDGHALT is an option bit See option byte sec tion for more details 2 Peripheral clocked with an external clock source can still be active 3 Only some specific interrupts can exit the MCU from HALT mode such as external interrupt Re fer to Ta
27. POP instruc tions In the case of an interrupt the PCL is stored at the first location pointed to by the SP Then the other registers are stored in the next locations as shown in Figure 7 When an interrupt is received the SP is decre mented and the context is pushed on the stack On return from interrupt the SP is incremented and the context is popped from the stack A subroutine call occupies two locations and an in terrupt five locations in the stack area CALL Subroutine Interrupt Event Stack Higher Address 017Fh Stack Lower Address 0100h 16 140 4 57721046 ST72215G ST72216G 57722546 7 SUPPLY RESET AND CLOCK MANAGEMENT The ST72104G ST72215G ST72216G and ST72254G microcontrollers include a range of util ity features for securing the application in critical situations for example in case of a power brown out and reducing the number of external compo nents An overview is shown in Figure 8 See Section 14 ELECTRICAL CHARACTERIS TICS on page 96 for more details Main Features m Supply Manager with main supply low voltage detection LVD m Reset Sequence Manager RSM m Multi Oscillator MO 4 Crystal Ceramic resonator oscillators 1 External RC oscillator 1 Internal RC oscillator m Clock Security System CSS Clock Filter Backup Safe Oscillator Figure 8 Clock Reset and Supply Block Diagram CLOCK SECURITY SYSTEM CSS MAIN CL
28. Port A amp C IT1 interrupt vector Port B Temperature Range 0 C to 70 C 10 C to 85 C 40 C 85 40 C to 105 C 40 C to 125 C Clock Source Selection 1 Resonator LP Low power resonator 1 to 2 MHz Medium power resonator 2 to 4 MHz 1 MS Medium speed resonator 4 to 8 MHz HS High speed resonator 8 to 16 MHz RC Network 1 Internal External External Clock Clock Security System 1 Disabled Enabled Watchdog Selection Software Activation Hardware Activation Halt when Watchdog on Reset No reset Readout Protection Disabled Enabled LVD Reset 1 Disabled Enabled Highest threshold Medium threshold Lowest threshold Comments Supply Operating Range in the application Notes Signature 4 135 140 57721046 ST72215G 57722166 ST72254G 16 3 DEVELOPMENT TOOLS STmicroelectronics offers a range of hardware STMicroelectronics Tools and software development tools for the ST7 micro Three types of development tool are offered by controller family Full details of tools available for ST all of them connect to a PC via a parallel LPT the ST7 from third party manufacturers can ob Port see Table 27 and Table 28 for more details tain from the STMicroelectronics Internet site http mcu st com Third Party Tools m ACTUM BP COSMIC CMX DATA I O HITEX HIWARE ISYSTEM KANDA LEAP Tools from these manuf
29. Read Retums the buffered At t0 At S Byte LS Byte value at t0 Sequence completed At 10 The user must read the MS Byte first then the LS Byte value is buffered automatically This buffered value remains unchanged until the 16 bit read sequence is completed even if the user reads the MS Byte several times After a complete reading sequence if only the CLR register or ACLR register are read they re turn the LS Byte of the count value at the time of the read Whatever the timer mode used input capture out put compare One Pulse mode or PWM mode an overflow occurs when the counter rolls over from FFFFh to 0000h then The TOF bit of the SR register is set A timer interrupt is generated if TOIE bit of the CR1 register is set and bit of the CC register is cleared If one of these conditions is false the interrupt re mains pending to be issued as soon as they are both true 44 140 Clearing the overflow interrupt request is done in two steps 1 Reading the SR register while the TOF bit is set 2 An access read or write to the CLR register Note The TOF bit is not cleared by accessing the ACLR register The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times for example to measure elapsed time with out the risk of clearing the TOF bit erroneously The timer i
30. SS pin of the SPI when the SSM bit is set to 1 see SPI description It is set and cleared by software Table 10 Miscellaneous Register Map and Reset Values Address Register 7 1 Hex Label 0020h MISCR1 1511 1510 1501 1500 5 5 Reset Value 0 0 0 0 0 0 0 0 MISCR2 MOD SOD SSM Reset Value 0 0 0 38 140 4 12 ON CHIP PERIPHERALS 12 1 WATCHDOG TIMER WDG 12 1 1 Introduction The Watchdog timer is used to detect the occur rence of a software fault usually generated by ex ternal interference or by unforeseen logical condi tions which causes the application program to abandon its normal sequence The Watchdog cir cuit generates an MCU reset on expiry of a pro grammed time period unless the program refresh es the counter s contents before the T6 bit be comes cleared 12 1 2 Main Features m Programmable timer 64 increments of 12288 CPU cycles m Programmable reset m Reset if watchdog activated when the T6 bit reaches zero m Optional reset on HALT configurable by option byte Hardware Watchdog selectable by option byte 12 1 3 Functional Description The counter value stored in the CR register bits 6 0 is decremented every 12 288 machine instruction Figure 25 Watchdog Block Diagram 57721046 ST72215G ST72216G ST72254G cles and the length of the timeout period can be programmed by the user in 64 increments If the watchdog is activated the WDGA
31. See note 5 in Section 12 2 3 5 One Pulse Mode on page 54 3 See note 4 in Section 12 2 3 6 Pulse Width Modulation Mode on page 56 Output Compare and or 4 54 140 16 12 2 7 Register Description Each Timer is associated with three control and status registers and with six pairs of data registers 16 bit values relating to the two input captures the two output compares the counter and the al ternate counter CONTROL REGISTER 1 CR1 Read Write Reset Value 0000 0000 00h 7 0 FOLV2 FOLV1 OLVL2 IEDG1 OLVL 1 Bit 7 ICIE nput Capture Interrupt Enable 0 Interrupt is inhibited 1 A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set Bit 6 OCIE Output Compare Interrupt Enable 0 Interrupt is inhibited 1 A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set Bit 5 TOIE Timer Overflow Interrupt Enable 0 Interrupt is inhibited 1 A timer interrupt is enabled whenever the TOF bit of the SR register is set 4 577210406 ST72215G ST72216G 57722546 Bit 4 FOLV2 Forced Output Compare 2 This bit is set and cleared by software 0 No effect on the OCMP2 pin 1 Forces the OLVL2 bit to be copied to the OCMP2 pin if the OC2E bit is set and even if there is no successful comparison Bit 3 FOLV1 Forced Output Compare 1 This bit is set and cleared by s
32. The external interrupt sensitivity is controlled by the ISxx bits of the Miscellaneous register and the OPTION BYTE This control allows having two ful ly independent external interrupt source sensitivi ties with configurable sources using EXTIT option bit as shown in Figure 23 and Figure 24 Each external interrupt source can be generated on four different events on the pin m Falling edge m Rising edge m Falling and rising edge m Falling edge and low level To guarantee correct functionality the sensitivity bits in the MISCR1 register must be modified only when the bit of the CC register is set to 1 inter rupt masked See port register and Miscella neous register descriptions for more details on the programming 11 2 O PORT ALTERNATE FUNCTIONS MISCR registers manage four I O port miscel laneous alternate functions m Main clock signal output on PC2 m SPI pin configuration SS pin internal control to use the PB7 I O port function while the SPI is active Master output capability on MOSI PB4 deactivated while the SPI is active Slave output capability on MISO PB5 de activated while the SPI is active These functions are described in detail in the Sec tion 11 3 MISCELLANEOUS REGISTER DE SCRIPTION on page 37 36 140 Figure 23 Ext Interrupt Sensitivity EXTIT 0 eid 1500 1501 INTERRUPT SOURCE SENSITIVITY CONTROL INTERRUPT SOURCE SENSITIVITY C
33. bit can be used with an interrupt in order to measure events that exceed the timer range FFFFh 4 57721046 ST72215G ST72216G 57722546 16 Figure 30 Input Capture Block Diagram Control Register 1 CR1 EDGE DETECT EDGE DETECT CIRCUIT2 CIRCUIT1 IC1R Register Status Register SR ISI 16 Control Register 2 CR2 Serm LLLI es COUNTER Figure 31 Input Capture Timing Diagram COUNTER REGISTER FFO1 FFO2 FF03 X 7 ICAPi FLAG 1 ICAPi REGISTER FFO3 Note Active edge is rising edge 4 47 140 ST72104G ST72215G ST72216G ST72254G 16 BIT Cont d 12 2 3 4 Output Compare In this section the index may be 1 or 2 because there are 2 output compare functions in the 16 bit timer This function can be used to control an output waveform or indicate when a period of time has elapsed When a match is found between the Output Com pare register and the free running counter the out put compare function Assigns pins with a programmable value if the OCIE bit is set Sets a flag in the status register Generates an interrupt if enabled Two 16 bit registers Output Compare Register 1 OC1R and Output Compare Register 2 OC2R contain the value to be compared to the counter regist
34. both counters is also FFFCh in One Pulse mode and PWM mode The timer clock depends on the clock control bits of the CR2 register as illustrated in Table 13 Clock Control Bits The value in the counter register re peats every 131 072 262 144 or 524 288 CPU clock cycles depending on the CC 1 0 bits The timer frequency can be fcpy 2 fcpu 4 fepy 8 or an external frequency 4 57721046 ST72215G ST72216G 57722546 16 Figure 26 Timer Block Diagram ST7 INTERNAL BUS MCU PERIPHERAL INTERFACE OUTPUT OUTPUT INPUT COUNTER COMPARE COMPARE CAPTURE CAPTURE REGISTER REGISTER REGISTER REGISTER REGISTER 1 2 1 2 ALTERNATE COUNTER REGISTER CC 1 0 E TIMER INTERNAL BUS 164 16 OVERFLOW DETECT OUTPUT COMPARE DETECT CIRCUIT GIRGUIT ICAP 1 Eo pin EDGE DETECT 2 CIRCUIT um LATCHI OCMP1 o o o pin Status jii SR sone OCMP2 Control Register 2 CR2 TIMER INTERRUPT Note If IC OC and TO interrupt requests have separate vectors then the last OR is not present See device Interrupt Vector Table 4 43 140 ST72104G ST72215G ST72216G ST72254G 16 BIT TIMER Cont d 16 bit Read Sequence from either the Counter Register or the Alternate Counter Register LS Byte is buffered Beginning of the sequence Read MS Byte Other y instructions Y
35. by software the sensitivity bits in the Miscellane ous register must be modified 10 2 2 Output Modes The output configuration is selected by setting the corresponding DDR register bit In this case writ ing the DR register applies this digital value to the pin through the latch Then reading the DR reg ister returns the previously stored value Two different output modes can be selected by software through the OR register Output push pull and open drain DR register value and output pin status BR Push pull Co vs V Floating 10 2 3 Alternate Functions When an on chip peripheral is configured to use a pin the alternate function is automatically select ed This alternate function takes priority over the standard I O programming When the signal is coming from an on chip periph eral the I O pin is automatically configured in out put mode push pull or open drain according to the peripheral When the signal is going to an on chip peripheral the I O pin must be configured in input mode In this case the pin state is also digitally readable by addressing the DR register Note Input pull up configuration can cause unex pected value at the input of the alternate peripheral input When an on chip peripheral use a pin as in put and output this pin has to be configured in in put floating mode ky 57721046 ST72215G ST72216G 57722546 PORTS Cont d Figure 21 1 0 Port Ge
36. can use ports for handshake lines or data bytes with com mand fields Multi master System A multi master system may also be configured by the user Transfer of master control could be im plemented using a handshake method through the ports or by an exchange of code messages through the serial peripheral interface system The multi master system is principally handled by the MSTR bit in the CR register and the MODF bit in the SR register 68 140 4 57721046 ST72215G 57722166 57722546 SERIAL PERIPHERAL INTERFACE Contd 12 3 5 Low Power Modes Mode Description WAIT No effect on SPI SPI interrupt events cause the device to exit from WAIT mode SPI registers are frozen HALT In HALT mode the SPI is inactive SPI operation resumes when the MCU is woken up by an interrupt with exit from HALT mode capability 12 3 6 Interrupts Enable Interrupt Event Bit SPI End of Transfer Event SPIF SPIE Master Mode Fault Event MODF Note The SPI interrupt events are connected to the same interrupt vector see Interrupts chapter They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset RIM instruction 69 140 ST72104G ST72215G ST72216G ST72254G SERIAL PERIPHERAL INTERFACE Cont d 12 3 7 Register Description CONTROL REGISTER CR Read Write Reset Value 0000xxxx Oxh 7 0 SPIE MSTR CPOL CPHA SPRO Bit 7 S
37. capacitors on the power supply lines are proposed as a good price vs performance tradeoff They have to be put as close as possible to the device power supply pins Other EMC recommen dations are given in other sections I Os RESET OSCx pin characteristics 113 140 4 ST72104G ST72215G ST72216G ST72254G CHARACTERISTICS Cont d 14 7 2 Absolute Electrical Sensitivity Based on three different tests ESD LU and DLU using specific measurement methods the product is stressed in order to determine its performance in terms of electrical sensitivity For more details re fer to the AN1181 ST7 application note 14 7 2 1 Electro Static Discharge ESD Electro Static Discharges 3 positive then 3 nega tive pulses separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends of the number of supply pins of the device 3 parts n 1 supply pin Two models are usually simulated Human Body Model and Machine Model This test conforms to the JESD22 A114A A115A standard See Figure 71 and the following test sequences Human Body Model Test Sequence is loaded through S1 by the HV pulse gener ator 51 switches position from generator to R discharge from C through R body resistance to the ST7 occurs 52 must be closed 10 to 100ms after the pulse delivery period to ensure the ST7 is not left in charge state S2 must be opened at least 1
38. configuration the serial clock is received on the SCK pin from the master device The value of the SPRO amp SPR1 bits is not used for the data transfer Procedure For correct data transfer the slave device must be in the same timing mode as the mas ter device CPOL and CPHA bits See Figure 40 The 55 pin must be connected to a low level signal during the complete byte transmit se quence Clear the MSTR bit and set the SPE bit to as sign the pins to alternate function In this configuration the MOSI pin is a data input and the MISO pin is a data output Transmit Sequence The data byte is parallel loaded into the 8 bit shift register from the internal bus during a write cycle and then shifted out serially to the MISO pin most significant bit first The transmit sequence begins when the slave de vice receives the clock signal and the most signifi cant bit of the data on its MOSI pin 4 577210406 ST72215G ST72216G 57722546 When data transfer is complete The 5 bit is set by hardware An interrupt is generated if SPIE bit is set and bit in CCR register is cleared During the last clock cycle the SPIF bit is set a copy of the data byte received in the shift register is moved to a buffer When the DR register is read the SPI peripheral returns this buffered value Clearing the SPIF bit is performed by the following software sequence 1 An access to the SR register while t
39. eerta eer ee Eds 14 5 2 MAIN FEATURES eon nite Gi 14 533 CPUREGISTER iratos tte d et Dome 14 6 CENTRAL PROCESSING UNIT 16 7 SUPPLY RESET AND CLOCK MANAGEMENT 17 7 1 LOW VOLTAGE DETECTOR LVD 18 72 RESET SEQUENCE MANAGER RSM 19 Introductlon se UAE 19 7 2 2 Asynchronous External RESET pin 20 7 2 3 Internal Low Voltage Detection RESET 20 7 2 4 Internal Watchdog RESET 20 7 3 MULTI OSCILLATOR MO 21 7 4 CLOCK SECURITY SYSTEM 55 22 7 4 1 Clock Filter Control 22 7 4 2 Safe Oscillator Control 22 7 4 3 Low Power Modes 22 TAA Interr pts uius E xtti ute Sy RUE ge alo Reyes tales ERU ER aa anne 22 7 5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION CRSR 23 7 6 MAIN CLOCK CONTROLLER 24 SINTERRUPTS bui eie sin E eerie E 25 81
40. in which devices may be either masters or slaves The SPI is normally used for communication be tween the microcontroller and external peripherals or another microcontroller Refer to the Pin Description chapter for the device specific pin out 12 3 2 Main Features m Full duplex three wire synchronous transfers Master or slave operation Four master mode frequencies Maximum slave mode frequency fCPU 2 Four programmable master bit rates Programmable clock polarity and phase End of transfer interrupt flag Write collision flag protection Master mode fault protection capability Figure 37 Serial Peripheral Interface Master Slave MASTER MSBit 4 LSBit SPI CLOCK GENERATOR 60 140 12 3 3 General description The SPI is connected to external devices through 4 alternate pins MISO Master In Slave Out pin MOSI Master Out Slave In pin SCK Serial Clock pin SS Slave select pin A basic example of interconnections between a single master and a single slave is illustrated on Figure 37 The MOSI pins are connected together as are MISO pins In this way data is transferred serially between master and slave most significant bit first When the master device transmits data to a slave device via MOSI pin the slave device responds by sending data to the master device via the MISO pin This implies full duplex transmission with both data out and data in synchronized with the s
41. of bytes required per instruction To do Table 19 ST7 Addressing Mode Overview Pointer Pointer Destination Length a E shot oea for No Offset Id A X 00 FF Sot FF 1 Note 1 At the time the instruction is executed the Program Counter PC points to the instruction follow ing JRxx 0 with X register 1 with Y register 90 140 ST7 ADDRESSING MODES Cont d 13 1 1 Inherent All Inherent instructions consist of a single byte The opcode fully specifies all the required informa tion for the CPU to process the operation Inherent Instruction No operation TRAP S W Interrupt Wait For Interrupt Low Power W Mode HALT Halt Oscillator Lowest Power Mode ion Function Fl RIM SCF RCF RSP LD Reset Interrupt Mask Reset Carry Flag Reset Stack Pointer Load Clea ae SHE RLC Shift Rotate Operations Swap Nibbles 13 1 2 Immediate Immediate instructions have two bytes the first byte contains the opcode the second byte con tains the operand value Load Bit Compare AND OR XOR Logical Operations ADC ADD SUB SBC Arithmetic Operations 4 57721046 ST72215G ST72216G 57722546 13 1 3 Direct In Direct instructions the operands are referenced by their memory address The direct addressing mode consists of two sub modes Direct short The address is a byte thu
42. or write of DR reg ister It is also cleared by hardware when the inter face is disabled PE 0 Following a byte transmission this bit is set after reception of the acknowledge clock pulse In case an address byte is sent this bit is set only after the EV6 event See Figure 45 BTF is cleared by reading SR1 register followed by writ ing the next byte in DR register Following a byte reception this bit is set after transmission of the acknowledge clock pulse if ACK 1 is cleared by reading SR1 register followed by reading the byte from DR register SCL line is held low while BTF 1 0 Byte transfer not done 1 Byte transfer succeeded Bit 2 ADSL Adaress matched Slave mode This bit is set by hardware as soon as the received slave address matched with the OAR register con tent or a general call is recognized An interrupt is generated if ITE 1 It is cleared by software read ing SR1 register or by hardware when the inter face is disabled PE 0 The SCL line is held low while ADSL 1 0 Address mismatched or not received 1 Received address matched 81 140 ST72104G ST72215G ST72216G ST72254G 2 BUS INTERFACE Cont d Bit 1 M SL Master Slave This bit is set by hardware as soon as the interface is in Master mode writing START 1 It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration ARLO 1 It is also cleared when the interface is disable
43. part of the value to be compared to the CHR register 7 0 ne aie OUTPUT COMPARE 2 LOW REGISTER OC2LR Read Write Reset Value 0000 0000 00h This is an 8 bit register that contains the low part of the value to be compared to the CLR register 7 0 MSB LSB COUNTER HIGH REGISTER CHR Read Only Reset Value 1111 1111 FFh This is an 8 bit register that contains the high part of the counter value 7 0 MSB LSB COUNTER LOW REGISTER CLR Read Only Reset Value 1111 1100 FCh This is an 8 bit register that contains the low part of the counter value A write to this register resets the counter An access to this register after accessing the SR register clears the TOF bit 7 0 vse 58 140 ALTERNATE COUNTER HIGH REGISTER ACHR Read Only Reset Value 1111 1111 FFh This is an 8 bit register that contains the high part of the counter value 7 0 per JE ALTERNATE COUNTER LOW REGISTER ACLR Read Only Reset Value 1111 1100 FCh This is an 8 bit register that contains the low part of the counter value A write to this register resets the counter An access to this register after an access to SR register does not clear the TOF bit in SR register 7 0 INPUT CAPTURE 2 HIGH REGISTER IC2HR Read Only Reset Value Undefined This is an 8 bit read only register that contains the high part of the counter value transferred by the Input Capture 2 event
44. register Bit 3 OCF2 Output Compare Flag 2 0 No match reset value 1 The content of the free running counter matches the content of the OC2R register To clear this bit first read the SR register then read or write the low byte of the OC2R OC2LR register Bit 2 0 Reserved forced by hardware to 0 57721046 ST72215G ST72216G 57722546 INPUT CAPTURE 1 HIGH REGISTER IC1HR Read Only Reset Value Undefined This is an 8 bit read only register that contains the high part of the counter value transferred by the input capture 1 event 7 0 per JE A INPUT CAPTURE 1 LOW REGISTER IC1LR Read Only Reset Value Undefined This is an 8 bit read only register that contains the low part of the counter value transferred by the in put capture 1 event 7 0 MSB LSB OUTPUT COMPARE 1 OC1HR Read Write Reset Value 1000 0000 80h This is an 8 bit register that contains the high part of the value to be compared to the CHR register 7 0 E LOW REGISTER HIGH REGISTER OUTPUT COMPARE 1 OC1LR Read Write Reset Value 0000 0000 00h This is an 8 bit register that contains the low part of the value to be compared to the CLR register 7 0 DESEE 57 140 ST72104G ST72215G ST72216G ST72254G 16 BIT TIMER Cont d OUTPUT COMPARE 2 HIGH REGISTER OC2HR Read Write Reset Value 1000 0000 80h This is an 8 bit register that contains the high
45. saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status Figure 16 Power Saving Mode Transitions SLOW WAIT SLOW WAIT HALT Low POWER CONSUMPTION 4 57721046 ST72215G ST72216G 57722546 9 2 SLOW MODE This mode has two targets Toreduce power consumption by decreasing the internal clock in the device To adapt the internal clock frequency fcpy to the available supply voltage SLOW mode is controlled by three bits in the MISCR 1 register the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency fep j In this mode the oscillator frequency can be divid ed by 4 8 16 or 32 instead of 2 in normal operat ing mode The CPU and peripherals are clocked at this lower frequency Note SLOW WAIT mode is activated when enter ing WAIT mode while the device is already in SLOW mode Figure 17 SLOW Mode Clock Transitions fosc 8 fopu 2 NORMAL RUN MODE NEW SLOW REQUEST FREQUENCY REQUEST 27 140 ST72104G ST72215G ST72216G ST72254G POWER SAVING MODES Contd 9 3 WAIT MODE Figure 18 WAIT Mode Flow chart WAIT mode places the MCU in a low power con OSCILLATOR ON sumption mode by stopping the CPU PERIPHERALS ON This power saving mode is selected by calling the WFI INSTRUCTION
46. sult never decreases if the analog input does not and never increases if the analog input does not If the input voltage Vam is greater than or equal to VppA high level voltage reference then the conversion result in the DR register is FFh full scale without overflow indication If input voltage Vain is lower than or equal to Vssa low level voltage reference then the con version result in the DR register is 00 The A D converter is linear and the digital result of the conversion is stored in the ADCDR register The accuracy of the conversion is described in the parametric section Rain is the maximum recommended impedance for an analog input signal If the impedance is too high this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time 12 5 3 3 A D Conversion Phases The A D conversion is based on two conversion phases as shown in Figure 2 m Sample capacitor loading duration 4 During this phase the input voltage to be measured is loaded into the sample capacitor m A D conversion duration During this phase the A D conversion is computed 8 successive approximations cycles and the Capc sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy While the ADC is on these two phases are contin uously repeated At the end of each conversion the sample capaci t
47. the EIA of 3 samples when the micro is running to assess the latch up performance in dynamic mode Power supplies are set to the typical values the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode This test conforms to the IEC1000 4 2 and SAEJ1752 3 standards and is described in Figure 72 For more details refer to the AN1181 5 7 application note JESD 78 IC latch up standard For more details refer to the 1181 ST7 application note Electrical Sensitivities Symbol 25 DLU Dynamic latch up class Vpp 5 5V fosc 4MHz 25 Figure 72 Simplified Diagram of the ESD Generator for DLU 50 0 HV RELAY DISCHARGE RETURN CONNECTION Notes 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC spec ifications that means when a device belongs to Class A it exceeds the JEDEC standard B Class strictly covers all the JEDEC criteria international standard 2 Schaffner NSG435 with a pointed test finger 4 115 140 ST72104G ST72215G ST72216G ST72254G CHARACTERISTICS Cont d 14 7 3 ESD Pin Protection Strategy To protect an integrated circuit against Electro Static Discharge the stress must be controlled to prevent degradation or destruction of the circuit el ements The stress generally affects the circuit el ements which are connected t
48. time 0 25 VIMO tcPU th MO Data output hold time 0 25 CPOL 0 CPHA 0 CPOL 1 f tsuSl thsi 4 09 en Notes 1 Data based on design simulation and or characterisation results not tested in production 2 When no communication is on going the data output line of the SPI MOSI in master mode MISO in slave mode has its alternate function capability released In this case the pin status depends on the port configuration 3 Measurement points are done at CMOS levels 0 3xVpp and 0 7xVpp 125 140 ST72104G ST72215G ST72216G ST72254G COMMUNICATION INTERFACE CHARACTERISTICS Cont d Figure 92 SPI Slave Timing Diagram with CPHA 1 dis SO MISO OUTPUT 599 6 2 Mos weur 7 BD AAA 0 CPOL 1 p cer D 1 CPOL 0 UN 55 1 CPOL 1 i SCK INPUT tw SCKH twscKL lsu MI a ELM C Lo MEE CEN E lt eX tmo tno 4 Ss Notes 1 Measurement points are done at CMOS levels 0 3xVpp and 0 7xVpp 2 When no communication is on going the data output line of the SPI MOSI in master mode MISO in slave mode has its alternate function capability released In this case the pin status depends of the
49. 0 0 ST721 4G1B10 7 ST72104G ST72215G ST ST72216G ST72254G 8 BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY ADC 16 BIT TIMERS SPI INTERFACES PRELIMINARY DATA Memories 4K or 8K bytes Program memory ROM and single voltage FLASH with read out protec tion and in situ programming remote ISP 256 bytes RAM m Clock Reset and Supply Management Enhanced reset system Enhanced low voltage supply supervisor with 3 programmable levels Clock sources crystal ceramic resonator os cillators or RC oscillators external clock backup Clock Security System Clock out capability 8 Power Saving Modes Halt Wait and Slow m Interrupt Management 7 interrupt vectors plus TRAP and RESET 22 external interrupt lines on 2 vectors m 22 1 0 Ports m Instruction Set 22 multifunctional bidirectional lines 8 bit data manipulation 14 alternate function lines 63 basic instructions 8 high sink outputs 17 main addressing modes m 3 Timers 8 x 8 unsigned multiply instruction Configurable watchdog timer True bit manipulation Two 16 bit timers with 2 input captures 2 out put compares external clock input on one tim Development Tools er PWM and Pulse generator modes one only on ST72104Gx and ST72216G1 Full hardware software development package m 2 Communications Interfaces SPI synchronous serial interface 126 multimaster interfa
50. 0000 0000 00h 7 0 D7 D6 D5 D4 D3 D2 D1 DO Bits 7 0 D 7 0 Analog Converted Value This register contains the converted analog value in the range 00 to FFh Note Reading this register reset the COCO flag 4 57721046 ST72215G ST72216G 57722546 8 BIT A D CONVERTER ADC Table 18 ADC Register Map and Reset Values Address Register 7 1 Hex Label ADCDR D7 D5 D4 D3 D2 D1 0071h ADCCSR COCO ADON CH3 CH2 CH1 CHO Reset Value 0 0 0 0 0 0 4 89 140 57721046 ST72215G 57722166 ST72254G 13 INSTRUCTION SET 13 1 ST7 ADDRESSING MODES So most of the addressing modes may be subdi i i lled I hort The ST7 Core features 17 different addressing vided ovo SUb modes caled long and snor modes which can be classified in 7 main groups Long addressing mode is more powerful be cause it can use the full 64 Kbyte address space Addressing Mode si however it uses more bytes and more CPU cy Short addressing mode is less powerful because it can generally only access page zero 0000h OOFFh range but the instruction size is more compact and faster All memory to memory in Indi structions use short addressing modes only 8551 CLR CPL NEG BSET BRES BTJT BTJF INC DEC RLC RRC SLL SRL SRA SWAP The ST7 Assembler optimizes the use of long and short addressing modes The ST7 Instruction set is designed to minimize the number
51. 00MG06 CSTCC4 00MG0H6 CSTS0400MG06 CSTCC4 00MG0H6 CSTS0800MG06 CSTCC8 00MG0H6 CSTS0800MG06 CSTCC8 00MG0H6 CSTS1000MGO03 15 15 Notes 1 Murata Ceralock refer to Table 23 for correlation factor 2 Vbpp 4 5 to 5 5V 3 Values in parentheses refer to the capacitors integrated in the resonator 4 107 140 ST72104G ST72215G ST72216G ST72254G CLOCK AND TIMING CHARACTERISTICS Cont d Table 22 Typical Ceramic Resonators for Automotive Applications Option Byte fosc Rrext Rp Config MHz 5 50200 06 5 2 00 6 CSTS0200MGA06 5 2 00 6 5 50400 06 5 4 00 6 CSTS0400MGA06 5 4 00 6 CSTSO800MGA06 5 8 00 6 CSTSO800MGA06 CSTCC8 00MGA0H6 CSTS1000MGA03 CSTCC10 0MGA CST12 0MTWA CSTCS12 0MTA 1 47 4 Open L2 00 7 15 Notes 1 Murata Ceralock refer to Table 23 for correlation factor 2 4 5 5 5V 3 Values in parentheses refer to the capacitors integrated in the resonator Figure 65 Typical Application with Ceramic Resonator WHEN RESONATOR WITH INTEGRATED CAPACITORS Notes 1 Resonator characteristics given by the ceramic resonator manufacturer 2 tsu oso the typical oscillator start up time measured between Vpp 2 8V and the fetch of the first instruction with a quick Vpp ramp up from 0 to 5V 50us 3 The oscillator
52. 0ms prior to the delivery of the next pulse Absolute Maximum Ratings Machine Model Test Sequence C is loaded through S1 by the HV pulse gener ator 61 switches position from generator to ST7 A discharge from C to the ST7 occurs S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST7 is not left in charge state S2 must be opened at least 10ms prior to the delivery of the next pulse R machine resistance in series with S2 en sures a slow discharge of the ST7 Symb axiom vat T Unt Electro static discharge voltage Human Body Model Taste ee 2000 static ur voltage Figure 71 Typical Equivalent ESD Circuits HIGH VOLTAGE PULSE 100pF GENERATOR Pid HUMAN BODY MODEL Notes HIGH VOLTAGE PULSE GENERATOR 200 MACHINE MODEL 1 Data based on characterization results not tested in production 114 140 4 57721046 ST72215G ST72216G 57722546 CHARACTERISTICS Cont d 14 7 2 2 Static and Dynamic Latch Up m LU 3 complementary static tests are required m DLU Electro Static Discharges one positive then one negative test are applied to each pin on 10 parts to assess the latch up performance A supply overvoltage applied to each power supply pin a current injection applied to each input output and configurable pin and a power supply switch sequence are performed on each sample This test conforms to
53. 104G ST72215G ST72216G 57722549 RESET SEQUENCE MANAGER Cont d 7 2 2 Asynchronous External RESET pin The RESET pin is both an input and an open drain output with integrated Roy weak pull up resistor This pull up has no fixed value but varies in ac cordance with the input voltage It can be pulled low by external circuitry to reset the device See electrical characteristics section for more details A RESET signal originating from an external source must have a duration of at least tn sr ji in order to be recognized This detection is asynchro nous and therefore the MCU can enter reset state even in HALT mode The RESET pin is an asynchronous signal which plays a major role in EMS performance In a noisy environment it is recommended to follow the guidelines mentioned in the electrical characteris tics section Two RESET sequences can be associated with this RESET source short or long external reset pulse see Figure 12 Starting from the external RESET pulse recogni tion the device RESET pin acts as an output that is pulled low during at least tw RSTL out Figure 12 RESET Sequences SHO R RT EXT ESET Y DELA th RSTL int EXTERNAL WATCHDOG RESET 20 140 7 2 3 Internal Low Voltage Detection RESET Two different RESET sequences caused by the in ternal LVD circuitry can be distinguished m Power On RESET m Voltage Drop RESET The device RESET pin acts as an output that is pul
54. 12 140 57721046 ST72215G ST72216G 57722546 14 7 CHARACTERISTICS Susceptibility tests are performed sample ba m ESD Electro Static Discharge positive and sis during product characterization negative is applied on all pins of the device until 14 7 1 Functional EMS a functional disturbance occurs This test conforms with the IEC 1000 4 2 standard Eleetro Magneue Suscepubility m FTB A Burst of Fast Transient voltage positive Based on a simple running application on the and negative is applied to Vpp and Vgs through product toggling 2 LEDs through I O ports the 100pF capacitor until a functional disturbance product is stressed by two electro magnetic events occurs This test conforms with the IEC 1000 4 until a failure occurs indicated by the LEDs 4 standard A device reset allows normal operations to be re sumed Symbol Paametr Conditions V Voltage limits to be applied on any NC DEREN pin Vpp 5V EU o EMI fosc 8MHz FESD to induce a functional disturbance conforms to IEC 1000 4 2 Fast transient voltage burst limits to be ap plied through 100pF on Vpp and Vpp pins to induce a functional disturbance Vpp 5V 25 fosc 8MHz conforms to IEC 1000 4 4 ST72XXX ST7 DIGITAL NOISE FILTERING SUPPLY SOURCE NOISE 1 FILTERING _ Notes 1 Data based on characterization results not tested in production 2 The suggested and 0 1uF decoupling
55. 2 5 3Functional Description 86 3 140 Table of Contents 12 5 4Low Power Modes 87 12 5 5Interr pts E eter oen den e eR RR e 87 12 56 Register Description i ke ge Eee du n BR 88 13 INSTRUCTION SET da eR lare 90 13 1 ST7 ADDRESSING MODES 90 T3 T TInherent ER Rice Re DRE des e es 91 13 1 2Immediate irse t 91 19 1 BS DIPS Ct le css ese ig tote edu s pre Pde 91 13 1 41 No Offset Short Long 91 13 1 5Indirect Short Long 91 13 1 6Indirect Indexed Short Long 92 13 1 7Relative Mode Direct Indirect 92 13 2 INSTRUCTION GROUPS 232 4 nd gue dex Rex 93 14 ELECTRICAL CHARACTERISTICS 96 14 4 PARAMETER CONDITIONS 96 14 1 1 Minimum and Maximum values 96 14 1 2Typical values o cei nena a iaa S E Syd riu ee 96 14 1 3Typlcal CULVOS d
56. 22546 7 5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION CRSR Read Write Reset Value 000x 000x XXh 7 0 LVD CSS CSS WDG PM NS RE Bit 7 5 Reserved always read as 0 Bit 4 LVDRF LVD reset flag This bit indicates that the last RESET was gener ated by the LVD block It is set by hardware LVD reset and cleared by software writing zero See WDGRHEF flag description for more details When the LVD is disabled by option byte the LVDRF bit value is undefined Bit 3 Reserved always read as 0 Bit 2 CSSIE Clock security syst interrupt enable This bit enables the interrupt when a disturbance is detected by the clock security system CSSD bit Set It is set and cleared by software 0 Clock security system interrupt disabled 1 Clock security system interrupt enabled Refer to Table 5 Interrupt Mapping on page 26 for more details on the CSS interrupt vector When the CSS is disabled by option byte the CSSIE bit has no effect Bit 1 CSSD Clock security system detection This bit indicates that the safe oscillator of the clock security system block has been selected by hardware due to a disturbance on the main clock signal fosc It is set by hardware and cleared by reading the CRSR register when the original oscil lator recovers 0 Safe oscillator is not active 1 Safe oscillator has been activated When the CSS is disabled by option byte the CSSD bit value is forc
57. 28 1 27 04 SO28 ENPLAS OTS28312704 OpenTop YAMAICHI 51 0282 334 1 Clamshell EMU PROBE Adapter from SO28 to SDIP32 footprint delivered with emulator SMD to SDIP ky 137 140 ST72104G ST72215G ST72216G ST72254G 16 4 ST7 APPLICATION NOTES PROGRAMMING AND TOOLS PROGRAMMING AND TOOLS EXECUTING CODE IN ST7 RAM USING THE ST7 INDIRECT ADDRESSING MODE IN CIRCUIT PROGRAMMING STARTING WITH ST7 ASSEMBLY TOOL CHAIN STARTING WITH ST7 HIWARE C 106 965 ANSTO ANST2 ANS73 AN974 976 ANTS ANGE ANT017 ANTO ANT042 ANTO44 ANTOAS 046 047 ANT048 ANT082 ANT083 ANTI29 ANTZO ANT148 149 ANTT80 ANTIB2 982 014 ANTO7O ANTITO ANS1 ANGOO ANTOGS 1150 16 5 MORE INFORMATION To get the latest information on this product please use the ST web server http mcu st com 138 140 4 57721046 ST72215G ST72216G 57722546 17 SUMMARY CHANGES Description of the changes between the current release of the specification and the previous one charges 9m 2 6 Added one temperature range 10 C to 85 C Nov 00 4 139 140 ST72104G ST72215G ST72216G 57722549 Notes Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other righ
58. 54G Multisupply Configuration When several types of ground Vss and power supply Vpp are available for any reason better noise immunity the structure shown in Figure 77 is implemented to protect the device against ESD Figure 75 Positive Stress on a True Open Drain Pad vs Vss Main path m e Path to avoid o Main path Figure 77 Multisupply Configuration E BACK BACK DIODE BETWEEN GROUNDS 4 117 140 ST72104G ST72215G ST72216G ST72254G 14 8 I O PORT PIN CHARACTERISTICS 14 8 1 General Characteristics Subject to general operating conditions for Vpp fosc and T4 unless otherwise specified Static current consumption Floating input mode L S Weak pull up equivalent resistor 5 pin capacitance O 500F External interrupt pulse time Figure 78 Two typical Applications with unused I O Pin ST72XXX UNUSED I O PORT UNUSED PORT ST72XXX Figure 79 Typical vs Vpp with Vinj Vss Ipu uA 70 60 1 50 40 30 vdd V Notes 1 Unless otherwise specified typical data are based on 25 and Vpp 5V 2 Data based on characterization results not tested in production 3 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested 4 Configuration not recommended all unused pins must be kept at a fixed voltage using the output mode of t
59. 5G ST72216G 57722546 SERIAL PERIPHERAL INTERFACE Cont d Figure 40 Data Clock Timing Diagram SCLK with CPOL 1 SCLK with CPOL 0 Note This figure should not be used as a replacement for parametric information Refer to the Electrical Characteristics chapter VR02131B ky 65 140 ST72104G ST72215G ST72216G ST72254G SERIAL PERIPHERAL INTERFACE Cont d 12 3 4 4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is tak ing place with an external device When this hap pens the transfer continues uninterrupted and the software write will be unsuccessful Write collisions can occur both in master and slave mode Note a read collision will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU oper ation In Slave mode When the CPHA bit is set The slave device will receive a clock SCK edge prior to the latch of the first data transfer This first clock edge will freeze the data in the slave device DR register and output the MSBit on to the exter nal MISO pin of the slave device The SS pin low state enables the slave device but the output of the MSBit onto the MISO pin does not take place until the first data transfer clock edge When the CPHA bit is reset Data is latched on the occurrence of the first clock transition The slave device does not have any way
60. 72215G ST72216G ST72254G This mode needs five signals plus the Vpp signal if necessary to be connected to the programming tool This signals are RESET device reset Vss device ground power supply ISPCLK ISP output serial clock pin ISPDATA ISP input serial data pin SPSEL Remote ISP mode selection This pin must be connected to on the application board through a pull down resistor If any of these pins are used for other purposes on the application a serial resistor has to be imple mented to avoid a conflict if the other device forces the signal level Figure 5 shows a typical hardware interface to a standard ST7 programming tool For more details on the pin locations refer to the device pinout de scription Figure 5 Typical Remote ISP Interface HE10 CONNECTOR TYPE TO PROGRAMMING TOOL ISPDATA m L APPLICATION 4 5 MEMORY READ OUT PROTECTION The read out protection is enabled through an op tion bit For FLASH devices when this option is selected the program and data stored in the FLASH memo ry are protected against read out piracy including a re write protection When this protection option is removed the entire FLASH program memory is first automatically erased However the data memory when available be protected only with ROM devices 13 140 ST72104G ST72215G ST72216G ST72254G 5 CENTRAL PROCESSING UNIT 5 1 INTRODUCTION Accumulator A This CP
61. Asynchronous RESET Pin Subject to general operating conditions for Vpp fosc and T4 unless otherwise specified mb Fames Mm 7 He Ua merat sees 89 Output low level voltage 5 068 0 95 V Vpp 5V V Vpp 5V 20 40 RE OST External pin or 6 1 f twiRSTL out Generated reset pulse duration anal ee BENE XE uc Figure 86 Typical Application with RESET pin 9 INTERNAL RESET CONTROL USER EXTERNAL RESET CIRCUIT 9 WATCHDOG RESET LVD RESET Notes 1 Unless otherwise specified typical data are based on 25 and Vpp 5V 2 Data based on characterization results not tested in production 3 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested 4 The current sunk must always respect the absolute maximum rating specified in Section 14 2 2 and the sum of lio ports and control pins must not exceed lyss 5 The Roy pull up equivalent resistor is based on a resistive transistor corresponding loy current characteristics de scribed in Figure 87 This data is based on characterization results not tested in production 6 To guarantee the reset of the device a minimum pulse has to be applied to RESET pin All short pulses applied on RESET pin with a duration below th RsTL in can be ignored 7 The reset network th
62. BIT A D CONVERTER ADC 12 5 1 Introduction The on chip Analog to Digital Converter ADC pe ripheral is a 8 bit successive approximation con verter with internal sample and hold circuitry This peripheral has up to 16 multiplexed analog input channels refer to device pin out description that allow the peripheral to convert the analog voltage levels from up to 16 different sources The result of the conversion is stored in a 8 bit Data Register The A D converter is controlled through a Control Status Register 12 5 2 Main Features m 8 bit conversion Up to 16 channels with multiplexed input Linear successive approximation Data register DR which contains the results Conversion complete status flag m On off bit to reduce consumption The block diagram is shown in Figure 1 Figure 47 ADC Block Diagram 86 140 12 5 3 Functional Description 12 5 3 1 Analog Power Supply VppA Vas are the high and low level refer ence voltage pins In some devices refer to device pin out description they are internally connected to the Vpp and Vss pins Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines See electrical characteristics section for more de tails ANALOG TO DIGITAL CONVERTER 4 8 A D CONVERTER ADC 12 5 3 2 Digital A D Conversion Result The conversion is monotonic meaning that the re
63. CPU OFF WFI ST7 software instruction BIT 0 All peripherals remain active During WAIT mode the bit of the CC register is forced to 0 to enable all interrupts All other registers and memory re main unchanged The MCU remains in WAIT mode until an interrupt or Reset occurs whereup on the Program Counter branches to the starting address of the interrupt or Reset service routine The MCU will remain in WAIT mode until a Reset or an Interrupt occurs causing it to wake up i OSCILLATOR ON Refer to Figure 18 PERIPHERALS OFF ON 1 OSCILLATOR PERIPHERALS FETCH RESET VECTOR OR SERVICE INTERRUPT Note 1 Before servicing an interrupt the CC register is pushed on the stack The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped 4 28 140 POWER SAVING MODES Contd 9 4 HALT MODE The HALT mode is the lowest power consumption mode of the MCU It is entered by executing the ST7 HALT instruction see Figure 20 The MCU can exit HALT mode on reception of ei ther a specific interrupt see Table 5 Interrupt Mapping on page 26 or a RESET When exiting HALT mode by means of a RESET or an interrupt the oscillator is immediately turned on and the 4096 CPU cycle delay is used to stabilize the os cillator After the start up delay the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up see Figure 19 When entering
64. CU is in reset state when the internal reset signal is high When it is low the MCU is running 4 45 140 ST72104G ST72215G ST72216G ST72254G 16 BIT TIMER Cont d 12 2 3 3 Input Capture In this section the index may be 1 or 2 because there are 2 input capture functions in the 16 bit timer The two input capture 16 bit registers IC1R and IC2R are used to latch the value of the free run ning counter after a transition is detected by the pin see figure 5 MS Byte LS Byte ICiR register is a read only register The active transition is software programmable through the IEDG bit of Control Registers Timing resolution is one count of the free running counter fcpu CC 1 0 Procedure To use the input capture function select the fol lowing in the CR2 register Select the timer clock CC 1 0 see Table 13 Clock Control Bits Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit the ICAP2 pin must be configured as a floating input And select the following in the CR1 register Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit the ICAP1pin must be configured as a floating input 46 140 When an input capture occurs The ICFi bit is set
65. ICATION INTERFACE CHARACTERISTICS 125 14 11 1SPI Serial Peripheral 125 14 11 212C Inter IC Control Interface 127 14 12 8 BIT ADC CHARACTERISTICS 128 15 PACKAGE CHARACTERISTICS 130 15 1 PACKAGE MECHANICAL DATA 130 15 2 THERMAL CHARACTERISTICS 131 15 3 SOLDERING AND 132 16 DEVICE CONFIGURATION AND ORDERING INFORMATION 133 161 OPTION BYTES de RET BOA een ghee 133 16 2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE 134 16 3 DEVELOPMENT TOOLS 136 16 3 1 PACKAGE SOCKET FOOTPRINT PROPOSAL 137 16 4 ST7 APPLICATION NOTES 4 or eer MM 138 165 TO GET MORE INFORMATION 138 17 SUMMARY OF CHANGES 139 5 140 ST72104G ST72215G 57722166 ST72254G 1 INTRODUCTION The ST72104G ST72215G ST72216G and ST72254G devices are members of the ST7 mi crocontroller family They can be grouped as fol lows ST72254G devi
66. LTERNATE FUNCTIONS 36 11 3 MISCELLANEOUS REGISTER DESCRIPTION 37 12 ON CHIP PERIPHERALS ocara ata sae cee 2 2 1 eee eee 39 12 1 WATCHDOG TIMER WDG 39 12 1 1Introduction 39 12 1 2 Features 2 4 ber 39 12 1 3Functional Description 39 12 1 4Hardware Watchdog Option 40 12 1 5Low Power Modes 40 T2ct 6lnterr pts eraot E ads 40 12 1 7Register 40 12 2 16 BIT TIMER oe see ne db De ete xis doe desde ede eta d 42 12 2 MIntroductiony iss ene eed 42 12 2 2MainFeatut s Bhan qued tee ERR a 42 12 2 3Functional Description 42 12 2 4Low Power Modes Ju 54 12 2 5Interr ptS eiea em Be 54 12 2 68ummary of Timer modes 54 12 2 7Register 1 55 12 3 SERIAL PERIPHERAL INTERFACE
67. Master mode A 9th clock pulse follows the 8 clock cycles of a byte transfer during which the receiver must send an acknowledge bit to the transmitter Refer to Fig ure 43 CONDITION VR02119B 73 140 ST72104G ST72215G ST72216G ST72254G BUS INTERFACE Cont d Acknowledge may be enabled and disabled by The SCL frequency is controlled by a pro software grammable clock divider which depends on the The IC interface address and or general ad bus mode dress can be selected by software When the IC cell is enabled the SDA and SCL The speed of the 12C interface may be selected ports must be configured as floating inputs In this between Standard 0 100KHz and Fast IC 100 the value of the external pull up resistor 400 2 used depends on the application When the 2 cell is disabled the SDA and SCL ins SDA SCL Line Control ports revert to being standard port pins Transmitter mode the interface holds the clock line low before transmission to wait for the micro controller to write the byte in the Data Register Receiver mode the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register Figure 44 Interface Block Diagram DATA REGISTER DR SDA or SDAI DATA CONTROL L DATA SHIFT REGISTER COMPARATOR OWN ADDRESS REGISTER 1 OAR1 OWN ADDRESS REGISTER 2 OA
68. OCK CONTROLLER MCO MULTI OSCILLATOR MO CLOCK fopu FILTER RESET SEQUENCE MANAGER FROM WATCHDOG RSM PERIPHERAL LOW VOLTAGE vo DETECTOR CSS INTERRUPT 17 140 4 ST72104G ST72215G ST72216G ST72254G 7 1 LOW VOLTAGE DETECTOR LVD To allow the integration of power management features in the application the Low Voltage Detec tor function LVD generates a static reset when the Vpp supply voltage is below reference value This means that it secures the power up as well as the power down keeping the ST7 in reset The Vir reference value for a voltage drop is lower than the Vir reference value for power on in order to avoid a parasitic reset when the MCU starts run ning and sinks current on the supply hysteresis The LVD Reset circuitry generates a reset when Vpp is below when Vpp is rising when Vpp is falling The LVD function is illustrated in the Figure 9 Provided the minimum Vpp value guaranteed for the oscillator frequency is above Vir the MCU can only be in two modes under full software control in static safe reset Figure 9 Low Voltage Detector vs Reset In these conditions secure operation is always en sured for the application without the need for ex ternal reset hardware During a Low Voltage Detector Reset the RESET pin is held low thus permitting the MCU to reset other devices Notes 1 The LVD allows the dev
69. ONTROL Figure 24 Ext Interrupt Sensitivity 1 ISCR1 INTERRUPT SOURCE SENSITIVITY CONTROL ISCR1 INTERRUPT SOURCE SENSITIVITY CONTROL 4 MISCELLANEOUS REGISTERS Cont d 11 3 MISCELLANEOUS REGISTER DESCRIPTION MISCELLANEOUS REGISTER 1 MISCR1 Read Write Reset Value 0000 0000 00h 7 0 s 1510 1501 1500 CP1 svs Bit 7 6 IS1 1 0 eif sensitivity The interrupt sensitivity defined using the 151 1 0 bits is applied to the ei1 external interrupts These two bits can be written only when the bit of the CC register is set to 1 interrupt masked ei1 Port B C optional External Interrupt Sensitivity IS11 1510 Falling edge amp low level ojo Cisna edeo fofa FFalingedge ony Bit 5 Main clock out selection This bit enables the MCO alternate function on the PC2 I O port It is set and cleared by software 0 MCO alternate function disabled 1 pin free for general purpose I O 1 MCO alternate function enabled on I O port Bit 4 3 ISO 1 0 e 0 sensitivity The interrupt sensitivity defined using the ISO 1 0 bits is applied to the ei0 external interrupts These two bits can be written only when the bit of the CC register is set to 1 interrupt masked ei0 Port A C optional Falling edge only Rising and falling edge 4 57721046 ST72215G ST72216G 57722546 Bit 2 1 CP 1 0 CPU clock presc
70. One Pulse mode m 5alternate functions on I O ports ICAP1 ICAP2 OCMP1 OCMP2 EXTCLK The Block Diagram is shown in Figure 26 Note Some timer pins may not be available not bonded in some ST7 devices Refer to the device pin out description When reading an input signal on a non bonded pin the value will always be 1 42 140 12 2 3 Functional Description 12 2 3 1 Counter The main block of the Programmable Timer is a 16 bit free running upcounter and its associated 16 bit registers The 16 bit registers are made up of two 8 bit registers called high amp low Counter Register CR Counter High Register CHR is the most sig nificant byte MS Byte Counter Low Register CLR is the least sig nificant byte LS Byte Alternate Counter Register ACR Alternate Counter High Register ACHR is the most significant byte MS Byte Alternate Counter Low Register ACLR is the least significant byte LS Byte These two read only 16 bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit Timer overflow flag located in the Status register SR See note at the end of paragraph titled 16 bit read sequence Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value Both counters have a reset value of FFFCh this is the only value which is reloaded in the 16 bit tim er The reset value of
71. PIE Serial peripheral interrupt enable This bit is set and cleared by software 0 Interrupt is inhibited 1 An SPI interrupt is generated whenever SPIF 1 or MODF 1 in the SR register Bit 6 Serial peripheral output enable This bit is set and cleared by software It is also cleared by hardware when in master mode 55 0 see Section 12 3 4 5 Master Mode Fault on page 70 0 I O port connected to pins 1 SPI alternate functions connected to pins The SPE bit is cleared by reset so the SPI periph eral is not initially connected to the external pins Bit 5 SPR2 Divider Enable this bit is set and cleared by software and it is cleared by reset It is used with the SPR 1 0 bits to Set the baud rate Refer to Table 15 0 Divider by 2 enabled 1 Divider by 2 disabled Bit 4 MSTR Master This bit is set and cleared by software It is also cleared by hardware when in master mode 55 0 see Section 12 3 4 5 Master Mode Fault on page 70 0 Slave mode is selected 1 Master mode is selected the function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are re versed 70 140 Bit 3 CPOL Clock polarity This bit is set and cleared by software This bit de termines the steady state of the serial Clock The CPOL bit affects both the master and slave modes 0 The steady state is a low value at the SCK pin 1 The steady state is a high value at the SCK pin
72. R2 SCL or SCLI CLOCK CONTROL CLOCK CONTROL REGISTER CCR CONTROL REGISTER CR STATUS REGISTER 1 SR1 2 CONTROL LOGIC STATUS REGISTER 2 SR2 v INTERRUPT 4 74 140 BUS INTERFACE Cont d 12 4 4 Functional Description Refer to the CR SR1 and SR2 registers in Section 12 4 7 for the bit definitions By default the 2 interface operates in Slave mode M SL bit is cleared except when it initiates a transmit or receive sequence First the interface frequency must be configured using the FRi bits in the OAR2 register 12 4 4 1 Slave Mode As soon as a start condition is detected the address is received from the SDA line and sent to the shift register then it is compared with the address of the interface or the General Call address if selected by software Note In 10 bit addressing mode the comparision includes the header sequence 11110xx0 and the two most significant bits of the address Header matched 10 bit mode only the interface generates an acknowledge pulse if the ACK bit is set Address not matched the interface ignores it and waits for another Start condition Address matched the interface generates in se quence Acknowledge pulse if the ACK bit is set EVF and ADSL bits are set with an interrupt if the ITE bit is set Then the interface waits for a read of the SR1 reg ister holding the SCL line low see Figure 45 Transfer sequencing 1 N
73. RAM COUNTER RESET VALUE RESET VECTOR FFFEh FFFFh 7 0 2 CONDITION CODE REGISTER RESET VALUE 1 1 1 X 1 X X X 15 817 0 STACK POINTER RESET VALUE STACK HIGHER ADDRESS Undefined Value 4 14 140 CPU REGISTERS CONDITION CODE REGISTER CC Read Write Reset Value 111x1xxx The 8 bit Condition Code register contains the in terrupt mask and four flags representative of the result of the instruction just executed This register can also be handled by the PUSH and POP in structions These bits can be individually tested and or con trolled by specific instructions Bit 4 Half carry This bit is set by hardware when a carry occurs be tween bits 3 and 4 of the ALU during an ADD or ADC instruction It is reset by hardware during the same instructions 0 No half carry has occurred 1 A half carry has occurred This bit is tested using the JRH or JRNH instruc tion The H bit is useful in BCD arithmetic subrou tines Bit 3 nterrupt mask This bit is set by hardware when entering in inter rupt or by software to disable all interrupts except the TRAP software interrupt This bit is cleared by software 0 Interrupts are enabled 1 Interrupts are disabled This bit is controlled by the RIM SIM and IRET in structions and is tested by the JRM and JRNM in structions Note Interrupts requested while is set are latched and be processed when
74. RISTICS Subject to general operating conditions for Vpp fosc and T4 unless otherwise specified Van Conversion range vofage Vs Yoon V Stabilization time after ADC enable Conversion time Sample Hold tapc Sample capacitor loading time Hold conversion time Figure 95 Typical Application with ADC fcpu 8M Hz fapc 4M Hz ST72XXX Notes 1 Unless otherwise specified typical data are based on 25 and Vpp Vgg 5V They are given only as design guide lines and are not tested 2 When and Vgga pins are not available on the pinout the ADC refer to Vpp and Vgg 3 Any added external serial resistor will downgrade the ADC accuracy especially for resistance greater than 10kQ Data based on characterization results not tested in production 4 The stabilization time of the AD converter is masked by the first The first conversion after the enable is then always valid 4 128 140 57721046 ST72215G ST72216G 57722546 8 CHARACTERISTICS Accuracy Vpp 5V 2 Vpp 5 0V Vpp 3 3V 3 Symbol Parameter fcpu 1MHz fcpu 8MHz fcpu 8MHz efi osem Diferentalineartrenar 15 integral inearireror 18 1125 Figure 96 ADC Accuracy Characteristics Digital Result ADCDR 1 Example of an actual transfer curv
75. S and LVD disabled 4 SLOW mode selected with based on fosc divided by 32 All I O pins in input mode with a static value Vpp or lock Vss no load all peripherals in reset state 102 140 nput OSC1 driven by external square wave CSS and LVD disabled ky 57721046 ST72215G ST72216G 57722546 SUPPLY CURRENT CHARACTERISTICS Cont d 14 4 2 WAIT and SLOW WAIT Modes fosc 1 MHz fcpu 500kHz fosc 4MHz fcpu 2MHz fosc 1 6MHz 8 2 fosc 1 MHz fcpy 31 25kHz fosc 4MHz 125 2 fosc 1 6MHz fcpu 500kHz fosc 1 MHz fcpu 500kHz fosc 4MHz fcpy 2MHz fosc 1 6MHz fcpy 8MHz fosc 1 MHz fcpy 31 25kHz fosc 4MHz fopy 125kHz fosc 1 6MHz fcopy 500kHz Supply current WAIT mode 3 see Figure 61 Supply current in SLOW WAIT mode 4 see Figure 62 Supply current WAIT mode 3 see Figure 61 Supply current in SLOW WAIT mode see Figure 62 3 2 lt lt 3 6 4 5 lt lt 5 5 Figure 61 Typical Ipp in WAIT vs IDD mA 8MHz 2MHz 4 5 4 5 VDD V VDD V Notes 1 Typical data are based on 25 Vpp 5V 4 5VsVppx5 5V range and Vpp 3 4V 3 2 lt lt 3 6 range 2 Data based on characterization results tested in production at Vpp max and max 3 All I O pins in input mode with a static value at Vpp or no load all peripherals in reset state clock input OSC1 driven by external s
76. S pin pulled low then the MODF bit is set Master mode fault affects the SPI peripheral in the following ways The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set The SPE bit is reset This blocks all output from the device and disables the SPI periph eral The MSTR bit is reset thus forcing the device into slave mode Clearing the MODF bit is done through a software sequence 1 A read or write access to the SR register while the MODF bit is set 2 A write to the CR register Notes To avoid any multiple slave conflicts in the case of a system comprising several MCUs the SS pin must be pulled high during the clearing se quence of the MODF bit The SPE and MSTR bits 4 57721046 ST72215G ST72216G 57722546 be restored to their original state during or af ter this clearing sequence Hardware does not allow the user to set the SPE and bits while the bit is set except in the bit clearing sequence In a slave device the MODF bit can not be set but in a multi master configuration the device can be in slave mode with this MODF bit set The bit indicates that there might have been a multi master conflict for system control and allows a proper exit from system operation to a re Set or default system state using an interrupt rou tine 12 3 4 6 Overrun Condition An overrun condition occurs when the master de vice has sent severa
77. SPI 60 12 9 TIntrod ction Roues bm d beste e oe nd ble ete ess 60 12 3 2 rte pa Pues e pde e xd 60 12 3 3General description zie ceguera DEEP endis 60 12 3 4Functional Description 62 12 3 5bow Power Modos ine of ve Se die ees DP T EI A 69 12 3 6lrniterupts n ae EIU aay 69 12 3 7Register 70 12 4 l2G BUS INTERFAGE 126 RE a eis peer HEM 73 Introduction 5 s Ce EROS DEUS m dnd 73 12 4 2 Features gt 22 eR EE UE uiu d ROV IO EU LEES 73 12 4 3General Description 73 12 4 4Functional Description 75 12 4 5Low Power Modes 79 12 4 6Interr pts hike ond Ma ents oh EE 79 12 4 7Register 80 12 5 8 BIT A D CONVERTER ADC 86 12 5 1Introduction Pe Vee 86 12 5 2 5 x ctor ope dote Kaela deuce RI ROC 86 1
78. T mode the 2 interface is inactive and does not acknowledge data on the bus The 2 interface resumes operation when the MCU is woken up by an interrupt with exit from HALT mode capability 12 4 6 Interrupts Figure 46 Event Flags and Interrupt Generation INTERRUPT EVF can also be set by EV6 or an error from the 582 register Interrupt Event Control Bit 10 bit Address Sent Event Master mode End of Byte Transfer Event BTF Address Matched Event Slave mode Start Bit Generation Event Master mode Acknowledge Failure Event Arbitration Lost Event Multimaster configuration ARLO Bus Error Event BERR Note The 2 interrupt events are connected to the same interrupt vector see Interrupts chapter They generate an interrupt if the corresponding Enable Control Bit is set and the I bit in the CC reg ister is reset RIM instruction 79 140 ST72104G ST72215G 57722166 ST72254G I C BUS INTERFACE Cont d 12 4 7 Register Description I C CONTROL REGISTER CR Read Write Reset Value 0000 0000 00h 7 0 Bit 7 6 Reserved Forced to 0 by hardware Bit 5 PE Peripheral enable This bit is set and cleared by software 0 Peripheral disabled 1 Master Slave capability Notes When 0 all the bits of the CR register and the SR register except the Stop bit are reset All outputs are released while 0 When PE 1 the corresponding I O pins are se lected by hardware as al
79. T72254G INTERRUPTS Cont d Figure 15 Interrupt Processing Flowchart FROM RESET STACK PC X A CC SET I BIT LOAD PC FROM INTERRUPT VECTOR EXECUTE INSTRUCTION Table 5 Interrupt Mapping Source Register Priority Address _ 4 Highest E N A por CRSR 0 External Interrupt Port A7 0 C5 0 1 External Interrupt Port B7 0 C5 0 2 CSS Clock Security System Interrupt CRSR f Pi SPI Peripheral Interrupts Priority FFFCh FFFDh FFFAh FFFBh yes no TIMERA TIMER A Peripheral Interrupts PS Notes 7 OSPF 6 TMERB TIMER B Peripheral merups FFEERFFEFh 7 m Not Used Lowest ME is Ma C 1 Configurable by option byte n FFE4h FFES5h FFE2h FFE3h FFEOh FFE1h 4 26 140 9 POWER SAVING MODES 9 1 INTRODUCTION To give a large measure of flexibility to the applica tion in terms of power consumption three main power saving modes are implemented in the ST7 see Figure 16 After a RESET the normal operating mode is se lected by default RUN mode This mode drives the device CPU and embedded peripherals by means of a master clock which is based on the main oscillator frequency divided by 2 fep From Run mode the different power
80. TE ENABLE OUTPUT amp gt z lt El z IMPLEMENTED IN TRUE OPEN DRAIN DR REGISTER ACCESS VOPORTS pucr pee e M cene DR REGISTER DATA BUS PUSH PULL OUTPUT 2 ALTERNATE ALTERNATE ENABLE OUTPUT Notes 1 When the I O port is in input configuration and the associated alternate function is enabled as an output reading the DR register will read the alternate function output status 2 When the I O port is in output configuration and the associated alternate function is enabled as an input the alternate function reads the pin status given by the DR register content 32 140 PORTS CAUTION The alternate function must not ac tivated as long as the pin is configured as input with interrupt in order to avoid generating spurious interrupts Analog alternate function When the pin is used as an ADC input the must be configured as floating input The analog multiplexer controlled by the ADC registers switches the analog voltage present on the select ed pin to the common analog rail which is connect ed to the ADC input It is recommended not to change the voltage level or loading on any port pin while conversion is in progress Furthermore it is recommended not to have clocking pins located close to a selected an alog pin WARNING The analog input voltage level must be within the limits stated in the absolute maxi mum rating
81. TE bit is set Closing slave communication After the last data byte is transferred a Stop Con dition is generated by the master The interface detects this condition and sets EVF and STOPF bits with an interrupt if the ITE bit is set Then the interface waits for a read of the SR2 reg ister see Figure 45 Transfer sequencing Error Cases BERR Detection of a Stop or a Start condition during a byte transfer In this case the EVF and the BERR bits are set with an interrupt if the ITE bit is set If itis a Stop then the interface discards the data released the lines and waits for another Start condition If it is a Start then the interface discards the data and waits for the next slave address on the bus AF Detection of a non acknowledge bit In this case the EVF and AF bits are set with an inter rupt if the ITE bit is set Note In both cases SCL line is not held low how ever SDA line can remain low due to possible 0 bits transmitted last It is then necessary to release both lines by software 75 140 ST72104G ST72215G ST72216G ST72254G I C BUS INTERFACE Cont d How to release the SDA SCL lines Set and subsequently clear the STOP bit while BTF is set The SDA SCL lines are released after the transfer of the current byte 12 4 4 2 Master Mode To switch from default Slave mode to Master mode a Start condition generation is needed Start condition Setting the START b
82. U has a full 8 bit architecture and contains The Accumulator is an 8 bit general purpose reg six internal registers allowing efficient 8 bit data ster used to hold operands and the results of the manipulation arithmetic and logic calculations and to manipulate data 5 2 MAIN FEATURES Index Registers X and Y In indexed addressing modes these 8 bit registers 63 basic instructions are used to create either effective addresses or m Fast 8 bit by 8 bit multiply temporary storage areas for data manipulation m 17 main addressing modes The Cross Assembler generates a precede in u Two 8 bit index registers struction PRE to indicate that the following in struction refers to the Y register m 16 bit stack pointer Lownower modas The Y register is not affected by the interrupt auto m p matic procedures not pushed to and popped from m Maskable hardware interrupts the stack Non maskable software interrupt Program Counter PC The program counter is a 16 bit register containing 5 3 CPU REGISTERS the address of the next instruction to be executed The 6 CPU registers shown in Figure 1 are not by the CPU It is made of two 8 bit registers PCL Program Counter Low which is the LSB and PCH ana arg 89065594 Program Counter High which is the MSB Figure 6 CPU Registers ACCUMULATOR RESET VALUE XXh 7 0 X INDEX REGISTER RESET VALUE XXh 7 0 Y INDEX REGISTER RESET VALUE XXh 115 PCH 817 PCL 0 PROG
83. Wave Soldering Profile with 37 Sn and 63 Pb 250 COOLING PHASE 200 5 sec ROOM TEMPERATURE SOLDERING 150 PHASE Temp 199 PREHEATING 50 0 Time sec 160 Figure 100 Recommended Reflow Soldering Oven Profile MID JEDEC 2 220 5 for 25 sec 200 4 150 150 sec above 183 C 90 sec at 125 C Temp 100 ramp down natural ramp up 2 C sec max 50 2 C sec for 50sec 0 Time sec 400 4 132 140 57721046 ST72215G ST72216G 57722546 16 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro grammable versions FLASH as well as in factory coded versions ROM FLASH devices are shipped to customers with a default content FFh while ROM factory coded parts contain the code supplied by the customer This implies that FLASH devices have to be configured by the customer us ing the Option Bytes while the ROM devices are factory configured 16 1 OPTION BYTES The two option bytes allow the hardware configu ration of the microcontroller to be selected The option bytes have no address in the memory map and can be accessed only in programming mode for example using a standard ST7 program ming tool The default content of the FLASH is fixed to FFh In masked ROM devices the option bytes are fixed in hardware by the ROM code see option list USER OPTION BYTE 0 Bit 7 2 Reserved must always be 1
84. acturers include C compli ers emulators and gang programmers Table 27 STMicroelectronics Tool Features Po In Circuit Emulation Programming Capability Software Included Yes Same features as ST7 CD ROM with ST7 Development Kit 052 emulator but without Yes DIP packages only ST7 Assembly toolchain logic analyzer STVD7 and WGDB7 powerful Yes powerful emulation Source Level Debugger for Win ale an er ion logic analyzer C compiler demo versions ST Realizer for Win 3 1 and Win ST7 Programming Board Yes All packages is Programming Tools for Win 3 1 Win 95 and NT Table 28 Dedicated STMicroelectronics Development Tools Supported Products ST7 Development Kit ST7 HDS2 Emulator ST7 Programming Board ST72254G1 ST72C254G1 ST72254G2 ST72C254G2 ST7MDT1 EPB2 EU ST72215G2 ST72C215G2 4 ST7MDT1 DVP2 ST7MDT1 EMU2B ST7MDT1 EPB2 US ST72104G1 ST72C104G1 ST7MDT1 EPB2 UK ST72104G2 ST72C104G2 Note 1 In Situ Programming ISP interface for FLASH devices 136 140 57721046 ST72215G ST72216G 57722546 DEVELOPMENT TOOLS 16 3 1 PACKAGE SOCKET FOOTPRINT PROPOSAL Table 29 Suggested List of SDIP32 Socket Types Same Package Probe Adaptor Socket Reference Footprint Socket Type SDIP32 Table 30 Suggested List of 5 028 Socket Types Same Package Probe Adaptor Socket Reference Footprint Socket Type ENPLAS OTS
85. aler These bits select the CPU clock prescaler which is applied in the different slow modes Their action is conditioned by the setting of the SMS bit These two bits are set and cleared by software SLOW mode CP1 CPO p eM ipsi n 1 71 51 tose Bit 0 SMS Slow mode select This bit is set and cleared by software 0 Normal mode fcpu fosc 2 1 Slow mode fcpy is given by CP1 See low power consumption mode and MCC chapters for more details 37 140 ST72104G ST72215G ST72216G ST72254G MISCELLANEOUS REGISTERS Cont d MISCELLANEOUS REGISTER 2 MISCR2 Read Write Reset Value 0000 0000 00h 7 0 0 0 0 0 SOD SSM SSI Bit 7 4 Reserved always read as 0 Bit 3 MOD SP Master Output Disable This bit is set and cleared by software When set it disables the SPI Master MOSI output signal 0 SPI Master Output enabled 1 SPI Master Output disabled Bit 2 SOD SP Slave Output Disable This bit is set and cleared by software When set it disable the SPI Slave MISO output signal 0 SPI Slave Output enabled 1 SPI Slave Output disabled Bit 1 SSM 55 mode selection This bit is set and cleared by software _ 0 Normal mode the level of the SPI SS signal is input from the external SS _ 1 mode the level of the SPI SS signal is read from the SSI bit Bit 0 SSI 55 internal mode This bit replaces the
86. ame clock signal which is provided by the master de vice via the SCK pin Thus the byte transmitted is replaced by the byte received and eliminates the need for separate transmit empty and receiver full bits A status flag is used to indicate that the operation is com plete Four possible data clock timing relationships may be chosen see Figure 40 but master and slave must be programmed with the same timing mode SLAVE MSBit 6 LSBit a 8 BIT SHIFT REGISTER 4 57721046 ST72215G ST72216G 57722546 SERIAL PERIPHERAL INTERFACE Cont d Figure 38 Serial Peripheral Interface Block Diagram Internal Bus Read Read Buffer ES IT request SR TUE MISO 0 8 Bit Shift Register STATE CONTROL CR ee edendi MASTER A CONTROL SERIAL CLOCK GENERATOR 61 140 4 ST72104G ST72215G ST72216G ST72254G SERIAL PERIPHERAL INTERFACE Cont d 12 3 4 Functional Description Figure 37 shows the serial peripheral interface SPI block diagram This interface contains 3 dedicated registers A Control Register CR A Status Register SR A Data Register DR Refer to the CR SR and DR registers in Section 12 3 7for the bit definitions 12 3 4 1 Master Configuration In a master configuration the serial clock is gener ated on the SCK pin Procedure Select the SPRO amp SPR1 bits to define the se rial clock baud rate see CR register Select
87. amily of oscillators has the advantage of pro ducing a very accurate rate on the main clock of the ST7 The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption In this mode of the multi oscillator the resonator and the load capacitors have to be placed as close as pos sible to the oscillator pins in order to minimize out put distortion and start up stabilization time The loading capacitance values must be adjusted ac cording to the selected oscillator These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start up phase ST7 OSC1 OSC2 LOAD CAPACITORS lt M 2 a 2 E 5 D External RC Oscillator External RC Oscillator This oscillator allows a low cost solution for the main clock of the ST7 using only an external resis tor and an external capacitor The frequency of the external RC oscillator in the range of some MHz is fixed by the resistor and the capacitor values Consequently in this MO mode the accuracy of the clock is directly linked to the accuracy of the discrete components Internal RC Oscillator The internal RC oscillator mode is based on the same principle as the external RC oscillator includ ing the resistance and the capacitance of the de vice This mode is the most cost effective one with the
88. bit is set and when the 7 bit timer bits T6 TO rolls over from 40h to 3Fh T6 becomes cleared it initiates a reset cycle pulling low the reset pin for typically 500ns The application program must write in the CR reg ister at regular intervals during normal operation to prevent an MCU reset The value to be stored in the CR register must be between FFh and COh see Table 11 Watchdog Timing fCPU 8 MHz The WDGA bit is set watchdog enabled The T6 bit is set to prevent generating an imme diate reset The T5 TO bits contain the number of increments which represents the time delay before the watchdog produces a reset WATCHDOG CONTROL REGISTER CR 7 BIT DOWNCOUNTER CLOCK DIVIDER 12288 4 39 140 ST72104G ST72215G ST72216G ST72254G WATCHDOG TIMER Cont d Table 11 Watchdog Timing 8 MHz CR Register WDG timeout period initial value ms Max FFh 98 304 Min COh 1 536 Notes Following a reset the watchdog is disa bled Once activated it cannot be disabled except by a reset The T6 bit can be used to generate a software re set the WDGA bit is set and the T6 bit is cleared 12 1 4 Hardware Watchdog Option If Hardware Watchdog is selected by option byte the watchdog is always active and the WDGA bit in the CR is not used Refer to the device specific Option Byte descrip tion 12 1 5 Low Power Modes WAIT Instruction No ef
89. ble 5 Interrupt Mapping on page 26 for more details 4 Before servicing an interrupt the CC register is pushed on the stack The bit of the CC register is set during the interrupt routine and cleared when the CC register is popped 29 140 ST72104G ST72215G ST72216G ST72254G 10 PORTS 10 1 INTRODUCTION The I O ports offer different functional modes transfer of data through digital inputs and outputs and for specific pins external interrupt generation alternate signal input output for the on chip pe ripherals An I O port contains up to 8 pins Each be programmed independently as digital input with or without interrupt generation or digital output 10 2 FUNCTIONAL DESCRIPTION Each port has 2 main registers Data Register DR Data Direction Register DDR and one optional register Option Register OR Each I O pin may be programmed using the corre sponding register bits in the DDR and OR regis ters bit X corresponding to pin X of the port The same correspondence is used for the DR register The following description takes into account the OR register for specific ports which do not pro vide this register refer to the Port Implementa tion section The generic block diagram is shown in Figure 21 10 2 1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit In this case reading the DR r
90. ce only on ST72254Gx m 1 Analog peripheral 8 bit ADC with 6 input channels except on ST72104Gx Device Summary ST72104G1 ST72104G2 ST72216G1 ST72215G2 ST72254G1 ST72254G2 Peripherals One 16 bit timer One 16 bit timer Two 16 bit timers Two 16 bit timers SPI SPI ADC SPI ADC SPI PC ADC Up to 8 MHz with oscilator up to 16 0 C to 70 C 10 C to 85 C 40 C to 85 C 40 C to105 C 40 C to 125 C optional 5028 SDIP32 2 6 November 2000 1 140 This is preliminary information on a new product in development or undergoing evaluation Details are subject to change without notice Table of Contents TINTRODUCTION nre Rey RE EIS EX Race tT I 6 2 PIN DESCRIPTION uude AW RE RR Rs 7 3 REGISTER amp MEMORY 10 4 FLASH PROGRAM MEMORY 13 44 INTRODUGTION pha REP eA Pee E dione 13 42 MAIN FEATURES i REIR NER 13 4 STRUCTURAL ORGANISATION 13 4 4 IN SITU PROGRAMMING ISP MODE 13 4 5 MEMORY READ OUT PROTECTION 13 5 CENTRAL PROCESSING UNIT 14 INTRODUCTION 25223 dara ELE erem e ER
91. ces are designed for mid range applications with ADC and interface capabili ties ST72215 6G devices target the same range of applications but without 2 interface ST72104G devices are for applications that do not need ADC and PC peripherals All devices are based on a common industry standard 8 bit core featuring an enhanced instruc tion set The ST72C104G ST72C215G ST72C216G and ST72C254G versions feature single voltage FLASH memory with byte by byte In Situ Pro gramming ISP capability Figure 1 General Block Diagram Under software control all devices can be placed in WAIT SLOW or HALT mode reducing power consumption when the application is in idle or stand by state The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers enabling the design of highly efficient and compact application code In addition to standard 8 bit data management all ST7 micro controllers feature true bit manipulation 8x8 un signed multiplication and indirect addressing modes For easy reference all parametric data are located in Section 14 on page 96 Internal 5 1 gt CLOCK MULTI OSC OSC2 CLOCK FILTER RENE POWER UPPLY Vss 3 RESET CONTROL 8 BIT CORE ALU PROGRAM MEMORY 4 or 8K Bytes RAM 256 5 K 16 TIMER A MI PORT PCSO 6 bits 8
92. d 0 0 Slave mode 1 Master mode Bit 0 SB Start bit Master mode This bit is set by hardware as soon as the Start condition generated following write START 1 An interrupt is generated if ITE 1 It is cleared by software reading SR1 register followed by writing the address byte in DR register It is also cleared by hardware when the interface is disa bled PE 0 0 No Start condition 1 Start condition generated 2 STATUS REGISTER 2 582 Read Only Reset Value 0000 0000 00h 7 0 o o ARLO GCAL Bit 7 5 Reserved Forced to 0 by hardware Bit 4 AF Acknowledge failure This bit is set by hardware when no acknowledge is returned An interrupt is generated if ITE 1 It is cleared by software reading SR2 register or by hardware when the interface is disabled 0 The SCL line is not held low while AF 1 0 No acknowledge failure 1 Acknowledge failure Bit 3 STOPF Stop detection Slave mode This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge if ACK 1 An interrupt is generated if ITE 1 It is cleared by software reading SR2 register or by hardware when the interface is disabled PE 0 The SCL line is not held low while STOPF 1 0 No Stop condition detected 1 Stop condition detected 82 140 Bit 2 ARLO Arbitration lost This bit is set by hardware when the interface los es the arbitration of the b
93. d 13 1 6 Indirect Indexed Short Long This is a combination of indirect and short indexed addressing modes The operand is referenced by its memory address which is defined by the un signed addition of an index register value X or Y with a pointer value located in memory The point er address follows the opcode The indirect indexed addressing mode consists of two sub modes Indirect Indexed Short The pointer address is a byte the pointer size is a byte thus allowing 00 1FE addressing space and requires 1 byte after the opcode Indirect Indexed Long The pointer address is a byte the pointer size is a word thus allowing 64 Kbyte addressing space and requires 1 byte after the opcode Table 20 Instructions Supporting Direct Indexed Indirect and Indirect Indexed Addressing Modes Instructions D P ADC ADD SUB SBC Arithmetic Addition subtrac tion operations CP Clear INC DEC Increment Decrement CPL NEG 1 or 2 Complement Short Instructions Only Function TNZ i BSET BRES Bit Operations BTJT BTJF Bit Test and Jump Opera tions SEE SRE SRA RLC Shift and Rotate Operations RRC 92 140 SWAP Swap Nibbles CALL JP Call or Jump subroutine 13 1 7 Relative Mode Direct Indirect This addressing mode is used to modify the PC register value by adding an 8 bit signed offset to it Available Relative Direct Indirect Instructions CALLR Call Relative The re
94. de pending on the I C mode They are not cleared when the interface is disabled 0 Standard mode FM SMz0 lt 100kHz Fopy 2x CC6 CC0 2 Fast mode FM SM 1 Fac gt 100kHz Fopy 3x CC6 CC0 2 Note The programmed Fac assumes no load on SCL and SDA lines 4 57721046 ST72215G ST72216G 57722546 DATA REGISTER DR Read Write Reset Value 0000 0000 00h 7 0 os os o oe or o Bit 7 0 D7 DO 8 bit Data Register These bits contain the byte to be received or trans mitted on the bus Transmitter mode Byte transmission start auto matically when the software writes in the DR reg ister Receiver mode the first data byte is received au tomatically in the DR register using the least sig nificant bit of the address Then the following data bytes are received one by one after reading the DR register 83 140 ST72104G ST72215G 57722166 ST72254G 2 BUS INTERFACE Cont d OWN ADDRESS REGISTER OAR1 Read Write Reset Value 0000 0000 00h OWN ADDRESS REGISTER OAR2 Read Write Reset Value 0100 0000 40h 7 0 7 0 ADD7 ADD6 ADD5 ADD4 ADDS ADD2 ADD1 ADDO FR1 mo ADD9 ADD8 0 7 bit Addressing Mode Bit 7 1 ADD7 ADD1 Interface address These bits define the 2 bus address of the inter face They are not cleared when the interface is disabled PE 0 Bit 0
95. drawback of a lower frequency accuracy Its frequency is in the range of several MHz In this mode the two oscillator pins have to be tied to ground Internal RC Oscillator 21 140 ST72104G ST72215G ST72216G ST72254G 7 4 CLOCK SECURITY SYSTEM CSS The Clock Security System CSS protects the ST7 against main clock problems To allow the in tegration of the security features in the applica tions itis based on a clock filter control and an In ternal safe oscillator The CSS can be enabled or disabled by option byte 7 4 1 Clock Filter Control The clock filter is based on a clock frequency limi tation function This filter function is able to detect and filter high frequency spikes on the ST7 main clock If the oscillator is not working properly e g work ing at a harmonic frequency of the resonator the current active oscillator clock can be totally fil tered and then no clock signal is available for the ST7 from this oscillator anymore If the original clock source recovers the filtering is stopped au tomatically and the oscillator supplies the ST7 clock 7 4 2 Safe Oscillator Control The safe oscillator of the CSS block is a low fre quency back up clock source see Figure 13 If the clock signal disappears due to a broken or disconnected resonator during a safe oscillator period the safe oscillator delivers a low frequency clock signal which allows the ST7 to perform some rescue operat
96. e 2 The ideal transfer curve DDA SSA 3 End point correlation line 68 256 Er Total Unadjusted Error maximum deviation between the actual and the ideal transfer curves Eo Offset Error deviation between the first actual transition and the first ideal one Eg Gain Error deviation between the last ideal transition and the last actual one Ep Differential Linearity Error maximum deviation between actual steps and the ideal one E Integral Linearity Error maximum deviation between any actual transition and the end point correlation line fL Vin 1 5 253 254 255 256 1 Accuracy vs Negative Injection Current For Ij 20 8m4A the typical leakage induced inside the die is 1 and the effect on the ADC accuracy is a loss of 1 LSB for each 10 increase of the external analog source impedance This effect on the ADC accuracy has been observed under worst case conditions for injection negative injection injection to an Input with analog capability adjacent to the enabled Analog Input at 5V Vpp supply and worst case temperature 2 Data based on characterization results with TA225 C 3 Data based on characterization results over the whole temperature range 129 140 4 ST72104G ST72215G ST72216G ST72254G 15 PACKAGE CHARACTERISTICS 15 1 PACKAGE MECHANICAL DATA Figure 97 32 Pin Shrink Plastic Dual In Line Package os
97. e 2 Pin Enable This bit is used only to output the signal from the timer on the OCMP2 pin OLV2 in Output Com pare mode Whatever the value of the OC2E bit the internal Output Compare 2 function of the timer remains active 0 OCMP2 pin alternate function disabled I O pin free for general purpose 1 OCMP2 pin alternate function enabled Bit 5 OPM One Pulse mode 0 One Pulse mode is not active One Pulse mode is active the ICAP1 pin can be used to trigger one pulse on the pin the active transition is given by the IEDG1 bit The length of the generated pulse depends on the contents of the OC1R register 56 140 Bit 4 PWM Pulse Width Modulation 0 PWM mode is not active 1 PWM mode is active the pin outputs a programmable cyclic signal the length of the pulse depends on the value of OC1R register the period depends on the value of OC2R regis ter Bits 3 2 CC 1 0 Clock Control The timer clock mode depends on these bits Table 13 Clock Control Bits External Clock where available Note If the external clock pin is not available pro gramming the external clock configuration stops the counter Bit 1 IEDG2 nput Edge 2 This bit determines which type of level transition on the 2 pin will trigger the capture 0 A falling edge triggers the capture 1 A rising edge triggers the capture Bit 0 EXEDG External Clock Edge This bit determine
98. e 69 Typical Safe Oscillator Frequencies fosc kHz 40 C X 85 C 25 125 VDD V Note 1 Data based on characterization results tested in production between 90KHz and 600KHz 2 Filtered glitch on the fosc signal See functional description in Section 7 5 on page 23 for more details 4 111 140 ST72104G ST72215G ST72216G ST72254G 14 6 MEMORY CHARACTERISTICS Subject to general operating conditions for Vpp fosc and T4 unless otherwise specified 14 6 1 RAM and Hardware Registers Symbol Parameter Conditions Typ ELZ Baaren PAT moe ornes te _ 14 6 2 FLASH Program Memory Parameter Condions Wim Mex Unit Pewammmgmeeauere7 9 Programming ime tor 16 Tse tar Bataretenton Pid a Naw erase oyses es Notes 1 Minimum Vpp supply voltage without losing data stored in RAM in HALT mode or under RESET or in hardware reg isters only in HALT mode Guaranteed by construction not tested in production 2 Data based on characterization results tested in production at 25 3 Up to 16 bytes can be programmed at a time for a 4kBytes FLASH block then up to 32 bytes at a time for an 8k device 4 The data retention time increases when the T decreases 5 Data based on reliability test results and monitored in production 4 1
99. e ICAP2 pin can be used to perform input capture ICF2 can be set and IC2R can be loaded but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set 5 When One Pulse mode is used is dedi cated to this mode Nevertheless OC2R and 2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the OLVL2 level is dedi cated to One Pulse mode 51 140 ST72104G ST72215G ST72216G ST72254G 16 BIT TIMER Cont d Figure 35 One Pulse Mode Timing Example 2ED3 ICAP1 OCMP1 OLVL2 OLVL1 OLVL2 comparet Note IEDG1 1 OC1R 2bDOh OLVL1 0 OLVL2 1 Figure 36 Pulse Width Modulation Mode Timing Example COUNTER 34E2KFFFC JFFFD XFFFE 2 2ED1X2ED2X 34 2 X FFFC OCMP1 OLVL2 OLVL1 OLVL2 compare2 comparet compare2 Note OC1R 2ED0h OC2R 34E2 OLVL1 0 OLVL2 1 52 140 4 16 TIMER 12 2 3 6 Pulse Width Modulation Mode Pulse Width Modulation PWM mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers The Pulse Width Modulation mode uses the com plete Output Compare 1 function plus the OC2R register and so these functions cannot be used when the PWM mode is activated Procedure To use Pulse Width Modulation mode 1 Load the OC2R r
100. e resistor and two capacitors protects the device against parasitic resets especially in a noisy environments 8 The output of the external reset circuit must have an open drain output to drive the ST7 reset pad Otherwise the device can be damaged when the ST7 generates an internal reset LVD or watchdog 4 121 140 ST72104G ST72215G ST72216G ST72254G CONTROL PIN CHARACTERISTICS Cont d Figure 87 Typical loy vs Vpp with Vin Vss Figure 88 Typical Vo at Vpp 5V RESET lon yA Vol V at Vdd 5V lio mA Vol V at lio 5mA Ta 40 C 85 Vdd V Vad V 122 140 57721046 ST72215G ST72216G 57722546 CONTROL CHARACTERISTICS Cont d 14 9 2 ISPSEL Pin Subject to general operating conditions for Vpp fosc and T4 unless otherwise specified ISPSEL L ST72XXX ST72XXX Notes 1 Data based on design simulation and or technology characteristics not tested in production 2 When the ISP Remote mode is not required by the application ISPSEL pin must be tied to Vss 4 123 140 ST72104G ST72215G ST72216G ST72254G 14 10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for Vpp Refer to I O port characteristics for more details on fosc and T4 unless otherwise specified the input output alternate function characteristics output compare input capture external clock PWM output 14 10
101. ed Threshold 3 50 2 Low Threshold 3 00 Reset release threshold Vpp rise Reset generation threshold Vpp fall LVD voltage threshold hysteresis o2 so Vims Filtered glitch delay on Vpp ot detected by the LVD 40 FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA FOR TEMPERATURES HIGHER THAN 85 FUNCTIONALITY NOT GUARANTEED IN THIS AREA DEVICE UNDER RESET IN THIS AREA 5 FUNCTIONAL AREA SUPPLY VOLTAGE V FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA FOR TEMPERATURES HIGHER THAN 85 C FUNCTIONALITY NOT GUARANTEED IN THIS AREA DEVICE UNDER RESET IN THIS AREA FUNCTIONALITY NOT GUARANTEED IN THIS AREA FOR TEMPERATURES HIGHER THAN 85 FUNCTIONALITY NOT GUARANTEED IN THIS AREA DEVICE UNDER RESET IN THIS AREA 1 1 1 23 3 2 3 5 Notes 1 LVD typical data are based 25 They are given only as design guidelines are not tested 2 Data based on characterization results not tested in production 3 The Vpp rise time rate condition is needed to insure a correct device power on and LVD reset Not tested in production 4 If the low LVD threshold is selected when Vpp falls below 3 2V Vpp minimum operating voltage the device is guar anteed to continue functioning until it goes into reset state The specified Vpp min value is necessary in the device power on phase but during a power down phase or voltage d
102. ed to O Bit 0 WDGRF Watchdog reset flag This bit indicates that the last RESET was gener ated by the watchdog peripheral It is set by hard ware Watchdog RESET and cleared by software writing zero or an LVD RESET to ensure a sta ble cleared state of the WDGRF flag when the CPU starts Combined with the LVDRF flag information the flag description is given by the following table External RESET pin Watchdog LVD Application notes The LVDRF flag is not cleared when another RE SET type occurs external or watchdog the LVDRF flag remains set to keep trace of the origi nal failure In this case a watchdog reset can be detected by software while an external reset can not Table 4 Clock Reset and Supply Register Map and Reset Values Address Register 7 1 Hex Label 0025h 4 CRSR LVDRF CSSIE CSSD WDGRF Reset Value 0 0 23 140 ST72104G ST72215G ST72216G ST72254G 7 6 MAIN CLOCK CONTROLLER MCC The Main Clock Controller MCC supplies the clock for the ST7 CPU and its internal peripherals It allows SLOW power saving mode to be man aged by the application All functions are managed by the Miscellaneous register 1 MISCR1 The MCC block consists of m programmable CPU clock prescaler m A clock out signal to supply external devices The prescaler allows the selection of the main clock frequency and is controlled by three bits of the MISCR1 CP1 and SMS The cloc
103. egister returns the digital value applied to the external I O pin Different input modes can be selected by software through the OR register Notes 1 Writing the DR register modifies the latch value but does not affect the pin status 2 When switching from input to output mode the DR register has to be written first to drive the cor rect level on the pin as soon as the port is config ured as an output External interrupt function When I O is configured as Input with Interrupt an event on this I O can generate an external inter rupt request to the CPU Each pin can independently generate an interrupt request The interrupt sensitivity is independently 30 140 programmable using the sensitivity bits in the Mis cellaneous register Each external interrupt vector is linked to a dedi cated group of I O port pins see pinout description and interrupt section If several input pins are se lected simultaneously as interrupt source these are logically ANDed For this reason if one of the interrupt pins is tied low it masks the other ones In case of a floating input with interrupt configura tion special care must be taken when changing the configuration see Figure 22 The external interrupts are hardware interrupts which means that the request latch not accessible directly by the application is automatically cleared when the corresponding interrupt vector is fetched To clear an unwanted pending interrupt
104. egister with the value corre sponding to the period of the signal using the formula in the opposite column 2 Load the OC1R register with the value corre sponding to the period of the pulse if OLVL1 0 and OLVL2 1 using the formula in the oppo site column 3 Select the following in the CR1 register Using the OLVL 1 bit select the level to be ap plied to the OCMP1 pin after a successful comparison with OC1R register Using the OLVL2 bit select the level to be ap plied to the OCMP1 pin after a successful comparison with OC2R register 4 Select the following in the CR2 register Set OC1E bit the pin is then dedicat ed to the output compare 1 function Set the PWM bit Select the timer clock CC 1 0 see Table 13 Clock Control Bits If OLVL1 1 and OLVL2 0 the length of the posi tive pulse is the difference between the OC2R and OC1R registers If OLVL1 OLVL2 a continuous signal will be seen on the pin Pulse Width Modulation cycle gt OCMP1 OLVL1 OCMP1 OLVL2 When Counter 2 to FFFCh ICF1 bit is set 4 577210406 ST72215G ST72216G 57722546 The OCR register value required for a specific tim ing application can be calculated using the follow ing formula t f 2 5 Where t Signal or pulse period in seconds fcpu CPU clock frequency in hertz PRESC Timer prescaler factor 2 4 or
105. er each timer clock cycle MS Byte LS Byte These registers are readable and writable and are not affected by the timer hardware A reset event changes the value to 8000h Timing resolution is one count of the free running counter fcpuyccit 0 OCiR Procedure To use the output compare function select the fol lowing in the CR2 register Set the bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal Select the timer clock CC 1 0 see Table 13 Clock Control Bits And select the following in the CR1 register Select the OLVLibit to applied to the OCMP pins after the match occurs Set the OCIE bit to generate an interrupt if it is needed When a match is found between OCRi register and CR register OCFi bit is set 48 140 The OCMPi pin takes OLVLibit value OCMP pin latch is forced low during reset A timer interrupt is generated if the OCIE bit is set in the CR2 register and the bit is cleared the CC register CC The OCR register value required for a specific tim ing application can be calculated using the follow ing formula f AocR CPU PRESC Where At Output compare period in seconds fcpu CPU clock frequency in hertz PRESC Timer prescaler factor 2 4 or 8 de pending on 1 0 bits see Table 13 Clock Control Bits If the timer clock is an external clock the formula is
106. ervice routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack Note As a consequence of the IRET instruction the bit will be cleared and the main program will resume Priority Management By default a servicing interrupt cannot be inter rupted because the bit is set by hardware enter ing in interrupt routine In the case when several interrupts are simultane ously pending an hardware priority defines which one will be serviced first see the Interrupt Map ping Table Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode Only external and specifi cally mentioned interrupts allow the processor to leave the HALT low power mode refer to the Exit from HALT column in the Interrupt Mapping Ta ble 8 1 NON MASKABLE SOFTWARE INTERRUPT This interrupt is entered when the TRAP instruc tion is executed regardless of the state of the bit 4 57721046 ST72215G ST72216G 57722546 It will be serviced according to the flowchart Figure 1 8 2 EXTERNAL INTERRUPTS External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the bit is cleared These interrupts allow the processor to leave the Halt low power mode The external interrupt polarity is selected through the miscellaneous register or interrupt register if available
107. ext in 7 bit mode read the DR register to deter mine from the least significant bit Data Direction Bit if the slave must enter Receiver or Transmitter mode In 10 bit mode after receiving the address se quence the slave is always in receive mode It will enter transmit mode on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set 11110xx1 Slave Receiver Following the address reception and after SR1 register has been read the slave receives bytes from the SDA line into the DR register via the inter nal shift register After each byte the interface gen erates in sequence Acknowledge pulse if the ACK bit is set ky 57721046 ST72215G ST72216G ST72254G EVF and bits set with an interrupt if the ITE bit is set Then the interface waits for a read of the SR1 reg ister followed by a read of the DR register holding the SCL line low see Figure 45 Transfer se quencing EV2 Slave Transmitter Following the address reception and after SR1 register has been read the slave sends bytes from the DR register to the SDA line via the internal shift register The slave waits for a read of the SR1 register fol lowed by a write in the DR register holding the SCL line low see Figure 45 Transfer sequencing EV3 When the acknowledge pulse is received The EVF and bits are set by hardware with an interrupt if the I
108. fect on Watchdog HALT Instruction If the Watchdog reset on HALT option is selected by option byte a HALT instruction causes an im mediate reset generation if the Watchdog is acti vated WDGA bit is set 12 1 5 1 Using Halt Mode with the WDG option If the Watchdog reset on HALT option is not se lected by option byte the Halt mode can be used when the watchdog is enabled In this case the HALT instruction stops the oscilla tor When the oscillator is stopped the WDG stops counting and is no longer able to generate a reset until the microcontroller receives an external inter rupt or a reset If an external interrupt is received the WDG re starts counting after 4096 CPU clocks If a reset is generated the WDG is disabled reset state Recommendations Make sure that an external event is available to wake up the microcontroller from Halt mode Before executing the HALT instruction refresh the WDG counter to avoid an unexpected WDG 40 140 reset immediately after waking up the microcon troller When using an external interrupt to wake up the microcontroller reinitialize the corresponding I O as Input Pull up with Interrupt before executing the HALT instruction The main reason for this is that the I O may be wrongly configured due to ex ternal interference or by an unforeseen logical condition For the same reason reinitialize the level sensi tiveness of each external interrupt a
109. gis ter value plus 1 see Figure 34 on page 53 The output compare functions can be used both for generating external events on the OCMP pins even if the input capture mode is also used The value in the 16 bit register and the OLVi bit should be changed after each suc cessful comparison in order to control an output waveform or establish a new elapsed timeout Figure 32 Output Compare Block Diagram ST72104G ST72215G ST72216G ST72254G Forced Compare Output capability When the bit is set by software the OLVL bit is copied to the pin The OLVi bit has to be toggled in order to toggle the OCMPi pin when itis enabled OC E bit 1 The OCFi bit is then not set by hardware and thus no interrupt request is generated FOLVLi bits have no effect in either One Pulse mode or PWM mode Status Register SR 4 49 140 ST72104G ST72215G ST72216G ST72254G 16 BIT TIMER Figure 33 Output Compare Timing Diagram ftimer fcpy 2 INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER OCR OUTPUT COMPARE FLAG i OLVLi 1 GE _ T Figure 34 Output Compare Timing Diagram fcpy 4 INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER COMPARE REGISTER ij LATCH OUTPUT COMPARE FLAG i OCFi OLVLi 1
110. gure 80 Typical at Vpp 5V standard Figure 82 Typical Vpp Voy at Vppz5V Vol V at Vdd 5V 2 5 Ta 40 C 85 2 25 6 125 lio mA lio mA Figure 81 Typical at Vppz5V high sink Vol V at Vdd 5V 2 Ta 40 C 85 1 5 S eS Ta 25 C 125 10 15 20 25 lio mA Notes 1 The current sunk must always respect the absolute maximum rating specified in Section 14 2 2 and the sum of ljo ports and control pins must not exceed lyss 2 The current sourced must always respect the absolute maximum rating specified in Section 14 2 2 and the sum of ports and control pins must not exceed lypp True open drain I O pins does not have Voy 119 140 ST72104G ST72215G ST72216G ST72254G PORT PIN CHARACTERISTICS Cont d Figure 83 Typical Vo vs Vpp standard I Os Vol V at 2 120 140 Ta 40 C 85 Vol V at lio 5mA Ta 40 C 85 vdd V Vol V at lio 20mA Ta 40 C 85 1 5 vdd V Vdd Voh V at lio 5mA 4 5 Vdd V vdd V 4 57721046 ST72215G ST72216G 57722546 14 9 CONTROL CHARACTERISTICS 14 9 1
111. h 0025h CRSR Clock Reset Supply Control Status Register 000 000 R W 0026h Reserved 2 bytes 0027h 2 Control Register R W I2CSR1 Status Register 1 Read Only I2CSR2 Status Register 2 Read Only 2 2 Clock Control Register R W I2COAR1 Own Address Register 1 R W I2COAR2 Own Address Register 2 R W I2CDR Data Register R W 002Fh to Reserved 4 Bytes 0030h 11 140 ST72104G ST72215G ST72216G ST72254G S Register Label TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR TIMER A Register Name Timer A Control Register 2 Timer A Control Register 1 Timer A Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register Reset Status R W R W Read Only Read Only Read Only R W R W Read Only Read Only Read Only Read Only Read Only Read Only R W R W 0040h MISCR2 Miscellaneous Register 2 TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR
112. he for example or an external pull up or pull down resistor see Figure 78 Data based on design simulation and or technology characteristics not tested in production 5 The pull up equivalent resistor is based on a resistive transistor corresponding current characteristics de scribed Figure 79 This data is based on characterization results tested in production at Vpn max 6 Data based on characterization results not tested in production 7 To generate an external interrupt a minimum pulse width has to be applied on an I O port pin configured as an external interrupt source 118 140 57721046 ST72215G ST72216G 57722546 PORT PIN CHARACTERISTICS Cont d 14 8 2 Output Driving Current Subject to general operating conditions for Vpp fosc and T4 unless otherwise specified 5 lt 85 Output low level voltage for a standard pin gt 859 when 8 pins sunk at same time 5 see Figure 80 and Figure 83 2 lt 85 gt 859 20 lt 85 Output low level voltage for a high sink I O pin T4A285 C when 4 pins are sunk at same time see Figure 81 and Figure 84 8 lt 85 TA285 C 5 lt 85 Vpp 1 6 Output high level voltage for an I O pin Ta285 C Vpp 1 7 when 4 pins are sourced at same time 5 see Figure 82 and Figure 85 2 lt 85 Vpp 0 8 TA285 C Vpp 1 0 Fi
113. he IC1R register Because the ICF1 bit is set when an active edge occurs an interrupt can be generated if the ICIE bit is set ST72104G ST72215G ST72216G 57722546 Clearing the Input Capture interrupt request i e clearing the ICF bit is done in two steps 1 Reading the SR register while the ICF bit is set 2 An access read or write to the register The register value required for a specific timing application can be calculated using the fol lowing formula t f Value aor PRESC Where t Pulse period in seconds CPU clock frequency in hertz PRESC Timer prescaler factor 2 4 or 8 depend ing on the CC 1 0 bits see Table 13 Clock Control Bits If the timer clock is an external clock the formula is OCR t fExT Where t fExT ll Pulse period in seconds External timer clock frequency in hertz When the value of the counter is equal to the value of the contents of the register the OLVL1 bit is output on the pin see Figure 35 Notes 1 The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an Output Compare interrupt 2 When the Pulse Width Modulation PWM and One Pulse mode OPM bits are both set the PWM mode is the only active one If OLVL1 OLVL2 a continuous signal will be seen on the pin 4 The ICAP1 pin can not be used to perform input capture Th
114. he SPIF bit is set 2 A read to the DR register Notes While the SPIF bit is set all writes to the DR register are inhibited until the SR register is read The SPIF bit can be cleared during a second transmission however it must be cleared before the second SPIF bit in order to prevent an overrun condition see Section 12 3 4 6 Depending on the CPHA bit the SS pin has to be set to write to the DR register between each data byte transfer to avoid a write collision see Section 12 3 4 4 63 140 ST72104G ST72215G ST72216G ST72254G SERIAL PERIPHERAL INTERFACE Cont d 12 3 4 3 Data Transfer Format During an SPI transfer data is simultaneously transmitted shifted out serially and received shifted in serially The serial clock is used to syn chronize the data transfer during a sequence of eight clock pulses The SS pin allows individual selection of a slave device the other slave devices that are not select ed do not interfere with the SPI transfer Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software using the CPOL and CPHA bits The CPOL clock polarity bit controls the steady state value of the clock when no data is being transferred This bit affects both master and slave modes The combination between the CPOL and CPHA clock phase bits selects the data capture clock edge Figure 40 shows an SPI transfer with the four combinations of the CPHA and CPOL bi
115. he input output direction configuration of the pins Each bit is set and cleared by software 0 Input mode 1 Output mode OPTION REGISTER OR Port x Option Register PxOR with x A B or C Read Write Reset Value 0000 0000 00h 7 0 07 06 5 4 02 O1 O0 Bit 7 0 O 7 0 Option register 8 bits For specific I O pins this register is not implement ed In this case the DDR register is enough to se lect the I O pin configuration The OR register allows to distinguish in input mode if the pull up with interrupt capability or the basic pull up configuration is selected in output mode if the push pull or open drain configuration is selected Each bit is set and cleared by software Input mode 0 Floating input 1 Pull up input with or without interrupt Output mode 0 Output open drain with P Buffer deactivated 1 Output push pull when available 4 57721046 ST72215G ST72216G 57722546 PORTS Cont d Table 9 I O Port Register and Reset Values Address Register Hex Label Reset Value of all I O port registers 0000h PCDR 0001h PCDDR 0002h PCOR 0004h 0005h 0006h 0008h 0009h 4 35 140 ST72104G ST72215G ST72216G ST72254G 11 MISCELLANEOUS REGISTERS The miscellaneous registers allow control over several different features such as the external in terrupts or the I O alternate functions 11 1 PORT INTERRUPT SENSITIVITY
116. header byte Address byte successfully transmitted in Mas ter mode Bit 6 ADD10 10 bit addressing in Master mode This bit is set by hardware when the master has sent the first byte in 10 bit address mode It is cleared by software reading SR2 register followed by a write in the DR register of the second address byte It is also cleared by hardware when the pe ripheral is disabled PE 0 0 No ADD10 event occurred 1 Master has sent first address byte header Bit 5 TRA Transmitter Receiver When is set TRA 1 if a data byte has been transmitted It is cleared automatically when BTF is cleared It is also cleared by hardware after de tection of Stop condition GSTOPF 1 loss of bus 4 57721046 ST72215G ST72216G 57722546 arbitration ARLO 1 or when the interface is disa bled PE 0 0 Data byte received if BTF 1 1 Data byte transmitted Bit 4 BUSY Bus busy This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition It indicates a communication in progress on the bus This information is still updat ed when the interface is disabled 0 0 No communication on the bus 1 Communication ongoing on the bus Bit 3 BTF Byte transfer finished This bit is set by hardware as soon as a byte is cor rectly received or transmitted with interrupt gener ation if ITE 1 It is cleared by software reading SR1 register followed by a read
117. holding the SCL line low see Figure 45 Transfer sequencing EV8 When the acknowledge bit is received the interface sets EVF and bits with an interrupt if the ITE bit is set To close the communication after writing the last byte to the DR register set the STOP bit to gener ate the Stop condition The interface goes auto matically back to slave mode M SL bit cleared Error Cases BERR Detection of a Stop or a Start condition during a byte transfer In this case the EVF and 4 57721046 ST72215G ST72216G 57722546 bits set by hardware with an interrupt if ITE is set AF Detection of a non acknowledge bit In this case the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set To resume set the START or STOP bit ARLO Detection of an arbitration lost condition In this case the ARLO bit is set by hardware with an interrupt if the ITE bit is set and the interface goes automatically back to slave mode the M SL bit is cleared Note In all these cases the SCL line is not held low however the SDA line can remain low due to possible 0 bits transmitted last It is then neces sary to release both lines by software 77 140 ST72104G ST72215G ST72216G ST72254G 2 BUS INTERFACE Cont d Figure 45 Transfer Sequencing T bit Slave receiver S access F Eva T bit Slave transmitter B En
118. ice to be used without any external RESET circuitry 2 Three different reference levels are selectable through the option byte according to the applica tion requirement LVD application note Application software can detect a reset caused by the LVD by reading the LVDRF bit in the CRSR register This bit is set by hardware when a LVD reset is generated and cleared by software writing zero 18 140 4 7 2 RESET SEQUENCE MANAGER RSM 7 2 1 Introduction The reset sequence manager includes three RE SET sources as shown in Figure 11 m External RESET source pulse m Internal LVD RESET Low Voltage Detection m Internal WATCHDOG RESET These sources act on the RESET pin and it is al ways kept low during the delay phase The RESET service routine vector is fixed at ad dresses FFFEh FFFFh in the ST7 memory map The basic RESET sequence consists of 3 phases as shown in Figure 10 m Delay depending on the RESET source m 4096 CPU clock cycle delay m RESET vector fetch Figure 11 Reset Block Diagram 4 57721046 ST72215G ST72216G 57722546 The 4096 CPU clock cycle delay allows the oscil lator to stabilise and ensures that recovery has taken place from the Reset state The RESET vector fetch phase duration is 2 clock cycles Figure 10 RESET Sequence Phases RESET DELAY INTERNAL RESET FETCH 4096 CLOCK CYCLES VECTOR INTERNAL RESET COUNTER WATCHDOG RESET LVD RESET 19 140 ST72
119. in loading conditions di ST7 PIN 96 140 14 1 5 Pin input voltage The input voltage measurement on a pin of the de vice is described in Figure 50 Figure 50 Pin input voltage ST7 PIN 4 57721046 ST72215G ST72216G 57722546 14 2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as absolute maxi tions is not implied Exposure to maximum rating mum ratings may cause permanent damage to conditions for extended periods may affect device the device This is a stress rating only and func reliability tional operation of the device under these condi 14 2 1 Voltage Characteristics Input voltage on any pin Vss 0 3 to yn 3 Electro static discharge voltage Human Body Model see Section 14 7 2 Absolute Elec Electro static discharge voltage Machine Model trical Sensitivity on page 114 14 2 2 Current Characteristics Total current into Vpp power lines source 3 Total current out of Vas ground lines sink Output current sunk by any standard and control pin Output current sunk by any high sink I O pin current on OSC1 and 14 2 3 Thermal Characteristics lINJ PIN Storage temperature range 65 to 4150 Maximum junction temperature see Section 15 2 THERMAL CHARACTERISTICS on page 131 Notes 1 Directly connecting the RESET and I O pins to Vpp or Vgs could damage the device if an unintentional internal reset is generated or an unexpected change of
120. ions Automatically the ST7 clock source switches back from the safe oscillator if the original clock source recovers Limitation detection The automatic safe oscillator selection is notified by hardware setting the CSSD bit of the CRSR register An interrupt can be generated if the CS SIE bit has been previously set These two bits are described in the CRSR register description 7 4 3 Low Power Modes Description WAIT No effect on CSS CSS interrupt cause the device to exit from Wait mode The CRSR register is frozen The CSS in cluding the safe oscillator is disabled until HALT mode is exited The previous CSS configuration resumes when the MCU is woken up by an interrupt with exit from HALT mode capability or from the counter reset value when the MCU is woken up by a RESET 7 4 4 Interrupts The CSS interrupt event generates an interrupt if the corresponding Enable Control Bit CSSIE is set and the interrupt mask in the CC register is re set RIM instruction Interrupt Event CSS event detection safe oscillator acti CSSD CSSIE Yes vated as main clock Note 1 This interrupt allows to exit from active halt mode if this mode is available in the MCU Figure 13 Clock Filter Function and Safe Oscillator Function fosc 2 CLOCK FILTER FUNCTION fopu gt o E J2 oz uu lt 22 140 feu 11 2 4 577210406 ST72215G ST72216G 577
121. it while the BUSY bit is cleared causes the interface to switch to Master mode M SL bit set and generates a Start condi tion Once the Start condition is sent The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set Then the master waits for a read of the SR1 regis ter followed by a write in the DR register with the Slave address holding the SCL line low see Figure 45 Transfer sequencing EV5 Slave address transmission Then the slave address is sent to the SDA line via the internal shift register In 7 bit addressing mode one address byte is sent In 10 bit addressing mode sending the first byte including the header sequence causes the follow ing event The EVF bit is set by hardware with interrupt generation if the ITE bit is set Then the master waits for a read of the SR1 regis ter followed by a write in the DR register holding the SCL line low see Figure 45 Transfer se quencing EV9 Then the second address byte is sent by the inter face 76 140 After completion of this transfer and acknowledge from the slave if the ACK bit is set The EVF bit is set by hardware with interrupt generation if the ITE bit is set Then the master waits for a read of the SR1 regis ter followed by a write in the CR register for exam ple set PE bit holding the SCL line low see Fig ure 45 Transfer sequencing EV6 Next the master must enter Receiver or Transmit ter m
122. k out capability consists of a dedicated port pin configurable as an fcpy clock output to drive external devices It is controlled by the MCO bit in the MISCR1 register See Section 11 MISCELLANEOUS REGIS TERS on page 36 for more details Figure 14 Main Clock Controller MCC Block Diagram CLOCK TO CAN PERIPHERAL PORT ALTERNATE FUNCTION MCO foxcl2 meo sus DIV 2 4 8 16 CPU CLOCK CPU AND PERIPHERALS 24 140 4 8 INTERRUPTS ST7 core may be interrupted by one of two dif ferent methods maskable hardware interrupts as listed in the Interrupt Mapping Table and a non maskable software interrupt TRAP The Interrupt processing flowchart is shown in Figure 1 The maskable interrupts must be enabled clearing the I bit in order to be serviced However disabled interrupts may be latched and processed when they are enabled see external interrupts subsec tion When an interrupt has to be serviced Normal processing is suspended at the end of the current instruction execution The PC X A and CC registers are saved onto the stack The bit of the CC register is set to prevent addi tional interrupts The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched refer to the Interrupt Mapping Table for vector address es The interrupt s
123. l data bytes and the slave de vice has not cleared the SPIF bit issuing from the previous data byte transmitted In this case the receiver buffer contains the byte sent after the SPIF bit was last cleared A read to the DR register returns this byte All other bytes are lost This condition is not detected by the SPI peripher al 67 140 ST72104G ST72215G ST72216G ST72254G SERIAL PERIPHERAL INTERFACE Cont d 12 3 4 7 Single Master and Multimaster Configurations There are two types of SPI systems Single Master System Multimaster System Single Master System A typical single master system may be configured using an MCU as the master and four MCUs as slaves see Figure 42 The master device selects the individual slave de vices by using four pins of a parallel port to control the four SS pins of the slave devices The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time thus disabling the slave devices Note To prevent a bus conflict on the MISO line the master allows only one active slave device during a transmission Figure 42 Single Master Configuration For more security the slave device may respond to the master with the received data byte Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are con nected and the slave has not written its DR regis ter Other transmission security methods
124. lative addressing mode consists of two sub modes Relative Direct The offset follows the opcode Relative Indirect The offset is defined in memory of which the ad dress follows the opcode 4 13 2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions The instructions may ST72104G ST72215G ST72216G ST72254G be subdivided into 13 main groups as illustrated in the following table Code Condition Flag modification Using a pre byte The instructions are described with one to four bytes In order to extend the number of available op codes for an 8 bit CPU 256 opcodes three differ ent prebyte opcodes are defined These prebytes modify the meaning of the instruction they pre cede The whole instruction becomes PC 2 End of previous instruction PC 1 Prebyte PC PC 1 Additional word 0 to 2 according to the number of bytes required to compute the effective address ERLA 5 0 i m These prebytes enable instruction in Y as well as indirect addressing modes to be implemented They precede the opcode of the instruction in X or the instruction using direct addressing mode The prebytes are PDY 90 Replace an X based instruction using immediate direct indexed or inherent addressing mode by a Y one Replace an instruction using direct di rect bit or direct relative addressing mode to an instruction using the corre s
125. led low when Vpp Vir rising edge or Vpp Vy falling edge as shown in Figure 12 The LVD filters spikes on Vpp larger than tgyypp to avoid parasitic resets 7 2 4 Internal Watchdog RESET The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 12 Starting from the Watchdog counter underflow the device RESET pin acts as an output that is pulled low during at least tw RSTL out LONG EXT RESET DELAY WATCHDOG RESET DELAY WATCHDOG UNDERFLOW EE INTERNAL RESET 4096 Tcpu EE FETCH VECTOR 4 57721046 ST72215G ST72216G 57722546 7 3 MULTI OSCILLATOR The main clock of the ST7 can be generated by Table 3 ST7 Clock Sources four different source types coming from the multi oscillator block Hardware Configuration m external source m 4 crystal or ceramic resonator oscillators ST7 m an external RC oscillator OSC1 OSC2 aninternal high frequency RC oscillator Each oscillator is optimized for a given frequency range in terms of consumption and is selectable EXTERNAL through the option byte The associated hardware SOURCE configuration are shown in Table 3 Refer to the electrical characteristics section for more details External Clock External Clock Source In this external clock mode a clock signal square sinus or triangle with 50 duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground Crystal Ceramic Oscillators This f
126. lways enabled 1 Software watchdog to be enabled by software Table 25 Main Oscillator Configuration Selected Oscillator OSC2 OSC1 OSCO External Clock Stand by 1 1 1 4 MHz Internal RC 1 14 MHz External RC Low Power Resonator LP Medium Speed Resonator MS High Speed Resonator HS Table 26 LVD Threshold Configuration LVD1 LVDO 1 1210 1 1 0 Medium Power Resonator MP 0 0 0 Configuration LVD Off 1 Highest Voltage Threshold 4 50V 1 Medium Voltage Threshold 4 05V 0 Lowest Voltage Threshold 3 45V 0 USER OPTION BYTE 0 USER OPTION BYTE 1 Reserved EXTIT FMP LVD1 LVDO OSC 5 5 WDG WDG 2 1 0 Default Value 4 1 1 1 0 1 1 1 1 133 140 ST72104G ST72215G ST72216G ST72254G 16 2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE Customer code is made up of the ROM contents The selected options are communicated to and the list of the selected options if any The STMicroelectronics using the correctly completed ROM contents are to be sent on diskette or by OPTION LIST appended electronic means with the S19 hexadecimal file STMicroelectronics Sales Organization will be generated by the development tool All unused pleased to provide detailed information on con bytes must be set to FFh tractual points
127. mer registers are frozen In HALT mode the counter stops counting until Halt mode is exited Counting resumes from the previous count when the MCU is woken up by an interrupt with exit from HALT mode capability or from the counter reset value when the MCU is woken up by a RESET If an input capture event occurs on the ICAP pin the input capture detection circuitry is armed Consequent ly when the MCU is woken up by an interrupt with exit from HALT mode capability the ICFi bit is set and the counter value present when exiting from HALT mode is captured into the IC R register Enable Interrupt Event Control Input Capture 1 event Counter reset in PWM mode ICF1 Input Capture 2 event ICF2 Output Compare 1 event not available in PWM mode OCF1 Output Compare 2 event not available in PWM mode OCF2 Timer Overflow event TOF 12 2 5 Interrupts Note The 16 bit Timer interrupt events are connected to the same interrupt vector see Interrupts chap ter These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset RIM instruction 12 2 6 Summary of Timer modes AVAILABLE RESOURCES Input E 1 Input Capture2 Output Compare 1 Output ee 2 input Capture andor sees recen eee One Pulse mode Not Recommended PWM Mode Not Recommended No No 1 See note 4 in Section 12 2 3 5 One Pulse Mode on page 54
128. n four I O port pins of the device 6 True open drain I O port pins do not accept positive injection 97 140 ST72104G ST72215G ST72216G 57722549 14 3 OPERATING CONDITIONS 14 3 1 General Operating Conditions Vpp24 5V for FLASH devices FUNCTIONALITY GUARANTEED IN THIS AREA FUNCTIONALITY NOT GUARANTEED 3 5 FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR 1 SUPPLY VOLTAGE V 98 140 4 ST72104G 57722156 57722166 57722549 OPERATING CONDITIONS Cont d Figure 52 fos Maximum Operating Frequency Versus Vp Supply Voltage for FLASH devices 2 FUNCTIONALITY NOT GUARANTEED fosc MHz IN THIS AREA AT gt 85 C FUNCTIONALITY GUARANTEED IN THIS AREA 9 FUNCTIONALITY NOT GUARANTEED 2 FUNCTIONALITY IN THIS AREA NOT GUARANTEED IN THIS AREA WITH RESONATOR 1 SUPPLY VOLTAGE V Notes 1 Guaranteed by construction A D operation and resonator oscillator start up are not guaranteed below 1 2 2 Operating conditions with 40 to 125 C 3 FLASH programming tested in production at maximum with two different conditions Vpp 5 5V fopy 8MHz and Vpp 3 2V fopy 4MHz 99 140 ST72104G ST72215G ST72216G 57722549 OPERATING CONDITIONS Cont d 14 3 2 Operating Conditions with Low Voltage Detector LVD Subject to general operating conditions for Vpp fosc and High Threshold Med Threshold Low Threshold High Threshold 3 85 M
129. n interrupt or polled Figure 43 I C BUS Protocol START CONDITION 4 57721046 ST72215G ST72216G 57722546 handshake interrupts are enabled or disabled by software The interface is connected to the bus by a data pin SDAI and by a clock pin SCLI It can be connected both with a standard bus and a Fast bus This selection is made by soft ware Mode Selection The interface can operate in the four following modes Slave transmitter receiver Master transmitter receiver By default it operates in slave mode The interface automatically switches from slave to master after it generates a START condition and from master to slave in case of arbitration loss or a STOP generation allowing then Multi Master ca pability Communication Flow In Master mode it initiates a data transfer and generates the clock signal A serial data transfer always begins with a start condition and ends with a stop condition Both start and stop conditions are generated in master mode by software In Slave mode the interface is capable of recog nising its own address 7 or 10 bit and the Gen eral Call address The General Call address de tection may be enabled or disabled by software Data and addresses are transferred as 8 bit bytes MSB first The first byte s following the start con dition contain the address one in 7 bit mode two in 10 bit mode The address is always transmitted in
130. n the Stop condition is sent n slave mode 0 No stop generation 1 Release the SCL and SDA lines after the cur rent byte transfer BTF 1 In this mode the STOP bit has to be cleared by software Bit 0 ITE nterrupt enable This bit is set and cleared by software and cleared by hardware when the interface is disabled 0 0 Interrupts disabled 1 Interrupts enabled Refer to Figure 46 for the relationship between the events and the interrupt SCL is held low when the ADD10 SB BTF or ADSL flags or an EV6 event See Figure 45 is de tected 4 BUS INTERFACE Cont d STATUS REGISTER 1 SR1 Read Only Reset Value 0000 0000 00h 7 0 tv anmo Busy nost ws Bit 7 EVF Event flag This bit is set by hardware as soon as an event oc curs It is cleared by software reading SR2 register in case of error event or as described in Figure 45 It is also cleared by hardware when the interface is disabled PE 0 0 No event 1 One of the following events has occurred 1 Byte received or transmitted ADSL 1 Address matched in Slave mode while ACK 1 SB 1 Start condition generated in Master mode AF 1 No acknowledge received after byte transmission STOPF 1 Stop condition detected in Slave mode ARLO 1 Arbitration lost in Master mode BERR 1 Bus error misplaced Start or Stop condition detected ADD10 1 Master has sent
131. neral Block Diagram ALTERNATE REGISTER OUTPUT ACCESS P BUFFER see table below Vpp 274 ALTERNATE ENABLE PULL UP see table below Vpp sng viva N BUFFER DIODES see table below ANALOG CMOS INPUT SCHMITT TRIGGER ALTERNATE 0 EXTERNAL ERGH lt INTERRUPT OTHER SOURCE BITS POLARITY SELECTION Table 6 Port Mode Options Diodes Diodes _ wa P Floating with without Interrupt m Pull up with without Interrupt Gn Push pull Output Open Drain logic level True Open Drain NI see note Legend not implemented Note The diode to Vpp is not implemented in the Off implemented not activated true open drain pads A local protection between On implemented and activated the pad and is implemented to protect the de vice against positive stress 4 31 140 ST72104G ST72215G ST72216G ST72254G PORTS Cont d Table 7 Port Configurations Hardware Configuration NOT IMPLEMENTED DR REGISTER ACCESS TRUE OPEN DRAIN 4 5 EU CONFIGURATION REGISTER SEL BUE gt i ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE ei INTERRUPT POLARITY CONFIGURATION SELECTION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN DR REGISTER ACCESS PORTS 7 DR REGISTER DATA BUS ALTERNATE ALTERNA
132. nterrupt vector fetch is the number of tcpy cycles needed to finish the current instruction execution 3 Data based on design simulation and or technology characteristics not tested in production 4 105 140 ST72104G ST72215G ST72216G ST72254G CLOCK AND TIMING CHARACTERISTICS Cont d 14 5 3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal Ceramic resonator oscillators All the information given in this paragraph are based on characterization results with specified typical external components In the application the reso close as possible to the oscillator pins in order to minimize output distortion and start up stabiliza tion time Refer to the crystal ceramic resonator manufacturer for more details frequency pack age accuracy nator and the load capacitors have to be placed as Symbol Parameter Conditions Symbol Conditions Min Unit LP Low power oscillator 1 2 MP Medium power oscillator 22 4 MHz MS Medium speed oscillator e 8 HS High speed oscillator 16 me rese LL LP oscillator 38 MP oscillator 32 j MS oscillator 18 26 HS oscillator 15 21 LP oscillator 40 100 MP oscillator 110 190 MS oscillator 180 360 HS oscillator 400 700 Oscillator Frequency 3 Recommended load capacitance ver sus equivalent serial resistance of the crystal or ceramic resonator Rs
133. o the DR register is done during a transmit sequence It is cleared by a software sequence see Figure 41 0 No write collision occurred 1 A write collision has been detected Bit 5 Unused Bit 4 MODF Mode Fault flag This bit set by hardware when the SS pin is pulled low in master mode see Section 12 3 4 5 Master Mode Fault on page 70 An SPI interrupt can be generated if SPIE 1 in the CR register This bit is cleared by a software sequence An ac cess to the SR register while MODF 1 followed by a write to the CR register 0 No master mode fault detected 1 A fault in master mode has been detected Bits 3 0 Unused 57721046 ST72215G ST72216G 57722546 DATA REGISTER DR Read Write Reset Value Undefined 7 0 mee os os o oe or o The DR register is used to transmit and receive data on the serial bus In the master device only a write to this register will initiate transmission re ception of another byte Notes During the last clock cycle the SPIF bit is set a copy of the received data byte in the shift register is moved to a buffer When the user reads the serial peripheral data I O register the buffer is actually being read Warning A write to the DR register places data directly into the shift register for transmission A write to the the DR register returns the value lo cated in the buffer and not the contents of the shift register See Figure 38 71
134. o the pads but can also affect the internal devices when the supply pads receive the stress The elements to be pro tected must not receive excessive current voltage or heating within their structure An ESD network combines the different input and output ESD protections This network works by al lowing safe discharge paths for the pins subjected to ESD stress Two critical ESD stress cases are presented in Figure 73 and Figure 74 for standard pins and in Figure 75 and Figure 76 for true open drain pins Standard Pin Protection To protect the output structure the following ele ments are added A diode to Vpp and a diode from Vss 3b A protection device between Vpp and Vss 4 To protect the input structure the following ele ments are added resistor in series with the pad 1 A diode to Vpp 2a and a diode from Vss 2b A protection device between Vpp and Vss 4 Figure 73 Positive Stress a Standard Pad vs Vss Main path 59 Path to avoid gt 116 140 4 CHARACTERISTICS Cont d True Open Drain Pin Protection The centralized protection 4 is not involved in the discharge of the ESD stresses applied to true open drain pads due to the fact that a P Buffer and diode to Vpp are not implemented An additional local protection between the pad and 5a amp 5b is implemented to completely absorb the posi tive ESD discharge ST72104G ST72215G ST72216G ST722
135. ode Note In 10 bit addressing mode to switch the master to Receiver mode software must generate a repeated Start condition and resend the header sequence with the least significant bit set 11110xx1 Master Receiver Following the address transmission and after SR1 and CR registers have been accessed the master receives bytes from the SDA line into the DR reg ister via the internal shift register After each byte the interface generates in sequence Acknowledge pulse if if the ACK bit is set EVF and BTF bits are set by hardware with an in terrupt if the ITE bit is set Then the interface waits for a read of the SR1 reg ister followed by a read of the DR register holding the SCL line low see Figure 45 Transfer se quencing 7 To close the communication before reading the last byte from the DR register set the STOP bit to generate the Stop condition The interface goes automatically back to slave mode M SL bit cleared Note In order to generate the non acknowledge pulse after the last received data byte the ACK bit must be cleared just before reading the second last data byte 4 2 5 Cont d Master Transmitter Following the address transmission and after 581 register has been read the master sends bytes from the DR register to the SDA line via the inter nal shift register The master waits for a read of the SR1 register fol lowed by a write in the DR register
136. oe be Mia uade ub 96 14 1 4Loading eee ecu x Rm 96 14 1 5Pinnput voltage usce eR amne i ae poU 96 14 2 ABSOLUTE MAXIMUM RATINGS 97 14 2 1 Voltage Characteristics 97 14 2 2Current Characteristics 97 14 2 3Thermal Characteristics 97 14 8 OPERATING CONDITIONS 98 14 3 1 General Operating Conditions 98 14 3 2O0perating Conditions with Low Voltage Detector LVD 100 14 4 SUPPLY CURRENT CHARACTERISTICS 102 14 4 4 RUN and SLOW Modes 102 14 4 2WAIT SLOW WAIT Modes 103 14 4 3 rane Picante postes voten AE Orders aces 104 14 4 4Supply and Clock Managers 104 14 4 50n Chip Peripherals 104 14 5 CLOCK AND TIMING CHARACTERISTICS 105 14 5 1General TimingS 105 14 5 2External Clock Source 105 14 5 3Cr
137. of knowing when that transition will occur therefore the slave device collision occurs when software attempts to write the DR register after its SS pin has been pulled low For this reason the SS pin must be high between each data byte transfer to allow the CPU to write in the DR register without generating a write colli sion In Master mode Collision in the master device is defined as a write of the DR register while the internal serial clock SCK is in the process of transfer The SS pin signal must be always high on the master device WCOL bit The WCOL bit in the SR register is set if a write collision occurs No SPI interrupt is generated when the WCOL bit is set the WCOL bit is a status flag only Clearing the WCOL bit is done through a software sequence see Figure 41 Figure 41 Clearing the WCOL bit Write Collision Flag Software Sequence Clearing sequence after SPIF z 1 end of a data byte transfer isi Step Read SR THEN 2nd Step Read DR CDS Read SR SPIF 20 WCOL 0 if no transfer has started WCOL 1 if a transfer has started before the 2nd step Clearing sequence before SPIF z 1 during a data byte transfer Read SR Read DR 1st Step 2nd Step 66 140 THEN WCOL 0 Note Writing in DR register in stead of reading in it do not reset WCOL bit 4 SERIAL PERIPHERAL INTERFACE Cont d 12 3 4 5 Master Mode Fault Master mode fault occurs when the master device has its S
138. oftware 0 No effect on the pin 1 Forces OLVL1 to be copied to the pin if the bit is set and even if there is no suc cessful comparison Bit 2 OLVL2 Output Level 2 This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R reg ister and is set in the CR2 register This val ue is copied to the OCMP1 pin One Pulse mode and Pulse Width Modulation mode Bit 1 2 IEDG1 nput Edge f This bit determines which type of level transition on the ICAP1 pin will trigger the capture 0 A falling edge triggers the capture 1 A rising edge triggers the capture Bit 0 OLVL1 Output Level 1 The OLVL1 bit is copied to the OCMP1 when ever a successful comparison occurs with the register and the OC1E bit is set in the CR2 register 55 140 ST72104G ST72215G ST72216G ST72254G 16 TIMER CONTROL REGISTER 2 2 Read Write Reset Value 0000 0000 00h 7 0 Bit 7 OC1E Output Compare 1 Pin Enable This bit is used only to output the signal from the timer on the OCMP1 pin OLV1 in Output Com pare mode both OLV1 and OLV2 in PWM and one pulse mode Whatever the value of the OC1E bit the internal Output Compare 1 function of the timer remains active 0 pin alternate function disabled I O pin free for general purpose 1 OCMP1 pin alternate function enabled Bit 6 OC2E Output Compar
139. or is kept loaded with the previous measurement load The advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement 12 5 3 4 Software Procedure Refer to the control status register CSR and data register DR in Section 0 1 6 for the bit definitions and to Figure 2 for the timings ADC Configuration The total duration of the A D conversion is 12 ADC clock periods 1 2 4 57721046 ST72215G ST72216G 57722546 The analog input ports must be configured as in put no pull up no interrupt Refer to the ports chapter Using these pins as analog inputs does not affect the ability of the port to be read as a logic input In the CSR register Select the CH 3 0 bits to assign the analog channel to be converted ADC Conversion In the CSR register Set the ADON bit to enable the A D converter and to start the first conversion From this time on the ADC performs a continuous conver sion of the selected channel When a conversion is complete The COCO bit is set by hardware No interrupt is generated The result is in the DR register and remains valid until the next conversion has ended A write to the CSR register with ADON set aborts the current conversion resets the COCO bit and starts a new conversion Figure 48 ADC Conversion Timings CONTROL Load L COCO BIT SET 24 12 5 4 Low Power Modes
140. ponding indirect addressing mode It also changes an instruction using X indexed addressing mode to an instruc tion using indirect X indexed addressing mode Replace an instruction using X indirect indexed addressing mode by a Y one PIX 92 PIY 91 93 140 ST72104G ST72215G 57722166 ST72254G INSTRUCTION GROUPS Cont d Jump relative always Jump relative Dm wmpretmeng i umpietmemg Lm un JRNH Jump if H 2 0 0 df JRM Jump if 1 1 1 a n s JRNM Jump if 0 1 02 _ JRMI Jump if N 2 1 minus N21 a qn uas SEPE o Tr i EE 7207702702208 22222 noe 94 140 57721046 ST72215G ST72216G 57722546 INSTRUCTION GROUPS Cont d m JRULE Jumpif C Z 1 Unsigned EE E Te a a es La ee ee Pop from the Stack pop reg pop CC 2 rescore semen m 3 mu mm
141. quare wave CSS and LVD disabled 4 SLOW WAIT mode selected with based on fosc divided by 32 All I O pins in input mode with a static value at Vpp or Vss no load all peripherals in reset state clock input OSC1 driven by external square wave CSS and LVD disabled 103 140 4 ST72104G ST72215G ST72216G ST72254G SUPPLY CURRENT CHARACTERISTICS Cont d 14 4 3 HALT Mode 40 lt lt 85 Vpp 5 5V 40 C lt T a lt 125 C Supply current in HALT mode 2 Vpp23 6V 40 lt lt 125 14 4 4 lt previous current consumption specified for Source current consumption To get the total de the ST7 functional operating modes over tempera vice consumption the two current values must be ture range does not take into account the clock added except for HALT mode Supply current of internal RC oscillator Supply current of external RC oscillator 4 LP Low power oscillator 4 amp MP Medium power oscillator MS Medium speed oscillator HS High speed oscillator Supply current of resonator oscillator Notes 1 Typical data are based on 25 2 All I O pins in input mode with a static value at Vpp or 55 no load CSS and LVD disabled Data based on charac terization results tested in production at Vpp max and max 3 Data based on characterization results not tested in production 4 Data based on characteriza
142. riation vs temperature 14 4 1 RUN and SLOW Modes vice consumption the two current values must be added except for HALT mode for which the clock is stopped Conditions Constant Vpp and fopy Condtons Max Uni Supply current in RUN mode 3 see Figure 59 Supply current SLOW mode see Figure 60 Supply current in RUN mode 3 see Figure 59 Supply current in SLOW mode 4 see Figure 60 3 2 lt lt 3 6 4 5 lt lt 5 5 Figure 59 Typical Ipp in RUN vs fcpy IDD mA 4 5 VDD V Notes fosc 1 MHz fcpu 500kHz fosc 4MHz fcpy 2MHz fosc 1 6MHz 8 2 fosc 1 MHz fcpy 31 25kHz fosc 4MHz fcpy 125kHz fosc 1 6MHz fcpu 500kHz fosc 1 MHz fcpy 500kHz fosc 4MHz fcpy 2MHz fosc 1 6MHz 8 2 fosc 1 MHz fcpu 31 25kHz fosc 4MHz fopy 125kHz fosc 1 6MHz fcpu 500kHz Figure 60 Typical Ipp in SLOW vs fepy IDD mA 0 8 500kHz X 125kHz 250kHz 31 25kHz 0 7 0 6 0 5 0 4 0 3 0 2 4 4 5 VDD 1 Typical data are based on TA 25 C Vpp 5V 4 5VxVppx5 5V range VDD 3 4V 3 2V lt Vpp lt 3 6V range 2 Data based on characterization results tested in production at Vpp max and max 3 CPU running with memory access all I O pins in input mode with a static value at Vpp or Vss no load all peripherals in reset state clock input OSC1 driven by external square wave CS
143. rop the device will function below this min level 100 140 7 77 ST72104G 57722156 57722166 57722549 FUNCTIONAL OPERATING CONDITIONS Cont d Figure 56 High LVD Threshold Versus V and fosc for ROM devices 2 fosc MHz FUNCTIONALITY NOT GUARANTEED IN THIS AREA DEVICE UNDER RESET IN THIS AREA FUNCTIONAL AREA SUPPLY VOLTAGE V Figure 57 Medium LVD Threshold Versus V and fosc for ROM devices 2 fosc MHz FUNCTIONALITY NOT GUARANTEED IN THIS AREA DEVICE UNDER RESET IN THIS AREA FUNCTIONAL AREA SUPPLY VOLTAGE V Figure 58 Low LVD Threshold Versus Vp and fosc for ROM devices 2 3 FUNCTIONALITY NOT GUARANTEED IN THIS AREA DEVICE UNDER FUNCTIONAL AREA RESET IN THIS AREA SUPPLY VOLTAGE V 23 00 8 5 Notes 1 LVD typical data are based on T 25 C They are given only as design guidelines and are not tested 2 The minimum V pp rise time rate is needed to insure a correct device power on and LVD reset Not tested in production 3 If the low LVD threshold is selected when Vpp falls below 3 2V the device is guaranteed to be either functioning or under reset 4 101 140 ST72104G ST72215G ST72216G ST72254G 14 4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over tempera ture range does not take into account the clock Source current consumption To get the total de Alpp ara Supply current va
144. ry Multiple Time Programmable Read out memory protection against piracy 4 3 STRUCTURAL ORGANISATION The FLASH program memory is organised in a single 8 bit wide memory block which can be used for storing both code and data constants The FLASH program memory is mapped in the up per part of the ST7 addressing space and includes the reset and interrupt user vector area 4 4 IN SITU PROGRAMMING ISP MODE The FLASH program memory can be programmed using Remote ISP mode This ISP mode allows the contents of the ST7 program memory to be up dated using a standard ST7 programming tools af ter the device is mounted on the application board This feature can be implemented with a minimum number of added components and board area im pact An example Remote ISP hardware interface to the standard ST7 programming tool is described be low For more details on ISP programming refer to the ST7 Programming Specification Remote ISP Overview The Remote ISP mode is initiated by a specific se quence on the dedicated ISPSEL pin The Remote ISP is performed in three steps Selection of the RAM execution mode Download of Remote ISP code in RAM Execution of Remote ISP code in RAM to pro gram the user program into the FLASH Remote ISP hardware configuration In Remote ISP mode the ST7 has to be supplied with power Vpp and Vss and a clock signal os cillator and application crystal circuit for example ky 57721046 ST
145. s 10 3 PORT IMPLEMENTATION The hardware implementation on each I O port de pends on the settings in the DDR and OR registers and specific feature of the port such as ADC In put or true open drain Switching these ports from one state to anoth er should be done in a sequence that prevents un wanted side effects Recommended safe transi tions are illustrated in Figure 22 Other transitions are potentially risky and should be avoided since they are likely to present unwanted side effects such as spurious interrupt generation Table 8 Port Configuration Input DDR 0 1 57721046 57722156 57722166 57722546 Figure 22 Interrupt I O Port State Transitions GD GD GD INPUT INPUT floating reset state OUTPUT open drain OUTPUT floating pull up push pull interrupt DDR OR The I O port register configurations are summa rized as follows Interrupt Ports PA7 PA5 PA3 0 PB7 0 PC5 0 with pull up i True Open Drain Interrupt Ports 6 4 without pull up f loating interrupt input open drain high sink ports Output DDR 1 OR 1 floating pull up interrupt push pull floating pull up interrupt push pull floating floating interrupt PAE foaing foating interrupt 4 33 140 ST72104G ST72215G ST72216G ST72254G PORTS Cont d 10 4 LOW POWER MODES Description WAIT No effect on por
146. s and tested by the JRC and JRNC instructions It is also affected by the bit test and branch shift and rotate instructions 15 140 ST72104G ST72215G ST72216G ST72254G 6 CENTRAL PROCESSING UNIT Cont d Stack Pointer SP Read Write Reset Value 01 7Fh 15 8 0 0 0 0 0 0 0 1 7 0 o se ss sre sro sre ser seo The Stack Pointer is a 16 bit register which is al ways pointing to the next free location in the stack It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack see Figure 7 Since the stack is 128 bytes deep the 9 most sig nificant bits are forced by hardware Following an MCU Reset or after a Reset Stack Pointer instruc tion RSP the Stack Pointer contains its reset val ue the SP6 to SPO bits are set which is the stack higher address Figure 7 Stack Manipulation Example The least significant byte of the Stack Pointer called S can be directly accessed by a LD in struction Note When the lower limit is exceeded the Stack Pointer wraps around to the stack upper limit with out indicating the stack overflow The previously stored information is then overwritten and there fore lost The stack also wraps in case of an under flow The stack is used to save the return address dur ing a subroutine call and the CPU context during an interrupt The user may also directly manipulate the stack by means of the PUSH and
147. s a precau tionary measure The opcode for the HALT instruction is Ox8E To avoid an unexpected HALT instruction due to a program counter failure it is advised to clear all occurrences of the data value Ox8E from memo ry For example avoid defining a constant in ROM with the value Ox8E As the HALT instruction clears the bit in the CC register to allow interrupts the user may choose to clear all pending interrupt bits before execut ing the HALT instruction This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake up event reset or external interrupt 12 1 6 Interrupts None 12 1 7 Register Description CONTROL REGISTER CR Read Write Reset Value 0111 1111 7Fh 7 0 WDGA 6 5 T4 T8 T2 TO Bit 7 WDGA Activation bit This bit is set by software and only cleared by hardware after a reset When WDGA 1 the watchdog can generate a reset 0 Watchdog disabled 1 Watchdog enabled Bit 6 0 T 6 0 7 bit timer MSB to LSB These bits contain the decremented value A reset is produced when it rolls over from 40h to 3Fh T6 becomes cleared ky 57721046 ST72215G ST72216G 57722546 WATCHDOG Table 12 Watchdog Timer Register Map and Reset Values Register WDGCR WDGA T6 T5 Reset Value 0 1 1 4 41 140 ST72104G ST72215G ST72216G ST72254G 12 2
148. s not affected by WAIT mode In HALT mode the counter stops counting until the mode is exited Counting then resumes from the previous count MCU awakened by an interrupt or from the reset count MCU awakened by a Reset 12 2 3 2 External Clock The external clock where available is selected if 0 1 and 1 1 in the CR2 register The status of the EXEDG bit in the CR2 register determines the type of level transition on the exter nal clock pin EXTCLK that will trigger the free run ning counter The counter is synchronised with the falling edge of the internal CPU clock A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock thus the external clock fre quency must be less than a quarter of the CPU clock frequency 4 57721046 ST72215G ST72216G 57722546 16 BIT TIMER Cont d Figure 27 Counter Timing Diagram internal clock divided by 2 epuciock JU UU UUUUUUUU INTERNAL RESET U TIMER CLOCK EN EN EN L COUNTER REGISTER FFFD FFFEj FFFFX 0000 0001 0002 0003 TIMER OVERFLOW FLAG TOF Figure 28 Counter Timing Diagram internal clock divided by 4 cucos JUUUUL AZUUUUUUUUI INTERNAL RESET 2 2 TIMER CLOCK Z4 COUNTER REGISTER FFFC FFFD 0000 0001 OVERFLOW FLAG TOF CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG TOF Note The M
149. s requires only one byte after the opcode but only allows 00 FF address ing space Direct long The address is a word thus allowing 64 Kbyte ad dressing space but requires 2 bytes after the op code 13 1 4 Indexed No Offset Short Long In this mode the operand is referenced by its memory address which is defined by the unsigned addition of an index register X or Y with an offset The indirect addressing mode consists of three sub modes Indexed No Offset There is no offset no extra byte after the opcode and allows 00 FF addressing space Indexed Short The offset is a byte thus requires only one byte af ter the opcode and allows 00 1FE addressing space Indexed long The offset is a word thus allowing 64 Kbyte ad dressing space and requires 2 bytes after the op code 13 1 5 Indirect Short Long The required data byte to do the operation is found by its memory address located in memory point er The pointer address follows the opcode The indi rect addressing mode consists of two sub modes Indirect short The pointer address is a byte the pointer size is a byte thus allowing 00 FF addressing space and requires 1 byte after the opcode Indirect long The pointer address is a byte the pointer size is a word thus allowing 64 Kbyte addressing space and requires 1 byte after the opcode 91 140 ST72104G ST72215G ST72216G ST72254G ST7 ADDRESSING MODES Cont
150. s which type of level transition on the external clock pin EXTCLK will trigger the counter register 0 A falling edge triggers the counter register 1 A rising edge triggers the counter register 4 16 STATUS REGISTER SR Read Only Reset Value 0000 0000 00h The three least significant bits are not used 7 0 Bit 7 1 1 nput Capture Flag 1 0 No input capture reset value 1 An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode To clear this bit first read the SR register then read or write the low byte of the IC1R IC1LR register Bit 6 OCF1 Output Compare Flag 1 0 No match reset value 1 The content of the free running counter matches the content of the OC1R register To clear this bit first read the SR register then read or write the low byte of the OC1LR register Bit 5 TOF Timer Overflow Flag 0 No timer overflow reset value 1 The free running counter has rolled over from FFFFh to 0000h To clear this bit first read the SR register then read or write the low byte of the CR CLR register Note Reading or writing the ACLR register does not clear TOF Bit 4 ICF2 nput Capture Flag 2 0 No input capture reset value 1 An input capture has occurred on the ICAP2 pin To clear this bit first read the SR register then read or write the low byte of the IC2R IC2LR
151. selection can be optimized in terms of supply current using an high quality resonator with small Rs value Refer to ceramic resonator manufacturer for more details 108 140 57721046 ST72215G ST72216G 57722546 CLOCK AND TIMING CHARACTERISTICS Cont d Table 23 Ceramic Resonator Frequency Correlation Factor Option Corre MP CSTSO400MGUS 030 CSTSO400MGUS 030 MS Notes 74HCU04 Corre lation CSTS0800MG06 CSTS0800MGA06 74HCU04 Option Refer ence IC CSTCC8 00MGOH6 CSTS1000MG03 40 34 4069UBP CSTCC10 0MG 4069UBE Byte Resonator lation Pefer Byte Resonator Config ence Ig Config 65810000 CSTCC2 00MG0H6 0 10 CSTS0200MG06 0 15 CSTCC2 00MGOH6 0 14 74 004 009 1 See Table 21 and Table 22 for ceramic resonator values 109 140 ST72104G ST72215G ST72216G ST72254G CLOCK CHARACTERISTICS Cont d 14 5 4 RC Oscillators The ST7 internal clock can be supplied with an RC or external components selectable by option oscillator This oscillator can be used with internal byte Fames ar Vui Internal RC oscillator frequency see Figure 67 3 60 Es Mis osc 4 RG Startup Te isu oso 0 Rex 47KQ Cey 0 pF 1 0 3 Rex 47KQ Cey 1 OOpF ms External RC Oscillator Star
152. t up Time Rey 10KQ Cey 6 8pF Rex 1 Cgx 470pF Oscillator external resistor EX see Figure 68 Oscillator external capacitor Figure 66 Typical Application with RC oscillator EXTERNAL RC Voltage generator Figure 68 Typical External RC Oscillator fosc MHz 20 Rex 10KOhm gt Rex 15KOhm Rex 22KOhm K Rex 33KOhm Rex 39KOhm 9 Rex 47KOhm 15 VDD V Notes 1 Data based on characterization results 2 Guaranteed frequency range with the specified and Rex ranges taking into account the device process variation Data based on design simulation 3 Data based on characterization results done with Vpp nominal at 5V not tested in production 4 Rex must have a positive temperature coefficient ppm C carbon resistors should therefore not be used 5 Important when no external is applied the capacitance to be considered is the global parasitic capacitance which is subject to high variation package application In this case the RC oscillator frequency tuning has to be done by trying out several resistor values 110 140 57721046 ST72215G 57722166 57722546 CLOCK CHARACTERISTICS Cont d 14 5 5 Clock Security System CSS 25 Vpp 5 0V 250 340 550 f Safe Oscillator Frequency 1 Ac S Ce 250 340 550 kHz Glitch Filtered Frequency Figur
153. ternate functions To enable the 2 interface write the CR register TWICE with PE 1 as the first write only activates the interface only PE is set Bit 4 ENGC Enable General Call This bit is set and cleared by software It is also cleared by hardware when the interface is disa bled PE 0 The 00h General Call address is ac knowledged 01h ignored 0 General Call disabled 1 General Call enabled Bit 3 START Generation of a Start condition This bit is set and cleared by software It is also cleared by hardware when the interface is disa bled PE 0 or when the Start condition is sent with interrupt generation if ITE 1 master mode 0 No start generation 1 Repeated start generation n slave mode 0 No start generation 1 Start generation when the bus is free 80 140 Bit 2 ACK Acknowledge enable This bit is set and cleared by software It is also cleared by hardware when the interface is disa bled 0 0 No acknowledge returned 1 Acknowledge returned after an address byte or a data byte is received Bit 1 STOP Generation of a Stop condition This bit is set and cleared by software It is also cleared by hardware in master mode Note This bit is not cleared when the interface is disabled 0 In master mode 0 No stop generation 1 Stop generation after the current byte transfer or after the current Start condition is sent The STOP bit is cleared by hardware whe
154. the configuration occurs for example due to a corrupted program counter To guarantee safe operation this connection has to be done through a pull up or pull down resistor typical 4 7kQ for RESET 10kQ for I Os Unused I O pins must be tied in the same way to Vpp or Vgg according to their reset configuration 2 When the current limitation is not possible the Vi absolute maximum rating must be respected otherwise refer to IiNJ PIN Specification A positive injection is induced by Viy Vpp while a negative injection is induced by Viy Vss 3 All power Vpp and ground Vss lines must always be connected to the external supply 4 Negative injection disturbs the analog performance of the device In particular it induces leakage currents throughout the device including the analog inputs To avoid undesirable effects on the analog functions care must be taken Analog input pins must have a negative injection less than 0 8 mA assuming that the impedance of the analog voltage is lower than the specified limits Pure digital pins must have a negative injection less than 1 6mA In addition it is recommended to inject the current as far as possible from the analog input pins 5 When several inputs are submitted to a current injection the maximum Xi is the absolute sum of the positive and negative injected currents instantaneous values These results are based characterisation with Xy maxi mum current injection o
155. the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock see Figure 40 The SS pin must be connected to a high level signal during the complete byte transmit se quence The MSTR and SPE bits must be set they re main set only if the SS pin is connected to a high level signal 62 140 In this configuration the MOSI pin is a data output and to the MISO pin is a data input Transmit sequence The transmit sequence begins when a byte is writ ten the DR register The data byte is parallel loaded into the 8 bit shift register from the internal bus during a write cycle and then shifted out serially to the MOSI pin most significant bit first When data transfer is complete The 5 bit is set by hardware An interrupt is generated if the SPIE bit is set and the bit in the register is cleared During the last clock cycle the SPIF bit is set a copy of the data byte received in the shift register is moved to a buffer When the DR register is read the SPI peripheral returns this buffered value Clearing the SPIF bit is performed by the following software sequence 1 An access to the SR register while the SPIF bit is set 2 A read to the DR register Note While the SPIF bit is set all writes to the DR register are inhibited until the SR register is read 4 SERIAL PERIPHERAL INTERFACE 12 3 4 2 Slave Configuration In slave
156. tion results done with the external components specified in Section 14 5 3 and Section 14 5 4 not tested in production 5 As the oscillator is based on a current source the consumption does not depend on the voltage 6 Data based on a differential Ipp measurement between reset configuration timer counter running at fcpu 4 and timer counter stopped selecting external clock capability Data valid for one timer 7 Data based a differential Ipp measurement between reset configuration and a permanent SPI master communica tion data sent equal to 55h 8 Data based a differential Ipp measurement between reset configuration and I2C peripheral enabled PE bit set 9 Data based on a differential Ipp measurement between reset configuration and continuous A D conversions 4 104 140 57721046 ST72215G ST72216G 57722546 14 5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for Vpp fosc and Ta 14 5 1 General Timings Instruction cycle time t Interrupt reaction time 2 D Hym Afgqsr 10 14 5 2 External Clock Source OSC1 input pin high level voltage OSC1 input pin low level voltage OSC1 high or low time 3 see Figure 63 tw OSC1L OSC1 rise or fall time 3 OSC1 90 eos 10 1 we V OSCIL EXTERNAL CLOCK SOURCE JUUL ST72XXX Notes 1 Data based on typical application software 2 Time measured between interrupt event and i
157. tions consist of 128 bytes of register location 256 bytes of RAM and up to 8Kbytes of user program memory The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh The highest address bytes contain the user reset and interrupt vectors Figure 4 Memory Map HW Registers see Table 2 256 Bytes RAM Reserved Program Memory 4K 8 KBytes Interrupt amp Reset Vectors see Table 5 on page 26 10 140 IMPORTANT Memory locations marked as Re served must never be accessed Accessing a re served area can have unpredictable effects on the device Short Addressing RAM Zero page 128 Bytes Stack or 16 bit Addressing RAM 128 Bytes 8 KBytes 4 KBytes 4 57721046 ST72215G ST72216G 57722546 Table 2 Hardware Register Register 2 Reset Port C Data Register 00h 1 Port C Port C Data Direction Register 00h Port C Option Register 00h Reserved 1 Byte Port B Data Register 00h R W Port Data Direction Register 00h R W Port B Option Register 00h R W Reserved 1 Byte 0003h 0007h Port A Data Register 00h 1 R W Port A Port A Data Direction Register 00h R W Port A Option Register 00h R W 000Bh to Reserved 21 Bytes 001Fh 0020h MISCR1 Miscellaneous Register 1 00h R W SPI Data I O Register xxh R W SPI SPI Control Register Oxh R W SPI Status Register 00h Read Only W 0024h ATCHDOG WDGCR Watchdog Control Register 7F
158. ts External interrupts cause the device to exit from WAIT mode HALT No effect on ports External interrupts cause the device to exit from HALT mode 10 5 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the I bit in the CC reg ister is reset RIM instruction Interrupt Event External interrupt on p DDRx selected external Yes Yes ORx event 10 6 REGISTER DESCRIPTION DATA REGISTER DR Port x Data Register PxDR with x A B or C Read Write Reset Value 0000 0000 00h 7 0 D7 D6 D5 D4 D3 D2 D1 DO Bit 7 0 D 7 0 Data register 8 bits The DR register has a specific behaviour accord ing to the selected input output configuration Writ ing the DR register is always taken into account even if the pin is configured as an input this allows always having the expected level on the pin when toggling to output mode Reading the DR register returns either the DR register latch content pin configured as output or the digital value applied to the I O pin pin configured as input 34 140 DATA DIRECTION REGISTER DDR Port x Data Direction Register PxDDR with x A B or C Read Write Reset Value 0000 0000 00h 7 0 DD7 DD6 DDS DD4 DD3 DD2 DD1 DDO Bit 7 0 DD 7 0 Data direction register 8 bits The DDR register gives t
159. ts The di agram may be interpreted as a master or slave timing diagram where the SCK pin the MISO pin the MOSI pin are directly connected between the master and the slave device The SS pin is the slave device select input and can be driven by the master device Figure 39 SS Timing Diagram MOSI MISO Master SS The master device applies data to its MOSI pin clock edge before the capture clock edge CPHA bit is set The second edge on the SCK pin falling edge if the CPOL bit is reset rising edge if the CPOL bit is set is the MSBit capture strobe Data is latched on the occurrence of the second clock transition No write collision should occur even if the SS pin stays low during a transfer of several bytes see Figure 39 CPHA bit is reset The first edge on the SCK pin falling edge if CPOL bit is set rising edge if CPOL bit is reset is the MSBit capture strobe Data is latched on the oc currence of the first clock transition The SS pin must be toggled high and low between each byte transmitted see Figure 39 To protect the transmission from a write collision a low value on the SS pin of a slave device freezes the data in its DR register and does not allow it to be altered Therefore the SS pin must be high to write a new data byte in the DR without producing a write collision ae 7 Slave SS 0 ee a ee Slave SS CPHA 1 64 140 VR02131A 57721046 ST7221
160. ts of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics 02001 STMicroelectronics All Rights Reserved Purchase of 2 Components by STMicroelectronics conveys a license under the Philips Patent Rights to use these components in an system is granted provided that the system conforms to the Standard Specification as defined by Philips STMicroelectronics Group of Companies Australia Brazil China Finland France Germany Hong Kong India Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom U S A http www st com 4 140 140
161. us to another master An interrupt is generated if ITE 1 It is cleared by soft ware reading SR2 register or by hardware when the interface is disabled PE 0 After an ARLO event the interface switches back automatically to Slave mode M SL 0 The SCL line is not held low while ARLO 1 0 No arbitration lost detected 1 Arbitration lost detected Bit 1 BERR Bus error This bit is set by hardware when the interface de tects a misplaced Start or Stop condition An inter rupt is generated if ITE 1 It is cleared by software reading SR2 register or by hardware when the in terface is disabled PE 0 The SCL line is not held low while BERR 1 0 No misplaced Start or Stop condition 1 Misplaced Start or Stop condition Bit 0 GCAL General Call Slave mode This bit is set by hardware when a general call ad dress is detected on the bus while ENGC 1 It is cleared by hardware detecting a Stop condition STOPF 1 or when the interface is disabled 0 0 No general call address detected on bus 1 general call address detected on bus 4 2 BUS INTERFACE Cont d CLOCK CONTROL REGISTER CCR Read Write Reset Value 0000 0000 00h 7 0 Bit 7 FM SM Fast Standard C mode This bit is set and cleared by software It is not cleared when the interface is disabled PE 0 0 Standard 12 mode 1 Fast 12 mode Bit 6 0 CC6 CCO 7 bit clock divider These bits select the speed of the bus
162. ystal and Ceramic Resonator Oscillators 106 14 5 4 RC Oscillators a E Bee eee d 110 14 5 5Clock Security System CSS 111 14 6 MEMORY CHARACTERISTICS 112 14 6 1 and Hardware Registers 112 14 6 2FLASH Program Memory 112 14 7 EMG CHARACTERISTICS sensona tees E SD 113 14 7 1Functional EMS 113 14 7 2Absolute Electrical Sensitivity 114 14 7 3ESD Pin Protection Strategy 116 14 8 PORT PIN CHARACTERISTICS 4 140 Table of Contents 14 8 1 Characteristics 118 14 8 2Output Driving 119 14 9 CONTROL PIN CHARACTERISTICS 121 14 9 1 Asynchronous RESET Pin 121 14 9 2ISPSEL Pin 202 Robe den Oe ds 123 14 10 TIMER PERIPHERAL CHARACTERISTICS 124 14 10 TWatchdog Timer 2 Gees 124 1410 216 Bit Timer pts Ten ar ois tae be 124 14 11 COMMUN

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