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ST ST72101/ST72212/ST72213 handbook

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1. TimerA 32 CR1 ICIE OCIE TOIE FOLV2 FOLV 1 OLVL2 IEDG 1 OLVL1 TimerA 31 CR2 OC2E OPM PWM CC1 CCO IEDG2 EXEDG TimerA 33 SR ICF1 OCF1 TOF ICF2 OCF2 mese o o 9 TimerA 34 IC1HR MSB LSB messes c o o TimerA 35 ICALR MSB LSB gt TimerA 36 OC1HR MSB LSB o o bo TimerA 37 OC1LR MSB TimerA 3E OC2HR TimerA 3A ACHR MSB TimerA 3B ACLR MSB TimerA 3C IC2HR MSB TimerA 3D IC2LR MS 4 48 84 4 4 SERIAL PERIPHERAL INTERFACE SPI 4 4 1 Introduction The Serial Peripheral Interface SPI allows full duplex synchronous serial communication with external devices An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves The SPI is normally used for communication be tween the microcontroller and external peripherals or another microcontroller Refer to the Pin Description chapter for the device specific pin out 4 4 2 Main Features Full duplex three wire synchronous transfers Master or slave operation Four master mode frequencies Maximum slave mode frequency fCPU 2 Four programmable master bit rates Programmable clock polarity and phase End of transfer interrupt flag Write collision flag protection Master mode fau
2. 1 2 4 5 7 PCO AINO PC1 AIN1 PC2 CLKOUT AIN2 Vss TEST V pp PA1 PA2 4 5 7 PC1 PC2 CLKOUT ST72101 ST72212 ST72213 Figure 5 ST72212 Pinout SDIP32 RESET OSCIN OSCOUT SS PB7 SCK PB6 MISO PB5 MOSI PB4 NC NC OCMP2_A PB3 ICAP2_A PB2 OCMP1_A PB1 ICAP1_A PBO AINS EXTCLK 5 2 4 AIN3 ICAP2_B PC3 1 Vop on EPROM OTP only Serge RESET OSCIN OSCOUT SS PB7 SCK PB6 MISO PB5 MOSI PB4 NC NC OCMP2_A PB3 ICAP2_A PB2 OCMP1 ICAP1_A PBO AINS EXTCLK_A PC5 AIN4 PC4 AIN3 PC3 OSCOUT SS PB7 SCK PB6 MISO PB5 MOSI PB4 NC NC OCMP2_A PB3 ICAP2_A PB2 OCMP1_A PB1 ICAP1_A PBO EXTCLK_A PC5 PC4 PC3 Vss TEST V pp 1 2 NC NC PA4 PAS 6 7 PCO ICAP1_B AINO PC1 OCMP1_B AIN1 PC2 CLKOUT AIN2 Vss TEST V PAO 2 NC NC PA4 5 7 PCO AINO PC1 AIN1 PC2 CLKOUT AIN2 Vss TEST V pp PAO PA1 PA2 NC NC PA4 PAS PA6 7 PC1 PC2 CLKOUT 5 84 ST72101 ST72212 ST72213 Table 1 ST72212 Pin Configuration EE 1 RESET vo Bidirectional Active low Top priority non maskable interrupt 7 Input O
3. z 13 mc o e LmugE mpic o wmprG 220 _ 69 84 ST72101 ST72212 ST72213 INSTRUCTION GROUPS Cont d ee PE mur FA wos m d Pop the Stack pop reg pop CC EE m mer usan mw emere oom _ LN mo e L mu mmenae ETE gt CC wwe oat baa Wwe wwe wer i L LIS 70 84 6 ELECTRICAL CHARACTERISTICS 6 1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages how ever it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages For proper operation it is recommended that V and be higher than Vss and lower than Vpp Reliability is enhanced if unused inputs are con nected to an appropriate logic voltage level or Vsg ST72101 ST72212 ST72213 Power Considerations The average chip junc tion temperature Ty in Celsius ca
4. September 1999 1 84 Table of Contents 1 GENERAL DESCRIPTION cio EET Games 4 1 1 INTRODUCTION 22 56 bd Gee Rend ona 4 1 2 PIN DESCRIPTION 4 5 1 3 EXTERNAL 1 1 9 1 4 MEMORY occ e A a We eed 10 2 CENTRAL PROCESSING UNIT 13 2 1 INTRODUCTION 2 ce e am a n me spell 13 2 2 MAIN FEATURES txt Eee me ba dees e hes 13 2 3 GPU REGISTERS genau Ave reu uu cad dae dO We as 13 3 CLOCKS RESET INTERRUPTS amp POWER SAVING MODES 16 3 1 CLOCK SYSTEM sei ebd eae eS thee ea eee a 16 3 1 1 General Description 1 16 32 RESET ebrei eu Oe dee cnet LM ut 17 3 2 1 drittodUctiODk Seite wed RES has bap bod She 17 3 2 2 External Reset eee ee 17 3 2 3 Reset Operation asic 2254s x dade awed eS 17 3 2 4 Poweron Reset Used Rn ra b tee o bade 17 3 9 INTERRUPTS sacs RR PRAES EI A BUR ee Bae oe een 18 3 4 POWER SAVING MODES 2 5 ceed
5. 57721011511 ST72101 ST72212 ST72213 8 BIT MCU WITH 4 TO 8K ROM OTP EPROM 256 BYTES RAM ADC WDG SPI AND 1 OR 2 TIMERS DATASHEET User Program Memory ROM OTP EPROM 4 to 8K bytes Data RAM 256 bytes including 64 bytes of stack Master Reset and Power On Reset Run Wait Slow and RAM Retention modes m 22 multifunctional bidirectional I O lines 22 programmable interrupt inputs 8 high sink outputs 6 analog alternate inputs 10 to 14 alternate functions EMI filtering Programmable watchdog WDG One or two 16 bit Timers each featuring 2 Input Captures 2 Output Compares External Clock input on Timer A only CSDIP32W PWM and Pulse Generator modes m Synchronous Serial Peripheral Interface SPI 8 bit Analog to Digital converter 6 channels ST72212 and ST72213 only 8 bit Data Manipulation 63 Basic Instructions 17 main Addressing Modes 8 x 8 Unsigned Multiply Instruction True Bit Manipulation Complete Development Support on PC DOS WINDOWS Real Time Emulator Full Software Package on DOS WINDOWS C Compiler Cross Assembler Debugger Features 817210190 517221262 RAM stack bytes ____ one ro i esd PSDIP32 gt See ordering information the end of datasheet Device Summary 3105 5 V 8MHz max 16 2 oscillator 4MHz max over 85 C Rev 1 7
6. The DR register has a specific behaviour accord ing to the selected input output configuration Writ ing the DR register is always taken in account even if the pin is configured as an input Reading the DR register returns either the DR register latch content pin configured as output or the digital val ue applied to the I O pin pin configured as input 4 1 4 2 Data direction registers Port A Data Direction Register PADDR Port B Data Direction Register PBDDR Port C Data Direction Register PCDDR Read Write Reset Value 0000 0000 00h input mode 7 0 oor one Bit 7 0 DD7 DDO Data Direction Register 8 bits The DDR register gives the input output direction configuration of the pins Each bit is set and cleared by software 0 Input mode 1 Output mode 28 84 4 1 4 3 Option registers Port A Option Register PAOR Port B Option Register PBOR Port Option Register Read Write Reset Value 0000 0000 00h no interrupt 7 0 Bit 7 0 7 0 Option Register 8 bits For specific I O pins this register is not implement ed In this case the DDR register is enough to se lect the I O pin configuration The OR register allow to distinguish in input mode if the interrupt capability or the floating configura tion is selected in output mode if the push pull or open drain configuration is selected Each bit is set and cleared by sof
7. e Clock SCK high time 2 100 Clock 5 low time 100 Data set up time ihe Data hold time inputs Access time time to data active from high 1 state Slave Disable time hold time to high im pedance state Master before capture edge 0 25 Slave enable edge Master before capture edge 0 25 Slave enable edge 0 Outputs SCK MOSI MISO 20 to 70 Vpp 200pF Inputs SCK MOSI MISO SS Fall time Outputs SCK MOSI MISO 70 to 20 Vpp 200pF Inputs SCK MOSI MISO SS Measurement points are Vij and Vj in the SPI Timing Diagram Figure 43 SPI Master Timing Diagram CPHA 0 CPOL 0 55 INPUT SCK OUTPUT MISO DON ___ INPUT 3 DO IN SEEN OUTPUT D6 OUT 00 VR000109 77 84 4 ST72101 ST72212 ST72213 SPI CHARACTERISTICS Conta Measurement points are Vi and in the SPI Timing Diagram Figure 44 SPI Master Timing Diagram CPHA 0 CPOL 1 SCK OUTPUT so 5 Co XXXX 1 Mos OUT X OUTPUT a DO OUT VR000110 SCK OUTPUT er F MISO X C DOOUT INPUT x DO OUT OUTPUT gm D6 IN DO IN LILLLU I VR000107 SCK OUTPUT 1 1 1 INPUT 2 D6 IN DO IN XXX 2 1 1 6 11 H FR 1 vos gt OUTPUT D7 OUT D6 OUT D0 OUT 11011 1
8. 5 When the Pulse Width Modulation PWM and One Pulse Mode OPM bits are both set the PWM mode is the only active one ST72101 ST72212 ST72213 16 BIT TIMER Cont d 4 3 4 Low Power Modes Description WAIT No effect on 16 bit Timer Timer interrupts cause the device to exit from WAIT mode If an input capture event occurs on the ICAP pin the input capture detection circuitry is armed Consequent ly when the MCU is woken up by an interrupt with exit from HALT mode capability the ICF bit is set and the counter value present when exiting from HALT mode is captured into the IC R register 16 bit Timer registers are frozen In HALT mode the counter stops counting until Halt mode is exited Counting resumes from the previous count when the MCU is woken up by an interrupt with exit from HALT mode capability or from the counter HALT reset value when the MCU is woken up by a RESET 4 3 5 Interrupts Interrupt Event Input Capture 1 event Counter reset in PWM mode ICF1 Input Capture 2 event ICF2 Output Compare 1 event not available in PWM mode OCF1 OCIE ee Output Compare 2 event not available in PWM mode OCF2 Yes No TmerOwrowswm ves Note The 16 bit Timer interrupt events are con nected to the same interrupt vector see Interrupts chapter These events generate an interrupt if the corre sponding Enable Control Bit is set and the I bit in the CC register is reset RIM i
9. Falling edge only Rising edge only Rising and falling edge Note Any modification of one of these two bits re sets the interrupt request related to this interrupt vector Bit 1 2 Unused always read at 0 Warning Software must write 1 to these bits for compatibility with future products Bit 0 SMS Slow Mode Select This bit is set and cleared by software 0 Normal mode Oscillator frequency 2 Reset state 1 Slow mode Oscillator frequency 32 23 84 ST72101 ST72212 ST72213 4 ON CHIP PERIPHERALS 4 1 1 0 PORTS 4 1 1 Introduction The I O ports offer different functional modes transfer of data through digital inputs and outputs and for specific pins analog signal input ADC alternate signal input output for the on chip pe ripherals external interrupt generation An port is composed of up to 8 pins Each pin can be programmed independently as digital input with or without interrupt generation or digital out put 4 1 2 Functional Description Each port is associated to 2 main registers Data Register DR Data Direction Register DDR and some of them to an optional register Option Register OR Each pin may be programmed using the corre sponding register bits in DDR and OR registers bit X corresponding to pin X of the port The same cor respondence is used for the DR register The following description takes into acc
10. Note Interrupts requested while is set are latched and can be processed when is cleared By default an interrupt routine is not interruptable because the bit is set by hardware when you en 14 84 ter it and reset by the IRET instruction at the end of the interrupt routine If the bit is cleared by soft ware in the interrupt routine pending interrupts are serviced regardless of the priority level of the cur rent interrupt routine Bit 2 N Negative This bit is set and cleared by hardware It is repre sentative of the result sign of the last arithmetic logical or data manipulation It is a copy of the 7 bit of the result 0 The result of the last operation is positive or null 1 The result of the last operation is negative i e the most significant bit is a logic 1 This bit is accessed by the JRMI and JRPL instruc tions Bit 1 2 Z Zero This bit is set and cleared by hardware This bit in dicates that the result of the last arithmetic logical or data manipulation is zero 0 The result of the last operation is different from zero 1 The result of the last operation is zero This bit is accessed by the JREQ and JRNE test instructions Bit 0 C Carry borrow This bit is set and cleared by hardware and soft ware It indicates an overflow or an underflow has occurred during the last arithmetic operation 0 No overflow or underflow has occurred 1 An overflow or underflow has occurred Thi
11. fetes whe deed ee ees 21 3 41 Introduction searre RESTI exc ee de deca 21 3 4 2 Slow RR oes ees Ree 21 9 4 9 oe ede RC aes 21 3 44 Mode Ra iad en Xa esee le ee ac a 22 3 5 MISCELLANEOUS REGISTER 0 4440 ads Peed ede 23 4 PERIPHERALS cette eee ee eee we eee 24 AL WO RON jc ETT 24 24 4 1 2 Functional Description ree RR Reap ee 24 4 1 3 Port Implementation 25 4 1 4 Register Description 2 28 4 2 WATCHDOG TIMER WDG 30 4 21 INTOQUCHION oed ete Dur td end ee dur 30 422 Features sues ee ee ke mee EDAN 44 44 44 30 4 2 3 Functional Description rr ERREUR 31 4 2 4 Low Power Modes 31 4 2 5 Interrupts a de oe db dade bees ae bea ded s 31 4 2 6 Register Description
12. 31 4 3 16 BIT TIMER dee eden DEED ed ee eee eee 32 4 3 1 IntroductiOm nesses ne ete dbo eee 32 432 Features dee ed eee a 32 4 3 3 Functional Description 1 2 4 eee 32 4 3 4 Low Power Modes 43 4 3 0 Interr pts oss sse oe ee ee Bass 43 4 3 6 Register Description 1 44 2 84 477 Table of Contents 4 4 SERIAL PERIPHERAL INTERFACE SPI 49 4 4 1 Introduction 4 49 4 4 2 Main Features 1 49 4 4 8 General description 49 4 4 4 Functional Descripti0N 1 035 51 4 4 5 Low Power Modes 58 4 4 6 Intertupts ded ead new be AA ww ewes 58 4 4 7 Register Description 59 4 5 8 BIT A D CONVERTER 62 4 9 1 INTFOUCI N oues ue ao 62 45 2 Features ree b REX 62 4 5 3 Functional Descripti0N 2 63 4 5 4 Low Power Modes
13. DEVICE PACKAGE RANGE B Plastic DIP M Plastic SOIC ST72T101G1 ST72T101G2 ST721212G2 ST721213G1 Note The ST72E251G2D0 CERDIP 25 C is used as the EPROM version for the above devices 82 84 ST72101 ST72212 ST72213 ST72101 ST72213 and ST72212 MICROCONTROLLER OPTION LIST Customer Address Contact Phone No Reference STMicroelectronics references Device 161772101 ST72212 ST72213 Package Dual in Line Plastic Small Outline Plastic with conditioning 1 Standard Stick Tape amp Reel Temperature Range 0 C to 70 C 40 C 85 C 40 C to 125 C Special Marking No Yes Authorized characters are letters digits and spaces only Maximum character count SDIP32 10 5028 8 Comments Supply Operating Range in the application Oscillator Frequency in the application Notes Signature T 83 84 ST72101 ST72212 ST72213 8 SUMMARY OF CHANGES Change Description Rev 1 5 to 1 6 Added new External Connections section Removed RP external resistor Changed ORed to ANDed in External interrupts paragraph to read If several input pins con nected to the same interrupt vector are configured as interrupts their signals are logically AN 18 and 24 Ded before entering the edge level detection block Added note modification of one of these two bits resets the interrupt request related to this interrupt vector Added clamp
14. The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time thus disabling the slave devices Note To prevent a bus conflict on the MISO line the master allows only one slave device during a transmission Figure 38 Single Master Configuration For more security the slave device may respond to the master with the received data byte Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are con nected and the slave has not written its DR regis ter Other transmission security methods can use ports for handshake lines or data bytes with com mand fields Multi master System A multi master system may also be configured by the user Transfer of master control could be im plemented using a handshake method through the ports or by an exchange of code messages through the serial peripheral interface system The multi master system is principally handled by the MSTR bit in the CR register and the MODF bit in the SR register 57 84 ST72101 ST72212 ST72213 SERIAL PERIPHERAL INTERFACE 4 4 5 Low Power Modes Description WAIT No effect on SPI SPI interrupt events cause the device to exit from WAIT mode SPI registers are frozen HALT In HALT mode the SPI is inactive SPI operation resumes when the MCU is woken up by an interrupt with exit from HALT mode capability 4 4 6 Interrupts Enable In
15. CALLR Call Relative The relative addressing mode consists of two sub modes Relative Direct The offset is following the opcode Relative Indirect The offset is defined in memory which address follows the opcode 67 84 ST72101 ST72212 ST72213 5 2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions The instructions may be subdivided into 13 main groups as illustrated in the following table sra itc a o ewe s Conditional management TRAP rnc pier Gode Condon Fao modico sim RIM se mcr _ Using a pre byte The instructions are described with one to four bytes In order to extend the number of available op codes for an 8 bit CPU 256 opcodes three differ ent prebyte opcodes are defined These prebytes modify the meaning of the instruction they pre cede The whole instruction becomes PC 2 End of previous instruction PC 1 Prebyte PC opcode PC 1 Additional word 0 to 2 according to the number of bytes required to compute the ef fective address 68 84 These prebytes enable instruction in Y as well as indirect addressing modes to be implemented They precede the opcode of the instruction in X or the instruction using direct addressing mode The prebytes are PDY 90 Replace an X based instruction using immediate direct indexed or inherent ad dressing mode by a Y
16. Figure 51 28 Pin Small Outline Package 300 mil Width 80 84 mm ms om Tr Tuc i Ts Papes zes wows Er oro o3 noon oss foo Fc ozs ose poor 00125 o i770 07125 Fe oz pep je Pa fron foafoa fons n fo oov 8 Lee Figure 52 32 Pin Shrink Plastic Dual In Line Package VR01725J Figure 53 32 Pin Shrink Ceramic Dual In Line Package CDIP32SW ST72101 ST72212 ST72213 m bv a ec we a sse 576 sos 2 je sos ss 57 o 2oo30 185 fose oss aora oae noz Cr oe o2 40 eras ar se 2a as 0601100 0 ser roa rros oaoo ono oss 7 62 s oo oso ro pee Fe res enm ss Number mm ches Ras Bep pL pe ose _ oss 25 058 ons pore 025 Fer oss oce oss oss par poer oso vise 202 ew Fer sas ss rose os72 so oos Fe iret gt __ Fe d S of Pins gt 81 84 ST72101 ST72212 ST72213 7 3 ORDERING I
17. OLVL1 OLVL2 compare2 comparet compare2 Note OC1R22bEDOh OC2R 34E2 OLVL1 0 OLVL2 1 ki 41 84 ST72101 ST72212 ST72213 16 BIT TIMER Cont d 4 3 3 7 Pulse Width Modulation Mode Pulse Width Modulation PWM mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers The pulse width modulation mode uses the com plete Output Compare 1 function plus the OC2R register and so these functionality can not be used when the PWM mode is activated Procedure To use pulse width modulation mode 1 Load the OC2R register with the value corre sponding to the period of the signal 2 Load the register with the value corre sponding to the length of the pulse if 1 0 and OLVL2 1 3 Select the following in the CR1 register Using the OLVL 1 bit select the level to be ap plied to the OCMP1 pin after a successful comparison with OC1R register Using the OLVL2 bit select the level to be ap plied to the OCMP1 pin after a successful comparison with OC2R register 4 Select the following in the CR2 register Set bit the pin is then dedicat ed to the output compare 1 function Set the PWM bit Select the timer clock 1 see Table 15 If OLVL1 1 and OLVL2 0 the length of the posi tive pulse is the difference between the OC2R and OCAR registers If OLVL1 OLVL2 a continuous si
18. Reading this register reset the COCO flag AD6 AD5 AD4 AD3 AD2 AD1 ADO 0 0 0 0 0 0 0 71 CSR COCO ADON CH2 CH1 CHO Reset Value 0 0 0 0 0 64 84 5 INSTRUCTION SET 5 1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups Rairessing Mode Example me _ The ST7 Instruction set is designed to minimize the number of bytes required per instruction To do Table 21 ST7 Addressing Mode Overview Pointer Syntax rar Address Size Hex Hex A ST72101 ST72212 ST72213 so most of the addressing modes may be subdi vided in two sub modes called long and short Long addressing mode is more powerful be cause itcan use the full 64 Kbyte address space however it uses more bytes and more CPU cy cles Short addressing mode is less powerful because it can generally only access page zero 0000h OOFFh range but the instruction size is more compact and faster All memory to memory in structions use short addressing modes only CLR CPL NEG BSET BRES BTJT BTJF INC DEC RLC RRC SLL SRL SRA SWAP The ST7 Assembler optimizes the use of long and short addressing modes Pointer YA feao i _ rong Bret o Short Id A 10 X 00 1FE 7 0 with X register 1 with Y register
19. a stabilisation time before accurate conversions can performed 4 5 5 Interrupts None 63 84 ST72101 ST72212 ST72213 8 A D CONVERTER ADC 4 5 6 Register Description CONTROL STATUS REGISTER CSR Read Write Reset Value 0000 0000 00h 7 0 Bit 7 COCO Conversion Complete This bit is set by hardware It is cleared by soft ware reading the resultin the DR register or writing to the CSR register 0 Conversion 15 not complete 1 Conversion can be read from the DR register Bit 6 Reserved Must always be cleared Bit 5 ADON A D converter On This bit is set and cleared by software 0 A D converter is switched off 1 A D converter is switched on Note a typically 30us delay time is necessary for the ADC to stabilize when the ADON bitis set Bit 4 Reserved Forced by hardware to 0 Bit 3 Reserved Must always be cleared Bits 2 0 CH 2 0 Channel Selection Table 20 ADC Register Map Address Register 7 Hex Name 70 AD7 Reset Value 0 These bits are set and cleared by software They select the analog input to convert Table 19 Channel Selection IMPORTANT NOTE The number of pins AND the channel selection vary according to the device REFER TO THE DEVICE PINOUT DATA REGISTER DR Read Only Reset Value 0000 0000 00h 7 0 Bit 7 0 AD 7 0 Analog Converted Value This register contains the converted analog value in the range 00h to FFh
20. cleared If the watchdog is activated the HALT instruction will generate a Reset ST72101 ST72212 ST72213 4 2 4 Low Power Modes Mode Description WAIT No effect on Watchdog Immediate reset generation as soon as HALT the HALT instruction is executed if the Watchdog is activated WDGA bit is set 4 2 5 Interrupts None 4 2 6 Register Description CONTROL REGISTER CR Read Write Reset Value 0111 1111 7Fh 7 0 Bit 7 WDGA Activation bit This bit is set by software and only cleared by hardware after a reset When WDGA 1 the watchdog can generate a reset 0 Watchdog disabled 1 Watchdog enabled Bit 6 0 T 6 0 7 bit timer 5 to LSB These bits contain the decremented value A reset is produced when it rolls over from 40h to 3Fh 6 becomes cleared Table 14 Watchdog Timer Register Map and Reset Values Address Register 7 Hex Label 0024h WDGCR WDGA T6 15 T4 T3 T2 T1 TO Reset Value 0 1 1 1 1 1 1 1 31 84 ST72101 ST72212 ST72213 4 3 16 BIT TIMER 4 3 1 Introduction The timer consists of a 16 bit free running counter driven by a programmable prescaler It may be used for a variety of purposes including pulse length measurement of up to two input sig nals input capture or generation of up to two out put waveforms output compare and PWM Pulse lengths and waveform periods can be mod ulated from a few microseconds to several milli seconds using the timer
21. is a byte the pointer size is a word thus allowing 64 Kbyte addressing space and requires 1 byte after the opcode 574 577 ADDRESSING MODES Cont d 5 1 6 Indirect Indexed Short Long This is a combination of indirect and short indexed addressing modes The operand is referenced by its memory address which is defined by the un signed addition of an index register value X or Y with a pointer value located in memory The point er address follows the opcode The indirect indexed addressing mode consists of two sub modes Indirect Indexed Short The pointer address is a byte the pointer size is a byte thus allowing 00 1FE addressing space and requires 1 byte after the opcode Indirect Indexed Long The pointer address is a byte the pointer size is a word thus allowing 64 Kbyte addressing space and requires 1 byte after the opcode Table 22 Instructions Supporting Direct Indexed Indirect Indirect Indexed Addressing Modes Instructions ADC ADD SUB SBC Arithmetic Addition subtrac tion operations Short Instructions Only Function BTJT BTJF Bit Test and Jump Opera tions son Shift and Rotate Operations SWAP Swap Nibbles CALL JP Call or Jump subroutine ST72101 ST72212 ST72213 5 1 7 Relative mode Direct Indirect This addressing mode is used to modify the PC register value by adding an 8 bit signed offset to it Available Relative Direct Indirect Instructions
22. low power mode The external interrupt polarity is selected through the miscellaneous register or interrupt register if available External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine If several input pins connected to the same inter rupt vector are configured as interrupts their sig nals are logically ANDed before entering the edge level detection block Warning The type of sensitivity defined in the Miscellaneous or Interrupt register if available applies to the El source In case of an ANDed source as described on the I O ports section a low level on an I O pin configured as input with in terrupt masks the interrupt request even in case of rising edge sensitivity Peripheral Interrupts Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both The I bit of the CC register is cleared The corresponding enable bit is set in the control register If any of these two conditions is false the interrupt is latched and thus remains pending Clearing an interrupt request is done by writing 0 to the corresponding bit in the status register or an access to the status register while the flag is set followed by a read or write of an associated register Note the clearing sequence resets the internal latch A pending interrupt i e waiting f
23. multi plexer controlled by the ADC registers switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input It is recommended not to change the voltage level or loading on any port pin while conversion is in progress Furthermore it is recommended not to have clocking pins located close to a selected an alog pin Warning The analog input voltage level must be within the limits stated in the Absolute Maximum Ratings ST72101 ST72212 ST72213 4 1 3 I O Port Implementation The hardware implementation on each I O port de pends on the settings in the DDR and OR registers and specific feature of the I O port such as ADC In put see Figure 20 or true open drain Switching these I O ports from one state to another should be done in a sequence that prevents unwanted side effects Recommended safe transitions are il lustrated in Figure 19 Other transitions are poten tially risky and should be avoided since they are likely to present unwanted side effects such as spurious interrupt generation Figure 19 Recommended I O State Transition Diagram INPUT INPUT no interrupt with interrupt OUTPUT push pull OUTPUT open drain 25 84 ST72101 ST72212 ST72213 PORTS Cont d Figure 20 Block Diagram ALTERNATE ENABLE ALTERNATE Vpp OUTPUT P BUFFER SEE TaBLE BELOW ALTERNATE pi ENABLE CONDITION L SEE TABLE BELOW OR LATCH ANA
24. register is pushed on the stack The I Bit is set during the inter rupt routine and cleared when the CC register is popped 3 5 MISCELLANEOUS REGISTER The Miscellaneous register allows to select the SLOW operating mode the polarity of external in terrupt requests and to output the internal clock Register Address 0020h Read Write Reset Value 0000 0000 00h 7 0 2 PEIO BBE Bit 7 6 PEI 3 2 External Interrupt Polarity Option These bits are set and cleared by software They determine which event on El1 causes the exter nal interrupt according to Table 8 Table 8 External Interrupt Polarity Options Falling edge and low level Reset state Falling edge ony 1 9 ising edge only 9 5 Note Any modification of one of these two bits re sets the interrupt request related to this interrupt vector Bit 5 MCO Main Clock Out This bit is set and cleared by software When set it enables the output of the Internal Clock on the PC2 I O port 0 is a general purpose port 1 alternate function is output on PC2 pin ST72101 ST72212 ST72213 Bit 4 3 PEI 1 0 External Interrupt EIO Polarity Option These bits are set and cleared by software They determine which event on EIO causes the exter nal interrupt according to Table 9 Table 9 0 External Interrupt Polarity Options Falling edge and low level Reset state
25. 1 p 1j VR000108 78 84 ST72101 ST72212 ST72213 SPI CHARACTERISTICS Cont d Measurement points Vi and in the SPI Timing Diagram Figure 47 SPI Slave Timing Diagram CPHA 0 CPOL 0 MISO OUTPUT MOSI INPUT MISO OUTPUT E IL INPUT pp DO IN XXX VR000111 VR000112 7574 79 84 ST72101 ST72212 ST72213 7 GENERAL INFORMATION 7 1 EPROM ERASURE EPROM version devices are erased by exposure to high intensity UV light admitted through the transparent window This exposure discharges the floating gate to its initial state through induced photo current It is recommended that the EPROM devices be kept out of direct sunlight since the UV content of sunlight can be sufficient to cause functional fail ure Extended exposure to room level fluorescent lighting may also cause erasure 7 2 PACKAGE MECHANICAL DATA An opaque coating paint tape label etc should be placed over the package window the product is to be operated under these lighting con ditions Covering the window also reduces Ipp in power saving modes due to photo diode leakage currents An Ultraviolet source of wave length 2537 A yield ing a total integrated dosage of 15 Watt sec cm is required to erase the device It will be erasedin 15 to 20 minutes if such a UV lamp with a 12mW cm power rating is placed 1 inch from the device win dow without any interposed filters
26. 13 SERIAL PERIPHERAL INTERFACE Cont d Figure 34 Serial Peripheral Interface Block Diagram Internal Bus IT D request ite E SPI STATE ES T SS Em FX ER FX SERIAL CLOCK GENERATOR 50 84 SERIAL PERIPHERAL INTERFACE Cont d 4 4 4 Functional Description Figure 33 shows the serial peripheral interface SPI block diagram This interface contains 3 dedicated registers A Control Register CR A Status Register SR A Data Register DR Refer to the CR SR and DR registers in Section 4 4 7for the bit definitions 4 4 4 1 Master Configuration In a master configuration the serial clock is gener ated on the SCK pin Procedure Select the SPRO amp SPR1 bits to define the se rial clock baud rate see CR register Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock see Figure 36 The SS pin must be connected to a high level signal during the complete byte transmit se quence The MSTR and SPE bits must be set they re main set only if the SS pin is connected to a high level signal ST72101 ST72212 ST72213 In this configuration the MOSI pin is a data output and to the MISO pin 15 a data input Transmit sequence The transmit sequence begins when a byte 15 writ ten the DR register The data byte 15 parallel loaded into the 8 bit shift register from the internal bus
27. 66 84 5 1 3 Direct In Direct instructions the operands are referenced by their memory address The direct addressing mode consists of two sub modes Direct short The address is a byte thus requires only one byte after the opcode but only allows 00 FF address ing space Direct long The address is a word thus allowing 64 Kbyte ad dressing space but requires 2 bytes after the op code 5 1 4 Indexed No Offset Short Long In this mode the operand is referenced by its memory address which is defined by the unsigned addition of an index register X or Y with an offset The indirect addressing mode consists of three sub modes Indexed No Offset There is no offset no extra byte after the opcode and allows 00 FF addressing space Indexed Short The offset is a byte thus requires only one byte af ter the opcode and allows 00 1FE addressing space Indexed long The offset is a word thus allowing 64 Kbyte ad dressing space and requires 2 bytes after the op code 5 1 5 Indirect Short Long The required data byte to do the operation is found by its memory address located in memory point er The pointer address follows the opcode The indi rect addressing mode consists of two sub modes Indirect short The pointer address is a byte the pointer size is a byte thus allowing 00 FF addressing space and requires 1 byte after the opcode Indirect long The pointer address
28. 9 Figure 39 ADC block diagram Control Status Register CSR 2 ANALOG DIGITAL HOLD CONVERTER gt per pes os eos we Tr Data Register DR 62 84 437 8 A D CONVERTER ADC Cont d 4 5 3 Functional Description The high level reference voltage must be connected externally to the Vpp pin The low level reference voltage Vss4 must be connected exter nally to the Vas pin In some devices refer to de vice pin out description high and low level refer ence voltages are internally connected to the Vpp and Vgg pins Conversion accuracy may therefore be degraded by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines Figure 40 Recommended Ext Connections L Px x AINx Characteristics The conversion is monotonic meaning the result never decreases if the analog input does not and never increases if the analog input does not If input voltage is greater than or equal to Vpp voltage reference high then results FFh full scale without overflow indication If input voltage lt Vss voltage reference low then the results 00h The conversion time is 64 CPU clock cycles in cluding a sampling time of 31 5 CPU clock cycles Rain is the maximum recommended impedance for an analog input signal If the impedance is too high this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time The A D co
29. Com pare register and the free running counter the out put compare function Assigns pins with a programmable value if the OCIE bit is set Sets a flag in the status register Generates an interrupt if enabled Two 16 bit registers Output Compare Register 1 OC1R and Output Compare Register 2 OC2R contain the value to be compared to the free run ning counter each timer clock cycle MS Byte LS Byte OCiHR OCILR These registers are readable and writable and are not affected by the timer hardware A reset event changes the value to 8000h Timing resolution is one count of the free running counter cpU C1 cc0 Procedure To use the output compare function select the fol lowing in the CR2 register Set the bit if an output is needed then the OCMPi pin is dedicated to the output compare i function Select the timer clock CC1 CCO see Table 15 And select the following in the CR1 register Select the OLVL i bit to applied to the OCMP pins after the match occurs Set the OCIE bit to generate an interrupt if it is needed When a match is found OCFi bit is set The pin take