Home

ST ST72101/ST72212/ST72213 handbook

1. 1 2 4 5 6 7 PCO AINO PC1 AIN1 PC2 CLKOUT AIN2 Vss TEST V pp 1 2 4 5 6 7 PC1 PC2 CLKOUT ST72101 ST72212 ST72213 Figure 5 ST72212 Pinout SDIP32 RESET OSCIN OSCOUT SS PB7 SCK PB6 MISO PB5 MOSI PB4 NC NC OCMP2_A PB3 ICAP2_A PB2 OCMP1_A PB1 ICAP1_A PBO AINS EXTCLK A PC5 2 4 AINS ICAP2 1 Vop EPROM OTP only PAE RESET OSCIN OSCOUT SS PB7 SCK PB6 MISO PB5 MOSI PB4 NC NC OCMP2_A PB3 ICAP2_A PB2 OCMP1 ICAP1 A PBO AINS EXTCLK_A PC5 AIN4 PC4 AIN3 PC3 OSCOUT SS PB7 SCK PB6 MISO PB5 MOSI PB4 NC NC OCMP2_A PB3 ICAP2_A PB2 OCMP1_A PB1 ICAP1_A PBO EXTCLK_A PC5 PC4 PC3 Vss TEST V pp 1 2 PA4 PAS 6 PA7 PCO ICAP1_B AINO PC1 OCMP1 B AIN1 PC2 CLKOUT AIN2 Vss TEST V PAO PA2 PA3 NC NC PA4 PA5 PAG PA7 PCO AINO PC1 AIN1 PC2 CLKOUT AIN2 Vss TEST V pp 1 2 NC 4 5 6 7 1 PC2 CLKOUT 5 84 ST72101 ST72212 ST72213 Table 1 ST72212 Pin Configuration EE 1 RESET vo Bidirectional Active low Top priority non maskable interrupt 1 1 Input Output Oscillator pin These
2. LmugE mpic o wmprG 220 ___ __ ___ 69 84 ST72101 ST72212 ST72213 INSTRUCTION GROUPS Cont d ee PE mur wos PE m d ae Pop from the Stack pop reg pop CC EE m mer usan mw emere __ _____ _ romernes oom _ _ reesen rone mo ___ L _ mu _ _ O EZ Wwe wwe wer AAA HA L LIS 70 84 6 ELECTRICAL CHARACTERISTICS 6 1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages how ever it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages For proper operation it is recommended that V and be higher than Vss and lower than Vpp Reliability is enhanced if unused inputs are con nected to an appropriate logic voltage level Vpp or Vsg ST72101 ST72212 ST72213 Power Considerations The average chip junc tion temperature Ty in Celsius can be obtained from Where Ta Ambient Temperature RthJA Package thermal resi
3. 24424 eem qute ome mx DEED Red id 32 4 3 1 IntroductiOm 2222 seen ERR t E 32 432 Features ados eee a ERE EY d 32 4 3 3 Functional Description 1 2 4 4 32 4 3 4 Low Power Modes 43 4 3 5 Interr pts oss sse meme mx EE ERE t b Y EE XU Bass 43 4 3 6 Register Description 1 44 2 84 574 Table of Contents 4 4 SERIAL PERIPHERAL INTERFACE SPI 49 4 4 1 Introduction 4 49 4 4 2 Main Features 1 49 4 4 8 General description 49 4 4 4 Functional Description 1 035 51 4 4 5 Low Power Modes 58 4 4 6 Intertupts RR Ree dun AA ww ewes 58 4 4 7 Register Description 59 4 5 8 BIT A D CONVERTER 62 4 9 1 INTFOUCI N oues ue ao 62 452 Features ree b REX A 62 4 5 3 Functional Description 2 63
4. 1 ICIE OCIE TOIE FOLV2 FOLV 1 OLVL2 IEDG 1 OLVL1 TimerA 31 CR2 1 2 PWM CC1 CCO IEDG2 EXEDG TimerA 33 SR ICF1 OCF1 TOF ICF2 OCF2 mese o o 9 TimerA 34 IC1HR MSB LSB messes c o o TimerA 35 ICALR MSB LSB _ _ TimerA 36 OC1HR MSB LSB o o o o TimerA 37 OC1LR MSB TimerA 3E OC2HR TimerA 3A ACHR MSB TimerA 3B ACLR MSB TimerA 3C IC2HR MSB A EN TimerA 3D IC2LR MS 4 48 84 4 4 SERIAL PERIPHERAL INTERFACE SPI 4 4 1 Introduction The Serial Peripheral Interface SPI allows full duplex synchronous serial communication with external devices An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves The SPI is normally used for communication be tween the microcontroller and external peripherals or another microcontroller Refer to the Pin Description chapter for the device specific pin out 4 4 2 Main Features m Full duplex three wire synchronous transfers Master or slave operation Four master mode frequencies Maximum slave mode frequency fCPU 2 Four programmable master bit rates Programmable clock polarity and phase End of transfer interrupt flag Write collision flag protection Master mode fault protection capability Figure 33 Serial Peripheral Inte
5. Vi and in the SPI Timing Diagram Figure 47 SPI Slave Timing Diagram CPHA 0 CPOL 0 MISO OUTPUT MOSI INPUT MISO OUTPUT E IL I INPUT i DO IN XXX VR000111 VR000112 7574 79 84 ST72101 ST72212 ST72213 7 GENERAL INFORMATION 7 1 EPROM ERASURE EPROM version devices are erased by exposure to high intensity UV light admitted through the transparent window This exposure discharges the floating gate to its initial state through induced photo current It is recommended that the EPROM devices be kept out of direct sunlight since the UV content of sunlight can be sufficient to cause functional fail ure Extended exposure to room level fluorescent lighting may also cause erasure 7 2 PACKAGE MECHANICAL DATA An opaque coating paint tape label etc should be placed over the package window if the product is to be operated under these lighting con ditions Covering the window also reduces Ipp in power saving modes due to photo diode leakage currents An Ultraviolet source of wave length 2537 yield ing a total integrated dosage of 15 Watt sec cm is required to erase the device It will be erased in 15 to 20 minutes if such a UV lamp with a 12mW cm power rating is placed 1 inch from the device win dow without any interposed filters Figure 51 28 Pin Small Outline Package 300 mil Width 80 84 mm ms om Tr Tuc i Ts Papes zes wows Er o
6. Access time time to data active from high 1 state Slave Disable time hold time to high im pedance state Master before capture edge 0 25 Slave enable edge Master before capture edge 0 25 Slave enable edge 0 Outputs SCK MOSI MISO 20 to 70 Vpp 200pF Inputs SCK MOSI MISO SS Fall time Outputs SCK MOSI MISO 70 to 20 Vpp 200pF Inputs SCK MOSI MISO SS Measurement points are Vij and Vj in the SPI Timing Diagram Figure 43 SPI Master Timing Diagram CPHA 0 CPOL 0 SS INPUT SCK OUTPUT MISO Don XXX INPUT DO IN SEEN OUTPUT D6 OUT 00 VR000109 77 84 4 ST72101 ST72212 ST72213 SPI CHARACTERISTICS Conta Measurement points are Vi and in the SPI Timing Diagram Figure 44 SPI Master Timing Diagram CPHA 0 CPOL 1 SCK OUTPUT so 5 Co XXXX 1 Mos OUT X OUTPUT a D0 OUT VR000110 SCK OUTPUT AAA MISO X C DOOUT INPUT x DO OUT OUTPUT gm D6 IN DO IN LILLLU I VR000107 SCK OUTPUT 1 1 INPUT ____2 D6 IN DO IN XXX 2 1 1 6 11 H FR 1 vos gt OUTPUT D7 OUT D6 OUT D0 OUT 11011 11 p 1j VR000108 78 84 437 ST72101 ST72212 ST72213 SPI CHARACTERISTICS Cont d Measurement points are
7. ST72101G1 ST72101 ST72212 ST72213 8 BIT MCU WITH 4 TO 8K ROM OTP EPROM 256 BYTES RAM ADC WDG SPI AND 1 OR 2 TIMERS DATASHEET User Program Memory ROM OTP EPROM 4 to 8K bytes m Data RAM 256 bytes including 64 bytes of stack m Master Reset and Power On Reset Run Wait Slow and RAM Retention modes m 22 multifunctional bidirectional I O lines 22 programmable interrupt inputs 8 high sink outputs 6 analog alternate inputs 10 to 14 alternate functions EMI filtering m Programmable watchdog WDG m One or two 16 bit Timers each featuring 2 Input Captures 2 Output Compares External Clock input on Timer A only CSDIP32W PWM and Pulse Generator modes m Synchronous Serial Peripheral Interface SPI 8 bit Analog to Digital converter 6 channels ST72212 and ST72213 only 8 bit Data Manipulation 63 Basic Instructions 17 main Addressing Modes 8 x 8 Unsigned Multiply Instruction True Bit Manipulation Complete Development Support on PC DOS WINDOWS Real Time Emulator m Full Software Package DOS WINDOWS C Compiler Cross Assembler Debugger Features 817210190 517221262 RAM stack bytes i esd ves PSDIP32 gt See ordering information the end of datasheet Device Summary 3105 5 V 8MHz max 16MHz oscillator AMHz max over 85 Rev 1
8. register value required for a specific tim ing application can be calculated using the follow ing formula t f OCI Value 5 PRESC Where t Desired output compare period in sec onds fcpy Internal clock frequency PRESC limer prescaler factor 2 4 or 8 de pending on CC1 CCO bits see Table 15 42 84 The Output Compare 2 event causes the counter to be initialized to FFFCh See Figure 32 Pulse Width Modulation cycle OCMP1 OLVL1 OLVL2 Counter is reset to FFFCh ICF1 bit is set Notes 1 After a write instruction to the OC HR register the output compare function is inhibited until the register is also written Therefore the Input Capture 1 function is inhib ited but the Input Capture 2 is available 2 The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited 3 The ICF1 bitis set by hardware when the coun ter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared 4 PWM mode the ICAP1 pin can not be used to perform input capture because it is discon nected to the timer The ICAP2 pin can be used to perform input capture ICF2 can be set and IC2R can be loaded but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set 5 When the Pulse Width Modulation PWM and One Pulse Mode OPM
9. 4 3 2 Main Features m Programmable divided by 2 4 or8 Overflow status flag and maskable interrupt m External clock input must be at least 4 times slower thanthe CPU clock speed with the choice of active edge m Output compare functions with 2 dedicated 16 bit registers 2 dedicated programmable signals 2 dedicated status flags 1 dedicated maskable interrupt m Input capture functions with 2 dedicated 16 bit registers 2 dedicated active edge selection signals 2 dedicated status flags 1 dedicated maskable interrupt m Pulse width modulation mode PWM m One pulse mode m 5 alternate functions on ports ICAP1 ICAP2 OCMP1 OCMP2 EXTCLK The Block Diagram is shown in Figure 22 Note Some external pins are not available on all devices Refer to the device pin out description When reading an input signal which is not availa ble on an external pin the value will always be 1 32 84 4 3 3 Functional Description 4 3 3 1 Counter The principal block of the Programmable Timer is a 16 bit free running increasing counter and its as sociated 16 bit registers Counter Registers Counter High Register CHR is the most sig nificant byte MSB Counter Low Register CLR is the least sig nificant byte LSB Alternate Counter Registers Alternate Counter High Register ACHR is the most significant byte MSB Alternate Counter Low Regis
10. 4 5 5 Interrupts None 63 84 ST72101 ST72212 ST72213 8 A D CONVERTER ADC 4 5 6 Register Description CONTROL STATUS REGISTER CSR Read Write Reset Value 0000 0000 00h 7 0 Bit 7 COCO Conversion Complete This bit is set by hardware It is cleared by soft ware reading the resultin the DR register or writing to the CSR register 0 Conversion is not complete 1 Conversion can be read from the DR register Bit 6 Reserved Must always be cleared Bit 5 ADON A D converter On This bit is set and cleared by software 0 A D converter is switched off 1 A D converter is switched on Note a typically 30us delay time is necessary for the ADC to stabilize when the ADON bitis set Bit 4 Reserved Forced by hardware to 0 Bit 3 Reserved Must always be cleared Bits 2 0 CH 2 0 Channel Selection Table 20 ADC Register Map Address Register 7 Hex Name 70 AD7 Reset Value 0 These bits are set and cleared by software They select the analog input to convert Table 19 Channel Selection IMPORTANT NOTE The number of pins AND the channel selection vary according to the device REFER TO THE DEVICE PINOUT DATA REGISTER DR Read Only Reset Value 0000 0000 00h 7 0 Bit 7 0 AD 7 0 Analog Converted Value This register contains the converted analog value in the range 00h to FFh Reading this register reset the COCO flag AD6 AD5 AD4 AD3 AD2 AD1 ADO 0 0 0
11. Added details to description of FOLV1 and FOLV2 bits Added ADC recommended external connections SPR2 bit reinstated in SPI chapter 49 to 61 Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics All Rights Reserved Purchase of Components by STMicroelectronics conveys a license under the Philips Patent Rights to use these components in an system is granted provided that the system conforms to the Standard Specification as defined by Philips STMicroelectronics Group of Companies Australia Brazil China Finland France Germany Hong Kong India Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom U S A http www st com 4 84 84
12. Cont d 4 3 6 Register Description Each Timer is associated with three control and status registers and with six pairs of data registers 16 bit values relating to the two input captures the two output compares the counter and the al ternate counter CONTROL REGISTER 1 CR1 Read Write Reset Value 0000 0000 00h 7 0 ICIEJOCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL 1 Bit 7 ICIE nput Capture Interrupt Enable 0 Interrupt is inhibited 1 timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set Bit 6 OCIE Output Compare Interrupt Enable 0 Interrupt is inhibited 1 A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set Bit 5 TOIE Timer Overflow Interrupt Enable 0 Interrupt is inhibited 1 A timer interrupt is enabled whenever the TOF bit of the SR register is set 44 84 Bit 4 FOLV2 Forced Output Compare 2 This bit is set and cleared by software 0 No effect on the OCMP2 pin 1 Forces the OLVL2 bit to be copied to the pin if the OC2E bit is set and even if there is no successful comparison Bit 3 FOLV1 Forced Output Compare 1 This bit is set and cleared by software 0 No effect on the pin 1 Forces OLVL 1 to be copied to the 1 pin if the OC1E bit is set and even if there is no suc cessful comparison Bit 2 OLVL2 Output Level 2 This bit is copied to the OCMP2 pin whenever a succes
13. and the effect on the ADC accuracy is loss of 1 LSB by 10Ka increase of the external analog source impedance These measurement results and recommendations take worst case injection conditions into account negative injection injection to an Input with analog capability adjacent to the enabled Analog Input at 5V Vpp supply and worst case temperature lapc Sampling Switch Px x AINx Coin 5pF input capacitance threshold voltage sampling switch Chola sample hold capacitance leakage current at the pin due to various junctions 75 84 4 ST72101 ST72212 ST72213 A D CONVERTER CHARACTERISTICS Cont d Figure 42 ADC conversion characteristics Offset Error OSE Error GE LSB VietP je ideal 7 256 Example of an actual transfer curve The ideal transfer curve Integral non linearity error ILE 1 2 3 Differential non linearity error DLE 4 5 Center of a step of the actual transfer curve 250 251 252 253 254 255 256 Vina LSBidea Offset Error OSE VR02133A 76 84 437 ST72101 ST72212 ST72213 6 7 SPI CHARACTERISTICS Serial Peripheral Interface Value Symbol Parameter Condition Master Em ET t SPI clock period Masier t SPI CPU esseri fs e Clock SCK high time 2 100 Clock SCK low time 100 Data set up time ihe Data hold time inputs
14. 0 0 0 0 71 CSR COCO ADON CH2 CH1 CHO Reset Value 0 0 0 0 0 64 84 5 INSTRUCTION SET 5 1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups Rairessing Mode Example mee CS The ST7 Instruction set is designed to minimize the number of bytes required per instruction To do Table 21 ST7 Addressing Mode Overview Pointer Syntax rar Address Size Hex Hex PU A ST72101 ST72212 ST72213 so most of the addressing modes may be subdi vided in two sub modes called long and short Long addressing mode is more powerful be cause itcan use the full 64 Kbyte address space however it uses more bytes and more CPU cy cles Short addressing mode is less powerful because it can generally only access page zero 0000h OOFFh range but the instruction size is more compact and faster All memory to memory in structions use short addressing modes only CLR CPL NEG BSET BRES BTJT BTJF INC DEC RLC RRC SLL SRL SRA SWAP The ST7 Assembler optimizes the use of long and short addressing modes Pointer ___ i LE S i rong Short Id A 10 X 00 1FE 7 0 with X register 1 with Y register Long Id A 1000 X 0000 FFFF Short Indirect ____ Id A 10 00
15. 3 2 External Clock The external clock where available is selected if CCO 1 and CC1 1 in register The status of the EXEDG bit determines the type of level transition on the external clock pin EXT CLK that will trigger the free running counter The counter is synchronised with the falling edge of the internal CPU clock At least four falling edges of the CPU clock must occur between two consecutive active edges of the external clock thus the external clock frequen cy must be less than a quarter of the CPU clock frequency ST72101 ST72212 ST72213 16 BIT TIMER Contd Figure 23 Counter Timing Diagram internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF Figure 24 Counter Timing Diagram internal clock divided by 4 INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF ki 35 84 ST72101 ST72212 ST72213 16 BIT TIMER Cont d 4 3 3 3 Input Capture In this section the index may be 1 or 2 The two input capture 16 bit registers IC1R and IC2R are used to latch the value of the free run ning counter after a transition detected by the ICAP pin see figure 5 MS Byte LS Byte ICiR ICiLR ICi register is a read only register The active transition is software programmable through the IEDGibit of the Control Register Timing r
16. 4 5 4 Low Power Modes 44 ia room d Pe Y 63 455 sse Xe RE eee Pee eo eared ee Whe di oe e e RE E 63 4 5 6 Register Description 64 5 INSTRUCTION SET oec e n Rem em ru dee eee 65 5 1 517 ADDRESSING MODES Le 564 b b ER dor xx hea REG A 65 5 1 1 Inh rent Ron ehh ct ce E rg not n d 66 Immediate sae Rea E EX A ERES RET REOS NUR e ERR 66 51 3 DITECL CET 66 5 1 4 Indexed No Offset Short Long 66 5 1 5 Indirect Short Long 2 4 66 5 1 6 Indirect Indexed Short Long 67 5 1 7 Relative mode Direct Indirect 67 5 2 INSTRUCTION GROUPS 1 68 6 ELECTRICAL CHARACTERISTICS 71 6 1 ABSOLUTE MAXIMUM RATINGS 71 6 2 RECOMMENDED OPERATING CONDITIONS 72 6 3 DC ELECTRICAL CHARACTERISTICS 73 6 4 RESET CHARACTERISTICS 2 74 6 5 OSCILLATOR CHARACTERISTICS 74 6 6 A D CONVERTER CHARACTE
17. ANALOG DIGITAL HOLD CONVERTER gt per pes os eos we Tr Data Register DR 62 84 437 8 A D CONVERTER ADC Cont d 4 5 3 Functional Description The high level reference voltage must be connected externally to the Vpp pin The low level reference voltage Vss4 must be connected exter nally to the Vas pin In some devices refer to de vice pin out description high and low level refer ence voltages are internally connected to the Vpp and Vgg pins Conversion accuracy may therefore be degraded by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines Figure 40 Recommended Ext Connections Px x AINx Characteristics The conversion is monotonic meaning the result never decreases if the analog input does not and never increases if the analog input does not If input voltage is greater than or equal to Vpp voltage reference high then results FFh full scale without overflow indication If input voltage lt Vss voltage reference low then the results 00h The conversion time is 64 CPU clock cycles in cluding a sampling time of 31 5 CPU clock cycles Rain is the maximum recommended impedance for an analog input signal If the impedance is too high this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time The A D converter is linear and the digital result of the conversion is given by th
18. EPROM version for the above devices 82 84 ST72101 ST72212 ST72213 ST72101 ST72213 and ST72212 MICROCONTROLLER OPTION LIST Customer Address Contact Phone No Reference STMicroelectronics references Device ST72101 ST72212 ST72213 Package Dual in Line Plastic Small Outline Plastic with conditioning 1 Standard Stick Tape amp Reel Temperature Range 0 C to 70 C 40 C 85 C 40 C to 125 C Special Marking No Yes Authorized characters are letters digits and spaces only Maximum character count SDIP32 10 SO28 8 Comments Supply Operating Range in the application Oscillator Frequency in the application Notes Signature 83 84 ST72101 ST72212 ST72213 8 SUMMARY OF CHANGES Change Description Rev 1 5 to 1 6 Added new External Connections section Removed RP external resistor Changed ORed to ANDed in External interrupts paragraph to read If several input pins con nected to the same interrupt vector are configured as interrupts their signals are logically AN 18 and 24 Ded before entering the edge level detection block Added note Any modification of one of these two bits resets the interrupt request related to this interrupt vector Added clamping diodes to pin figure and table Added sections on low power modes and interrupts to peripheral descriptions 31 43 58 63 Changed 16 bit Timer Chapter 32 to 48 44
19. FEATURES m 63 basic instructions m Fast 8 bit by 8 bit multiply 17 main addressing modes addressing mode Two 8 bit index registers 16 bit stack pointer 8 MHz CPU internal frequency Low power modes Maskable hardware interrupts Non maskable software interrupt indirect with 2 3 CPU REGISTERS The 6 CPU registers shown in Figure 10 are not present in the memory mapping and are accessed by specific instructions Figure 10 CPU Registers RESET VALUE XXh 7 RESET VALUE XXh 7 RESET VALUE XXh 15 817 01 RESET VALUE RESET VECTOR FFFEh FFFFh 7 0 ERR CREER ES RESET VALUE 1 4 1 X 1 X X X 15 8i7 0 RESET VALUE STACK HIGHER ADDRESS ST72101 ST72212 ST72213 Accumulator A The Accumulator is an 8 bit general purpose reg ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data Index Registers X and Y In indexed addressing modes these 8 bit registers are used to create either effective addresses or temporary storage areas for data manipulation The Cross Assembler generates a precede in struction PRE to indicate that the following in struction refers to the Y register The Y register is not affected by the interrupt auto matic procedures not pushed to and popped from the stack Program Counter PC The program counter is a 16 bit register containing the address of the next instruction to be executed by the CPU It is made
20. FF 00 FF Long Indirect ld A 10 w 0000 FFFF 00 FF Short Id A 10 X 00 1FE 00 FF Long TA 10 01 X 0000 FFFF Torr Relative Direct imeloop PC 128 PC 127 PRetatve __ me 10 00 FF it ndirect elative tjt 7 ski yte Bi di Relati btjt 10 7 skip 00 FF 00 FF b 3 Note 1 At the ounter P OW p time the instruction Is executed the Program r points to the instruction fo ing JRxx 65 84 ST72101 ST72212 ST72213 ST7 ADDRESSING MODES 5 1 1 Inherent All Inherent instructions consist of a single byte The opcode fully specifies all the required informa tion for the CPU to process the operation TRAP S W Interrupt Wait For Interrupt Low Power Mode HALT Halt Oscillator Lowest Power Mode NO WF IRET Interrupt Sub routine Return RIM Reset Interrupt Mask SCF Set Carry Flag RCF Reset Carry Flag RSP LD CLR NZ U PUSHPOP SLL SRL SRA RLC RRC SWAP Swap Nibbles 5 1 2 Immediate Immediate instructions have two bytes the first byte contains the opcode the second byte con tains the the operand value Immediate Instruction RSP Reset Stack Pointer Shift and Rotate Operations Load LD CP Compare BCP AND OR XOR ADC ADD SUB SBC Arithmetic Operations Logical Operations 66 84 5 1 3 Direct In Direct instructions the operands are referenced by their memory ad
21. SPIE Master Mode Fault Event MODF Note The SPI interrupt events are connected to the same interrupt vector see Interrupts chapter They generate an interrupt if the corresponding Enable Control Bit is set and the I bit in the CC reg ister is reset RIM instruction 58 84 577 SERIAL PERIPHERAL INTERFACE Cont d 4 4 7 Register Description CONTROL REGISTER CR Read Write Reset Value 0000xxxx Oxh 7 0 Bit 7 SPIE Serial peripheral interrupt enable This bit is set and cleared by software 0 Interrupt is inhibited 1 An SPI interrupt is generated whenever SPIF 1 or MODF 1 in the SR register Bit 6 SPE Serial peripheral output enable This bit is set and cleared by software It is also cleared by hardware when in master mode SS 0 see Section 4 4 4 5 Master Mode Fault 0 port connected to pins 1 SPI alternate functions connected to pins The SPE bit is cleared by reset so the SPI periph eral is not initially connected to the external pins Bit 5 SPR2 Divider Enable this bit is set and cleared by software and it is cleared by reset It is used with the SPR 1 0 bits to set the baud rate Refer to Table 17 0 Divider by 2 enabled 1 Divider by 2 disabled Bit 4 MSTR Master This bit is set and cleared by software It is also cleared by hardware when in master mode SS 0 see Section 4 4 4 5 Master Mode Fault 0 Slave mode is selected 1 Master mode is selected the function of
22. bits are both set the PWM mode is the only active one ST72101 ST72212 ST72213 16 BIT TIMER Cont d 4 3 4 Low Power Modes Description WAIT No effect on 16 bit Timer Timer interrupts cause the device to exit WAIT mode If an input capture event occurs on the ICAP pin the input capture detection circuitry is armed Consequent ly when the MCU is woken up by an interrupt with exit from HALT mode capability the ICF bit is set and the counter value present when exiting from HALT mode is captured into the IC R register 16 bit Timer registers are frozen In HALT mode the counter stops counting until Halt mode is exited Counting resumes from the previous count when the MCU is woken up by an interrupt with exit from HALT mode capability or from the counter HALT reset value when the MCU is woken up by a RESET 4 3 5 Interrupts Interrupt Event Input Capture 1 event Counter reset in PWM mode ICF1 Input Capture 2 event ICF2 Output Compare 1 event not available in PWM mode OCF1 OCIE ee Output Compare 2 event not available in PWM mode OCF2 Yes No TmerOwrowswm ves Note The 16 bit Timer interrupt events are con nected to the same interrupt vector see Interrupts chapter These events generate an interrupt if the corre sponding Enable Control Bit is set and the I bit in the CC register is reset RIM instruction 4 43 84 ST72101 ST72212 ST72213 16 BIT TIMER
23. device ports will be forced to be inputs at that time thus disabling the slave devices Note To prevent a bus conflict on the MISO line the master allows only one slave device during a transmission Figure 38 Single Master Configuration For more security the slave device may respond to the master with the received data byte Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are con nected and the slave has not written its DR regis ter Other transmission security methods can use ports for handshake lines or data bytes with com mand fields Multi master System A multi master system may also be configured by the user Transfer of master control could be im plemented using a handshake method through the ports or by an exchange of code messages through the serial peripheral interface system The multi master system is principally handled by the MSTR bit in the CR register and the MODF bit in the SR register 57 84 ST72101 ST72212 ST72213 SERIAL PERIPHERAL INTERFACE 4 4 5 Low Power Modes Description WAIT No effect on SPI SPI interrupt events cause the device to exit from WAIT mode SPI registers are frozen HALT In HALT mode the SPI is inactive SPI operation resumes when the MCU is woken up by an interrupt with exit from HALT mode capability 4 4 6 Interrupts Enable Interrupt Event Control Bit SPI End of Transfer Event SPIF
24. does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence In a slave device the MODF bit can not be set but in a multi master configuration the device can be in slave mode with this MODF bit set The MODF bit indicates that there might have been amulti master conflict for system control and allows a proper exit from system operation to a re set or default system state using an interrupt rou tine 4 4 4 6 Overrun Condition An overrun condition occurs when the master de vice has sent several data bytes and the slave de vice has not cleared the SPIF bit issuing from the previous data byte transmitted In this case the receiver buffer contains the byte sent after the SPIF bit was last cleared A read to the DR register returns this byte All other bytes are lost This condition is not detected by the SPI peripher al SERIAL PERIPHERAL INTERFACE Cont d ST72101 ST72212 ST72213 4 4 4 7 Single Master and Multimaster Configurations There are two types of SPI systems Single Master System Multimaster System Single Master System A typical single master system may be configured using an MCU as the master and four MCUs as slaves see Figure 38 The master device selects the individual slave de vices by using four pins of a parallel port to control the four SS pins of the slave devices The SS pins are pulled high during reset since the master
25. may also directly manipulate the stack by means of the PUSH and POP instruc tions In the case of an interrupt the is stored at the first location pointed to by the SP Then the other registers are stored in the next locations as shown in Figure 11 When an interrupt is received the SP is decre mented and the context is pushed on the stack On return from interrupt the SP is incremented and the context is popped from the stack A subroutine call occupies two locations and an in terrupt five locations in the stack area 15 84 ST72101 ST72212 ST72213 3 CLOCKS RESET INTERRUPTS 8 POWER SAVING MODES 3 1 CLOCK SYSTEM 3 1 1 General Description The MCU accepts either a Crystal or Ceramic res onator or an external clock signal to drive the in ternal oscillator The internal clock is de rived from the external oscillator frequency foso The external Oscillator clock is first divided by 2 and division factor of 32 can be applied if Slow Mode is selected by setting the SMS bit in the Mis cellaneous Register This reduces the frequency of the the clock signal is also routed to the on chip peripherals The internal oscillator is designed to operate with an AT cut parallel resonant quartz crystal resona tor in the frequency range specified for fose The circuit shown in Figure 13 is recommended when using a crystal and Table 6 lists the recommend ed capacitance and feedback resistanc
26. of two 8 bit registers PCL Program Counter Low which is the LSB and PCH Program Counter High which is the MSB ACCUMULATOR X INDEX REGISTER Y INDEX REGISTER PROGRAM COUNTER CONDITION CODE REGISTER STACK POINTER X Undefined Value 13 84 ST72101 ST72212 ST72213 CENTRAL PROCESSING UNIT Cont d CONDITION CODE REGISTER CC Read Write Reset Value 111x1xxx The 8 bit Condition Code register contains the in terrupt mask and four flags representative of the result ofthe instruction just executed This register can also be handled by the PUSH and POP in structions These bits can be individually tested and or con trolled by specific instructions Bit 4 H Half carry This bitis set by hardware when a carry occurs be tween bits 3 and 4 of the ALU during an ADD or ADC instruction It is reset by hardware during the same instructions 0 No half carry has occurred 1 A half carry has occurred This bit is tested using the JRH or JRNH instruc tion The H bit is useful in BCD arithmetic subrou tines Bit 3 I nterrupt mask This bit is set by hardware when entering in inter rupt or by software to disable all interrupts except the TRAP software interrupt This bit is cleared by software 0 Interrupts are enabled 1 Interrupts are disabled This bit is controlled by the RIM SIM and IRET in structions and is tested by the JRM and JRNM in structions Note Interrupts requested whi
27. the stack The is set during the inter rupt routine and cleared when the CC register is popped 3 5 MISCELLANEOUS REGISTER The Miscellaneous register allows to select the SLOW operating mode the polarity of external in terrupt requests and to output the internal clock Register Address 00201 Read Write Reset Value 0000 0000 00h 7 0 PEIS 2 PEIO BE Bit 7 6 PEI 3 2 External Interrupt Polarity Option These bits are set and cleared by software They determine which event on causes the exter nal interrupt according to Table 8 Table 8 El1 External Interrupt Polarity Options Falling edge and low level Reset state Falling edge ony 1 9 ising edge only 9 5 Note Any modification of one of these two bits re sets the interrupt request related to this interrupt vector Bit 5 MCO Main Clock Out This bit is set and cleared by software When set it enables the output of the Internal Clock on the PC2 port 0 is a general purpose port 1 alternate function is output on PC2 pin ST72101 ST72212 ST72213 Bit 4 3 PEI 1 0 External Interrupt EIO Polarity Option These bits are set and cleared by software They determine which event on EIO causes the exter nal interrupt according to Table 9 Table 9 External Interrupt Polarity Options Falling edge and low level Reset state Falling edge only Rising ed
28. transfer during a sequence of eight clock pulses The SS pin allows individual selection of a slave device the other slave devices that are not select ed do not interfere with the SPI transfer Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software using the CPOL and CPHA bits The CPOL clock polarity bit controls the steady state value of the clock when no data is being transferred This bit affects both master and slave modes The combination between the CPOL and CPHA clock phase bits selects the data capture clock edge Figure 36 shows an SPI transfer with the four combinations of the CPHA and CPOL bits The di agram may be interpreted as a master or slave timing diagram where the SCK pin the MISO pin the MOSI pin are directly connected between the master and the slave device The SS pin is the slave device select input and can be driven by the master device Figure 35 CPHA SS Timing Diagram MOSI MISO Master SS ST72101 ST72212 ST72213 The master device applies data to its MOSI pin clock edge before the capture clock edge CPHA bitis set The second edge on the SCK pin falling edge if the CPOL bit is reset rising edge if the CPOL bit is set is the MSBit capture strobe Data is latched on the occurrence of the first clock transition No write collision should occur even if the SS pin stays low during a transfer of several bytes see Figure 35 CPHA bit i
29. 1 byte after the opcode 574 ST7 ADDRESSING MODES Cont d 5 1 6 Indirect Indexed Short Long This is a combination of indirect and short indexed addressing modes The operand is referenced by its memory address which is defined by the un signed addition of an index register value X or Y with a pointer value located in memory The point er address follows the opcode The indirect indexed addressing mode consists of two sub modes Indirect Indexed Short The pointer address is a byte the pointer size is a byte thus allowing 00 1FE addressing space and requires 1 byte after the opcode Indirect Indexed Long The pointer address is a byte the pointer size is a word thus allowing 64 Kbyte addressing space and requires 1 byte after the opcode Table 22 Instructions Supporting Direct Indexed Indirect and Indirect Indexed Addressing Modes Instructions ADC ADD SUB SBC Arithmetic Addition subtrac tion operations Short Instructions Only Function BTJT BTJF Bit Test and Jump Opera tions son Shift and Rotate Operations SWAP Swap Nibbles CALL JP Call or Jump subroutine ST72101 ST72212 ST72213 5 1 7 Relative mode Direct Indirect This addressing mode is used to modify the PC register value by adding an 8 bit signed offset to it Available Relative Direct Indirect Instructions CALLR Call Relative The relative addressing mode consists of two sub modes Relative Dire
30. 1111 1100 FCh This is an 8 bit register that contains the low part of the counter value A write to this register resets the counter An access to this register after accessing the SR register clears the TOF bit 7 0 4 ST72101 ST72212 ST72213 ALTERNATE COUNTER HIGH REGISTER ACHR Read Only Reset Value 1111 1111 FFh This is an 8 bit register that contains the high part of the counter value 7 0 per ALTERNATE COUNTER LOW REGISTER ACLR Read Only Reset Value 1111 1100 FCh This is an 8 bit register that contains the low part of the counter value A write to this register resets the counter An access to this register after an access to SR register does not clear the TOF bit in SR register 7 0 INPUT CAPTURE 2 HIGH REGISTER IC2HR Read Only Reset Value Undefined This is an 8 bit read only register that contains the high part of the counter value transferred by the Input Capture 2 event 7 0 INPUT CAPTURE 2 LOW REGISTER IC2LR Read Only Reset Value Undefined This is an 8 bit read only register that contains the low part of the counter value transferred by the In put Capture 2 event 7 0 ST72101 ST72212 ST72213 16 BIT TIMER Cont d Table 16 16 Bit Timer Register Map and Reset Values 32
31. 7 September 1999 1 84 Table of Contents 1 GENERAL DESCRIPTION E ERR EET 4 1 1 INTRODUCTION is bd E RS ea eh ona 4 1 2 PIN DESCRIPTION 4 5 1 3 EXTERNAL 1 1 9 1 4 MEMORY cou is Re Rr bios eed 10 2 CENTRAL PROCESSING UNIT 13 2 1 INTRODUCTION see pie bind ao a n me ro og 13 2 2 MAIN FEATURES txt dees e hes 13 2 3 GPU REGISTERS genau Ave reu uu cad dae dO We 13 3 CLOCKS RESET INTERRUPTS amp POWER SAVING MODES 16 94 CLOCK SYSTEM sei ebd ees eR aa e RR AER 16 3 1 1 General Description 1 16 32 RESET ebrei eu Oe dee cnet LM ut 17 3 2 1 drittodUctiODk Seite wed RES has bap bod She 17 3 2 2 External a a a a a 17 3 2 3 Reset Operation us e x ah EROR ad 17 3 2 4 Poweron Reset cuoc Used Rn ra b tee o Sosa teet 17 3 3 INTERRUPTS iuh et R
32. ACTERISTICS Ta 40 C to 125 C and Vpp 5V unless otherwise specified Symbol Parameter Test Conditions Mm Input Low Level Voltage Input High Level Voltage All Input pins lt lt 5 5V Vpp 0 7 V Hysteresis Voltage Low Level Output Voltage All Output pins lo 100A Low Level Output Voltage loy 10mA High Sink I O pins lo 15mA lo 20mA Ta 85 max High Level Output Voltage All Output pins Input Leakage Current Vin Vss No Pull up configured All Input pins but RESET Vin VoL a Input Leakage Current RESET pin Vin 0 1 Ron Reset Weak Pull up Roy Hp VO Weak Pulrup Ri Supply Current in Ingo 4 MHz 2 MHz RUN Mode 2 fosc 8 MHz fopu 4 MHz fosc 16 MHz 8 MHz fosc 4 MHz 125 kHz Supply Current in SLOW Mode 2 fosc 8 MHz fopy 250 kHz fosc 16 MHz fopy 500 kHz fosc 4MHz fcpu 2MHz Supply Current in WAIT Mode 3 fogc 8MHz 4 MHz fosc 16MHz 8 MHz Supply Current in WAIT MINI fosc 2 Mhz 125 khz MUM Mode osc Z 25 2 fosc 16 MHz fcpu 500 kHz 85 Supply Current in HALT Mode iL oap OMA Notes 1 Hysteresis voltage between switching levels Based on characterisation results not tested 2 CPU running with memory access no DC load or activity on clock input OSCIN driven by external squ
33. CF instructions and tested by the JRC and JRNC instructions It is also affected by the bit test and branch shift and rotate instructions CENTRAL PROCESSING UNIT Cont d Stack Pointer SP Read Write Reset Value 01 7Fh 15 8 CPP PPE 7 0 PD foe The Stack Pointer is a 16 bit register which is al ways pointing to the next free location in the stack It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack see Figure 11 Since the stack is 64 bytes deep the 10 most sig nificant bits are forced by hardware Following an MCU Reset or after a Reset Stack Pointer instruc tion RSP the Stack Pointer contains its reset val ue the SP5 to SPO bits are set which is the stack higher address Figure 11 Stack Manipulation Example CALL Interrupt Subroutine Event 0140h PCL Stack Lower Address 0140h Stack Higher Address 017Fh ST72101 ST72212 ST72213 The least significant byte of the Stack Pointer called S can be directly accessed by a LD in struction Note When the lower limit is exceeded the Stack Pointer wraps around to the stack upper limit with out indicating the stack overflow The previously stored information is then overwritten and there fore lost The stack also wraps in case of an under flow The stack is used to save the return address dur ing a subroutine call and the CPU context during an interrupt The user
34. E BELOW ORSEL SWITCH d SEE NOTE BELOW DATA BUS d lt O O lt 2 lt 2 gt gt DDR SEL 4 N BUFFER ALTERNATE INPUT CMOS POLARITY SCHMITT TRIGGER EXTERNAL EL i INTERRUPT SOURCE Elx Table 10 Port Mode Configuration Configuration Mode Pukup __ VopDiode Floating RAR 30 LL Push pull 80 1 31 3 not in OTP Open Drain logic Teva Legend Notes 0 present not activated No OR Register on some ports see register map 1 present and activated ADC Switch on ports with analog alternate functions 26 84 ST72101 ST72212 ST72213 Table 11 Port Configuration TS DDR 0 T True uM D Drain PAO PA7 Floating with Interrupt High Sink Capability B PBO PB7 PB7 Floating Pull Pull up with Interrupt with Pull up with Interrupt Open Drain Logic level Drain Logic level Push Push pull E CUN Pull up with Interrupt EE Drain Logic level ELM Reset State 4 27 84 ST72101 ST72212 ST72213 PORTS Cont d 4 1 4 Register Description 4 1 4 1 Data registers Port A Data Register PADR Port B Data Register PBDR Port C Data Register PCDR Read Write Reset Value 0000 0000 00h 7 0 os on Bit 7 0 D7 DO Data Register 8 bits The DR register has a specific beha
35. In Data External Interrupt to 8 PB3 OCMP2_A Port B3 or TimerA Output Compare 2 External Interrupt PB2 ICAP2_A Port B2 or TimerA Input Capture 2 External Interrupt PB1 OCMP1_A Port B1 or TimerA Output Compare 1 External Interrupt PBO ICAP1_A Port BO or TimerA Input Capture 1 External Interrupt PC5 EXTCLK_A Port C5 or TimerA Input Clock External Interrupt 16 o Port Pr External External Interrupt El Port C2 or Internal Clock Frequency CA E Ree TROUT 10 is driven by bit of the miscellaneous register External mp 18 Pci Port C1 External Interrupt Port CO External Interrupt Port A7 High Sink External Interrupt EIO Port A6 High Sink External Interrupt EIO Port A5 High Sink External Interrupt EIO Port A4 High Sink External Interrupt EIO Port High Sink External Interrupt EIO Port A2 High Sink External Interrupt EIO 28 84 PAT Port A1 High Sink External Interrupt EIO 29 Port AO High Sink External Interrupt EIO 30 TEST V Test mode pin should be tied low in user mode In the EPROM programming pp mode this pin acts as the programming voltage input Ee AA Note 1 Vpp on EPROM OTP only 4 8 84 1 3 EXTERNAL CONNECTIONS The following figure shows the recommended ex ternal connections for the device The Vpp pin is only used for programming OTP an
36. R PRAES EI A BUR eb Bae oe een 18 3 4 POWER SAVING MODES 2 5 ERE Pe dba 21 3 41 Introduction uiuere e RESTI exc eal 21 3 4 2 Slow ocio ET Ree ERE 21 9 4 9 EROR Ere RC aes 21 3 4 4 Halt Mode eere Re Een ea iad ic ee tna nete ac da 22 3 5 MISCELLANEOUS REGISTER ads Peed ede 23 4 ON CHIP PERIPHERALS 2 2 2 we eee 24 AL WO RON jc ETT 24 24 4 1 2 Functional Description ree a XR RR 24 4 1 3 Port Implementation 25 4 1 4 Register Description 2 28 4 2 WATCHDOG TIMER WDG 30 INTOQUCHION oed ete Dur td end itd Foot ee dur 30 422 Main Features vee sues Yee ee ee ke mee 44 44 44 30 4 2 3 Functional Description i sss em rr ERREUR RR A RT ERA 31 4 2 4 Low Power Modes 31 4 2 5 Interrupts 2224 22 eae a de bebe dade ded ae ded s 31 4 2 6 Register Description 31 4 3 16 BIT
37. RISTICS ST72212 AND ST72213 ONLY 75 6 7 SPI CHARACTERISTICS 77 7 GENERAL INFORMATION 80 7 1 EPROM ERASURE eoo ed er Dod E edad es 80 7 2 PACKAGE MECHANICAL 80 7 3 ORDERING INFORMATION 2 82 7 3 1 Transfer Of Customer 82 8 SUMMARY OF CHANGES 84 3 84 ST72101 ST72212 ST72213 1 GENERAL DESCRIPTION 1 1 INTRODUCTION The ST72101 ST72213 and ST72212 HCMOS Microcontroller Units are members of the ST7 family These devices are based on an industry standard 8 bit core and feature an enhanced instruction set They normally operate ata 16MHz oscillator frequency Under software control the ST72101 ST72213 and ST72212 may be placed in either WAIT SLOW or HALT modes thus reducing power consumption The enhanced instruction set and addressing modes afford real programming potential In addition to standard 8 bit data management the ST72101 ST72213 and ST72212 feature true bit manipulation 8x8 unsigned multiplication and indirect addressing modes on the whole memory The devices include an on chip oscillator CPU program memory ROM OTP EPROM versions RAM 22 lines and the following on chip periphera
38. SI pin most significant bit first When data transfer is complete The SPIF bit is set by hardware An interrupt is generated if the SPIE bit is set and the I bit in the CCR register is cleared During the last clock cycle the SPIF bit is set a copy of the data byte received in the shift register is moved to a buffer When the DR register is read the SPI peripheral returns this buffered value Clearing the SPIF bit is performed by the following software sequence 1 An access to the SR register while the SPIF bit is set 2 A write or a read of the DR register Note While the SPIF bit is set all writes to the DR 51 84 ST72101 ST72212 ST72213 SERIAL PERIPHERAL INTERFACE Conta 4 4 4 2 Slave Configuration In slave configuration the serial clock is received on the SCK pin from the master device The value of the SPRO amp SPR1 bits is not used for the data transfer Procedure For correct data transfer the slave device must be in the same timing mode as the mas ter device CPOL and CPHA bits See Figure 36 The SS pin must be connected to a low level signal during the complete byte transmit se quence Clear the MSTR bit and set the SPE bit to as sign the pins to alternate function In this configuration the MOSI pin is a data input and the MISO pin is a data output Transmit Sequence The data byte is parallel loaded into the 8 bit shift register from the internal bus during a wri
39. application can be calculated using the follow ing formula OCiR 38 84 At f lt u PRESC Where At Desired output compare period in sec onds fcpu Internal clock frequency PRESC Timer prescaler factor 2 4 or 8 de pending on CC1 CCO bits see Table 15 Clearing the output compare interrupt request is done by 1 Reading the SR register while the OCFi bit is set 2 An access read or write to the register The following procedure is recommended to pre vent the OCFi bit from being set between the time it is read and the write to the OCR register Write to the OC HR register further compares are inhibited Read the SR register first step of the clearance of the OCFi bit which may be already set Write to the register enables the output compare function and clears the OCFi bit Notes 1 After a processor write cycle to the OC HR reg ister the output compare function is inhibited until the register is also written 2 If the bit is not set the pin is a general I O port and the bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set 3 When the clock is divided by 2 OCFi and OCMPi are set while the counter value equals the OCiR register value see Figure 29 on page 39 This behaviour is the same in OPM or PWM mode When the clock is divided by 4 8 or in exter
40. are wave 3 No DC load or activity on I O s clock input OSCIN driven by external square wave 4 Except OSCIN and OSCOUT 5 WAIT Mode with SLOW Mode selected Based on characterisation results not tested 4 73 84 ST72101 ST72212 ST72213 6 4 RESET CHARACTERISTICS 40 1259 and Vpp 5V 10 unless otherwise eai NK ILL NN 20 40 80 t Pulse duration generated by watch RESET dog and POR reset t Minimum pulse Ins n to be ap PULSE plied on external RESET pin Note 1 These values given only as design guidelines and are not tested 6 5 OSCILLATOR CHARACTERISTICS TA 40 C to 125 C unless otherwise specified Symbol Parameter Test Conditions MEUM E lE Oscillator transconductance 9 on fosc Crystal frequency A 056 start up time 74 84 437 ST72101 ST72212 ST72213 6 6 A D CONVERTER CHARACTERISTICS ST72212 and ST72213 only TA 40 C to 125 C and Vpp 5V 10 unless otherwise specified Sample Duration fcpy 3MHz Res ADC Resolution Pin Differential Linearity Error Integral Error Supply current rise during A D conversion Stabilization time after ADC enable R Resistance of analog sources AN VAIN Hold Capacitance ad R Resistance of sampling switch and 55 internal trace Note ADC Accuracy vs Negative Injection Current For linj 0 8mA the typical leakage induced inside the die is 1 6
41. counter the out put compare function Assigns pins with a programmable value if the OCIE bit is set Sets a flag in the status register Generates an interrupt if enabled Two 16 bit registers Output Compare Register 1 OC1R and Output Compare Register 2 OC2R contain the value to be compared to the free run ning counter each timer clock cycle MS Byte LS Byte OCiHR OCILR These registers are readable and writable and are not affected by the timer hardware A reset event changes the value to 8000h Timing resolution is one count of the free running counter cpU C1 cc0 Procedure To use the output compare function select the fol lowing in the CR2 register Set the bit if an output is needed then the OCMPi pin is dedicated to the output compare function Select the timer clock CC1 CCO see Table 15 And select the following in the CR1 register Select the OLVL i bit to applied to the OCMP pins after the match occurs Set the OCIE bit to generate an interrupt if it is needed When a match is found OCFi bit is set The pin takes OLVL bit value OCMP pin latch is forced low during reset and stays low until valid compares change it to a high level A timer interrupt is generated if the OCIE bit is set in the register and the bit is cleared in the CC register CC The register value required for a specific tim ing
42. counter is equal to the value of the contents of the register the OLVL1 bit is output on OCMP pin See Figure 31 Notes 1 The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt 2 The ICF1 bit is set when an active edge occurs and can generate an interrupt if the ICIE bit is set 3 When the Pulse Width Modulation PWM and One Pulse Mode OPM bits are both set the PWM mode is the only active one 4 11 OLVL1 OLVL2 a continuous signal will be seen on the OCMP 1 pin 5 The ICAP1 pin can not be used to perform input capture The ICAP2 pin can be used to perform input capture ICF2 can be set and IC2R can be loaded but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set 6 When the one pulse mode is used is dedicated to this mode Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode ST72101 ST72212 ST72213 Figure 31 One Pulse Mode Timing Example OCMP1 OLVL2 OLVL1 OLVL2 comparet Note IEDG1 1 OC1R 2ED0h OLVL1 0 OLVL2 1 Figure 32 Pulse Width Modulation Mode Timing Example COUNTER FFFC 2EDO 2ED2 34E2 YFFFC OCMP1 OLVL2 OLVL1 OLVL2 compare2 comparet compare2 N
43. ct The offset is following the opcode Relative Indirect The offset is defined in memory which address follows the opcode 67 84 ST72101 ST72212 ST72213 5 2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions The instructions may be subdivided into 13 main groups as illustrated in the following table Sa sra itc a o ewe s Conditional Branch ______ TL dP Cr ES management TRAP wer rnc pier _ Gode Condon sim se Using a pre byte The instructions are described with one to four bytes In order to extend the number of available op codes for an 8 bit CPU 256 opcodes three differ ent prebyte opcodes are defined These prebytes modify the meaning of the instruction they pre cede The whole instruction becomes PC 2 End of previous instruction PC 1 Prebyte PC opcode 1 Additional word 0 to 2 according to the number of bytes required to compute the ef fective address 68 84 These prebytes enable instruction in Y as well as indirect addressing modes to be implemented They precede the opcode of the instruction in X or the instruction using direct addressing mode The prebytes are PDY 90 Replace an X based instruction using immediate direct indexed or inherent ad dressing mode by a Y one PIX 92 Replace an instruction using di rect direct bit or direct relati
44. d EPROM devices and must be tied to ground in user mode The 10 nF and 0 1 uF decoupling capacitors on the power supply lines are a suggested EMC per formance cost tradeoff Figure 8 Recommended External Connections 1 Or configure unused I O ports ST72101 ST72212 ST72213 The external reset network is intended to protect the device against parasitic resets especially in noisy environments Unused l Os should be tied high to avoid any un necessary power consumption on floating lines An alternative solution is to program the unused ports as inputs with pull up 1 by software as input with pull up 1 Vpp Unused 1 0 9 84 ST72101 ST72212 ST72213 1 4 MEMORY MAP Figure 9 Memory Map HW Registers see Table 5 Short Addressing RAM zero page 16 bit Addressing 256 Bytes RAM 64 Bytes Stack or 16 bit Addressing RAM Reserved 8K Bytes Program Memory 4K Bytes Program Memory Interrupt amp Reset Vectors see Table 4 Table 4 Interrupt Vector Map Vector Address Description memes FFEO FFE1h Not Used 2 Not Used FFE4 FFE5h Not Used FFE6 FFE7h Not Used FFE8 FFE9h Not Used FFEA FFEBh Not Used FFEC FFEDh Not Used FFEE FFEFh TIMER B Interrupt Vector ST72212 only Internal Interrupt FFFO FFF1h Not Used FFF2 FFF3h TIMER A Interrupt Vector Internal Interrupt FFF4 FF F5h SPI Interrupt Vector Internal Interrupt FFF6 FFF7h Not Used FFF8 FFF9h External In
45. de and PWM mode 4 3 3 6 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs This mode is selected via the OPM bit in the CR2 register The one pulse mode uses the Input Capture function and the Output Compare function Procedure To use one pulse mode 1 Load the register with the value corre sponding to the length of the pulse see the for mula in Section 4 3 3 7 2 Select the following in the CR1 register Using the OLVL 1 bit selectthe level to be ap plied to the 1 pin after the pulse Using the OLVL2 bit select the level to be ap plied to the pin during the pulse Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit the ICAP1 pin must be configured as floating input 3 Select the following in the CR2 register Set the bit the OCMP1 pin is then ded icated to the Output Compare 1 function Set the OPM bit Select the timer clock CC1 CCO see Table 15 40 84 One pulse mode cycle When event occurs on ICAP1 OCMP 1 OLVL2 Counter is reset to FFFCh ICF1 bit is set When Counter 1 1 OLVL1 Then on a valid event on the ICAP1 pin the coun ter is initialized to FFFCh and OLVL2 bit is loaded on the pin the bit is set and the val ue FFFDh is loaded in the IC1R register When the value of the
46. dress The direct addressing mode consists of two sub modes Direct short The address is a byte thus requires only one byte after the opcode but only allows 00 FF address ing space Direct long The address is a word thus allowing 64 Kbyte ad dressing space but requires 2 bytes after the op code 5 1 4 Indexed No Offset Short Long In this mode the operand is referenced by its memory address which is defined by the unsigned addition of an index register X or Y with an offset The indirect addressing mode consists of three sub modes Indexed No Offset There is no offset no extra byte after the opcode and allows 00 FF addressing space Indexed Short The offset is a byte thus requires only one byte af ter the opcode and allows 00 1FE addressing space Indexed long The offset is a word thus allowing 64 Kbyte ad dressing space and requires 2 bytes after the op code 5 1 5 Indirect Short Long The required data byte to do the operation is found by its memory address located in memory point er The pointer address follows the opcode The indi rect addressing mode consists of two sub modes Indirect short The pointer address is a byte the pointer size is a byte thus allowing 00 FF addressing space and requires 1 byte after the opcode Indirect long The pointer address is a byte the pointer size is a word thus allowing 64 Kbyte addressing space and requires
47. e When the CPHA bit is set The slave device will receive a clock SCK edge prior to the latch of the first data transfer This first clock edge will freeze the data in the slave device DR register and output the MSBit on to the exter nal MISO pin of the slave device The SS pin low state enables the slave device but the output of the MSBit onto the MISO pin does not take place until the first data transfer clock edge ST72101 ST72212 ST72213 When the CPHA bit is reset Data 15 latched on the occurrence of the first clock transition The slave device does not have any way of knowing when that transition will occur therefore the slave device collision occurs when software attempts to write the DR register after its SS pin has been pulled low For this reason the SS pin must be high between each data byte transfer to allow the CPU to write in the DR register without generating a write colli sion In Master mode Collision in the master device is defined as a write of the DR register while the internal serial clock SCK is in the process of transfer The SS pin signal must be always high on the master device WCOL bit The WCOL bit in the SR register is set if a write collision occurs No SPI interrupt is generated when the WCOL bit is set the WCOL bit is a status flag only Clearing the WCOL bit is done through a software sequence see Figure 37 Figure 37 Clearing the WCOL bit Write Collision Flag Sof
48. e formula 255 x Input Voltage Digital result Reference Voltage Where Reference Voltage is Vpp ST72101 ST72212 ST72213 The accuracy of the conversion is described in the Electrical Characteristics Section Procedure Refer to the CSR and DR register description sec tion for the bit definitions Each analog input pin must be configured as input no pull up no interrupt Refer to the l O ports chapter Using these pins as analog inputs does not affect the ability of the portto be read as a logic input In the CSR register Select the CH2 to CHO bits to assign the ana log channel to convert Refer to Table 19 Set the ADON bit Then the A D converter is enabled after a stabilization time typically 30 us Itthen performs a continuous conversion of the selected channel When a conversion is complete The COCO bit is set by hardware No interrupt is generated The result is in the DR register A write to the CSR register aborts the current con version resets the COCO bit and starts a new conversion 4 5 4 Low Power Modes Note The A D converter may be disabled by re setting the ADON bit This feature allows reduced power consumption when no conversion is need d Description AIT No effect on A D Converter A D Converter disabled After wakeup from Halt mode the A D HALT Converter requires a stabilisation time e before accurate conversions can be performed
49. e values The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start up stabilisation time Use of an external CMOS oscillator is recom mended when crystals outside the specified fre quency ranges are to be used Table 6 Recommended Values for 16 MHz Crystal Resonator Co lt 7pF ion 56 47 22 56 47 22 Co parasitic shunt capacitance of the quartz crys tal Rsmax equivalent serial resistor of the crystal up er See crystal specification Coscour Coscin maximum total capacitance on OSGIN and OSCOUT including the external ca pacitance plus the parasitic capacitance of the board and the device 16 84 Figure 12 External Clock Source Connections OSCIN OSCOUT D EXTERNAL CLOCK Figure 13 Crystal Ceramic Resonator OSCIN OSCOUT D D I T Figure 14 Clock Prescaler Block Diagram L OSCIN OSCOUT fopu to CPU and Peripherals 3 2 RESET 3 2 1 Introduction There are three sources of Reset RESET pin external source Power On Reset Internal source WATCHDOG Internal Source The Reset Service Routine vector is located at ad dress FFFEh FFFFh 3 2 2 External Reset The RESET pin is both an input and an open drain output with integrated pull up resistor When one of the inter
50. ed the HALT instruction will generate a Reset ST72101 ST72212 ST72213 4 2 4 Low Power Modes Mode Description WAIT No effect on Watchdog Immediate reset generation as soon as HALT the HALT instruction is executed if the Watchdog 15 activated WDGA bit is set 4 2 5 Interrupts None 4 2 6 Register Description CONTROL REGISTER CR Read Write Reset Value 0111 1111 7Fh 7 0 Bit 7 WDGA Activation bit This bit is set by software and only cleared by hardware after a reset When WDGA 1 the watchdog can generate a reset 0 Watchdog disabled 1 Watchdog enabled Bit 6 0 T 6 0 7 bit timer MSB to LSB These bits contain the decremented value A reset is produced when it rolls over from 40h to T6 becomes cleared Table 14 Watchdog Timer Register Map and Reset Values Address Register 7 Hex Label 0024h WDGCR WDGA T6 5 T4 T3 T2 T1 TO Reset Value 0 1 1 1 1 1 1 1 31 84 ST72101 ST72212 ST72213 4 3 16 BIT TIMER 4 3 1 Introduction The timer consists of a 16 bit free running counter driven by a programmable prescaler It may be used for a variety of purposes including pulse length measurement of up to two input sig nals input capture or generation of up to two out put waveforms output compare and PWM Pulse lengths and waveform periods can be mod ulated from a few microseconds to several milli seconds using the timer prescaler and the CPU clock prescaler
51. er reads the serial peripheral data I O register the buffer is actually being read Warning A write to the DR register places data directly into the shift register for transmission A write to the the DR register returns the value lo cated in the buffer and not the contents of the shift register See Figure 34 ST72101 ST72212 ST72213 SERIAL PERIPHERAL INTERFACE Table 18 SPI Register Map and Reset Values Address Register Hex Name 21 EE SSH ES ES 22 a Value ES mo 23 28 61 84 ST72101 ST72212 ST72213 4 5 8 BIT A D CONVERTER ADC 4 5 1 Introduction 4 5 2 Main Features The on chip Analog to Digital Converter ADC pe 8 bit conversion ripheral is a 8 bit successive approximation con Up to 8 channels with multiplexed input verter with internal sample and hold circuitry This Linear successive approximation peripheral has up to 8 multiplexed analog input channels refer to device pin out description that Data register DR which contains the results allow the peripheral to convert the analog voltage Conversion complete status flag levels from up to 8 different sources On off bit to reduce consumption The result of the conversion is stored in a 8 bit Data Register The A D converter is controlled through a Control Status Register The block diagram is shown in Figure 39 Figure 39 ADC block diagram Control Status Register CSR
52. er with a default blank content FFh while ROM factory coded parts contain the code sent by customer There is one common EPROM version for debugging and prototyping which features the maximum memory size and peripherals of the family Care must be taken to only use resources available on the target device 7 3 1 Transfer Of Customer Code ROM contents are to be sent on diskette or by electronic means with the hexadecimal file in S19 format generated by the development tool All un used bytes must be set to FFh The selected options are communicated to STMi croelectronics using the correctly completed OP TION LIST appended The STMicroelectronics Sales Organization will be pleased to provide detailed information on con tractual points Customer code is made up of the ROM contents and the list of the selected options if any The Figure 54 ROM Factory Coded Device Types TEMP DEVICE PACKAGE RANGE u XXX TL Code name defined by STMicroelectronics 1 standard 0 to 70 C 3 automotive 40 to 125 C 6 industrial 40 to 85 C B Plastic DIP M Plastic SOIC ST72101G1 ST72101G2 ST72212G2 ST72213G1 Figure 55 OTP User Programmable Device Types XXX Option if any 3 automotive 40 to 125 C 6 industrial 40 to 85 TEMP DEVICE PACKAGE RANGE B Plastic DIP M Plastic SOIC ST72T101G1 ST72T101G2 ST721212G2 ST721213G1 Note The ST72E251G2D0 CERDIP 25 C is used as the
53. erates a pulse thatis used to resetthe applica tion at approximately 2V Power On Reset is designed exclusively to cope with power up conditions and should not be used in order to attempt to detect a drop in the power supply voltage Caution to re initialize the Power On Reset the power supply must fall below approximately 0 8V Vtn prior to rising above 2V If this condition is not respected on subsequent power up the Reset pulse may not be generated An external Reset pulse may be required to correctly reactivate the circuit INTERNAL RESET ke 2 gt POWER ON RESET WATCHDOG RESET 17 84 ST72101 ST72212 ST72213 3 3 INTERRUPTS The ST7 core may be interrupted by one of two dif ferent methods maskable hardware interrupts as listed in the Interrupt Mapping Table and a non maskable software interrupt TRAP The Interrupt processing flowchart is shown in Figure 16 The maskable interrupts must be enabled clearing the bit in order to be serviced However disabled interrupts may be latched and processed when they are enabled see external interrupts subsec tion When an interrupt has to be serviced Normal processing is suspended at the end of the current instruction execution The PC X A and CC registers are saved onto the stack The bit of the CC register is set to prevent addi tional interrupts ThePC is then loaded with the interrupt vector of the int
54. erefore be lost if the clear sequence is executed ST72101 ST72212 ST72213 INTERRUPTS Cont d Figure 16 Interrupt Processing Flowchart FROM RESET STACK PC X A CC SET BIT LOAD PC FROM INTERRUPT VECTOR EXECUTE INSTRUCTION RESTORE X CC FROM STACK THIS CLEARS BIT BY DEFAULT 19 84 ST72101 ST72212 ST72213 Table 7 Interrupt Mapping Source Register em Vector Priority Block Label HALT Address Order BIN eo area erin PATER yes E PBOPB7 NA NA yes FFFERTFFSh Not Used LES ModeFault Fault MODF Input 1 _ TIMER A Input InputCapture2 2 TASR ICF2 A A FFF2h FFF3h I Compare 2 IER Not Used FFFOh FFFih FFF 1h AAA rr OutputComparet Compare 1 _ Input 2 TBSR B FFEEh FFEFh 2 SS PH B FFECh FFEDh FFEDh ETE FFEBh ME FFEQh Not Used FFEGR FFE7R FFESRFFESR FFE2R KFFE3h 009S Priority FFEOh FFE 1h Priority Note 1 Timer B is available on ST72212 only 4 20 84 3 4 POWER SAVING MODES 3 4 1 Introduction There are three Power Saving modes Slow Mode is selected by setting the relevant bits in the Mis cellaneous register Wait and Halt modes may be entered using the and HALT instructions 3 4 2 Slow M
55. erruptto service and the first instruction of the interrupt service routine is fetched refer to the Interrupt Mapping Table for vector address es The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack Note As a consequence of the IRET instruction the bit will be cleared and the main program will resume Priority management By default a servicing interrupt can not be inter rupted because the bit is set by hardware enter ing in interrupt routine In the case several interrupts are simultaneously pending an hardware priority defines which one will be serviced first see the Interrupt Mapping Ta ble Non Maskable Software Interrupts This interrupt is entered when the TRAP instruc tion is executed regardless of the state of the bit It will be serviced according to the flowchart on Figure 16 Interrupts and Low power mode All interrupts allow the processor to leave the Wait low power mode Only external and specific men tioned interrupts allow the processor to leave the 18 84 Halt low power mode refer to the Exit from HALT column in the Interrupt Mapping Table External Interrupts External interrupt vectors can be loaded in the PC register if the corresponding external interrupt oc curred and if the bit is cleared These interrupts allow the processor to leave the Halt low power mode The exter
56. esolution is one count of the free running counter Procedure To use the input capture function select the follow ing in the CR2 register Select the timer clock CC1 CCO see Table 15 Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit the ICAP2 pin must be configured as floating input And select the following in the CR1 register Set the ICIE bit to generate an interrupt after an input capture coming from both the ICAP1 pin or the ICAP2 pin Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit the ICAP1pin must be configured as floating input 36 84 When an input capture occurs ICFi bit is set The register contains the value of the free running counter on the active transition on the ICAPi pin see Figure 27 A timer interrupt is generated if the ICIE bit is set and the bit is cleared in the CC register Other wise the interrupt remains pending until both conditions become true Clearing the Input Capture interrupt request is done in two steps 1 Reading the SR register while the ICF bit is set 2 An access read or write to the register Notes 1 After reading the IC HR register transfer of input capture data is inhibited until the ICILR register is also read 2 The IC R register always contains the free run ning counter value which corresponds to the most recent
57. ge only Rising and falling edge Note Any modification of one of these two bits re sets the interrupt request related to this interrupt vector Bit 1 2 Unused always read at 0 Warning Software must write 1 to these bits for compatibility with future products Bit 0 SMS S ow Mode Select This bit is set and cleared by software 0 Normal mode Oscillator frequency 2 Reset state 1 Slow mode Oscillator frequency 32 23 84 ST72101 ST72212 ST72213 4 ON CHIP PERIPHERALS 4 1 1 0 PORTS 4 1 1 Introduction The I O ports offer different functional modes transfer of data through digital inputs and outputs and for specific pins analog signal input ADC alternate signal input output for the on chip pe ripherals external interrupt generation An port is composed of up to 8 pins Each pin can be programmed independently as digital input with or without interrupt generation or digital out put 4 1 2 Functional Description Each port is associated to 2 main registers Data Register DR Data Direction Register DDR and some of them to an optional register Option Register OR Each pin may be programmed using the corre sponding register bits in DDR and OR registers bit X corresponding to pin X of the port The same cor respondence is used for the DR register The following description takes into account the OR register for spec
58. he high part of the counter value transferred by the input capture 1 event 7 0 INPUT CAPTURE 1 LOW REGISTER IC1LR Read Only Reset Value Undefined This is an 8 bit read only register that contains the low part of the counter value transferred by the in put capture 1 event 7 0 OUTPUT COMPARE 1 HIGH REGISTER OC1HR Read Write Reset Value 1000 0000 80h This is an 8 bit register that contains the high part of the value to be compared to the CHR register 7 0 OUTPUT COMPARE 1 LOW REGISTER OC1LR Read Write Reset Value 0000 0000 00h This is an 8 bit register that contains the low part of the value to be compared to the CLR register 7 0 4 16 BIT TIMER Cont d OUTPUT COMPARE 2 HIGH REGISTER OC2HR Read Write Reset Value 1000 0000 80h This is an 8 bit register that contains the high part of the value to be compared to the CHR register 7 0 peu qo OUTPUT COMPARE 2 LOW REGISTER OC2LR Read Write Reset Value 0000 0000 00h This is an 8 bit register that contains the low part of the value to be compared to the CLR register 7 0 COUNTER HIGH REGISTER CHR Read Only Reset Value 1111 1111 FFh This is an 8 bit register that contains the high part of the counter value 7 0 gp jJ COUNTER LOW REGISTER CLR Read Only Reset Value
59. ial Peripheral Interface Block Diagram Internal Bus IT D request ite E SPI STATE ES T SS Em FX ER FX SERIAL CLOCK GENERATOR 50 84 437 SERIAL PERIPHERAL INTERFACE Cont d 4 4 4 Functional Description Figure 33 shows the serial peripheral interface SPI block diagram This interface contains 3 dedicated registers A Control Register CR A Status Register SR A Data Register DR Refer to the CR SR and DR registers in Section 4 4 7for the bit definitions 4 4 4 1 Master Configuration In a master configuration the serial clock is gener ated on the SCK pin Procedure Select the SPRO amp SPR1 bits to define the se rial clock baud rate see CR register Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock see Figure 36 The SS pin must be connected to a high level signal during the complete byte transmit se quence The MSTR and SPE bits must be set they re main set only if the SS pin is connected to a high level signal ST72101 ST72212 ST72213 In this configuration the MOSI pin is a data output and to the MISO pin is a data input Transmit sequence The transmit sequence begins when a byte is writ ten the DR register The data byte is parallel loaded into the 8 bit shift register from the internal bus during a write cycle and then shifted out serially to the MO
60. ific ports which do not provide this register refer to the I O Port Implementation Section 4 1 3 The generic I O block diagram is shown on Figure 20 4 1 2 1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit In this case reading the DR register returns the digital value applied to the external I O pin Different input modes can be selected by software through the OR register Notes 1 All the inputs are triggered by a Schmitt trigger 2 When switching from input mode to output mode the DR register should be written first to output the correct value as soon as the port is con figured as an output 24 84 Interrupt function When an is configured in Input with Interrupt an event on this I O can generate an external In terrupt request to the CPU The interrupt polarity is given independently according to the description mentioned in the Miscellaneous register or in the interrupt register where available Each pin can independently generate an Interrupt request Each external interrupt vector is linked to a dedi cated group of I O port pins see Interrupts sec tion If several input pins are configured as inputs to the same interrupt vector their signals are logi cally ANDed before entering the edge level detec tion block For this reason if one of the interrupt pins is tied low it masks the other ones 4 1 2 2 Output Mode The pin is configured in output m
61. input capture 3 The 2 input capture functions can be used together even if the timer also uses the output compare mode 4 n One pulse Mode and PWM mode only the input capture 2 can be used 5 The alternate inputs ICAP1 amp ICAP2 are always directly connected to the timer So any transitions on these pins activate the input cap ture process 6 Moreover if one of the ICAP pin is configured as an input and the second one as an output an interrupt can be generated if the user toggle the output pin and if the ICIE bit is set 7 The TOF bit can be used with interrupt in order to measure event that go beyond the timer range FFFFh ST72101 ST72212 ST72213 16 BIT TIMER Conta Figure 26 Input Capture Block Diagram Control Register 1 CR1 EDGE EDGE DETECT CIRCUIT2 CIRCUIT1 IC2R Register IC1R Register Status Register SR Control Register 2 CR2 TIT ileje COUNTER Figure 27 Input Capture Timing Diagram Timer clock 11 NST Ll COUNTER REGISTER X o XC ICAPi PIN ICAPi FLAG ICAPi REGISTER Note Active edge is rising edge 37 84 ST72101 ST72212 ST72213 16 BIT TIMER Cont d 4 3 3 4 Output Compare In this section the index may be 1 or 2 This function can be used to control an output waveform or indicating when a period of time has elapsed When match is found between the Output Com pare register and the free running
62. input capture reset value 1 An input capture has occurred or the counter has reached the OC2R value in PWM mode To clear this bit first read the SR register then read or write the low byte of the IC1R IC1LR regis ter Bit 6 OCF1 Output Compare Flag 1 No match reset value 1 The content of the free running counter has matched the content of the register To clear this bit first read the SR register then read or write the low byte of the OC1R OC1LR reg ister Bit 5 TOF Timer Overflow 0 No timer overflow reset value 1 The free running counter rolled over from FFFFh to 0000h To clear this bit first read the SR reg ister then read or write the low byte of the CR CLR register Note Reading or writing the ACLR register does not clear TOF Bit 4 ICF2 Input Capture Flag 2 0 No input capture reset value 1 An input capture has occurred To clear this bit first read the SR register then read or write the low byte of the IC2R IC2LR register Bit 3 OCF2 Output Compare Flag 2 E No match reset value 1 The content of the free running counter has matched the content of the OC2R register To clear this bit first read the SR register then read or write the low byte of the OC2R OC2LR reg ister 46 84 Bit 2 0 Reserved forced by hardware to 0 INPUT CAPTURE 1 HIGH REGISTER IC1HR Read Only Reset Value Undefined This is an 8 bit read only register that contains t
63. l lowed by a read or write to the DR register 0 Data transfer is in progress or has been ap proved by a clearing sequence 1 Data transfer between the device and an exter nal device has been completed Note While the SPIF bit is set all writes to the DR register are inhibited Bit 6 WCOL Write Collision status This bit is set by hardware when a write to the DR register is done during a transmit sequence It is cleared by a software sequence see Figure 37 0 No write collision occurred 1 A write collision has been detected Bit 5 Unused Bit 4 MODF Mode Fault flag This bit is set by hardware when the SS pin is pulled low in master mode see Section 4 4 4 5 Master Mode Fault An SPI interrupt can be gen erated if SPIE 1 in the CR register This bit is cleared by a software sequence An access to the SR register while MODF 1 followed by a write to the CR register 0 No master mode fault detected 1 A fault in master mode has been detected Bits 3 0 Unused 60 84 DATA I O REGISTER DR Read Write Reset Value Undefined 7 0 or os os 09 oe or The DR register is used to transmit and receive data on the serial bus In the master device only a write to this register will initiate transmission re ception of another byte Notes During the last clock cycle the SPIF bit 15 set a copy of the received data byte in the shift register is moved to a buffer When the us
64. le is set are latched and can be processed when is cleared By default an interrupt routine is not interruptable because the bit is set by hardware when you en 14 84 ter it and reset by the IRET instruction at the end of the interrupt routine If the bit is cleared by soft ware in the interrupt routine pending interrupts are serviced regardless of the priority level of the cur rent interrupt routine Bit 2 Negative This bit is set and cleared by hardware It is repre sentative of the result sign of the last arithmetic logical or data manipulation It is a copy of the 7 bit of the result 0 The result of the last operation is positive or null 1 The result of the last operation is negative i e the most significant bit is a logic 1 This bit is accessed by the JRMI and JRPL instruc tions Bit 1 2 Z Zero This bit is set and cleared by hardware This bit in dicates that the result of the last arithmetic logical or data manipulation is zero 0 The result of the last operation is different from zero 1 The result of the last operation is zero This bit is accessed by the JREQ and JRNE test instructions Bit 0 C Carry borrow This bit is set and cleared by hardware and soft ware It indicates an overflow or an underflow has occurred during the last arithmetic operation 0 No overflow or underflow has occurred 1 An overflow or underflow has occurred This bit is driven by the SCF and R
65. led Bit 5 OPM One Pulse Mode 0 One Pulse Mode is not active 1 One Pulse Mode is active the ICAP1 pin can be used to trigger one pulse on the OCMP 1 the active transition is given by the IEDG1 bit The length of the generated pulse depends on the contents of the register ST72101 ST72212 ST72213 Bit 4 PWM Pulse Width Modulation 0 PWM mode is not active 1 PWM mode is active the OCMP1 pin outputs a programmable cyclic signal the length of the pulse depends on the value of OC1R register the period depends on the value of OC2R regis ter Bit 2 CC1 CCO Clock Control The value of the timer clock depends on these bits Table 15 Clock Control Bits External Clock where available Bit 1 IEDG2 Input Edge 2 This bit determines which type of level transition on the ICAP2 pin will trigger the capture 0 A falling edge triggers the capture 1 A rising edge triggers the capture Bit 0 EXEDG External Clock Edge This bit determines which type of level transition on the external clock pin EXTCLK will trigger the free running counter 0 A falling edge triggers the free running counter 1 A rising edge triggers the free running counter 45 84 ST72101 ST72212 ST72213 16 BIT TIMER Cont d STATUS REGISTER SR Read Only Reset Value 0000 0000 00h The three least significant bits are not used 7 0 fen fener Te eT Bit 7 ICF1 Input Capture Flag 1 0 No
66. ls Analog to Digital Converter ADC with 6 multiplexed analog inputs ST72212 and ST72213 only industry standard synchronous SPI serial interface digital Watchdog one or two independent 16 bit Timers one featuring an External Clock Input and both featuring Pulse Generator capabilities 2 Input Captures and 2 Output Compares Figure 1 ST72101 ST72213 and ST72212 Block Diagram Internal CONTROL 8 BIT CORE ALU PROGRAM MEMORY 4 8K Bytes POWER E SUPPLY 1 ST72213 and 5772212 only 2 ST72212 only 4 84 8 bits gt gt PB7 8 bits Sar TIMERA gt 5 6 bits 8 BIT ADC 1 EP 2 WATCHDOG 1 2 PIN DESCRIPTION Figure 2 ST72212 Pinout SO28 RESET OSCIN OSCOUT SS PB7 SCK PB6 MISO PB5 MOSI PB4 OCMP2 A PB3 ICAP2 A PB2 OCMP1 A PB1 ICAP1 A PBO AINS EXTCLK A PC5 AIN4 OCMP2_B PC4 AIN3 ICAP2_B PC3 RESET OSCIN OSCOUT SS PB7 SCK PB6 MISO PB5 4 2 2 2 OCMP1 A PB1 ICAP1 A PBO AINS EXTCLK A PC5 AIN4 PC4 AIN3 PC3 1 Vop EPROM OTP only RESET OSCIN OSCOUT SS PB7 SCK PB6 MISO PB5 MOSI PB4 OCMP2 A PB3 ICAP2 A PB2 OCMP1_A PB1 ICAP1 A PBO A PC5 Vss TEST pp PAO PA1 PA2 PA3 PAS PAS 7 1 B AINO PC1 OCMP1 B AIN1 PC2 CLKOUT AIN2 Vss TEST V
67. mpare2 Low Register R W R W Read Only Read Only Read Only R W R W Read Only Read Only Read Only Read Only Read Only Read Only iid 0040h Reserved Area 1 Byte 4 11 84 ST72101 ST72212 ST72213 Block Register Address 9 Register name Reset Status Name Label 0041h TBCR2 Control Register2 0042h TBCR1 Control Register iM 0043h TBSR Status Register Read Only 0044h 0045h TBIC1HR Input Capture1 High Register Read Only Input Capture1 Low Register Read Only 0046h 0047h TBOC1HR Output Compare1 High Register R W TBOCILR Output Compare1 Low Register R W 0048h 0049h Timer B TBCHR Counter High Register Read Only TBCLR Counter Low Register Read Only 004Ah 004Bh TBACHR Alternate Counter High Register Read Only TBACLR Alternate Counter Low Register Read Only 004Ch 004Dh TBIC2HR Input Capture2 High Register Read Only TBIC2LR Input Capture2 Low Register Read Only 004Eh 004Fh TBOC2HR Output Compare2 High Register R W TBOC2LR Output Compare2 Low Register R W 0050h to 006Fh Reserved Area 32 Bytes 0070h ADC 2 ADCDR Data Register 2 0071h ADCCSR Control Status Register 007Fh Reserved Area 14 Bytes Notes 1 ST72212 only reserved area for other devices 2 ST72212 and ST72213 only reserved otherwise 12 84 4 2 CENTRAL PROCESSING UNIT 2 1 INTRODUCTION This CPU has a full 8 bit architecture and contains six internal registers allowing efficient 8 bit data manipulation 2 2 MAIN
68. nal clock mode OCFi and OCMP are set while the counter value equals the OCIR register value plus 1 see Figure 30 on page 39 4 The output compare functions can be used both for generating external events on the OCMP pins even if the input capture mode is also used 5 The value in the 16 bit register and the OLVi bit should be changed after each suc cessful comparison in order to control an output waveform or establish a new elapsed timeout 574 ST72101 ST72212 ST72213 16 BIT TIMER Cont d Figure 28 Output Compare Block Diagram mu Pls COUNTER Control Register 2 CR2 Control Register 1 CR1 wwreanaccpuctock TIMER CLOCK COUNTER OUTPUT COMPARE REGISTER OUTPUT COMPARE FLAG OCFi OCMPi PIN OLVLi 1 INTERNAL CPU CLOCK TIMER CLOCK COUNTER OUTPUT COMPARE REGISTER COMPARE REGISTER LATCH OCFi AND OCMPi PIN OLVLi 1 1574 39 84 ST72101 ST72212 ST72213 16 BIT TIMER 4 3 3 5 Forced Compare In this section may represent 1 or 2 The following bits of the CR1 register are used FOLV2 FOLV1 OLVL2 OLVL1 When the FOLVi bit is set by software the bit is copied to the OCMP pin The OLVi bit has to be toggled in order to toggle the pin when it is enabled bit 1 The OCFi bitis then not set by hardware and thus no interrupt request is generated FOLVLi bits have no effect in both one pulse mo
69. nal Reset sources is active the Reset pin is driven low for a duration of treser to reset the whole application 3 2 3 Reset Operation The duration of the Reset state is a minimum of 4096 internal CPU Clock cycles During the Reset state all I Os take their reset value A Reset signal originating from an external source must have a duration of at least sg in order to be recognised This detection is asynchronous and therefore the MCU can enter Reset state even in Halt mode At the end of the Reset cycle the MCU may be held in the Reset state by an External Reset sig nal The RESET pin may thus be used to ensure Vpp has risen to a point where the MCU can oper ate correctly before the user program is run Fol Figure 15 Reset Block Diagram OSCILLATOR SIGNAL ST72101 ST72212 ST72213 lowing a Reset event or after exiting Halt mode a 4096 CPU Clock cycle delay period 15 initiated in order to allow the oscillator to stabilise and to en sure that recovery has taken place from the Reset state In the high state the RESET pin is connected in ternally to a pull up resistor Ron This resistor can be pulled low by external circuitry to reset the device The RESET pin is an asynchronous signal which plays a major role in EMS performance In a noisy environment it is recommended to use the exter nal connections shown in Figure 8 3 2 4 Power on Reset This circuit detects the ramping up of Vpp and gen
70. nal interrupt polarity is selected through the miscellaneous register or interrupt register if available External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine If several input pins connected to the same inter rupt vector are configured as interrupts their sig nals are logically ANDed before entering the edge level detection block Warning The type of sensitivity defined in the Miscellaneous or Interrupt register if available applies to the El source In case of an ANDed source as described on the I O ports section a low level on an I O pin configured as input with in terrupt masks the interrupt request even in case of rising edge sensitivity Peripheral Interrupts Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both The I bit of the CC register is cleared The corresponding enable bit is set in the control register If any of these two conditions is false the interrupt is latched and thus remains pending Clearing an interrupt request is done by writing 0 to the corresponding bit in the status register or an access to the status register while the flag is set followed by a read or write of an associated register Note the clearing sequence resets the internal latch A pending interrupt i e waiting for being en abled will th
71. ode In Slow mode the oscillator frequency can be di vided by a value defined in the Miscellaneous Register The CPU and peripherals are clocked at this lower frequency Slow mode is used to reduce power consumption and enables the user to adapt clock frequency to available supply voltage 3 4 3 Wait Mode Wait mode places the MCU in a low power con sumption mode by stopping the CPU peripher als remain active During Wait mode the I bit CC Register is cleared so as to enable all interrupts All other registers and memory remain unchanged The MCU will remain in Wait mode until an Inter rupt or Reset occurs whereupon the Program Counter branches to the starting address of the In terrupt or Reset Service Routine The MCU will remain in Wait mode until a Reset or an Interrupt occurs causing it to wake up Refer to Figure 17 below ST72101 ST72212 ST72213 Figure 17 WAIT Flow Chart INSTRUCTION OSCILLATOR ON PERIPH CLOCK CPU CLOCK OFF CLEARED OSCILLATOR PERIPH CLOCK CPU CLOCK I BIT 4096 CPU CLOCK CYCLES DELAY OSCILLATOR PERIPH CLOCK CPU CLOCK I BIT FETCH RESET VECTOR OR SERVICE INTERRUP Note Before servicing an interrupt the CC register is pushed on the stack The I Bit is set during the inter rupt routine and cleared when the CC register is popped 21 84 ST72101 ST72212 ST72213 POWER SAVING MODES Cont d 3 4 4 Halt Mode The Halt mode is the MCU lowest powe
72. ode by setting the corresponding DDR register bit In this mode writing 0 or 1 to the DR register applies this digital value to the I O pin through the latch Then reading the DR register returns the previously stored value Note In this mode the interrupt function is disa bled 4 1 2 3 Digital Alternate Function When an on chip peripheral is configured to use a pin the alternate function is automatically select ed This alternate function takes priority over standard I O programming When the signal is coming from an on chip peripheral the I O pin is automatically configured in output mode push pull or open drain according to the peripheral When the signal is going to an on chip peripheral the I O pin has to be configured in input mode In this case the pin s state is also digitally readable by addressing the DR register Notes 1 Input pull up configuration can cause an unex pected value at the input of the alternate peripher al input 2 When the peripheral uses a pin as input and output this pin must be configured as an input DDR 0 Warning The alternate function must not be acti vated as long as the pin is configured as input with interrupt in order to avoid generating spurious in terrupts 1571 PORTS 4 1 2 4 Analog Alternate Function When the pin is used as an input the must be configured as input floating The analog multi plexer cont
73. or s Pesmo ____ Pones orsPi masier Save Ertemel menuet EN pe _____ _____ 2 VO Fors EXA s LO EE 1 PC5 EXTCLK_A AIN5 EE or TimerA Input Clock or ADC Analog Port C2 or Internal Clock Frequency Output or 17 PC2 CLKOUT AIN2 ADC Analog Input 2 Clockout is driven by Bit 5 External Interrupt of the miscellaneous register PC1 AIN1 Port C1 or ADC Analog Input 1 External Interrupt El1 Port A7 High Sink External Interrupt EIO peoe 26 8 VS Test mode pin should be tied low in user mode In the EPROM pro gramming mode this pin acts as the programming voltage input Vpp Note 1 Vp PROM OTP only pon 577 7184 ST72101 ST72212 ST72213 Table 3 ST72101 Pin Configuration DRE Description SDIP32 SO28 Typ RESET Bidirectional Active low Top priority non maskable interrupt EPEE OSCIN EN Input Output Oscillator pin These pins connect a parallel resonant crystal or OSCOUT an external source to the on chip oscillator PB7 SS Port B7 or SPI Slave Select active low External Interrupt PB6 SCK Port B6 or SPI Serial Clock External Interrupt 6 6 PB5 MISO Port B5 or SPI Master In Slave Out Data External Interrupt PB4 MOSI Port B4 or SPI Master Out Slave
74. ote OC1R22bEDOh OC2R 34E2 OLVL1 0 OLVL2 1 ki 41 84 ST72101 ST72212 ST72213 16 BIT TIMER Cont d 4 3 3 7 Pulse Width Modulation Mode Pulse Width Modulation PWM mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers The pulse width modulation mode uses the com plete Output Compare 1 function plus the OC2R register and so these functionality can not be used when the PWM mode is activated Procedure To use pulse width modulation mode 1 Load the OC2R register with the value corre sponding to the period of the signal 2 Load the register with the value corre sponding to the length of the pulse if 1 0 and OLVL2 1 3 Select the following in the CR1 register Using the OLVL 1 bit select the level to be ap plied to the OCMP1 pin after a successful comparison with OC1R register Using the OLVL2 bit select the level to be ap plied to the OCMP1 pin after a successful comparison with OC2R register 4 Select the following in the CR2 register Set bit the OCMP1 pin is then dedicat ed to the output compare 1 function Set the PWM bit Select the timer clock 1 see Table 15 If OLVL1 1 and OLVL2 0 the length of the posi tive pulse is the difference between the OC2R and OCAR registers If OLVL1 OLVL2 a continuous signal will be seen on the pin
75. pins connect a parallel resonant 3 foscor 0 crystal or an external source to the on chip oscillator e mo vo pones or SPI Save _ ___ o A s resocwera vo Pon Bs or Tmora Oupa Comparez Eroma merwe ET s vo Por Beor Tmora mour Enora runt E E E 12 POS EXTCLK_A AIN5 A AIN5 VO PortC5orTimerA Input Clock or ADC Analog Input VO PortC5orTimerA Input Clock or ADC Analog Input Input5 External Interrupt External Interrupt MM B AIN4 input Output Compare 2or ADCAnalog External Interrupt O Rig eet Fe Ce ET Port C2or Internal Clock Frequency Output or ADC Analog Input 2 Clockout is driven by Bit 5 ofthe External Interrupt miscellaneous register a Nw S a Nw Port A1 High Sink External Interrupt EIO Port AO High Sink External Interrupt EIO TEST Veo Test mode pin should be tied low in user mode In the EPROM program ming mode this pin acts as the programming 1 input Vpp 4 6 84 ST72101 ST72212 ST72213 Table 2 ST72213 Pin Configuration e __ SDIP32 5028 2 2 joson Input Output Oscillator These pins connect parallel resonant 3 lt crystal or an external source to the on chip oscillat
76. r con sumption mode The Halt mode is entered by exe cuting the HALT instruction The internal oscillator is then turned off causing all internal processing to be stopped including the operation of the on chip peripherals The Halt mode cannot be used when the watchdog is enabled if the HALT instruction is executed while the watchdog system is enabled a watchdog reset is generated thus resetting the en tire MCU When entering Halt mode the bit in the CC Reg ister is cleared so as to enable External Interrupts If an interrupt occurs the CPU becomes active The MCU can exit the Halt mode upon reception of an interrupt or a reset Refer to the Interrupt Map ping Table The oscillator is then turned on and a stabilization time is provided before releasing CPU operation The stabilization time is 4096 CPU clock cycles After the start up delay the CPU continues oper ation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up 22 84 Figure 18 HALT Flow Chart HALT INSTRUCTION WDG ENABLED N OSCILLATOR PERIPH CLOCK CPU CLOCK WATCHDOG RESET OSCILLATOR PERIPH CLOCK CPU CLOCK I BIT 4096 CPU CLOCK CYCLES DELAY OSCILLATOR PERIPH CLOCK CPU CLOCK I BIT FETCH RESET VECTOR OR SERVICE INTERRUPT 1 or some specific interrupts 2 if reset PERIPH CLOCK ON if interrupt PERIPH CLOCK OFF Note Before servicing an interrupt the CC register is pushed on
77. r when the T6 bit reaches zero Figure 21 Watchdog Block Diagram WATCHDOG CONTROL REGISTER CR 7 DOWNCOUNTER CLOCK DIVIDER 12288 30 84 437 WATCHDOG TIMER Cont d 4 2 3 Functional Description The counter value stored in the CR register bits T6 TO is decremented every 12 288 machine cy cles and the length of the timeout period can be programmed by the user in 64 increments If the watchdog is activated the WDGA bit is set and when the 7 bit timer bits T6 TO rolls over from 40h to 3Fh T6 becomes cleared it initiates a reset cycle pulling low the reset pin for typically 500ns The application program must write in the CR reg ister at regular intervals during normal operation to prevent an MCU reset The value to be stored in the CR register must be between FFh and see Table 13 The WDGA bit is set watchdog enabled The T6 bit is set to prevent generating an imme diate reset The T5 TO bits contain the number of increments which represents the time delay before the watchdog produces a reset Table 13 Watchdog Timing fcpy 8 MHz CR Register WDG timeout period initial value ms Max FFh Min COh 98 304 1 536 Notes Following a reset the watchdog is disa bled Once activated it cannot be disabled except by a reset The T6 bit can be used to generate a software re set the WDGA bit is set and the T6 bit is cleared If the watchdog is activat
78. rface Master Slave MASTER MSBit 4 LSBit 8 BIT SHIFT SPI CLOCK GENERATOR ST72101 ST72212 ST72213 4 4 3 General description The SPI is connected to external devices through 4 alternate pins MISO Master In Slave Out pin MOSI Master Out Slave In pin SCK Serial Clock pin SS Slave select pin A basic example of interconnections between a single master and a single slave is illustrated on Figure 33 The MOSI pins are connected together as are MISO pins In this way data is transferred serially between master and slave most significant bit first When the master device transmits data to a slave device via MOSI pin the slave device responds by sending data to the master device via the MISO pin This implies full duplex transmission with both data out and data in synchronized with the same clock signal which is provided by the master de vice via the SCK pin Thus the byte transmitted is replaced by the byte received and eliminates the need for separate transmit empty and receiver full bits A status flag is used to indicate that the operation is com plete Four possible data clock timing relationships may be chosen see Figure 36 but master and slave must be programmed with the same timing mode SLAVE MSBit 4 LSBit 7 8 BIT SHIFT REGISTER 49 84 ST72101 ST72212 ST72213 SERIAL PERIPHERAL INTERFACE Cont d Figure 34 Ser
79. ro o3 noon oss foo Fc ozs ose poor 00125 o i770 07125 Fe oz e pep je Pa fron foafoa 6278 Pa os oov Pt oar Ti oos Lee Figure 52 32 Pin Shrink Plastic Dual In Line Package VR01725J Figure 53 32 Pin Shrink Ceramic Dual In Line Package CDIP32SW ST72101 ST72212 ST72213 mm bv a ec we a sse 576 sos 2 je sos ss 57 o 2oo30 185 fose oss aora oae noz Cr oe o2 40 eras ar se 2a as 0601100 120 ser ro rros oaoo ono oss 7 62 s oo oso ro pee Fe fore res T enm 5 Number mm ches Ras pL Bep pL pe mfo oss 25 55s ons pore oes Fer oss oce oss oss par poer oso vise 202 ew Fer sas ss rose os72 so oos iret Fer gt Fer Fe d 81 84 ST72101 ST72212 ST72213 7 3 ORDERING INFORMATION Each device is available for production in user pro grammable version OTP as well as in factory coded version ROM OTP devices are shipped to custom
80. rolled by the ADC registers switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input It is recommended not to change the voltage level or loading on any port pin while conversion is in progress Furthermore it is recommended not to have clocking pins located close to a selected an alog pin Warning The analog input voltage level must be within the limits stated in the Absolute Maximum Ratings ST72101 ST72212 ST72213 4 1 3 I O Port Implementation The hardware implementation on each I O port de pends on the settings in the DDR and OR registers and specific feature of the I O port such as ADC In put see Figure 20 or true open drain Switching these ports from one state to another should be done in a sequence that prevents unwanted side effects Recommended safe transitions are il lustrated in Figure 19 Other transitions are poten tially risky and should be avoided since they are likely to present unwanted side effects such as spurious interrupt generation Figure 19 Recommended I O State Transition Diagram INPUT INPUT no interrupt with interrupt OUTPUT push pull OUTPUT open drain 25 84 ST72101 ST72212 ST72213 PORTS Cont d Figure 20 Block Diagram ALTERNATE ENABLE ALTERNATE 1 Vpp OUTPUT P BUFFER SEE TaBLE BELOW ALTERNATE pi ENABLE CONDITION L SEE TABLE BELOW OR LATCH ANALOG ENABLE SEE TABL
81. s reset The firstedge on the SCK pin falling edge if CPOL bit is set rising edge if CPOL bit is reset is the MSBit capture strobe Data is latched on the oc currence of the second clock transition This pin must be toggled high and low between each byte transmitted see Figure 35 To protect the transmission from a write collision a low value on the SS pin of a slave device freezes the data in its DR register and does not allow it to be altered Therefore the SS pin must be high to write a new data byte in the DR without producing a write collision Slave SS Slave SS CPHA 1 VRO2131A 53 84 ST72101 ST72212 ST72213 SERIAL PERIPHERAL INTERFACE Cont d Figure 36 Data Clock Timing Diagram Note This figure should not be used as a replacement for parametric information Refer to the Electrical Characteristics chapter VR02131B 54 84 STA SERIAL PERIPHERAL INTERFACE Cont d 4 4 4 4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is tak ing place with an external device When this hap pens the transfer continues uninterrupted and the software write will be unsuccessful Write collisions can occur both in master and slave mode Note a read collision will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU oper ation In Slave mod
82. sful comparison occurs with the OC2R reg ister and is set in the CR2 register This val ue is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode Bit 1 IEDG1 nput Edge 1 This bit determines which type of level transition on the ICAP1 pin will trigger the capture 0 A falling edge triggers the capture 1 A rising edge triggers the capture Bit 0 OLVL1 Output Level 1 The OLVL1 bit is copied to the OCMP1 pin when ever a successful comparison occurs with the register and the OC1E bit is set in the CR2 register 16 BIT TIMER Cont d CONTROL REGISTER 2 CR2 Read Write Reset Value 0000 0000 00h 7 0 Bit 7 OC1E Output Compare 1 Pin Enable This bit is used only to output the signal from the timer on the OCMP1 pin OLV1 in Output Com pare mode both OLV1 and OLV2 in PWM and one pulse mode Whatever the value ofthe OC1E bit the Output Compare 1 function of the timer re mains active 0 OCMP1 pin alternate function disabled I O pin free for general purpose 1 0 1 OCMP1 pin alternate function enabled Bit 6 OC2E Output Compare 2 Enable This bit is used only to output the signal from the timer on the OCMP2 pin OLV2 in Output Com pare mode Whatever the value of the OC2E bit the Output Compare 2 function of the timer re mains active 0 2 pin alternate function disabled I O pin free for general purpose 1 0 1 OCMP2 pin alternate function enab
83. stance junction to ambient Pp Pur Pint X chip internal power Pport Port power dissipation determined by the user Supply Voltage 031060 Input Voltage Vss 0 3 to Vpp 0 3 Analog Input Voltage A D Converter Vss 0 3 to 0 3 vo Vo Output Voltage Vss 0 3 to Vpp 0 3 ota Coren uses i Note Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device atthese conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability 71 84 ST72101 ST72212 ST72213 6 2 RECOMMENDED OPERATING CONDITIONS 3 Suffix Version 40 125 fosc 16 MHz 1 amp 6 Suffix 3 5 5 5 Operating Supply Voltage fosc 8 MHz 30 55 V Vpp 3 0V 01 8 Note 1 A D operation and Oscillator start up are not guaranteed below 1MHz 1 Suffix Version Operating Temperature 6 Suffix Version 8 Figure 41 Maximum Operating Frequency fosc Versus Supply Voltage Vpp FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONALITY GUARANTEED IN THIS AREA fosc FUNCTIONALITY NOT GUARANTEED IN THIS AREA MHz FOR TEMPERATURE HIGHER THAN 85 C FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR 72 84 437 ST72101 ST72212 ST72213 6 3 DC ELECTRICAL CHAR
84. t interrupt with or without pull up Output mode only for PBO PB7 5 0 output open drain with P Buffer inactivated 1 output push pull Output mode only for PAO PA7 0 output open drain 1 reserved ST72101 ST72212 ST72213 PORTS Cont d Table 12 I O Port Register Map and Reset Values Address Register Hex Label PCDR pr 0000h BOOTE PCDDR DD7 DD6 DD5 DD4 DD3 DD2 DD1 DDO Reset Value 0 0 0 0 0 0 0 0 PCOR 07 O5 04 2 O1 0002h PBDR D7 D5 D4 D37 D2 D1 0004h 007 006 005 004 003 002 DD1 DDO Reset Value 0 0 0 0 0 0 0 0 PBOR O7 O5 O4 O3 02 O1 0006h PADR D7 D5 D4 D37 D2 D1 0008h Deer Ere pepe posee PADDR DD7 DD6 DD5 DD4 DD3 DD2 DD1 DDO Reset Value 0 0 0 0 0 0 0 0 PAOR 07 05 04 2 O1 000Ah 29 84 4 ST72101 ST72212 ST72213 4 2 WATCHDOG TIMER WDG 4 2 1 Introduction 4 2 2 Main Features The Watchdog timer is used to detect the occur m Programmable timer 64 increments of 12288 rence of a software fault usually generated by ex CPU cycles ternal interference or by unforeseen logical condi Programmable reset tions which causes the application program to abandon its normal sequence The Watchdog cir cuit generates an MCU reset on expiry of a pro grammed time period unless the program refresh es the counters contents before the T6 bit be comes cleared m Reset if watchdog activated after a HALT instruction o
85. te cycle and then shifted out serially to the MISO pin most significant bit first The transmit sequence begins when the slave de vice receives the clock signal and the most signifi cant bit of the data on its MOSI pin 52 84 When data transfer is complete The SPIF bit is set by hardware An interrupt is generated if SPIE bit is set and bitin CCR register is cleared During the last clock cycle the SPIF bit is set a copy of the data byte received in the shift register is moved to a buffer When the DR register is read the SPI peripheral returns this buffered value Clearing the SPIF bit is performed by the following software sequence 1 An access to the SR register while the SPIF bit is set 2 A write or a read of the DR register Notes While the SPIF bit is set all writes to the DR register are inhibited until the SR register is read The SPIF bit can be cleared during a second transmission however it must be cleared before the second SPIF bit in order to prevent an overrun condition see Section 4 4 4 6 Depending on the CPHA bit the SS pin has to be set to write to the DR register between each data byte transfer to avoid a write collision see Section 4 4 4 4 SERIAL PERIPHERAL INTERFACE Cont d 4 4 4 3 Data Transfer Format During an SPI transfer data is simultaneously transmitted shifted out serially and received shifted in serially The serial clock is used to syn chronize the data
86. ter ACLR is the least significant byte LSB These two read only 16 bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit overflow flag see note at the end of paragraph titled 16 bit read sequence Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value The timer clock depends on the clock control bits of the CR2 register as illustrated in Table 15 The value in the counter register repeats every 131 072 262 144 or 524 288 internal processor clock cycles depending on the CC1 and CCO bits ST72101 ST72212 ST72213 16 BIT TIMER Cont d Figure 22 Timer Block Diagram ST7 INTERNAL BUS MCU PERIPHERAL INTERFACE OUTPUT OUTPUT INPUT INPUT FREE RUNNING COMPARE COMPARE CAPTURE CAPTURE COUNTER REGISTER REGISTER REGISTER REGISTER 2 COUNTER ALTERNATE REGISTER CC1 CCO mo INTERNAL OVERFLOW DETECT UT COMPAR EDGE DETECT CIRCUIT1 EDGE DETECT CIRCUIT2 LATCH1 VV TIMER INTERRUPT 33 84 4 ST72101 ST72212 ST72213 16 BIT TIMER Contd 16 bit read sequence from either the Counter Register or the Alternate Counter Register LSB is buffered Beginning of the sequence Read MSB At t0 Other 1 instructions Returns the buffered At t0 At Read LSB LSB value at t0 Sequence completed The user must read the MSB first then
87. terrupt Vector External Interrupt FFFA FF FBh External Interrupt Vector EIO External Interrupt FFFC FFFDh TRAP software Interrupt Vector CPU Interrupt FFFE FFFFh RESET Vector 4 10 84 Table 5 Hardware Register Memory Address Plock Register Register name Reset Status Name Label 00h R W 00h R W 00h R W 000Bh to 001Fh Data Register Data Direction Register Option Register Reserved Area 1 Byte Data Register Data Direction Register Option Register Reserved Area 1 Byte Data Register Data Direction Register Option Register Reserved Area 21 Bytes ST72101 ST72212 ST72213 00h R W R W R W R W R W R W Data Register Control Register Status Register E Read Only 0024h WDG WDGCR Watchdog Control register BEC F 0025h to 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Timer A TACR2 1 TASR TAIC1HR TAIC1LR TAOC1HR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR Reserved Area 12 Bytes Control Register2 Control Register Status Register Input Capture1 High Register Input Capture1 Low Register Output Compare1 High Register Output Compare1 Low Register Counter High Register Counter Low Register Alternate Counter High Register Alternate Counter Low Register Input Capture2 High Register Input Capture2 Low Register Output Compare2 High Register Output Co
88. the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are re versed ST72101 ST72212 ST72213 Bit 3 CPOL Clock polarity This bit is set and cleared by software This bit de termines the steady state of the serial Clock The CPOL bit affects both the master and slave modes 0 The steady state is a low value at the SCK pin 1 The steady state is a high value at the SCK pin Bit 2 Clock phase This bit is set and cleared by software 0 The first clock transition is the first data capture edge 1 The second clock transition 15 the first capture edge Bit 1 0 SPR 1 0 Serial peripheral rate These bits are set and cleared by software Used with the SPR2 bit they select one of six baud rates to be used as the serial clock when the device is a master These 2 bits have no effect in slave mode Table 17 Serial Peripheral Baud Rate Serial Glock SPR2 ho 7111919 ewe opuso 59 84 ST72101 ST72212 ST72213 SERIAL PERIPHERAL INTERFACE Cont d STATUS REGISTER SR Read Only Reset Value 0000 0000 00h 7 0 Bit 7 SPIF Serial Peripheral data transfer flag This bit is set by hardware when a transfer has been completed An interrupt is generated if SPIE 1 in the CR register It is cleared by a soft ware sequence an access to the SR register fo
89. the LSB value is buffered automatically This buffered value remains unchanged until the 16 bit read sequence is completed even if the user reads the MSB several times After a complete reading sequence if only the CLR register or ACLR register are read they re turn the LSB of the count value at the time of the read Whatever the timer mode used input capture out put compare one pulse mode or PWM mode an overflow occurs when the counter rolls over from FFFFh to 0000h then The TOF bit of the SR register is set A timer interrupt is generated if TOIE bit of the CR1 register is set and bit of the CC register is cleared If one of these conditions is false the interrupt re mains pending to be issued as soon as they are both true 34 84 Clearing the overflow interrupt request is done in two steps 1 Reading the SR register while the TOF bit is set 2 An access read or write to the CLR register Notes The TOF bit is not cleared by accesses to ACLR register This feature allows simultaneous use of the overflow function and reads of the free running counter at random times for example to measure elapsed time without the risk of clearing the TOF bit erroneously The timer is not affected by WAIT mode In HALT mode the counter stops counting until the mode is exited Counting then resumes from the previous count MCU awakened by an interrupt or from the reset count MCU awakened by a Reset 4 3
90. tware Sequence Clearing sequence after SPIF z 1 end of a data byte transfer ist Step Read SR THEN 2nd Step Read DR WCOL 0 Read SR Write DR SPIF 0 WCOL 0 if no transfer has started WCOL 1 if a transfer has started before the 2nd step Clearing sequence before SPIF z 1 during a data byte transfer Read SR Read DR 1st Step 2nd Step THEN WCOL 0 Note Writing in DR register in stead of reading in it do not reset WCOL bit 55 84 ST72101 ST72212 ST72213 SERIAL PERIPHERAL INTERFACE Cont d 4 4 4 5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low then the bit is set Master mode fault affects the SPI peripheral in the following ways The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set The SPE bit is reset This blocks all output from the device and disables the SPI periph eral The MSTR bit is reset thus forcing the device into slave mode Clearing the bit is done through a software sequence 1 A read or write access to the SR register while the MODF bit is set 2 A write to the CR register Notes To avoid any multiple slave conflicts in the case of a system comprising several MCUs the SS pin must be pulled high during the clearing se quence of the MODF bit The SPE and MSTR bits 56 84 may be restored to their original state during or af ter this clearing sequence Hardware
91. ve addressing mode to an instruction using the corresponding indirect addressing mode It also changes an instruction using X indexed ad dressing mode to an instruction using indirect X in dexed addressing mode PIY 91 Replace an instruction using X in direct indexed addressing mode by a Y one ST72101 ST72212 ST72213 INSTRUCTION GROUPS Cont d Mnemo Description FunctonExample Dst Sre awna ND _ M Ei compare A Memoy wr My SES ECC _ ser arse retenes amp iras aise gn Bri samp risa weve uw _ ca sois CALLA Ca wbewme ae que ____ fen One Complement ___ _____ DEC War a RET memermunewum _ INC Increment inc X reg M Increment p reso ___ ___ CS Dumpretmeng i o Lm JRNH Jump if H 0 H 0 JRNH E umerr o mms Law samp tiesa z 13 mc o e arnes
92. viour accord ing to the selected input output configuration Writ ing the DR register is always taken in account even if the pin is configured as an input Reading the DR register returns either the DR register latch content pin configured as output or the digital val ue applied to the I O pin pin configured as input 4 1 4 2 Data direction registers Port A Data Direction Register PADDR Port B Data Direction Register PBDDR Port C Data Direction Register PCDDR Read Write Reset Value 0000 0000 00h input mode 7 0 oor oos one Bit 7 0 DD7 DDO Data Direction Register 8 bits The DDR register gives the input output direction configuration of the pins Each bit is set and cleared by software 0 Input mode 1 Output mode 28 84 4 1 4 3 Option registers Port A Option Register PAOR Port B Option Register PBOR Port C Option Register PCOR Read Write Reset Value 0000 0000 00h no interrupt 7 0 Bit 7 0 07 00 Option Register 8 bits For specific I O pins this register is not implement ed In this case the DDR register is enough to se lect the I O pin configuration The OR register allow to distinguish in input mode if the interrupt capability or the floating configura tion is selected in output mode if the push pull or open drain configuration is selected Each bit is set and cleared by software Input mode 0 floating input 1 inpu

Download Pdf Manuals

Related Search

ST ST72101/ST72212/ST72213 handbook

ST ST72101/ST72212/ST72213 handbook

Contents

Download Pdf Manuals

Related Search

Related Contents