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ST ST72334J/N ST72314J/N ST72124J 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY ADC 16-BIT TIMERS SPI SCI INTERFACES handbook(1)

1. 16 2 5 PROGRAM MEMORY READ OUT PROTECTION 16 2 6 EEPROM 224 ede war ade o D 17 2 6 11 Introduction 17 26 2 Features sci cca rox eek denne eae eee 17 26 3 Memory ACCESS 22 222 442 o b een 18 2 6 4 Data EEPROM and Power Saving Modes 19 2 6 5 Data EEPROM Access Error Handling 19 2 6 6 Register Description 0 2 0 nes 20 3 CENTRAL PROCESSING UNIT 21 3 1 INTRODUCTION ates au kpc aon ee ace ewan teu ole eagle 21 3 2 MAIN FEATURES Rem aues muda RS ERE 21 3 3 CPU REGISTERS dicet p act ades men RR 21 4 SUPPLY RESET AND CLOCK MANAGEMENT 24 4 1 LOW VOLTAGE DETECTOR 25 4 2 RESET SEQUENCE MANAGER RSM 26 4 3 CLOCK SECURITY SYSTEM 5865 24 32 4 3 1 Clock Filter 4 4 32 4 3 2 Safe Oscillator 32 4 4 SUPPLY RESET AND CLOCK REGISTER DESCRIPTION
2. tHe Beep signal 50 duty cycle The beep output signal is available in ACTIVE HALT mode but has to be disabled to reduce the consumption Bit 3 2 Reserved Must always be cleared Bit 1 SSM SS mode selection It is set and cleared by software 0 Normal_mode 55 uses information coming from the SS pin of the SPI 1 mode the SPI uses the information stored into bit SSI Bit 0 SSI SS internal mode This bit replaces pin SS of the SPI when bit SSM is set to 1 see SPI description Itis set and cleared by software Table 11 Miscellaneous Register Map and Reset Values Address Register 7 Hex Label MISCR1 1511 510 MCO 1521 0 ST72334J N ST72314J N ST72124J IS20 CP1 0 0 0 MISCR2 BC1 BCO SSM 0 49 125 ST72334J N ST72314J N ST72124J 6 3 WATCHDOG TIMER WDG 6 3 1 Introduction The Watchdog timer is used to detect the occur rence of a software fault usually generated by ex ternal interference or by unforeseen logical condi tions which causes the application program to abandon its normal sequence The Watchdog cir cuit generates an MCU reset on expiry of a pro grammed time period unless the program refresh es the counters contents before the bit be comes cleared 6 3 2 Main Features m Programmable timer 64 increments of 12288 CPU cycles m Programmable reset m Heset if watchdog activated after a HALT inst
3. x x Pon Timers Compare 1 2 uo os RS x X Pon ca Timer input Capture 2 ___ ro er ns x x PX rares mec pa Canine 1 Se irr Save Ot ro or X x Port 05 Se Master Out Save m Dar x x o cr X X Pon SP Slave Select 0m x A L m xp 8 L me TX 3 ES _ Lear wai Supp Vote SS opere 3 spes vo forms Rp Pe x oe 3 te E ronan Must be tied low in user mode In pro 1 38 31 ISPSEL gramming mode when available this pin acts as In Situ Programming mode se lection 9 32 RESE X Top priority non maskable interrupt ac tive low NC TE 23 TUE UN E RR These pins connect parallel resonant crystal or an external clock source to the exe on chip oscilator fobs C Co i retos pop x sea t ral js reor screen Dain
4. 33 4 5 MAIN CLOCK CONTROLLER 34 5 INTERRUPTS amp POWER SAVING MODES 36 5 1 INTERRUPTS dda ene oa eel Ghee eho hw ee eae a 36 5 2 POWER SAVING MODES veda 38 5 21 TATOGUCHON 38 5 2 2 HALT Modes ass 38 5 2 3 WAIT MOJE ute ots pote oed Ro Res 40 5 24 SLOW irt eee PUR Ut Baa Eon a ee 41 6 ON CHIP PERIPHERALS a a a d 42 6 1 VO PORTS e ERE doe gee UP AR AA a 42 6 11 ean RUE Run baa ade 42 6 1 2 Functional Description 24 4 9 42 6 1 3 I O Port Implementation 2 44 6 1 4 Register Description eee ake ERU e RR E RH ERR NUR es 45 6 2 MISCELLANEOUS REGISTERS 1 47 6 2 1 Port Interrupt Sensitivity Description 47 2 125 5 Table of Contents 6 2 2 I O Port Alternate 1 47 6 2 3 Miscellaneous Registers Description 48 6 9 WATCHDOG TIMER
5. _ oss 076 pore oozs ooo ru Number of Pins aes N o ND 16 ne 16 Figure 68 56 Pin Shrink Plastic Dual In Line Package 600 mil Width mm mes Dim a wae i rat feast mfo pos rwr Pe fox 005 209 ret e p pep we ex pes ose p pL pep 524 2 res 50867 o2 117 125 ST72334J N ST72314J N ST72124J PACKAGES Cont d Figure 69 44 Pin Thin Quad Flat Package m ___ TES L pes Far oos os 5002 poss rao 14s oos nass oos oso poiz nore ors Pe e oos pe poo fossa feo Pe fool frooof T res Pe oso po a oss oso 075 Rp ep poe ue pos osos E sm a reo ro rae o so seo o s7o LEAD DETAIL pp pem L pes T psp L qe sep 254 o oo130 o 146 paeem ELE 425 E 3 118 125 ST72334J N ST72314J N 57721247 PACKAGES 9 1 2 User supplied TQFP64 Adaptor Socket m Direct TQFP64 soldering To solder the TQFP64 device directly on the appli YAMAICHI 1C149 064 008 S5
6. en 96 6 6 Register Description sr eee bes ad 97 INSTRUCTION 5252 Rem Pew oo de ere 99 7 1 lt 517 ADDRESSING MODES 99 xe cn ata Aa ge 100 FS EAD medale EI ee eee 100 JAMBES 100 7 1 4 Indexed No Offset Short Long 100 7 1 5 Indirect Short Long 100 7 1 6 Indirect Indexed Short Long 101 437 3 125 Table of Contents 7 1 7 Relative mode Direct Indirect 101 7 2 INSTRUCTION GROUPS 2 5 na x Rep ER a Ex Rare p nte EROR De dca a 102 8 ELECTRICAL CHARACTERISTICS 105 8 1 ABSOLUTE MAXIMUM RATINGS 105 8 2 RECOMMENDED OPERATING CONDITIONS 106 8 3 DC ELECTRICAL CHARACTERISTICS 107 8 4 GENERAL TIMING CHARACTERISTICS 107 8 5 108 8 6 SUPPLY RESET AND CLOCK CHARACTERISTICS 109 8 6 1 Su
7. rhe tes dd x rok RA 50 6 3 1 Introduction a LEE leds 50 6 3 2 Maini Fealt les 50 6 3 3 Functional Description 50 6 3 4 Hardware Watchdog 51 6 3 5 Low Power Modos Gave Re EE oe eee 51 6 3 6 Interr pts des a SRR es ere aaa ee aie ans 51 6 3 7 Register 51 6 4 AGEBIT TIMER ette aret ti bai ace rar der e oh ae 53 6 4 Introd clion xb RE UD dede Bou e bate aas I a 53 6 4 2 Main Features 2 225 22 222 442122 aed pa AEN aid 53 6 4 3 Functional Description 1 2 53 6 4 4 Low Power Modes 64 6 4 5 Interrupts issues bre RE 64 6 4 6 Register 65 6 5 SERIAL PERIPHERAL INTERFACE SPI 70 6 5 14 Introduction wee Obata REI Dedede ERROR ened Owed ea wae 70 6 5 2 Features sea dean dad kd 70 6 5 3 General descriptio
8. PD4 5 PD5 Vssa MCO PFO BEEP PF1 PF2 OCMP1 A PF4 ICAP1 A HS PF6 EXTCLK A HS 2 OCMP1 B PC1 2 HS PC2 ICAP1_B HS ISPDATA MISO PC4 MOSI PC5 ISPSEL 1_ 4 HS PFe O ICAP1 A Vss 1 Vpp 1 7 55 PC6 ISPCLK PC5 MOSI PC4 MISO ISPDATA HS ICAP1 B 2 HS 2 B PC1 OCMP1 B OCMP2 B PB3 PB2 PB1 PBO PE1 RDI PEO TDO Vpp_2 OSC 1 OSC2 Weg 2 RESET ISPSEL PA7 HS PA6 HS PAS HS 4 HS Vss 1 1 7 55 PC6 ISPCLK 9 125 ST72334J N ST72314J N ST72124J PIN DESCRIPTION Legend Abbreviations Type input output S supply Input level A Dedicated analog input In Output level C CMOS 0 3Vpp 0 7Vpp CMOS 0 3Vpp 0 7Vpp with input trigger Output level high sink on N buffer only Port configuration capabilities Input float floating wpu weak pull up int interrupt ana analog Output OD open drain T true open drain PP push pull Note the Reset configuration of each pin is shown in bold Table 1 Device Pin Description Level Main ial after Alternate function de ere pee ________ Hes pps e eres tojep
9. _____ Not Connected ae 64 NIT 314 ial iB 11 125 ST72334J N ST72314J N ST72124J 2 3 REGISTER amp MEMORY MAP As shown in the Figure 5 the MCU is capable of 8 Kbytes of user program memory The RAM addressing 64K bytes of memories and regis space includes up to 256 bytes for the stack from ters 0100h to 01FFh The available memory locations consist of 128 The highest address bytes contain the user reset bytes of register locations 384 or 512 bytes of and interrupt vectors RAM up to 256 bytes of data EEPROM and 4 or Figure 5 Memory Map HW Registers Short Addressing see Table 2 RAM zero page 256 Bytes Stack or J MAM 16 bit Addressing RAM 20080 Short Addressing ooFFh RAM zero 256 Bytes Data EEPROM 16 bit Addressing RAM 16K Bytes 8K Bytes Program x 16 bit Addressing Program Memory RAM 027Fh Memory Interrupt amp Reset Vectors see Table 6 page 37 4 12 125 ST72334J N ST72314J N ST72124J REGISTER amp MEMORY MAP Cont d Table 2 Hardware Register Map Register Reset Port A Data Register 00h R W Port A Data Direction Register 00h R W Port A Option Register 00h R W 1 Reserved Area 1 Byte Port C Data Register 00h R W Port C Data Direction Register 00h R W Port C Option Register 00h R W Reserved Area 1 Byte Port B Data Register 00h R W Port B Data Direction Register 00h
10. Main clock out selection This bit enables the MCO alternate function on the I O port It is set and cleared by software 0 MCO alternate function disabled pin free for general purpose 1 MCO alternate function enabled fosc 2 on I O port Note To reduce power consumption the MCO function is not active in ACTIVE HALT mode 48 125 Bit 4 3 IS2 1 0 0 and sensitivity The interrupt sensitivity defined using the IS2 1 0 bits is applied to the following external interrupts EIO port A3 0 and port F2 0 These 2 bits can be written only when the bit of the CC register is setto 1 interrupt disabled Bit 2 1 CP 1 0 CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes Their action is conditioned by the setting of the SMS bit These two bits are set and cleared by software 3 ofen foseri Bit 0 SMS S ow mode select This bit is set and cleared by software 0 Normal mode fosc 2 1 Slow mode fcpy is given by CP1 See low power consumption mode and MCC chapters for more details 3 MISCELLANEOUS REGISTERS Cont d MISCELLANEOUS REGISTER 2 MISCR2 Read Write Reset Value 0000 0000 00h 7 0 Bit 7 6 Reserved Must always be cleared Bit 5 4 BC 1 0 Beep control These 2 bits select the PF1 pin beep capability
11. Value 5 Where t Desired output compare period in sec onds Internal clock frequency Timer prescaler factor 2 4 or 8 de pending on CC1 CCO bits see Table 14 Clock Control Bits ST72334J N ST72314J N ST72124J The Output Compare 2 event causes the counter to be initialized to FFFCh See Figure 45 Pulse Width Modulation cycle OCMP1 OLVL1 OLVL2 Counter is reset to FFFCh ICF1 bit is set Notes 1 After a write instruction to the OC HR register the output compare function is inhibited until the OCILR register is also written Therefore the Input Capture 1 function is inhib ited but the Input Capture 2 is available 2 The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited 3 The ICF1 bitis set by hardware when the coun ter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared 4 PWM mode the ICAP1 pin can not be used to perform input capture because it is discon nected to the timer The ICAP2 pin can be used to perform input capture ICF2 can be set and IC2R can be loaded but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set 5 When the Pulse Width Modulation PWM and One Pulse Mode OPM bits are both set the PWM mode is the only active one 63
12. 57721242100 IST ST72334J N 77 ST72314J N 5772124 8 MCU WITH SINGLE VOLTAGE FLASH MEMORY ADC 16 BIT TIMERS SPI SCI INTERFACES PRODUCT PREVIEW m or 16K Program memory ROM or Single voltage FLASH with read out protection 256 bytes EEPROM Data memory In Situ Programming Remote ISP Enhanced Reset System Low voltage supply supervisor with 3 programmable levels m Low consumption resonator or RC oscillators and by pass for external clock source with safe control capabilities m 4 Power saving modes m Standard Interrupt Controller m 44 or 32 multifunctional bidirectional lines External interrupt capability 4 vectors 21 or 19 alternate function lines 12 8 high sink outputs TOFP64 44 Real time base Beep Clock out capabilities 14x14 10 10 Configurable watchdog reset Two 16 bit timers with 2 input captures only one on timer A 2 output compares only one on timer A External clock input on timer A PWM and Pulse generator modes m SPI synchronous serial interface m 5 asynchronous serial interface m 8 bit ADC with 8 input pins 6 only on ST72334Jx not available on ST72124J2 8 bit data manipulation 63 basic instructions 17 main addressing modes 8 x 8 unsigned multiply instruction True bit manipulation m Full hardware software development package Device Summary ST72124J2 ST72314J2 ST72314J4 ST72314N2 ST72314N4 ST72334J2 51723
13. 2 dedicated status flags 1 dedicated maskable interrupt m Pulse width modulation mode PWM m One pulse mode m 5 alternate functions on ports ICAP1 ICAP2 1 2 EXTCLK Block Diagram is shown Figure 35 Note Some external pins are not available on all devices Refer to the device pin out description When reading an input signal which is not availa ble on an external pin the value will always be 1 ST72334J N ST72314J N ST72124J 6 4 3 Functional Description 6 4 3 1 Counter The principal block of the Programmable Timer is a 16 bit free running increasing counter and its as sociated 16 bit registers Counter Registers Counter High Register CHR is the most sig nificant byte MSB Counter Low Register CLR is the least sig nificant byte LSB Alternate Counter Registers Alternate Counter High Register ACHR is the most significant byte MSB Alternate Counter Low Register ACLR is the least significant byte LSB These two read only 16 bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit overflow flag see note at the end of paragraph titled 16 bit read sequence Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value The timer clock depends on the clock control bits of the CR2 register as illustrated in Table 14 Clock Control
14. At least four falling edges of the CPU clock must occur between two consecutive active edges of the external clock thus the external clock frequen cy must be less than a quarter of the CPU clock frequency 55 125 ST72334J N ST72314J N ST72124J 16 BIT TIMER Cont d Figure 36 Counter Timing Diagram internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF Figure 37 Counter Timing Diagram internal clock divided by 4 INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF 56 125 3 16 6 4 3 3 Input Capture In this section the index may be 1 or 2 The two input capture 16 bit registers IC1R and IC2R are used to latch the value of the free run ning counter after a transition detected by the ICAP i see figure 5 MS Byte LS Byte ICiR ICi register is a read only register The active transition is software programmable through the IEDGibit of the Control Register Timing resolution is one count of the free running counter fcpy CC1 CCO0 Procedure To use the input capture function select the follow ing in the CR2 register Select the timer clock CC1 CCO see Table 14 Clock Control Bits Select the edge of the active transition on the ICAP2 pin with the IEDG2
15. Crystal Ceramic Oscillators This family of oscillators has the advantage of pro ducing a high accuracy on the main clock of the ST7 The selection within a list of 4 oscillators with different frequency ranges has to be done by OP TION BYTE in order to reduce the consumption In this mode of the MO block the resonator and the load capacitances have to be connected as shown in Figure 20 and have to be mounted as close as possible to the oscillator pins in order to minimize output distortion and start up stabilization time The loading capacitance values must be adjusted according to the selected oscillator These oscillators when selected via the OPTION BYTE are not stopped during the RESET phase to avoid losing time in the oscillator start up phase Figure 20 MO Crystal Ceramic Resonator ST7 OSC1 OSC2 Cio LOAD CAPACITANCES 3 MULTI OSCILLATOR External RC Oscillator This oscillator allows a low cost solution for the main clock of the ST7 using only an external resis tor and an external capacitor see Figure 21 The selection of the external RC oscillator has to be done by OPTION BYTE The frequency of the external RC oscillator in the range of some MHz is fixed by the resistor and the capacitor values 1 OSC Cex The previous formula shows that in this MO mode the accuracy of the clock is directly linked to the accuracy of the discrete co
16. PRESC Timer prescaler factor 2 4 or 8 de pending on CC1 CCO bits see Table 14 Clock Control Bits Clearing the output compare interrupt request is done by 1 Reading the SR register while the OCFi bit is set 2 An access read or write to the register The following procedure is recommended to pre vent the OCFi bit from being set between the time it is read and the write to the register Write to the OC HR register further compares are inhibited Read the SR register first step of the clearance of the OCFi bit which may be already set Write to the register enables the output compare function and clears the OCFi bit Notes 1 After a processor write cycle to the OC HR reg ister the output compare function is inhibited until the register is also written 2 the bit is not set the pin is a general I O port and the bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set 3 When the clock is divided by 2 OCFi are set while the counter value equals the register value see Figure 42 This behaviour is the same in OPM or PWM mode When the clock is divided by 4 8 or in external clock mode OCFi and OCMP i set while the counter value equals the register value plus 1 see Figure 43 4 The output compare functions can be used both for generat
17. SERIAL PERIPHERAL INTERFACE STATUS REGISTER SR Read Only Reset Value 0000 0000 00h 7 0 Bit 7 SPIF Serial Peripheral data transfer flag This bit is set by hardware when a transfer has been completed An interrupt is generated if SPIE 1 in the CR register It is cleared by a soft ware sequence an access to the SR register fol lowed by a read or write to the DR register 0 Data transfer is in progress or has been ap proved by a clearing sequence 1 Data transfer between the device and an exter nal device has been completed Note While the SPIF bit is set all writes to the DR register are inhibited Bit 6 WCOL Write Collision status This bit is set by hardware when a write to the DR register is done during a transmit sequence It is cleared by a software sequence see Figure 50 0 No write collision occurred 1 A write collision has been detected Bit 5 Unused Bit 4 MODF Mode Fault flag This bit is set by hardware when the SS pin is pulled low in master mode see Section 6 5 4 5 Master Mode Fault An SPI interrupt can be gen erated if SPIE 1 in the CR register This bit is cleared by a software sequence An access to the SR register while MODF 1 followed by a write to the CR register 0 No master mode fault detected 1 A fault in master mode has been detected Bits 3 0 Unused ST72334J N ST72314J N ST72124J DATA REGISTER DR Read Write Reset V
18. __ INC Increment inc X reg M FING Increment CS pumemawe was DRE Lm JRNH Jump if H 0 0 JRNH H 07 umerr o pmerw ogus z 13 mc _ LmugE mpic o wmprG e S 437 103 125 ST72334J N ST72314J N ST72124J INSTRUCTION GROUPS LLIIHNE NN EAE 8 mur es wos m d Pop from the Stack pop reg pop CC EE m mer romernes oom _ _ mo ___ s oom mu Ec oo _ sen ETE a CC wwe 2 722 Wwe wwe Summe wer L LIS 104 125 ST72334J N ST72314J N ST72124J 8 ELECTRICAL CHARACTERISTICS 8 1 ABSOLUTE MAXIMUM RATINGS This product conta
19. out put compare one pulse mode or PWM mode an overflow occurs when the counter rolls over from FFFFh to 0000h then The TOF bit of the SR register is set A timer interrupt is generated if TOIE bit of the CR1 register is set and bit of the CC register is cleared If one of these conditions is false the interrupt re mains pending to be issued as soon as they are both true ST72334J N ST72314J N ST72124J Clearing the overflow interrupt request is done in two steps 1 Reading the SR register while the TOF bit is set 2 An access read or write to the CLR register Notes The TOF bit is not cleared by accesses to ACLR register This feature allows simultaneous use of the overflow function and reads of the free running counter at random times for example to measure elapsed time without the risk of clearing the TOF bit erroneously The timer is not affected by WAIT mode In HALT mode the counter stops counting until the mode is exited Counting then resumes from the previous count MCU awakened by an interrupt or from the reset count MCU awakened by a Reset 6 4 3 2 External Clock The external clock where available is selected if 1 and CC1 1 in CR2 register The status of the EXEDG bit determines the type of level transition on the external clock pin EXT CLK that will trigger the free running counter The counter is synchronised with the falling edge of the internal CPU clock
20. peripheral When the signal is going to an on chip peripheral the I O pin has to be configured in input mode In this case the pin s state is also digitally readable by addressing the DR register Note Input pull up configuration can cause unex pected value at the input of the alternate peripheral input When an on chip peripheral use a pin as in put and output this pin has to be configured in in put floating mode WARNING The alternate function must not be ac tivated as long as the pin is configured as input with interrupt in order to avoid generating spurious interrupts r ST72334J N ST72314J N 57721247 PORTS Cont d Figure 32 Block Diagram ALTERNATE OUTPUT P BUFFER see table below ALTERNATE ENABLE PULL UP see table below PULL UP CONDITION gt gt 0 N BUFFER DIODES see table below ANALOG CMOS INPUT SCHMITT TRIGGER ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE Elx POLARITY SELECTION Table 8 Port Mode Options Diodes Configuration Mode Diodes to Vpp to Vss Floating with without Interrupt Input Pull up with without Interrupt Pushpa Output Open Drain logic level Legend NI not implemented Note the diode to Vpp is not implemented in the Off implemented not activated true open drain pads A local protection between On implemented and activated the pad and Vas is implemented
21. socket cation board or to solder a socket for connecting soldering to plug either the emulator probe or an the emulator probe the application board should adaptor board with TQFP64 clamshell provide the footprint described in Figure 71 This socket footprint allows both configurations Not compatible with TQFP64 package Figure 71 64 Device And Emulator Probe Compatible Footprint em ponoru re C EI Number of Pins EN 64 4x16 0000 SK Plastic socket overall dimensions Table 22 Suggested List of TQFP64 Socket Types Package Probe Adaptor Socket Reference Socket type ENPLAS OTQ 64 0 8 02 Open Top TQFP64 YAMAICHI 51 0644 1240 5 14584 Clamshell EMU PROBE YAMAICHI 1 149 064 008 55 r 119 125 ST72334J N ST72314J N ST72124J PACKAGES 9 1 3 User supplied TQFP44 Adaptor Socket m Direct TQFP44 soldering To solder the 44 device directly on the appli YAMAICHI 1 149 044 52 5 socket soldering cation board or to solder a socket for connecting to plug either the emulator probe or an adaptor the emulator probe the application board should board with an TQFP44 clamshell socket provide the footprint described in Figure 72 This footprint allows both configurations Figure 72 44 Device And Emulator Probe Compatible Footprint m Ee esee em
22. 125 ST72334J N ST72314J N ST72124J 16 BIT TIMER Cont d 6 4 4 Low Power Modes Description WAIT No effect on 16 bit Timer Timer interrupts cause the device to exit from WAIT mode If an input capture event occurs on the ICAP pin the input capture detection circuitry is armed Consequent ly when the MCU is woken up by an interrupt with exit from HALT mode capability the ICF bit is set and the counter value present when exiting from HALT mode is captured into the IC R register 16 bit Timer registers are frozen In HALT mode the counter stops counting until Halt mode is exited Counting resumes from the previous count when the MCU is woken up by an interrupt with exit from HALT mode capability or from the counter HALT reset value when the MCU is woken up by a RESET 6 4 5 Interrupts Interrupt Event Input Capture 1 event Counter reset in PWM mode ICF1 Input Capture 2 event ICF2 Output Compare 1 event not available in PWM mode OCF1 OCIE Output Compare 2 event not available in PWM mode OCF2 Yes ves Note The 16 bit Timer interrupt events connected to the same interrupt vector see Interrupts chap ter These events generate an interrupt if the corresponding Enable Control Bit is set and the I bit in the CC register is reset RIM instruction 4 64 125 16 BIT TIMER Cont d 6 4 6 Register Description Each Timer is asso
23. 2 OC2R contain the value to be compared to the free run ning counter each timer clock cycle MS Byte LS Byte OCiHR These registers are readable and writable and not affected by the timer hardware A reset event changes the value to 8000h Timing resolution is one count of the free running counter fcpu CC1 CC0 Procedure To use the output compare function select the fol lowing in the CR2 register Set the bit if an output is needed then the OCMPi pin is dedicated to the output compare function Select the timer clock 1 see Table 14 Clock Control Bits And select the following in the CR1 register Select the OLVL ibit to applied to the OCMP pins after the match occurs Set the OCIE bit to generate an interrupt if it is needed When a match is found OCFi bit is set The pin takes OLVL bit value OCMP pin latch is forced low during reset and stays low until valid compares change it to a high level A timer interrupt is generated if the OCIE bit is set in the CR2 register and the bit is cleared in the CC register CC The register value required for a specific tim ing application can be calculated using the follow ing formula OCiR r ST72334J N ST72314J N ST72124J At f lt u PRESC Where At Desired output compare period in sec onds fcpu Internal clock frequency
24. 4 4 Conventional Baud Rate Generation The baud rate for the receiver and transmitter Rx and Tx are set independently and calculated as follows _ fopu Rx 82 PR TR 82 PR RR with PR 1 3 4 13 see SCPO amp 5 1 bits TR 1 2 4 8 16 32 64 128 see SCTO SCT1 amp 5 2 bits RR 1 2 4 8 16 32 64 128 see SCRO SCR1 amp SCR2 bits All this bits are in the BRR register Example If is 8 MHz normal mode and if PR 13 and TR RR 1 the transmit and receive baud rates are 19200 baud Note the baud rate registers MUST NOT be changed while the transmitter or the receiver is en abled 6 6 4 5 Extended Baud Rate Generation The extended prescaler option gives a very fine tuning onthe baud rate using a 255 value prescal er whereas the conventional Baud Rate Genera tor retains industry standard software compatibili ly The extended baud rate generator block diagram is described in the Figure 54 The output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the ERPR or the ETPR register Note the extended prescaler is activated by set ting the ETPR or ERPR register to a value other than zero The baud rates are calculated as fol lows fopu cPU 16 ERPR 16 ETPR with ETPR 1 255 see ETPR register ERPR 1 255 see ERPR register 6
25. 6 4 6 Receiver Muting and Wake up Feature In multiprocessor configurations it is often desira ble that only the intended message recipient should actively receive the full message contents thus reducing redundant SCI service overhead for all non addressed receivers The non addressed devices may be placed in sleep mode by means of the muting function Setting the RWU bit by software puts the SCI in sleep mode All the reception status bits can not be set All the receive interrupt are inhibited A muted receiver may be awakened by one of the following two ways by Idle Line detection if the WAKE bit is reset by Address Mark detection if the WAKE bit is set Receiver wakes up by Idle Line detection when the Receive line has recognised an Idle Frame Then the RWU bit is reset by hardware but the IDLE bit is not set Receiver wakes up by Address Mark detection when it received 1 as the most significant bit of a word thus indicating that the message is an ad dress The reception of this particular word wakes up the receiver resets the RWU bit and sets the RDREF bit which allows the receiver to receive this word normally and to use it as an address word 89 125 ST72334J N ST72314J N ST72124J SERIAL COMMUNICATIONS INTERFACE Cont d 6 6 5 Low Power Modes Mode Description WAIT No effect on SCI SCI interrupts cause the device to exit from Wait mode HAUT SCI registers are frozen
26. Bits The value in the counter register re peats every 131 072 262 144 or 524 288 internal processorclock cycles depending on the CC1 and CCO bits 53 125 ST72334J N ST72314J N ST72124J 16 BIT TIMER Cont d Figure 35 Timer Block Diagram ST7 INTERNAL BUS MCU PERIPHERAL INTERFACE 8 bit buffer 16 BIT OUTPUT OUTPUT INPUT INPUT FREE RUNNING COMPARE COMPARE CAPTURE CAPTURE COUNTER REGISTER REGISTER REGISTER REGISTER 2 COUNTER ALTERNATE REGISTER CC1 CCO mo INTERNAL OVERFLOW UT COMPAR EDGE DETECT PETAT CIRCUIT1 CIRCUIT Lil EDGE DETECT CIRCUIT2 m LATCH jv Puppe n TIMER INTERRUPT 54 125 3 16 BIT TIMER Cont d 16 bit read sequence from either the Counter Register or the Alternate Counter Register LSB is buffered Beginning of the sequence Read MSB At t0 Other L instructions Returns the buffered At t0 At Read LSB LSB value at t0 Sequence completed The user must read the MSB first then the LSB value is buffered automatically This buffered value remains unchanged until the 16 bit read sequence is completed even if the user reads the MSB several times After a complete reading sequence if only the CLR register or ACLR register are read they re turn the LSB of the count value at the time of the read Whatever the timer mode used input capture
27. Break Characters Setting the SBK bit loads the shift register with a break character The break frame length depends on the M bit see Figure 53 As long as the SBK bit is set the SCI send break frames to the TDO pin After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame Idle Characters Setting the TE bit drives the SCI to send an idle frame before the first data frame Clearing and then setting the TE bit during a trans mission sends an idle frame after the current word Note Resetting and setting the TE bit causes the data in the TDR register to be lost Therefore the best time to toggle the TE bit is when the TDRE bit is set i e before writing the next byte in the DR 4 SERIAL COMMUNICATIONS INTERFACE Cont d 6 6 4 3 Receiver The SCI can receive data words of either 8 or 9 bits When the M bit is set word length is 9 bits and the MSB is stored in the R8 bit in the CR1 reg ister Character reception During SCI reception data shifts in least signifi cant bit first through the RDI pin In this mode DR register consists in a buffer RDR between the in ternal bus and the received shift register see Fig ure 52 Procedure Select the M bit to define the word length Selectthe desired baud rate using the BRR and the ERPR registers Set the RE bit this enables the receiver which b
28. CR1 ps Timer B 42 Reset Value Timer A 31 CR2 i Timer B 41 Reset Value Timer A 33 ICF1 Timer B 43 Reset Value Timer A 34 ICHR1 Timer B 44 Reset Value Timer 35 ICLR1 Timer B 45 Reset Value Timer A 36 OCHR1 Timer B 46 Reset Value Timer A 37 OCLR1 Timer 47 Reset Value Timer OCHR2 Timer B 4 Reset Value Timer A OCLR2 Timer B 4F Reset Value Timer A 38 CHR Timer B 48 Reset Value Timer A 39 CLR Timer B 49 Reset Value Timer A ACHR Timer 4 Reset Value Timer A 3B ACLR M Timer B 4 Reset Value Timer A 3C ICHR2 Timer B 40 Reset Value Timer A 3D ICLR2 Timer B 4D Reset Value OCIE 0 OC2E 0 OCF1 15 i 69 125 ST72334J N ST72314J N ST72124J 6 5 SERIAL PERIPHERAL INTERFACE SPI 6 5 1 Introduction The Serial Peripheral Interface SPI allows full duplex synchronous serial communication with external devices An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves The SPI is normally used for communication be tween the microcontroller and external peripherals or another microcontroller Refer to the Pin Description chapter for the device specific pin out 6 5 2 Main Features m Full duplex three wire synchronous transfers Master or slave operation Four master mode frequencies Maximum slave mode frequency fCP
29. In Halt mode the SCI stops transmitting receiving until Halt mode is exited 6 6 6 Interrupts Enable Interrupt Event Control Bit Transmit Data Register Empty TDRE Transmission Complete TCIE i RDRF Y N Received Data Ready to be Read RDRF RIE Overrrun Error Detected OR Idle Line Detected IDLE ILIE The SCI interrupt events are connected to the These events generate an interrupt if the corre same interrupt vector see Interrupts chapter sponding Enable Control Bit is set and the I bit in the CC register is reset RIM instruction 3 90 125 SERIAL COMMUNICATIONS INTERFACE Cont d 6 6 7 Register Description STATUS REGISTER SR Read Only Reset Value 1100 0000 COh 7 0 Bit 7 Transmit data register empty This bit is set by hardware when the content of the TDR register has been transferred into the shift register An interrupt is generated if the TIE 1 in the CR2 register It is cleared by a software se quence an access to the SR register followed by a write to the DR register 0 Data is not transferred to the shift register 1 Data is transferred to the shift register Note data will not be transferred to the shift regis ter as long as the TDRE bit is not reset Bit 6 TC Transmission complete This bit is set by hardware when transmission of a frame containing Data a Preamble or a Break is complete An interrupt is generated if TCIE 1 in the CR2 register It is cleared by a softw
30. OCMP2 pin alternate function enabled Bit 5 OPM One Pulse Mode 0 One Pulse Mode is not active 1 One Pulse Mode is active the ICAP1 pin can be used totrigger one pulse on the OCMP 1 pin the active transition is given by the IEDG1 bit The length of the generated pulse depends on the contents of the register 66 125 Bit 4 PWM Pulse Width Modulation 0 PWM mode is not active 1 PWM mode is active the OCMP1 pin outputs a programmable cyclic signal the length of the pulse depends on the value of OC1R register the period depends on the value of OC2R regis ter Bit 2 CC1 CCO Clock Control The value of the timer clock depends on these bits Table 14 Clock Control Bits External Clock where available Bit 1 IEDG2 Input Edge 2 This bit determines which type of level transition on the ICAP2 pin will trigger the capture 0 A falling edge triggers the capture 1 A rising edge triggers the capture Bit 0 EXEDG External Clock Edge This bit determines which type of level transition on the external clock pin EXTCLK will trigger the free running counter 0 A falling edge triggers the free running counter 1 A rising edge triggers the free running counter 3 16 BIT TIMER STATUS REGISTER SR Read Only Reset Value 0000 0000 00h The three least significant bits are not used 7 0 fen ene oe eT oT Bit 7 ICF1 Input Capture Flag 1 0 No input capture reset
31. Vi yp rising edge or Vop lt V falling edge as shown in Figure 9 EXTERNAL RESET SOURCE RESET PIN WATCHDOG RESET WATCHDOG RESET 3 ST72334J N ST72314J N ST72124J RESET SEQUENCE MANAGER Cont d Internal Watchdog RESET Starting from the Watchdog counter underflow the The RESET sequence generated by a internal device RESET pin acts as an output that is pulled Watchdog counter overflow is shown in Figure 18 OW during at least Avmin Figure 18 Watchdog RESET Sequence VpDnominal RESET DELAY INTERNAL RESET FETCH 4096 CLOCK CYCLES VECTOR EXTERNAL RESET SOURCE WATCHDOG RESET i WATCHDOG UNDERFLOW 29 125 ST72334J N ST72314J N ST72124J MULTI OSCILLATOR MO The main clock of the ST7 can be generated by 7 different sources coming from the multi oscillator block m an external source 4 crystalor ceramic resonator oscillators m 1 external RC oscillator m 1 internal high frequency RC oscillator Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the OPTION BYTE External Clock Source The default OPTION BYTE value selects the Ex ternal Clock in the MO block In this mode a clock signal square sinus or triangle with 50 duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground see Figure 19 Figure 19 MO External Clock ST7 OSC2 OSC1 EXTERNAL SOURCE 30 125
32. bit the ICAP2 pin must be configured as floating input And select the following in the CR1 register Set ICIE bit to generate an interrupt after an input capture coming from both the ICAP1 pin or the ICAP2 pin Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit the ICAP1pin must be configured as floating input ST72334J N ST72314J N ST72124J When an input capture occurs ICFi bit is set The register contains the value of the free running counter on the active transition on the ICAPi pin see Figure 40 timer interrupt is generated if the ICIE bit is set and the bit is cleared in the CC register Other wise the interrupt remains pending until both conditions become true Clearing the Input Capture interrupt request is done in two steps 1 Reading the SR register while the ICF bit is set 2 An access read or write to the register Notes 2 After reading the IC HR register transfer of input capture data is inhibited until the register is also read 3 The IC R register always contains the free run ning counter value which corresponds to the most recent input capture 4 The 2 input capture functions can be used together even if the timer also uses the output compare mode 5 One pulse Mode PWM mode only the input capture 2 can be used 6 The alternate inputs ICAP1 amp ICAP2 are always directly
33. bit of the received word when 1 Bit 6 T8 Transmit data bit 8 This bit is used to store the 9th bit of the transmit ted word when M21 Bit 4 M Word length This bit determines the word length It is set or cleared by software 0 1 Start bit 8 Data bits 1 Stop bit 1 1 Start bit 9 Data bits 1 Stop bit Bit 3 WAKE Wake Up method This bit determines the SCI Wake Up method it is set or cleared by software 0 ldle Line 1 Address Mark CONTROL REGISTER 2 CR2 Read Write Reset Value 0000 0000 00h 7 0 Bit 7 TIE Transmitter interrupt enable This bit is set and cleared by software 0 interrupt is inhibited 1 An SCI interrupt is generated whenever TDRE 1 in the SR register Bit 6 TCIE Transmission complete interrupt ena ble This bit is set and cleared by software 0 interrupt is inhibited 92 125 1 An SCI interrupt 5 generated whenever TC 1 in the SR register Bit 5 RIE Receiver interrupt enable This bit is set and cleared by software 0 interrupt is inhibited 1 An interrupt is generated whenever OR 1 or RDRF 1 in the SR register Bit 4 dle line interrupt enable This bit is set and cleared by software 0 interrupt is inhibited 1 An SCI interrupt is generated whenever IDLE 1 in the SR register Bit 3 TE Transmitter enable This bit enables the transmitter and assigns the TDO pin to the alternate function It is set and cleared by software 0 Tran
34. in structions use short addressing modes only CLR CPL NEG BSET BRES BTJT BTJF INC DEC RLC RRC SLL SRL SRA SWAP The ST7 Assembler optimizes the use of long and short addressing modes Pointer ___ a S _ rong Short Id A 10 X 00 1FE 0 with X register 1 with register Long Id A 1000 X 0000 FFFF Short Indirect 194 10 00 FF 00 FF Long Indrect ____ ld A 10 w 0000 FFFF 00 FF Short Id A 10 X 00 1FE 00 FF Long TA 10 01 X 0000 FFFF 00 Relative Diect PC 128 PC 127 1 PRetatve __ me 10 1277 oor it ndirect elative 7 ski yte Bi di Relati bijt 10 7 skip 00 FF 00 FF b 3 Note 1 At the ounter OW p time the instruction Is executed the Program r points to the instruction fo ing JRxx 99 125 ST72334J N ST72314J N ST72124J ST7 ADDRESSING MODES Cont d 7 1 1 Inherent All Inherent instructions consist of a single byte The opcode fully specifies all the required informa tion for the CPU to process the operation TRAP S W Interrupt Wait For Interrupt Low Power Mode HALT Halt Oscillator Lowest Power Mode NO WF IRET Interrupt Sub routine Return RIM Reset Interrupt Mask SCF Set Carry Flag RCF Reset Ca
35. resp RR 8 PR 3 10416 67 TR resp RR 1 PR 13 19230 77 Extended Mode ETPR resp ERPR 13 38461 54 See STANDARD I O PORT PINS description for more details Note 1 Unless otherwise specified typical data are based on 25 and Vpp Vss 5V They are given only as design guide lines and are not tested 115 125 ST72334J N ST72314J N ST72124J MEMORY AND PERIPHERAL CHARACTERISTICS Cont d ADC Analog to Digital Converter 8 bit TUE Total unadjusted error Offset error 0 5 fopy 8MHZ fapc 4MHz DLE Differential linearity error JILE Integral linearity error Conversion range vtage A D conversion supply current Stabilization time after ADC enable 2 t 2 fApc 4MHz Sample capacitor loading time 5 tconv Hold conversion time Sample capaci Notes 1 Unless otherwise specified typical data are based on 25 and Vpp Vss 5V They are given only as design guide lines and are not tested 2 Data based on characterization results not tested in production 3 Tested in production at 25 characterized over the whole temperature range 4 ADC Accuracy vs Negative Injection Current For Ijyy 0 8mA the typical leakage induced inside the die is 1 6uA and the effect on the ADC accuracy is a loss of 1 LSB for each 10KQ increase of the external analog source impedance Thi
36. ropa rfl pot ren ee espe oss oss oss oos oos mp pep Number of Pins 8 EN 44 4x11 SK Plastic socket overall dimensions Table 23 Suggested List of TQFP44 Socket Types Package Probe Adaptor Socket Reference Socket type ENPLAS OTQ 44 0 8 04 Open Top TQFP44 YAMAICHI 51 0444 467 5 11787 Clamshell TQFP44 3 120 125 9 2 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device 15 available for production in user pro grammable versions FLASH as well as in factory coded versions ROM FLASH devices are shipped to customers with a default content FFh while ROM factory coded parts contain the code supplied by the customer This implies that FLASH devices have to be con figured by the customer using the Option Bytes while the ROM devices are factory configured 9 2 1 Option Bytes The two Option Bytes allow the hardware configu ration of the microcontroller to be selected The Option Bytes have no address in the memory map and can be accessed only in programming mode for example using standard 5 7 4programming tool The default contents of the FLASH is fixed to FFh This means that all the op tions have 1 as their default value In masked ROM devices the Option Bytes are fixed in hardware by the ROM code USER OPTION BYTE 1 7 0 Bit 7 2 Reserved must always be 1 Bit 1 56 42 Package configuration This opti
37. the WDGHALT option bit of the OPTION BYTE The HALT instruction when executed while the Watchdog system is enabled can generate a Watchdog RESET see dedicated section for more details When exiting HALT mode by means of a RESET or an interrupt the oscillator is immediately turned on and the 4096 CPU cycle delay is used to stabi lize the oscillator Figure 29 HALT modes flow chart If WDGHALT bit reset in i OPTION WATCHDOG ENABLE OSCILLATOR PERIPHERALS CPU BIT Y EXTERNAL INTERRUPT OSCILLATOR PERIP HERALS CPU Notes ST72334J N ST72314J N ST72124J Specific ACTIVE HALT mode As soon as the interrupt capability of the main os cillator is selected OIE bit set the HALT instruc tion will make the device enter a specific ACTIVE HALT power saving mode instead of the standard HALT one This mode consists of having only the main oscil lator and its associated counter running to keep a wake up time base All other peripherals are not clocked except the ones which get their clock sup ply from another clock generator such as external or auxiliary oscillator The safeguard against staying locked in this AC TIVE HALT mode is insured by the oscillator inter rupt Note As soon as the interrupt capability of one of the oscillators is selected OIE bit set entering in ACTIVE HALT mode while the Watchdog is active does not generate a RESET This means that the device cannot to spend
38. the master device WCOL bit The WCOL bit in the SR register is set if a write collision occurs No SPI interrupt is generated when the WCOL bit is set the WCOL bit is a status flag only Clearing the WCOL bit is done through a software sequence see Figure 50 Figure 50 Clearing the WCOL bit Write Collision Flag Software Sequence Clearing sequence after SPIF z 1 end of a data byte transfer ist Step Read SR 2nd Step Read DR WCOLCO Read SR Write DR SPIF 0 WCOL 0 if no transfer has started WCOL 1 if a transfer has started before the 2nd step Clearing sequence before SPIF 1 during data byte transfer Read SR Read DR 1st Step 2nd Step 76 125 THEN WCOL 0 Note Writing in DR register in stead of reading in it do not reset WCOL bit 3 SERIAL PERIPHERAL INTERFACE Cont d 6 5 4 5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low then the MODF bit is set Master mode fault affects the SPI peripheral in the following ways The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set The SPE bit is reset This blocks all output from the device and disables the SPI periph eral The MSTR bit is reset thus forcing the device into slave mode Clearing the MODF bit is done through a software sequence 1 A read or write access to the SR register while the MODF bit is set 2 A write to the CR r
39. to avoid a write collision see Section 6 5 4 4 73 125 ST72334J N ST72314J N ST72124J SERIAL PERIPHERAL INTERFACE Cont d 6 5 4 3 Data Transfer Format During an SPI transfer data is simultaneously transmitted shifted out serially and received shifted in serially The serial clock is used to syn chronize the data transfer during a sequence of eight clock pulses The SS pin allows individual selection of a slave device the other slave devices that are not select ed do not interfere with the SPI transfer Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software using the CPOL and CPHA bits The CPOL clock polarity bit controls the steady state value of the clock when no data is being transferred This bit affects both master and slave modes The combination between the CPOL and CPHA clock phase bits selects the data capture clock edge Figure 49 shows an SPI transfer with the four combinations of the CPHA and CPOL bits The di agram may be interpreted as a master or slave timing diagram where the SCK pin the MISO pin the MOSI pin are directly connected between the master and the slave device The SS pin is the slave device select input and can be driven by the master device Figure 48 CPHA SS Timing Diagram MOSI MISO Master SS The master device applies data to its MOSI pin clock edge before the capture clock edge CPHA bit is set The second edge on t
40. value 1 An input capture has occurred or the counter has reached the OC2R value in PWM mode To clear this bit first read the SR register then read or write the low byte of the IC1R IC1LR regis ter Bit 6 OCF1 Output Compare Flag 1 0 No match reset value 1 The content of the free running counter has matched the content of the OC1R register To clear this bit first read the SR register then read or write the low byte of the OC 1R OC1LR reg ister Bit 5 TOF Timer Overflow 0 No timer overflow reset value 1 The free running counter rolled over from FFFFh to 0000h To clear this bit first read the SR reg ister then read or write the low byte of the CR CLR register Note Reading or writing the ACLR register does not clear TOF Bit 4 ICF2 Input Capture Flag 2 0 No input capture reset value 1 An input capture has occurred To clear this bit first read the SR register then read or write the low byte of the IC2R IC2LR register Bit 3 OCF2 Output Compare Flag 2 0 No match reset value 1 The content of the free running counter has matched the content of the OC2R register To clear this bit first read the SR register then read or write the low byte of the OC2R OC2LR reg ister ST72334J N ST72314J N ST72124J Bit 2 0 Reserved forced by hardware to 0 INPUT CAPTURE 1 HIGH REGISTER IC1HR Read Only Reset Value Undefined This is an 8 bit read only register th
41. 00 0000 00h Allows setting of the Extended Prescaler rate divi sion factor for the receive circuit 7 0 ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR 7 6 5 4 3 2 1 0 Bit 7 1 ERPR 7 0 8 bit Extended Receive Pres caler Register The extended Baud Rate Generator is activated when a value different from is stored in this register Therefore the clock frequency issued from the 16 divider see Figure 54 is divided by the binary factor set in the ERPR register in the range 1 to 255 The extended baud rate generator is not used af ter a reset Table 18 SCI Register Map and Reset Values Address Register 7 Hex Label EXTENDED TRANSMIT PRESCALER DIVISION REGISTER ETPR Read Write Reset Value 0000 0000 00h Allows setting of the External Prescaler rate divi sion factor for the transmit circuit 7 0 ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR 7 6 5 4 3 2 1 0 Bit 7 1 ETPR 7 0 8 bit Extended Transmit Pres caler Register The extended Baud Rate Generator is activated when a value different from is stored in this register Therefore the clock frequency issued from the 16 divider see Figure 54 is divided by the binary factor set in the ETPR register in the range 1 to 255 The extended baud rate generator is not used af ter a reset SCISR RDRF IDLE LSB VPOL 2FHDET HVSEL VCORDIS CLPINV BLKINV 0054 SCICR2 TIE TCIE
42. 1 The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt 2 The ICF1 bit is set when an active edge occurs and can generate an interrupt if the ICIE bit is set 3 When the Pulse Width Modulation PWM and One Pulse Mode OPM bits are both set the PWM mode is the only active one 4 OLVL1 OLVL2 a continuous signal will be seen on the 1 pin 5 The ICAP1 pin can not be used to perform input capture The ICAP2 pin can be used to perform input capture ICF2 can be set and IC2R can be loaded but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set 6 When the one pulse mode is used is dedicated to this mode Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode 61 125 ST72334J N ST72314J N ST72124J Figure 44 One Pulse Mode Timing Example OCMP1 OLVL2 OLVL1 OLVL2 compare1 Note IEDG1 1 OC1R 2ED0h OLVL1 0 OLVL2 1 Figure 45 Pulse Width Modulation Mode Timing Example COUNTER FFFC 2EDO 2ED2 34E2 YFFFC OCMP1 OLVL2 OLVL1 OLVL2 compare2 comparet compare2 Note OC1R22bEDOh OC2R 34E2 OLVL1 0 OLVL2 1 62 125 4 16 BIT TIMER Cont d 6 4 3 7 Pulse Width Modulation M
43. 2 toru Note 1 Unless otherwise specified typical data are based on 25 and Vpp Vss 5V They are given only as design guide lines and are not tested 111 125 ST72334J N ST72314J N ST72124J MEMORY AND PERIPHERAL CHARACTERISTICS Cont d SPI Serial Peripheral Interface Symbol Parameter Condition Min Master 1 128 1 4 ti ead Enable lead time Slave 120 li ag Enable lag time Slave 120 Clock high time Hii 100 Master 100 Slave Master 100 Slave 100 ty Data hold time inputs 2 es Access time time to data active from high impedance state tsp Clock SCK low time tsu Data set up time try Disable time hold time to high im Dis pedance state Master before capture edge 0 25 Slave after enable edge Master before capture edge 0 25 Data hold time outputs Slave seri edge ge te Rise time Outputs SCK MOSI MISO Rise 20 Vpp to 70 Vpp 200pF Inputs SCK MOSI MISO SS t Fall time Outputs SCK MOSI MISO _ Fall 70 to 20 200pF Inputs SCK MOSI MISO SS c k Figure 59 SPI Master Timing Diagram CPHA 0 CPOL 0 2 55 INPUT SCK OUTPUT MISO INPUT MOSI OUTPUT VR000109 Notes 1 Data based on characterization results not tested in production 2 Measurement points Vi and in the SPI timing diag
44. 34 4 ST72334N2 5 72334 4 BC s TK RAM stack bytes 384 256 384 256 512 256 384 256 512 256 384 256 512 256 384 256 512 256 LC 5 Watchdog Peripherals Watchdog 16 bit Timers SPI 5 ADC SCI Operating Supply 3 0V to 5 5V CPU Frequency 500 kHz to 8 MHz with 1 to 16 MHz oscillator Operating Temperature 40 C to 85 C 40 C to 105 125 C optional TQFP44 SDIP42 TQFP64 SDIP56 TQFP44 SDIP42 TQFP64 SDIP56 Rev 1 0 September 1999 1 125 This is preliminary information on new product in development or undergoing evaluation Details are subject to change without notice Table of Contents 1 PREAMBLE ST72C334 VERSUS ST72E331 SPECIFICATION 5 2 GENERAL DESCRIPTION cr RR ie ee ee 6 21 INTRODUCTION 2 20 dees RESQUE 6 2 2 PIN DESCRIPTION mare ea ee ER CERTES 7 2 3 REGISTER amp MEMORY MAP 1 12 2 4 FLASH PROGRAMIMEMORY vesper ee dae nee TRES 16 2 4 1 INthOGUCTION 16 2 4 2 Malin features edi rh eR Rx ed Sone Pek ee eh ees 16 2 4 8 Structural organisation 11 42 20 4 16 2 4 4 In Situ Programming ISP
45. C opcode PC 1 Additional word 0 to 2 according to the number of bytes required to compute the ef fective address 102 125 These prebytes enable instruction in Y as well as indirect addressing modes to be implemented They precede the opcode of the instruction in X or the instruction using direct addressing mode The prebytes are PDY 90 Replace an X based instruction using immediate direct indexed or inherent ad dressing mode by a Y one PIX 92 Replace an instruction using di rect direct bit or direct relative addressing mode to an instruction using the corresponding indirect addressing mode It also changes an instruction using X indexed ad dressing mode to an instruction using indirect X in dexed addressing mode PIY 91 Replace an instruction using X in direct indexed addressing mode by a Y one 3 ST72334J N ST72314J N ST72124J INSTRUCTION GROUPS Mnemo Description ___ FunctionExample Dst Sre _ CP __ SES ser sr gn Bri uw _ feno CALLA Caavbrouine wave que ____ ____ One Complement ___ _____ DEC Decrement War a RET memermunewum
46. CAP1 B PC2 HS ICAP2 B PC1 OCMP1 B PC0 OCMP2 Ves AINO PDO AIN1 PD1 AIN2 PD2 AIN3 PD3 m 10 11 12 13 14 15 16 1 N 99 O 5 PD5 AIN6 6 O AIN7 PD7 PF1 HS 0 HS 7 O EXTCLK A ICAP1 A 7 125 ST72334J N ST72314J N ST72124J PIN DESCRIPTION Cont d Figure 3 56 Pin SDIP Package Pinout N versions 4 5 6 7 AINO PDO AIN1 PD1 AIN2 PD2 AIN3 AIN5 PDS AIN6 PD6 AIN7 PD7 Vppa Vssa PFO 1 2 1_ 4 1 HS EXTCLK_A HS Vss_0 OCMP2_B PCO OCMP1 B PC1 ICAP2 HS PC2 ICAP1 B HS PC3 ISPDATA MISO PC4 MOSI PC5 oo N 4 HS PE1 RDI TDO Vpp 2 OSC1 OSC2 RESET ISPSEL c E OAN NOOO O 6 SCK ISPCLK 3 8 125 DESCRIPTION ST72334J N ST72314J N ST72124J Figure 4 44 Pin 42 Pin SDIP Package Pinouts J versions PE1 RDI PBO PB1 PB2 4 AINO PDO AIN1 PD1 AIN2 PD2 AINS AIN5 PD5 4 AINO PDO AIN1 PD1 AIN2 PD2 AIN3 PD3
47. CC register is pushed on the stack 40 125 3 POWER SAVING MODES Cont d 5 2 4 SLOW Mode This mode has two targets Toreduce power consumption by decreasing the internal clock in the device To adapt the internal clock frequency fep to the available supply voltage SLOW mode is controlled by three bits in the MISCR1 register the SMS bit which enables or ST72334J N ST72314J N ST72124J disables Slow mode and two CPx bits which select the internal slow frequency fep In this mode the oscillator frequency can be divid ed by 4 8 16 or 32 instead of 2 in normal operat ing mode The CPU and peripherals are clocked at this lower frequency Note SLOW WAIT mode is activated when enter ring the WAIT mode while the device is already in SLOW mode Figure 31 SLOW Mode timing diagram for internal CPU clock transitions NEW FREQUENCY ACTIVEWHEN OSC 4 amp OSC 8 0 NEW FREQUENCY REQUEST NORMAL MODE ACTIVE OSC 4 OSC 8 STOPPED MISCR1 REGISTER NORMAL MODE REQUEST 41 125 ST72334J N ST72314J N ST72124J 6 ON CHIP PERIPHERALS 6 1 PORTS 6 1 1 Introduction The ports offer different functional modes transfer of data through digital inputs and outputs and for specific pins external interrupt generation alternate signal input output for the on chip pe ripherals SPI SCI TIMERs An I O port contains up to 8 pins Each pin can be programme
48. DCCSR Control Status Register 00h Reserved Area 14 Bytes Notes 1 The bits corresponding to unavailable pins are forced to 1 by hardware this affects the reset status value 2 External pin not available 3 Not used in versions without Low Voltage Detector Reset 15 125 ST72334J N ST72314J N ST72124J 2 4 FLASH PROGRAM MEMORY 2 4 1 Introduction Flash devices have a single voltage non volatile FLASH memory that may be programmed in situ or plugged in a programming tool on a byte by byte basis 2 4 2 Main features m Remote In Situ Programming ISP mode m Up to 16 bytes programmed in the same cycle m MTP memory Multiple Time Programmable m Read out memory protection against piracy 2 4 3 Structural organisation The FLASH program memory is organised in a single 8 bit wide memory block which can be used for storing both code and data constants The FLASH program memory is mapped in the up per part of the ST7 addressing space F000h FFFFh and includes the reset and interrupt user vector area 2 4 4 In Situ Programming ISP mode The FLASH program memory can be programmed using Remote ISP mode This ISP mode allows the contents of the ST7 program memory to be up dated using a standard ST7 programming tools af ter the device is mounted on the application board This feature can be implemented with a minimum number of added components and board area im pact An example Remote ISP hardware interface
49. Du Reset Value 3 20 125 3 CENTRAL PROCESSING UNIT 3 1 INTRODUCTION This CPU has a full 8 bit architecture and contains six internal registers allowing efficient 8 bit data manipulation 3 2 MAIN FEATURES 63 basic instructions Fast 8 bit by 8 bit multiply 17 main addressing modes Two 8 bit index registers 16 bit stack pointer Low power modes Maskable hardware interrupts Non maskable software interrupt 3 3 CPU REGISTERS The 6 CPU registers shown in Figure 10 are not present in the memory mapping and are accessed by specific instructions Figure 10 CPU Registers RESET VALUE XXh 7 RESET VALUE XXh 7 RESET VALUE XXh 115 817 0 RESET VALUE RESET VECTOR FFFEh FFFFh T 0 2 lt RESET VALUE 1 4 1 X 1 X X X 15 8i7 01 RESET VALUE STACK HIGHER ADDRESS ST72334J N ST72314J N ST72124J Accumulator A The Accumulator is an 8 bit general purpose reg ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data Index Registers X and Y In indexed addressing modes these 8 bit registers are used to create either effective addresses or temporary storage areas for data manipulation The Cross Assembler generates a precede in struction PRE to indicate that the following in struction refers to the Y register The Y register is not affected by the interrupt auto matic procedures not pushed to and popped f
50. ECTRICAL CHARACTERISTICS Recommended operating conditions with 40 to 85 C Vpp Vsg 5V unless otherwise specified Symbol Paameer Conditions sc 4 MHz fcpy 2 MHz Supply current in RUN mode fosc 8 MHz fcpy 4 MHz fosc 16 MHz 8 2 fosc 4 MHz fopy 125 kHz Supply current in SLOW mode 2 fosc 8 MHz 250 kHz fosc 16 MHz fopu 500 kHz fosc 4 MHz fopu 2 MHz Supply current in WAIT mode 3 fosc 8MHz fcpy 4 MHz fosc 16MHz 8 MHz fosc 4 MHz 2 MHz Supply current SLOW WAIT mode 3 fosc 8 MHz 250 kHz fosc 16 MHz fopy 500 kHz Supply current in HALT mode 7 T oap mA eurenton Vos Vm Uwareennmoje HALTmode 2 8 4 GENERAL TIMING CHARACTERISTICS uem Notes 1 Unless otherwise specified typical data are based on 25 and Vpp Vsg 5V They are given only as design guide lines and are not tested 2 CPU running with memory access all I O pins in input mode with a static value at Vpp or Vgg all peripherals switched off clock input OSC1 driven by external square wave 3 All I O pins in input mode with a static value at Vpp or Vss all peripherals switched off clock input OSC1 driven by external square wave 4 All I O pins in input mode with a static value at Vpp or Vss LVD disabled 5 Data based on characterization resul
51. H User Programmable Device Types TEMP DEVICE PACKAGE RANGE Code name defined by STMicroelectronics 1 standard 0 to 70 C 6 industrial 40 to 85 C 7 automotive 40 to 125 C 3 automotive 40 to 125 C B Plastic DIP T Plastic TQFP ST72C334J2 ST72C334J4 ST72C334N2 ST72C334N4 ST72C314J2 ST72C314J4 ST72C314N2 ST72C314NA ST72C124J2 3 122 125 ST72334J N ST72314J N ST72124J MICROCONTROLLER OPTION LIST Customer Address Contact Phone No Reference STMicroelectronics references Device ST72334J2 ST72314J2 ST72124J2 ST72334J4 ST72314J4 ST72334N2 ST72314N2 1 ST72334N4 577231434 64 SDIP56 44 SDIP42 0 C to 70 C 1 40 C to 85 C 40 C to 125 C Clock Source Selection 1 Resonator LP Low power resonator 1 to 2 MHz MP Medium power resonator 2 to 4 MHz MS Medium speed resonator 4 to 8 MHz 1 HS High speed resonator 8 to 16 MHz RC Network Internal External External Clock Clock Security System Disabled Enabled Watchdog Selection Software Activation Hardware Activation Halt when Watchdog on Reset No reset Readout Protection Disabled Enabled LVD Reset Disabled 1 Enabled Highest threshold 4 30V 4 05V Medium threshold 3 90V 3 65V Lowest threshold 3 35V 3 10V Commen
52. IGITAL CONVERTER 2222121227212 95 125 ST72334J N ST72314J N ST72124J 8 BIT A D CONVERTER ADC Cont d 6 7 3 2 Digital A D Conversion Result The conversion is monotonic meaning that the re sult never decreases if the analog input does not and never increases if the analog input does not If the input voltage is greater than or equal to Vppa high level voltage reference then the conversion result in the DR register is FFh full scale without overflow indication If input voltage is lower than or equal to Vssa low level voltage reference then the con version result in the DR register is OOh The A D converter is linear and the digital result of the conversion is stored in the ADCDR register The accuracy of the conversion is described in the Electrical Characteristics Section Rain is the maximum recommended impedance for an analog input signal If the impedance is too high this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time 6 7 3 3 A D Conversion Phases The A D conversion is based on two conversion phases as shown in Figure 57 m Sample capacitor loading duration During this phase the input voltage to be measured is loaded into the CsampLe sample capacitor A D conversion duration During this phase the A D conversion is computed 8 successive approximations cycles and the C
53. LR Timer A Input Capture 2 Low Register Read Only 2 TAOC2HR Timer A Output Compare 2 High Register R W 2 Timer A Output Compare 2 Low Register R W 0040h MISCR2 Miscellaneous Register 2 om TBCR2 Timer B Control Register 2 R W TBCR1 Timer B Control Register 1 R W TBSR Timer B Status Register Read Only TBIC1HR Timer B Input Capture 1 High Register Read Only TBIC1LR Timer B Input Capture 1 Low Register Read Only 1 Timer B Output Compare 1 High Register R W TBOC1LR Timer B Output Compare 1 Low Register R W TIMER B TBCHR Timer B Counter High Register Read Only TBCLR Timer B Counter Low Register Read Only TBACHR Timer B Alternate Counter High Register Read Only TBACLR Timer B Alternate Counter Low Register Read Only TBIC2HR Timer B Input Capture 2 High Register Read Only TBIC2LR Timer B Input Capture 2 Low Register Read Only 2 Timer B Output Compare 2 High Register R W TBOC2LR Timer B Output Compare 2 Low Register R W SCISR SCI Status Register COh Read Only SCIDR SCI Data Register xxh R W SCIBRR SCI Baud Rate Register 00 xxxx R W SCICR1 SCI Control Register 1 xxh R W SCICR2 SCI Control Register 2 00h R W SCIERPR SCI Extended Receive Prescaler Register 00h R W Reserved area SCIETPR SCI Extended Transmit Prescaler Register 4 14 125 ST72334J N ST72314J N ST72124J Register Reset Reserved Area 24 Bytes 0070h ADCDR Data Register xxh 0071h A
54. OM RESET STACK PC X A CC SET BIT LOAD PC FROM INTERRUPT VECTOR EXECUTE INSTRUCTION RESTORE X A CC FROM STACK THIS CLEARS BIT BY DEFAULT Table 6 Interrupt Mapping Source Description Register Priority Address Block Label Order Vector 8 TMERA TIMER Peripheral Iterups TASR 9 TIMERB TIMER Peripheral Interrupts FFEAh FFEBh FFE8h FFE9h 37 125 ST72334J N ST72314J N ST72124J 5 2 POWER SAVING MODES 5 2 1 Introduction To give a large measure of flexibility to the applica tion in terms of power consumption four main power saving modes are implemented in the ST7 After a RESET the normal operating mode is se lected by default RUN mode This mode drives the device CPU and embedded peripherals by means of a master clock which is based on the main oscillator frequency divided by 2 fcpy From Run mode the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the the oscil lator status Figure 27 Power saving mode consumption transitions C EN a m HALT ACTIVE HALT SLOW WAIT WAIT SLOW RUN POWER CONSUMPTION 5 2 2 HALT Modes The HALT modes are the lowest power consump tion modes of the MCU They are entered by exe cuting the ST7 HALT instruction see Figure 29 Two different HALT modes can be
55. Program Memory Read out Protection The read out protection is enabled through an op tion bit For FLASH devices when this option is selected the program and data stored in the FLASH memo ry are protected against read out piracy including a re write protection When this protection option is removed the entire FLASH program memory is first automatically erased 3 ST72334J N ST72314J N ST72124J 2 6 DATA EEPROM 2 6 1 Introduction 2 6 2 Main Features The Electrically Erasable Programmable Read m Upto 16 Bytes programmed in the same cycle Only Memory can be used as a non volatile back EEPROM mono voltage charge pump up for storing data Using the EEPROM requires a Chained erase and programming cycles basic access protocol described in this chapter Internal control of the global programming cycle duration End of programming cycle interrupt flag m WAIT mode management Figure 7 EEPROM Block Diagram FALLING EEPROM INTERRUPT EDGE DETECTOR X HIGH VOLTAGE PUMP RESERVED EEPROM m MEMORY MATRIX 1 ROW 16 x 8 BITS ADDRESS ROW DECODER DECODER DATA 16x 8 BITS MULTIPLEXER DATA LATCHES ADDRESS BUS 17 125 ST72334J N ST72314J N ST72124J DATA EEPROM Cont d 2 6 3 Memory Access The Data EEPROM memory read write access modes are controlled by the LAT bit of the EEP ROM Control Status register EECSR The flow chart in Figure 8 describes these d
56. R LOW REGISTER CLR Read Only Reset Value 1111 1100 FCh This is an 8 bit register that contains the low part of the counter value A write to this register resets the counter An access to this register after accessing the SR register clears the TOF bit 7 0 68 125 ALTERNATE COUNTER HIGH REGISTER ACHR Read Only Reset Value 1111 1111 FFh This is an 8 bit register that contains the high part of the counter value 7 0 per ee ALTERNATE COUNTER LOW REGISTER ACLR Read Only Reset Value 1111 1100 FCh This is an 8 bit register that contains the low part of the counter value A write to this register resets the counter An access to this register after an access to SR register does not clear the TOF bit in SR register 7 0 INPUT CAPTURE 2 HIGH REGISTER 2 Read Only Reset Value Undefined This is an 8 bit read only register that contains the high part of the counter value transferred by the Input Capture 2 event 7 0 INPUT CAPTURE 2 LOW REGISTER IC2LR Read Only Reset Value Undefined This is an 8 bit read only register that contains the low part of the counter value transferred by the In put Capture 2 event 7 0 4 ST72334J N ST72314J N ST72124J 16 BIT TIMER Cont d Table 15 16 Bit Timer Register Map and Reset Values pa ird icd S E Po Address Register Hex Label Timer A 32
57. R W Port B Option Register 00h R W 7 Reserved Area 1 Byte Port E Data Register 00h R W Port E Data Direction Register 00h R W Port E Option Register 00h Ew 1 Reserved Area 1 Byte Port D Data Register 00h R W Port D Data Direction Register 00h R W Port D Option Register 00h R W 7 Reserved Area 1 Byte Port F Data Register 00h R W Port F Data Direction Register 00h R W Port F Option Register 00h R W Reserved Area 9 Bytes SPI Data I O Register R W SPI Control Register R W SPI Status Register Read Only Reserved Area 5 Bytes 437 13 125 ST72334J N ST72314J N ST72124J Register Reset 002Ah WATCHDOG WDGCR Watchdog Control Register 002Bh CRSR Clock Reset Supply Control Status Registe oon RW 002Ch Data EEPROM EECSR Data EEPROM Control Status Register 002Dh 0030h Reserved Area 4 Bytes TACR2 Timer A Control Register 2 R W TACR1 Timer A Control Register 1 R W TASR Timer A Status Register Read Only TAIC1HR Timer A Input Capture 1 High Register Read Only TAIC1LR Timer A Input Capture 1 Low Register Read Only 1 Timer A Output Compare 1 High Register R W TAOC1LR Timer A Output Compare 1 Low Register R W TIMER A TACHR Timer A Counter High Register Read Only TACLR Timer A Counter Low Register Read Only TAACHR Timer A Alternate Counter High Register Read Only TAACLR Timer A Alternate Counter Low Register Read Only TAIC2HR Timer A Input Capture 2 High Register Read 5 TAIC2
58. RIE ILIE TE RE RWU SBK Reset Value 0 0 0 0 0 0 0 0 SCIPBRR MSB LSB SCIPBRT MSB LSB 3 94 125 6 7 8 BIT A D CONVERTER ADC 6 7 1 Introduction The on chip Analog to Digital Converter ADC pe ripheral is a 8 bit successive approximation con verter with internal sample and hold circuitry This peripheral has up to 16 multiplexed analog input channels refer to device pin out description that allow the peripheral to convert the analog voltage levels from up to 16 different sources The result of the conversion is stored in a 8 bit Data Register The A D converter is controlled through a Control Status Register 6 7 2 Main Features 8 bit conversion Up to 16 channels with multiplexed input Linear successive approximation Data register DR which contains the results Conversion complete status flag On off bit to reduce consumption The block diagram is shown in Figure 56 Figure 56 ADC Block Diagram ST72334J N ST72314J N ST72124J 6 7 3 Functional Description 6 7 3 1 Analog Power Supply VppA Vssa are the high and low level refer ence voltage pins In some devices refer to device pin out description they are internally connected to the Vss pins Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines Figure 55 Recommended Ext Connections Px x AINx ANALOG TO D
59. SET 3 RESET SEQUENCE MANAGER External RESET pin The RESET pin is both an input and an open drain output with integrated Row weak pull up resistor This pull up has no fixed value but varies in ac cordance with the input voltage It can be pulled low by external circuitry to reset the device Figure 16 External RESET Sequences ST72334J N ST72314J N ST72124J A RESET signal originating from an external source must have a duration of at least sp order to be recognized Two RESET sequences can be associated with this RESET source as shown in Figure 16 Starting from the external RESET pulse recogni tion the device RESET pin acts as an output that is pulled low during at least tpg Avmin RESET DELAYmin qM tPULSE 4 o tc z o 2 o z DELAY INTERNAL RESET FETCH 4096 CLOCK CYCLES VECTOR 1 EXTERNAL RESET SOURCE WATCHDOG RESET WATCHDOG RESET 27 125 ST72334J N ST72314J N ST72124J RESET SEQUENCE MANAGER Cont d Internal Low Voltage Detection RESET Two different RESET sequences caused by the in ternal LVD circuitry can be distinguished m Power On RESET Figure 17 LVD RESET Sequences VpDnominal POWER ON RESET VpDnominal o tc tc a lt gt 28 125 m Voltage Drop RESET The device RESET pin acts as an output that is pulled low when Vpp
60. SS CONTROLLER MAIN CLOCK MULTI CLOCK CLOC OSCILLATOR MO FILTER OSC E MCC RESET SEQUENCE MANAGER FROM RSM WATCHDOG PERIPHERAL LOW VOLTAGE DETECTOR CSS INTERRUPT 24 125 4 4 1 LOW VOLTAGE DETECTOR LVD To allow the integration of power management features in the application the Low Voltage Detec tor function LVD generates a static reset when the Vpp supply voltage is below a V yp reference value This means that it secures the power up as well as the power down keeping the ST7 in reset The V yp reference value for a voltage drop is lower than the V yp reference value for power on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply hysteresis The LVD Reset circuitry generates a reset when Vpp is below M yp When Vpp is rising when Vpp is falling The LVD function is illustrated in the Figure 13 Provided the minimum Vpp value guaranteed for the oscillator frequency is below yp the MCU can only be in two modes under full software control in static safe reset Figure 13 Low Voltage Detector vs Reset ST72334J N ST72314J N ST72124J In these conditions secure operation is always en sured for the application without the need for ex ternal reset hardware During a Low Voltage Detector Reset the RESET pin is held low thus permitting the MCU to reset other devices Notes 1 th
61. ST72C334 I O Confuguration and Pinout Same pinout as ST72E331 PA6 and PA7 are true open drain ports without pull up same as ST72E331 m PB3 4 and PF2 have no pull up configuration all lOs present on TQFP44 5 4 PC3 2 7 4 PF7 6 have high sink capabilities 20 N buffer 2mA P buffer pull up On the ST72E331 all these pads except PA5 4 were 2mA push pull pad without high sink capabilities PA4 were 20mA true open drain New Memory Locations in ST72C334 m 20h MISCR register becomes MISCR 1 register naming change m 29h new control status register for the MCC module m 2Bh new control status register for the Clock Reset and Supply control This register replaces the WDGSR register keeping the WDOGF flag compatibility m 40h new MISCR2 register 5 125 ST72334J N ST72314J N ST72124J 2 GENERAL DESCRIPTION 2 1 INTRODUCTION The ST72334J N ST72314J N and ST72124J de vices are members of the ST7 microcontroller fam ily They can be grouped as follows ST72334J N devices are designed for mid range applications with Data EEPROM ADC SPI and SCI interface capabilities ST72314J N devices target the same range of applications but without Data EEPROM ST72124J devices are for applications that do not need Data EEPROM and the ADC peripher al All devices are based on a common industry standard 8 bit core featuring an enha
62. T power saving mode Bit 0 OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the CSR register It indicates when set that the main oscillator has measured the selected elapsed time TB1 0 0 Timeout not reached 1 Timeout reached Warning The BRES and BSET instructions must not be used on the MCCSR register to avoid unin tentionally clearing the OIF bit MCCSR r 35 125 ST72334J N ST72314J N ST72124J 5 INTERRUPTS amp POWER SAVING MODES 5 1 INTERRUPTS The ST7 core may be interrupted by one of two dif ferent methods maskable hardware interrupts as listed in the Interrupt Mapping Table and a non maskable software interrupt TRAP The Interrupt processing flowchart is shown in Figure 26 The maskable interrupts must be enabled clearing the I bit in order to be serviced However disabled interrupts may be latched and processed when they are enabled see external interrupts subsec tion When an interrupt has to be serviced Normal processing is suspended at the end of the current instruction execution The PC X A and CC registers are saved onto the stack The bit of the CC register is set to prevent addi tional interrupts ThePC is then loaded with the interrupt vector of the interruptto service and the first instruction of the interrupt service routine is fetched refer to the Interrupt Mapping Table for vector address es The
63. TB1 TBO OIE and OIF The clock out capability allows to configure a ded icated port pin as fosc 2 clock out to drive external devices It is controlled by the MCO bit in the MISCR1 register When selected the clock out pin suspends the clock during ACTIVE HALT mode Figure 25 Main Clock Controller MCC Block Diagram p OSCILLATOR MISCR1 DIV 2 4 8 16 CPU CLOCK TO CPU AND PERIPHERALS PORT ALTERNATE FUNCTION 34 125 4 MAIN CLOCK CONTROLLER MISCELLANEOUS REGISTER 1 MISCR1 See section 6 2 on page 47 MAIN CLOCK CONTROL STATUS REGISTER MCCSR Read Write Reset Value 0000 0001 01h 7 0 Bit 7 4 Reserved always read as 0 Bit 3 2 TB1 TBO Time base These bits select the programmable divider time base They are set and cleared by software TB1 Prescaler fosc 8MHz fosc 16MHz 52000 ms Address Register Hex Label ST72334J N ST72314J N ST72124J A modification of the time base is taken into ac count at the end of the current period previously set to avoid unwanted time shift This allows to use this time base as a real time clock Bit 1 OIE Oscillator interrupt enable This bit set and cleared by software 0 Oscillator interrupt disabled 1 Oscillator interrupt enabled This interrupt allows to exit from ACTIVE HALT mode When this bit is set calling the ST7 software HALT instruction enters the ACTIVE HAL
64. U 2 Four programmable master bit rates Programmable clock polarity and phase End of transfer interrupt flag Write collision flag protection Master mode fault protection capability Figure 46 Serial Peripheral Interface Master Slave MASTER MSBit 4 LSBit 8 SHIFT SPI CLOCK GENERATOR 70 125 6 5 3 General description The SPI is connected to external devices through 4 alternate pins MISO Master In Slave Out pin MOSI Master Out Slave In pin SCK Serial Clock pin SS Slave select pin A basic example of interconnections between a single master and a single slave is illustrated on Figure 46 The MOSI pins are connected together as are MISO pins In this way data is transferred serially between master and slave most significant bit first When the master device transmits data to a slave device via MOSI pin the slave device responds by sending data to the master device via the MISO pin This implies full duplex transmission with both data out and data in synchronized with the same clock signal which is provided by the master de vice via the SCK pin Thus the byte transmitted is replaced by the byte received and eliminates the need for separate transmit empty and receiver full bits A status flag is used to indicate that the operation is com plete Four possible data clock timing relationships may be chosen see Figure 49 but master and slave mus
65. WDG HALT Watchdog and halt mode This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active 0 No Reset generation when entering Halt mode 1 Reset generation when entering Halt mode Bit 0 WDG SW Hardware or software watchdog This option bit selects the watchdog type 0 Hardware watchdog always enabled 1 Software watchdog to be enabled by software 121 125 ST72334J N ST72314J N ST72124J DEVICE CONFIGURATION AND ORDERING INFORMATION Cont d 9 2 2 Transfer Of Customer Code Customer code is made up of the ROM contents and the list of the selected options if any The ROM contents are to be sent on diskette or by electronic means with the hexadecimal file in S19 format generated by the development tool All un The selected options are communicated to STMi croelectronics using the correctly completed OP TION LIST appended The STMicroelectronics Sales Organization will be pleased to provide detailed information on con tractual points used bytes must be set to FFh Figure 73 ROM Factory Coded Device Types TEMP DEVICE PACKAGE RANGE u XXX Code name defined by STMicroelectronics 1 standard 0 to 70 C 6 industrial 40 to 85 C 7 automotive 40 to 125 C 3 automotive 40 to 125 C B Plastic DIP T Plastic TQFP ST72334J2 ST72334J4 ST72334N2 ST72334N4 ST72314J2 ST72314J4 5 72314 2 ST72314N4 ST72124J2 Figure 74 FLAS
66. _ 280 34 4 Sale Oscar 56 29 Hu m Sopp caret Notes 1 Unless otherwise specified typical data are based on 25 and Vpp Vss 5V They are given only as design guide lines and are not tested 2 These data are based on typical The oscillator selection can be optimized in terms of supply current with high quality resonator 3 is the equivalent serial resistance of the crystal or ceramic resonator 4 Data based on design simulation and or technology characteristics not tested in production 5 Data based on characterization results not tested in production 6 In this condition the capacitor to be considered is the global parasitic capacitor In this case the RC oscillator frequen cy tuning has to be done by trying out several resistor values 110 125 177 ST72334J N ST72314J N ST72124J 8 7 MEMORY AND PERIPHERAL CHARACTERISTICS Recommended operating conditions with 40 to 85 C and 3V Vpp Vss 5 5V unless otherwise specified FLASH Program Memory FLASH Program Wemoy 2 Parameter min typ unt iseenos Typical programming me 21 64 seo Dataretenion 1 4 Naw Write erase eyes f oo 90 Data EEPROM Programming time Data retention Write erase cycles WATCHDOG 12 288 786 43
67. alue Undefined 7 0 o os oo e The DR register is used to transmit and receive data on the serial bus In the master device only a write to this register will initiate transmission re ception of another byte Notes During the last clock cycle the SPIF bit is set a copy of the received data byte in the shift register is moved to a buffer When the user reads the serial peripheral data I O register the buffer is actually being read Warning A write to the DR register places data directly into the shift register for transmission A write to the the DR register returns the value lo cated in the buffer and not the contents of the shift register See Figure 47 81 125 ST72334J N ST72314J N ST72124J SERIAL PERIPHERAL INTERFACE Cont d Table 17 SPI Register Map and Reset Values Address Register Hex Label SPIDR MSB Reset Value aes SPICR mE E He 0022h Reset Value SPISR SPIF WCOL MODF r 82 125 6 6 SERIAL COMMUNICATIONS INTERFACE SCI 6 6 1 Introduction The Serial Communications Interface SCI offers a flexible means of full duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format The SCI of fers a very wide range of baud rates using two baud rate generator systems 6 6 2 Main Features m Full duplex asynchronous communications m NRZ standard format Mark Space m Dual baud r
68. are se quence an access to the SR register followed by a write to the DR register 0 Transmission is not complete 1 Transmission is complete Bit 5 RDRF Received data ready flag This bit is set by hardware when the content of the RDR register has been transferred into the DR register An interrupt is generated if RIE 1 in the CR2 register It is cleared by hardware when RE 0 or by a software sequence an access to the SR register followed by a read to the DR register 0 Data is not received 1 Received data is ready to be read Bit 4 IDLE dle line detect This bit is set by hardware when a Idle Line is de tected An interrupt is generated if the ILIE 1 in the CR2 register It is cleared by hardware when 0 by a software sequence an access to the SR register followed by a read to the DR register 0 No ldle Line is detected 1 Idle Line is detected ST72334J N ST72314J N ST72124J Note The IDLE bit will not be set again until the RDREF bit has been set itself i e a new idle line oc curs This bit is not set by an idle line when the re ceiver wakes up from wake up mode Bit 3 OR Overrun error This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF 1 An interrupt is generated if RIE 1 in the CR2 reg ister It is cleared by hardware when RE 0 by a software sequence an access to the SR register followed
69. at contains the high part of the counter value transferred by the input capture 1 event 7 0 j INPUT CAPTURE 1 LOW REGISTER IC1LR Read Only Reset Value Undefined This is an 8 bit read only register that contains the low part of the counter value transferred by the in put capture 1 event 7 0 OUTPUT COMPARE 1 HIGH REGISTER OC1HR Read Write Reset Value 1000 0000 80h This is an 8 bit register that contains the high part of the value to be compared to the CHR register 7 0 OUTPUT COMPARE 1 LOW REGISTER OC1LR Read Write Reset Value 0000 0000 00h This is an 8 bit register that contains the low part of the value to be compared to the CLR register 7 0 j 67 125 ST72334J N ST72314J N ST72124J 16 BIT TIMER Cont d OUTPUT COMPARE 2 HIGH REGISTER OC2HR Read Write Reset Value 1000 0000 80h This is an 8 bit register that contains the high part of the value to be compared to the CHR register 7 0 peu qo OUTPUT COMPARE 2 LOW REGISTER OC2LR Read Write Reset Value 0000 0000 00h This is an 8 bit register that contains the low part of the value to be compared to the CLR register 7 0 COUNTER HIGH REGISTER CHR Read Only Reset Value 1111 1111 FFh This is an 8 bit register that contains the high part of the counter value 7 0 me ___ je COUNTE
70. ate generator systems Independently programmable transmit receive baud rates up to 250K baud Programmable data word length 8 or 9 bits Receive buffer full Transmit buffer empty and End of Transmission flags Two receiver wake up modes Address bit MSB Idle line m Muting function for multiprocessor configurations Separate enable bits for Transmitter and Receiver Three error detection flags Overrun error Noise error Frame error Five interrupt sources with flags Transmit data register empty Transmission complete Receive data register full Idle line received Overrun error detected ST72334J N ST72314J N ST72124J 6 6 3 General Description The interface is externally connected to another device by two pins see Figure 53 TDO Transmit Data Output When the transmit ter is disabled the output pin returns to its port configuration When the transmitter is ena bled and nothing is to be transmitted the TDO pin is at high level RDI Receive Data Input is the serial data input Oversampling techniques are used for data re covery by discriminating between valid incoming data and noise Through this pins serial data is transmitted and re ceived as frames comprising An Idle Line prior to transmission or reception A start bit A data word 8 or 9 bits least significant bit first A Stop bit indicating that th
71. ates that the last Reset was generat ed by the LVD block It is set by hardware LVD re set and cleared by software writing zero See WDGRHEF flag description for more details When the LVD is disabled by OPTION BYTE the LVDRF bit value is undefined Bit 3 Reserved always read as 0 Bit 2 CSSIE Clock security syst interrupt enable This bit enables the interrupt when a disturbance is detected by the Clock Security System CSSD bit set It is set and cleared by software 0 Clock security system interrupt disabled 1 Clock security system interrupt enabled When the CSS is disabled by OPTION BYTE the CSSIE bit has no effect Bit 1 CSSD Clock security system detection This bit indicates that the safe oscillator of the Clock Security System block has been selected by hardware due to a disturbance on the main clock signal fosc It is set by hardware and cleared by a read of the CRSR register when the original os cillator recovers 0 Safe oscillator is not active 1 Safe oscillator has been activated When the CSS is disabled by OPTION BYTE the CSSD bit value is forced to 0 Bit WDGRF Watchdog reset flag This bit indicates that the last Reset was generat ed by the Watchdog peripheral It is set by hard ware watchdog reset and cleared by software writing zero or a LVD Reset to ensure a stable cleared state of the WDGRF flag when CPU starts Combined with the LVDRF flag information the flag description is
72. ating pull up push pull Port F floating floating interrupt push pull PF1 0 floating pull up interrupt push pull 44 125 4 PORTS 6 1 4 Register Description DATA REGISTER DR Port x Data Register PxDR with A B C D E or F Read Write Reset Value 0000 0000 00h 7 0 ST72334J N ST72314J N ST72124J OPTION REGISTER OR Port x Option Register PxOR with D or F Read Write Reset Value 0000 0000 00h 7 0 Bit 7 0 D 7 0 Data register 8 bits The DR register has a specific behaviour accord ing to the selected input output configuration Writ ing the DR register is always taken into account even ifthe pin is configured as an input this allows to always have the expected level on the pin when toggling to output mode Reading the DR register returns either the DR register latch content pin configured as output or the digital value applied to the pin pin configured as input DATA DIRECTION REGISTER DDR Port x Data Direction Register PxDDR with x A B C D Eor F Read Write Reset Value 0000 0000 00h 7 0 Bit 7 0 DD 7 0 Data direction register 8 bits The DDR register gives the input output direction configuration of the pins Each bits is set and cleared by software 0 Input mode 1 Output mode Bit 7 0 O 7 0 Option register 8 bits For specific I O pins this register is not implement ed In this case the DDR re
73. be totally fil tered and then no clock signal is available for the ST7 from this oscillator anymore If the original clock source recovers the filtering is stopped au tomatically and the oscillator supplies the ST7 clock Figure 23 Clock Filter Function MAIN OSCILLATOR CLOCK INTERNAL Figure 24 Safe Oscillator Function MAIN OSCILLATOR CLOCK SAFE OSCILLATOR CLOCK INTERNAL 32 125 4 3 2 Safe Oscillator Control The Safe Oscillator of the CSS block is a low fre quency back up clock source see Figure 24 If the clock signal disappears due to a broken or disconnected resonator during a Safe Oscillator period the Safe oscillator delivers a low frequency clock signal which allows the ST7 to perform some rescue operations Automatically the ST7 clock source switches back from the Safe Oscillator if the original clock source recovers Limitation detection The automatic Safe Oscillator selection is notified by hardware setting the CSSD bit of the CRSR register An interrupt can be generated if the CS SIE bit has been previously set These two bits are described in the CRSR register description 3 ST72334J N ST72314J N ST72124J 4 4 SUPPLY RESET AND CLOCK REGISTER DESCRIPTION CLOCK RESET AND SUPPLY REGISTER CRSR Read Write Reset Value 000x 000x 00h 7 0 LVD CSS CSS WDG RF IE D Bit 7 5 Reserved always read as 0 Bit 4 LVDRF LVD reset flag This bit indic
74. by a read to the DR register 0 No Overrun error 1 Overrun error is detected Note When this bit is set RDR register content will not be lost but the shift register will be overwritten Bit 2 NF Noise flag This bit is set by hardware when noise is detected on a received frame It is cleared by hardware when RE 0 by a software sequence an access to the SR register followed by a read to the DR regis ter 0 No noise is detected 1 Noise is detected Note This bit does not generate interrupt as it ap pears at the same time as the RDRF bit which it self generates an interrupt Bit 1 FE Framing error This bit is set by hardware when a de synchroniza tion excessive noise or a break character is de tected It is cleared by hardware when RE 0 by a software sequence an access to the SR register followed by a read to the DR register 0 No Framing error is detected 1 Framing error or break character is detected Note This bit does not generate interrupt as it ap pears at the same time as the RDRF bit which it self generates an interrupt If the word currently being transferred causes both frame error and overrun error it will be transferred and only the OR bit will be set Bit 0 Unused 91 125 ST72334J N ST72314J N ST72124J SERIAL COMMUNICATIONS INTERFACE Cont d CONTROL REGISTER 1 CR1 Read Write Reset Value Undefined 7 0 Bit 7 R8 Heceive data bit 8 This bit is used to store the 9th
75. ciated with three control and status registers and with six pairs of data registers 16 bit values relating to the two input captures the two output compares the counter and the al ternate counter CONTROL REGISTER 1 CR1 Read Write Reset Value 0000 0000 00h 7 0 ICIEJOCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL 1 Bit 7 ICIE nput Capture Interrupt Enable 0 Interrupt is inhibited 1 timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set Bit 6 OCIE Output Compare Interrupt Enable 0 Interrupt is inhibited 1 A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set Bit 5 TOIE Timer Overflow Interrupt Enable 0 Interrupt is inhibited 1 A timer interrupt is enabled whenever the TOF bit of the SR register is set ST72334J N ST72314J N ST72124J Bit 4 FOLV2 Forced Output Compare 2 This bit is set and cleared by software 0 No effect on the OCMP2 pin 1 Forces the OLVL2 bit to be copied to the 2 pin if the OC2E bit is set and even if there is no successful comparison Bit 3 FOLV1 Forced Output Compare 1 This bit is set and cleared by software 0 No effect on the pin 1 Forces OLVL 1 to be copied to the 1 pin if the OC1E bit is set and even if there is no suc cessful comparison Bit 2 OLVL2 Output Level 2 This bit is copied to the OCMP2 pin whenever a successful comparison occurs wi
76. connected to the timer So any transitions on these pins activate the input cap ture process 7 Moreover if one of the ICAP pin is configured as an input and the second one as an output an interrupt can be generated if the user toggle the output pin and if the ICIE bit is set 8 The TOF bit can be used with interrupt in order to measure event that go beyond the timer range FFFFh 57 125 ST72334J N ST72314J N ST72124J 16 BIT TIMER Cont d Figure 39 Input Capture Block Diagram Control Register 1 CR1 EDGE EDGE DETECT CIRCUIT2 CIRCUIT1 IC2R Register IC1R Register Status Register SR Control Register 2 CR2 TIT ileje COUNTER Figure 40 Input Capture Timing Diagram Timer clock COUNTER REGISTER U X o X XC ICAPi PIN uuu ICAPi FLAG REGISTER FF03 Note Active edge is rising edge 3 58 125 16 BIT TIMER Cont d 6 4 3 4 Output Compare In this section the index may be 1 or 2 This function can be used to control an output waveform or indicating when a period of time has elapsed When match is found between the Output Com pare register and the free running counter the out put compare function Assigns pins with a programmable value if the OCIE bit is set Sets a flag in the status register Generates an interrupt if enabled Two 16 bit registers Output Compare Register 1 OC1R and Output Compare Register
77. d and the interrupt request automatically cleared upon entering the interrupt service routine If several input pins connected to the same inter rupt vector are configured as interrupts their sig nals are logically ANDed before entering the edge level detection block Warning The type of sensitivity defined in the Miscellaneous or Interrupt register if available applies to the El source In case of an ANDed source as described on the ports section a low level on an I O pin configured as input with in terrupt masks the interrupt request even in case of rising edge sensitivity Peripheral Interrupts Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both The I bit of the CC register is cleared The corresponding enable bit is setin the control register If any of these two conditions is false the interrupt is latched and thus remains pending Clearing an interrupt request is done by writing 0 to the corresponding bit in the status register or an access to the status register while the flag is set followed by a read or write of an associated register Note the clearing sequence resets the internal latch A pending interrupt i e waiting for being en abled will therefore be lost if the clear sequence is executed 3 ST72334J N ST72314J N ST72124J INTERRUPTS Cont d Figure 26 Interrupt Processing Flowchart FR
78. d independently as digital input with or without interrupt generation or digital output 6 1 2 Functional Description Each port is associated to 2 main registers Data Register DR Data Direction Register DDR and one optional register Option Register OR Each may be programmed using the corre sponding register bits in DDR and OR registers bit X corresponding to pin X of the port The same cor respondence is used for the DR register The following description takes into account the OR register for specific port which do not provide this register refer to the I O Port Implementation section The generic block diagram is shown on Figure 32 Input Modes The input configuration is selected by clearing the corresponding DDR register bit In this case reading the DR register returns the digital value applied to the external pin Different input modes can be selected by software through the OR register Note1 Writing the DR register modifies the latch value but does not affect the pin status Note2 When switching from input to output mode the DR register has to be written first to drive the correct level on the pin as soon as the ports is con figured as an output External interrupt function When an is configured in Input with Interrupt an event on this can generate an external In terrupt request to the CPU Each pin can independently generate an Interrupt req
79. distinguished HALT main oscillator is turned off ACTIVE HALT only main oscillator is running The decision to enter either in HALT or ACTIVE HALT mode is given by the main oscillator enable interrupt flag OIE bit in CROSS MCCSR register see Table 7 When entering HALT modes the bit in the CC register is forced to 0 to enable interrupts The MCU can exit HALT or ACTIVE HALT modes on reception of an interrupt with Exit from Halt Mode capability or a reset See Table 6 page 37 A 4096 CPU clock cycles delay is performed be fore the CPU operation resumes see Figure 28 After the start up delay the CPU resumes opera tion by servicing the interrupt or by fetching the re set vector which woke it up Table 7 HALT Modes selection Power Saving Mode entered when HALT instruction is executed HALT reset if watchdog enabled 1 ACTIVE HALT no reset if watchdog enabled Figure 28 HALT ACTIVE HALT Modes timing overview HALT INSTRUCTION 38 125 FETCH VECTOR INTERRUPT 3 POWER SAVING MODES Cont d Standard HALT mode In this mode the main oscillator is turned off caus ing all internal processing to be stopped including the operation of the on chip peripherals All periph erals are not clocked except the ones which get their clock supply from another clock generator such as an external or auxiliary oscillator The compatibility of Watchdog operation with Halt mode is configured by
80. e data on the bus will not be latched If a programming cycle is interrupted by software RESET action the memory data will not be guar anteed READ OPERATION POSSIBLE WRITE CYCLE m EEPROM INTERRUPT 19 125 ST72334J N ST72314J N ST72124J DATA EEPROM Cont d 2 6 6 Register Description CONTROL STATUS REGISTER CSR Read Write Reset Value 0000 0000 00h 0 Bit 7 3 Reserved forced by hardware to 0 Bit 2 IE nterrupt enable This bitis set and cleared by software Itenables the Data EEPROM interrupt capability when the PGM bit is cleared by hardware The interrupt request is automatically cleared when the software enters the interrupt routine 0 Interrupt disabled 1 Interrupt enabled Bit 1 2 LAT Latch Access Transfer This bit is set by software It is cleared by hard ware at the end of the programming cycle It can only be cleared by software if PGM bit is cleared 0 Read mode 1 Write mode Bit 0 Programming control and status This bit is set by software to begin the programming cycle At the end of the programming cycle this bit is clearedby hardware and aninterrupt is generated if the ITE bit is set 0 Programming finished or not yet started 1 Programming cycle is in progress Note if the PGM bit is cleared during the program ming cycle the memory data is not guaranteed Table 3 DATA EEPROM Register Map and Reset Values Address Register Hex Label EECSR 002Ch
81. e LVD allows the device to be used without any exter nal RESET circuitry 2 three different reference levels are selectable through the OPTION BYTE according to the application require ment LVD application note Application software can detect a reset caused by the LVD by reading the LVDRF bit in the CRSR register This bit is set by hardware when a LVD reset is generated and cleared by software writing zero HYSTERESIS Vi vDhyst 25 125 ST72334J N ST72314J N ST72124J 4 2 RESET SEQUENCE MANAGER RSM The reset sequence manager includes three RE SET sources as shown in Figure 15 m EXTERNAL RESET SOURCE pulse m Internal LVD RESET Low Voltage Detection m Internal WATCHDOG RESET These sources act on the RESET PIN and it is al ways kept low during the delay phase The RESET service routine vector is fixed at ad dresses FFFEh FFFFh in the ST7 memory map The basic RESET sequence consists of 3 phases as shown in Figure 14 m Delay depending on the RESET source m 4096 CPU clock cycle delay m RESET vector fetch Figure 15 Reset Block Diagram 26 125 The 4096 CPU clock cycle delay allows the oscil lator to stabilise and ensures that recovery has taken place from the Reset state The RESET vector fetch phase duration is 2 clock cycles Figure 14 RESET Sequence Phases RESET DELAY INTERNAL RESET FETCH 4096 CLOCK CYCLES VECTOR INTERNAL RESET COUNTER WATCHDOG RESET LVD RE
82. e T Ts amp perse ee sse qe gt p px ree pe 7 z roov T X x x pr X e x rr AD Arto mone 8 0 ADC Analog Input 3 1x x Dope pr Poros O x rers pep Poran XX X Pon 07 ADC Analog iut 7 Power Supply Voltage LS 1 _ Analog Ground voes _____ Does 1101 voe ita Groune Vonage x X X Pon Fo Main dock ouput 198027 sper erres XX Pon Ft Beep signal ouipat IX EPI a vo Not Connected 5 Ej 10 125 3 ST72334J N ST72314J N ST72124J Main ss Alternate function after HHBHBBE Ee PFS HSCRP Tro es RS X TX T TT X Pon Timer A inp Capture 1 PET A VO x x Timer A External lock Source eine S TT CET a Pee gt _____ or X X X x Timer 8 Compare 2
83. e frame is complete This interface usestwo types ofbaud rate generator A conventional type for commonly used baud rates An extended type with a prescaler offering a very wide range of baud rates even with non standard oscillator frequencies 83 125 ST72334J N ST72314J N ST72124J SERIAL COMMUNICATIONS INTERFACE Cont d Figure 52 SCI Block Diagram DATA REGISTER DR E ved Shift Regi S S 553 pu ow b SESS WAKE TRANSMIT UP RECEIVER RECEIVER CONTROL UNIT CONTROL CLOCK zm i SCI INTERRUPT CONTROL TRANSMITTER CLOCK 84 125 437 ST72334J N ST72314J N 57721247 SERIAL COMMUNICATIONS INTERFACE Cont d 6 6 4 Functional Description The block diagram of the Serial Control Interface is shown in Figure 52 It contains 6 dedicated reg isters Two control registers CR1 amp CR2 A status register SR A baud rate register BRR An extended prescaler receiver register ERPR Anextendedprescalertransmitter register ETPR Refer to the register descriptions in Section 6 6 7for the definitions of each bit Figure 53 Word length programming 9 bit Word length M bit is set Data Frame 6 6 4 1 Serial Data Format Word length may be selected as being either 8 or 9 bits by programming the M bit in the CR1 register see Figure 52 The TDO pin is in low state during the start bit The TDO pin is in high state during the stop bit An Idle charac
84. eared by software and it is cleared by reset It is used with the SPR 1 0 bits to set the baud rate Refer to Table 16 0 Divider by 2 enabled 1 Divider by 2 disabled Bit 4 MSTR Master This bit is set and cleared by software It is also cleared by hardware when in master mode 55 0 see Section 6 5 4 5 Master Mode Fault 0 Slave mode is selected 1 Master mode is selected the function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are re versed 80 125 Bit 3 CPOL Clock polarity This bit is set and cleared by software This bit de termines the steady state of the serial Clock The CPOL bit affects both the master and slave modes 0 The steady state is a low value at the SCK pin 1 The steady state is a high value at the SCK pin Bit 2 CPHA Clock phase This bit is set and cleared by software 0 The first clock transition is the first data capture edge 1 The second clock transition is the first capture edge Bit 1 0 SPR 1 0 Serial peripheral rate These bits are set and cleared by software Used with the SPR2 bit they select one of six baud rates to be used as the serial clock when the device is a master These 2 bits have no effect in slave mode Table 16 Serial Peripheral Baud Rate Clock SPR SPAT 520 wu ew 91919 10 0 t 3
85. ed 1 Interrupts are disabled This bit is controlled by the RIM SIM and IRET in structions and is tested by the JRM and JRNM in structions Note Interrupts requested while is set are latched and be processed when 1 is cleared By default an interrupt routine is not interruptable because the bit is set by hardware when you ter it and reset by the IRET instruction at the end of the interrupt routine If the bit is cleared by soft ware the interrupt routine pending interrupts serviced regardless of the priority level of the cur rent interrupt routine 22 125 Bit 2 Negative This bit is set and cleared by hardware It is repre sentative of the result sign of the last arithmetic logical or data manipulation It is a copy of the 7 bit of the result 0 The result of the last operation is positive or null 1 The result of the last operation is negative i e the most significant bit is a logic 1 This bit is accessed by the JRMI and JRPL instruc tions Bit 1 2 Z Zero This bit is set and cleared by hardware This bit in dicates that the result of the last arithmetic logical or data manipulation is zero 0 The result of the last operation is different from Zero 1 The result of the last operation is zero This bit is accessed by the JREQ and JRNE test instructions Bit 0 C Carry borrow This bit is set and cleared by hardware and soft ware It indicates an overflo
86. egins searching for a start bit When a character is received The bit is set It indicates that the content of the shift register is transferred to the RDR An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register The error flags can be set if a frame error noise or an overrun error has been detected during re ception Clearing the RDRF bit is performed by the following software sequence done by 1 An access to the SR register 2 A read to the DR register The bit must be cleared before the end of the reception of the next character to avoid an overrun error Break Character When a break character is received the SPI han dles it as a framing error Idle Character When idle frame is detected there is the same procedure as a data received character plus an in terrupt if the bit is set and the bit is cleared in the CCR register ST72334J N ST72314J N ST72124J Overrun Error An overrun error occurs when a character is re ceived when RDRF has not been reset Data can not be transferred from the shift register to the register as long as the bit is not cleared When overrun error occurs The OR bit is set The RDR content will not be lost The shift register will be overwritten Aninterrupt is generated if the RIE bitis set and the bit is cleared in the CCR register The OR bit is r
87. egister Notes To avoid any multiple slave conflicts in the case of a system comprising several MCUs the SS pin must be pulled high during the clearing se quence of the MODF bit The SPE and MSTR bits ST72334J N ST72314J N ST72124J may be restored to their original state during or af ter this clearing sequence Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence In a slave device the MODF bit can not be set but in a multi master configuration the device can be in slave mode with this MODF bit set The MODF bit indicates that there might have been amulti master conflict for system control and allows a proper exit from system operation to a re set or default system state using an interrupt rou tine 6 5 4 6 Overrun Condition An overrun condition occurs when the master de vice has sent several data bytes and the slave de vice has not cleared the SPIF bit issuing from the previous data byte transmitted In this case the receiver buffer contains the byte sent after the SPIF bit was last cleared A read to the DR register returns this byte All other bytes are lost This condition is not detected by the SPI peripher al 77 125 ST72334J N ST72314J N ST72124J SERIAL PERIPHERAL INTERFACE Cont d 6 5 4 7 Single Master and Multimaster Configurations There are two types of SPI systems Single Master System Multimast
88. ence The transmit sequence begins when a byte is writ ten the DR register The data byte is parallel loaded into the 8 bit shift register from the internal bus during a write cycle and then shifted out serially to the MOSI pin most significant bit first When data transfer is complete The SPIF bit is set by hardware An interrupt is generated if the SPIE bit is set and the I bit in the CCR register is cleared During the last clock cycle the SPIF bit is set a copy of the data byte received in the shift register is moved to a buffer When the DR register is read the SPI peripheral returns this buffered value Clearing the SPIF bit is performed by the following software sequence 1 An access to the SR register while the SPIF bit is set 2 A write or a read of the DR register Note While the SPIF bit is set all writes to the DR register are inhibited until the SR register is read 4 SERIAL PERIPHERAL INTERFACE 6 5 4 2 Slave Configuration In slave configuration the serial clock is received on the SCK pin from the master device The value of the SPRO amp SPR1 bits is not used for the data transfer Procedure For correct data transfer the slave device must be in the same timing mode as the mas ter device CPOL and CPHA bits See Figure 49 The SS pin must be connected to a low level signal during the complete byte transmit se quence Clear the MSTR bit and set the SPE b
89. er System Single Master System A typical single master system may be configured using an MCU as the master and four MCUs as slaves see Figure 51 The master device selects the individual slave de vices by using four pins of a parallel port to control the four SS pins of the slave devices The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time thus disabling the slave devices Note To prevent a bus conflict on the MISO line the master allows only one slave device during a transmission Figure 51 Single Master Configuration For more security the slave device may respond to the master with the received data byte Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are con nected and the slave has not written its DR regis ter Other transmission security methods can use ports for handshake lines or data bytes with com mand fields Multi master System A multi master system may also be configured by the user Transfer of master control could be im plemented using a handshake method through the ports or by an exchange of code messages through the serial peripheral interface system The multi master system is principally handled by the MSTR bit in the CR register and the MODF bit in the SR register 78 125 3 ST72334J N ST72314J N ST72124J SERIAL PERIPHERAL INTERFACE 6 5 5 Low Powe
90. erface between the internal bus and the output shift reg ister see Figure 52 The RDR register provides the parallel interface between the input shift register and the internal bus see Figure 52 BAUD RATE REGISTER BRR Read Write Reset Value 00xx xxxx XXh 7 0 Bit 7 62 SCP 1 0 First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges ST72334J N ST72314J N ST72124J Bit 5 3 SCT 2 0 SC Transmitter rate divisor These 3 bits in conjunction with the SCP1 amp SCPO bits define the total division applied to the bus clock to yield the transmit rate clock in convention al Baud Rate Generator mode pm qe Lo op 1 Lo Note this TR factor is used only when the ETPR fine tuning factor is equal to 00h otherwise TR is replaced by the ETPR dividing factor Bit 2 0 SCR 2 0 SC Receiver rate divisor These 3 bits in conjunction with the SCP1 amp SCPO bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode RR dividi factor SCR2 SCR1 SCRO Note this RR factor is used only when the ERPR fine tuning factor is equal to 00h otherwise RR is replaced by the ERPR dividing factor 93 125 ST72334J N ST72314J N ST72124J SERIAL COMMUNICATIONS INTERFACE Cont d EXTENDED RECEIVE PRESCALER DIVISION REGISTER ERPR Read Write Reset Value 00
91. eset by an access to the SR register followed by a DR register read operation Noise Error Oversampling techniques are used for data recov ery by discriminating between valid incoming data and noise When noise is detected in a frame The NF 15 set at the rising edge of the RDRF bit Data is transferred from the Shift register to the DR register No interrupt is generated However this bit rises at the same time as the bit which itself generates an interrupt The NF bit is reset by a SR register read operation followed by a DR register read operation Framing Error A framing error is detected when The stop bit is not recognized on reception at the expected time following either a de synchroni zation or excessive noise A break is received When the framing error is detected the FE bit is set by hardware Data is transferred from the Shift register to the DR register No interrupt is generated However this bit rises at the same time as the RDRF bit which itself generates an interrupt The FE bit is reset by a SR register read operation followed by a DR register read operation 87 125 ST72334J N ST72314J N ST72124J SERIAL COMMUNICATIONS INTERFACE Cont d Figure 54 SCI Baud Rate and Extended Prescaler Block Diagram TRANSMITTER SCPOSCT2 SCT1 SCTO SCRO RECEIVER 88 125 3 ST72334J N ST72314J N ST72124J SERIAL COMMUNICATIONS INTERFACE Cont d 6 6
92. gister is enough to se lect the I O pin configuration The OR register allows to distinguish in input mode if the pull up with interrupt capability or the basic pull up configuration is selected in output mode if the push pull or open drain configuration is selected Each bit is set and cleared by software Input mode 0 floating input 1 pull up input with or without interrupt Output mode 0 output open drain with P Buffer unactivated 1 output push pull 45 125 ST72334J N ST72314J N ST72124J PORTS Cont d Table 10 I O Port Register and Reset Values 5 SAEs ES Label PIC CNEERENENENENEN of all IO eae registers PADR vs 0010h 0011h PDDDR 0012h 0015h PFDDR Notes 1 The bits corresponding to unavailable pins are forced to 1 by hardware this affects the reset status value 46 125 3 6 2 MISCELLANEOUS REGISTERS The miscellaneous registers allow control over several different features such as the external in terrupts or the I O alternate functions 6 2 1 Port Interrupt Sensitivity Description The external interrupt sensitivity is controlled by the ISxx bits of the MISCR1 miscellaneous regis ter This control allows to have two fully independ ent external interrupt source sensitivities Each external interrupt source can be generated on four different events on the pin m Falling edge m R
93. given by the following table RESET Sources LVDRF WDGRF External RESET pin o Application notes In case the LVDRF flag is not cleared upon anoth er RESET type occurs extern or watchdog the LVDRF flag remains set to keep trace of the origi nal failure In this condition a watchdog reset can be detect ed by the software while an external reset not Table 4 Clock Reset and Supply Register Map and Reset Values Address Register Hex Label CRSR Reset Value LVDRF CFIE CSSD WDGRF x 0 0 X 33 125 ST72334J N ST72314J N ST72124J 4 5 MAIN CLOCK CONTROLLER MCC The MCC block supplies the clock for the ST7 CPU its internal peripherals It allows to man age the power saving modes such as the SLOW and ACTIVE HALT modes The whole functionali is managed by the Main Clock Control Status Register MCCSR and the Miscellaneous Regis ter 1 MISCR1 The MCC block consists of a programmable CPU clock prescaler atime base counter with interrupt capability clock out signal to supply external devices The prescaler allows to select the main clock fre quency and is controlled with three bits of the MISCR1 CP1 and SMS The counter allows to generate an interrupt based on a accurate real time clock Four different time bases depending directly on fosc are available The whole functionality is controlled by four bits of the MCCSR register
94. he I O configuration To guarantee safe op eration this connection has be done through a pull up or pull down resistor 10KQ typical Thermal Characteristics Package thermal resistance TQFP64 SDIP56 TQFP44 SDIP42 Storage temperature range 65 to 150 S 105 125 ST72334J N ST72314J N ST72124J 8 2 RECOMMENDED OPERATING CONDITIONS GENERAL Supply voltage see Figure 58 Vpp gt 3 5V Resonator oscillator frequency LT ______ _ 2 fosc JEwemalcocksouce Tswv _ _ 8 Ambient temperature am version SSuikVeson o Figure 58 fosc Maximum Operating Frequency Versus Supply Voltage FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONALITY GUARANTEED IN THIS AREA fosc FUNCTIONALITY NOT GUARANTEED IN THIS AREA MHz FOR TEMPERATURE HIGHER THAN 85 C SUPPLY VOLTAGE V 5 5 FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR Notes 1 Unless otherwise specified typical data are based on 25 and Vpp Vss 5V They are given only as design guide lines and are not tested 2 A D operation and resonator oscillator start up are not guaranteed below 1MHz 3 Operating conditions 40 to 85 C The shaded area is outside the recommended operating range device func tionality is not guaranteed under these conditions 106 125 3 ST72334J N ST72314J N 57721247 8 3 DC EL
95. he SCK pin falling edge if the CPOL bit is reset rising edge if the CPOL bit is set is the MSBit capture strobe Data is latched on the occurrence of the first clock transition No write collision should occur even if the SS pin stays low during a transfer of several bytes see Figure 48 CPHA bit is reset The firstedge on the SCK pin falling edge if CPOL bit is set rising edge if CPOL bit is reset is the MSBit capture strobe Data is latched on the oc currence of the second clock transition This pin must be toggled high and low between each byte transmitted see Figure 48 To protect the transmission from a write collision a low value on the SS pin of a slave device freezes the data in its DR register and does not allow it to be altered Therefore the SS pin must be high to write a new data byte in the DR without producing a write collision Slave SS CPHA SA Slave SS CPHA 1 VR02131A 74 125 4 ST72334J N ST72314J N ST72124J SERIAL PERIPHERAL INTERFACE Cont d Figure 49 Data Clock Timing Diagram Note This figure should not be used as a replacement for parametric information Refer to the Electrical Characteristics chapter VR02131B r 75 125 ST72334J N ST72314J N ST72124J SERIAL PERIPHERAL INTERFACE Cont d 6 5 4 4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is tak ing place w
96. he op code 7 1 5 Indirect Short Long The required data byte to do the operation is found by its memory address located in memory point er The pointer address follows the opcode The indi rect addressing mode consists of two sub modes Indirect short The pointer address is a byte the pointer size is a byte thus allowing 00 FF addressing space and requires 1 byte after the opcode Indirect long The pointer address is a byte the pointer size is a word thus allowing 64 Kbyte addressing space and requires 1 byte after the opcode r ST7 ADDRESSING MODES Cont d 7 1 6 Indirect Indexed Short Long This is a combination of indirect and short indexed addressing modes The operand is referenced by its memory address which is defined by the un signed addition of an index register value X or Y with a pointer value located in memory The point er address follows the opcode The indirect indexed addressing mode consists of two sub modes Indirect Indexed Short The pointer address is a byte the pointer size is a byte thus allowing 00 1FE addressing space and requires 1 byte after the opcode Indirect Indexed Long The pointer address is a byte the pointer size is a word thus allowing 64 Kbyte addressing space and requires 1 byte after the opcode Table 21 Instructions Supporting Direct Indexed Indirect Indirect Indexed Addressing Modes Instructions ADC ADD SUB SBC Ar
97. ifferent memory access modes Read Operation LAT 0 The EEPROM can be read as a normal ROM loca tion when the LAT bit of the EECSR register is cleared In a read cycle the byte to be accessed is put on the data bus in less than 1 CPU clock cycle This means that reading data from EEPROM takes the same time as reading data from EPROM but this memory cannot be used to exe cute machine code Write Operation LAT 1 To access the write mode the LAT bit has to be set by software the PGM bit remains cleared When a write access to the EEPROM area occurs the value is latched inside the 16 data latches ac cording to its address Figure 8 Data EEPROM Programming Flowchart READ MODE INTERRUPT GENERATION IF 1 1 When bit is set by the software all the previ ous bytes written in the data latches up to 16 are programmed in the EEPROM cells The effective high address row is determined by the last EEP ROM write sequence To avoid wrong program ming the user must take care that all the bytes written between two programming sequences have the same high address only the four Least Significant Bits of the address can change At the end of the programming cycle the PGM and LAT bits are cleared simultaneously and an inter rupt is generated if the IE bitis set The Data EEP ROM interrupt request is cleared by hardware when the Data EEPROM interrupt vector is fetched Note Care should be taken during the pr
98. imum current injection on four 1 O port pins of the device 8 To generate an external interrupt minimum pulse width has to be applied on an I O port pin configured as an external interrupt source 3 108 125 ST72334J N ST72314J N ST72124J 8 6 SUPPLY RESET AND CLOCK CHARACTERISTICS 8 6 1 Supply Manager Recommended operating conditions with 40 to 85 C and voltage are referred to Vas unless otherwise specified LOW VOLTAGE DETECTOR LVD Reset release threshold High Threshold 4 30 4 50 Vpop rise Med Threshold lt 16 2 3 90 4 05 DD Low Threshold lt 8 2 3 35 3 45 Reset generation threshold High Threshold 3 85 4 05 4 25 VLvof V fall Med Threshold lt 16 3 50 3 65 3 80 BB Low Threshold lt 8 3 00 3 10 3 20 Hysteresis ___ 257 ino 1 0 Supply Current HALT mode 1507 w 8 6 2 Reset Sequence Manager Recommended operating conditions with T 40 85 C and 4 5V Vpp Vss 5 5V unless otherwise specified RESET SEQUENCE MANAGER RSM Vin gt Be E t Reset delay for external and 1 fgFosc DELAYmin watchdog reset sources M us Enema RESET pn Pusei 2 8 6 3 Multi Oscillator Clock Security System Recommended operating conditions with 40 to 85 C and voltage are referred to Vs
99. ing external events on the OCMP pins even if the input capture mode is also used 5 The value in the 16 bit register and the OLVi bit should be changed after each suc cessful comparison in order to control an output waveform or establish a new elapsed timeout 59 125 ST72334J N ST72314J N ST72124J 16 BIT TIMER Cont d Figure 41 Output Compare Block Diagram 16 BIT FREE RUNNING COUNTER INTERNAL CPU CLOCK TIMER CLOCK COUNTER OUTPUT COMPARE REGISTER OUTPUT COMPARE FLAG OCFi OCMPi PIN OLVLi 1 INTERNAL CPU CLOCK TIMER CLOCK COUNTER OUTPUT COMPARE REGISTER COMPARE REGISTER LATCH OCFi AND OCMPi PIN OLVLi 1 60 125 Pls Control Register 2 CR2 Control Register 1 CR1 4 16 BIT TIMER 6 4 3 5 Forced Compare In this section may represent 1 or 2 The following bits of the CR1 register are used FOLV2 FOLV1 OLVL2 OLVL1 When the FOLVi bit is set by software the OLVLi bit is copied to the OCMP pin The OLVi bit has to be toggled in order to toggle the pin when it is enabled bit 1 The OCFi bitis then not set by hardware and thus no interrupt request is generated FOLVLi bits have no effect in both one pulse mode and PWM mode 6 4 3 6 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs This mode is selected via the OPM bit in the CR2 register The one pulse mode uses the Inpu
100. ins devices for protecting the in Power Considerations The average chip junc puts against damage due to high static voltages tion temperature Ty in Celsius can be obtained however it is advisable to take normal precautions from to applying higher than the TA PD x RIhJA maximum rated voltages Where Ta Ambient Temperature For proper operation it is recommended that Vj RthJA thermal resistance and Vo be higher than and lower than Vpp junction to ambient Reliability is enhanced if unused inputs are con Pp Pint nected to an appropriate logic voltage level Pint lpp X Vpp chip internal power or Port power dissipation determined by the user Supply volage Analog reference voltage Vssa Visas V V i Vp Max variations power line 50 mV i IVss Vssal Note Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating con ditions for extended periods may affect device reliability General Warning Directly connecting the RESET and I O pins to Vpp or Vgs could damage the device if an unintentional internal reset is generated or the program counter is corrupted by an expected change to t
101. interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack Note As a consequence of the IRET instruction the bit will be cleared and the main program will resume Priority management By default the interrupt being serviced cannot be interrupted because the bit is set by hardware when entering an interrupt routine If several interrupts are simultaneously pending a hardware priority defines which one will be serv iced first see the Interrupt Mapping Table Non Maskable Software Interrupts This interrupt is entered when the TRAP instruc tion is executed regardless of the state of the bit It will be serviced according to the flowchart on Figure 26 Interrupts and Low power mode All interrupts allow the processor to leave the Wait low power mode Only external and specific men tioned interrupts allow the processor to leave the 36 125 Halt low power mode refer to the Exit from HALT column in the Interrupt Mapping Table External Interrupts External interrupt vectors can be loaded in the PC register if the corresponding external interrupt oc curred and if the bit is cleared These interrupts allow the processor to leave the Halt low power mode The external interrupt polarity is selected through the miscellaneous register or interrupt register if available External interrupt triggered on edge will be latche
102. ion results not tested 4 Data based on characterization results not tested in production 5 Positive injection The lings is performed protection diodes insulated from the substrate of the die The true open drain pins do not accept positive AGE In this case the maximum voltage rating must be respected 6 ADC accuracy reduced by negative injection The liy is performed through protection diodes INSULATED from the substrate of the die The drawback is a small leakage a few uA induced inside the die when a negative injection is performed This leakage is tolerated by the digital structure but it acts on the analog line depending on the impedance versus a leakage current of a few uA if the MCU has an AD converter The effect depends on the pin which is submitted to the injection Of course external digital signals applied to the component must have a maximum impedance close to 50K Location of the negative current injection Pins with analog input capability are the most sensitive lj maximum is 0 8 mA assuming that the impedance of the analog voltage is lower than 25K OQ Pure digital pins can tolerate 1 6mA In addition the best choice is to inject the current as far as possible from the analog input pins 7 When several inputs are submitted to a current injection the maximum is the sum of the positive or negative cur rents instantaneous values These results are based on characterisation with liy max
103. ising edge m Falling and rising edge m Falling edge and low level To guarantee correct functionality the sensitivity bits in the MISCR1 register must be modified only when the bit of the CC register is set to 1 inter rupt masked See I O port register and Miscella neous register descriptions for more details on the programming ST72334J N ST72314J N ST72124J 6 2 2 I O Port Alternate Functions MISCR registers manage four I O port miscel laneous alternate functions m Main clock signal output on PFO m beep signal output on with selectable audio frequencies m SPI pin configuration SS pin internal control to use the PC7 I O port function while the SPI is active These functions are described in detail in the Sec tion 6 2 3 Miscellaneous Registers Description 47 125 ST72334J N ST72314J N ST72124J MISCELLANEOUS REGISTERS 6 2 3 Miscellaneous Registers Description MISCELLANEOUS REGISTER 1 MISCR1 Read Write Reset Value 0000 0000 00h 7 0 TIT Bit 7 6 IS1 1 0 E 2 and EIS sensitivity The interrupt sensitivity defined using the IS1 1 0 bits is applied to the following external interrupts EI2 port B3 0 and EI3 port B7 4 These 2 bits can be written only when the bit of the CC register is setto 1 interrupt disabled 510 External Interrupt Sensitivity Faling edge 8 Towie L1 rating edge only Bit 5
104. it to as sign the pins to alternate function In this configuration the MOSI pin is a data input and the MISO pin is a data output Transmit Sequence The data byte is parallel loaded into the 8 bit shift register from the internal bus during a write cycle and then shifted out serially to the MISO pin most significant bit first The transmit sequence begins when the slave de vice receives the clock signal and the most signifi cant bit of the data on its MOSI pin ST72334J N ST72314J N ST72124J When data transfer is complete The SPIF bit is set by hardware An interrupt is generated if SPIE bit is set and bitin CCR register is cleared During the last clock cycle the SPIF bit is set a copy of the data byte received in the shift register is moved to a buffer When the DR register is read the SPI peripheral returns this buffered value Clearing the SPIF bit is performed by the following software sequence 1 An access to the SR register while the SPIF bit is set 2 A write or a read of the DR register Notes While the SPIF bit is set all writes to the DR register are inhibited until the SR register is read The SPIF bit can be cleared during a second transmission however it must be cleared before the second SPIF bit in order to prevent an overrun condition see Section 6 5 4 6 Depending on the CPHA bit the SS pin has to be set to write to the DR register between each data byte transfer
105. ith ADON set aborts the current conversion resets the COCO bit and starts a new conversion Figure 57 ADC Conversion Timings ADCCSR WRITE OPERATION HOLD CONTROL _ e ds _ 6 7 4 5 Note The A D converter be disabled by setting the ADON bit This feature allows reduced power consumption when no conversion is need ed and between single shot conversions Mode Description WAIT No effect on A D Converter A D Converter disabled After wakeup from Halt mode the A D HALT Converter requires a stabilisation time before accurate conversions can be performed 6 7 5 Interrupts None 3 8 BIT A D CONVERTER ADC 6 7 6 Register Description CONTROL STATUS REGISTER CSR Read Write Reset Value 0000 0000 00h ST72334J N ST72314J N ST72124J DATA REGISTER DR Read Only Reset Value 0000 0000 00h 7 0 7 0 Bit 7 Conversion Complete This bit is set by hardware It is cleared by soft ware reading the result in the DR register or writing to the CSR register 0 Conversion is not complete 1 Conversion can be read from the DR register Bit 6 Reserved must always be cleared Bit 5 ADON A D Converter On This bit is set and cleared by software 0 A D converter is switched off 1 A D converter is switched on Bit 4 Reserved must always be cleared Bit 3 0 CH 3 0 Channel Selection These bits are set and clea
106. ith an external device When this hap pens the transfer continues uninterrupted and the software write will be unsuccessful Write collisions can occur both in master and slave mode Note a read collision will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU oper ation In Slave mode When the CPHA bit is set The slave device will receive a clock SCK edge prior to the latch of the first data transfer This first clock edge will freeze the data in the slave device DR register and output the MSBit on to the exter nal MISO pin of the slave device The SS pin low state enables the slave device but the output of the MSBit onto the MISO pin does not take place until the first data transfer clock edge When the CPHA bit is reset Data is latched on the occurrence of the first clock transition The slave device does not have any way of knowing when that transition will occur therefore the slave device collision occurs when software attempts to write the DR register after its SS pin has been pulled low For this reason the SS pin must be high between each data byte transfer to allow the CPU to write in the DR register without generating a write colli sion In Master mode Collision in the master device is defined as a write of the DR register while the internal serial clock SCK is in the process of transfer The SS pin signal must be always high on
107. ithmetic Addition subtrac tion operations Short Instructions Only Function BTJT BTJF Bit Test and Jump Opera tions son Shift and Rotate Operations SWAP Swap Nibbles CALL JP Call or Jump subroutine ST72334J N ST72314J N ST72124J 7 1 7 Relative mode Direct Indirect This addressing mode is used to modify the PC register value by adding an 8 bit signed offset to it Available Relative Direct Indirect Instructions CALLR Call Relative The relative addressing mode consists of two sub modes Relative Direct The offset is following the opcode Relative Indirect The offset is defined in memory which address follows the opcode 101 125 ST72334J N ST72314J N ST72124J 7 2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions The instructions may be subdivided into 18 main groups as illustrated in the following table Sa sra itc Tnnc s management TRAP wer rnc pier _ Gode Condon sim se Using pre byte The instructions are described with one to four bytes In order to extend the number of available op codes for an 8 bit CPU 256 opcodes three differ ent prebyte opcodes are defined These prebytes modify the meaning of the instruction they pre cede The whole instruction becomes PC 2 End of previous instruction PC 1 Prebyte P
108. lost The stack also wraps in case of an under flow The stack is used to save the return address dur ing a subroutine call and the CPU context during an interrupt The user may also directly manipulate the stack by means of the PUSH and POP instruc tions In the case of an interrupt the PCL is stored at the first location pointed to by the SP Then the other registers are stored in the next locations as shown in Figure 11 When interrupt is received the SP is decre mented and the context is pushed on the stack return from interrupt the SP is incremented and the context is popped from the stack A subroutine call occupies two locations and an in terrupt five locations in the stack area 23 125 ST72334J N ST72314J N ST72124J 4 SUPPLY RESET AND CLOCK MANAGEMENT The ST72334J N ST72314J N and ST72124J mi crocontrollers include a range of utility features for securing the application in critical situations for example in case of a power brown out and re Reset Sequence Manager RSM Multi Oscillator MO 4 Crystal Ceramic resonator oscillators ducing the number of external components An 1 External RC oscillator overview is shown in Figure 12 1 Internal RC oscillator Main Features m Clock Suy System CSS m Supply Manager with Main supply Low voltage OER Filar detection LVD Backup Safe Oscillator Figure 12 Clock Reset and Supply Block Diagram CLOCK SECURITY SYSTEM C
109. more than a defined delay in this power saving mode HALT INSTRUCTION MAIN OSCILLATOR OIE BIT OSCILLATOR PERIPHERALS CPU BIT 4096 clock cycles delay OSCILLATOR PERIPHERALS CPU External interrupt or internal interrupts with Exit from Halt Mode capability Before servicing an interrupt the CC register is pushed on the stack 39 125 ST72334J N ST72314J N ST72124J POWER SAVING MODES Cont d 5 2 3 WAIT Mode WAIT mode places the MCU in a low power con sumption mode by stopping the CPU This power saving mode is selected by calling the WFI ST7 software instruction All peripherals remain active During WAIT mode the I bit of the CC register is forced to 0 to enable all interrupts All other registers and memory re main unchanged The MCU remains in WAIT Figure 30 WAIT mode flow chart OSCILLATOR BIT OSCILLATOR PERIPHERALS CPU Note mode until an interrupt or Reset occurs whereup on the Program Counter branches to the starting address of the interrupt or Reset service routine The MCU will remain in WAIT mode until a Reset or an Interrupt occurs causing it to wake up Refer to Figure 30 if exit caused by a RESET a 4096 CPU clock cycle delay is inserted OSCILLATOR PERIPHERALS CPU FETCH RESET VECTOR OR SERVICE INTER RUPT The peripheral clock is stopped only when exit caused by RESET and not by an interrupt Before servicing an interrupt the
110. mponents Figure 21 MO External RC ST7 OSC2 Note ST72334J N ST72314J N ST72124J Internal RC Oscillator The Internal RC oscillator mode is based on the same principle as the External RC oscillator in cluding the resistance and the capacitance of the device This mode is the most cost effective one with the drawback of a lower frequency accuracy Its frequency is in the range of several MHz In this mode the two oscillator pins have to be tied to ground as shown in Figure 22 The selection of the internal RC oscillator has to be done by OPTION BYTE Figure 22 MO Internal RC ST7 5 1 OSC2 1 This formula provides an approximation of the frequency with typical Rex and Cex values at Vpp 5V It is given only as design guidelines 31 125 ST72334J N ST72314J N ST72124J 4 3 CLOCK SECURITY SYSTEM CSS The Clock Security System CSS protects the ST7 against main clock problems To allow the in tegration of the security features in the applica tions itis based on a clock filter control and an In ternal Safe Oscillator The CSS can be disabled by OPTION BYTE 4 3 1 Clock Filter Control The Clock Filter is based on a clock frequency lim itation function This filter function is able to detect and filter high frequency spikes on the ST7 main clock If the oscillator is not working properly e g work ing at a harmonic frequency of the resonator the current active oscillator clock can
111. n 70 6 5 4 Functional Description 72 655 Low Power RR PLE AREE d Red n 79 6 5 6 eri PEGE eee eee 79 6 5 7 Register Description 80 6 6 SERIAL COMMUNICATIONS INTERFACE SCI 83 66 1 INtTFOGUCHON es ie Bee oe 83 6 6 2 Main Features eee ees 83 6 6 3 General Description 83 6 6 4 Functional Description 85 6 6 5 Low Power Modas i isses oe vane bob eee RURAL gt 90 6 6 6 lnterrupts 2 5 coh RR nexu RERO ERR EGG E E RE UTE 90 6 6 7 Register Description 91 6 7 8 BIT A D CONVERTER 95 6 7 1 IntrOdUCHON 222222522 Rer bee a vee ees 95 6 7 2 Main Features dated tee Had awe AER Oe Rap debts 95 6 7 3 Functional Description 95 6 7 4 Low Power Modes 96 6 5 nterr pts expeti
112. nce activated it cannot be disabled except by areset The T6 bit can be used to generate a software re set the WDGA bit is set and the T6 bit is cleared If the watchdog is activated the HALT instruction will generate a Reset 6 3 4 Hardware Watchdog Option If Hardware Watchdog Is selected by option byte the watchdog is always active and the WDGA bit in the CR is not used Refer to the device specific Option Byte descrip tion 6 3 5 Low Power Modes No effect on Watchdog Immediate reset generation as soon as the HALT instruction is executed if the Watchdog is activated WDGA bit is set 6 3 6 Interrupts None ST72334J N ST72314J N ST72124J 6 3 7 Register Description CONTROL REGISTER CR Read Write Reset Value 0111 1111 7Fh 7 0 Bit 7 WDGA Activation bit This bit is set by software and only cleared by hardware after a reset When WDGA 1 the watchdog can generate a reset 0 Watchdog disabled 1 Watchdog enabled Note This bit is not used if the hardware watch dog option is enabled by option byte Bit 6 0 T 6 0 7 bit timer MSB to LSB These bits contain the decremented value A reset is produced when it rolls over from 40h to 3Fh T6 becomes cleared STATUS REGISTER SR Read Write Reset Value 0000 0000 00h 7 0 Bit 0 WDOGF Watchdog flag This bit is set by a watchdog reset and cleared by software or a power on off reset This bit is u
113. nced instruc tion set Figure 1 Device Block Diagram Internal CLOCK PD7 0 8 bits for N versions 6 bits for J versions CONTROL AND LVD 8 BIT CORE ALU PROGRAM MEMORY 8 or 16K Bytes Data EEPROM 256 Bytes 6 125 gt D m n n gt gt gt n The ST72C334J N ST72C314J N and ST72C124J versions feature single voltage FLASH memory with byte by byte In Situ Pro gramming ISP capability Under software control all devices can be placed in WAIT SLOW ACTIVE HALT or HALT mode reducing power consumption when the application is in idle or standby state The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers enabling the design of highly efficient and compact application code In addition to standard 8 bit data management all ST7 micro controllers feature true bit manipulation 8x8 un signed multiplication and indirect addressing modes 8 bits for N versions 5 bits for J versions 8 bits for N versions 5 bits for J versions PC7 0 8 bits 6 bits for N versions 2 bits for J versions 384 or 512 Bytes 4 ST72334J N ST72314J N ST72124J 2 2 PIN DESCRIPTION Figure 2 64 Pin TQFP Package Pinout N versions TDO 1 Vss 1 Vpp 1 2 1 7 55 6 ISPCLK PC5 5 PC4 MISO ISPDATA PC3 HS I
114. ode Pulse Width Modulation PWM mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers The pulse width modulation mode uses the com plete Output Compare 1 function plus the OC2R register and so these functionality can not be used when the PWM mode is activated Procedure To use pulse width modulation mode 1 Load the OC2R register with the value corre sponding to the period of the signal 2 Load the register with the value corre sponding to the length of the pulse if 1 0 OLVL2 1 3 Select the following in the CR1 register Using the OLVL 1 bit select the level to be ap plied to the OCMP1 pin after a successful comparison with OC1R register Using the OLVL2 bit select the level to be ap plied to the 1 pin after a successful comparison with OC2R register 4 Select the following in the CR2 register Set bit the pin is then dedicat ed to the output compare 1 function Set the PWM bit Select the timer clock CC1 CCO see Table 14 Clock Control Bits If OLVL1 1 and OLVL2 0 the length of the tive pulse is the difference between the OC2R and OC1R registers If OLVL1 OLVL2 a continuous signal will be seen on the pin The register value required for a specific tim ing application can be calculated using the follow ing formula t f
115. ogram ming cycle Writing to the same memory location will over program the memory logical AND be tween the two write access data result because the data latches are only cleared at the end of the programming cycle and by the falling edge of LAT bit It is not possible to read the latched data This note is ilustrated by the Figure 9 WRITE MODE 1 PGM 0 WRITE UP TO 16 BYTES EEPROM AREA with the same 12 MSB of the address START PROGRAMMING CYCLE LAT 1 1 set by software CLEARED BY 18 125 3 DATA EEPROM Cont d 2 6 4 Data EEPROM and Power Saving Modes Wait mode The DATA EEPROM can enter WAIT mode on ex ecution of the WFI instruction of the microcontrol ler The DATA EEPROM will immediately enter this mode if there is no programming in progress otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode Halt mode The DATA EEPROM immediatly enters HALT mode if the microcontroller executes the HALT in struction Therefore the EEPROM will stop the function in progress and data may be corrupted Figure 9 Data EEPROM Programming Cycle READ OPERATION NOT POSSIBLE INTERNAL PROGRAMMING VOLTAGE ERASE CYCLE WRITE OF DATA LATCHES ST72334J N ST72314J N ST72124J 2 6 5 Data EEPROM Access Error Handling If a read access occurs while LAT 1 then the data bus will not be driven If a write access occurs while LAT 0 then th
116. on are subject to change without notice This publication supersedes and replaces all information previously supplied S TMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics All Rights Reserved Purchase of Components by STMicroelectronics conveys a license under the Philips Patent Rights to use these components an 12 system is granted provided that the system conforms to the Standard Specification as defined by Philips STMicroelectronics Group of Companies Australia Brazil China Finland France Germany Hong Kong India Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom U S A http www st com 125 125 WWW ALLDATASHEET COM Copyright Each Manufacturing Company Datasheets cannot be modified without permission This datasheet has been download from www AllDataSheet com 100 Free DataSheet Search Site Free Download No Register Fast Search System www AllDataSheet com
117. on bit allows to configure the device ac cording to the package 0 42 and 44 pin 1 56 and 64 pin Bit 0 FMP Full memory protection This option bit enables or disables external access to the internal program memory read out protec tion Clearing this bit causes the erasing to 00h of the whole memory including the option byte 0 Program memory not read out protected 1 Program memory read out protected ST72334J N ST72314J N ST72124J USER OPTION BYTE 2 7 0 WDG WDG bsp espe Bit 7 Clock filter control on off This option bit enables or disables the clock filter CF features 0 Clock filter enabled 1 Clock filter disabled Bit 6 4 OSC 2 0 Oscillator selection These three option bits can be used to select the main oscillator as shown in Table 24 Table 24 Main Oscillator Configuration Serao 1 meam __ External RC 1 Tow SpecdResonator o 1 7 Speed Resonator 0 1 o Medium high Speed Resonator 0 9 1 High Speed Resonator o 9 9 Bit 3 2 LVD 1 0 Low voltage detection selection These option bits enable the LVD block with a se lected threshold as shown in Table 25 Table 25 LVD Threshold Configuration Configuration LVD1 LVDO Lip OF Highest Voltage Threshold 5 ESEA Medium Voltage Threshold fosc lt 16MHz 0 1 Lowest Voltage Threshold fosc lt 8MHz o Bit 1
118. pply Manager eee Resides 109 8 6 2 Reset Sequence 109 8 6 3 Multi Oscillator Clock Security System 109 8 7 MEMORY AND PERIPHERAL CHARACTERISTICS 111 9 GENERAL INFORMATION 117 9 1 PACKAGES i 117 9 1 1 Package Mechanical 117 9 1 2 User supplied TQFP64 Adaptor 5 119 9 1 3 User supplied TQFP44 Adaptor 120 9 2 DEVICE CONFIGURATION AND ORDERING INFORMATION 121 9 24 OptiOIT Sos ERG ele e dnd d ied 121 9 2 2 Transfer Of Customer 122 10 SUMMARY OF CHANGES 124 4 125 3 Table of Contents 1 PREAMBLE ST72C334 VERSUS ST72E331 SPECIFICATION New Features available on the ST72C334 8 or 16K FLASH ROM with In Situ Programming and Read out protection New ADC with a better accuracy and conversion time New configurable Clock Reset and Supply system New power saving mode with real time base Active Halt Beep capability on PF1 New interrupt source Clock security system CSS or Main clock controller MCC
119. r Modes Description WAIT No effect on SPI SPI interrupt events cause the device to exit from WAIT mode SPI registers are frozen HALT In HALT mode the SPI is inactive SPI operation resumes when the MCU is woken up by an interrupt with exit from HALT mode capability 6 5 6 Interrupts Enable Interrupt Event Control Bit SPI End of Transfer Event SPIF SPIE Master Mode Fault Event MODF Note The SPI interrupt events are connected to the same interrupt vector see Interrupts chapter They generate an interrupt if the corresponding Enable Control Bit is set and the I bit in the CC reg ister is reset RIM instruction 79 125 ST72334J N ST72314J N ST72124J SERIAL PERIPHERAL INTERFACE Cont d 6 5 7 Register Description CONTROL REGISTER CR Read Write Reset Value 0000xxxx Oxh 7 0 Bit 7 SPIE Serial peripheral interrupt enable This bit is set and cleared by software 0 Interrupt is inhibited 1 An SPI interrupt is generated whenever SPIF 1 or MODF 1 in the SR register Bit 6 SPE Serial peripheral output enable This bit is set and cleared by software It is also cleared by hardware when in master mode 55 0 see Section 6 5 4 5 Master Mode Fault 0 port connected to pins 1 SPI alternate functions connected to pins The SPE bit is cleared by reset so the SPI periph eral is not initially connected to the external pins Bit 5 SPR2 Divider Enable this bit is set and cl
120. ram 112 125 3 ST72334J N ST72314J N ST72124J MEMORY AND PERIPHERAL CHARACTERISTICS Cont d Figure 60 SPI Master Timing Diagram 0 CPOL 1 1 SCK OUTPUT XXXXXL Ur X 1 6 161 7 MOSI OUTPUT M 5 Do ouT XXXX INPUT D0 OUT XXX N OUTPUT r1 f DOAN VR000107 55 INPUT SCK OUTPUT 1 H 1 T Den DO IN XXX i 6 II nos OUTPUT En OUT D6 OUT D0 OUT VR000108 Note 1 Measurement points Vi and the SPI timing diagram 113 125 ST72334J N ST72314J N ST72124J MEMORY AND PERIPHERAL CHARACTERISTICS Cont d Measurement points and Vy the SPI Timing Diagram Figure 63 SPI Slave Timing Diagram 0 CPOL 0 1 MISO OUTPUT MOSI INPUT MISO OUTPUT E IL MOSI 757 i DO IN XXX VR000111 VR000112 Note 1 Measurement points Vi and the SPI timing diagram 3 114 125 ST72334J N ST72314J N ST72124J MEMORY AND PERIPHERAL CHARACTERISTICS Cont d SCI Serial Communication Interface Standard Mode TR resp RR 64 PR 13 300 48 resp RR 16 PR 13 1201 92 resp RR 8 PR 13 2403 84 resp RR 4 PR 13 4807 69 2 fcpu 8MHz 2 PR 13 9615 38 precision vs standard 0 16 TR TR TR TR TR
121. red by software They select the analog input to convert Note The number of pins AND the channel selection var ies according to the device Refer to the device pinout Bit 7 0 D 7 0 Analog Converted Value This register contains the converted analog value in the range 00h to FFh Note Reading this register reset the COCO flag 97 125 ST72334J N ST72314J N ST72124J 8 A D CONVERTER ADC Cont d Table 19 ADC Register Map and Reset Values Address Register 7 Hex Label D ADCDR 7 ADCCSR COCO 98 125 3 7 INSTRUCTION SET 7 1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups Rairessing Mode mee The ST7 Instruction set is designed to minimize the number of bytes required per instruction To do Table 20 ST7 Addressing Mode Overview Pointer Syntax Address Size Hex Hex ST72334J N ST72314J N ST72124J so most of the addressing modes may be subdi vided in two sub modes called long and short Long addressing mode is more powerful be cause itcan use the full 64 Kbyte address space however it uses more bytes and more CPU cy cles Short addressing mode is less powerful because it can generally only access page zero 0000h OOFFh range but the instruction size is more compact and faster All memory to memory
122. rom the stack Program Counter PC The program counter is a 16 bit register containing the address of the next instruction to be executed by the CPU It is made of two 8 bit registers PCL Program Counter Low which is the LSB and PCH Program Counter High which is the MSB ACCUMULATOR X INDEX REGISTER Y INDEX REGISTER PROGRAM COUNTER CONDITION CODE REGISTER STACK POINTER X Undefined Value 21 125 ST72334J N ST72314J N ST72124J CENTRAL PROCESSING UNIT CONDITION CODE REGISTER CC Read Write Reset Value 111x1xxx The 8 bit Condition Code register contains the in terrupt mask and four flags representative of the result ofthe instruction just executed This register can also be handled by the PUSH and POP in structions These bits can be individually tested and or con trolled by specific instructions Bit 4 H Half carry This bitis set by hardware when a carry occurs be tween bits 3 and 4 of the ALU during an ADD or ADC instruction It is reset by hardware during the same instructions 0 No half carry has occurred 1 A half carry has occurred This bit is tested using the JRH or JRNH instruc tion The H bit is useful in BCD arithmetic subrou tines Bit 3 I nterrupt mask This bit is set by hardware when entering in inter rupt or by software to disable all interrupts except the TRAP software interrupt This bit is cleared by software 0 Interrupts are enabl
123. rry Flag RSP LD CLR NZ U PUSHPOP SLL SRL SRA RLC RRC SWAP Swap Nibbles 7 1 2 Immediate Immediate instructions have two bytes the first byte contains the opcode the second byte con tains the the operand value Immediate Instruction RSP 2 Reset Stack Pointer Shift and Rotate Operations Load LD CP Compare BCP AND OR XOR ADC ADD SUB 5 Arithmetic Operations Logical Operations 100 125 7 1 3 Direct In Direct instructions the operands are referenced by their memory address The direct addressing mode consists of two sub modes Direct short The address is a byte thus requires only one byte after the opcode but only allows 00 FF address ing space Direct long The address is a word thus allowing 64 Kbyte ad dressing space but requires 2 bytes after the op code 7 1 4 Indexed No Offset Short Long In this mode the operand is referenced by its memory address which is defined by the unsigned addition of an index register X or Y with an offset The indirect addressing mode consists of three sub modes Indexed No Offset There is no offset no extra byte after the opcode and allows 00 FF addressing space Indexed Short The offset is a byte thus requires only one byte af ter the opcode and allows 00 1FE addressing space Indexed long The offset is a word thus allowing 64 Kbyte ad dressing space and requires 2 bytes after t
124. ruction or when the T6 bit reaches zero Figure 34 Watchdog Block Diagram m Hardware Watchdog selectable by option byte m Watchdog Reset indicated by status flag in versions with Safe Reset option only 6 3 3 Functional Description The counter value stored in the CR register bits T 6 0 is decremented every 12 288 machine cy cles and the length of the timeout period can be programmed by the user in 64 increments If the watchdog is activated the WDGA bit is set and when the 7 bit timer bits T 6 0 rolls over from 40h to 3Fh T6 becomes cleared it initiates a reset cycle pulling low the reset pin for typically 500ns WATCHDOG CONTROL REGISTER CR III o 7 BIT DOWNCOUNTER CLOCK DIVIDER 12288 50 125 3 WATCHDOG Cont d The application program must write in the CR reg ister at regular intervals during normal operation to prevent an MCU reset The value to be stored in the CR register must be between FFh and COh see Table 12 Watchdog Timing fCPU 8 MHz The WDGA bit is set watchdog enabled The T6 bit is set to prevent generating an imme diate reset The T 5 0 bits contain the number of increments which represents the time delay before the watchdog produces a reset Table 12 Watchdog Timing 8 MHz CR Register WDG timeout period initial value ms Max FFh Min COh 98 304 1 536 Notes Following a reset the watchdog is disa bled O
125. s effect on the ADC accuracy has been observed under worst case conditions for injection negative injection injection to an Input with analog capability adjacent to the enabled Analog Input at 5V Vpp supply and worst case temperature Digital Result ADCDR 1 Example of an actual transfer curve 2 The ideal transfer curve 3 End point correlation line 188 7 TUE Total Unadjusted Error maximum deviation between the actual and the ideal transfer curves OE Offset Error deviation between the first actual transition and the first ideal one GE Gain Error deviation between the last ideal transition and the last actual one DLE Differential Linearity Error maximum devia tion between actual steps and the ideal one ILE Integral Linearity Error maximum deviation between any actual transition and the end point gt 1 DLE n an correlation line 1 LSB ideal A Vin LSBideai 253 254 255 256 DDA 3 116 125 ST72334J N ST72314J N ST72124J 9 GENERAL INFORMATION 9 1 PACKAGES 9 1 1 Package Mechanical Data Figure 67 64 Pin Thin Quad Flat Package P us T pue i v uc rmm pas m oo 015 00 009 135 120 145 0053 0 055 0057 037 045 Fe oos For e Fo Teo feo Fer peo Fer Teo Pe po
126. s first transmission Access the register and write the data to send in the DR register this sequence clears the TDRE bit Repeat this sequence for each data to be transmitted Clearing the TDRE bit is always performed by the following software sequence 1 An access to the SR register 2 A write to the DR register The TDRE bit is set by hardware and it indicates The TDR register is empty The data transfer is beginning The next data can be written in the DR register without overwriting the previous data This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register When a transmission is taking place a write in struction to the DR register stores the data in the TDR register and which is copied in the shift regis ter at the end of the current transmission When no transmission is taking place a write in struction to the DR register places the data directly in the shift register the data transmission starts and the TDRE bit is immediately set 86 125 When frame transmission is complete after the stop bit or after the break frame the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register Clearing the TC bit is performed by the following software sequence 1 An access to the SR register 2 A write to the DR register Note The TDRE and bits are cleared by the same software sequence
127. s unless otherwise specified EXTERNAL CLOCK SOURCE OSC1 input pin high level voltage Square wave signal Rl OSC1 input pin low level voltage with 50 Duty Cycle 954 Notes 1 LVD typical data are based T 25 C They are given only as design guidelines and are not tested 2 The VLypnyst hysteresis is constant 3 Data based on characterization results not tested in production 4 Unless otherwise specified typical data are based 25 and Vpp Vgs 5V They are given only as design guide lines and are not tested 109 125 ST72334J N ST72314J N ST72124J SUPPLY RESET AND CLOCK CHARACTERISTICS Cont d CRYSTAL AND CERAMIC RESONATOR OSCILLATORS Low speed resonator f Oscillator Freg ency 2 Medium low speed resonator osc quency Medium high speed resonator High speed resonator Low speed Rsmax 200 0 Load Medium low speed 2000 3 Capacitance Medium high speed Rsmax 2002 3 High speed Rsmax 1002 3 Low speed Supply Medium low speed Current Medium high speed High speed Oscillator start up time Depends on resonator quality A typical value is 10ms EXTERNAL RC OSCILLATOR Vpo 5V INTERNAL RC OSCILLATOR Symbol Parameter Conditions Min 1 Max Vpp 5 5V 50 4 25 5 00 fosc Internal RC Oscillator Frequency 00255 502 V 50 CLOCK SECURITY SYSTEM CSS
128. sampLe sample capacitor is disconnected from the analog input pin to get the optimum A D conversion accuracy While the ADC is on these two phases are contin uously repeated At the end of each conversion the sample capaci tor is kept loaded with the previous measurement load The advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement 6 7 3 4 Software Procedure Refer to the control status register CSR and data register DR in Section 6 7 6 for the bit definitions and to Figure 57 for the timings ADC Configuration The total duration of the A D conversion is 12 ADC clock periods 1 fapc 2 fcpy 96 125 The analog input ports must be configured as in put no pull up no interrupt Refer to the I O ports chapter Using these pins as analog inputs does not affect the ability of the port to be read as a logic input In the CSR register Select the CH 3 0 bits to assign the analog channel to convert ADC Conversion In the CSR register Set the ADON bit to enable the A D converter and to start the first conversion From this time on the ADC performs a continuous conver sion of the selected channel When a conversion is complete The COCO bit is set by hardware No interrupt is generated The result is in the DR register and remains valid until the next conversion has ended write to the CSR register w
129. seful for distinguishing power on off or external reset and watchdog reset 0 No Watchdog reset occurred 1 Watchdog reset occurred Only by software and power on off reset Note This register is not used in versions without LVD Reset 51 125 ST72334J N ST72314J N ST72124J WATCHDOG TIMER Cond t Table 13 Watchdog Timer Register Map and Reset Values Address Register Hex Label WDGCR 002Ah Reset Value 3 52 125 6 4 16 6 4 1 Introduction The timer consists of a 16 bit free running counter driven by a programmable prescaler It may be used for a variety of purposes including pulse length measurement of up to two input sig nals input capture or generation of up to two out put waveforms output compare and PWM Pulse lengths and waveform periods can be mod ulated from a few microseconds to several milli seconds using the timer prescaler and the CPU clock prescaler 6 4 2 Main Features m Programmable prescaler fopy divided by 2 4 8 Overflow status flag and maskable interrupt External clock input must be at least 4 times slower thanthe CPU clock speed with the choice of active edge Output compare functions with 2 dedicated 16 bit registers 2 dedicated programmable signals 2 dedicated status flags 1 dedicated maskable interrupt Input capture functions with 2 dedicated 16 bit registers 2 dedicated active edge selection signals
130. smitter is disabled the TDO pin is back to the I O port configuration 1 Transmitter is enabled Note during transmission a 0 pulse on the TE bit followed by 1 sends a preamble after the current word Bit 2 RE Receiver enable This bit enables the receiver It is set and cleared by software 0 Receiver is disabled it resets the RDRF IDLE OR NF and FE bits of the SR register 1 Receiver is enabled and begins searching for a start bit Bit 1 RWU Receiver wake up This bit determines if the SCI is in mute mode or not It is set and cleared by software and can be cleared by hardware when a wake up sequence is recognized 0 Receiver in active mode 1 Receiver in mute mode Bit 0 SBK Send break This bit set is used to send break characters It is set and cleared by software 0 No break character is transmitted 1 Break characters are transmitted Note If the SBK bit is set to 1 and then to 0 the transmitter will send a BREAK word at the end of the current word 3 SERIAL COMMUNICATIONS INTERFACE Cont d DATA REGISTER DR Read Write Reset Value Undefined Contains the Received or Transmitted data char acter depending on whether it is read from or writ ten to 7 0 The Data register performs a double function read and write since it is composed of two registers one for transmission TDR and one for reception RDR The TDR register provides the parallel int
131. t Capture function and the Output Compare function Procedure To use one pulse mode 1 Load the register with the value corre sponding to the length of the pulse see the for mula in Section 6 4 3 7 Select the following in the CR1 register Using the OLVL 1 bit selectthe level to be ap plied to the 1 pin after the pulse Using the OLVL2 bit select the level to be ap plied to the pin during the pulse Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit the ICAP1 pin must be configured as floating input Select the following in the CR2 register Set the OC1E bit the pin is then ded icated to the Output Compare 1 function Set the OPM bit Select the timer clock CC1 CCO see Table 14 Clock Control Bits ST72334J N ST72314J N ST72124J One pulse mode cycle When event occurs on ICAP1 OCMP 1 OLVL2 Counter is reset to FFFCh ICF1 bit is set When Counter 1 1 OLVL1 Then a valid event the the coun ter is initialized to FFFCh and OLVL2 bit is loaded on the pin the ICF1 bit is set and the val FFFDh is loaded in the register When the value of the counter is equal to the value of the contents of the register the OLVL1 bit is output on the pin See Figure 44 Notes
132. t be programmed with the same timing mode SLAVE MSBit 4 LSBit 7 8 BIT SHIFT REGISTER 3 ST72334J N ST72314J N ST72124J SERIAL PERIPHERAL INTERFACE Cont d Figure 47 Serial Peripheral Interface Block Diagram Internal Bus IT E request ite E SPI STATE ES T SS Em FX ER FX SERIAL CLOCK GENERATOR 437 71 125 ST72334J N ST72314J N ST72124J SERIAL PERIPHERAL INTERFACE Cont d 6 5 4 Functional Description Figure 46 shows the serial peripheral interface SPI block diagram This interface contains 3 dedicated registers A Control Register CR A Status Register SR A Data Register DR Refer to the CR SR and DR registers in Section 6 5 7for the bit definitions 6 5 4 1 Master Configuration In a master configuration the serial clock is gener ated on the SCK pin Procedure Select the SPRO amp SPR1 bits to define the se rial clock baud rate see CR register Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock see Figure 49 The SS pin must be connected to a high level signal during the complete byte transmit se quence The MSTR and SPE bits must be set they re main set only if the SS pin is connected to a high level signal 72 25 In this configuration the MOSI pin is a data output and to the MISO pin is a data input Transmit sequ
133. ter is interpreted as an entire frame of 1 s followed by the start bit of the next frame which contains data A Break character is interpreted on receiving 0 5 for some multiple of the frame period At the end of the last break frame the transmitter inserts an ex tra 1 bit to acknowledge the start bit Transmission and reception are driven by their own baud rate generator Possible Parity Bit i Next Next Data Frame Start Start Start Idle Frame Bit Break Frame T 8 bit Word length M bit is reset Data Frame Start Bit Idle Frame Possible Next Data Frame Extra i 85 125 ST72334J N ST72314J N 5772124 SERIAL COMMUNICATIONS INTERFACE Cont d 6 6 4 2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status When the M bit is set word length is 9 bits and the 9th bit the MSB has to be stored in the T8 bit in the CR1 reg ister Character Transmission During an SCI transmission data shifts out least significant bit first on the TDO pin In this mode the DR register consists of a buffer TDR between the internal bus and the transmit shift register see Figure 52 Procedure Select the M bit to define the word length Selectthe desired baud rate using the BRR and the registers Setthe TE bit to assign the TDO pin to the alter nate function and to send a idle frame a
134. th the OC2R reg ister and is set in the CR2 register This val ue is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode Bit 1 IEDG1 nput Edge 1 This bit determines which type of level transition on the pin will trigger the capture 0 A falling edge triggers the capture 1 A rising edge triggers the capture Bit 0 OLVL1 Output Level 1 The OLVL1 bit is copied to the OCMP1 pin when ever a successful comparison occurs with the register and the OC1E bit is set in the CR2 register 65 125 ST72334J N ST72314J N ST72124J 16 BIT TIMER Cont d CONTROL REGISTER 2 CR2 Read Write Reset Value 0000 0000 00h 7 0 Bit 7 OC1E Output Compare 1 Pin Enable This bit is used only to output the signal from the timer on the OCMP1 pin OLV1 in Output Com pare mode both OLV1 and OLV2 in PWM and one pulse mode Whatever the value ofthe OC1E bit the Output Compare 1 function of the timer re mains active 0 1 pin alternate function disabled I O pin free for general purpose 1 OCMP1 pin alternate function enabled Bit 6 OC2E Output Compare 2 Enable This bit is used only to output the signal from the timer on the OCMP2 pin OLV2 in Output Com pare mode Whatever the value of the OC2E bit the Output Compare 2 function of the timer re mains active 0 2 pin alternate function disabled I O pin free for general purpose 1
135. to protect the de vice against positive stress 437 43 125 ST72334J N ST72314J N ST72124J PORTS Cont d 6 1 3 Port Implementation The port register configurations are summa rised as following Standard Ports PA5 4 PC7 0 PD7 0 PE7 4 PE1 0 PF7 6 PF4 Interrupt Ports PA2 0 PB6 4 PB2 0 PF1 0 with pull up floating interrupt input open drain output push pull output Table 9 Port Configuration Switching these I O ports from one state to anoth er should be done in a sequence that prevents un wanted side effects Recommended safe transi tions are illustrated in Figure 33 Other transitions are potentially risky and should be avoided since they are likely to present unwanted side effects such as spurious interrupt generation Figure 33 Interrupt I O Port State Transition 00 GD INPUT INPUT floating reset state OUTPUT open drain OUTPUT pull up floating push pull interrupt DDR OR True Open Drain Ports floating input open drain high sink ports true open drain 5 4 floating pull up push pull floating floating interrupt push pull PA2 0 Port B floating pull up interrupt push pull PB7 PB3 floating floating interrupt push pull PB6 4 PB2 0 floating pull up interrupt push pull floating pull up push pull 075 push pull PE7 4 PE1 0 floating pull up push pull PF7 6 PF4 flo
136. to the standard ST7 programming tool is described be low For more details on ISP programming refer to the ST7 Programming Specification Remote ISP Overview The Remote ISP modeis initiated by a specific se quence on the dedicated ISPSEL pin The Remote ISP is performed in three steps Selection of the RAM execution mode Download of Remote ISP code in RAM Execution of Remote ISP code in RAM to pro gram the user program into the FLASH Remote ISP hardware configuration In Remote ISP mode the ST7 has to be supplied with power Vpp and Vss and a clock signal os cillator and application crystal circuit for example 16 125 This mode needs five signals plus the Vpp signal if necessary to be connected to the programming tool This signals are RESET device reset device ground power supply SPCLK ISP output serial clock pin ISPDATA ISP input serial data pin ISPSEL Remote ISP mode selection This pin must be connected to Vgs on the application board If any of these pins are used for other purposes on the application a serial resistor has to be imple mented to avoid a conflict if the other device forces the signal level Figure 6 shows a typical hardware interface to a standard ST7 programming tool For more details on the pin locations refer to the device pinout de scription Figure 6 Typical Remote ISP Interface HE10 CONNECTOR TYPE TO PROGRAMMING TOOL APPLICATION 2 5
137. ts Supply Operating Range in the application Notes Signature 123 125 ST72334J N ST72314J N ST72124J 10 SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one New chapter to compare ST72334 versus ST72331 section 2 1 on page 6 Correction of the address of the CRSR register to 2Bh instead of 25h Table 4 page 33 Correction of port A pin name column in Table 9 page 44 PA2 0 instead of PA3 0 Correction of MISCR2 register description section 6 2 3 on page 48 Correction of the FLASH and data EEPROM programming time section 8 7 on page 111 Correction of the 44 socket proposal Table 23 page 120 More information on the FMP option bit section 9 2 1 on page 121 Added 519 format in transfer of Code section 9 2 2 on page 122 Correction of the microcontroller option list section 9 2 2 on page 122 History page added section 10 on page 124 124 125 3 ST72334J N ST72314J N ST72124J Notes Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of useof such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publicati
138. ts not tested in production 6 is the number of to finish the current instruction execution 107 125 ST72334J N ST72314J N ST72124J 8 5 PORT CHARACTERISTICS Recommended operating conditions with 40 to 85 C and 4 5V Vpp Vss 5 5V unless otherwise specified PORT PINS leve vogs nut igh Tevel Schmit trigger voltage fysterei E m m Output low level voltage 5mA BRB 0 0 ____ ______________ gt _ Output leve voltage A 05 Vpp 2 0 Output high level voltage ema Pull up equivalent resistor _ gt VIH 20 35 50 Vin Lesern sv Static current consumption Floating input mode Positive Vx Vvpp 5 Ipiny Single pin injected current 7 0 Negative sal jected carer bo INJ sum of all I O and control pins NC NON 5597 857 Notes 1 Unless otherwise specified typical data are based on 25 and Vpp Vss 5V They are given only as design guide lines and are not tested 2 Data based on design simulation and or technology characteristics not tested in production 3 Hysteresis voltage between Schmitt trigger switching levels Based on characterizat
139. uest The interrupt sensitivity is given inde pendently according to the description mentioned in the Miscellaneous register 42 125 Each external interrupt vector is linked to a dedi cated group of I O port pins see Interrupt section If more than one input pins are selected simultane ously as interrupt source these are logically AND ed For this reason if one of the interrupt pins is tied low it masks the other ones In case of a floating input with interrupt configura tion special cares mentioned in the I O port imple mentation section have to be taken Output Mode The output configuration is selected by setting the corresponding DDR register bit In this case writing the DR register applies this digital value to the I O pin through the latch Then reading the DR register returns the previously stored value Two different output modes can be selected by software through the OR register Output push pull and open drain DR register value and output pin status DR vw v Note In this mode interrupt function is disabled Alternate function When an on chip peripheral is configured to use a pin the alternate function is automatically select ed This alternate function takes priority over the standard I O programming When the signal is coming from an on chip periph eral the I O pin is automatically configured in out put mode push pull or open drain according to the
140. w or an underflow has occurred during the last arithmetic operation 0 No overflow or underflow has occurred 1 An overflow or underflow has occurred This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions It is also affected by the bit test and branch shift and rotate instructions 3 CENTRAL PROCESSING UNIT Stack Pointer SP Read Write Reset Value 01 FFh 15 8 1 7 0 The Stack Pointer is a 16 bit register which is al ways pointing to the next free location in the stack It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack see Figure 11 Since the stack is 256 bytes deep the 8th most significant bits are forced by hardware Following an MCU Reset or after a Reset Stack Pointer in struction RSP the Stack Pointer contains its re set value the SP7 to SPO bits are set which is the stack higher address Figure 11 Stack Manipulation Example CALL Interrupt Subroutine Stack Higher Address 01FFh Stack Lower Address 0100h ST72334J N ST72314J N ST72124J The least significant byte of the Stack Pointer called S can be directly accessed by a LD in struction Note When the lower limit is exceeded the Stack Pointer wraps around to the stack upper limit with out indicating the stack overflow The previously stored information is then overwritten and there fore

ST ST72334J/N ST72314J/N ST72124J 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY ADC 16-BIT TIMERS SPI SCI INTERFACES handbook(1)

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