ST EMIF06-10006C2 IPAD 6 line EMI filter ESD protection handbook
Contents
1. 0 00 d Aplac 7 62 User ST Microelectronics J 44B dB 4 12 5 p 25 i3_02 s2p 25 1 4 00 1 a 37 50 4 4 75 Measurement Simulation t Hz 50 00 E f Hz 100 0k 1 0M 10 0M 100 0M 1 06 100 Lt 100k 1M 10M 100M 1G Figure 5 Digital crosstalk measurements Figure 6 ESD response to IEC 61000 4 2 15 kV air discharge on one imput Vin and one output Vout E SSeS ae Figure 7 ESD response to IEC 61000 4 2 Figure 8 Line capacitance versus applied 15 kV air discharge on one imput voltage for filter Vin and one output Vout C pF see A 100 f a 90 80 70 60 50 40 30 20 10 0 00 05 10 15 20 25 30 35 40 45 50 VR V Characteristics EMIF06 10006C2 Figure 9 Aplac model Rbump Lbump Rs 100 Lbump Rbump Oi Output of each filter cell O sub Lbump li Input of each filter cell Cgnd 3 Lgnd Rgnd EMIF06 10006C2 model Ground return for each GND bump Fi2. 197 EMIF06 10006C2 IPAD 6 line EMI filter and ESD protection Main product characteristics Where EMI filtering in ESD sensitive equipment is required m Mobile phones and communication systems m Computers printers and MCU Boards Description The EMIF06 10006C2 is a highly integrated device designed to suppress EMI RFI noise in all systems subjected to electromagnetic interference The EMIFO6 Flip Chip packaging means the package size is equal to the die size This filter includes an ESD protection circuitry which prevents damage to the application when subjected to ESD surges up 15 kV This device includes 6 EMIF filters Benefits EMI symmetrical I O low pass filter High efficiency in EMI filtering Lead free coated package Very low PCB space consumption 2 92 mm x 1 29 mm m Very thin package 0 695 mm m High efficiency in ESD suppression IEC 61000 4 2 level 4 m High reliability offered by monolithic integration m High reduction of parasitic elements through integration and wafer level packaging TM IPAD is a trademeark of STMicroelectronics November 2006 Flip Chip 15 Bumps Order Code Part Number Marking EMIF06 10006C2 FT Figure 1 Pin Configuration bump side 1 15 2 mm 06 05 04 03 02 01 Complies with the following standards IEC 61000 4 2 level 4 15 kV air discharge 8 kV contact discharge MIL STD 883G M
3. SZL L 0 ge 0 8 0 73 0 05 4 l 0 1 All dimensions in mm User direction of unreeling In order to meet environmental requirements ST offers these devices in ECOPACK packages These packages have a lead free second level interconnect The category of second level interconnect is marked on the package and on the inner box label in compliance with JEDEC Standard JESD97 The maximum ratings related to soldering conditions are also marked on the inner box label ECOPACK is an ST trademark ECOPACK specifications are available at www st com Note More packing information is available in the application notes AN1235 Flip Chip Package description and recommendations for use AN1751 EMI Filters Recommendations and measurements 7 9 Ordering Information EMIF06 10006C2 4 5 8 9 Ordering Information Ordering code Marking Package Weight Base qty Delivery mode EMIFO6 10006C2 FT Flip Chip 5 9 mg 5000 Tape and reel 7 Revision History Date Revision Description of Changes 17 Nov 2006 1 First issue EMIF06 10006C2 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described here
4. S NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2006 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 9 9 q
5. ethod 3015 7 Class 3 30 kV Rev 1 1 9 www st com Characteristics EMIF06 10006C2 2 9 Characteristics Figure 2 Basic cell configuration 1000 100 0 Input 1 Output 1 Input 4 Output 4 po Td 1000 1000 Input 2 Output 2 Input 5 Output 5 qr 1000 1009 Input 3 Output 3 Input 6 Output 6 o TT Table 1 Absolute Ratings limiting values Symbol Parameter and test conditions Value Unit PR DC power per resistance 0 1 Ww Pr Total DC power per package 0 6 W Tj Maximum junction temperature 125 C Top Operating temperature range 40 to 85 C T stg Storage temperature range 125 C Table 2 Electrical Characteristics Tamp 25 C Symbol Parameter VBR Breakdown voltage IE eee IRM Leakage current O VRM Vrm Stand off voltage VeL Clamping voltage VeL VBR VRM Re Ry Dynamic impedance E y lpp Peak pulse current Ryo Series resistance between Input and output Si lnc CT Symbol Test conditions Min Typ Max Unit Ver lg 1mA 5 5 7 9 V IBM Vam 3 3 V per line 500 nA Ro l 10mA 80 100 120 Q Cline Vg 2 5 V F 1 MHz 30 mV on filter cells 50 60 70 pF EMIF06 10006C2 Characteristics Figure 3 S21 db attenuation measurements Figure 4 Analog crosstalk measurements and Aplac simulation
6. gure 10 Figure 10 Aplac parameters aplacvar RS 1009 aplacvar Cz 41 pF aplacvar Lbump 50 pH aplacvar Rbump 20m aplacvar Cbump 1 2 pF aplacvar Rsub 100 m aplacvar Rgnd 100 m aplacvar Lgnd 100 pH aplacvar Cgnd 0 15 pF 4 9 4 EMIF06 10006C2 Ordering Information Scheme 2 Ordering Information Scheme EMIF yy EMI Filter Number of lines Information XXX zz Cx x resistance value Ohms z Capacitance value 10 pF or 3 letters application 2 digits version Package C Coated Flip Chip x 2 Lead free Pitch 500 um Bump 315 um 5 9 Package information EMIF06 10006C2 3 6 9 Package information Figure 11 Flip Chip Package dimensions 315 um 50 500 um 50 250 um 50 1 Vo 1 29 mm 50 pm 2 92 mm 50 um 695 um 75 OO Figure 12 Foot print recommendations Figure 13 Marking f Dot ST logo l xx marking z manufacturing location yww datecode y year ww week Copper pad Diameter 250 um recommended 300 um max Solder stencil opening 330 um Solder mask opening recommendation 340 um min for 300 um copper pad diameter 4 EMIF06 10006C2 Package information Note Figure 14 Flip Chip Tape and reel specification Dot identifying Pin A1 location O15 0 1 VO
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ST EMIF06 10006C2 IPAD 6 line EMI filter ESD protection handbook