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ST ST72104G ST72215G ST72216G ST72254G handbook

1. Counter High Register CHR is the most sig nificant byte MS Byte Counter Low Register CLR is the least sig nificant byte LS Byte Alternate Counter Register ACR Alternate Counter High Register ACHR is the most significant byte MS Byte Alternate Counter Low Register ACLR is the least significant byte LS Byte These two read only 16 bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit Timer overflow flag located in the Status register SR see note at the end of paragraph titled 16 bit read sequence Writing inthe CLR register or ACLR register resets the free running counter to the FFFCh value Both counters have a reset value of FFFCh this is the only value which is reloaded in the 16 bit tim er The reset value of both counters is also FFFCh in One Pulse mode and PWM mode The timer clock depends on the clock control bits of the CR2 register as illustrated in Table 13 Clock Control Bits The value in the counter register re peats every 131 072 262 144 or 524 288 CPU clock cycles depending on the CC 1 0 bits The timer frequency can be L fepy 4 fepu 8 or an external frequency d ST72104G ST72215G ST72216G ST72254G 16 BIT TIMER Cont d Figure 26 Timer Block Diagram ST7 INTERNAL BUS MCU PERIPHERAL INTERFACE OUTPUT OUTPUT INPUT COUNTER compare COMPARE CAPTURE CAPTURE REGISTER R
2. START condition hold time Lauer Repeated START condition setup time 300 20 0 1Cp 3 E a 5 tsusto STOP condition setup time STOP to START condition time bus free Capacitive load for each bus line Figure 93 Typical Application with EC Bus and Timing Diagram 7 w 3 GEI N L OLN O o o REPEATED START 7 oe STA tw STO STA lt i ee I A ee a 8 e Lef thsta twsckH wSCKL tysck Beie Notes 1 Data based on standard 12C protocol requirement not tested in production 2 The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL 3 The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal 4 Measurement points are done at CMOS levels 0 3xVpp and 0 7xVpp ky 123 135 ST72104G ST72215G ST72216G ST72254G 13 12 8 BIT ADC CHARACTERISTICS Subject to general operating conditions for Vpp fosc and Ta unless otherwise specified Symb Pe Conditions win Wye Max Unit too ADC aran LL CHE Cie conversion range A Vesa Yona v 7 Raw Exemalinputvesitor JO A Stabilization time after ADC enable Conversion time Sample Hold foru 8MHz fano 4MHz ADC i i Sample capacitor loading time Hold conversion time Figure 94 Typical Application with ADC ST72XXX Notes 1 Unless otherwise sp
3. In slave mode 0 No start generation 1 Start generation when the bus is free 80 135 Bit 2 ACK Acknowledge enable This bit is set and cleared by software It is also cleared by hardware when the interface is disa bled PE 0 0 No acknowledge returned 1 Acknowledge returned after an address byte or a data byte is received Bit 1 STOP Generation of a Stop condition This bit is set and cleared by software It is also cleared by hardware in master mode Note This bit is not cleared when the interface is disabled PE 0 In master mode 0 No stop generation 1 Stop generation after the current byte transfer or after the current Start condition is sent The STOP bit is cleared by hardware when the Stop condition is sent In slave mode 0 No stop generation 1 Release the SCL and SDA lines after the cur rent byte transfer BTF 1 In this mode the STOP bit has to be cleared by software Bit 0 ITE nterrupt enable This bitis set and cleared by software and cleared by hardware when the interface is disabled PE 0 0 Interrupts disabled 1 Interrupts enabled Refer to Figure 46 for the relationship between the events and the interrupt SCL is held low when the ADD10 SB BTF or ADSL flags or an EV6 event See Figure 45 is de tected d DC BUS INTERFACE Cont d UC STATUS REGISTER 1 SR1 Read Only Reset Value 0000 0000 00h T 0 Leve aooro tea susy evr fansi ws Bit 7
4. The MCC block consists of a A programmable CPU clock prescaler A clock out signal to supply external devices The prescaler allows the selection of the main clock frequency and is controlled by three bits of the MISCR1 CP1 CPO and SMS The clock out capability consists of a dedicated I O port pin configurable as an fcpy clock output to drive external devices It is controlled by the MCO bit in the MISCR1 register See Section 10 MISCELLANEOUS REGIS TERS on page 36 for more details Figure 14 Main Clock Controller MCC Block Diagram CLOCK TO CAN PERIPHERAL PORT ALTERNATE FUNCTION BRERSGRRESES 24 135 CPU CLOCK TO CPU AND PERIPHERALS d 7 INTERRUPTS The ST7 core may be interrupted by one of two dif ferent methods maskable hardware interrupts as listed in the Interrupt Mapping Table and a non maskable software interrupt TRAP The Interrupt processing flowchart is shown in Figure 15 The maskable interrupts must be enabled clearing the bit in order to be serviced However disabled interrupts may be latched and processed when they are enabled see external interrupts subsec tion When an interrupt has to be serviced Normal processing is suspended at the end of the current instruction execution The PC X A and CC registers are saved onto the stack The bit of the CC register is set to prevent addi tional interrupts The PC is then loaded with the interrupt v
5. 000000 cee eee 104 13 5 1General TimingS 104 13 5 2External Clock Source sideang tantuin eee 104 13 5 3Crystal and Ceramic Resonator Oscillators 0 0 0 0 cee eee eee 105 13 5 4RC Oscillators 106 13 5 5Clock Security System Cp 107 13 6 MEMORY CHARACTERISTICS 000 cece eee 108 13 6 1RAM and Hardware Registers 000 c cece eee tees 108 13 6 2FLASH Program Memory 108 13 7 EMC CHARAC TERISTICS b sapiens aa ddr rara A dag ae 109 13 7 AFun ttona EMS iarsan mesam a a hae a Ss bale wale 109 13 7 2Absolute Electrical Sensitivity 110 13 7 3ESD Pin Protection Strategy 112 13 8 I O PORT PIN CHARACTERISTICS 0 0000 cee cee eee 114 13 8 1General Characteristics 114 13 8 20utput Driving Current 0 0 0 eee 115 13 9 CONTROL PIN CHARACTERISTICS 000 000 cee eee eee 117 4 135 57 ST72104G ST72215G ST72216G ST72254G 13 9 1Asynchronous RESET Pm 117 13 S9 2ISPSEL PIN sua icon a Yeas ue E 119 13 10 TIMER PERIPHERAL CHARACTERISTICS oococcccccccccc ee 120 13 10 1Watehdog Timer EE deere eee edie ANEN NNN 120 1310 216 Bit IME EE 120 13 11 COMMUNICATION INTERFACE CHARACTERISGTICGS 000000005 121 13 11 1SPI Serial Peripheral Interface 2 0 0 0 0 ce eee 121 13 11 212C Inter IC Control Interface 123 13 12 8 BIT ADC CHARACTERISTICS 0 0 0 0 eee eee 124 14 PACKAGE CHARACTERISTICS 2 0 2 0 cece eee eee eee eee eens 126 14 1 PACKAGE MECHANICAL DATA 126
6. 3 OSC1 and OSC2 pins connect a crystal or ceramic resonator an external RC or an external source to the on chip oscillator see Section 2 PIN DESCRIPTION on page 7 and Section 13 5 CLOCK AND TIM ING CHARACTERISTICS on page 104 for more details 1 E N APE A a 9 135 ST72104G ST72215G ST72216G ST72254G 3 REGISTER amp MEMORY MAP As shown in the Figure 4 the MCU is capable of addressing 64K bytes of memories and UO regis ters The available memory locations consist of 128 bytes of register location 256 bytes of RAM and up to 8Kbytes of user program memory The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh The highest address bytes contain the user reset and interrupt vectors Figure 4 Memory Map HW Registers see Table 2 256 Bytes RAM Reserved Program Memory 4K 8 KBytes Interrupt amp Reset Vectors see Table 5 on page 26 a l l L l l l A 10 135 IMPORTANT Memory locations marked as Re served must never be accessed Accessing a re seved area can have unpredicable effects on the device Short Addressing RAM Zero page 128 Bytes Stack or 16 bit Addressing RAM 128 Bytes z E000h 8 KBytes Le F000h 4 KBytes S FFFFh dl Table 2 Hardware Register Map Register Address Label ST72104G ST72215G ST72216G ST72254G Reset Status Register Name Port C Data Register Port C Data
7. 4 Rex must have a positive temperature coefficient ppm C carbon resistors should therefore not be used 5 Important when no external Cex is applied the capacitance to be considered is the global parasitic capacitance which is subject to high variation package application In this case the RC oscillator frequency tuning has to be done by trying out several resistor values 106 135 STA ST72104G ST72215G ST72216G ST72254G CLOCK CHARACTERISTICS Cont d 13 5 5 Clock Security System CSS Symbol Parameter Conditions min Typ Max Unit Tp 25 C Vpp 5 0V 250 340 430 srosc Safe Oscillator Frequency 1 a ap RA E REESEN Ise amara YO o Figure 68 Typical Safe Oscillator Frequencies fosc kHz 40 C gt 85 C Wo 425 C AF 125 C VDD V Note 1 Data based on characterization results tested in production between 90KHz and 500KHz 2 Filtered glitch on the fosg signal See functional description in Section 6 5 on page 23 for more details 107 135 a ST72104G ST72215G ST72216G ST72254G 13 6 MEMORY CHARACTERISTICS Subject to general operating conditions for Vpp fosc and Ta unless otherwise specified 13 6 1 RAM and Hardware Registers Data retention mode HALT mode or RESET 13 6 2 FLASH Program Memory Symbol Paame NI LT O IA NE Programming time for 1 16 bytes ZU Ta 25 C es ies ing ti Programming time for 4 or 8kBytes Ta 25 C Data retention Ta 5
8. H m Wei m O SPI Slave Select active low SPI Serial Clock or ISP Clock SPI Master In Slave Out Data or ISP Data SPI Master Out Slave In Data al pe Pele ons 205025 O 0 O Po w el ep BR 5 PB6 SCK ISPC LK O PB5 MISO ISPDATA PB4 MOSI BS ES open PC5 EXTCLK_A AIN5 I O 15 PC4 OCMP2_B AIN4 I O PC3 ICAP2_B AIN3 I O PC2 MCO AIN2 O 8 135 O Lofo e o w sors a a ala lt a gt Port B3 Timer A Output Compare 2 Port B2 Timer A Input Capture 2 Timer A Output Compare 1 m O O fl fi Bai Bari ag oO OF O10 E EEE SR Il o 4 C ei0 ei1 Port C2 ADC Analog Input 2 dl ST72104G ST72215G ST72216G ST72254G Function Alternate Function after reset Ple Pee 30 26 Ieren In c E situ programming selection Should be tied ow in standard user mode ae s eee EIER ERR SBS RER Notes 1 In the interrupt input column eiX defines the associated external interrupt vector If the weak pull up column wpu is merged with the interrupt column int then the I O configuration is pull up interrupt input else the configuration is floating interrupt input 2 In the open drain output column T defines a true open drain I O P Buffer and protection diode to Von are not implemented See Section 9 I O PORTS on page 30 and Section 13 8 l O PORT PIN CHAR ACTERISTICS on page 114 for more details
9. ing the resistance and the capacitance of the de vice This mode is the most cost effective one with the drawback of a lower frequency accuracy lts frequency is in the range of several MHz In this mode the two oscillator pins have to be tied to ground LSTA ST72104G ST72215G ST72216G ST72254G Table 3 ST7 Clock Sources We Hardware Configuration ST7 OSC1 OSC2 External Clock EXTERNAL SOURCE erg OSC osc2 1 Lan _A LOAD CAPACITORS CL 2 2 E O wn a AS E o D o m wn e o External RC Oscillator Internal RC Oscillator 21 135 ST72104G ST72215G ST72216G ST72254G 6 4 CLOCK SECURITY SYSTEM CSS The Clock Security System CSS protects the ST7 against main clock problems To allow the in tegration of the security features in the applica tions itis based on a clock filter control and an In ternal safe oscillator The CSS can be enabled or disabled by option byte 6 4 1 Clock Filter Control The clock filter is based on a clock frequency limi tation function This filter function is able to detect and filter high frequency spikes on the ST7 main clock If the oscillator is not working properly e g work ing at a harmonic frequency of the resonator the current active oscillator clock can be totally fil tered and then no clock signal is available for the ST7 from this oscillator anymore If the original clock source recovers the filtering is stoppe
10. EVF Event flag This bit is set by hardware as soon as an event oc curs Itis cleared by software reading SR2 register in case of error event or as described in Figure 45 It is also cleared by hardware when the interface is disabled PE 0 0 No event 1 One of the following events has occurred BTF 1 Byte received or transmitted ADSL 1 Address matched in Slave mode while ACK 1 SB 1 Start condition generated in Master mode AF 1 No acknowledge received after byte transmission STOPF 1 Stop condition detected in Slave mode ARLO 1 Arbitration lost in Master mode BERR 1 Bus error misplaced Start or Stop condition detected ADD10 1 Master has sent header byte Address byte successfully transmitted in Mas ter mode Bit 6 ADD10 10 bit addressing in Master mode This bit is set by hardware when the master has sent the first byte in 10 bit address mode It is cleared by software reading SR2 register followed by awrite inthe DR register of the second address byte It is also cleared by hardware when the pe ripheral is disabled PE 0 0 No ADD10 event occurred 1 Master has sent first address byte header Bit 5 TRA Transmitter Receiver When BTF is set TRA 1 if a data byte has been transmitted It is cleared automatically when BTF is cleared It is also cleared by hardware after de tection of Stop condition STOPF 1 loss of bus a ST72104G ST72215G
11. PROGRAM MEMORY 4 or 8K Bytes 256 Bytes 6 135 snd vVLvd ANY SSayHdqqv Under software control all devices can be placed in WAIT SLOW or HALT mode reducing power consumption when the application is in idle or standby state The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers enabling the design of highly efficient and compact application code In addition to standard 8 bit data management all ST7 micro controllers feature true bit manipulation 8x8 un signed multiplication and indirect addressing modes For easy reference all parametric data are located in Section 13 on page 96 oat Re PORTB J L 16 BIT TIMER A SE 16 BIT TIMER B PC5 0 6 bits d ST72104G ST72215G ST72216G ST72254G 2 PIN DESCRIPTION Figure 2 28 Pin SO Package Pinout RESET OSCH OSC SS PB7 ISPCLK SCK PB6 ISPDATA MISO PB5 CZ MOSI PB4 E OCMP2_A PB3 ICAP2_A PB2 OCMP1_A PB1 ICAP1_A PBO AIN5 EXTCLK_A PC5 AIN4 OCMP2_B PC4 AIN3 ICAP2_B PC3 ISPSEL PAO HS PA1 HS PA2 HS PA3 HS a 28 PA4 HS SCLI HS HS N Ook Go N PAS HS PAG HS SDAI PA7 HS PCO ICAP1_B AINO PC1 OCMP1_B AIN1 PC2 MCO AIN2 0 o ei0 or eit HS 20mA high sink capability eiX associated external interrupt vector Figure 3 32 Pin SDIP Package Pinout RESET OSC OSCH SS PB7 ISPCLK SCK PB6 ISPDATA MISO PB5 MOSI PB4 NC NC OCMP2_
12. RSM 0 0 000 cee eee eee 19 6 2 1 INtrOQUCUON vota did bed ee gees eee Fe BS eee eee aes 19 6 2 2 Asynchronous External HtEGETon ee 20 6 2 3 Internal Low Voltage Detection HEGET 0 000 c eee eee 20 6 2 4 Internal Watchdog RESET 0 00 eee ete REEE 20 6 3 MULTI OSCILLATOR MO 21 6 4 CLOCK SECURITY SYSTEM CS 22 6 4 1 Clock Filter Control 2 0 co ooo 22 6 4 2 Safe Oscillator Control 22 6 4 3 Low Power Modes 1 1 ee eee nee teens 22 6 44 INterrupis EE 22 6 5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION CRSR 23 6 6 MAIN CLOCK CONTROLLER MG 24 7 INTERRUPTS iii A ee eee ee ee es 25 7 1 NON MASKABLE SOFTWARE INTERRUPT 0000 c cee eee eee 25 7 2 EXTERNAL INTERRUPTS 0 0 00 ccc ee eee ee eee 25 7 38 PERIPHERAL INTERRUPTS 0 0 00 cc ccc ce een ene eens 25 8 POWER SAVING MODES 0 cee ee ees 27 8 1 INTRODUCTION scsi Ged damm be E a hae hi AE sad eee 27 S 2 SLOW MODE rea erdeelt eng ait be ah eee tidak ee ahr ans 27 83 WAM MODE sera ay ee bar ae eg oe eee a ee oman Be ea 28 S4 HALT MODE as rer diia sate sees 28 bs eae a ad da ans 29 DUO PORTS we cece ie eee eee eee ee ie ee a ee ei ee eee eee 30 91 INTRODUCTION 0025020000000 bra bad ounce Rede Set ee deeded 30 9 2 FUNCTIONAL DESCRIPTION 0 0 0 0 c cee tne eens 30 9 2 1 Input Modes ecos Sie d hirad Oe a ed a eae 30 9 2 2 Output MOdeS casaco ic o hha Oe ee ae
13. aC ST SHI 25 _ 13 4 4 Supply and Clock Managers The previous current consumption specified for source current consumption To get the total de the ST7 functional operating modes over tempera vice consumption the two current values must be ture range does not take into account the clock added except for HALT Ge Supply current of internal RC oscillator current of internal RC oscillator EEN LP Low power oscillator 4 amp 5 MP Medium power oscillator MS Medium speed oscillator HS High speed oscillator LVD supply current HALT mode 13 4 5 On Chip Peripherals sel gt O a ee Supply current of resonator oscillator Notes 1 Typical data are based on T 25 C 2 All I O pins in input mode with a static value at Vpp or Vgg no load CSS and LVD disabled Data based on charac terization results tested in production at Vpp max and fopy max 3 Data based on characterization results not tested in production 4 Data based on characterization results done with the external components specified in Section 13 5 3 and Section 13 5 4 not tested in production 5 As the oscillator is based on a current source the consumption does not depend on the voltage 6 Data based on a differential Ipp measurement between reset configuration timer counter running at fopy 4 and timer counter stopped selecting external clock capability Data valid for one timer 7 Data based on a differential Ipp measurem
14. matched the content of the OC2R register To clear this bit first read the SR register then read or write the low byte of the OC2R OC2LR reg ister Bit 2 0 Reserved forced by hardware to 0 a ST72104G ST72215G ST72216G ST72254G INPUT CAPTURE 1 HIGH REGISTER IC1HR Read Only Reset Value Undefined This is an 8 bit read only register that contains the high part of the counter value transferred by the input capture 1 event 7 0 ee ih ee INPUT CAPTURE 1 LOW REGISTER IC1LR Read Only Reset Value Undefined This is an 8 bit read only register that contains the low part of the counter value transferred by the in put capture 1 event 7 0 a EE OUTPUT COMPARE 1 OC1HR Read Write Reset Value 1000 0000 80h This is an 8 bit register that contains the high part of the value to be compared to the CHR register 7 0 so FT tT de OUTPUT COMPARE 1 OC1LR Read Write Reset Value 0000 0000 00h This is an 8 bit register that contains the low part of the value to be compared to the CLR register 7 0 so A ES HIGH REGISTER LOW REGISTER 57 1135 ST72104G ST72215G ST72216G ST72254G 16 BIT TIMER Cont d OUTPUT COMPARE 2 HIGH REGISTER OC2HR Read Write Reset Value 1000 0000 80h This is an 8 bit register that contains the high part of the value to be compared to the CHR register 7 0 he DER Ee OUTPUT COMPARE 2 LOW REGISTER OC2LR Read Write Reset Value 00
15. 14 2 THERMAL CHARACTERISTICS 0 0000 127 14 3 SOLDERING AND GLUEABILITY INFORMATION 0000000 e eee 128 14 4 PACKAGE SOCKET FOOTPRINT PROPOSAL 0 000000 e eee eee 128 15 DEVICE CONFIGURATION AND ORDERING INFORMATION oo ooococco 129 15 11 OPTION BYTES et dake ri ada vee nes 129 15 2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE 130 15 3 DEVELOPMENT TOOLS ocio EE ENEE dE Seer EERE EE eee e 132 15 4 ST 7 APPLICATION NOTES MINN sra pa bebe abate dawn AR ede 133 15 5 TO GETMORE INFORMATION 133 16 SUMMARY OF CHANGES 2 cece eee eee eens 134 Zar 5 135 ST72104G ST72215G ST72216G ST72254G 1 INTRODUCTION The ST72104G ST72215G ST72216G and ST72254G devices are members of the ST7 mi crocontroller family They can be grouped as fol lows ST72254G devices are designed for mid range applications with ADC and C interface capabili ties ST72215 6G devices target the same range of applications but without C interface T72104G devices are for applications that do not need ADC and C peripherals All devices are based on a common industry standard 8 bit core featuring an enhanced instruc tion set The ST72C104G ST72C215G ST72C216G and ST72C254G versions feature single voltage FLASH memory with byte by byte In Situ Pro gramming ISP capability Figure 1 General Block Diagram Internal CLOCK MULTI OSC CLOCK FILTER CONTROL 8 BIT CORE ALU
16. 7 bit addressing mode one address byte is sent In 10 bit addressing mode sending the first byte including the header sequence causes the follow ing event The EVF bit is set by hardware with interrupt generation if the ITE bitis set Then the master waits for a read of the SR1 regis ter followed by a write in the DR register holding the SCL line low see Figure 45 Transfer se quencing EV9 Then the second address byte is sent by the inter face 76 135 After completion of this transfer and acknowledge from the slave if the ACK bit is set The EVF bit is set by hardware with interrupt generation if the ITE bit is set Then the master waits for a read of the SR1 regis ter followed by a write in the CR register for exam ple set PE bit holding the SCL line low see Fig ure 45 Transfer sequencing EV6 Next the master must enter Receiver or Transmit ter mode Note In 10 bit addressing mode to switch the master to Receiver mode software must generate a repeated Start condition and resend the header sequence with the least significant bit set 11110xx1 Master Receiver Following the address transmission and after SR1 and CR registers have been accessed the master receives bytes from the SDA line into the DR reg ister via the internal shift register After each byte the interface generates in sequence Acknowledge pulse if if the ACK bit is set EVF and BTF bits are set by hardwa
17. Direction Register Port C Option Register Reserved 1 Byte Port B Data Register Port B Data Direction Register Port B Option Register Reserved 1 Byte Port A Data Register Port A Data Direction Register Port A Option Register Reserved 21 Bytes ooh rw 00h R W 00h R W 0020h VE MISCR1 Miscellaneous Register 1 SPI Data I O Register SPI Control Register SPI Status Register R W R W Read Only 0024h WATCHDOG WDGCR Watchdog Control Register 0025h EIA CRSR Clock Reset Supply Control Status Register 000x 000x 0026h 0027h I2CCR 12CSR1 l2CSR2 I2CCCR 12COAR1 I2COAR2 l2CDR a Reserved 2 bytes Control Register Status Register 1 Status Register 2 Clock Control Register Own Address Register 1 Own Address Register 2 Data Register Reserved 4 Bytes R W Read Only Read Only R W R W R W R W 11 135 ST72104G ST72215G ST72216G ST72254G steer Pm Register Label TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR TIMER A Register Name Timer A Control Register 2 Timer A Control Register 1 Timer A Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low
18. Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register Reset Status R W R W Read Only Read Only Read Only R W R W Read Only Read Only Read Only Read Only Read Only Read Only R W R W 0040h MA MISCR2 Miscellaneous Register 2 TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR TIMER B Timer B Control Register 2 Timer B Control Register 1 Timer B Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register Reserved 32 Bytes R W R W Read Only Read Only Read Only R W R W Read Only Read Only Read Only Read Only Read Only Read Only R W R W 0070h ADC ADCDR Data Register 00h Read Only 0071h ADCCSR Control Status Register 00h R W Reserved 14 Bytes Legend x undefined R W read write Notes 1 The contents of the I O port DR registers are readable only in output configuration In input configura tion the values of the I O pins
19. ST72215G ST72216G ST72254G 15 4 ST7 APPLICATION NOTES PROGRAMMING AND TOOLS EXAMPLE DRIVERS AN 1048 ST7 timer PWM duty cycle switch for true 0 or 100 duty cycle 15 5 TO GET MORE INFORMATION To get the latest information on this product please use the ST web server http mcu st com STA 133 135 ST72104G ST72215G ST72216G ST72254G 16 SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one E reen RS Power saving mode corrected in Figure 18 on page 28 and Figure 20 on page 29 Feb 00 134 135 ST ST72104G ST72215G ST72216G ST72254G Notes Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics All Rights Reserved Purchase of F
20. T5 TO bits contain the number of increments which represents the time delay before the watchdog produces a reset WATCHDOG CONTROL REGISTER CR pad re 15 ve o ve 0 7 BIT DOWNCOUNTER CLOCK DIVIDER 12288 a 39 135 ST72104G ST72215G ST72216G ST72254G WATCHDOG TIMER Cont d Table 11 Watchdog Timing fcpy 8 MHz CR Register WDG timeout period initial value ms Max FFh Min COh 98 304 1 536 Notes Following a reset the watchdog is disa bled Once activated it cannot be disabled except by a reset The T6 bit can be used to generate a software re set the WDGA bit is set and the T6 bit is cleared 11 1 4 Hardware Watchdog Option If Hardware Watchdog is selected by option byte the watchdog is always active and the WDGA bit in the CR is not used Refer to the device specific Option Byte descrip tion 11 1 5 Low Power Modes WAIT Instruction No effect on Watchdog HALT Instruction If the Watchdog reset on HALT option is selected by option byte a HALT instruction causes an im mediate reset generation if the Watchdog is acti vated WDGA bit is set 11 1 5 1 Using Halt Mode with the WDG option If the Watchdog reset on HALT option is not se lected by option byte the Halt mode can be used when the watchdog is enabled In this case the HALT instruction stops the oscilla tor When the oscillator is stopped the WDG stops counting and is no longer able to genera
21. Threshold Versus Vp and fosc for FLASH devices er eneren desea High Threshold 3 85 405 4 25 e Vv fall Med Threshold 3 50 3 65 3 80 DD Low Threshold 3 00 3 10 3 20 FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA FOR TEMPERATURES HIGHER THAN 85 C FUNCTIONALITY NOT GUARANTEED IN THIS AREA DEVICE pee Se IN THIS AREA GC FUNCTIONAL AREA SUPPLY VOLTAGE V FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA FOR TEMPERATURES HIGHER THAN 85 C FUNCTIONALITY NOT GUARANTEED IN THIS AREA DEVICE UNDER RESET E IN THIS AREA FUNCTIONALITY NOT GUARANTEED IN THIS AREA FOR TEMPERATURES HIGHER THAN 85 C FUNCTIONALITY NOT GUARANTEED IN THIS AREA DEVICE UNDER RESET IN THIS AREA Notes 1 LVD typical data are based on T 25 C They are given only as design guidelines and are not tested 2 Data based on characterization results not tested in production 3 The Vpp rise time rate condition is needed to insure a correct device power on and LVD reset Not tested in production ky 99 135 ST72104G ST72215G ST72216G ST72254G FUNCTIONAL OPERATING CONDITIONS Contd Figure 56 High LVD Threshold Versus Vp and fosc for ROM devices 7 FUNCTIONALITY NOT GUARANTEED IN THIS AREA DEVICE UNDER RESET E IN THIS AREA FUNCTIONAL AREA SUPPLY VOLTAGE V FUNCTIONALITY NOT GUARANTEED IN THIS AREA DEVICE UNDER RESET sE IN THIS AREA FUNCTIONAL AREA SUPPLY VOLTAGE V 2 FUNCTI ONAL
22. and the 4096 CPU cycle delay is used to stabilize the os cillator After the start up delay the CPU resumes OSCILLATOR OFF operation by servicing the interrupt or by fetching PERIPHERALS 2 OFF the reset vector which woke it up see Figure 19 When entering HALT mode the I bit in the CC reg 0 ister is forced to 0 to enable interrupts Therefore if an interrupt is pending the MCU wakes immedi ately In the HALT mode the main oscillator is turned off Hei causing all internal processing to be stopped in cluding the operation of the on chip peripherals lt gt All peripherals are not clocked except the ones which get their clock supply from another clock generator such as an external or auxiliary oscilla tor The compatibility of Watchdog operation with HALT mode is configured by the WDGHALT op tion bit of the option byte The HALT instruction when executed while the Watchdog system is en abled can generate a Watchdog RESET see Section 15 1 OPTION BYTES on page 129 for more details OSCILLATOR PERIPHERALS FETCH RESET VECTOR OR SERVICE INTERRUPT OSCILLATOR ON PERIPHERALS OFF Figure 19 HALT Mode Timing Overview 4096 CPU CYCLE RUN HALT DELAY HALT Notes INSTRUCTION 1 WDGHALLT is an option bit See option byte sec tion for more details 2 Peripheral clocked with an external clock source RESET FETCH can still be active VECTOR 3 Only some specific interrupts can exit the MCU INTERRU
23. create either effective addresses or temporary storage areas for data manipulation The Cross Assembler generates a precede in struction PRE to indicate that the following in struction refers to the Y register The Y register is not affected by the interrupt auto matic procedures not pushed to and popped from the stack Program Counter PC The program counter is a 16 bit register containing the address of the next instruction to be executed by the CPU It is made of two 8 bit registers PCL Program Counter Low which is the LSB and PCH Program Counter High which is the MSB ACCUMULATOR X INDEX REGISTER Y INDEX REGISTER PROGRAM COUNTER CONDITION CODE REGISTER STACK POINTER X Undefined Value d CPU REGISTERS Cont d CONDITION CODE REGISTER CC Read Write Reset Value 111x1xxx The 8 bit Condition Code register contains the in terrupt mask and four flags representative of the result ofthe instruction just executed This register can also be handled by the PUSH and POP in structions These bits can be individually tested and or con trolled by specific instructions Bit 4 H Half carry This bitis set by hardware when a carry occurs be tween bits 3 and 4 of the ALU during an ADD or ADC instruction It is reset by hardware during the same instructions 0 No half carry has occurred 1 A half carry has occurred This bit is tested using the JRH or JRNH instruc tion The H bit is
24. current in SLOW mode 4 see Figure 60 3V lt Vpp lt 3 6V 4 5V lt Vpps5 5V Figure 59 Typical Ipp in RUN vs fepy Figure 60 Typical Ipp in SLOW vs feu IDD mA IDD mA 250kHz AK 31 25kHz 8MHz 2MHz i gt 4MHz E 500kHz 4 4 45 VDD V VDD V Notes 1 Typical data are based on T 25 C Vpp 5V 4 5V lt Vpps5 5V range and Vpp 3 3V 3V lt Vpp lt 3 6V range 2 Data based on characterization results tested in production at Vpp max and fcpy max 3 CPU running with memory access all I O pins in input mode with a static value at Vpp or Vss no load all peripherals in reset state clock input OSC1 driven by external square wave CSS and LVD disabled 4 SLOW mode selected with fopy based on fosc divided by 32 All I O pins in input mode with a static value at Vpp or Vas no load all peripherals in reset state clock input OSC 1 driven by external square wave CSS and LVD disabled STA 101 135 ST72104G ST72215G ST72216G ST72254G SUPPLY CURRENT CHARACTERISTICS Cont d 13 4 2 WAIT and SLOW WAIT Modes Sept Peer D nen Immler fosc 1MHz fopy 500kHz 150 280 fosc 4MHz foru 2MHz 560 900 fosc 1 6MHz fcpy 8MHz 2200 3000 fogc 1MHz fopy 31 25kHz fosc 4MHz fopy 125kHz 90 190 fosc 1 6MHz fcpy 900kHz 340 850 fosc 1MHz fcpy 500kHz 90 200 fosc 4MHz fopy 2MHz 350 550 fosc 16MHZ fopy 8MHz 1370 1900 fosc 1MHz fopy 31 25kHz 10 20 fosc 4MHz fopy 125kHz 50 80 fosc 1 6MHz fcru 5
25. different events on the pin a Falling edge a Rising edge a Falling and rising edge a Falling edge and low level To guarantee correct functionality the sensitivity bits in the MISCR1 register must be modified only when the bit of the CC register is set to 1 inter rupt masked See I O port register and Miscella neous register descriptions for more details on the programming 10 2 I O PORT ALTERNATE FUNCTIONS The MISCR registers manage four I O port miscel laneous alternate functions a Main clock signal fcpy output on PC2 a SPI pin configuration SS pin internal control to use the PB7 I O port function while the SPl is active Master output capan on MOSI pin PB4 deactivated while the SPl is active Slave output capability on MISO pin PB5 de activated while the SPI is active These functions are described in detail in the Sec tion 10 3 MISCELLANEOUS REGISTER DE SCRIPTION on page 37 36 135 Figure 23 Ext Interrupt Sensitivity EXTIT 0 ei0 INTERRUPT SOURCE SENSITIVITY CONTROL MISCR1 ei isto eu SENSITIVITY CONTROL INTERRUPT SOURCE MISCR1 Bi isoo 1S01 INTERRUPT SOURCE SENSITIVITY CONTROL MISCR1 SENSITIVITY CONTROL INTERRUPT SOURCE d MISCELLANEOUS REGISTERS Cont d 10 3 MISCELLANEOUS REGISTER DESCRIPTION MISCELLANEOUS REGISTER 1 MISCR1 Read Write Reset Value 0000 0000 00h 7 0 EN IGE Bit 7 6 1S1 1 0 e 7 sensitivity The in
26. each data byte transfer to allow the CPU to write in the DR register without generating a write colli sion In Master mode Collision in the master device is defined as a write of the DR register while the internal serial clock SCK is in the process of transfer The SS pin signal must be always high on the master device WCOL bit The WCOL bit in the SR register is set if a write collision occurs No SPI interrupt is generated when the WCOL bit is set the WCOL bit is a status flag only Clearing the WCOL bit is done through a software sequence see Figure 41 Figure 41 Clearing the WCOL bit Write Collision Flag Software Sequence Clearing sequence after SPIF 1 end of a data byte transfer ist Step Read SR THEN 2nd Step Read DR WCOL 0 Read SR Write DR SPIF 0 WCOL 0 if no transfer has started WCOL 1 if a transfer has started before the 2nd step Clearing sequence before SPIF 1 during a data byte transfer Read SR Read DR 1st Step 2nd Step 66 135 THEN WCOL 0 Note Writing in DR register in stead of reading in it do not reset WCOL bit d SERIAL PERIPHERAL INTERFACE Cont d 11 3 4 5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low then the MODF bit is set Master mode fault affects the SPI peripheral in the following ways The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set The SPE bit is r
27. eliminates the need for separate transmit empty and receiver full bits A status flag is used to indicate that the I O operation is com plete Four possible data clock timing relationships may be chosen see Figure 40 but master and slave must be programmed with the same timing mode SLAVE MSBit A LSBit 7 8 BIT SHIFT REGISTER i d ST72104G ST72215G ST72216G ST72254G SERIAL PERIPHERAL INTERFACE Conta Figure 38 Serial Peripheral Interface Block Diagram Internal Bus IT E request ite eee SPI STATE EEEL ect SS As E ER E SERIAL CLOCK GENERATOR STA 61 135 ST72104G ST72215G ST72216G ST72254G SERIAL PERIPHERAL INTERFACE Cont d 11 3 4 Functional Description Figure 37 shows the serial peripheral interface SPI block diagram This interface contains 3 dedicated registers A Control Register CR A Status Register SR A Data Register DR Refer to the CR SR and DR registers in Section 11 3 7for the bit definitions 11 3 4 1 Master Configuration In a master configuration the serial clock is gener ated on the SCK pin Procedure Select the SPRO 8 SPR1 bits to define the se rial clock baud rate see CR register Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock see Figure 40 The SS pin must be connected to a high level signal during the complete byte transmit se q
28. even if the timer also uses the 2 output compare functions A In One pulse Mode and PWM mode only the input capture 2 can be used 5 The alternate inputs ICAP1 amp ICAP2 are always directly connected to the timer So any transitions on these pins activate the input cap ture function Moreover if one of the ICAP pin is configured as an input and the second one as an output an interrupt can be generated if the user toggle the output pin and if the ICIE bit is set This can be avoided if the input capture func tion is disabled by reading the IC HR see note 1 6 The TOF bit can be used with interrupt in order to measure event that go beyond the timer range FFFFh d ST72104G ST72215G ST72216G ST72254G 16 BIT TIMER Cont d Figure 30 Input Capture Block Diagram Control Register 1 CR1 EDGE DETECT EDGE DETECT CIRCUIT2 CIRCUIT1 IC2R Register IC1R Register Status Register SR Control Register 2 CR2 Geen TIT let COUNTER Figure 31 Input Capture Timing Diagram Timer clock OLE T b NST COUNTER REGISTER DZ o X ma OK ICAPi PIN SEAS 3 ICAPi FLAG ICAPi REGISTER FFOS Note Active edge is rising edge a 47 135 ST72104G ST72215G ST72216G ST72254G 16 BIT TIMER Cont d 11 2 3 4 Output Compare In this section the index may be 1 or 2 because there are 2 output compare functions in the 16 bit timer This function can be used to control an output waveform o
29. from the SDA line into the DR register via the inter nal shift register After each byte the interface gen erates in sequence Acknowledge pulse if the ACK bit is set LSTA ST72104G ST72215G ST72216G ST72254G EVF and BTF bits are set with an interrupt if the ITE bit is set Then the interface waits for a read of the SR1 reg ister followed by a read of the DR register holding the SCL line low see Figure 45 Transfer se quencing EV2 Slave Transmitter Following the address reception and after SR1 register has been read the slave sends bytes from the DR register to the SDA line via the internal shift register The slave waits for a read of the SR1 register fol lowed by a write in the DR register holding the SCL line low see Figure 45 Transfer sequencing EV3 When the acknowledge pulse is received The EVF and BTF bits are set by hardware with an interrupt if the ITE bitis set Closing slave communication After the last data byte is transferred a Stop Con dition is generated by the master The interface detects this condition and sets EVF and STOPF bits with an interrupt if the ITE bit is set Then the interface waits for a read of the SR2 reg ister see Figure 45 Transfer sequencing EV4 Error Cases BERR Detection of a Stop or a Start condition during a byte transfer In this case the EVF and the BERR bits are set with an interrupt ifthe ITE bit is set If itis a Stop th
30. input capture event occurs on the ICAP pin the input capture detection circuitry is armed Consequent ly when the MCU is woken up by an interrupt with exit from HALT mode capability the ICFibit is set and the counter value present when exiting from HALT mode is captured into the IC R register 16 bit Timer registers are frozen In HALT mode the counter stops counting until Halt mode is exited Counting resumes from the previous count when the MCU is woken up by an interrupt with exit from HALT mode capability or from the counter HALT reset value when the MCU is woken up by a RESET 11 2 5 Interrupts Interrupt Event Input Capture 1 event Counter reset in PWM mode ICF1 Input Capture 2 event ICF2 Output Compare 1 event not available in PWM mode OCF1 OCIE DN Output Compare 2 event not available in PWM mode OCF2 Yes No Timer Overa event TOF TOE ves mo Note The 16 bit Timer interrupt events are connected to the same interrupt vector see Interrupts chap ter These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset RIM instruction 11 2 6 Summary of Timer modes AVAILABLE RESOURCES Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2 input Capture 1 andor 2 Ouiput Compare 1 andor 2 One Pulse Mode Not Recommended Partially PWM Mode Not Recommended 1 See note 4 in Section 11 2 3 5 One Pulse
31. of supply pins of the device 3 parts n 1 supply pin Two models are usually simulated Human Body Model and Machine Model This test conforms to the JESD22 A114A A115A standard See Figure 70 and the following test sequences Human Body Model Test Sequence C is loaded through S1 by the HV pulse gener ator S1 switches position from generator to R Adischarge from C through R body resistance to the ST7 occurs S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST7 is not left in charge state S2 must be opened at least 10ms prior to the delivery of the next pulse Absolute Maximum Machine Model Test Sequence D is loaded through S1 by the HV pulse gener ator S1 switches position from generator to ST7 A discharge from C to the ST7 occurs S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST7 is not left in charge state S2 must be opened atleast 10ms prior to the delivery of the next pulse R machine resistance in series with S2 en sures a slow discharge of the ST7 Symbol Conditions Maximum value I Unit ee static discharge voltage Human Body Model Jess 2000 Electro static discharge voltage Figure 70 Typical Equivalent ESD Circuits HIGH VOLTAGE PULSE GENERATOR A C 100pF HUMAN BODY MODEL Notes HIGH VOLTAGE PULSE GENERATOR C 200pF MACHINE MODEL 1 Data based o
32. set A timer interrupt is generated if TOIE bit of the CR1 register is set and bit of the CC register is cleared If one of these conditions is false the interrupt re mains pending to be issued as soon as they are both true 44 135 Clearing the overflow interrupt request is done in two steps 1 Reading the SR register while the TOF bit is set 2 An access read or write to the CLR register Notes The TOF bit is not cleared by accesses to ACLR register The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times for example to measure elapsed time with out the risk of clearing the TOF bit erroneously The timer is not affected by WAIT mode In HALT mode the counter stops counting until the mode is exited Counting then resumes from the previous count MCU awakened by an interrupt or from the reset count MCU awakened by a Reset 11 2 3 2 External Clock The external clock where available is selected if CCO 1 and CC1 1 in CR2 register The status of the EXEDG bit in the CR2 register determines the type of level transition on the exter nal clock pin EXTCLK that will trigger the free run ning counter The counter is synchronised with the falling edge of the internal CPU clock A minimum of four falling edges of the CPU clock must occur between two consecutive active e
33. the electrical characteristics section for more details External Clock Source In this external clock mode a clock signal Square sinus or triangle with 50 duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground Crystal Ceramic Oscillators This family of oscillators has the advantage of pro ducing a very accurate rate on the main clock of the ST7 The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption In this mode of the multi oscillator the resonator and the load capacitors have to be placed as close as pos sible to the oscillator pins in order to minimize out put distortion and start up stabilization time The loading capacitance values must be adjusted ac cording to the selected oscillator These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start up phase External RC Oscillator This oscillator allows a low cost solution for the main clock of the ST7 using only an external resis tor and an external capacitor The frequency of the external RC oscillator in the range of some MHz is fixed by the resistor and the capacitor values Consequently in this MO mode the accuracy of the clock is directly linked to the accuracy of the discrete components Internal RC Oscillator The internal RC oscillator mode is based on the same principle as the external RC oscillator includ
34. useful in BCD arithmetic subrou tines Bit 3 I Interrupt mask This bit is set by hardware when entering in inter rupt or by software to disable all interrupts except the TRAP software interrupt This bit is cleared by software 0 Interrupts are enabled 1 Interrupts are disabled This bit is controlled by the RIM SIM and IRET in structions and is tested by the JRM and JRNM in structions Note Interrupts requested while is set are latched and can be processed when is cleared By default an interrupt routine is not interruptable because the bit is set by hardware when you en ter it and reset by the IRET instruction at the end of a ST72104G ST72215G ST72216G ST72254G the interrupt routine If the bit is cleared by soft ware in the interrupt routine pending interrupts are serviced regardless of the priority level of the cur rent interrupt routine Bit 2 N Negative This bit is set and cleared by hardware It is repre sentative of the result sign of the last arithmetic logical or data manipulation It is a copy of the 7 bit of the result 0 The result of the last operation is positive or null 1 The result of the last operation is negative i e the most significant bit is a logic 1 This bit is accessed by the JRMI and JRPL instruc tions Bit 1 Z Zero This bit is set and cleared by hardware This bit in dicates that the result of the last arithmetic logical or data manipulati
35. 0 00 eee 54 11 2 7Register Description 0020 ee 55 11 3 SERIAL PERIPHERAL INTERFACE GP 60 TES Nodu escrita rra E RUE RRR Rie he aia ee 60 11 3 2Mam Features ceiba stc dada ke eer ened 60 11 3 3General description sss iait cod wise sees ve ee ge EE EEN a 60 T13 4Functional Description 2 dd deeg tiras ra A eek 62 Ti3 Slow Power Modes ed aaa etc Eege da eek od wee ede SE esas 69 TES GIMErUpIS eg eee eh woe a i ee OE ed A E E Es 69 11 3 7Register Description css Erns TINAASAN eee 70 11 4 120 BUS INTERFACE l2C iseia aiiiar ccc cee eee 73 11 4 AIMPOGUCHION ic eset a i awada ed haa E SES Rw ee eae ene 73 T14 2Main Features vous e Gadde debate aad bees da Bare waded ee wae 73 11 4 3General Description 0 00 0 eee 73 11 4 4Functional Description 75 11 4 5Low Power Modes sss EE EEN a EE EE 79 11 4 Dlpterrupte 2 004 2200 dee ke ee Da eee bee dee SWE Dd a ad 79 11 4 7Register Description 0 00 eee 80 11 5 8 BIT A D CONVERTER ADC 0000 eects 86 TALS AIMUFOGUCUION vivas ota Sean cd diareeha tae E eee Be 86 T15 2Main Features 2 2050 a le a 86 11 5 3Functional Description 202x020 cmiccdr rar rr ra 86 11 5 4Low Power Modes 0c cee cette teenies 87 T15 OlnteMmupls Aide EE dad ener Aah dea od PELE OR be a eee 87 11 5 6Register Description eszedre teris 0 0 ce eee 88 3 135 a ST72104G ST72215G ST72216G ST72254G 12 INSTRUCTION SET WEE 90 124 STZ ADDRESSI
36. 0 2 16 Bit Timer Symbor Fee LS win Typ wax Unt TEA AECI pasetime fi tf dr ETICO E IE FE ECT Ce rear Town Propone O tera Pewee dT SL d 120 135 ST72104G ST72215G ST72216G ST72254G 13 11 COMMUNICATION INTERFACE CHARACTERISTICS 13 11 1 SPI Serial Peripheral Interface Refer to I O port characteristics for more details on Subject to general operating conditions for Von the input output alternate function characteristics fosc and Ta unless otherwise specified SS SCK MOSI MISO Caspar Leger J win wex Unit Master fopy 128 f 8MHz 0 0625 SPI clock frequency CPUT Slave gt fopy 8MHz AECH SPI clock rise and fall time NA see UO port pin description es E ss SS thes SS hold time Slave 120 CC 100 w SCKH w SCKL EE Slave ZC SS Mi Master 100 Data input setup time Slave 100 th Master 100 Data input hold time Slave 100 Data output disable time Save O t Data output valid time 120 mm ES Es Slave after enable edge EN Data output hold time gt Data output valid time Master before capture edge 7 MO Data output hold time Figure 90 SPI Slave Timing Diagram with CPHA 0 di thsi BS a i iii a tiny en wn RKO ee GAR rer Notes 1 Data based on design simulation and or characterisation results not tested in production 2 When no communication is on going the data output line of the SPI MOSI in master mode MISO in slave mode has its al
37. 00 0000 00h This is an 8 bit register that contains the low part of the value to be compared to the CLR register 7 0 ER EES WEE COUNTER HIGH REGISTER CHR Read Only Reset Value 1111 1111 FFh This is an 8 bit register that contains the high part of the counter value 7 0 CIA COUNTER LOW REGISTER CLR Read Only Reset Value 1111 1100 FCh This is an 8 bit register that contains the low part of the counter value A write to this register resets the counter An access to this register after accessing the SR register clears the TOF bit 7 0 CHATENET 58 135 ALTERNATE COUNTER HIGH REGISTER ACHR Read Only Reset Value 1111 1111 FFh This is an 8 bit register that contains the high part of the counter value 7 0 ee ih E ALTERNATE COUNTER LOW REGISTER ACLR Read Only Reset Value 1111 1100 FCh This is an 8 bit register that contains the low part of the counter value A write to this register resets the counter An access to this register after an access to SR register does not clear the TOF bit in SR register 7 0 ml le INPUT CAPTURE 2 HIGH REGISTER IC2HR Read Only Reset Value Undefined This is an 8 bit read only register that contains the high part of the counter value transferred by the Input Capture 2 event 7 0 A A ES INPUT CAPTURE 2 LOW REGISTER IC2LR Read Only Reset Value Undefined This is an 8 bit read only register that contains the low par
38. 00kHz 200 350 Supply current in WAIT mode see Figure 61 Supply current in SLOW WAIT mode see Figure 62 Supply current in WAIT mode see Figure 61 Supply current in SLOW WAIT mode 4 see Figure 62 3V lt Vpp lt 3 6V 4 5V lt Vpp lt 5 5V Figure 61 Typical Ipp in WAIT vs fepy Figure 62 Typical Ipp in SLOW WAIT vs fcpy IDD mA IDD mA 3 0 35 2 2MHz 03 500kHz 125kHz Ka 4MHz 500kHz La Se 250kHz AF 31 25kHz 4 4 5 VDD V VDD V Notes 1 Typical data are based on Ta 25 C Vpp 5V 4 5V lt Vpp lt 5 5V range and Vpp 3 3V 3V lt Vpp lt 3 6V range 2 Data based on characterization results tested in production at Vpp max and fcpy max 3 All I O pins in input mode with a static value at Vpp or Vss no load all peripherals in reset state clock input OSC 1 driven by external square wave CSS and LVD disabled 4 SLOW WAIT mode selected with fcpy based on joer divided by 32 All I O pins in input mode with a static value at VDD OF Vss no load all peripherals in reset state clock input OSC1 driven by external square wave CSS and LVD sabled 102 135 d ST72104G ST72215G ST72216G ST72254G SUPPLY CURRENT CHARACTERISTICS Cont d 13 4 3 HALT Mode Symbol Parameter Conditions Typ Max Unit 40 C lt T lt 85 C 10 Vpp 5 5V 10 40 C lt T a lt 125 C lt 125 C 50 Supply current in HALT mode 2 ESE E uA 40 C lt T lt 85 C 6 Vpp 3 6V
39. 2 pin OLV2 in Output Com pare mode Whatever the value of the OC2E bit the Output Compare 2 function of the timer re mains active 0 OCMP2 pin alternate function disabled I O pin free for general purpose 1 0 1 OCMP2 pin alternate function enabled Bit 5 OPM One Pulse Mode 0 One Pulse Mode is not active 1 One Pulse Mode is active the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin the active transition is given by the IEDG1 bit The length of the generated pulse depends on the contents of the OC1R register 56 135 Bit 4 PWM Pulse Width Modulation 0 PWM mode is not active 1 PWM mode is active the OCMP1 pin outputs a programmable cyclic signal the length of the pulse depends on the value of OC1R register the period depends on the value of OC2R regis ter Bit 3 2 CC 1 0 Clock Control The timer clock mode depends on these bits Table 13 Clock Control Bits External Clock where available Note If the external clock pin is not available pro gramming the external clock configuration stops the counter Bit 1 IEDG2 Input Edge 2 This bit determines which type of level transition on the ICAP2 pin will trigger the capture 0 A falling edge triggers the capture 1 A rising edge triggers the capture Bit 0 EXEDG External Clock Edge This bit determines which type of level transition on the external clock pin EXTCLK will trigger the counter register 0 A falling
40. 2a and a diode from Vss 2b A protection device between Vpp and Vss 4 Figure 72 Positive Stress on a Standard Pad vs Vss Main path o Path to avoid 112 135 d EMC CHARACTERISTICS Cont d True Open Drain Pin Protection The centralized protection 4 is not involved in the discharge of the ESD stresses applied to true open drain pads due to the fact that a P Buffer and diode to Vpp are not implemented An additional local protection between the pad and Vss 5a amp 5b is implemented to completly absorb the posi tive ESD discharge ST72104G ST72215G ST72216G ST72254G Multisupply Configuration When several types of ground Vss Vssa and power supply pp Vppa are available for any reason better noise immunity the structure shown in Figure 76 is implemented to protect the device against ESD Figure 74 Positive Stress on a True Open Drain Pad vs Vss Main path gt Path to avoid EVER a 1131135 ST72104G ST72215G ST72216G ST72254G 13 8 I O PORT PIN CHARACTERISTICS 13 8 1 General Characteristics Subject to general operating conditions for Vpp fosc and Ta unless otherwise specified EE A A O A AAN do REEL E EE CL reee current Dateie LL Kee mere gt 200 Weak pull up equivalent resistor aves ee Er EE es ee LB E VO pin capacitance ce Output high to low level fall time IC 50pF Output low to high level rise time Between 10 and 90 Ex
41. 5 C 20 Write erase cycles Ta 25 C 100 Notes 1 Minimum Vpp supply voltage without losing data stored in RAM in in HALT mode or under RESET or in hardware registers only in HALT mode Guaranteed by construction not tested in production 2 Data based on characterization results tested in production at T 25 C 3 Up to 16 bytes can be programmed at a time for a 4kBytes FLASH block then up to 32 bytes at a time for an 8k device 4 The data retention time increases when the T decreases 5 Data based on reliability test results and monitored in production dl 108 135 13 7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba sis during product characterization 13 7 1 Functional EMS Electro Magnetic Susceptibility Based on a simple running application on the product toggling 2 LEDs through UO ports the product is stressed by two electro magnetic events until a failure occurs indicated by the LEDs ST72104G ST72215G ST72216G ST72254G a ESD Electro Static Discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 1000 4 2 standard a FTB A Burst of Fast Transient voltage positive and negative is applied to Vpp and Vss through a 100pF capacitor until a functional disturbance occurs This test conforms with the IEC 1000 4 4 standard A device reset allows normal operations to be re sumed P
42. 72215G ST72216G ST72254G 15 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro grammable versions FLASH as well as in factory coded versions ROM FLASH devices are shipped to customers with a default content FFh while ROM factory coded parts contain the code supplied by the customer This implies that FLASH devices have to be configured by the customer us ing the Option Bytes while the ROM devices are factory configured 15 1 OPTION BYTES The two option bytes allow the hardware configu ration of the microcontroller to be selected The option bytes have no address in the memory map and can be accessed only in programming mode for example using a standard ST7 program ming tool The default content of the FLASH is fixed to FFh In masked ROM devices the option bytes are fixed in hardware by the ROM code see option list USER OPTION BYTE 0 Bit 7 2 Reserved must always be 1 Bit 1 EXTIT External Interrupt Configuration This option bit allows the external interrupt map ping to be configured as shown in Table 23 Table 23 External Interrupt Configuration External ITO External IT1 EXTIT Ports PB7 PBO Ports PA7 PAO Ports PC5 PCO Ports PA7 PAO Bit 0 FMP Full memory protection This option bit enables or disables external access to the internal program memory read out protec tion Clearing this bit causes the erasing to 00h of the whole memory
43. A PB3 HS SCLI ICAP2_A PB2 OCMP1_A PB1 DAG HS SDAI ICAP 1_A PBO PA7 HS AIN5 EXTCLK_A PC5 PCO ICAP1_B AINO AIN4 OCMP2_B PC4 ei0oreit PC1 OCMP1_B AIN1 AIN3 ICAP2_B PC3 PC2 MCO AIN2 DJ o Om A Go DMD N O HS 20mA high sink capability eiX associated external interrupt vector a 7 135 ST72104G ST72215G ST72216G ST72254G PIN DESCRIPTION Cont d For external pin connection guidelines refer to Section 13 ELECTRICAL CHARACTERISTICS on page 96 Legend Abbreviations for Table 1 Type input O output S supply Input level A Dedicated analog input In Output level C CMOS 0 3Vpp 0 7Vpp Gr CMOS 0 3Vpp 0 7Vpp with input trigger Output level HS 20mA high sink on N buffer only Port and control configuration Input float floating wpu weak pull up int interrupt 1 ana analog Output OD open drain 2 PP push pull Refer to Section 9 UO PORTS on page 30 for more details on the software configuration of the I O ports The RESET configuration of each pin is shown in bold This configuration is valid as long as the device is in reset state Table 1 Device Pin Description Level Function Alternate Function after reset Top priority non maskable interrupt active low External clock input or Resonator oscillator in verter input or resistor input for RC oscillator Resonator oscillator inverter output or capaci tor input for RC oscillator O Oo O e
44. AL CHARACTERIS TICS on page 96 for more details Main Features Supply Manager with main supply low voltage detection LVD m Reset Sequence Manager RSM a Multi Oscillator MO 4Crystal Ceramic resonator oscillators 1 External RC oscillator 1 Internal RC oscillator m Clock Security System CSS Clock Filter Backup Safe Oscillator Figure 8 Clock Reset and Supply Block Diagram CLOCK SECURITY SYSTEM CSS 5 MAIN CLOCK MULTI CLOCK OSCILLATOR CONTROLLER MO FILTER MCC RESET SEQUENCE MANAGER FROM WATCH DOG RSM PERIPHERAL LOW VOLTAGE DETECTOR LVD CSS INTERRUPT a 17 135 ST72104G ST72215G ST72216G ST72254G 6 1 LOW VOLTAGE DETECTOR LVD To allow the integration of power management features in the application the Low Voltage Detec tor function LVD generates a static reset when the Vpp supply voltage is below a Vir reference value This means that it secures the power up as well as the power down keeping the ST7 in reset The V y reference value for a voltage drop is lower than the Mur reference value for power on in order to avoid a parasitic reset when the MCU starts run ning and sinks current on the supply hysteresis The LVD Reset circuitry generates a reset when Vop is below Vit when Vpp is rising Viz when Vpp is falling The LVD function is illustrated in the Figure 9 Provided the minimum Vpp value guaranteed for the oscillato
45. Analog peripheral 8 bit ADC with 6 input channels except on ST72104Gx Device Summary Features ST72104G1 ST72104G2 ST72216G1 ST72215G2 ST72254G1 ST72254G2 Program memory Byles 256 128 Peripherals One 16 bit timer One 16 bit timer Two 16 bit timers Two 16 bit timers SPI SPI ADC SPI ADC SPI C ADC ES Up to 8 MHz with oscillator up to 16 MHz 40 C to 85 C 40 C to 105 125 C optional SOZBTSDPS2 Rev 2 2 February 2000 1 135 This is preliminary information on a new product in development or undergoing evaluation Details are subject to change without notice Table of Contents 1 INTRODUCTI N 0000 a a a 6 2 PIN DESCRIPTION es ee See Seel a do a ee 7 3 REGISTER amp MEMORY MAP occoccococc ee ee eee 10 4 FLASH PROGRAM MEMORY 13 41 INTRODUCTION 4022 4 4244 4ihasehense ook gana D a a i al a dee 13 4 2 MAINFEATURES 0 cc cc cc eee nee e e aa es 13 43 STRUCTURAL ORGANISATION 13 4 4 IN SITU PROGRAMMING ISP MODE 0000000 cece eee ee 13 4 5 MEMORY READ OUT PROTECTION 13 5 CENTRAL PROCESSING UNIT 00 0 cece ee eee eee eee eee 14 Ba INTRODUGHON ss ctas rr cate ete eects be oe eer re pene ee 14 52 MAIN FEATURES ER d asentadas eena Eana aa a a aa dag als iaa 14 53 CPU REGISTERS iis oss oeit eaaa is 2804 da 14 6 SUPPLY RESET AND CLOCK MANAGEMENT 200 e cece eee eee eens 17 6 1 LOW VOLTAGE DETECTOR VD 18 6 2 RESET SEQUENCE MANAGER
46. C Components by STMicroelectronics conveys a license under the Philips DC Patent Rights to use these components in an 12C system is granted provided that the system conforms to the DC Standard Specification as defined by Philips STMicroelectronics Group of Companies Australia Brazil China Finland France Germany Hong Kong India Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom U S A http www st com 135 1135 a WWW ALLDATASHEET COM Copyright O Each Manufacturing Company All Datasheets cannot be modified without permission This datasheet has been download from www AllDataSheet com 100 Free DataSheet Search Site Free Download No Register Fast Search System www AllDataSheet com
47. CCESS VO PORTS y DR REGISTER DATABUS PUSH PULL OUTPUT 2 ALTERNATE ALTERNATE ENABLE OUTPUT Notes 1 When the I O port is in input configuration and the associated alternate function is enabled as an output reading the DR register will read the alternate function output status 2 When the I O port is in output configuration and the associated alternate function is enabled as an input the alternate function reads the pin status given by the DR register content 32 135 dl UO PORTS Cont d CAUTION The alternate function must not be ac tivated as long as the pin is configured as input with interrupt in orderto avoid generating spurious interrupts Analog alternate function When the pin is used as an ADC input the I O must be configured as floating input The analog multiplexer controlled by the ADC registers switches the analog voltage present on the select ed pin to the common analog rail which is connect ed to the ADC input It is recommended not to change the voltage level or loading on any port pin while conversion is in progress Furthermore it is recommended not to have clocking pins located close to a selected an alog pin WARNING The analog input voltage level must be within the limits stated in the absolute maxi mum ratings 9 3 1 0 PORT IMPLEMENTATION The hardware implementation on each I O port de pends onthe settings in the DDR and OR registers and specific feature of the
48. EGISTER REGISTER REGISTER REGISTER 2 1 2 EXTCLKI ALTERNATE pin COUNTER A A REGISTER CC 1 0 TIMER INTERNAL BUS a an UT COMPARE EE E DETECT O EDGE DETECT CIRCUIT2 LLL LATCH e pora o o 0 em b O LATCH2 Status ASTON SR OVERFLOW DETECT CIRCUIT Control Register 1 CR1 Control Register 2 CR2 See note TIMER INTERRUPT Note If IC OC and TO interrupt requests have separate vectors then the last OR is not present See device Interrupt Vector Table 43 135 a ST72104G ST72215G ST72216G ST72254G 16 BIT TIMER Contd 16 bit read sequence from either the Counter Register or the Alternate Counter Register LS Byte is buffered Beginning of the sequence Read MS Byte r At t0 Other 7 instructions Read Returns the buffered At t0 At LS Byte LS Byte value at t0 Sequence completed The user must read the MS Byte first then the LS Byte value is buffered automatically This buffered value remains unchanged until the 16 bit read sequence is completed even if the user reads the MS Byte several times After a complete reading sequence if only the CLR register or ACLR register are read they re turn the LS Byte of the count value at the time of the read Whatever the timer mode used input capture out put compare one pulse mode or PWM mode an overflow occurs when the counter rolls over from FFFFh to 0000h then The TOF bit of the SR register is
49. EGISTER OUTPUT COMPARE REGISTER i OCR OUTPUT COMPARE FLAG i OCF OCMP PIN OLVLi 1 INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER OCR COMPARE REGISTER LATCH OUTPUT COMPARE FLAG i OCF OCMPiPIN OLVLi 1 DEC 2ED3 d 16 BIT TIMER Cont d 11 2 3 5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs This mode is selected via the OPM bit in the CR2 register The one pulse mode uses the Input Capture function and the Output Compare function Procedure To use one pulse mode 1 Load the OC1R register with the value corre sponding to the length of the pulse see the for mula in the opposite column 2 Select the following in the CR1 register Using the OLVL1 bit select the level to be ap plied to the OCMP1 pin after the pulse Using the OLVL2 bit select the level to be ap plied to the OCMP1 pin during the pulse Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit the ICAP1 pin must be configured as floating input 3 Select the following in the CR2 register Set the OC1E bit the OCMP1 pin is then ded icated to the Output Compare 1 function Set the OPM bit Select the timer clock CC 1 0 see Table 13 Clock Control Bits One pulse mode cycle When event occurs on ICAP1 OCMP1 OLVL2 Counter is reset to FFFCh ICF1 bit is set OCM
50. ER Vpp 5V a a Weak pull up equivalent resistor Vin Vss ter A O A ar g External pin or W srosc Leer ENeralresetpuseroaime fC A Leet eres gen duration LI Figure 85 Typical Application with RESET pin INTERNAL RESET CONTROL EXTERNAL RESET CIRCUIT WATCHDOG RESET LVD RESET Notes 1 Unless otherwise specified typical data are based on T 25 C and Vpp 5V 2 Data based on characterization results not tested in production 3 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested 4 The lig current sunk must always respect the absolute maximum rating specified in Section 13 2 2 and the sum of lig I O ports and control pins must not exceed lyss 5 The Ron pull up equivalent resistor is based on a resistive transistor corresponding loy current characteristics de scribed in Figure 86 This data is based on characterization results not tested in production 5 To guarantee the reset of the device a minimum pulse has to be applied to RESET pin 6 All short pulse applied on RESET pin with a duration below th RSTL in can be ignored 7 The reset network the resistor and two capacitors protects the device against parasitic resets especially in a noisy environment 8 The output of the external reset circuit must have an open drain output to drive the ST7 reset pad Otherwise the device can be damaged when the ST7 generates an internal rese
51. Figure 47 Figure 47 ADC Block Diagram 86 135 11 5 3 Functional Description 11 5 3 1 Analog Power Supply Vopa and Vssa are the high and low level refer ence voltage pins In some devices refer to device pin out description they are internally connected to the Von and Vss pins Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines See electrical characteristics section for more de tails ANALOG TO DIGITAL CONVERTER ANNA A DOCODD0O d 8 BIT A D CONVERTER ADC Cont d 11 5 3 2 Digital A D Conversion Result The conversion is monotonic meaning that the re sult never decreases if the analog input does not and never increases if the analog input does not If the input voltage Vam is greater than or equal to Vppa high level voltage reference then the conversion result in the DR register is FFh full scale without overflow indication If input voltage Vain is lower than or equal to Vssa low level voltage reference then the con version result in the DR register is 00h The A D converter is linear and the digital result of the conversion is stored in the ADCDR register The accuracy of the conversion is described in the parametric section Rain is the maximum recommended impedance for an analog input signal If the impedance is too high this will result in a loss of accuracy due to leakage and sampling not bein
52. I O port such as ADC In put or true open drain Switching these I O ports from one state to anoth er should be done in a sequence that prevents un wanted side effects Recommended safe transi tions are illustrated in Figure 22 Other transitions are potentially risky and should be avoided since they are likely to present unwanted side effects such as spurious interrupt generation Table 8 Port Configuration Input DDR 0 floating pull up interrupt push pull feaing oaing nera PA3 0 a i Port A floating pull up interrupt push pull i ST72104G ST72215G ST72216G ST72254G Figure 22 Interrupt I O Port State Transitions GD G GD GD INPUT INPUT floating reset state OUTPUT open drain OUTPUT floating pull up push pull interrupt DDR OR The I O port register configurations are summa rized as follows Interrupt Ports PA7 PA5 PA3 0 PB7 0 PC5 0 with pull up pull up ineroptinpat O O open drain opt St o True Open Drain Interrupt Ports PA6 PA4 without pull up Foaling pa aa floating interrupt input GE ECH open drain high sink ports Output DDR 1 33 135 ST72104G ST72215G ST72216G ST72254G 1 0 PORTS Cont d 9 4 LOW POWER MODES No effect on I O ports External interrupts cause the device to exit from WAIT mode No effect on I O ports External interrupts cause the device to exit from HALT mode 9 5 INTERRUPTS The external in
53. ION BYTE 1 T 0 lt g I ES E 30 n g ER 129 135 ST72104G ST72215G ST72216G ST72254G 15 2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE Customer code is made up of the ROM contents and the list of the selected options if any The ROM contents are to be sent on diskette or by electronic means with the S19 hexadecimal file generated by the development tool All unused bytes must be set to FFh Figure 100 ROM Factory Coded Device Types TEMP DEVICE PACKAGE RANGE XXX a Code name defined by STMicroelectronics The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended The STMicroelectronics Sales Organization will be pleased to provide detailed information on con tractual points 1 standard 0 to 70 C 6 industrial 40 to 85 C 7 automotive 40 to 105 C 3 automotive 40 to 125 C B Plastic DIP M Plastic SOIC ST72104G1 ST72104G2 ST72215G2 ST72216G1 ST72254G1 ST72254G2 Figure 101 FLASH User Programmable Device Types TEMP DEVICE PACKAGE RANGE PS 1 standard O to 70 C 6 industrial 40 to 85 C 7 automotive 40 to 105 C 3 automotive 40 to 125 C B Plastic DIP M Plastic SOIC ST72C104G1 ST72C104G2 ST72C215G2 ST72C216G1 ST72C254G1 ST72C254G2 d 130 135 ST72104G ST72215G ST72216G ST72254G TRANSFER OF CUSTOMER CODE Cont d MICROCONTROLLER OPTION LI
54. ITY NOT GUARANTEED IN THIS AREA DEVICE UNDER FUNCTIONAL AREA RESET IN THIS AREA SUPPLY VOLTAGE V Notes 1 LVD typical data are based on T 25 C They are given only as design guidelines and are not tested 2 The minimum Vpp rise time rate is needed to insure a correct device power on and LVD reset Not tested in production d 100 135 ST72104G ST72215G ST72216G ST72254G 13 4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for vice consumption the two current values must be the ST7 functional operating modes over tempera added except for HALT mode for which the clock ture range does not take into account the clock is stopped source current consumption To get the total de sp Cape a oni AlDD ATa Supply current variation vs temperature Constant Vpp and fcpy 13 4 1 RUN and SLOW Modes Spa TETONAS Contos LC Wax Unit fosc 1MHz fepy 500kHz 500 900 fosc 4MHz fopy 2MHz 1500 2500 fosc 16MHz fopy 8MHz 5600 9000 fosc 1MHz fopy 31 25kHz 150 450 fosc 4MHz fopy 125kHz 250 550 fosc 1 6MHz fcpy 900kHz 670 1250 fosc 1MHz fopy 500kHz 300 550 fosc 4MHz fopy 2MHz 970 1350 fosc 16MHZ fopy 8MHz 3600 4500 fosc 1MHz fopy 31 25kHz 100 250 fosc 4MHz fcpu 1 25kHz 170 300 fosc 1 6MHz fcpy 900kHz 420 700 Supply current in RUN mode 3 see Figure 59 Supply current in SLOW mode see Figure 60 uA Supply current in RUN mode 3 see Figure 59 Supply
55. Mode on page 50 2 See note 5 in Section 11 2 3 5 One Pulse Mode on page 50 3 See note 4 in Section 11 2 3 6 Pulse Width Modulation Mode on page 52 d 54 135 16 BIT TIMER Cont d 11 2 7 Register Description Each Timer is associated with three control and status registers and with six pairs of data registers 16 bit values relating to the two input captures the two output compares the counter and the al ternate counter CONTROL REGISTER 1 CR1 Read Write Reset Value 0000 0000 00h 7 0 ICIEJOCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL 1 Bit 7 ICIE Input Capture Interrupt Enable 0 Interrupt is inhibited 1 A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set Bit 6 OCIE Output Compare Interrupt Enable 0 Interrupt is inhibited 1 A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set Bit 5 TOIE Timer Overflow Interrupt Enable 0 Interrupt is inhibited 1 A timer interrupt is enabled whenever the TOF bit of the SR register is set a ST72104G ST72215G ST72216G ST72254G Bit 4 FOLV2 Forced Output Compare 2 This bit is set and cleared by software 0 No effect on the OCMP2 pin 1 Forces the OLVL2 bit to be copied to the OCMP2 pin if the OC2E bit is set and even if there is no successful comparison Bit 3 FOLV1 Forced Output Compare 1 This bit is set and cleared by software 0 No effect on the OCMP1 pi
56. NG MODES uc seu wae ha a ath gale MN EEN 90 12 1 WAN A 91 CN lun EE 91 ENEE RL sota sica E A A A AAA A E 91 12 1 4Indexed No Offset Short Long 91 12 1 5Indirect Short Long 91 12 1 6Indirect Indexed Short Long 92 12 1 7Relative mode Direct Indirect 92 12 2 INSTRUCTION GROUPS su irua mee ieaiao a eee 93 13 ELECTRICAL CHARACTERISTICS 0002 annann 96 13 1 PARAMETER CONDITIONS 000000 aaa cette 96 13 1 1Minimum and Maximum values 96 13 1 21 YpiCal ValUCS ooo sasaaina dt EH Ee d NEEN Peed eh ede eal ae 96 13 1 SVYpiCal EE 96 13 1 4Loading Capacitor Veo doi ae ea eae ee ee ee elev cee Re ee 96 13 1 5Pin input voltage is win ha ed ed ne ies eo da Ba 96 13 2 ABSOLUTE MAXIMUM RATINGS 2 00000 eee eee ee 97 13 2 1Voltage Characteristics 97 13 2 2Current Characteristics 00 ccc eee ee 97 13 2 3Thermal CharacteristicS siaus yenid duana tap kida a a tae 97 13 3 OPERATING CONDITIONS conta sidad asiri naian ai dE a NI 98 13 3 1General Operating Conditions 98 13 3 20perating Conditions with Low Voltage Detector VD 99 13 4 SUPPLY CURRENT CHARACTERISTICS 0 000 ccc eee eee eee 101 13 4 1RUN and SLOW Modes 00 000 cece eee eee 101 13 4 2WAIT and SLOW WAIT Modes 102 ISA SHALT MOGE cios ana liege St eee NEE EE de Ae 103 13 4 4Supply and Clock Managers 103 13 4 50n Chip Peripherals 0 0 00 cee eae 103 13 5 CLOCK AND TIMING CHARACTERISTICS
57. Negative Injection Current For wtf Dm the typical leakage induced inside the die is 1 6uA and the effect on the ADC accuracy is a loss of 1 LSB for each 10KQ increase of the external analog source impedance This effect on the ADC accuracy has been observed under worst case conditions for injection negative injection injection to an Input with analog capability adjacent to the enabled Analog Input at 5V Vpp supply and worst case temperature 3 Data based on characterization results over the whole temperature range monitored in production 125 135 a ST72104G ST72215G ST72216G ST72254G 14 PACKAGE CHARACTERISTICS 14 1 PACKAGE MECHANICAL DATA Figure 96 32 Pin Shrink Plastic Dual In Line Package es Le OI as loool SIETE NARA 205 955 57 o x20foa0 o 180 1 MANY 1 HOW UU EX 5 0 c ref pe loom al bad Joon res O E A ooo Ted Figure 97 28 Pin Plastic Small Outline Package 300 mil Width Papes ebe Fa lat Jako Fr Pe oss ostfoois 0 020 Pe o2s ose locos foo ONSE RRE Pe 740 _ re0fozora Fa GI D I Si Pa fron foafoa fons nfo forfooo foo po ae Pt oar aooe foo ef O CO Jas CT tee gt d 126 135 ST72104G ST72215G ST72216G ST72254G 14 2 THERMAL CHARACTERISTICS Symbol is Vao e Package thermal resistance junction to ambient SDIP32 60 C W S028 75 Notes 1 The power dissipation is obtained from the formula Pp Pijt P
58. ORTS Cont d Figure 21 I O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS gt P BUFFER see table below Vop ALTERNATE ENABLE PULL UP see table below PULL UP CONDITION sng v Lva N BUFFER DIODES see table below ANALOG CMOS INPUT SCHMITT TRIGGER ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE ei POLARITY SELECTION Table 6 I O Port Mode Options Di o Output Open Drain logic level NT see noie Legend NI not implemented Note The diode to Vpp is not implemented in the Off implemented not activated true open drain pads A local protection between On implemented and activated the pad and Vgs is implemented to protect the de vice against positive stress a 31 135 ST72104G ST72215G ST72216G ST72254G 1 O PORTS Cont d Table 7 I O Port Configurations E Hardware Configuration NOT IMPLEMENTED IN y DR REGISTER ACCESS TRUE OPEN DRAIN Q qEE _ _ gt IS VOPORTS y PULL UP DR WwW eee pecisten REGISTER DATABUS R ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE eix INTERRUPT POLARITY CONDITION SELECTION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN DR REGISTER ACCESS VO PORTS y ye _ _ _ gt _ _ we ES DR REGISTER DATABUS ALTERNATE ALTERNATE ENABLE OUTPUT a kr a ke 5 O Z T oc a Z D o O NOT IMPLEMENTED IN TRUE OPEN DRAIN DR REGISTER A
59. P1 OLVL1 Then on a valid event on the ICAP1 pin the coun ter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin the ICF1 bit is set and the val ue FFFDh is loaded in the IC1R register Because the ICF1 bit is set when an active edge occurs an interrupt can be generated if the ICIE bit is set a ST72104G ST72215G ST72216G ST72254G Clearing the Input Capture interrupt request i e clearing the ICF bit is done in two steps 1 Reading the SR register while the ICF bit is set 2 An access read or write to the IC LR register The OC1R register value required for a specific timing application can be calculated using the fol lowing formula t f a OCR Value RE a PRESC Where t Pulse period in seconds fcpu CPU clock frequency in hertz PRESC Timer prescaler factor 2 4 or 8 depend ing on the CC 1 0 bits see Table 13 Clock Control Bits If the timer clock is an external clock the formula is OCIR t fexT 5 Where t fEXT Pulse period in seconds External timer clock frequency in hertz When the value of the counter is equal to the value of the contents of the OC1R register the OLVL1 bit is output on the OCMP1 pin See Figure 35 Notes 1 The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt 2 When the Pulse Width Modulation PWM and One Pulse Mode OPM bits are both set the PWM mode is the onl
60. PT from HALT mode such as external interrupt Re fer to Table 5 Interrupt Mapping on page 26 for more details 4 Before servicing an interrupt the CC register is pushed on the stack The bit of the CC register is set during the interrupt routine and cleared when the CC register is popped a 29 135 ST72104G ST72215G ST72216G ST72254G 9 1 0 PORTS 9 1 INTRODUCTION The I O ports offer different functional modes transfer of data through digital inputs and outputs and for specific pins external interrupt generation alternate signal input output for the on chip pe ripherals An I O port contains up to 8 pins Each pin can be programmed independently as digital input with or without interrupt generation or digital output 9 2 FUNCTIONAL DESCRIPTION Each port has 2 main registers Data Register DR Data Direction Register DDR and one optional register Option Register OR Each UO pin may be programmed using the corre sponding register bits in the DDR and OR regis ters bit X corresponding to pin X of the port The same correspondence is used for the DR register The following description takes into account the OR register for specific ports which do not pro vide this register refer to the I O Port Implementa tion section The generic I O block diagram is shown in Figure 21 9 2 1 Input Modes The input configuration is selected by clearing the correspondin
61. SD CSSIE Yes No vated as main clock Interrupt Event Figure 13 Clock Filter Function and Safe Oscillator Function CLOCK FILTER FUNCTION x O E q z J2 E 90 KE OS w H pra lt q o 22 135 dl ST72104G ST72215G ST72216G ST72254G 6 5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION CRSR Read Write Reset Value 000x 000x XXh 7 0 LVD CSS CSS WDG RF IE D RF Bit 7 5 Reserved always read as 0 Bit 4 LVDRF LVD reset flag This bit indicates that the last RESET was gener ated by the LVD block It is set by hardware LVD reset and cleared by software writing zero See WDGRF flag description for more details When the LVD is disabled by option byte the LVDRF bit value is undefined Bit 3 Reserved always read as 0 Bit 2 CSSIE Clock security syst interrupt enable This bit enables the interrupt when a disturbance is detected by the clock security system CSSD bit set Itis set and cleared by software 0 Clock security system interrupt disabled 1 Clock security system interrupt enabled Refer to Table 5 Interrupt Mapping on page 26 for more details on the CSS interrupt vector When the CSS is disabled by option byte the CSSIE bit has no effect Bit 1 CSSD Clock security system detection This bit indicates that the safe oscillator of the clock security system block has been selected by hardware due to a disturbance on the main clock signal fosc It is set by hardwa
62. SET pin acts as an output that is pulled low during at least tw RSTL out Figure 12 RESET Sequences I Li tw RSTL out Li Li h RSTL N1 1 le EXTERNAL 1 ES WATCHDOG RESET 20 135 6 2 3 Internal Low Voltage Detection RESET Two different RESET sequences caused by the in ternal LVD circuitry can be distinguished a Power On RESET a Voltage Drop RESET The device RESET pin acts as an output that is pulled low when Vpp lt V r rising edge or Vpp lt V r falling edge as shown in Figure 12 The LVD filters spikes on Vpp larger than Lupp to avoid parasitic resets 6 2 4 Internal Watchdog RESET The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 12 Starting from the Watchdog counter underflow the device RESET pin acts as an output that is pulled low during at least tw rsTLout WATCHDOG RESET DELAY a tw RSTL out WATCHDOG UNDERFLOW _4 INTERNAL RESET 4096 Top y FETCH VECTOR d 6 3 MULTI OSCILLATOR MO The main clock of the ST7 can be generated by four different source types coming from the multi oscillator block m an external source 4 crystalor ceramic resonator oscillators a an external RC oscillator a an internal high frequency RC oscillator Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte The associated hardware configuration are shown in Table 3 Refer to
63. ST Customer Phone No Reference STMicroelectronics references Device ST72104G1 ST72215G2 ST72254G1 ST72104G2 ST72216G1 ST72254G2 Package SDIP32 SO28 with Standard conditioming tube SO28 with Tape amp Reel conditionning External Interrupt ITO interrupt vector Port A IT1 interrupt vector Port B 8 C ITO interrupt vector Port A amp C IT1 interrupt vector Port B Temperature Range 0 C to 70 C 40 C to 105 C 40 C to 85 C 40 C to 125 C Clock Source Selection Resonator LP Low power resonator 1 to 2 MHz MP Medium power resonator 2 to 4 MHz MS Medium speed resonator 4 to 8 MHz HS High speed resonator 8 to 16 MHz RC Network Intemal External External Clock Clock Security System Disabled Enabled Watchdog Selection Software Activation Hardware Activation Halt when Watchdog on Reset No reset Readout Protection Disabled Enabled LVD Reset Disabled Enabled Highest threshold 4 05V 4 30V Medium threshold 3 65V 3 90V Lowest threshold 3 10V 3 35V Comments Supply Operating Range in the application Notes Signature a 131 135 ST72104G ST72215G ST72216G ST72254G 15 3 DEVELOPMENT TOOLS STmicroelectronics offers a range of hardware STMicroelectronics Tools and software development tools forthe ST7 micro Three types of develop
64. ST72216G ST72254G arbitration ARLO 1 or when the interface is disa bled PE 0 0 Data byte received if BTF 1 1 Data byte transmitted Bit 4 BUSY Bus busy This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition It indicates a communication in progress on the bus This information is still updat ed when the interface is disabled PE 0 0 No communication on the bus 1 Communication ongoing on the bus Bit 3 BTF Byte transfer finished This bit is set by hardware as soon as a byte is cor rectly received or transmitted with interrupt gener ation if ITE 1 It is cleared by software reading SR1 register followed by a read or write of DR reg ister It is also cleared by hardware when the inter face is disabled PE 0 Following a byte transmission this bit is set after reception of the acknowledge clock pulse In case an address byte is sent this bit is set only after the EV6 event See Figure 45 BTF is cleared by reading SR1 register followed by writ ing the next byte in DR register Following a byte reception this bit is set after transmission of the acknowledge clock pulse if ACK 1 BTF is cleared by reading SR1 register followed by reading the byte from DR register The SCL line is held low while BTF 1 0 Byte transfer not done 1 Byte transfer succeeded Bit 2 ADSL Address matched Slave mode This bit is set by hardware as
65. TF ST72104G ST72215G ST ST72216G ST72254G 8 BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY ADC 16 BIT TIMERS SPI EC INTERFACES PRELIMINARY DATA Memories 4K or 8K bytes Program memory ROM and single voltage FLASH with read out protec tion and in situ programming remote ISP 256 bytes RAM a Clock Reset and Supply Management Enhanced reset system Enhanced low voltage supply supervisor with 3 programmable levels Clock sources crystal ceramic resonator os cillators or RC oscillators external clock backup Clock Security System Clock out capability 3 Power Saving Modes Halt Wait and Slow a Interrupt Management 7 interrupt vectors plus TRAP and RESET 22 external interrupt lines on 2 vectors a 22 I O Ports a Instruction Set 22 multifunctional bidirectional UO lines 8 bit data manipulation 14 alternate function lines 63 basic instructions 8 high sink outputs 17 main addressing modes m 3 Timers 8 x 8 unsigned multiply instruction Configurable watchdog timer True bit manipulation Two 16 bit timers with 2 input captures 2 out put compares external clock input on one tim Development Tools er PWM and Pulse generator modes one only on ST72104Gx and ST72216G1 Full hardware software development package 2 Communications Interfaces SPI synchronous serial interface DC multimaster interface only on ST72254Gx 1
66. ad C bus mode dress can be selected by software When the C cell is enabled the SDA and SCL The speed of the 12C interface may be selected ports must be configured as floating inputs In this between Standard 0 100KHz and Fast 1 C 100 case the value of the external pull up resistor 400KHz used depends on the application When the EC cell is disabled the SDA and SCL i ins SDA SCL Line Control ports revert to being standard I O port pins Transmitter mode the interface holds the clock line low before transmission to wait for the micro controller to write the byte in the Data Register Receiver mode the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register Figure 44 C Interface Block Diagram DATA REGISTER DR SDA or SDAI DATA CONTROL PM a O DATA SHIFT REGISTER COMPARATOR OWN ADDRESS REGISTER 1 OAR1 OWN ADDRESS REGISTER 2 OAR2 SCL or SCLI CLOCK CONTROL CLOCK CONTROL REGISTER CCR CONTROL REGISTER CR STATUS REGISTER 1 SR1 CONTROL LOGIC STATUS REGISTER 2 SR2 INTERRUPT dl 74 135 DC BUS INTERFACE Cont d 11 4 4 Functional Description Refer tothe CR SR1 and SR2 registers in Section 11 4 7 for the bit definitions By default the IC interface operates in Slave mode M SL bit is cleared except when it initiates a transmit or receive sequence First the interface frequency must be configured using
67. als or another microcontroller Refer to the Pin Description chapter for the device specific pin out 11 3 2 Main Features a Full duplex three wire synchronous transfers Master or slave operation Four master mode frequencies Maximum slave mode frequency fCPU 2 Four programmable master bit rates Programmable clock polarity and phase End of transfer interrupt flag Write collision flag protection Master mode fault protection capability Figure 37 Serial Peripheral Interface Master Slave MASTER MSBit A LSBit i 8 BIT SHIFT see sf SPI CLOCK GENERATOR 60 135 11 3 3 General description The SPI is connected to external devices through 4 alternate pins MISO Master In Slave Out pin MOSI Master Out Slave In pin SCK Serial Clock pin SS Slave select pin A basic example of interconnections between a single master and a single slave is illustrated on Figure 37 The MOSI pins are connected together as are MISO pins In this way data is transferred serially between master and slave most significant bit first When the master device transmits data to a slave device via MOSI pin the slave device responds by sending data to the master device via the MISO pin This implies full duplex transmission with both data out and data in synchronized with the same clock signal which is provided by the master de vice via the SCK pin Thus the byte transmitted is replaced by the byte received and
68. are returned instead of the DR register contents 2 The bits associated with unavailable pins must always keep their reset value d 12 135 4 FLASH PROGRAM MEMORY 4 1 INTRODUCTION FLASH devices have a single voltage non volatile FLASH memory that may be programmed in situ or plugged in a programming tool on a byte by byte basis 4 2 MAIN FEATURES Remote In Situ Programming ISP mode Up to 16 bytes programmed in the same cycle MTP memory Multiple Time Programmable Read out memory protection against piracy 4 3 STRUCTURAL ORGANISATION The FLASH program memory is organised in a single 8 bit wide memory block which can be used for storing both code and data constants The FLASH program memory is mapped in the up per part of the ST7 addressing space and includes the reset and interrupt user vector area 4 4 IN SITU PROGRAMMING ISP MODE The FLASH program memory can be programmed using Remote ISP mode This ISP mode allows the contents of the ST7 program memory to be up dated using a standard ST7 programming tools af ter the device is mounted on the application board This feature can be implemented with a minimum number of added components and board area im pact An example Remote ISP hardware interface to the standard ST7 programming tool is described be low For more details on ISP programming refer to the ST7 Programming Specification Remote ISP Overview The Remote ISP mode is initiated by a speci
69. ave transmitter receiver Master transmitter receiver By default it operates in slave mode The interface automatically switches from slave to master after it generates a START condition and from master to slave in case of arbitration loss or a STOP generation allowing then Multi Master ca pability Communication Flow In Master mode it initiates a data transfer and generates the clock signal A serial data transfer always begins with a start condition and ends with a stop condition Both start and stop conditions are generated in master mode by software In Slave mode the interface is capable of recog nising its own address 7 or 10 bit and the Gen eral Call address The General Call address de tection may be enabled or disabled by software Data and addresses are transferred as 8 bit bytes MSB first The first byte s following the start con dition contain the address one in 7 bit mode two in 10 bit mode The address is always transmitted in Master mode A 9th clock pulse follows the 8 clock cycles of a byte transfer during which the receiver must send an acknowledge bit to the transmitter Refer to Fig ure 43 STOP CONDITION VR02119B 73 135 ST72104G ST72215G ST72216G ST72254G 12C BUS INTERFACE Cont d Acknowledge may be enabled and disabled by The SCL frequency Fse is controlled by a pro software grammable clock divider which depends on the The 12C interface address and or general call
70. byte after the opcode and allows 00 FF addressing space Indexed Short The offset is a byte thus requires only one byte af ter the opcode and allows 00 1FE addressing space Indexed long The offset is a word thus allowing 64 Kbyte ad dressing space and requires 2 bytes after the op code 12 1 5 Indirect Short Long The required data byte to do the operation is found by its memory address located in memory point er The pointer address follows the opcode The indi rect addressing mode consists of two sub modes Indirect short The pointer address is a byte the pointer size is a byte thus allowing 00 FF addressing space and requires 1 byte after the opcode Indirect long The pointer address is a byte the pointer size is a word thus allowing 64 Kbyte addressing space and requires 1 byte after the opcode 91 135 ST72104G ST72215G ST72216G ST72254G ST7 ADDRESSING MODES Cont d 12 1 6 Indirect Indexed Short Long This is a combination of indirect and short indexed addressing modes The operand is referenced by its memory address which is defined by the un signed addition of an index register value X or Y with a pointer value located in memory The point er address follows the opcode The indirect indexed addressing mode consists of two sub modes Indirect Indexed Short The pointer address is a byte the pointer size is a byte thus allowing 00 1FE addressing space an
71. ce is disabled PE 0 Bit O Reserved d ST72104G ST72215G ST72216G ST72254G C BUS INTERFACE Cont d Table 17 DC Register Map and Reset Values Address Register 7 Hex Label 0028h 12CCR PE ENGC START ACK STOP ITE Reset Value 0 0 0 0 0 0 0029h 12CSR1 EVF ADD10 TRA BUSY BTF ADSL M SL SB Reset Value 0 0 0 0 0 0 0 0 002Ah 12CSR2 AF STOPF ARLO BERR GCAL Reset Value 0 0 0 0 0 02Bh 12CCCR FM SM CC6 CC5 CC4 CC3 CC2 CC1 CCO Reset Value 0 0 0 0 0 0 0 0 02Ch 12COAR1 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADDO Reset Value 0 0 0 0 0 0 0 0 12COAR2 FRI FRO ADD9 ADD8 12CDR MSB LSB a 85 135 ST72104G ST72215G ST72216G ST72254G 11 5 8 BIT A D CONVERTER ADC 11 5 1 Introduction The on chip Analog to Digital Converter ADC pe ripheral is a 8 bit successive approximation con verter with internal sample and hold circuitry This peripheral has up to 16 multiplexed analog input channels refer to device pin out description that allow the peripheral to convert the analog voltage levels from up to 16 different sources The result of the conversion is stored in a 8 bit Data Register The A D converter is controlled through a Control Status Register 11 5 2 Main Features a 8 bit conversion Up to 16 channels with multiplexed input Linear successive approximation Data register DR which contains the results Conversion complete status flag On off bit to reduce consumption The block diagram is shown in
72. controller and the serial EC bus It provides both multimaster and slave functions and controls all 1 C bus specific sequencing pro tocol arbitration and timing It supports fast PC mode 400kHz 11 4 2 Main Features a Parallel bus 12C protocol converter a Multi master capability m 7 bit 10 bit Addressing m Transmitter Receiver flag a End of byte transmission flag a Transfer problem detection IC Master Features m Clock generation 12C bus busy flag Arbitration Lost Flag End of byte transmission flag Transmitter Receiver Flag Start bit detection flag a Start and Stop generation UC Slave Features Stop bit detection IC bus busy flag Detection of misplaced start or stop condition Programmable EC Address detection Transfer problem detection End of byte transmission flag a Transmitter Receiver flag 11 4 3 General Description In addition to receiving and transmitting data this interface converts it from serial to parallel format and vice versa using either an interrupt or polled Figure 43 CC BUS Protocol CONDITION a ST72104G ST72215G ST72216G ST72254G handshake The interrupts are enabled or disabled by software The interface is connected to the 1 C bus by a data pin SDAI and by a clock pin SCLI It can be connected both with a standard IC bus and a Fast 12C bus This selection is made by soft ware Mode Selection The interface can operate in the four following modes Sl
73. d au tomatically and the oscillator supplies the ST7 clock 6 4 2 Safe Oscillator Control The safe oscillator of the CSS block is a low fre quency back up clock source see Figure 13 If the clock signal disappears due to a broken or disconnected resonator during a safe oscillator period the safe oscillator delivers a low frequency clock signal which allows the ST7 to perform some rescue operations Automatically the ST7 clock source switches back from the safe oscillator if the original clock source recovers Limitation detection The automatic safe oscillator selection is notified by hardware setting the CSSD bit of the CRSR register An interrupt can be generated if the CS SIE bit has been previously set These two bits are described in the CRSR register description 6 4 3 Low Power Modes ose beses No effect on CSS CSS interrupt cause the device to exit from Wait mode The CRSR register is frozen The CSS in cluding the safe oscillator is disabled until HALT mode is exited The previous CSS configuration resumes when the MCU is woken up by an interrupt with exit from HALT mode capability or from the counter reset value when the MCU is woken up by a 6 4 4 Interrupts The CSS interrupt event generates an interrupt if the corresponding Enable Control Bit CSSIE is set and the interrupt mask in the CC register is re set RIM instruction CSS event detection safe oscillator acti CS
74. d requires 1 byte after the opcode Indirect Indexed Long The pointer address is a byte the pointer size is a word thus allowing 64 Kbyte addressing space and requires 1 byte after the opcode Table 20 Instructions Supporting Direct Indexed Indirect and Indirect Indexed Addressing Modes Instructions ADC ADD SUB SBC Arithmetic Addition subtrac tion operations Short Instructions Only Function BTJT BTJF Bit Test and Jump Opera tions ae le ed Shift and Rotate Operations SWAP Swap Nibbles CALL JP Call or Jump subroutine 92 135 12 1 7 Relative mode Direct Indirect This addressing mode is used to modify the PC register value by adding an 8 bit signed offset to it Available Relative Direct Indirect Instructions CALLR Call Relative The relative addressing mode consists of two sub modes Relative Direct The offset follows the opcode Relative Indirect The offset is defined in memory of which the ad dress follows the opcode d ST72104G ST72215G ST72216G ST72254G 12 2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions The instructions may be subdivided into 13 main groups as illustrated in the following table sar sra mee a o ewe sa 7 Conditional Bra A Tnierupion management DEIER pp Gode Condon Fiagoafcaton sim RIM se e Using a pre byte The instructions are described with one to four by
75. ddress Then the following data bytes are received one by one after reading the DR register 83 135 ST72104G ST72215G ST72216G ST72254G 12C BUS INTERFACE Cont d DC OWN ADDRESS REGISTER OAR1 Read Write Reset Value 0000 0000 00h CC OWN ADDRESS REGISTER OAR2 Read Write Reset Value 0100 0000 40h 7 0 7 0 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADDO jeri emo o fo fo ADD9 ADD8 ES 7 bit Addressing Mode Bit 7 1 ADD7 ADD1 Interface address These bits define the 12C bus address of the inter face They are not cleared when the interface is disabled PE 0 Bit 0 ADDO Address direction bit This bit is don t care the interface acknowledges either 0 or 1 It is not cleared when the interface is disabled PE 0 Note Address 01h is always ignored 10 bit Addressing Mode Bit 7 0 ADD7 ADDO Interface address These are the least significant bits of the DC bus address of the interface They are not cleared when the interface is disabled PE 0 84 135 Bit 7 6 FR1 FRO Frequency bits These bits are set by software only when the inter face is disabled PE 0 To configure the interface to 12C specifed delays select the value corre sponding to the microcontroller frequency Fopy Bit 5 3 Reserved Bit 2 1 ADD9 ADD8 Interface address These are the most significant bits of the CC bus address of the interface 10 bit mode only They are not cleared when the interfa
76. ddress 0100h 16 135 The least significant byte of the Stack Pointer called S can be directly accessed by a LD in struction Note When the lower limit is exceeded the Stack Pointer wraps around to the stack upper limit with out indicating the stack overflow The previously stored information is then overwritten and there fore lost The stack also wraps in case of an under flow The stack is used to save the return address dur ing a subroutine call and the CPU context during an interrupt The user may also directly manipulate the stack by means of the PUSH and POP instruc tions In the case of an interrupt the PCLis stored at the first location pointed to by the SP Then the other registers are stored in the next locations as shown in Figure 7 When an interrupt is received the SP is decre mented and the context is pushed on the stack On return from interrupt the SP is incremented and the context is popped from the stack A subroutine call occupies two locations and an in terrupt five locations in the stack area dl ST72104G ST72215G ST72216G ST72254G 6 SUPPLY RESET AND CLOCK MANAGEMENT The ST72104G ST72215G ST72216G and ST72254G microcontrollers include a range of util ity features for securing the application in critical situations for example in case of a power brown out and reducing the number of external compo nents An overview is shown in Figure 8 See Section 13 ELECTRIC
77. dges of the external clock thus the external clock fre quency must be less than a quarter of the CPU clock frequency d ST72104G ST72215G ST72216G ST72254G 16 BIT TIMER Contd Figure 27 Counter Timing Diagram internal clock divided by 2 erucock U UU UUUUUUUUUUUUT INTERNAL RESET mmerciock Jl JL JL JL JL IL TL TL COUNTER REGISTER FFFD oe 0001 0002 1 0003 TIMER OVERFLOW FLAG TOF Figure 28 Counter Timing Diagram internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG TOF CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG TOF Note The MCU is in reset state when the internal reset signal is high when it is low the MCU is running a 45 135 ST72104G ST72215G ST72216G ST72254G 16 BIT TIMER Cont d 11 2 3 3 Input Capture In this section the index may be 1 or 2 because there are 2 input capture functions in the 16 bit timer The two input capture 16 bit registers IC1R and IC2R are used to latch the value of the free run ning counter after a transition detected by the ICAP pin see figure 5 MS Byte LS Byte ICiR ICIHR ICiLR ICR register is a read only register The active transition is software programmable through the IEDG bit of Control Registers CRA Timing resolution is one count of the free running counter fcpy CC 1 0 Procedure To use the input capture function s
78. e in the same timing mode as the mas ter device CPOL and CPHA bits See Figure 40 The SS pin must be connected to a low level signal during the complete byte transmit se quence Clear the MSTR bit and set the SPE bit to as sign the pins to alternate function In this configuration the MOSI pin is a data input and the MISO pin is a data output Transmit Sequence The data byte is parallel loaded into the 8 bit shift register from the internal bus during a write cycle and then shifted out serially to the MISO pin most significant bit first The transmit sequence begins when the slave de vice receives the clock signal and the most signifi cant bit of the data on its MOSI pin a ST72104G ST72215G ST72216G ST72254G When data transfer is complete The SPIF bit is set by hardware An interrupt is generated if SPIE bit is set and bit in CCR register is cleared During the last clock cycle the SPIF bit is set a copy of the data byte received in the shift register is moved to a buffer When the DR register is read the SPI peripheral returns this buffered value Clearing the SPIF bit is performed by the following software sequence 1 An access to the SR register while the SPIF bit is set 2 A write or a read of the DR register Notes While the SPIF bit is set all writes to the DR register are inhibited until the SR register is read The SPIF bit can be cleared during a second transmis
79. e is activated Procedure To use pulse width modulation mode 1 Load the OC2R register with the value corre sponding to the period of the signal using the formula in the opposite column 2 Load the OC1R register with the value corre sponding to the period of the pulse if OLVL1 0 and OLVL2 1 using the formula in the oppo site column 3 Select the following in the CR1 register Using the OLVL1 bit select the level to be ap plied to the OCMP1 pin after a successful comparison with OC1R register Using the OLVL2 bit select the level to be ap plied to the OCMP1 pin after a successful comparison with OC2R register 4 Select the following in the CR2 register Set OC1E bit the OCMP1 pin is then dedicat ed to the output compare 1 function Set the PWM bit Select the timer clock CC 1 0 see Table 13 Clock Control Bits If OLVL1 1 and OLVL2 0 the length of the posi tive pulse is the difference between the OC2R and OC1R registers If OLVL1 OLVL2 a continuous signal will be seen on the OCMP1 pin Pulse Width Modulation cycle OCMP1 OLVL1 OCMP1 OLVL2 Counter is reset to FFFCh ICF1 bit is set a ST72104G ST72215G ST72216G ST72254G The OCR register value required for a specific tim ing application can be calculated using the follow ing formula t f OCR Value CPU 5 PRESC Where t Signal or pulse period in seconds fopy CPU clock frequency in he
80. e lend a ee ee es 30 9 2 3 Alternate Functions 0 0 0 0 0 ee nee eee eens 30 9 3 VO PORT IMPLEMENTATION 0 00 cc cee eee teenies 33 2 135 STA Table of Contents 9 4 LOW POWER MODES siet DI o aaa 34 9 5 INTERRUPTS ucraniana RA Aa e A e 34 9 6 REGISTER DESCRIPTON prai eee eee 34 10 MISCELLANEOUS REGISTERS 36 10 1 VO PORT INTERRUPT SENSITIVITY 0 0000 eee ee 36 10 2 VO PORT ALTERNATE FUNCTIONS 00 0000 eee eee 36 10 3 MISCELLANEOUS REGISTER DESCRIPTION 2 00200 cece eee eee 37 11 ON CHIP PERIPHERALS 39 11 1 WATCHDOG TIMER DO 39 VASAT LMOGUCTION sa wecs can edo ee eee tl eee ree ees eae OS eee eas 39 11 1 2Main Features steier ee tos ade ea taken gs OP Wa Ladi bad Ge 39 T1 1 3Functional Description ie dees ss eked eset beeen is debbew vee e ein da 39 11 1 4Hardware Watchdog Option 40 11 1 5Low Power Modes 40 TU LGINISTTUpiS scab oe a Pave ache Mae wand ee a Da oa a ba ei 40 11 1 7 Register Description z ss eensd tan ue dE Ee dee a be beds eds 40 142 T6BIETIMER unan a oe ws deg cee dete Ae ten ed yet Rea ao sew ae al Sele a ee 42 all o A nies at Math we Mn ee phates oR EANA ANARA 42 le dan Features suureet iris a NEEN Sa ev tee ace en aod aoe ee ee E 42 T1 2 3Functional Description ie WEE che pate dee ene ie 42 11 2 4Low Powar Modes v2 02 EE Seneca SOR Rea Bae a Rae EE 54 TAO la Die cta A E AS ee ee Pate ise E 54 11 2 6Summary of Timer modes 0
81. ecific I O pins this register is not implement ed In this case the DDR register is enough to se lect the I O pin configuration The OR register allows to distinguish in input mode if the pull up with interrupt capability or the basic pull up configuration is selected in output mode if the push pull or open drain configuration is selected Each bit is set and cleared by software Input mode 0 Floating input 1 Pull up input with or without interrupt Output mode 0 Output open drain with P Buffer unactivated 1 Output push pull when available d ST72104G ST72215G ST72216G ST72254G UO PORTS Cont d Table 9 I O Port Register Map and Reset Values Address Register 7 Hex Label Reset Value of all I O port registers 0000h PCDR 0001h PCDDR 0002h PCOR 0004h 0005h 0006h 0008h 0009h 000Ah a 35 135 ST72104G ST72215G ST72216G ST72254G 10 MISCELLANEOUS REGISTERS The miscellaneous registers allow control over several different features such as the external in terrupts or the I O alternate functions 10 1 I O PORT INTERRUPT SENSITIVITY The external interrupt sensitivity is controlled by the ISxx bits of the Miscellaneous register and the OPTION BYTE This control allows having two ful ly independent external interrupt source sensitivi ties with configurable sources using EXTIT option bit as shown in Figure 23 and Figure 24 Each external interrupt source can be generated on four
82. ecified typical data are based on T 25 C and Vpp Vsg 5V They are given only as design guide lines and are not tested 2 When Vopa and Vgga pins are not available on the pinout the ADC refer to Vpp and Vss 3 Any added external serial resistor will downgrade the ADC accuracy especially for resistance greater than 10kQ Data based on characterization results not tested in production 4 The stabilization time of the AD converter is masked by the first hoan The first conversion after the enable is then always valid d 124 135 ST72104G ST72215G ST72216G ST72254G 8 BIT ADC CHARACTERISTICS Cont d ADC Accuracy Syme Pampers Unit ae EE EEC C 1 Example of an actual transfer curve 2 The ideal transfer curve its _Yopa7 ssa 3 End point correlation line IDEAL 256 E Total Unadjusted Error maximum deviation between the actual and the ideal transfer curves Eo Offset Error deviation between the first actual transition and the first ideal one 2 r yes E esp 3 a transition and the last actual one Ep Differential Linearity Error maximum deviation between actual steps and the ideal one E Integral Linearity Error maximum deviation between any actual transition and the end point I I I Li Li I I I I 1 Eg Gain Error deviation between the last ideal I Li Li I I 1 correlation line I I ipep Vin LSBipEaL 253 254 255 256 DDA Notes 1 ADC Accuracy vs
83. ector of the interrupt to service and the first instruction of the interrupt service routine is fetched refer to the Interrupt Mapping Table for vector address es The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack Note As a consequence of the IRET instruction the bit will be cleared and the main program will resume Priority management By default a servicing interrupt cannot be inter rupted because the bit is set by hardware enter ing in interrupt routine In the case when severalinterrupts are simultane ously pending an hardware priority defines which one will be serviced first see the Interrupt Map ping Table Interrupts and Low power mode All interrupts allow the processor to leave the WAIT low power mode Only external and specifi cally mentioned interrupts allow the processor to leave the HALT low power mode refer to the Exit from HALT column in the Interrupt Mapping Ta ble 7 1 NON MASKABLE SOFTWARE INTERRUPT This interrupt is entered when the TRAP instruc tion is executed regardless of the state of the bit a ST72104G ST72215G ST72216G ST72254G It will be serviced according to the flowchart on Figure 15 7 2 EXTERNAL INTERRUPTS External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the bit is cleared These int
84. edge triggers the counter register 1 A rising edge triggers the counter register d 16 BIT TIMER Cont d STATUS REGISTER SR Read Only Reset Value 0000 0000 00h The three least significant bits are not used 7 0 fen ene oe poe T Bit 7 ICF1 Input Capture Flag 1 0 No input capture reset value 1 An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode To clear this bit first read the SR register then read or write the low byte of the IC1R IC1LR register Bit 6 OCF1 Output Compare Flag 1 0 No match reset value 1 The content of the free running counter has matched the content of the OC1R register To clear this bit first read the SR register then read or write the low byte of the OC 1R OC1LR reg ister Bit 5 TOF Timer Overflow Flag 0 No timer overflow reset value 1 The free running counter rolled over from FFFFh to 0000h To clear this bit first read the SR reg ister then read or write the low byte of the CR CLR register Note Reading or writing the ACLR register does not clear TOF Bit 4 ICF2 Input Capture Flag 2 0 No input capture reset value 1 An input capture has occurred on the ICAP2 pin To clear this bit first read the SR register then read or write the low byte of the IC2R IC2LR register Bit 3 OCF2 Output Compare Flag 2 0 No match reset value 1 The content of the free running counter has
85. egister and the bit is cleared in the CC register CC The OCR register value required for a specific tim ing application can be calculated using the follow ing formula At f Aocr PRESC Where At Output compare period in seconds fepu CPU clock frequency in hertz PRESC Timer prescaler factor 2 4 or 8 de pending on CC 1 0 bits see Table 13 Clock Control Bits If the timer clock is an external clock the formula is A OCR At fey Where At Output compare period in seconds fexr External timer clock frequency in hertz Clearing the output compare interrupt request i e clearing the OCFi bit is done by 1 Reading the SR register while the OCFi bit is set 2 An access read or write to the OCILR register The following procedure is recommended to pre vent the OCF bit from being set between the time it is read and the write to the OCR register Write to the OC HR register further compares are inhibited Read the SR register first step of the clearance of the OCFi bit which may be already set Write to the OCILR register enables the output compare function and clears the OCF bit dl ST72104G ST72215G ST72216G ST72254G 16 BIT TIMER Cont d Notes 1 After a processor write cycle to the OC HR reg Forced Compare Output capability ister the output compare function is inhibited when the FOLVI bit is set by software the OLVL until the OCILR re
86. elect input and can be driven by the master device Figure 39 CPHA SS Timing Diagram MOSI MISO Master SS Slave SS CPHA 0 The master device applies data to its MOSI pin clock edge before the capture clock edge CPHA bitis set The second edge on the SCK pin falling edge if the CPOL bit is reset rising edge if the CPOL bit is set is the MSBit capture strobe Data is latched on the occurrence of the second clock transition No write collision should occur even if the SS pin stays low during a transfer of several bytes see Figure 39 CPHA bit is reset The firstedge on the SCK pin falling edge if CPOL bit is set rising edge if CPOL bit is reset is the MSBit capture strobe Data is latched on the oc currence of the first clock transition The SS pin must be toggled high and low between each byte transmitted see Figure 39 To protect the transmission from a write collision a low value on the SS pin of a slave device freezes the data in its DR register and does not allow it to be altered Therefore the SS pin must be high to write a new data byte in the DR without producing a write collision Slave SS CPHA 1 A_ ___ _ _ __S 64 135 VRO2131A dl ST72104G ST72215G ST72216G ST72254G SERIAL PERIPHERAL INTERFACE Cont d Figure 40 Data Clock Timing Diagram SCLK with CPOL 1 SCLK with Note This figure should not be used as a replacement for parametric informati
87. elect the follow ing in the CR2 register Select the timer clock CC 1 0 see Table 13 Clock Control Bits Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit the ICAP2 pin must be configured as floating input And select the following in the CR1 register Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit the ICAP1pin must be configured as floating input 46 135 When an input capture occurs ICF bit is set The IC R register contains the value of the free running counter on the active transition on the ICAPi pin see Figure 31 A timer interrupt is generated if the ICIE bit is set and the bit is cleared in the CC register Other wise the interrupt remains pending until both conditions become true Clearing the Input Capture interrupt request i e clearing the ICF bit is done in two steps 1 Reading the SR register while the ICF bit is set 2 An access read or write to the IC LR register Notes 1 After reading the IC HR register transfer of input capture data is inhibited and ICFi will never be set until the ICR register is also read 2 The IC R register contains the free running counter value which corresponds to the most recent input capture 3 The 2 input capture functions can be used together
88. en the interface discards the data released the lines and waits for another Start condition If itis a Start then the interface discards the data and waits for the next slave address on the bus AF Detection of anon acknowledge bit In this case the EVF and AF bits are set with an inter rupt if the ITE bit is set Note In both cases SCL line is not held low how ever SDA line can remain low due to possible 0 bits transmitted last It is then necessary to release both lines by software 75 135 ST72104G ST72215G ST72216G ST72254G 12C BUS INTERFACE Cont d How to release the SDA SCL lines Set and subsequently clear the STOP bit while BTF is set The SDA SCL lines are released after the transfer of the current byte 11 4 4 2 Master Mode To switch from default Slave mode to Master mode a Start condition generation is needed Start condition Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode M SL bit set and generates a Start condi tion Once the Start condition is sent The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set Then the master waits for a read of the SR1 regis ter followed by a write in the DR register with the Slave address holding the SCL line low see Figure 45 Transfer sequencing EV5 Slave address transmission Then the slave address is sent to the SDA line via the internal shift register In
89. ent between reset configuration and a permanent SPI master communica tion data sent equal to 55h 8 Data based on a differential pp measurement between reset configuration and DC peripheral enabled PE bit set 9 Data based on a differential Ipp measurement between reset configuration and continuous A D conversions a 103 135 ST72104G ST72215G ST72216G ST72254G 13 5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for Vpp fosc and Ta 13 5 1 General Timings IN E OSC1 input pin high level voltage OSC1 input pin low level voltage E OSCH high or low time see Figure 63 Sen r OSC1 OSC1 rise or fall time EXTERNAL CLOCK SOURCE JULU ST72XXX Notes 1 Data based on typical application software 2 Time measured between interrupt event and interrupt vector fetch Auen is the number of kou cycles needed to finish the current instruction execution 3 Data based on design simulation and or technology characteristics not tested in production d 104 135 ST72104G ST72215G ST72216G ST72254G CLOCK AND TIMING CHARACTERISTICS Cont d 13 5 3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal Ceramic resonator oscillators All the information given in this paragraph are based on characterization results with specified typical external componants In the application the reso close as possible to the osci
90. ent ue gt em gt feat ree RET Tasen Teen INC reenen mex dea E roscado Jer RA rompe aways Y Ar rampa RRE A noveno RA RE RH merma id SRL mera meso EIN EIC CESA FS FEAS ON CTC CISCO SSC id jaw amperes fei Sd jaan umpar o CECI Yd ES RPL EDIC Wer FEAS EN EIN ESTOS RE me Deene Je Y ano mao er gt Y RU smpro 1 RRE AUGE Jump C O metas _ Dag tumpw Z 0 Tiet 94 135 ST72104G ST72215G ST72216G ST72254G INSTRUCTION GROUPS Cont d E O TS w eo TRUE ETICA owe TI me DEI wos E FS ee ee A E ae Pop from the Stack pop reg pop CC EE CC fae ror reacts feo TL a IE ES ero meras Jr Y pe romernes ome feon nc froenn feroase feon _ e resasacrone Jess EC CESTO COI IR IES sm pesen i A Siete L _ fat COUTO CEEI oom fac COUTO CESTA oo _ amer ere CU gt CC O EZ oat baa TN _ fre LIC fw FU IE e swe James wei warmed O Y EC E AAA ky 95 135 ST72104G ST72215G ST72216G ST72254G 13 ELECTRICAL CHARACTERISTICS 13 1 PARAMETER CONDITIONS Unless otherwise specified all voltages are re ferred to Vgg 13 1 1 Minimum and Maximum values Unless otherwise specified the minimum and max imum values are guaranteed in the worst condi tions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at T 25 C and T T amax given by the selected temperat
91. er EV5 EVF 1 SB 1 cleared by reading SR1 register followed by writing DR register EV6 EVF 1 cleared by reading SR1 register followed by writing CR register for example PE 1 EV7 EVF 1 BTF 1 cleared by reading SR1 register followed by reading DR register EV8 EVF 1 BTF 1 cleared by reading SR1 register followed by writing DR register EV9 EVF 1 ADD10 1 cleared by reading SR1 register followed by writing DR register d 78 135 ST72104G ST72215G ST72216G ST72254G DC BUS INTERFACE Cont d 11 4 5 Low Power Modes Mode Description No effect on IC interface E interrupts cause the device to exit from WAIT mode WAIT IC registers are frozen HALT In HALT mode the I C interface is inactive and does not acknowledge data on the bus The 12C interface resumes operation when the MCU is woken up by an interrupt with exit from HALT mode capability 11 4 6 Interrupts Figure 46 Event Flags and Interrupt Generation ADD10 EVF can also be set by EV6 or an error from the SR2 register Interrupt Event 10 bit Address Sent Event Master mode End of Byte Transfer Event Address Matched Event Slave mode Start Bit Generation Event Master mode INTERRUPT Control Acknowledge Failure Event Stop Detection Event Slave mode STOPF Arbitration Lost Event Multimaster configuration Bus Error Event BERR Note The DC interrupt events are connected to the same interrupt vector see Interrup
92. errupts allow the processor to leave the Halt low power mode The external interrupt polarity is selected through the miscellaneous register or interrupt register if available An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine If several input pins connected to the same inter rupt vector are configured as interrupts their sig nals are logically ANDed before entering the edge level detection block Caution The type of sensitivity defined in the Mis cellaneous or Interrupt register if available ap plies to the ei source Incase of an ANDed source as described on the I O ports section a low level on an I O pin configured as input with interrupt masks the interrupt request even in case of rising edge sensitivity 7 3 PERIPHERAL INTERRUPTS Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both The bit of the CC register is cleared The corresponding enable bit is set in the control register If any of these two conditions is false the interrupt is latched and thus remains pending Clearing an interrupt request is done by Writing 0 to the corresponding bit in the status register or Access to the status register while the flag is set followed by a read or write of an associated reg ister Note the clearing sequence re
93. eset This blocks all output from the device and disables the SPI periph eral The MSTR bit is reset thus forcing the device into slave mode Clearing the MODF bit is done through a software sequence 1 A read or write access to the SR register while the MODF bit is set 2 A write to the CR register Notes To avoid any multiple slave conflicts in the case of a system comprising several MCUs the SS pin must be pulled high during the clearing se quence of the MODF bit The SPE and MSTR bits a ST72104G ST72215G ST72216G ST72254G may be restored to their original state during or af ter this clearing sequence Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence In aslave device the MODF bit can not be set but in a multi master configuration the device can be in slave mode with this MODF bit set The MODF bit indicates that there might have been amulti master conflict for system control and allows a proper exit from system operation to a re set or default system state using an interrupt rou tine 11 3 4 6 Overrun Condition An overrun condition occurs when the master de vice has sent several data bytes and the slave de vice has not cleared the SPIF bit issuing from the previous data byte transmitted In this case the receiver buffer contains the byte sent after the SPIF bit was last cleared A read to the DR register retur
94. eset Block Diagram a ST72104G ST72215G ST72216G ST72254G The 4096 CPU clock cycle delay allows the oscil lator to stabilise and ensures that recovery has taken place from the Reset state The RESET vector fetch phase duration is 2 clock cycles Figure 10 RESET Sequence Phases RESET DELAY INTERNAL RESET FETCH 4096 CLOCK CYCLES VECTOR INTERNAL RESET COUNTER WATCHDOG RESET LVD RESET 19 135 ST72104G ST72215G ST72216G ST72254G RESET SEQUENCE MANAGER Cont d 6 2 2 Asynchronous External RESET pin The RESET pin is both an input and an open drain output with integrated Ron weak pull up resistor This pull up has no fixed value but varies in ac cordance with the input voltage It can be pulled low by external circuitry to reset the device See electrical characteristics section for more details A RESET signal originating from an external source must have a duration of at least th RSTL in In order to be recognized This detection is asynchro nous and therefore the MCU can enter reset state even in HALT mode The RESET pin is an asynchronous signal which plays a major role in EMS performance In a noisy environment it is recommended to follow the guidelines mentioned in the electrical characteris tics section Two RESET sequences can be associated with this RESET source short or long external reset pulse see Figure 12 Starting from the external RESET pulse recogni tion the device RE
95. fic se quence on the dedicated ISPSEL pin The Remote ISP is performed in three steps Selection of the RAM execution mode Download of Remote ISP code in RAM Execution of Remote ISP code in RAM to pro gram the user program into the FLASH Remote ISP hardware configuration In Remote ISP mode the ST7 has to be supplied with power Vpp and Vss and a clock signal os cillator and application crystal circuit for example LSTA ST72104G ST72215G ST72216G ST72254G This mode needs five signals plus the Vpp signal if necessary to be connected to the programming tool This signals are RESET device reset Vsg device ground power supply ISPCLK ISP output serial clock pin ISPDATA ISP input serial data pin ISPSEL Remote ISP mode selection This pin must be connected to Vgs on the application board through a pull down resistor If any of these pins are used for other purposes on the application a serial resistor has to be imple mented to avoid a conflict if the other device forces the signal level Figure 5 shows a typical hardware interface to a standard ST7 programming tool For more details on the pin locations refer to the device pinout de scription Figure 5 Typical Remote ISP Interface HE10 CONNECTOR TYPE TO PROGRAMMING TOOL ISPDATA APPLIC ATION 4 5 MEMORY READ OUT PROTECTION The read out protection is enabled through an op tion bit For FLASH devices whe
96. g DDR register bit In this case reading the DR register returns the digital value applied to the external I O pin Different input modes can be selected by software through the OR register Notes 1 Writing the DR register modifies the latch value but does not affect the pin status 2 When switching from input to output mode the DR register has to be written first to drive the cor rect level on the pin as soon as the port is config ured as an output External interrupt function When an I O is configured as Input with Interrupt an event on this I O can generate an external inter rupt request to the CPU Each pin can independently generate an interrupt request The interrupt sensitivity is independently 30 135 programmable using the sensitivity bits in the Mis cellaneous register Each external interrupt vector is linked to a dedi cated group of I O port pins see pinout description and interrupt section If several input pins are se lected simultaneously as interrupt source these are logically ANDed For this reason if one of the interrupt pins is tied low it masks the other ones In case of a floating input with interrupt configura tion special care must be taken when changing the configuration see Figure 22 The external interrupts are hardware interrupts which means that the request latch not accessible directly by the application is automatically cleared when the corresponding interrupt vector i
97. g completed in the alloted time 11 5 3 3 A D Conversion Phases The A D conversion is based on two conversion phases as shown in Figure 48 a Sample capacitor loading duration hoan During this phase the Va input voltage to be measured is loaded into the Cape sample capacitor a A D conversion duration tcony During this phase the A D conversion is computed 8 successive approximations cycles and the Cape sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy While the ADC is on these two phases are contin uously repeated At the end of each conversion the sample capaci tor is kept loaded with the previous measurement load The advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement 11 5 3 4 Software Procedure Refer to the control status register CSR and data register DR in Section 11 5 6 for the bit defini tions and to Figure 48 for the timings ADC Configuration The total duration of the A D conversion is 12 ADC clock periods 1 fapc 2 fopy a ST72104G ST72215G ST72216G ST72254G The analog input ports must be configured as in put no pull up no interrupt Refer to the I O ports chapter Using these pins as analog inputs does not affect the ability of the port to be read as a logic input In the CSR register Select the CH 3 0 bits to a
98. g mode is se lected by default RUN mode This mode drives the device CPU and embedded peripherals by means of a master clock which is based on the main oscillator frequency divided by 2 fcpy From Run mode the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the the oscil lator status Figure 16 Power Saving Mode Transitions SLOW WAIT SLOW WAIT HALT Low POWER CONSUMPTION a 8 2 SLOW MODE This mode has two targets To reduce power consumption by decreasing the internal clock in the device To adapt the internal clock frequency fcpy to the available supply voltage SLOW mode is controlled by three bits in the MISCR1 register the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency fcpy In this mode the oscillator frequency can be divid ed by 4 8 16 or 32 instead of 2 in normal operat ing mode The CPU and peripherals are clocked at this lower frequency Note SLOW WAIT mode is activated when enter ring the WAIT mode while the device is already in SLOW mode Figure 17 SLOW Mode Clock Transitions NORMAL RUN MODE REQUEST NEW SLOW FREQUENCY REQUEST 27 135 ST72104G ST72215G ST72216G ST72254G POWER SAVING MODES Contd 8 3 WAIT MODE Figure 18 WAIT Mode Flow chart WAIT mode places the MCU in a low powe
99. gister is also written bit is copied to the OCMP pin The OLV bit has to 2 If the OCIE bit is not set the OCMPi pin is a be toggled in order to toggle the OCMP pin when general I O port and the OLVLi bit will not it is enabled OCIE bit 1 The OCF bit is then not appear when a match is found but an interrupt set by hardware and thus no interrupt request is could be generated if the OCIE bit is set generated 3 When the timer clock is fopy 2 OCFi and FOLVL bits have no effect in both one pulse mode OCMPi are set while the counter value equals and PWM mode the OCR register value see Figure 33 on page 49 This behaviour is the same in OPM or PWM mode When the timer clock is fcpy 4 fopy 8 or in external clock mode OCFi and OCMPi are set while the counter value equals the OCR regis ter value plus 1 see Figure 34 on page 49 4 The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used 5 The value in the 16 bit OC R register and the OLVi bit should be changed after each suc cessful comparison in order to control an output waveform or establish a new elapsed timeout Figure 32 Output Compare Block Diagram EZE FOLVAFOLVHOLVL2 Status Register SR 49 135 a ST72104G ST72215G ST72216G ST72254G 16 BIT TIMER Cont d Figure 33 Output Compare Timing Diagram frimer fcpu 2 50 135 INTERNAL CPU CLOCK TIMER CLOCK COUNTER R
100. he UO ports or by an exchange of code messages through the serial peripheral interface system The multi master system is principally handled by the MSTR bit in the CR register and the MODF bit in the SR register 68 135 d ST72104G ST72215G ST72216G ST72254G SERIAL PERIPHERAL INTERFACE Contd 11 3 5 Low Power Modes Description WAIT No effect on SPI SPI interrupt events cause the device to exit from WAIT mode SPI registers are frozen HALT In HALT mode the SPI is inactive SPI operation resumes when the MCU is woken up by an interrupt with exit from HALT mode capability 11 3 6 Interrupts Enable Interrupt Event Control Bit SPI End of Transfer Event SPIF SPIE Master Mode Fault Event MODF Note The SPI interrupt events are connected to the same interrupt vector see Interrupts chapter They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset RIM instruction a 69 135 ST72104G ST72215G ST72216G ST72254G SERIAL PERIPHERAL INTERFACE Cont d 11 3 7 Register Description CONTROL REGISTER CR Read Write Reset Value 0000xxxx Oxh 7 0 Bit 7 SPIE Serial peripheral interrupt enable This bit is set and cleared by software 0 Interrupt is inhibited 1 An SPI interrupt is generated whenever SPIF 1 or MODF 1 in the SR register Bit 6 SPE Serial peripheral output enable This bit is set and cleared by sof
101. hronized after a MCU reset as long as the timer clock frequen cies are not modified This description covers one or two 16 bit timers In ST7 devices with two timers register names are prefixed with TA Timer A or TB Timer B 11 2 2 Main Features Programmable prescaler fopy divided by 2 4or8 Overflow status flag and maskable interrupt a External clock input must be at least 4 times slower thanthe CPU clock speed with the choice of active edge Output compare functions with 2 dedicated 16 bit registers 2 dedicated programmable signals 2 dedicated status flags 1 dedicated maskable interrupt m Input capture functions with 2 dedicated 16 bit registers 2 dedicated active edge selection signals 2 dedicated status flags 1 dedicated maskable interrupt a Pulse width modulation mode PWM One pulse mode a 5 alternate functions on I O ports ICAP1 ICAP2 OCMP1 OCMP2 EXTCLK The Block Diagram is shown in Figure 26 Note Some timer pins may not available not bonded in some ST7 devices Refer to the device pin out description When reading an input signal on a non bonded pin the value will always be 1 42 135 11 2 3 Functional Description 11 2 3 1 Counter The main block of the Programmable Timer is a 16 bit free running upcounter and its associated 16 bit registers The 16 bit registers are made up of two 8 bit registers called high amp low Counter Register CR
102. including the option byte 0 Program memory not read out protected 1 Program memory read out protected USER OPTIONBYTE 0 7 LSTA Default 1 1 1 1 1 1 1 1 1 4 1 4 Value USER OPTION BYTE 1 Bit 7 CFC Clock filter control on off This option bit enables or disables the clock filter CF features 0 Clock filter enabled 1 Clock filter disabled Bit 6 4 OSC 2 0 Oscillator selection These three option bits can be used to select the main oscillator as shown in Table 24 Bit 3 2 LVD 1 0 Low voltage detection selection These option bits enable the LVD block with a se lected threshold as shown in Table 25 Bit 1 WDG HALT Watchdog and halt mode This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active 0 No Reset generation when entering Halt mode 1 Reset generation when entering Halt mode Bit 0 WDG SW Hardware or software watchdog This option bit selects the watchdog type 0 Hardware watchdog always enabled 1 Software watchdog to be enabled by software Table 24 Main Oscillator Configuration i ita wie emae 0 x Law Power Resonator 0 1 Medium Power Resonator Al 0 1 Medium Speed Resonator s 0 0 1 High Speed Resonator 45 0 0 0 Table 25 LVD Threshold Configuration Highest Volage Testes aso 1 0 Medium Votage Tresno 405 1 Lowest Votage Threshois 24ey 0 USER OPT
103. ix Version 40 85 aos CS 5 7 BECH 7 Suffix Version 3 Suffix Version Figure 51 fosc Maximum Operating Frequency Versus Vp Supply Voltage for ROM devices 2 FUNCTIONALITY GUARANTEE D IN THIS AREA FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONALITY NOT GUARANTEED IN THIS AREA ee WITH RESONATOR l l a FUNCTIONALITY NOT GUARANTEED IN THIS AREA FOR TEMPERATURE HIGHER THAN 85 C FUNCTIONALITY GUARANTEED IN THIS AREA 9 FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONALITY NOT GUARANTEED IN THIS AREA O o e io WITH RESONATOR l I Il Lb EJlo SUPPLY VOLTAGE V Notes 1 Guaranteed by construction A D operation and resonator oscillator start up are not guaranteed below 1MHz 2 Operating conditions with T a 40 to 125 C 3 FLASH programming tested in production at maximum T with two different conditions Vpp 5 5V fepy 8MHz and Vop 3V feru 4MHz 98 135 STA ST72104G ST72215G ST72216G ST72254G OPERATING CONDITIONS Conta 13 3 2 Operating Conditions with Low Voltage Detector LVD Subject to general operating conditions for Vpp fosc and Ta asp Peer Conditions Win Tye Wax Unt Sere Seeche High Threshold 4 10 4 30 4 50 Vite Vop tise Med Threshold 3 752 3 90 4 05 DD Low Threshold 3 252 3 35 3 45 VI Deeg Voorsetmerae f fo f o ms Tvoo Fitered ch delay on Vog Nor deread oye Wo f 0 e Figure 53 High LVD
104. lave mode This bit is set by hardware when a general call ad dress is detected on the bus while ENGC 1 It is cleared by hardware detecting a Stop condition STOPF 1 or when the interface is disabled PE 0 0 No general call address detected on bus 1 general call address detected on bus d 12C BUS INTERFACE Cont d DC CLOCK CONTROL REGISTER CCR Read Write Reset Value 0000 0000 00h 7 0 Bit 7 FM SM Fast Standard FC mode This bit is set and cleared by software It is not cleared when the interface is disabled PE 0 0 Standard 12 mode 1 Fast C mode Bit 6 0 CC6 CCO 7 bit clock divider These bits select the speed of the bus Esc de pending on the IC mode They are not cleared when the interface is disabled PE 0 Standard mode FM SM 0 Fsc_ lt 100kHz Foci Fopy 2x CC6 CC0 2 Fast mode FM SM 1 Fsc gt 100kHz Fsc Fepy 3x CC6 CC0 2 Note The programmed Fs assumes no load on SCL and SDA lines a ST72104G ST72215G ST72216G ST72254G DC DATA REGISTER DR Read Write Reset Value 0000 0000 00h T 0 Bit 7 0 D7 DO 8 bit Data Register These bits contain the byte to be received or trans mitted on the bus Transmitter mode Byte transmission start auto matically when the software writes in the DR reg ister Receiver mode the first data byte is received au tomatically in the DR register using the least sig nificant bit of the a
105. leared by soft ware reading the resultin the DR register or writing to the CSR register 0 Conversion is not complete 1 Conversion can be read from the DR register Bit 6 Reserved must always be cleared Bit 5 ADON A D Converter On This bitis set and cleared by software 0 A D converter is switched off 1 A D converter is switched on Bit 4 Reserved must always be cleared Bit 3 0 CH 3 0 Channel Selection These bits are set and cleared by software They select the analog input to convert Note The number of pins AND the channel selec tion varies according to the device Refer to the de vice pinout 88 135 Bit 7 0 D 7 0 Analog Converted Value This register contains the converted analog value in the range 00h to FFh Note Reading this register reset the COCO flag d ST72104G ST72215G ST72216G ST72254G 8 BIT A D CONVERTER ADC Cont d Table 18 ADC Register Map and Reset Values Address Register Hex Label ADCDR ADCCSR Ge a 89 135 ST72104G ST72215G ST72216G ST72254G 12 INSTRUCTION SET 12 1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups beer Mode eame IEC CS The ST7 Instruction set is designed to minimize the number of bytes required per instruction To do Table 19 ST7 Addressing Mode Overview ads Pointer Syntax ge rar Address Size Hex Hex H EE E A so most of the add
106. leared by software Used with the SPR2 bit they select one of six baud rates to be used as the serial clock when the device is a master These 2 bits have no effect in slave mode Table 15 Serial Peripheral Baud Rate Seria Cock EA E ou io po hera oo fos o o 1 opus papa O ewa o a o O ovs o jo d SERIAL PERIPHERAL INTERFACE Contd STATUS REGISTER SR Read Only Reset Value 0000 0000 00h 7 0 Bit 7 SPIF Serial Peripheral data transfer flag This bit is set by hardware when a transfer has been completed An interrupt is generated if SPIE 1 in the CR register It is cleared by a soft ware sequence an access to the SR register fol lowed by a read or write to the DR register 0 Data transfer is in progress or has been ap proved by a clearing sequence 1 Data transfer between the device and an exter nal device has been completed Note While the SPIF bit is set all writes to the DR register are inhibited Bit 6 WCOL Write Collision status This bit is set by hardware when a write to the DR register is done during a transmit sequence It is cleared by a software sequence see Figure 41 0 No write collision occurred 1 A write collision has been detected Bit 5 Unused Bit 4 MODF Mode Fault flag This bit is set by hardware when the SS pin is pulled low in master mode see Section 11 3 4 5 Master Mode Fault on page 66 An SPI interrupt can be generated if SPIE 1 i
107. llator pins in order to minimize output distortion and start up stabiliza tion time Refer to the crystal ceramic resonator manufacturer for more details frequency pack age accuracy nator and the load capacitors have to be placed as Symbol O Parame Conditions Win Wax Unit LP Low power oscillator 1 MP Medium power oscillator gt 2 MHz MS Medium speed oscillator gt 4 HS High speed oscillator gt 8 6 Rr ___ Feotbackressor A ST TY LP oscillator MP oscillator MS oscillator HS oscillator Oscillator Frequency 3 Recommanded load capacitances ver sus equivalent serial resistance of the crystal or ceramic resonator Rs LP oscillator MP oscillator 110 MS oscillator 180 HS oscillator 400 OSC2 driving current Reference Characteristic PF PF sh os 30pm O H3Oppmaral Typ Ag 2000 de pelz Afosc 30ppm25 c 30ppM aral Typ Rs 600 mE DESEN EEN Afosc 0 5 tolerance 0 3 ATa 0 3 aging XX correll E Afosc 0 5 tolerance 0 3 ATa 0 3 aging XX correll 5 Afosc 0 5 tolerance 0 5 ATa 0 3 aging XX correll e Afosc 0 5 tolerance 0 3 ATa 0 3 aging X X correll Figure 64 Typical Application with a Crystal or Ceramic Resonator Typical Crystal or Ceramic Resonators Dan ose WHEN RESONATOR WITH INTEGRATE D CAPACITORS CT RESONATOR ST72XXX Notes 1 Resonator characteristics given by the crystal ceramic resonator manufacturer 2 tsu gsc is the typical osci
108. llator start up time measured between Vpp 2 8V and the fetch of the first instruction with a quick Vpp ramp up from 0 to 5V lt 50us 3 The oscillator selection can be optimized in terms of supply current using an high quality resonator with small Rg value Refer to crystal ceramic resonator manufacturer for more details 105 135 LSTA ST72104G ST72215G ST72216G ST72254G CLOCK CHARACTERISTICS Cont d 13 5 4 RC Oscillators The ST7 internal clock can be supplied with an RC or external components selectable by option oscillator This oscillator can be used with internal byte Rex 47KQ Cex 0 pF tsu osc 3 Rex 47KQ Cex 100pF External RC Oscillator Start up Time Rex 10K0 Cey 6 8pF Rex 1 OKQ Cex 470pF Oscillator external resistor e see Figure 67 Oscillator external capacitor Figure 65 Typical Application with RC oscillator INTERNAL RC EI EXTERNAL RC Figure 67 Typical External RC Oscillator fosc MHz 20 Rex 10KOhm Rex 15KOhm gt Rex 22KOhm Se Rex 33KOhm Rex 39KOhm Rex 47KOhm fosc MHz 400 e 85 0 43 So 425 C HE 125 C 15 VDD V Cex pF Notes 1 Data based on characterization results 2 Guaranteed frequency range with the specified Cex and Rex ranges taking into account the device process variation Data based on design simulation 3 Data based on characterization results done with Vpp nominal at 5V not tested in production
109. ment tool are offered by controller family Full details of tools available for ST all of them connect to a PC via a parallel LPT the ST7 from third party manufacturers can be ob port see Table 26 and Table 27 for more details tain from the STMicroelectronics Internet site gt http mcu st com Third Party Tools ACTUM BP COSMIC CMX DATA I O HITEX HIWARE ISYSTEM KANDA LEAP Tools from these manufacturers include C compli ers emulators and gang programmers Table 26 STMicroelectronic Tool Features In Circuit Emulation Programming Capability Software Included Yes Same features as ST7 CD ROM with ST7 Development Kit HDS2 emulator but without Yes DIP packages only ST7 Assembly toolchain logic analyzer STVD7 and WGDB7 powerful Yes powerful emulation Source Level Debugger for Win logic analyzer C compiler demo versions ST Realizer for Win 3 1 and Win ST7 Programming Board Yes All packages lo TO Programming Tools for Win 3 1 Win 95 and NT Table 27 Dedicated STMicroelectronics Development Tools Supported Products ST7 Development Kit ST7 HDS2 Emulator ST7 Programming Board ST72254G1 ST72C254G1 ST72254G2 ST72C254G2 ST7MDT1 EPB2 EU ST7MDT1 DVP2 ST7MDT1 EMU2B ST7MDT1 EPB2 US ST72215G2 ST72C215G2 ST72216G1 ST72C216G1 ST72104G1 ST72C104G1 ST7MDT1 EPB2 UK ST72104G2 ST72C104G2 Note 1 In Situ Programming ISP interface for FLASH devices dl 132 135 ST72104G
110. n 1 Forces OLVL1 to be copied to the OCMP1 pin if the OC1E bit is set and even if there is no suc cessful comparison Bit 2 OLVL2 Output Level 2 This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R reg ister and OCxE is set in the CR2 register This val ue is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode Bit 1 IEDG1 nput Edge 1 This bit determines which type of level transition on the ICAP1 pin will trigger the capture 0 A falling edge triggers the capture 1 A rising edge triggers the capture Bit 0 OLVL1 Output Level 1 The OLVL1 bit is copied to the OCMP1 pin when ever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register 55 135 ST72104G ST72215G ST72216G ST72254G 16 BIT TIMER Cont d CONTROL REGISTER 2 CR2 Read Write Reset Value 0000 0000 00h 7 0 Bit 7 OC1E Output Compare 1 Pin Enable This bit is used only to output the signal from the timer on the OCMP1 pin OLV1 in Output Com pare mode both OLV1 and OLV2 in PWM and one pulse mode Whatever the value of the OC1E bit the Output Compare 1 function of the timer re mains active 0 OCMP1 pin alternate function disabled I O pin free for general purpose 1 0 1 OCMP1 pin alternate function enabled Bit 6 OC2E Output Compare 2 Pin Enable This bit is used only to output the signal from the timer on the OCMP
111. n characterization results not tested in production 110 135 d ST72104G ST72215G ST72216G ST72254G EMC CHARACTERISTICS Cont d 13 7 2 2 Static and Dynamic Latch Up LU 3 complementary static tests are required DLU Electro Static Discharges one positive then one negative test are applied to each pin on 10 parts to assess the latch up performance A supply overvoltage applied to each power supply pin a current injection applied to each input output and configurable I O pin and a power supply switch sequence are performed on each sample This test conforms to the ElA JESD 78 IC latch up standard For more details refer to the AN1181 ST7 application note of 3 samples when the micro is running to assess the latch up performance in dynamic mode Power supplies are set to the typical values the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode This test conforms to the IEC1000 4 2 and SAEJ1752 3 standards and is described in Figure 71 For more details refer to the AN1181 ST7 application note Electrical Sensitivities Symbol Parameter Ta 25 C SS Static latch up class Ta 85 C DLU Dynamic latch up class Vpp 5 5V fosc 4MHz Ta 25 C Figure 71 Ee Diagram of the ESD Generator for DLU Cs 150pF HV RELAY ESD GENERATOR 2 DISCHARGE RETURN CONNECTION Notes 1 Class description A Class is an STMicroelectronics internal
112. n the CR register This bit is cleared by a software sequence An ac cess to the SR register while MODF 1 followed by a write to the CR register 0 No master mode fault detected 1 A fault in master mode has been detected Bits 3 0 Unused a ST72104G ST72215G ST72216G ST72254G DATA I O REGISTER DR Read Write Reset Value Undefined 7 0 or os os 04 09 oe 01 00 The DR register is used to transmit and receive data on the serial bus In the master device only a write to this register will initiate transmission re ception of another byte Notes During the last clock cycle the SPIF bit is set a copy of the received data byte in the shift register is moved to a buffer When the user reads the serial peripheral data I O register the buffer is actually being read Warning A write to the DR register places data directly into the shift register for transmission A write to the the DR register returns the value lo cated inthe buffer and not the contents of the shift register See Figure 38 71 135 ST72104G ST72215G ST72216G ST72254G SERIAL PERIPHERAL INTERFACE Cont d Table 16 SPI Register Map and Reset Values Address Register Hex Label SPIDR MSB 0021h Reset Value Cas SPICR a DS E de 0022h Reset Value SPISR SPIF WCOL MODF LSTA 72 135 11 4 12C BUS INTERFACE 12C 11 4 1 Introduction The 12C Bus Interface serves as an interface be tween the micro
113. n this option is selected the program and data stored in the FLASH memo ry are protected against read out piracy including a re write protection When this protection option is removed the entire FLASH program memory is first automatically erased However the E PROM data memory when available can be protected only with ROM devices 13 135 ST72104G ST72215G ST72216G ST72254G 5 CENTRAL PROCESSING UNIT 5 1 INTRODUCTION This CPU has a full 8 bit architecture and contains six internal registers allowing efficient 8 bit data manipulation 5 2 MAIN FEATURES 63 basic instructions Fast 8 bit by 8 bit multiply 17 main addressing modes Two 8 bit index registers 16 bit stack pointer Low power modes Maskable hardware interrupts Non maskable software interrupt 5 3 CPU REGISTERS The 6 CPU registers shown in Figure 6 are not present in the memory mapping and are accessed by specific instructions Figure 6 CPU Registers RESET VALUE XXh 7 RESET VALUE XXh 7 RESET VALUE XXh 15 817 0 RESET VALUE RESET VECTOR FFFEh FFFFh T 0 111 fu n z 0 RESET VALUE 1 1 1 X 1 X XX 15 817 0 RESET VALUE STACK HIGHER ADDRESS 14 135 Accumulator A The Accumulator is an 8 bit general purpose reg ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data Index Registers X and Y In indexed addressing modes these 8 bit registers are used to
114. ns this byte All other bytes are lost This condition is not detected by the SPI peripher al 67 135 ST72104G ST72215G ST72216G ST72254G SERIAL PERIPHERAL INTERFACE Cont d 11 3 4 7 Single Master and Multimaster Configurations There are two types of SPI systems Single Master System Multimaster System Single Master System A typical single master system may be configured using an MCU as the master and four MCUs as slaves see Figure 42 The master device selects the individual slave de vices by using four pins of a parallel port to control the four SS pins of the slave devices The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time thus disabling the slave devices Note To prevent a bus conflict on the MISO line the master allows only one active slave device during a transmission Figure 42 Single Master Configuration For more security the slave device may respond to the master with the received data byte Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are con nected and the slave has not written its DR regis ter Other transmission security methods can use ports for handshake lines or data bytes with com mand fields Multi master System A multi master system may also be configured by the user Transfer of master control could be im plemented using a handshake method through t
115. o Parameter Conditions s Vreso Voltage limits to be applied on any E T pin Vpp 5V anne r fosc 8MHz Vreso to induce a functional disturbance conforms to IEC 1000 4 2 Fast transient voltage burst limits to be ap A Vop 5V Ta 25 C f 8MHz VreT8 plied through 100pF on Vpp and Vpp pins Neo Hs IEC reen to induce a functional disturbance ST72XXX ST7 DIGITAL NOISE FILTERING E POWER SUPPLY SOURCE NOISE 4 FILTERING a Notes 1 Data based on characterization results not tested in production 2 The suggested 10nF and 0 1uF decoupling capacitors on the power supply lines are proposed as a good price vs EMC performance tradeoff They have to be put as close as possible to the device power supply pins Other EMC recommen dations are given in other sections I Os RESET OSCx pin characteristics 109 135 a ST72104G ST72215G ST72216G ST72254G EMC CHARACTERISTICS Cont d 13 7 2 Absolute Electrical Sensitivity Based on three differenttests ESD LU and DLU using specific measurement methods the product is stressed in order to determine its performance in terms of electrical sensitivity For more details re fer to the AN1181 ST7 application note 13 7 2 1 Electro Static Discharge ESD Electro Static Discharges 3 positive then 3 nega tive pulses separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends of the number
116. oftware reading SR2 register or by hardware when the interface is disabled PE 0 The SCL line is not held low while AF 1 0 No acknowledge failure 1 Acknowledge failure Bit 3 STOPF Stop detection Slave mode This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge if ACK 1 An interrupt is generated if ITE 1 It is cleared by software reading SR2 register or by hardware when the interface is disabled PE 0 The SCL line is not held low while STOPF 1 0 No Stop condition detected 1 Stop condition detected 82 135 Bit 2 ARLO Arbitration lost This bit is set by hardware when the interface los es the arbitration of the bus to another master An interrupt is generated if ITE 1 It is cleared by soft ware reading SR2 register or by hardware when the interface is disabled PE 0 After an ARLO event the interface switches back automatically to Slave mode M SL 0 The SCL line is not held low while ARLO 1 0 No arbitration lost detected 1 Arbitration lost detected Bit 1 BERR Bus error This bit is set by hardware when the interface de tects a misplaced Start or Stop condition An inter rupt is generated if ITE 1 Itis cleared by software reading SR2 register or by hardware when the in terface is disabled PE 0 The SCL line is not held low while BERR 1 0 No misplaced Start or Stop condition 1 Misplaced Start or Stop condition Bit 0 GCAL General Call S
117. on Refer to the Electrical Characteristics chapter VRO2131B TT 65 135 ST72104G ST72215G ST72216G ST72254G SERIAL PERIPHERAL INTERFACE Cont d 11 3 4 4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is tak ing place with an external device When this hap pens the transfer continues uninterrupted and the software write will be unsuccessful Write collisions can occur both in master and slave mode Note a read collision will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU oper ation In Slave mode When the CPHA bit is set The slave device will receive a clock SCK edge prior to the latch of the first data transfer This first clock edge will freeze the data in the slave device DR register and output the MSBit on to the exter nal MISO pin of the slave device The SS pin low state enables the slave device but the output of the MSBit onto the MISO pin does not take place until the first data transfer clock edge When the CPHA bit is reset Data is latched on the occurrence of the first clock transition The slave device does not have any way of knowing when that transition will occur therefore the slave device collision occurs when software attempts to write the DR register after its SS pin has been pulled low For this reason the SS pin mustbe high between
118. on is zero 0 The result of the last operation is different from zero 1 The result of the last operation is zero This bit is accessed by the JREQ and JRNE test instructions Bit 0 C Carry borrow This bit is set and cleared by hardware and soft ware It indicates an overflow or an underflow has occurred during the last arithmetic operation 0 No overflow or underflow has occurred 1 An overflow or underflow has occurred This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions It is also affected by the bit test and branch shift and rotate instructions 15 135 ST72104G ST72215G ST72216G ST72254G CENTRAL PROCESSING UNIT Cont d Stack Pointer SP Read Write Reset Value 01 7Fh 15 8 4 7 0 se ses ses see see ses sro The Stack Pointer is a 16 bit register which is al ways pointing to the next free location in the stack It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack see Figure 7 Since the stack is 128 bytes deep the 9th most significant bits are forced by hardware Following an MCU Reset or after a Reset Stack Pointer in struction RSP the Stack Pointer contains its re set value the SP6 to SPO bits are set which is the stack higher address Figure 7 Stack Manipulation Example CALL Interrupt Subroutine Stack Higher Address 017Fh Stack Lower A
119. or extended periods may affect device reliability Maximum value Unit el Vsg 0 3t0 Vpp 0 3 SCH 3 Electro static discharge voltage Human Body Model see Section 13 7 2 Absolute Elec Electro static discharge voltage Machine Model trical Sensitivity on page 110 13 2 2 an Characteristics symbol Jime Meios inn ia Toa cen ito Voy power ires sow O ooo ves Total currentoutaf Ves ground imes ro w EE Output current sunk by any high sink UO pin 50 Output current source by any l Os and control pin gt m nies current on ISESE pin 2 WH Injected current on OSC1 and OSC2 pins Injected current on any other pin 5 amp 6 Total injected current sum of all I O and control pins gt 13 2 3 Thermal Characteristics Storage temperature range 65 to 150 ise junction temperature see Section 14 2 THERMAL CHARACTERISTICS on page 127 Notes 1 Directly connecting the RESET and I O pins to Vpp or Vss could damage the device if an unintentional internal reset is generated or an unexpected change of the I O configuration occurs for example due to a corrupted program counter To guarantee safe operation this connection has to be done through a pull up or pull down resistor typical 4 7kQ for RESET 10kQ for I Os Unused I O pins must be tied in the same way to Vpp or Vgg according to their reset configuration 2 When the current limitation is not possible the Viy absolute maximum ra
120. port where Pyr is the chip internal power IppxVpp and PponT is the port power dissipation determined by the user 2 The average chip junction temperature can be obtained from the formula Ty Tq Pp x RthJA 127 135 a ST72104G ST72215G ST72216G ST72254G 14 3 SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only Recommended glue for SMD plastic packages as design guidelines in Figure 98 and Figure 99 dedicated to molding compound with silicone m Heraeus PD945 PD955 m Loctite 3615 3298 Figure 98 Recommended Wave Soldering Profile with 37 Sn and 63 Pb COOLING PHASE 200 ER ROOM TEMPERATURE SOLDERING 150 A PHASE Temp C 100 50 Time sec Tmax 220 5 C for 25 sec 150 sec above 183 C 90 sec at 125 C Temp C 100 ramp down natural ramp up 2 C sec max 2 C sec for 50sec Time sec 400 14 4 PACKAGE SOCKET FOOTPRINT PROPOSAL Table 21 Suggested List of SDIP32 Socket Types Same Package Probe Adaptor Socket Reference Footprint Socket Type SDIP32 EMU PROBE TEXTOOL 232 1291 00 Textool Table 22 Suggested List of SO28 Socket Types Same Package Probe Adaptor Socket Reference Footprint Socket Type ENPLAS OTS 28 1 27 04 OTS 28 1 27 04 S028 FENPLAS _OTS 28 1 27 04 o JO P YAMAICHI 1C51 0282 334 1 Clamshell EMU PROBE Adapter from SO28 to SDIP32 footprint delivered with emulator SMD to SDIP 128 135 STA ST72104G ST
121. r con OSCILLATOR ON sumption mode by stopping the CPU PERIPHERALS ON This power saving mode is selected by calling the WFI INSTRUCTION WEIT ST7 software instruction 0 All peripherals remain active During WAIT mode the bit of the CC register is forced to 0 to enable all interrupts All other registers and memory re main unchanged The MCU remains in WAIT mode until an interrupt or Reset occurs whereup on the Program Counter branches to the starting address of the interrupt or Reset service routine The MCU will remain in WAIT mode until a Reset or an Interrupt occurs causing it to wake up OSCILLATOR ON Refer to Figure 18 PERIPHERALS OFF ON 1 OSCILLATOR PERIPHERALS FETCH RESET VECTOR OR SERVICE INTERRUPT Note 1 Before servicing an interrupt the CC register is pushed on the stack The bit of the CC register is set during the interrupt routine and cleared when the CC register is popped d 28 135 ST72104G ST72215G ST72216G ST72254G POWER SAVING MODES Contd 8 4 HALT MODE Figure 20 HALT Mode Flow chart The HALT mode is the lowest power consumption mode of the MCU It is entered by executing the HALT INSTRUCTION ST7 HALT instruction see Figure 20 The MCU can exit HALT mode on reception of ei ther a specific interrupt see Table 5 Interrupt Mapping on page 26 or a RESET When exiting DISABLE HALT mode by means of a RESET or an interrupt the oscillator is immediately turned on
122. r frequency is below Vr the MCU can only be in two modes under full software control in static safe reset Figure 9 Low Voltage Detector vs Reset In these conditions secure operation is always en sured for the application without the need for ex ternal reset hardware During a Low Voltage Detector Reset the RESET pin is held low thus permitting the MCU to reset other devices Notes 1 The LVD allows the device to be used without any external RESET circuitry 2 Three different reference levels are selectable through the option byte according to the applica tion requirement LVD application note Application software can detect a reset caused by the LVD by reading the LVDRF bit in the CRSR register This bit is set by hardware when a LVD reset is generated and cleared by software writing zero 18 135 d 6 2 RESET SEQUENCE MANAGER RSM 6 2 1 Introduction The reset sequence manager includes three RE SET sources as shown in Figure 11 a External RESET source pulse a Internal LVD RESET Low Voltage Detection a Internal WATCHDOG RESET These sources act on the RESET pin and it is al ways kept low during the delay phase The RESET service routine vector is fixed at ad dresses FFFEh FFFFh in the ST7 memory map The basic RESET sequence consists of 3 phases as shown in Figure 10 a Delay depending on the RESET source 4096 CPU clock cycle delay a RESET vector fetch Figure 11 R
123. r indicate when a period of time has elapsed When a match is found between the Output Com pare register and the free running counter the out put compare function Assigns pins with a programmable value if the OCIE bit is set Sets a flag in the status register Generates an interrupt if enabled Two 16 bit registers Output Compare Register 1 OC1R and Output Compare Register 2 OC2R contain the value to be compared to the counter register each timer clock cycle MS Byte LS Byte OCH OCILR These registers are readable and writable and are not affected by the timer hardware A reset event changes the OCR value to 8000h Timing resolution is one count of the free running counter fcpu ccrt 0 OCiR Procedure To use the output compare function select the fol lowing in the CR2 register Set the OCIE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal Select the timer clock CC 1 0 see Table 13 Clock Control Bits And select the following in the CR1 register Select the OLVL bit to applied to the OCMP pins after the match occurs Set the OCIE bit to generate an interrupt if it is needed When a match is found between OCRi register and CR register OCFi bit is set 48 135 The OCMP pin takes OLVL bit value OCMP pin latch is forced low during reset A timer interrupt is generated if the OCIE bit is set in the CR2 r
124. re and cleared by reading the CRSR register when the original oscil lator recovers 0 Safe oscillator is not active 1 Safe oscillator has been activated When the CSS is disabled by option byte the CSSD bit value is forced to 0 Bit 0 WDGRF Watchdog reset flag This bit indicates that the last RESET was gener ated by the watchdog peripheral It is set by hard ware Watchdog RESET and cleared by software writing zero or an LVD RESET to ensure a sta ble cleared state of the WDGRF flag when the CPU starts Combined with the LVDRF flag information the flag description is given by the following table RESET Sources LVDRF WDGRF edema RESET en TOTO Watchdog PO Application notes The LVDRF flag is not cleared when another RE SET type occurs external or watchdog the LVDRF flag remains set to keep trace of the origi nal failure In this case a watchdog reset can be detected by software while an external reset can not Table 4 Clock Reset and Supply Register Map and Reset Values Pr te e Address Register Hex Label CRSR 0025h Reset Value a LVDRF CSSIE CSSD WDGRF x 0 0 X 23 135 ST72104G ST72215G ST72216G ST72254G 6 6 MAIN CLOCK CONTROLLER MCC The Main Clock Controller MCC supplies the clock for the ST7 CPU and its internal peripherals It allows SLOW power saving mode to be man aged by the application All functions are managed by the Miscellaneous register 1 MISCR1
125. re set by hardware with an interrupt if ITE is set AF Detection of anon acknowledge bit In this case the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set To resume set the START or STOP bit ARLO Detection of an arbitration lost condition In this case the ARLO bitis set by hardware with an interrupt if the ITE bit is set and the interface goes automatically back to slave mode the M SL bit is cleared Note In all these cases the SCL line is not held low however the SDA line can remain low due to possible 0 bits transmitted last It is then neces sary to release both lines by software 77 135 ST72104G ST72215G ST72216G ST72254G 12C BUS INTERFACE Cont d Figure 45 Transfer Sequencing 7 bit Slave receiver F z 7 bit Slave transmitter Poa a Legend S Start S Repeated Start P Stop A Acknowledge NA Non acknowledge EVx Event with interrupt if ITE 1 EV1 EVF 1 ADSL 1 cleared by reading SR1 register EV2 EVF 1 BTF 1 cleared by reading SR1 register followed by reading DR register EV3 EVF 1 BTF 1 cleared by reading SR1 register followed by writing DR register EV3 1 EVF 1 AF 1 BTF 1 AF is cleared by reading SR1 register BTF is cleared by releasing the lines STOP 1 STOP 0 or by writing DR register DR FFh Note If lines are released by STOP 1 STOP 0 the subsequent EV4 is not seen EV4 EVF 1 STOPF 1 cleared by reading SR2 regist
126. re with an in terrupt if the ITE bit is set Then the interface waits for a read of the SR1 reg ister followed by a read of the DR register holding the SCL line low see Figure 45 Transfer se quencing EV7 To close the communication before reading the last byte from the DR register set the STOP bit to generate the Stop condition The interface goes automatically back to slave mode M SL bit cleared Note In order to generate the non acknowledge pulse after the last received data byte the ACK bit must be cleared just before reading the second last data byte d DC BUS INTERFACE Cont d Master Transmitter Following the address transmission and after SR1 register has been read the master sends bytes from the DR register to the SDA line via the inter nal shift register The master waits for a read of the SR1 register fol lowed by a write in the DR register holding the SCL line low see Figure 45 Transfer sequencing EV8 When the acknowledge bit is received the interface sets EVF and BTF bits with an interrupt if the ITE bit is set To close the communication after writing the last byte to the DR register set the STOP bit to gener ate the Stop condition The interface goes auto matically back to slave mode M SL bit cleared Error Cases BERR Detection of a Stop or a Start condition during a byte transfer In this case the EVF and a ST72104G ST72215G ST72216G ST72254G BERR bits a
127. required informa tion for the CPU to process the operation TRAP S W Interrupt Wait For Interrupt Low Power Mode HALT Halt Oscillator Lowest Power Mode NO WF IRET Interrupt Sub routine Return RIM Reset Interrupt Mask SCF Set Carry Flag RCF Reset Carry Flag RSP LD CLR NZ U PUSHPOP SLL SRL SRA RLC RRC SWAP Swap Nibbles 12 1 2 Immediate Immediate instructions have two bytes the first byte contains the opcode the second byte con tains the operand value Immediate Instruction Per Reset Stack Pointer Shift and Rotate Operations Load LD CP Compare BCP AND OR XOR ADC ADD SUB SBC Arithmetic Operations Logical Operations a ST72104G ST72215G ST72216G ST72254G 12 1 3 Direct In Direct instructions the operands are referenced by their memory address The direct addressing mode consists of two sub modes Direct short The address is a byte thus requires only one byte after the opcode but only allows 00 FF address ing space Direct long The address is a word thus allowing 64 Kbyte ad dressing space but requires 2 bytes after the op code 12 1 4 Indexed No Offset Short Long In this mode the operand is referenced by its memory address which is defined by the unsigned addition of an index register X or Y with an offset The indirect addressing mode consists of three sub modes Indexed No Offset There is no offset no extra
128. ressing modes may be subdi vided in two sub modes called long and short Long addressing mode is more powerful be cause itcan use the full 64 Kbyte address space however it uses more bytes and more CPU cy cles Short addressing mode is less powerful because it can generally only access page zero 0000h OOFFh range but the instruction size is more compact and faster All memory to memory in structions use short addressing modes only CLR CPL NEG BSET BRES BTJT BTJF INC DEC RLC RRC SLL SRL SRA SWAP The ST7 Assembler optimizes the use of long and short addressing modes Pointer meda _ ar Ss i A ai oven feao Jm i rong Bret feas ooo __fre gt Short Id A 10 X 00 1FE 7 0 with X register No Otse 1 with Y register Long Id A 1000 X 0000 FFFF Short indirect 1d A 10 00 FF 00 FF Long Indirect IG A 10 w 0000 FFFF 00 FF Short Id A 10 X 00 1FE 00 FF Long TA 10 01 X 0000 FFFF Ter Relative Direct imeloop PC 128 PC 127 1 PRetatve maea meo EELER it ndirect elative tjt 7 ski 2 A yte Bi di Relati bijt 10 7 skip 00 FF 00 FF b 3 Note 1 At the P ounter P ow p time the Instruction is executed the Program r points to the Instruction to ing JRxx d 90 135 ST7 ADDRESSING MODES Cont d 12 1 1 Inherent All Inherent instructions consist of a single byte The opcode fully specifies all the
129. rference or by unforeseen logical condi tions which causes the application program to abandon its normal sequence The Watchdog cir cuit generates an MCU reset on expiry of a pro grammed time period unless the program refresh es the counter s contents before the T6 bit be comes cleared 11 1 2 Main Features a Programmable timer 64 increments of 12288 CPU cycles Programmable reset Reset if watchdog activated when the T6 bit reaches zero a Optional reset on HALT configurable by option byte m Hardware Watchdog selectable by option byte 11 1 3 Functional Description The counter value stored in the CR register bits T6 TO is decremented every 12 288 machine cy instruction Figure 25 Watchdog Block Diagram ST72104G ST72215G ST72216G ST72254G cles and the length of the timeout period can be programmed by the user in 64 increments If the watchdog is activated the WDGA bit is set and when the 7 bit timer bits T6 TO rolls over from 40h to 3Fh T6 becomes cleared it initiates a reset cycle pulling low the reset pin for typically 500ns The application program must write in the CR reg ister atregular intervals during normal operation to prevent an MCU reset The value to be stored in the CR register must be between FFh and COh see Table 11 Watchdog Timing fCPU MHz The WDGA bit is set watchdog enabled The T6 bit is set to prevent generating an imme diate reset The
130. rtz PRESC Timer prescaler factor 2 4 or 8 depend ing on CC 1 0 bits see Table 13 Clock Control Bits If the timer clock is an external clock the formula is OCR t fexr 5 Where t fexT Signal or pulse period in seconds External timer clock frequency in hertz The Output Compare 2 event causes the counter to be initialized to FFFCh See Figure 36 Notes 1 After a write instruction to the OC HR register the output compare function is inhibited until the OCILR register is also written 2 The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited 3 The ICF1 bitis set by hardware when the coun ter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the bit is cleared A In PWM mode the ICAP1 pin can not be used to perform input capture because it is discon nected to the timer The ICAP2 pin can be used to perform input capture ICF2 can be set and IC2R can be loaded but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set 5 When the Pulse Width Modulation PWM and One Pulse Mode OPM bits are both set the PWM mode is the only active one 53 135 ST72104G ST72215G ST72216G ST72254G 16 BIT TIMER Cont d 11 2 4 Low Power Modes Description WAIT No effect on 16 bit Timer Timer interrupts cause the device to exit from WAIT mode If an
131. s fetched To clear an unwanted pending interrupt by software the sensitivity bits in the Miscellane ous register must be modified 9 2 2 Output Modes The output configuration is selected by setting the corresponding DDR register bit In this case writ ing the DR register applies this digital value to the I O pin through the latch Then reading the DR reg ister returns the previously stored value Two different output modes can be selected by software through the OR register Output push pull and open drain DR register value and output pin status CRT FEI LC Open drain Co f es Floating 9 2 3 Alternate Functions When an on chip peripheral is configured to use a pin the alternate function is automatically select ed This alternate function takes priority over the standard I O programming When the signal is coming from an on chip periph eral the I O pin is automatically configured in out put mode push pull or open drain according to the peripheral When the signal is going to an on chip peripheral the I O pin must be configured in input mode In this case the pin state is also digitally readable by addressing the DR register Note Input pull up configuration can cause unex pected value at the input of the alternate peripheral input When an on chip peripheral use a pin as in put and output this pin has to be configured in in put floating mode LSTA ST72104G ST72215G ST72216G ST72254G UO P
132. s after executing the external interrupt routine corresponding to the wake up event reset or external interrupt 11 1 6 Interrupts None 11 1 7 Register Description CONTROL REGISTER CR Read Write Reset Value 0111 1111 7Fh 7 0 Bit 7 WDGA Activation bit This bit is set by software and only cleared by hardware after a reset When WDGA 1 the watchdog can generate a reset 0 Watchdog disabled 1 Watchdog enabled Bit 6 0 T 6 0 7 bit timer MSB to LSB These bits contain the decremented value A reset is produced when it rolls over from 40h to 3Fh T6 becomes cleared LSTA ST72104G ST72215G ST72216G ST72254G WATCHDOG TIMER Cond t Table 12 Watchdog Timer Register Map and Reset Values Address Register Hex Label Wees apen a 41 135 ST72104G ST72215G ST72216G ST72254G 11 2 16 BIT TIMER 11 2 1 Introduction The timer consists of a 16 bit free running counter driven by a programmable prescaler It may be used for a variety of purposes including pulse length measurement of up to two input sig nals input capture or generation of up to two out put waveforms output compare and PWM Pulse lengths and waveform periods can be mod ulated from a few microseconds to several milli seconds using the timer prescaler and the CPU clock prescaler Some ST7 devices have two on chip 16 bit timers They are completely independent and do not share any resources They are sync
133. sets the internal latch A pending interrupt i e waiting for being en abled will therefore be lost if the clear sequence is executed 25 135 ST72104G ST72215G ST72216G ST72254G INTERRUPTS Cont d Figure 15 Interrupt Processing Flowchart FROM RESET rs i TERRUP PENDING FETCH NEXT INSTRUCTION STACK PC X A CC SET I BIT LOAD PC FROM INTERRUPT VECTOR EXECUTE INSTRUCTION RESTORE PC X A CC FROM STACK THIS CLEARS BIT BY DEFAULT Table 5 Interrupt Mapping Source Description Register Priority Address Block p Label Order Vector RESET Highest FFFEh FFFFh TRAP Soft Int t Priorit FFFCh FFFDh C eaP Software interrup D y ro 0 e0 Extemal Interrupt Port A7 0 C5 0 FFFAh FFFBh External Interrupt Port B7 0 C5 0 FFF8h FFF9h Clock Filter Interrupt CRSR FFF6h FFF7h SPI Peripheral Interrupts SPISR FFF4h FFF5h TIMERA TIMER A Peripheral Interrupts TASR S ee O O FFF2h FFF3h FFFOh FFF1h BEE BER III LTS EE MC IEA LT A aile E 12 MotUsed Lowest ce III LA Proy Note 1 Configurable by option byte 6 TIMER B TIMER B Peripheral Interrupts TBSR no FFEEh FFEFh d 26 135 ST72104G ST72215G ST72216G ST72254G 8 POWER SAVING MODES 8 1 INTRODUCTION To give a large measure of flexibility to the applica tion in terms of power consumption three main power saving modes are implemented in the ST7 see Figure 16 After a RESET the normal operatin
134. sion however it must be cleared before the second SPIF bit in order to prevent an overrun condition see Section 11 3 4 6 Depending on the CPHA bit the SS pin has to be set to write to the DR register between each data byte transfer to avoid a write collision see Section 11 3 4 4 63 135 ST72104G ST72215G ST72216G ST72254G SERIAL PERIPHERAL INTERFACE Cont d 11 3 4 3 Data Transfer Format During an SPI transfer data is simultaneously transmitted shifted out serially and received shifted in serially The serial clock is used to syn chronize the data transfer during a sequence of eight clock pulses The SS pin allows individual selection of a slave device the other slave devices that are not select ed do not interfere with the SPI transfer Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software using the CPOL and CPHA bits The CPOL clock polarity bit controls the steady state value of the clock when no data is being transferred This bit affects both master and slave modes The combination between the CPOL and CPHA clock phase bits selects the data capture clock edge Figure 40 shows an SPI transfer with the four combinations of the CPHA and CPOL bits The di agram may be interpreted as a master or slave timing diagram where the SCK pin the MISO pin the MOSI pin are directly connected between the master and the slave device The SS pin is the slave device s
135. soon as the received slave address matched with the OAR register con tent or a general call is recognized An interrupt is generated if ITE 1 It is cleared by software read ing SR1 register or by hardware when the inter face is disabled PE 0 The SCL line is held low while ADSL 1 0 Address mismatched or not received 1 Received address matched 81 135 ST72104G ST72215G ST72216G ST72254G DC BUS INTERFACE Cont d Bit 1 M SL Master Slave This bit is set by hardware as soon as the interface is in Master mode writing START 1 Itis cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration ARLO 1 Itis also cleared when the interface is disabled PE 0 0 Slave mode 1 Master mode Bit 0 SB Start bit Master mode This bit is set by hardware as soon as the Start condition is generated following a write START 1 An interrupt is generated if ITE 1 It is cleared by software reading SR1 register followed by writing the address byte in DR register Itis also cleared by hardware when the interface is disa bled PE 0 0 No Start condition 1 Start condition generated 12C STATUS REGISTER 2 SR2 Read Only Reset Value 0000 0000 00h 7 0 o o o ar store ARLO BERR GCAL Bit 7 5 Reserved Forced to 0 by hardware Bit 4 AF Acknowledge failure This bit is set by hardware when no acknowledge is returned An interrupt is generated if ITE 1 It is cleared by s
136. specification All its limits are higher than the JEDEC spec ifications that means when a device belongs to Class A it exceeds the JEDEC standard B Class strictly covers all the JEDEC criteria international standard 2 Schaffner NSG435 with a pointed test finger a 111 135 ST72104G ST72215G ST72216G ST72254G EMC CHARACTERISTICS Cont d 13 7 3 ESD Pin Protection Strategy To protect an integrated circuit against Electro Static Discharge the stress must be controlled to prevent degradation or destruction of the circuit el ements The stress generally affects the circuit el ements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress The elements to be pro tected must not receive excessive current voltage or heating within their structure An ESD network combines the different input and output ESD protections This network works by al lowing safe discharge paths for the pins subjected to ESD stress Two critical ESD stress cases are presented in Figure 72 and Figure 73 for standard pins and in Figure 74 and Figure 75 for true open drain pins Standard Pin Protection To protect the output structure the following ele ments are added A diode to Vpp 3a and a diode from Vgg 3b A protection device between Vpp and Vss 4 To protect the input structure the following ele ments are added A resistor in series with the pad 1 A diode to Vpp
137. ssign the analog channel to be converted ADC Conversion In the CSR register Set the ADON bit to enable the A D converter and to start the first conversion From this time on the ADC performs a continuous conver sion of the selected channel When a conversion is complete The COCO bit is set by hardware No interrupt is generated The result is in the DR register and remains valid until the next conversion has ended A write to the CSR register with ADON set aborts the current conversion resets the COCO bit and starts a new conversion Figure 48 ADC Conversion Timings ADCCSR WRITE OPERATION y HOLD CONTROL 1 l a en LOAD vn COCO BIT SET 11 5 4 Low Power Modes WAIT No effect on A D Converter A D Converter disabled After wakeup from Halt mode the A D Con HALT R verter requires a stabilisation time before ac curate conversions can be performed Note The A D converter may be disabled by reset ting the ADON bit This feature allows reduced power consumption when no conversion is needed and between single shot conversions 11 5 5 Interrupts None 87 135 ST72104G ST72215G ST72216G ST72254G 8 BIT A D CONVERTER ADC Cont d 11 5 6 Register Description CONTROL STATUS REGISTER CSR Read Write Reset Value 0000 0000 00h DATA REGISTER DR Read Only Reset Value 0000 0000 00h 7 0 7 0 Bit 7 COCO Conversion Complete This bit is set by hardware It is c
138. t LVD or watchdog a 117 135 ST72104G ST72215G ST72216G ST72254G CONTROL PIN CHARACTERISTICS Cont d Figure 86 Typical lon VS Vpp with Viy Vss Figure 87 Typical Vo at Vpp 5V RESET Vol V at Vdd 5V Ta 40 C Ta 85 C Pe _ o EE lio mA Ta 40 C Ta 85 C Vol V at lio 5mA Ta 40 C Ta 85 C Vdd V Vdd V 118 135 d ST72104G ST72215G ST72216G ST72254G CONTROL PIN CHARACTERISTICS Cont d 13 9 2 ISPSEL Pin Subject to general operating conditions for Vpp fosc and Ta unless otherwise specified Symbol Parameter Condions min Max Va npu ow ievel valage IN EE a impar evo vorage St i pat stags eet et a Figure 89 Two typical Applications with ISPSEL Pin 2 PROGRAMMING ISPSEL TOOL ST72XXX ST72XXX Notes 1 Data based on design simulation and or technology characteristics not tested in production 2 When the ISP Remote mode is not required by the application ISP SEL pin must be tied to Vss a 119 135 ST72104G ST72215G ST72216G ST72254G 13 10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for Vpp Refer to I O port characteristics for more details on fosc and Ta unless otherwise specified the input output alternate function characteristics output compare input capture external clock PWM output 13 10 1 Watchdog Timer Sumber IC NIC Tiet twwpa Watchdog time out duration SECHER E EE E 13 1
139. t of the counter value transferred by the In put Capture 2 event 7 0 ml le dl ST72104G ST72215G ST72216G ST72254G 16 BIT TIMER Cont d Table 14 16 Bit Timer Register Map and Reset Values Ko e i KE Se Pg Address Register Hex Label Timer A 32 CR1 Ge Timer B 42 Reset Value Timer A 31 CR2 e Timer B 41 Reset Value Timer A 33 ICF1 Timer B 43 Reset Value Timer A 34 ICHR1 Timer B 44 Reset Value Timer A 35 ICLR1 Timer B 45 Reset Value Timer A 36 OCHR1 Timer B 46 Reset Value Timer A 37 OCLR1 Timer B 47 Reset Value Timer A 3E OCHR2 Timer B 4E Reset Value Timer A 3F OCLR2 Timer B 4F Reset Value Timer A 38 CHR Timer B 48 Reset Value Timer A 39 CLR Timer B 49 Reset Value Timer A 3A ACHR Timer B AA Reset Value Timer A 3B ACLR M Timer B 4B Reset Value Timer A 3C ICHR2 Timer B 4C Reset Value Timer A 3D ICLR2 Timer B 4D Reset Value OCIE 0 OC2E 0 OCF1 o Ee E e 59 135 a ST72104G ST72215G ST72216G ST72254G 11 3 SERIAL PERIPHERAL INTERFACE SPI 11 3 1 Introduction The Serial Peripheral Interface SPI allows full duplex synchronous serial communication with external devices An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves The SPI is normally used for communication be tween the microcontroller and external peripher
140. te a reset until the microcontroller receives an external inter rupt or a reset If an external interrupt is received the WDG re starts counting after 4096 CPU clocks If a reset is generated the WDG is disabled reset state Recommendations Make sure that an external event is available to wake up the microcontroller from Halt mode Before executing the HALT instruction refresh the WDG counter to avoid an unexpected WDG 40 135 reset immediately after waking up the microcon troller When using an external interrupt to wake up the microcontroller reinitialize the corresponding I O as Input Pull up with Interrupt before executing the HALT instruction The main reason for this is that the I O may be wrongly configured due to ex ternal interference or by an unforeseen logical condition For the same reason reinitialize the level sensi tiveness of each external interrupt as a precau tionary measure The opcode for the HALT instruction is Ox8E To avoid an unexpected HALT instruction due to a program counter failure it is advised to clear all occurrences of the data value Ox8E from memo ry For example avoid defining a constant in ROM with the value 0x8E As the HALT instruction clears the bit in the CC register to allow interrupts the user may choose to clear all pending interrupt bits before execut ing the HALT instruction This avoids entering other peripheral interrupt routine
141. ternal interrupt pulse time ptr ST72XXX UNUSED I O PORT UNUSED I O PORT ST72XXX Ht Ta 40 C Ta 85 C LIA Ta 25 C 1K Ta 125 C Vdd V Notes 1 Unless otherwise specified typical data are based on T 25 C and Vpp 5V 2 Data based on characterization results not tested in production 3 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested 4 Configuration not recommended all unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor see Figure 77 Data based on design simulation and or technology characteristics not tested in production 5 The Rey pull up equivalent resistor is based on a resistive transistor corresponding Ipy current characteristics de scribed in Figure 78 This data is based on characterization results tested in production at Vp Dp Max 6 Data based on characterization results not tested in production 7 To generate an external interrupt a minimum pulse width has to be applied on an I O port pin configured as an external interrupt source 114 135 STA ST72104G ST72215G ST72216G ST72254G UO PORT PIN CHARACTERISTICS Cont d 13 8 2 Output Driving Current Subject to general operating conditions for Vpp fosc and Ta unless otherwise specified Output low level voltage for a standard I O pin o 5ma 1 2 when 8 pins are sunk at same time Outp
142. ternate function capability released In this case the pin status depends on the I O port configuration 3 Measurement points are done at CMOS levels 0 3xVpp and 0 7xVpp Zar 121 135 ST72104G ST72215G ST72216G ST72254G COMMUNICATION INTERFACE CHARACTERISTICS Cont d Figure 91 SPI Slave Timing Diagram with CPHA 1 CPOL 0 CPHA 0 CPOL 1 D sen mear rte 2 tus 1 thst eet dk f vos RR OR Mowo RO Tse Kae OR to Notes 1 Measurement points are done at CMOS levels 0 3xVpp and 0 7xVpp 2 When no communication is on going the data output line of the SPI MOSI in master mode MISO in slave mode has its alternate function capability released In this case the pin status depends of the I O port configuration d 122 135 ST72104G ST72215G ST72216G ST72254G COMMUNICATION INTERFACE CHARACTERISTICS Cont d 13 11 2 I C Inter IC Control Interface Refer to I O port characteristics for more details on wu the input output alternate function characteristics l for V S EE o ee or YDD SDAI and SCLI The ST7 IC interface meets the oe i requirements of the Standard 12 communication protocol described in the following table Fast mode I2C Min Max Standard mode I2C Max me 5 Tio on Parameter Min SCL clock low time SCL clock high time SDA setup time SDA data hold time E a AJA oO N a w o a SDA and SCL rise time 1000 20 0 1Cp 3 SDA and SCL fall time
143. terrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the I bit in the CC reg ister is reset RIM instruction Interrupt Event External interrupt on selected external event 9 6 REGISTER DESCRIPTION DATA REGISTER DR Port x Data Register PxDR with x A B or C Read Write Reset Value 0000 0000 00h S 0 Bit 7 0 D 7 0 Data register 8 bits The DR register has a specific behaviour accord ing to the selected input output configuration Writ ing the DR register is always taken into account even ifthe pin is configured as an input this allows always having the expected level on the pin when toggling to output mode Reading the DR register returns either the DR register latch content pin configured as output or the digital value applied to the I O pin pin configured as input 34 135 DATA DIRECTION REGISTER DDR Port x Data Direction Register PxDDR with x A B or C Read Write Reset Value 0000 0000 00h 7 0 207 os pos 00s 003 poe 005 000 Bit 7 0 DD 7 0 Data direction register 8 bits The DDR register gives the input output direction configuration of the pins Each bit is set and cleared by software 0 Input mode 1 Output mode OPTION REGISTER OR Port x Option Register PxOR with x A Bor C Read Write Reset Value 0000 0000 00h 7 0 BSE Occiccs Bit 7 0 O 7 0 Option register 8 bits For sp
144. terrupt sensitivity defined using the 1S1 1 0 bits is applied to the ei1 external interrupts These two bits can be written only when the bit of the CC register is set to 1 interrupt masked ell Port B C optional External Interrupt Sensitivity Falling edge amp low level Rising edge only Falling edge only 1 Bit 5 MCO Main clock out selection This bit enables the MCO alternate function on the PC2 I O port It is set and cleared by software 0 MCO alternate function disabled I O pin free for general purpose I O 1 MCO alternate function enabled fepy on I O port Bit 4 3 ISO 1 0 e 0 sensitivity The interrupt sensitivity defined using the ISO 1 0 bits is applied to the ei0 external interrupts These two bits can be written only when the bit of the CC register is set to 1 interrupt masked ei0 Port A C optional External Interrupt Sensitivity 1501 1500 Falling edge amp low level ojo C TY FFaling edge ony oo a ST72104G ST72215G ST72216G ST72254G Bit 2 1 CP 1 0 CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes Their action is conditioned by the setting of the SMS bit These two bits are set and cleared by software fosc 4 o o ose 78 SCC EEC INN Bit 0 SMS Slow mode select This bit is set and cleared by software 0 Normal mode Tu fosc 2 1 Slow mode fcpy is given by CP1 CPO See low po
145. tes In order to extend the number of available op codes for an 8 bit CPU 256 opcodes three differ ent prebyte opcodes are defined These prebytes modify the meaning of the instruction they pre cede The whole instruction becomes PC 2 End of previous instruction PC 1 Prebyte PC opcode PC 1 Additional word 0 to 2 according to the number of bytes required to compute the ef fective address a These prebytes enable instruction in Y as well as indirect addressing modes to be implemented They precede the opcode of the instruction in X or the instruction using direct addressing mode The prebytes are PDY 90 Replace an X based instruction using immediate direct indexed or inherent ad dressing mode by a Y one PIX 92 Replace an instruction using di rect direct bit or direct relative addressing mode to an instruction using the corresponding indirect addressing mode It also changes an instruction using X indexed ad dressing mode to an instruction using indirect X in dexed addressing mode PIY 91 Replace an instruction using X in direct indexed addressing mode by a Y one 93 135 ST72104G ST72215G ST72216G ST72254G INSTRUCTION GROUPS Cont d Mnemo Description FunctonExampe Ost Sr oc rwn DACH DD AND EC CEEI CON CI EN EA ICA CN CU Baes CE ECT JCT aser esa feae MT ert TIN ECETIA CT EX EN EEC CN FE posee caras Y EIERE ea fee Ci EAS eP one Complement DP rea _ BEC Decrem
146. the FRi bits in the OAR2 register 11 4 4 1 Slave Mode As soon as a Start condition is detected the address is received from the SDA line and sent to the shift register then it is compared with the address of the interface or the General Call address if selected by software Note In 10 bit addressing mode the comparision includes the header sequence 11110xx0 and the two most significant bits of the address Header matched 10 bit mode only the interface generates an acknowledge pulse if the ACK bit is set Address not matched the interface ignores it and waits for another Start condition Address matched the interface generates in se quence Acknowledge pulse if the ACK bit is set EVF and ADSL bits are set with an interrupt if the ITE bit is set Then the interface waits for a read of the SR1 reg ister holding the SCL line low see Figure 45 Transfer sequencing EV1 Next in 7 bit mode read the DR register to deter mine from the least significant bit Data Direction Bit ifthe slave must enter Receiver or Transmitter mode In 10 bit mode after receiving the address se quence the slave is always in receive mode It will enter transmit mode on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set 11110xx1 Slave Receiver Following the address reception and after SR1 register has been read the slave receives bytes
147. ting must be respected otherwise refer to ling PIn Specification A positive injection is induced by Vu Von while a negative injection is induced by Viy lt V ss 3 All power Vpp and ground Vss lines must always be connected to the external supply 4 Negative injection disturbs the analog performance of the device In particular it induces leakage currents throughout the device including the analog inputs To avoid undesirable effects on the analog functions care must be taken Analog input pins must have a negative injection less than 0 8 mA assuming that the impedance of the analog voltage is lower than the specified limits Pure digital pins must have a negative injection less than 1 6mA In addition it is recommended to inject the current as far as possible from the analog input pins 5 When several inputs are submitted to a current injection the maximum 2Inyypiny is the absolute sum of the positive and negative injected currents instantaneous values These results are based on characterisation with 2I yypiny Maxi mum current injection on four I O port pins of the device 6 True open drain I O port pins do not accept positive injection LSTA 97 135 ST72104G ST72215G ST72216G ST72254G 13 3 OPERATING CONDITIONS 13 3 1 General Operating Conditions Vop Supply voltage see Figure 51 and Figure 52 Vpp23 5V for ROM devices External clock frequency Vpp24 5V for FLASH devices 1 Suffix Version 0 70 6 Suff
148. ts chapter They generate an interrupt if the corresponding Enable Control Bit is set and the I bit in the CC reg ister is reset RIM instruction a 79 135 ST72104G ST72215G ST72216G ST72254G 12C BUS INTERFACE Cont d 11 4 7 Register Description DC CONTROL REGISTER CR Read Write Reset Value 0000 0000 00h 7 0 Bit 7 6 Reserved Forced to 0 by hardware Bit 5 PE Peripheral enable This bit is set and cleared by software 0 Peripheral disabled 1 Master Slave capability Notes When PE 0 all the bits of the CR register and the SR register except the Stop bit are reset All outputs are released while PE 0 When PE 1 the corresponding I O pins are se lected by hardware as alternate functions To enable the fC interface write the CR register TWICE with PE 1 as the first write only activates the interface only PE is set Bit 4 ENGC Enable General Call This bit is set and cleared by software It is also cleared by hardware when the interface is disa bled PE 0 The 00h General Call address is ac knowledged 01h ignored 0 General Call disabled 1 General Call enabled Bit 3 START Generation of a Start condition This bit is set and cleared by software It is also cleared by hardware when the interface is disa bled PE 0 or when the Start condition is sent with interrupt generation if ITE 1 In master mode 0 No start generation 1 Repeated start generation
149. tware It is also cleared by hardware when in master mode SS 0 see Section 11 3 4 5 Master Mode Fault on page 66 0 I O port connected to pins 1 SPI alternate functions connected to pins The SPE bit is cleared by reset so the SPI periph eral is not initially connected to the external pins Bit 5 SPR2 Divider Enable this bit is set and cleared by software and it is cleared by reset It is used with the SPR 1 0 bits to set the baud rate Refer to Table 15 0 Divider by 2 enabled 1 Divider by 2 disabled Bit 4 MSTR Master This bit is set and cleared by software It is also cleared by hardware when in master mode SS 0 see Section 11 3 4 5 Master Mode Fault on page 66 0 Slave mode is selected 1 Master mode is selected the function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are re versed 70 135 Bit 3 CPOL Clock polarity This bit is set and cleared by software This bit de termines the steady state of the serial Clock The CPOL bit affects both the master and slave modes 0 The steady state is a low value at the SCK pin 1 The steady state is a high value at the SCK pin Bit 2 CPHA Clock phase This bit is set and cleared by software 0 The first clock transition is the first data capture edge 1 The second clock transition is the first capture edge Bit 1 0 SPR 1 0 Serial peripheral rate These bits are set and c
150. uence The MSTR and SPE bits must be set they re main set only if the SS pin is connected to a high level signal 62 135 In this configuration the MOSI pin is a data output and to the MISO pin is a data input Transmit sequence The transmit sequence begins when a byte is writ ten the DR register The data byte is parallel loaded into the 8 bit shift register from the internal bus during a write cycle and then shifted out serially to the MOSI pin most significant bit first When data transfer is complete The SPIF bit is set by hardware An interrupt is generated if the SPIE bit is set and the bit in the CCR register is cleared During the last clock cycle the SPIF bit is set a copy of the data byte received in the shift register is moved to a buffer When the DR register is read the SPI peripheral returns this buffered value Clearing the SPIF bit is performed by the following software sequence 1 An access to the SR register while the SPIF bit is set 2 A write or a read of the DR register Note While the SPIF bit is set all writes to the DR register are inhibited until the SR register is read d SERIAL PERIPHERAL INTERFACE Conta 11 3 4 2 Slave Configuration In slave configuration the serial clock is received on the SCK pin from the master device The value of the SPRO A SPR1 bits is not used for the data transfer Procedure For correct data transfer the slave device must b
151. ure range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the min imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 32 13 1 2 Typical values Unless otherwise specified typical data are based on Ta 25 C Vpp 5V for the 4 5V lt Vpp lt 5 5V voltage range and Vpp 3 3V for the 3V lt Vpp lt 4V voltage range They are given only as design guidelines and are not tested 13 1 3 Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested 13 1 4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 49 Figure 49 Pin loading conditions ST7 PIN ve 96 135 13 1 5 Pin input voltage The input voltage measurement on a pin of the de vice is described in Figure 50 Figure 50 Pin input voltage ST7 PIN d 13 2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as absolute maxi mum ratings may cause permanent damage to the device This is a stress rating only and func tional operation of the device under these condi 13 2 1 Voltage Characteristics Symbol Input voltage on any pin ST72104G ST72215G ST72216G ST72254G tions is not implied Exposure to maximum rating conditions f
152. ut low level voltage for a high sink I O pin gt lio 20MA T a lt 85 C 1 3 when 4 pins are sunk at same time L Ta285 C 1 5 V EE Sem Output high level voltage for an I O pin lio SMA Tas85 C Vpp 1 4 when 4 pins are sourced at same time T 285 C Vpp 1 6 see Figure 81 and Figure 84 foam Von Figure 81 Typical Vpp Von at Vpp 5V Vdd Voh V at Vdd 5V Ta 40 C Ta lio mA lio mA Notes 1 The ljo current sunk must always respect the absolute maximum rating specified in Section 13 2 2 and the sum of lig 1 O ports and control pins must not exceed lyss 2 The ljo current sourced must always respect the absolute maximum rating specified in Section 13 2 2 and the sum of lio VO ports and control pins must not exceed lypp True open drain I O pins does not have Voy T 115 135 ST72104G ST72215G ST72216G ST72254G UO PORT PIN CHARACTERISTICS Cont d Figure 82 Typical VoL vs Vpp standard I Os Vol V at lio 2mA Ta 40 C Ta 85 C Vol V at lio 5mA Ta 40 C Ta 85 C Vdd V Vol V at lio 20mA Ta 40 C Ta 85 C Vdd V Vdd Voh V at lio 5mA AAN AT Ta 40 Ss GE E Ta 40 C Ta 85 C AL RA Ta 40 C Ta 85 C Si Vdd V Vdd V 116 135 STA ST72104G ST72215G ST72216G ST72254G 13 9 CONTROL PIN CHARACTERISTICS 13 9 1 Asynchronous RESET Pin Subject to general operating conditions for Vpp fosc and Ta unless otherwise specified E EE CW Ip Dt REEL EE
153. wer consumption mode and MCC chapters for more details 37 135 ST72104G ST72215G ST72216G ST72254G MISCELLANEOUS REGISTERS Cont d MISCELLANEOUS REGISTER 2 MISCR2 Read Write Reset Value 0000 0000 00h 7 0 EEC Bit 7 4 Reserved always read as 0 Bit 5 MOD SPI Master Output Disable This bit is set and cleared by software When set it disables the SPI Master MOSI output signal 0 SPI Master Output enabled 1 SPI Master Output disabled Bit 4 SOD SPI Slave Output Disable This bit is set and cleared by software When set it disable the SPI Slave MISO output signal 0 SPI Slave Output enabled 1 SPI Slave Output disabled Bit 1 SSM SS mode selection This bit is set and cleared by software _ 0 Normal mode the level of the SPI SS signal is input from the external SS om 1 I O mode the level of the SPI SS signal is read from the SSI bit Bit 0 SSI SS internal mode This bit replaces the SS pin of the SPI when the SSM bit is set to 1 see SPI description It is set and cleared by software Table 10 Miscellaneous Register Map and Reset Values Address Reg ister 7 Hex Label 0020h MISCR1 IS11 IS10 MCO 1S01 1S00 Chi CPO SMS Reset Value 0 0 0 0 0 0 0 0 MISCR2 MOD SOD SSM SSI d 38 135 11 ON CHIP PERIPHERALS 11 1 WATCHDOG TIMER WDG 11 1 1 Introduction The Watchdog timer is used to detect the occur rence of a software fault usually generated by ex ternal inte
154. y active one 3 1f OLVL1 OLVL2 a continuous signal will be seen on the OCMP1 pin 4 The ICAP1 pin can not be used to perform input capture The ICAP2 pin can be used to perform input capture ICF2 can be set and IC2R can be loaded but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set 5 When one pulse mode is used OC1R is dedi cated to this mode Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an out put waveform because the level OLVL2 is dedi cated to the one pulse mode 51 135 ST72104G ST72215G ST72216G ST72254G 16 BIT TIMER Cont d Figure 35 One Pulse Mode Timing Example compare1 Note IEDG1 1 OC1R 2EDOh OLVL1 0 OLVL2 1 Figure 36 Pulse Width Modulation Mode Timing Example COUNTER 34E2KFFFC FFFC FFFD FFF E 2ED0 2ED 1X2E D2 34E2 XFFFC OCMP1 OLVL2 OLVL1_ cr compare2 compare1 compare2 Note OC1R 2ED0h OC2R 34E2 OLVL1 0 OLVL2 1 52 135 dl 16 BIT TIMER Cont d 11 2 3 6 Pulse Width Modulation Mode Pulse Width Modulation PWM mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers The pulse width modulation mode uses the com plete Output Compare 1 function plus the OC2R register and so these functionality can not be used when the PWM mod

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