intel 87C196CA/87C196CB handbook
Contents
1. Symbol Parameter Test Conditions min Units lu Input Leakage Current Std Inputs Vss lt Vin lt 10 pa in Input Leakage Current Port 0 Vss lt Vin lt VREF CA 15 CB i10 BA Vout SLPINT P5 4 and HLDA P2 6 loH 0 8 mA 20 v Output High Voltage in RESET Output High Voltage in RESET 16 nA 1 v Cs Pin Capacitance Any pin to Vss 1 0 10 pF Rweu Weak Pullup Resistance Note 6 150K n Rast Reset Pullup Resistor For cB 65k Rast Reset Pullup Resistor CA For CA 65K NOTES 1 All BD bidirectional pins except INST and CLKOUT INST and CLKOUT are excluded due to their not being weakly pulled high in reset BD pins include Port Port2 Porta Ports and Ports except SPLINT P5 4 and HLDA P2 6 2 Standard input pins include XTAL1 ER RESET and Port 1 2 5 6 when setup as inputs 3 All bidirectional 1 O pins when configured as Outputs Push Pull 4 Device is static and should operate below 1 Hz but only tested down to 4 MHz 5 Maximum lo currents per pin will be characterized and published at a later date 6 Typicals are based on limited number of samples and are not guaranteed The values listed are at room temperature and 50V Violating these specifications in reset may cause the device to enter test modes P5 4 and P2 6 When PO is used as analog inputs refer to A D s2. 30 ns ca 8 20 ns FD Low Period Tosc 10 ns High to ALE ADV High Tosc Tosc 25 ns TrLaz RU Low to Address Float 5 s Low to WR Low ns Tow CLKOUT Low to WR Low 25 ns Data Valid before WR High ns CLKOUT High to WR High 15 ns WR Low Period ca Tosc 30 ns CA Tosc 20 Data Hold after WR High Tosc 25 ns WA High to ALE RDV High Tose 10 Toso 15 ne INST Hold after WR High Tosc 10 ns 8 15 Hold after WR High Tosc 30 nsa INST Hold after RD High Tosc 10 s ADB 15 Hold after RU High Tosc 30 nsa NOTES Testing performed at 4 0 MHz however the device is static by design and will typically operate below 1 Hz Typical specifications not guaranteed bus only 1 2 3 Assuming back to back bus cycles 4 5 If wait states are used add 2 Tose n where n operation is selected add 2 to specification 6 is the time for the oscillator fail detect circuit to react to a clock failure The circuitry is enabled by programming the UPROM location 0778H with the value 0004H Programming the CDE bit enables oscilator fail detec tion 16 number of wait states If mode 0 1 automatic wait state added ADVANGE INFORMATION intel 87C196CA 87C196CB AC CHARACTERISTICS Over Specified Operating Conditions Test Co
3. v v v emye sx 266 as 6 v v v s The 87C196CA CB are new members of the MCS 96 microcontroller family These devices are based upon the MCS 96 Kx Jx microcontroller product families with enhancements ideal for automotive and industrial applications The CA CB are the first devices in the Kx family to support networking through the integration of the CAN 2 0 Controller Area Network peripheral on chip The 87C196CB offers the highests memory density of the MCS 96 microcontroller family with 56K of on chip EPROM 1 5K of on chip register RAM and 512 bytes of additional RAM Code RAM In addition the 87 196 provides up to 16 Mbyte of Linear Address Space The 87 196 is a sub set of the offering 32K of on chip EPROM up to 1 0K of on chip register RAM and 256 bytes of additional RAM Code RAM iher brands and names are he property of hee respective owners ayn for sale and use o nel produce excepi as provided st ntl Terms and Conditans ol Sale for suc products inel ets night Sh nges ness spocilcaions a any ime winaut noice Mierocomputer Products may have minar variations Ye specication known as emata COPYRIGHT INTEL CORPORATION 1996 April 1996 Order Number 272405004 87C196CA 87C196CB intel 5 The MCS 96 microcontroller family members are high performance
4. is selected to meet these specifications 8 BIT MODE A D CHARACTERISTICS Using Above Operating Conditions 6 Parameter Min Max Units 256 256 Level Resolution a A p Absolute Error 0 10 1585 Full Scale Error 05 1585 Zero Offset Error 05 1585 Non Linearity 10 1588 Differential Non Linearity 05 05 1588 Channel to Channel Matching 10 LSBs Repeatability 0 25 0 18860 Temperature Coefficients Offset 0 003 LsB ott Full Scale 0 003 1 8 0 Differential Non Linearity 0 008 188 0 Off Isolation 60 980 23 Feedthrough 60 deca Power Supply Rejection 60 Input Resistance 750 1 2K EI DC Input Leakage 10 15 uA Voltage on Analog Input Pin ANGND 05 05 ve Sampling Capacitor 3 0 LSB as used here has a value of approximately 20 mV NOTES 1 These values are expected for most parts at 25 C but are not tested or guaranteed 2 DC to 100 KHz 3 Multiplexer break before make is guaranteed 4 Resistance from device pin through internal MUX to sample capacitor 5 Applying voltage beyond these specifications will degrade the accuracy of other channels being converted 6 All conversions performed with processor in IDLE mode 30 ADVANGE INFORMATION intel 87 196 DESIGN CONSIDERATIONS The 87C196CA device is a memory scalar of the 87C196KR device with integrated CAN 2 0 The CA is designed for strict functional and electrical com patibility to the K
5. 87 196 ADVANGE INFORMATION intel tel 87C196CA 87C196CB 20 MHz ADVANCED 16 BIT CHMOS MICROCONTROLLER WITH INTEGRATED CAN 2 0 Automotive m High Performance CHMOS 16 Bit CPU up to 20 MHz Operation m Register Register Architecture m Up to 56 Kbytes of EPROM m Up to 1 5 Kbyte of On Chip Register RAM m Up to 512 Bytes of Additional RAM Code RAM m Up to 16 Mbyte Linear Address Space Supports CAN Controller Area Network Specification 2 0 m 15 Message Objects of 8 Bytes Data Length m Full Duplex Synchronous Serial 1 0 Port 6510 m Interprocessor Communication Slave Port m Selectable Bus Timing Modes for Flexible Interfacing m Oscillator Fail Detection m High Speed Peripheral Transaction Server PTS m Two Dedicated 16 Bit High Speed Compare Registers m High Speed Capture Compare EPA m Two Flexible 16 Bit Timer Counters uitry m 10 Bit A D with Sample Hold m Flexible 8 16 Bit External Bus m 38 Prioritized Interrupts Programmable Up to Seven 8 Bit 60 1 0 Ports m Programmable Bus HLD HLDA m Full Duplex Serial Port SIO with 14 16 x 16 Multiply Dedicated Baudrate Generator m 24 us 32 16 Divide 40 C to 125 C Ambient Deuce EPROM Rep at cove mnn PA so av eapnpLcc sek 15K sim 186 w v v v 6 _1 sek si
6. ADDRESS OUT J Tove 1 DATA OUT X BHE INST VALID X ane F If mode 0 operation is selected add 2 Tosc to this time AD8 ADiS X ADDRESS OUT 08 4015 VALID 8 81 BUS MODE X 272405 17 18 ADVANGE INFORMATION intel 87C196CA 87C196CB 87C196CA CB READY TIMINGS ONE WAIT STATE READY 1 susto X es 3 WR sus mode 0 selected only one wait state is always added If additional wait states are required add 2 Tosc to these specifications X 272405 18 87C196CB BUSWIDTH TIMINGS Bus WRITE 272405 19 If mode 0 selected CB only add 2 to these specifications ADVANGE INFORMATION 19 87C196CA 87C196CB 8XC196CB HOLD HOLDA TIMINGS Over Specified Operation Conditions Test Conditions Capacitance Load on All Pins 100 pF Rise and Fall Times 10 ns intel Symbol Parameter Min Max Units HOLD Setup Time 65 nsl ToLHAL CLKOUT Low to HLDA Low 15 15 ns CLKOUT Low to BREQ Low 15 15 ns HLDA Low to Address Float 20 ns HLDA Low to BHE INST RD WR Weakly Driven 25 ns TcuuH CLKOUT Low to HLDA High 15 15 ns CLKOUT Low to BREQ High 25 25 ns HLDA
7. Wiling to these bits wil have no effect 4 PORTS On 87C196CA P5 1 and P5 7 have been re moved from the device and are not available to the programmer Corresponding bits in the port registers have been hard wired to provide the following re sults when read When Read 1 7 1 1 7 1 7 Register Bits P5 PINx P5 REGx P5 DIRXx P5 MODEx 1 P5 MODEx 7 Wiling to these bits wil have no affect 5 87C196CA P6 2 and P6 3 have been re moved from the device and are not available to the programmer Corresponding bits in the port registers have been hard wired to provide the following re sults when read Register Bits When Read P6_PIN x 23 1 P6 REGx 23 1 P6 DIRx 23 1 P6 MODEx x 2 3 Wiling to these bits wil have no affect ADVANGE INFORMATION intel DATA SHEET REVISION HISTORY This is the 003 revision of the 87C196CA CB data sheet The following differences exist between the 002 version and the 003 revision 1 The data sheet has been revised to ADVANCE from PRELIMINARY indicaitng the specifica tions have been verified through electrical tests 2 The 87 196 10044 QFP package and device pinout has been added to the data sheet 3 The 87 196 10044 QFP device supports up the 16 Mbyte of linear address space 4 The package thermal characteris
8. 0000 Overlay Page 15 for CB QFP package External Memory 5 OEFFFFH 900 Kbytes External Memory 010000H OOFFFFH External Memory or OTPROM Program Memory 002080H 00207FH External Memory or Remapped OTPROM Special Purpose 3 002000 Memory Mapped Special Function Registers SFR s 001 OO1FDFH Internal Peripheral Special Function Registers SFR s 5 OO1EFFH Internal CAN Peripheral Memory 001E00H 0 Internal Register RAM 001BFFH External Memory 0005 Internal RAM Code 000400H Address with Indirect or Indexed Modes Register RAM Upper Register File Address with Indirect or Indexed Modes or through 000100H Windows 2 10 ADVANGE INFORMATION intel P 87C196CA 87C196CB 87C196CB Memory Map Continued Address Description 0000FFH Register RAM Lower Register File Address with Direct Indirect or Indexed Modes 2 000018H 000017H CPU SFR s 000000H NOTES 1 These areas are mapped internal EPROM if the REMAP bit CCB2 2 is set and EA 5V Otherwise they are external memory Code executed in locations 0000H to 00 will be forced external Reserved memory locations must contain OFFH unless noted Reserved SFR bit locations m
9. 87 196 tpLpH min 50 Tosc Separate specificatons for tepov for the 87 196 tpipy min 100 for the 87 196 tp_py min 50 Tosc 8 mode A D characteristics added the 33
10. 25 EA 12 5V 0 254 Fosc 5 0 MHz Symbol Parameter Min Max Units Tavu Address Setup Time Tosc Tuax Address Hold Time 100 Tosc Data Setup Time Tosc Teupx Data Hold Time 400 Tosc PALE Pulse Width 50 Tosc PROG Pulse Width CA 50 Tosc 100 Tose PALE High to PROG Low 220 Tosc PROG High to next PALE Low 220 Tose Word Dump Hold Time 50 Tosc TeHPL PROG High to next PROG Low 220 Tose PALE High to PROG Low 220 Toso TeLbv PROG Low to Word Dump Valid CA 50 Tosc 100 Tosc RESET High to First PALE Low 1100 Tosc TeHIL PROG High to AINC Low Tosc AING Pulse Width 240 Tosc PVER Hold after AINC Low 50 Tosc INT Low to PROG Low 170 Toso TeHVL PROG High to PVER Valid 220 Tose ime programming is done with 6 0 MHz to 10 0 MHz Vpn 59 0 8V 25 C 5C and Vep 125V 0 25 For run time programming over a full operating range contact factory 2 Programming specifications are not tested but guaranteed by design This specification is for the word dump mode For programming pulses use 300 Tosc 100 DC EPROM PROGRAMMING CHARACTERISTICS Symbol Parameter Min Max Units Ipp Vpp Programming Supply Current 200 mA NOTE must be within 1V of Voc while lt 4 5V Vpp must not have a low impedance path to ground Vss while gt 45V ADVANGE INFORMATION 25 87C196CA 87C1
11. High to Address No Longer Float 18 ns HLDA High to INST RD WR Valid 10 15 ns 8XC196CB HOLD HOLDA TIMINGS Tose en T HOLD FOLDA REG Bus 21 23 SHE INST RD WR p 20 ADVANGE INFORMATION intel 87C196CA 87C196CB 8XC196CB AC CHARACTERISTICS SLAVE PORT SLAVE PORT WAVEFORM SLPL 0 ALE AT SLAVE PORT TIMING SLPL 0 1 2 3 Symbol Parameter Min Max Uni Tsavwe Address Valid to WR Low 50 ns TSRHAV RD High to Address Valid 60 ns Low Period Tosc WR Low Period Tosc E Tsniov RD Low to Output Data Valid 80 Input Data Setup to WR High 20 ns TswHax WR High to Data Invalid 30 ns TsRHDZ RD High to Data Float 15 ns NOTES 1 Test Conditions 20 MHz 60 ns Rise Fall Time 10 ns Capacitive Pin Load 100 pF 2 These values are not tested in production and are based upon theoretical estimates and or laboratory tests 3 Specifications above are advanced information and are subject to change ADVANGE INFORMATION 21 87C196CA 87C196CB AC CHARACTERISTICS SLAVE PORT Continued SLAVE PORT WAVEFORM SLPL 1 intel ALE LT Tsaupy Toe Tonus nuc 2 Tsa
12. If CCR bit 1 is a one and CCR1 bit 2 is a one this pin CB only dynamically controls the Buswidth of the bus cycle in progress If BUSWIDTH is low an 8 bit cycle occurs BUSWIDTH is high 16 bit cycle occurs If CCR bit 1 is 0 and bit 2 is 1 all bus cycles are 8 bit if CCR bit 1 is 1 and bit 2 is 0 all bus cycles are 16 bit CCR bit 1 0 and CCR1 bit 2 0 is illegal Also an LSIO pin when not used as BUSWIDTH P5 6 READY Ready input to lengthen external memory cycles for interfacing with slow or dynamic memory or for bus sharing If the pin is high CPU operation continues in a normal manner if the pin is low prior to the falling edge of CLKOUT the memory controller goes into a wait state mode until the next opositive transition in CLKOUT occurs with READY high When external memory is not used READY has no effect The max number of wait states inserted into the bus cycle is controlled by the CCR CCR1 Also an LSIO if READY is not selected P5 5 BHE WRH Byte High Enable or Write High output as selected by the CCR BHE 0 selects the bank of memory that is connected to the high byte of the data bus AO 0 selects the of memory that is connected to the low byte Thus accesses to 16 bit wide memory can be to the low byte only AO 0 BHE 1 to the high byte only AO 1 0 or both bytes AO 0 BHE 0 If the WRH function is selected the pin will go low if
13. is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 Must be connected for A D and Port 0 to function Reference ground for the A D converter Must be held at nominally the same potential as Vss Programming voltage for EPROM parts It should be 12 5V for programming It is also the timing pin for the return from powerdown circuit Connect this pin with a 1 pF capacitor to Vss and a 1Mohm resistor to If this function is not used may be tied to Voc XTALI Input of the oscillator inverter and the internal clock generator XTAL2 Output of the Oscillator Inverter Reset input to the chip Input low for at least 16 state times will reset the chip The subsequent low to high transition resynchronizes CLKOUT and commences a 10 state time sequence in which the PSW is cleared bytes are read from 2018H 201Ah and 201CH if enabled loading the CCB s and a jump to location 2080H is executed Input high for normal operation RESET 4 has an internal pullup NMI positive transition causes non maskable interrupt vector through memory location 203EH not used this pin should be tied to Vss May be used by Intel Evaluation boards Input for memory select External Access EA equal to high causes memory accesses to locations OFF2000H through OFFFFFFH to be directed to on chip EPROM ROM EA equal to a low causes access
14. microcontrollers with a 16 bit CPU The 87 196 is composed of the high speed 20 MHz macrocore with up to 16 Mbyte linear address space 56 Kbytes of program EPROM up to 1 5 Kbytes of register RAM and up to 512 bytes of code RAM 16 bit addressing modes with the ability to execute from this RAM space It supports the high speed serial commu nications protocol CAN 2 0 with 15 message objects of 8 bytes data length an 8 channel 10 bit 3 LSB analog to digital converter with programmable S H times and conversion times lt 20 at 20 MHz It has an asynchronous synchronous serial 1 0 port 510 with a dedicated 16 bit baud rate generator an additional synchronous serial port SSIO with full duplex master slave transceivers a flexible timer counter struc ture with prescaler cascading and quadrature capabilities There are ten modularized multiplexed high speed I O for capture and compare called Event Processor Array with 200 ns resolution and double buffered inputs and a sophisticated prioritized interrupt structure with programmable Peripheral Transaction Server PTS implementing several channel modes including single burst block transfers from any memory location to any memory location a PWM and PWM toggle mode to be used in conjunction with the EPA and an A D scan mode NOTICE This is an advance information data sheet The A C and D C parameters contained within this data sheet may change after full automotive tem
15. output pin for the Serial I O port Also LSIO if not used as PORT 1 7 Dual function I O port pins Primary function is that of bidirectional 1 0 System function is that of High Speed capture and compare and 2 have another function of T2CLK and T2DIR of the TIMER timer counter PORT 0 ACHO 7 8 bit high impedance input only port These pins can be used as digital inputs and or as analog inputs to the on chip A D converter These pins are also used as inputs to EPROM parts to select the Programming Mode EPORT 8 bit bidirectional standard and 1 Port These bits are shared with the extended CB only address bus 16 19 for CB PLCC 16 23 for CB QFP Pin function is selected on a per pin basis TXCAN Push pull output to the CAN bus line RXCAN High impedance input only from the CAN bus line ADVANGE INFORMATION 9 87C196CA 87C196CB 87C196CB Memory Map Address Description FFFFFFH Program Memory Internal EPROM or External Memory FF2080H Determined by EA Pin FF207FH Special Purpose Memory Internal EPROM or External Memory FF2000H Determined by EA Pin External Memory FFO600H Internal RAM Identically Mapped into 00400 005 FFO400H FFOSFFH External Memory FFO100H FFOOFFH Reserved for ICE FFOOOOH FEFFFFH Overlayed Memory External Accesses into Memory Ranges to FEFFFFH will 0
16. s 1 mst strcse AS87C196CB Dm gis simo g e 6s B voc C17 View of component es mounted on PC board P2 4 INTOUT Ne P2 5 HOLD 2 6 HLDAM oncer CLKOUT E Yoo xmi Ne Po o acHo P6 7 s01 Po 1 acH P6 6 5c1 Po 2 acH2 P6 5 s00 PO 3 ACHS P6 4 sc0 Po 4 acHa 3132 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 COC TooToo oo ooo ooo T 272405 33 Figure 4 100 Pin QFP AS87C196CB Diagram ADVANGE INFORMATION 87C196CA 87C196CB 9 8 76 54 3 2 16857 65 6 62 61 amisi C12 veo AD11 P4 3 215 55 a EPAO P1 0 T2CLK monea 87C196CA speni 68 14 PLCC si Too Vis spend 07 83 Component Side sifre Soris ids of PC Board 105 3 B 22 02 832 B acts Po s Chas ss Bac moa 925 27 28 29 30 31 52 33 34 35 36 37 38 39 40 41 42 43 ape 272405 3 jure 5 68 Pin PLCC 87C196CA Diagram 6 ADVANGE INFORMATION 87C196CA 87C196CB Name and Function Main Supply Voltage 5V Digital circuit ground 0V There are 7 Vss pins CB 4 on all of which MUST be connected to a single ground plane Reference for the A D converter 5V
17. the bus cycle is writing to an odd memory location is only valid during 16 bit external Also an LSIO pin when not BHE WRH P5 4 SLPINT Dual function I O pin As a bidirectional port pin or as a system function The system function is a Slave Port Interrupt Output Pin on CA bidirectional port pin only 5 3 80 Read signal output to external memory RD is active only during external memory reads or LSIO when not used as RD P5 2 WR WRL amp Write and Write Low output to external memory as selected by the CCR WR will go low for every external write while WRL will go low only for external writes where an even byte is being written WR WRL is active during external memory writes Also an LSIO pin when not used as WR WRL P5 1 INST CB only Output high during external memory read indicates the read is instruction fetch INST is valid throughout the bus cycle INST is active only during external memory fetches during internal EPROM fetches INST is held low Also LSIO when not INST P5 0 ALE ADV Address Latch Enable or Address Valid Output as selected by CCR Both pin options provide a latch to demultiplex the address from the address data bus When the pin is it goes inactive high at the end of the bus cycle ADV 4 can be used as a chip select for external memory ALE ADV is active only during external memory accesses Also LSIO when not us
18. updated and read The programmer should not use the correspond ing bits associated with the removed port pins to conditionally branch in software Treat these bits as RESERVED ADVANGE INFORMATION 87C196CA 87C196CB Additionally these port pins should be setup in ternally by software as follows 1 Written to PXREG as 1 or 0 2 Configured as Push Pull PxIO as 0 3 Configured as LSIO This configuration will effectively strap the pin either high or low DO NOT Configure as Open Drain output 1 or as an Input pin This device is CMOS 6 EPA Timer RESET Write Conflict If the user writes to the EPA timer at the same time that the timer is reset it is indeterminate which will take precedence Users should not write to a timer if using EPA signals to reset it 7 Valid Time Matches The timer must incre ment decrement to the compare value for a match to occur A match does not occur if the timer is loaded with a value equal to an EPA compare value Matches also do not occur if a timer is reset and 0 is the EPA compare value 8 Write Cycle during Reset If RESET occurs dur ing a write cycle the contents of the external memory device may be corrupted 9 Indirect Shift Instruction The upper 3 bits of the byte register holding the shift count are not masked completely If the shift count register has the value 32 X n where n 1 3 5 7 operand will be shifted 32 times This should have result
19. 96CB intel 5 EPROM PROGRAMMING WAVEFORMS SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE RESET Tow H rie ADORESS COMMAND E TDDRESSCOMNAND E Tux Tex Pla PROG P2 2 FER P2 0 272405 26 SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT ADDRESS COMM VER BITS WO DUMP VER BITS WD DUMP mE N 272405 27 26 ADVANGE INFORMATION intel K 87C196CA 87C196CB SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE AND AUTO INCREMENT ADURESS COMNAND AA DATA Eu EN m 27405 28 CHARACTERISTICS SERIAL PORT SHIFT REGISTER MODE SERIAL PORT TIMING SHIFT REGISTER MODE 0 Test Conditions 40 to 125 5 0 10 Vss 0 0V Load Capacitance pF Symbol Parameter Min Max Units Tax Serial Port Clock Period 8 Tosc ns Serial Port Clock Falling Edge to Rising Edge 4Tosc 50 4Tosc 50 ms Output Data Setup to Clock Rising Edge 3 ns Output Data Hold after Clock Rising Edge 2 50 ns Next Output Data Valid after Clock Rising Edge 2Tosc 50 ms Input Data Setup to Clock Rising Edge 2 200 ns _ Input Data Hold after Clock Ri
20. KE OPERATION Symbol Parameter Min Max Units TcucH Clock Period at ns Clock Low Time Clock High Time 21 10 nst Clock Falling to Data Valid Master 051 15 20 ns Clock Falling to Data Valid Slave 051 1 5t 50 ns Data In Setup to Clock Rising Edge 10 ns Clock Rising Edge to Data in Invalid tt 16 ns Timings are guaranteed by design NOTE 1 This specification refers to input clocks during slave operation During master operation the device will output a nominal 50 duty cycle clock ES 2 3 p Took Slave Receiver Pulls Sox low 272405 34 NOTE The top SCx signal assumes that the SSIO is configured to sample on the leading edge with an active high clock signal The SCx signal wil be different for other configurations however setup and hold timings vill still be the same in relation to the latching edge of SCx Figure 6 Synchronous Serial Port ADVANGE INFORMATION 23 87C196CA 87C196CB EXTERNAL CLOCK DRIVE intel 272405 24 AC Testing inputs are driven at 3 5V for a logic 1 and 0 454 for a logic 0 Timing measurements are made at 20V for a logic 1 and 0 8V for logic 0 Symbol Par
21. SBs Differential Non Linearity 075 075 LSBs Channel to Channel Matching 01 0 10 LSBs Repeatability 025 15850 Temperature Coefficients Offset 0 009 158 00 Full Scale 0 009 158 00 Differential Non Linearity 0 009 158 00 Off Isolation 0 8023 Feedthrough EXE Power Supply Rejection 60 Input Resistance 750 12K DC Input Leakage 10 0 30 Voltage on Analog Input Pin ANGND 05 Vaer 05 ve Sampling Capacitor 30 pF An LSB as used here has a value of approximately 5 mV NOTES These values are expected for most parts at 25 C but are not tested or guaranteed DC to 100 KHz 1 2 3 Multiplexer break before make is guaranteed 4 Resistance from device pin through internal MUX to sample capacitor 5 5 Applying voltages beyond these specifications will degrade the accuracy of other channels being converted conversions performed with processor in IDLE mode ADVANGE INFORMATION 29 87C196CA 87C196CB 8 BIT MODE A D OPERATING CONDITIONS Symbol Description Units Ambient Temperature 40 125 C Voc Digital Supply Voltage 450 550 v VREF Analog Supply Voltage 450 550 Tsam Sample Time 20 use Tcowv Conversion Time 12 15 Fosc Oscillator Frequency 40 200 MHz NOTES 1 Vaer must be within 0 5V of Voc 2 The value of AD
22. ameter Min Max Units Oscillator Frequency 4 20 MHz Oscillator Period Tosc 50 0 250 ns High Time 0 35 x Tosc 0 65 ns Low Time 0 85 X Tosc 0 65 ns Rise Time 10 ns Trex Fall Time 10 ns EXTERNAL CLOCK DRIVE WAVEFORMS 27240 23 AC TESTING INPUT OUTPUT WAVEFORMS FLOAT WAVEFORMS meuts ourrurs 9 E xs 7 TIMING REFERENCE FM 2 2 i Vioag 015v 0 459 Eit 272405 25 For timing purposes a Port Pin is no longer floating when a 150 mV change from load voltage occurs and begins to float when a 150 mV change from the loading level occurs loL lon 15 mA EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by T for time The characters in a pair indicate a signal and its condition respectively Symbols represent the time between the two signal condition points 24 HA HLDA L ALE ADV BR BREG Q Data Out X No Longer C CLKOUT RD RD Valid W WR WRR WRI Z Floaing 6 X XTAL1 H HOLD Y READY ADVANGE INFORMATION intel EPROM IFICATIONS AC EPROM PROGRAMMING CHARACTERISTICS Operating Conditions Load Capacitance 150 pF 25 C 6 Vaer 50V 405 Vss 87C196CA 87C196CB ANGND OV 12 5V 0
23. cal characteristics for the CAN mod were removed The electrical characteristics for TXCAN and RXCAN are identical to standard port pins tosc 1 freq was modified to reflect 20 Mhz tim ings torp Oscillator Fail Detect Specification for clock failure to RESET pin pulled low was added to the data sheet 4 min 40 max has been increased to tosc 25 ns min from tosc 30 ns min tnxpx has been replaced by taHox taaz has been increased to 20 ns max from 5 ns max Ipp programming supply current has been in creased to 200 mA from 100 mA Conversion time for 10 bit A D conver sions has been decreased to reflect 20 Mhz op eration Rast was added for the 87C196CA min 6 65 parameters switched to accu rately reflect this timing parameter tigi Separate timings for the 87 196 vs 87C196CB tg c for the CB is min 8 ns max 20 ns For the CA tuc min 4 ns max 30 ns changed to 10 ns from 5ns tavav added for the 87 196 tiav added for the 87 196 tcLax added for the 87 196 tnipy Separate timings for 87 196 30 ns For the 87 196 taLov max Togo 22 ns HOLD HOLDA timings added for 87 196 Slave Port Timings added for the 87 196 Separate specifications for tpipy for the 87C196CB min 100 Toso For the
24. dependent on the accuracy and stability of Vacr Vggr must be close to since it supplies both the resistor ladder and the analog portion of the convert er and input port pins There is also an AD TEST SFR that allows for conversion on ANGND and as well as adjusting the zero offset The abso lute error listed is without doing any adjustments A D CONVERTER SPECIFICATION The specifications given assume adherence to the operating conditions section of this data sheet Test ing is performed with 5 12V and 20 MHz operating frequency After a conversion is started the device is placed in IDLE mode until the conver sion is complete ADVANGE INFORMATION intel 87C196CA 87C196CB 10 BIT MODE A D OPERATING CONDITIONS Symbol Description Units Ta Ambient Temperature 40 125 Voc Digital Supply Voltage 450 550 v VREF Analog Supply Voltage 450 550 Tsam Sample Time 20 use Tcowv Conversion Time 15 18 us Fosc Oscillator Frequency 40 200 MHz NOTES 1 Vaer must be within 0 8V of Voc 2 The value of AD selected to meet these specifications 10 BIT MODE A D CHARACTERISTICS Using Above Operating Conditions Parameter Typ Min Max Units Resolution p 1257 yd Absolute Error 230 LSBs Full Scale Error 0 25 205 LSBs Zero Offset Error 025 05 Non Linearity 10 20 30 L
25. ed as ALE ADVANGE INFORMATION intel 87C196CA 87C196CB Symbol Name and Function PORT 3 and 4 8 bit bidirectional I O ports with open drain outputs These pins are shared with the multiplexed address data bus which has strong internal pullups P2 7 CLKOUT Output of the internal clock generator The frequency is the oscillator frequency CLKOUT has a 50 duty cycle Also LSIO pin when not used as CLKOUT P2 6 HLDAs Bus Hold Acknowledge Active low output indicates that the bus controller has relinquished control of the bus Occurs in response to an external device asserting the HLD signal Also LSIO when not used as P2 5 HLD Bus Hold Active low signal indictes that an external device is requesting control of the CB only bus Also LSIO when not used HLD 2 Interrupt Output This active low output indicates that a pending interrupt requires use of the external bus Also LSIO when not used INTOUT P2 3 BREQ Bus Request This active low output signal is asserted during a HOLD cycle when the CB only bus controller has a pending external memory cycle Also LSIO when not used as BREQ P22 EXTINT A positive transition on this pin causes a maskable interrupt vector through memory location 203CH Also LSIO when not used as EXTINT P2 1 RXD Receive data input pin for the Serial I O port Also LSIO if not used as P2 0 TXD Transmit data
26. ed in no shift taking place 10 P2 7 CLKOUT P2 7 CLKOUT does not op erate in open drain mode 31 87C196CA 87C196CB 87C196CA ERRATA This data sheet was published prior to first available silicon Consequently there is no known errata at this time 87C196CA DESIGN CONSIDERATIONS 1 PORTO On the 87C196CA the analog inputs for P0 0 and 1 have been multiplexed and tied to Ver There fore initiating an analog conversion on ACHO or will result in a value equal to full scale On the CA the digital inputs for these two channels are tied to ground therefore reading 0 or will result in a digital 0 2 PORT1 On the 87C196CA P1 4 P1 5 P1 6 and P1 7 have been removed from the device and is unavailable to the programmer Corresponding bits in the port reg isters have been hard wired to provide the follow ing results when read Register Bits When Read P1 PINx x 4567 1 REGx x 4567 1 P1 DIRX x 4567 1 P1 MODEx 4567 Writing to these bits wil hava affect 3 PORT2 On 87C196CA P2 3 and P2 5 have been re moved from the device and are not available to the programmer Corresponding bits in the port registers have been hard wired to provide the following re sults when read 32 Register Bits P2 PINx 3 5 1 P2 REGx 35 1 P2 DIRXx 3 5 P2 MODEx 3 5 o
27. es to these locations to be directed to off chip memory EA 12 5V causes execution to begin in the Programming Mode EA is latched at reset PLLEN 196CB only Selects between mode or bypass mode This pin must be either tied high low PLLEN pin 0 bypass mode PLLEN pin 1 places 4x at the input of the crystal oscillator Allows for a low frequency crystal to drive the device i e 5 MHz 20 MHz operation 64 67 550 Dual function I O ports have a system function as Synchronous Serial I O Two pins clocks and two pins are data providing for full duplex capability Also LSIO when not used 5510 P63 TIDIR Dual function 1 0 pin Primary function is that of a bidirectional O pin however it CB only may also be used as TIMER Direction input The TIMER1 will increment when this pin is high and decrements when this pin is low P6 2 TICLK Dual function 1 0 pin Primary function is that of a bidirectional pin however may CB only also be used as a TIMER Clock input The TIMER will increment or decrement on both positive and negative edges of this pin P6 0 6 1 EPAB 9 Dual function 1 0 port pins Primary function is that of bidirectional I O System function is that of High Speed capture and compare ADVANGE INFORMATION 7 87C196CA 87C196CB intel Symbol Name and Function P5 7 BUSWIDTH Input for bus width selection
28. ics Device and Package On 7 96 35 0 C W 11 0 C W 84 Lead PLCC Package 7 196 365 C W 10 0 C W 68 Lead PLCC Package NOTES 1 Thermal resistance between junction and the surrounding environment ambient measurements are taken 1 ft away from case in air flow environment Thermal resistance between junction and package face case 2 All values of and jc may fluctuate depending on the environment with or without airflow and how much airflow and device power dissipation at temperature of operation Typical variations are 2 C W 3 Values listed are at a maximum power dissipation of 1 0W ADVANGE INFORMATION 3 87C196CA 87C196CB intel m a M seca MAE wenn Bros ma se si Bestes simos s Bros non sapis s Bros in amps ss Bros aon esp Bros jon TPUT ee E PEE 2 2405 14 Figure 3 84 Pin PLCC ANB7C196CB Diagram ADVANGE INFORMATION in 87C196CA 87C196CB 100 9 98 97 96 95 94 93 92 91 90 89 88 87 85 84 83 82 Ne 4007P3 0 79 reser tie 76 i Ps 3 A20 EPoRT 4 Yas c nBw c Yes 7 a ps ozaove saue mm
29. nditions Capacitance Load on All Pins 100 pF Rise anf Fall Times 10 ns The system must meet these specifications to work with the 87 196 Symbol Parameter Units Tavw Address Valid to Ready Setup 2 Tose 75 Tuw ALE Low to READY Setup Tosc 70 Non READY Time No Upper Limit ns Touyx READY Hold after CLKOUT Low o Toso 30 nst Address Valid to BUSWIDTH Setup 2 Tosc 75 ns 9 Tuev ALE Low to BUSWIDTH Setup Toso 60 ns 9 Torax BUSWIDTH Hold after CLKOUT Low ns Tavov Address Valid to Input Data Valid 3 55 ns RD active to input Data Valid CA Toso 22 Tosc 30 2 CLKOUT Low to Input Data Valid Tosc 50 ns End of RD to Input Data Float Tosc ns TRHOX Data Hold after RD High ns NOTES 1 If Max is exceeded additional wait states will occur 2 states are used add 2 n where n number of wait states If mode 0 is selected one state minimum is always added If additional wait states are required add 2 Tosc to the specification ADVANGE INFORMATION 17 87C196CA 87C196CB 87C196CA CB SYSTEM BUS TIMING CLOCKOUT ALE ADV BUS READ WR BUS WRITE INST Tose XTAL1 Teraz ERE DATA IN Tavov
30. pecifications for this characteristic For temperatures lt 100 C typical is 10 pA 8XC196CB ADDITIONAL BUS TIMING MODES The 8XC196CB device has 2 bus timing modes 0 external memory interfacing Mode 0 is the standard timing mode but 1 mini mum wait state is always inserted in external bus MODE 3 cycles Mode 3 is the standard timing mode Use this mode for systems that emulate the 8XC196KR bus tim ings ADVANGE INFORMATION 15 87C196CA 87C196CB AC CHARACTERISTICS Over Specified Operating Conditions Test Conditions Capacitance Load on All Pins 100 pF Rise and Fall Times 10 ns The 87 196 will meet these specifications Symbol Parameter Min Max Units Frequency on XTALT 40 20 MHC Tosc Period 1 500 250 ns XTAL1 High to CLKOUT High or Low 20 110 ns Toro Clock Failure to Reset Pulled 4 40 Tac CLKOUT Period 2Tosc s CLKOUT High Period 15 s Teun CLKOUT Low to ALE ADV High 15 10 ns ALE RDV Low to CLKOUT High 20 15 ns Cycle Time 4 Tou High Time Tosc 10 10 ns Tavu Address Valid to ALE Low Tose 15 Address Hold After ALE ADV Low Tosc 40 ns Tun ALE RDV Low to RD Low Tosc 30 s Tac RD Low to CLKOUT Low
31. perature characterization of the device has been per formed Contact your local sales office before finali to verify you have the latest information TUE M 35 1 a qo eso ron tra aa ea 272405 30 Figure 1 8XC196CB Block Diagram 2 ADVANGE INFORMATION intel 87C196CA 87C196CB PROCESS INFORMATION All thermal impedance data is approximate for static air conditions at 1 0W of power dissipation Values These devices are manufactured on P629 5 a change depending on operation conditions and CHMOS 11 process Additional process and reli application See the Intel Packaging Handbook or ability information is available in Intel s Components der number 240800 for a description of Intel s ther Quality and Reliability Handbook Order Number mal impedance test methodology 210997 Frequency Designation 20 202 No Mork 16 Miz Product Designation Product Fomily CHWOS Technology Program Memory Options 7 EFRON Package Options N PLCC plastic leaded chip carrier FP Quod Flatpack CB only Tomperoture and Burn in options A 4096 to 1259 ambiant with Intel Standard Burn in Figure 2 The 87C 196CA CB Familiy Nomenclature Thermal Characterist
32. r y m y 272405 22 SLAVE PORT TIMING SLPL 1 2 3 Symbol Parameter Min Max Units CS Low to ALE Low 20 TSRHEH RD or WR High to CS High 60 ns ALE Low to RD Low Tosc ns RD Low Period Tosc ns TswiwH WR Low Period Tosc ns Address Valid to ALE Low 20 ns ALE Low to Address Invalid 20 ns Tsniov Low to Output Data Valid 60 ns Input Data Setup to WRHigh 20 ns WR High to Data Invalid 30 ns TsRHDZ RD High to Data Float 15 ns NOTES 1 Test Conditions Fosc 20 MHz Tosc 60 ns Rise Fall Time 2 These values are not tested in production and are based upon theoretical estimates and or laboratory tests 3 Specifications above are advanced information and are subject to change 22 10 ns Pin Load 100 pF ADVANGE INFORMATION intel 87C196CA 87C196CB t 1 state time 125 ns 16 MHz NORMAL MASTER SLAVE OPERATION Symbol Parameter Units TcucH Clock Period at ns Tou Clock Low Time Clock High Time 21 10 nst Clock Falling to Data Valid Master 051 15 20 ns Clock Falling to Data Valid Slave 051 15 50 ns Data In Setup to Clock Rising Edge 10 ns Clock Rising Edge to Data in Invalid tt 16 ns Timings are guaranteed by design HANDSHA
33. sgned to be simlar to the 87C196KR bus pe Soo AC Tini section or actua timings data 12 ADVANGE INFORMATION intel ABSOLUTE MAXIMUM RATINGS Storage Temperature 60 C to 150 Voltage from Vpp or EA to Vss or ANGND 2 0 5 13 0V Voltage from Any Other Pin to Vss or ANGND 0 5 to 70 This includes Vpp on ROM and CPU devices 87C196CA 87C196CB NOTICE This data sheet contains information on products in the sampling and initial production phases of development The specifications are subject to change without notice Verify with your local Intel Sales office that you have the latest data sheet be Tore finalizing a design WARNING Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage These are stress ratings only Operation beyond the Power Dissipation 10W Operating Conditions is not recommended and tended exposure beyond the Operating Conditions may affect device reliability OPERATING CONDITIONS Symbol Parameter Min Max Units TA Ambient Temperature Under Bias 40 125 Veo Digital Supply Voltage 450 550 VREF Analog Supply Voltage 450 5 50 v Fosc Oscillator Frequency 4 20 NOTE ANGND and Vss should be nominally at the same potential DC CHARACTERISTICS Under Listed Operating Conditions Symbol Parameter Test Conditions uni
34. sing Edge 0 ns Last Clock Rising to Output Float 5 Tosc ns NOTE 8 Parameters not tested ADVANGE INFORMATION 27 87C196CA 87C196CB intel WAVEFORM SERIAL PORT SHIFT REGISTER MODE SERIAL PORT WAVEFORM SHIFT REGISTER MODE XX 27405 29 A TO D CHARACTERISTICS The sample and conversion time of the A D convert er in the 8 bit or 10 bit modes is programmed by loading a byte into the AD TIME Special Function Register This allows optimizing the A D operation for specific applications The AD TIME register is functional for all possible values but the accuracy of the A D converter is only guaranteed for the times specified in the operating conditions table The value loaded into AD TIME bits 5 6 7 deter mines the sample time SAMP The value loaded into AD TIME bits 0 1 2 3 and 4 determines the bit conversion time CONV These bits as well as the equation for calculating the total conversion time T are shown in the following table AD TIME 1FAFH Byte 4 3 2 1 o Tipe Bi Conversion Time SAMP 1 state times n 1 state times db n 21091 Equation SAMP Bx CONV 25 total conversion time states number of bits conversion 8 or 10 programmed register value 28 The converter is ratiometric so absolute accuracy is
35. tics for the PLCC packages was added to the data sheet for the CB 35 0 C W 11 0 C W For the CA 365 C W and 10 0 C W 5 The AN87C196CB pin package diagram was corrected to show EA as opposed to EA 6 The REMAP bit funciton for CCB2 was corrected Setting this bit to 0 selects EPROM CODERAM in segment OFFH only Setting this bit to 1 selects both segment OFFH and segment 00H 7 taLaz has been changed to 5 ns from 20 ns 8 for the CA has been changed to tosc 20 from tosc 30 9 tci gx has been changed to 0 ns min from tosc 46 max 10 Timing specifications for the SSIO are now add ed These timings are currently guaranteed by design 11 Added frequency designation to family nomen clature Figure 2 This is the 002 revision of the 87C196CA data sheet The following difference exist between the 001 version and the 002 revision 1 This data sheet now includes the specifications for the 87C196CB as well as the 87C196CA 2 ABSOLUTE MAXIMUM RATINGS have been added 3 Maximum Frequency has been increased to 20 MHz 4 Maximum ICC has been increased from 75 mA to 100 mA for the 90 mA for the CA 5 Idle Mode current has been increased to 35 mA from 30 mA for the CB 40 mA for the CA 6 Input leakage current for Port 0 111 was de creased to 1 5 from 2 0 pA for the ADVANGE INFORMATION 7 25 26 87C196CA 87C196CB The electri
36. ts Supply Current 20 MHz 40 C to 125 C Ambient Voc Vaer 55 While device in Reset 90 ma ca 100 imer A D Reference Supply Current 5 mA nue Idle Mode Current 20 MHz Voc Vngr 55 40 ma ca 35 mA __ Powerdown Mode Current Voc Vngr 5546 9 wa Vi Voltage all pins ForPORTOU V Vim Input High Voltage For PORTO 07 Voc 05 V VoL Output Low Voltage 00 03 v Outputs Configured as 2mA 045 v Complementary lo 7 0 15 Y Vou Output High Voltage 2004A0 03 Y Outputs Configured 82 07 Y Complementary 70mA 15 Y ADVANGE INFORMATION 13 87C196CA 87C196CB intel 87C196CB 1 vs Frequency 100 Active 90 j Active 83 mA 7 0 lae 30 Idle 28 na 2 o 2 2 bd m 272405 31 87 196 Icc vs Frequency 0 Active Ioc Max 50 Active kc 275 7 so so cu ot lale NAX 40 mA 5 lle ge 328 2 10 2 8 Ww 29 272405 32 14 ADVANGE INFORMATION intel 87C196CA 87C196CB DC CHARACTERISTICS Under Listed Operating Conditions Continued
37. ust be written with 0 Refer to 186 8 User s Guide for SFR CAN and Paging Descriptions 87C196CA Memory Map Address Description OOFFFFH External Memory 00A000H OO9FFFH Internal EPROM 32 Kbytes 002080H 00207FH Reserved Memory Internal EPROM or External Memory 002000H Determined by EA Pin Memory Mapped Special Function Registers SFR s 001 Internal Special Function Registers SFR s 001 00 OO1EFFH Internal CAN Peripheral Memory 001E00H 001DFFH External Memory 000500H 0004 Internal RAM Code RAM 000400H Address with Indirect or Indexed Modes 0003FFH Internal Register Upper Register File Address with Indirect or Indexed Modes or 000100H through Windows 2 0000 Internal Register RAM Lower Register File Address with Direct Indirect or Indexed 000018 Modes62 000017H CPU Special Function Registers SFR s 4 000000H NOTES 1 Refer to 8XC196KX Family User s Guide for SFR Description 2 Code executed in locations 0000H to wil be forced external 3 Reserved SFR bit locations must be written with 0 ADVANGE INFORMATION 11 87C196CA 87C196CB intel CCB 2018h Byte CCB1 201Ah B
38. x family as well as integration of on chip networking capability The 87C196CA has few er peripheral functions than the 196KR due in part to the integration of the CAN peripheral Following are the functionality differences between the 196KR and 196CA devices 196KR Features Unsupported on the 196CA Analog Channels 0 and 1 INST Pin Functionality SLPINT and SLPCS Pin Support HLD HLDA Functionality External Clocking Direction of Timer 1 Quadrature Clocking Timer 1 Dynamic Buswidth EPA Capture Channels 4 7 1 External Memory Removal of the Buswidth pin means the bus cannot dynamically switch from 8 to 16 bit bus mode or vice versa The pro grammer must define the bus mode by setting the associated bits in the CCB 2 Auto Programming Mode The 87C196CA de vice will ONLY support the 16 bit zero wait state bus during auto programming 3 EPA4 through EPAT Since the CA device is based on the KR design these functions are in the device however there are no associated pins A programmer can use these as compare only channels or for other functions like software timer start an A D conversion or reset timers 4 Slave Port Support The Slave port can not be used on the 196CA due to a function change for P5 4 SLPINT and P5 1 SLPCS not being bond ed out 5 Port Functions Some port pins have been re moved P5 1 P6 2 P6 3 P1 4 through P1 7 P2 3 P2 5 and P0 1 The PxREG PxSSEL and registers can still be
39. yte p gt 1 Enables Ponordown 1 Ewo see tate see Tato ware wane a mw soe Taio af Ae aeo aove s woe aways a ico soo tanie Reserved Must 86 s soo Tanie s Reserved Must 800 soo Tabie tor ca 7 Loci soo Tabie 7 mensen CCB2 201Ch Byte CB Only o 0 select 1 8 or 24 84 Mode EPROM CODERAM in Segment OFFH ony 2 REMAP 1 Select Both Segment OFFH and Segment 00H af Reserved Mist bo Reserved Must be 1 Reserved Musto ef 1 Resered Mist bo Reserved Must be 1 Loco Function IRC2 IRC1 IRCO Max Wait States 0 0 Read and Write Protected 0 0 Zero Wait States 0 1 Write Protected Only 1 0 1 Wait State 1 0 Read Protected Only 1 0 1 2 Wait States 1 jJ No Protection 1 1 0 3 Wait States 1 1 1 INFINITE MSEL1 MSELO Timing Mode 0 Mode 0 1 Wait KR BWA 2800 Bus Width 0 1 Reserved Must Not Be Used 0 ILLEGAL 1 0 Reserved Must Not Be Used 0 1 16 Bit Only 1 1 Mode 3 1 o 8 Bit Only 1 t BW Pin Controlled Designed to bo simlar to the 87C196KR bus tat KR umng win automate al stata oe AC Timings section tor actua timings data Modo 3 KR De
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