ST ST7066 Manual
Contents
1. MPU 5V 2 2K 10K VR 10K 30K Note R 2000 6 13 29 V1 22. E bis PAD DBO DB7 26 2000 6 13 ST7066 LCD and ST7066 Connection V1 2 1 5x8 dots 8 characters x 1 line 1 4 bias 1 8 duty ST7066 LCD Panel x 1 line 8 Characters 2 5x11 dots 8 characters x 1 line 1 4 bias 1 11 duty ST7066 LCD Panel x 1 line 8 Characters 27 2000 6 13 ST7066 V1 2 3 5x8 dots 8 characters x 2 line 1 5 bias 1 16 duty LCD Panel x 2 line 8 Characters 4 5x8 dots 16 characters x 1 line 1 5 bias 1 16 duty ST7066 LCD Panel 16 Characters x 1 line 28 2000 6 13 ST7066 Ion Circul ST7066 Applicat Dot Matrix LCD Panel 1 16 SEG1 40 D ST7066 ST7065 V1 V2 V4 V5 ST7065 V1 V2 V4 V5 7
3. V1 2 2000 6 13 10 ST7066 Table 4 Cont ROM Code 0B LL ea bh h hi man 2000 6 13 V1 2 ST7066 Character Code CGRAM Character Patterns DDRAM Data Address CGRAM Data DE bO 0 1 1 1 1 1 0 0 0 1 I 0 0 0 0 1 1 oloMNO O 0 0 010 9 aoto olo o olofo olofo 1 1 0 lk 0 1 1 1 1 1 0 0 0 1 0 0 1 HE 0 0 1 1 1 1 1 1 1 0 0 001119 19 9 olola 111011 olola 111010 1 111111 Table 5 Relationship between CGRAM Addresses Character Codes DDRAM Character patterns CGRAM Data Notes 1 Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 3 bits 8 types 2 CGRAM address bits 0 to 2 designate the character pattern line position The 8th line is the cursor position and its display is formed by a logical OR with the cursor Maintain the 8th line data corresponding to the cursor display position at 0 as the cursor display If the 8th line data is 1 1 bits will light up the 8th line regardless of the cursor presence 3 Character pattern row positions correspond to CGRAM data bits 0 to 4 bit 4 being at t
4. ST7068 Sitronix Features e 5x8and5x 11 dot matrix possible Low power operation support 2 7 to 5 5V Wide range LCD driver power 3 0 to 11V Correspond to high speed MPU bus interface 2 MHz when 5V 4 bit or 8 bit MPU interface enabled 80x 8 bit display RAM 80 characters max 9 920 bit character generator ROM for total of 240 character fonts 208 character fonts 5 x 8 dot 32 character fonts 5 x 11 dot 64x 8 bit character generator RAM 8 character fonts 5 x 8 dot 4character fonts 5 x 11 dot Description The ST7066 dot matrix liquid crystal display controller and driver LSI displays alphanumeric Japanese kana characters and symbols It can be configured to drive a dot matrix liquid crystal display under the control of a 4 or 8 bit microprocessor Since all the functions such as display RAM character generator and liquid crystal driver required for driving a dot matrix liquid crystal display are internally provided on one chip a minimal system can be interfaced with this controller driver The ST7066 has pin function compatibility with the HD44780 KSOO66U and SED1278 that allows the user to easily replace it with an ST7066 The ST7066 character generator ROM is extended to generate il 5 7066 Dot Matrix LCD Controller Driver 16 common x 40 segment liquid crystal display driver Programmable duty cycles 1 8 for one line
5. OSC1 OSC2 CPG Instruction Display data RAM DDRAM 80x8 bits CL1 CL2 Timing Generator Common Signal Driver Address Counter DR SEG1 to 40 bit SEG40 latch circuit Segment Signal Driver LCD Drive Voltage Selector Character generator ROM CGROM 9 920 bits Character generator RAM CGRAM 64 bits Parallel Serial converter and Attribute Circuit Cursor v4 V5 V1 2 2000 6 13 ST7066 Pad Arrangement Chip Size 2300x3000 Coordinate Pad Center Origin Chip Center Pad Size 90x90 Unit um EJ E DET EIE 0 0 0 0 0000000000000000 Subtrate VDD V1 2 3 64 2000 6 13 ST7066 Pad Location Coordinates V1 2 Function X Y 1 SEG22 1040 1400 2 SEG21 1040 1270 3 SEG20 1040 1140 4 SEG19 1040 1020 5 SEG18 1040 900 6 SEG17 1040 780 7 SEG16 1040 660 8 SEG15 1040 540 9 SEG14 1040 420 10 SEG13 1040 300 11 SEG12 1040 180 12 SEG11 1040 60 13 SEG10 1040 60 14 SEG9 1040 180 15 SEG8 1040 300 16 SEG7 1040 420 17 SEG6 1040 540 18 SEG5 1040 660 19 SEG4 1040 780 20 SEG3 1040 900 21 SEG2 1040 1020 22 SEGI 1040 1140 23 GND 1040 1270 24 05 1 1040 1400 25 05 2 910 1400 26 V1 780 1400 27 V2 660 1400 28 V3 540 14
6. When BF High indicates that the internal operation is being processed So during this time the next instruction cannot be accepted The address Counter AC stores DDRAM CGRAM addresses transferred from IR After writing into reading from DDRAM CGRAM AC is automatically increased decreased by 1 Write Data to CGRAM or DDRAM RS RW DB7 DB6 DB5 DB4 083 082 DBO E E Write binary 8 bit data to DDRAM CGRAM The selection of RAM from DDRAM CGRAM is set by the previous address set instruction DDRAM address set CGRAM address set RAM set instruction can also determine the AC direction to RAM After write operation the address is automatically increased decreased by 1 according to the entry mode Read Data from CGRAM or DDRAM RS RW DB7 DB6 DB5 DB4 083 082 DBO IEEE lee alee Read binary 8 bit data from DDRAM CGRAM The selection of RAM is set by the previous address set instruction If address set instruction of RAM is not performed before this instruction the data that read first is invalid because the direction of AC is not determined If you read RAM data several times without RAM address set instruction before read operation you can get correct RAM data from the second but the first data would be incorrect because there is no time margin to transfer RAM data In case of DDRAM read operation cursor shift instruction plays the same role as DDRAM address set instruction
7. it also transfer RAM data to output data register After read operation address counter is automatically increased decreased by 1 according to the entry mode After CGRAM read operation display shift may not be executed correctly In case of RAM write operation after this AC is increased decreased by 1 like read operation In this time AC indicates the next address position but you can read only the previous data by read instruction V1 2 17 2000 6 13 ST7066 Reset Function Initializing by Internal Reset Circuit An internal reset circuit automatically initializes the ST7066 when the power is turned on The following instructions are executed during the initialization The busy flag BF is kept in the busy state until the initialization ends BF 1 The busy state lasts for 10 ms after VCC rises to 4 5 V 1 Display clear 2 Function set DL 1 8 bit interface data 0 1 line display F 0 5 8 dot character font 3 Display on off control D 0 Display off C 0 Cursor off B 0 Blinking off 4 Entry mode set 1 Increment by 1 S 0 No shift Note If the electrical characteristics conditions listed under the table Power Supply Conditions Using Internal Reset Circuit are not met the internal reset circuit will not operate normally and will fail to initialize the ST7066 For such a case initialization must be performed by the MPU as explain by the following figure V1 2 18 2000 6 13 ST7066 V1 2
8. 8 bit Interface Wait time 15ms After Vcc 4 5V RS RW D7 D6 D5 D4 D3 D2 D1 DO 000011xxxx Wait time 4 1ms 000011xxxx Wait time 100us 000011xxxx 000011NFxx 0000001000 0000000001 0000000115 Initialization End BF cannot be checked before the Instruction Function set BF cannot be checked before the Instruction Function set BF cannot be checked before the Instruction Function set BF can be checked after the following Instructions Function Set Display Off Display Clear Entry mode set 2000 6 13 ST7066 V1 2 4 bit Interface Wait time 15ms After Vcc 4 5V RS RW D7 D6 D5 D4 0 0 0 0 1 1 Wait time 4 1ms Wait time 100us oojoo 2 Initialization End 20 BF cannot be checked before the Instruction Function set BF cannot be checked before the Instruction Function set BF cannot be checked before the Instruction Function set BF can be checked after the following Instructions Function Set Display Off Display Clear Entry mode set 2000 6 13 ST7066 Interfacing to the MPU The ST7066 can send data in either two 4 bit operations or one 8 bit operation thus allowing interfacing with 4 or 8 bit MPU For 4 bit interface data only four bus lines DB4 to DB7 are used for transfer Bus lines DBO
9. AC AC 1 AC AC 1 AC AC AC AC 2000 6 13 ST7066 DL Interface data length control bit When DL High it means 8 bit bus mode with MPU When DL Low it means 4 bit bus mode with MPU So to speak DL is a signal to select 8 bit or 4 bit bus mode When 4 bit bus mode it needs to transfer 4 bit data by two times N Display line number control bit When it means 1 line display mode When High 2 line display mode is set F Display font type control bit When F Low it means 5 x 8 dots format display mode When F High 5 x11 dots format display mode N F Set CGRAM Address RS RW 087 DB6 DB5 083 DB2 No of Display Lines 1 1 2 Character Font 5x8 5x11 5x8 DBO a a a Code Set CGRAM address to AC This instruction makes CGRAM data available from MPU Set DDRAM Address RS RW 087 DB6 DB5 084 083 DB2 DBO EXER a Code Set DDRAM address to AC This instruction makes DDRAM data available from MPU When 1 line display mode 0 DDRAM address is from to 4FH In 2 line display mode 1 DDRAM address in the 1st line is from to 27H and DDRAM address the 2nd line is from 40H to 67H V1 2 16 Duty Factor 1 8 1 11 1 16 2000 6 13 ST7066 Read Busy Flag and Address RS RW 087 086 DB5 083 DB2 DBO epe pee espe posses pen Code
10. COM9 to COM16 to COM16 16 LCD are non selection waveforms at 1 8 duty factor and 12 to COM16 are non selection waveforms at 1 11 duty factor to SEG40 40 LCD Segment signals Power supply for LCD drive V1 to V5 5 Power supply 11 V Max Vcc GND 2 Power supply 2 7V to 5 5V GND TE When crystal oscillation is performed a resistor OSC1 OSC2 2 Oscillation must be connected externally When the pin resistor clock input is an external clock it must be input to OSC1 Note 1 Vec gt V1 gt V2 gt V3 gt V4 gt V5 must be maintained 2 Two clock options R 91K 5 R 75K 05 1 05 1 OSC2 Clock input V1 2 5 2000 6 13 517066 FUNCTION DESCRIPTION System Interface This chip has all two kinds of interface type with MPU 4 bit bus and 8 bit bus 4 bit bus or 8 bit bus is selected by DL bit in the instruction register During read or write operation two 8 bit registers are used One is data register DR the other is instruction register IR The data register DR is used as temporary data storage place for being written into or read from DDRAM CGRAM target RAM is selected by RAM address setting instruction Each internal operation reading from or writing into RAM is done automatically So to speak after MPU reads DR data the data in the next DDRAM CGRAM address is transferred into DR automatically Also after MPU writes
11. Pins DBO DB7 Read Mode Reading Data from ST7 A ddress Setup Time Pins RS RW E Address Hold Time Pins RS RW E 2 2 o 5 T Tc PW Ta Tr AS AH 5 5 T T Data Setup Time DBO DB7 Data Hold Time Pins DBO DB7 Interface Mode with LCD Driver ST7065 Clock Pulse with High Pins CL1 CL2 Clock Pulse with Low Pins CL1 CL2 Tost Clock Setup Time CL2 o 2 5 o i 5 8 gt 5 V1 2 24 2000 6 13 ST7066 The relations between Oscillation Frequency and LCD Frame Frequency Assume the oscillation frequency is 270KHZ 1 clock cycle time 3 7us 1 1 8 Duty 400 clocks 1 frame 3 7 us x 400 x 8 11850 us 11 9 ms 2 1 11 Duty 400 clocks 1 frame 3 7 us x 400 x 11 16300 us 16 3 ms 3 1 16 Duty 200 clocks COM1 1 frame 3 7 us x 200 x 16 11850 us 11 9 ms V1 2 25 2000 6 13 ST7066 PAD Configuration 19 Input PAD E No Pull up ZX Em Output PAD CL1 CL2 M D a Input PAD RS RW with Pull up Enable
12. d d M ARN hexadecimal Figure 4 2 Line Display Display Position 1 2 3 4 5 DDRAM 6 7 8 Address SEN Ga ae Shift Left ERES For ud ed Figure 5 2 Line 8 Character Display Example Case 2 For a 16 character x 2 line display the ST7066 can be extended using one 40 output extension driver See Figure 6 W hen display shift operation is performed the DDRAM address shifts See Figure 6 Display 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Position wv Tee Pe e p TT TT Address ad Ea aC a a eS Cd a a Rd Figure 6 2 Line by 16 Character Display Example V1 2 8 2000 6 13 ST7066 Character Generator ROM CGROM The character generator ROM generates 5 x 8 dot or 5 x 11 dot character patterns from 8 bit character codes It can generate 208 5 x 8 dot character patterns and 32 5 x 11 dot character patterns User defined character patterns are also available by mask programmed ROM Character Generator RAM CGRAM In the character generator RAM the user can rewrite character patterns by program For 5 x 8 dots eight character patterns can be written and for 5 x 11 dots four character patterns can be written Write into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the character patterns stored in CGRAM See Table 5 for the r
13. data to DR the data in DR is transferred into DDRAM CGRAM automatically The Instruction register IR is used only to store instruction code transferred from MPU MPU cannot use it to read instruction data To select register use RS input pin in 4 bit 8 bit bus mode Table 1 Various kinds of operations according to RS and R W bits RS RW Operation L L Instruction Write operation MPU writes Instruction code into IR L Read Busy Flag DB7 and address counter DBO DB6 H L Data Write operation MPU writes data into DR Read operation MPU reads data from DR Busy Flag BF When High it indicates that the internal operation is being processed So during this time the next instruction cannot be accepted BF can be read when RS Low and R W High Read Instruction Operation through DB7 port Before executing the next instruction be sure that BF is not High Address Counter AC Address Counter AC stores DDRAM CGRAM address transferred from IR After writing into reading from DDRAM CGRAM AC is automatically increased decreased by 1 When RS Low and R W High be read through DBO DB6 ports V1 2 6 2000 6 13 ST7066 Display Data RAM DDRAM Display data RAM DDRAM stores display data represented in 8 bit character codes Its extended capacity is 80 x 8 bits or 80 characters The area in display data RAM DDRAM that is not used for display can be
14. to DB3 are disabled The data transfer between the ST7066 and the MPU is completed after the 4 bit data has been transferred twice As for the order of data transfer the four high order bits for 8 bit operation DB4 to DB7 are transferred before the four low order bits for 8 bit operation DBO to DB3 The busy flag must be checked one instruction after the 4 bit data has been transferred twice Two more 4 bit operations then transfer the busy flag and address counter data For 8 bit interface data all eight bus lines DBO to 087 are used Supply Voltage for LCD Drive There are different voltages that supply to ST7066 s pin V1 V5 to obtain LCD drive waveform The relations of the bias duty factor and supply voltages are shown as below DutyFactor Factor _ ___ 1 11 1 16 Supply Voltage Voltage 14 LN ess e 1 4 bias 1 5 bias 1 8 1 11 duty 1 16 duty cycle cycle V1 2 21 2000 6 13 ST7066 Timing Characteristics e Writing data from MPU to ST7066 RS R W DBO DB7 Reading data from ST7066 to MPU RS R W DBO DB7 V1 2 22 2000 6 13 ST7066 Absolute Maximum Ratings Characteristics Symbol Power Supply Voltage 0 3V to 7 0V LCD Driver Voltag
15. 00 29 V4 420 1400 30 V5 300 1400 31 CL1 180 1400 32 CL2 60 1400 33 Vcc 60 1400 34 M 180 1400 35 D 300 1400 36 RS 420 1400 37 RW 540 1400 38 E 660 1400 39 DBO 780 1400 40 081 910 1400 Function 540 540 1020 1140 1270 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 2000 6 13 ST7066 Pin Functions NAME NUMBER I O INTERFACED WITH FUNCTION Select registers 0 Instruction register for write Busy flag RS 1 MPU address counter for read 1 Data register for write and read Select read or write R W 1 MPU 0 Write 1 Read E 1 Starts data read write Four high order bi directional tristate data bus pins Used for data transfer and receive DB4 to DB7 4 VO MPU between the MPU and the ST7066 DB7 can be used as a busy flag Four low order bi directional tristate data bus pins Used for data transfer and receive DBO to DB3 4 MPU between the MPU and the ST7066 These pins are not used during 4 bit operation Clock to latch serial data D sent to the CL1 1 Extension driver extenstpn driver CL2 1 Extension driver Clock to shift serial data D M Switch signal for converting the liquid crystal Extension driver drive waveform to AC Character pattern data corresponding to each D 1 Extension driver segment signal Common signals that are not used are changed to non selection waveform
16. e 0 3V to 13 0V Input Voltage 0 3V to 0 3 Operating Temperature 20 C to 70 C Storage Temperature 55 C to 125 C DC Characteristics Ta 25 C Vcc 2 7V 5 5V Gees esce Win vans 0 3 loc Power Supply Current fosc 270KHz Vcc 5V 0 6 mA Input High Voltage 2 2 Voc V Except OSC1 Vii Input Low Voltage 0 3 Do mon I Input High Voltage 1 OSC1 Input Low Voltage OSC2 Output High Voltage 0 1mA 24 Vcc Vou Output Low Voltage lo 0 1mA 0 4 ee Output High Voltage lou 0 04mA 0 9 Vcc Output Low Voltage lo 0 04mA 0 1 Common Resistance Vicp 4V ly 0 05mA 20 ne errem m Input Leakage Vin OV to xi 1 __ l Pull Up MOS Current 5V 2 V1 2 23 2000 6 13 ST7066 AC Characteristics TA 25 C Vcc 5V Internal Clock Operation fosc OSC Frequency R 91KQ 190 270 350 KHz External Clock Operation Write Mode Writing data from MPU to ST7066 Enable Rise Fall TmePinE e Address Setup Time Pins RS RW E Address Hold Time Pins RS RW E fex External Frequency Tr TF 5 Tc PW Tr AS AH T5 2 o 2 T T T 2 Tpsw DataSetupTime
17. elationship between CGRAM addresses and data and display patterns Areas that are not used for display can be used as general data RAM Timing Generation Circuit The timing generation circuit generates timing signals for the operation of internal circuits such as DDRAM CGROM and CGRAM RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other Therefore when writing data to DDRAM for example there will be no undesirable interference such as flickering in areas other than the display area LCD Driver Circuit LCD Driver circuit has 16 common and 40 segment signals for LCD driving Data from CGRAM CGROM is transferred to 40 bit segment latch serially and then it is stored to 40 bit shift latch When each common is selected by 16 bit common register segment data also output through segment driver from 40 bit segment latch In case of 1 line display mode COM1 8 have 1 8 duty COM 11 have 1 11duty and in 2 line mode 16 have 1 16 duty ratio Cursor Blink Control Circuit It can generate the cursor or blink in the cursor blink control circuit The cursor or the blink appears in the digit at the display data RAM address set in the address counter V1 2 9 2000 6 13 Table 4 Correspondence between Character Codes and Character Patterns ROM Code 0A ST7066 r e e z b bd
18. he left 4 As shown Table 5 CGRAM character patterns are selected when character code bits 4 to 7 are all 0 However since character code bit 3 has no effect the R display example above can be selected by either character code 00H or 08H 5 1 for CGRAM data corresponds to display selection and 0 to non selection Indicates no effect V1 2 12 2000 6 13 ST7066 Instructions There are four categories of instructions that Designate ST 7066 functions such as display format data length etc Setinternal RAM addresses Perform data transfer with internal RAM Others Instruction Table Instruction Code Description Instruction DB DB DB DB DB Description Time RS RW 716 5 413121 270KHZ Clear Write 20H DDRAM and set 1 52 ms Display DDRAM address to 00H from AC Set DDRAM address to 00H from AC Return and return cursor to its original position 000000001 X 1 52 ms Home if shifted The contents of DDRAM are not changed Sets cursor move direction and Entry Mode specifies display shift These operations 0 0 0 0 0 0 0 1 U D S 37 Set are performed during data write and read D 1 entire display on Display 0 0 0 0 0 0 1 C t cursor on 37 us ON OFF s B 1 cursor position on Cursor or Set cursor moving and display shift Display 1 5 x x control bit and the direction
19. isplay ON OFF control bit When D High entire display is turned on When D Low display is turned off but display data is remained DDRAM C Cursor ON OFF control bit When C High cursor is turned on When C Low cursor is disappeared in current display but I D register remains its data B Cursor Blink ON OFF control bit When B High cursor blink is on that performs alternate between all the high data and display character at the cursor position When B Low blink is off Cursor or Display Shift RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO EE Without writing or reading of display data shift right left cursor position or display This instruction is used to correct or search display data During 2 line mode display cursor moves to the 2nd line after 40th digit of 1st line Note that display shift is performed simultaneously in all the line When displayed data is shifted repeatedly each line shifted individually When display shift is performed the contents of address counter are not changed S C I Function Set R L Description Shift cursor to the left Shift cursor to the right Shift display to the left Cursor follows the display shift Shift display to the right Cursor follows the display shift RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO ii E ELE ERR ELI RETE Control display cursor blink ON OFF 1 bit register V1 2 AC Value
20. lay data by writing 20H space code to all DDRAM address and set DDRAM address to into AC address counter Return cursor to the original status namely bring the cursor to the left edge on first line of the display Make entry mode increment I D 1 Return Home RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO d Return Home is cursor return home instruction Set DDRAM address to OOH into the address counter Return cursor to its original site and return display to its original status if shifted Contents of DDRAM does not change Entry Mode Set RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 2 ERES Set the moving direction of cursor and display 1 0 Increment decrement of DDRAM address cursor or blink When High cursor blink moves to right and DDRAM address is increased by 1 When Low cursor blink moves to left and DDRAM address is decreased by 1 CGRAM operates the same as DDRAM when read from or write to CGRAM S Shift of entire display When DDRAM read CGRAM read write operation or S Low shift of entire display is not performed If S High and DDRAM write operation shift of entire display is performed according to 1 0 value I D 1 shift left I D 0 shift right V1 2 14 2000 6 13 ST7066 Display ON OFF RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO ER Control display cursor blink ON OFF 1 bit register D D
21. of 5 x 8 dots with cursor 1 11 for one line of 5 x 11 dots amp cursor 1 16 for two lines of 5 x 8 dots amp cursor Wide range of instruction functions Display clear cursor home display on off cursor on off display character blink cursor shift display shift Pinfunction compatibility with HD44780 50066 and SED1278 Automatic reset circuit that initializes the controller driver after power on Internal oscillator with external resistors Low power consumption QFP80 and Bare Chip available 208 5 x 8 dot character fonts and 32 5 x 11 dot character fonts for a total of 240 different character fonts The low power supply 2 7V to 5 5V of the ST7066 is suitable for any portable battery driven product requiring low power dissipation The ST7066 LCD driver consists of 16 common signal drivers and 40 segment signal drivers which can extend display size by cascading segment driver ST7065 or ST7063 The maximum display size can be either 80 characters in 1 line display or 40 characters in 2 line display A single ST7066 can display up to one 8 character line or two 8 character lines Product Name Support Character ST7066 0A English Japan ST7066 0B English European V1 2 2000 6 13 ST7066 Block Diagram Reset Circuit RS MPU Interface RW DB4 to DB7 DBO to DB3 Vcc Register IR Instruction Decoder Data Register
22. used as general data RAM See Figure 1 for the relationships between DDRAM addresses and positions on the liquid crystal display The DDRAM address is set in the address counter AC as hexadecimal 1 line display N 0 Figure 2 When there are fewer than 80 display characters the display begins at the head position For example if using only the ST7066 8 characters are displayed See Figure 3 When the display shift operation is performed the DDRAM address shifts See Figure 3 High Order Low Order bits bits Example DDRAM Address 4F Figure1 DDRAM Address Display Position 78 79 1 2 3 4 5 6 ee el a a d REESE d DDRAM Address Figure 2 1 Line Display Display Position 1 2 3 4 5 6 T 8 d d DDRAM Address xi Shift Left ER D Shift Right Figure3 1 Line by 8 Character Display Example 2 line display 1 Figure 4 Case 1 When the number of display characters is less than 40 x 2 lines the two lines are displayed from the head Note that the first line end address and the second line start address are not consecutive For example when just the 577066 is used 8 characters x 2 lines are displayed See Figure 5 V1 2 7 2000 6 13 ST7066 W hen display shift operation is performed the DDRAM address shifts See Figure 5 Position a DDRAM Display 2 3 4 5 6 38 39 40 7 555
23. without 37 us Shift changing DDRAM data DL interface data is 8 4 bits Function 1 DL I N x NL number of line is 2 1 37 us e F font size is 5x11 5x8 Set Set CGRAM address in address counter CGRAM 0 0 4 37 us 51413 21110 address Set DDRAM age les AC AC Set DDRAM address in address counter us address 65431211 0 Whether during internal operation or not Read Busy be known by reading BF The flag and 0 1 0 us 65431211 0 contents of address counter can also be address read Write data Write data into internal RAM 1 0 071 06 D5 DA D3 D2 D1 DO 43 us to RAM DDRAM CGRAM Read data Read data from internal RAM 1 1 07 06 05 04 03 02 D1 DO 43 us from RAM DDRAM CGRAM Note Be sure the ST7066 is not in the busy state BF 0 before sending an instruction from the MPU to the ST7066 If an instruction is sent without checking the busy flag the time between the first instruction and next instruction will take much longer than the instruction time itself Refer to Instruction Table for the list of each instruction execution time V1 2 13 2000 6 13 ST7066 INSTRUCTION DESCRIPTION Clear Display RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO Clear all the disp
Download Pdf Manuals
Related Search
ST ST7066 Manual