ST M41ST85W 3.0/3.3 V I 2 C combination serial RTC NVRAM supervisor microprocessor supervisor handbook
Contents
1. 21 3 4 Setting alarm clock registers 23 3 5 Watchdog timer 24 3 6 Square wave output 25 3 7 Power on reset sesos RACER 25 3 8 amp RSTIN2 26 3 9 Power fail input output 26 S10 Century DIE 27 cbe em poe 27 3 12 Battery low warning 27 Sao Wee 28 3 14 Initial power on defaults 28 4 Maximum lt 29 5 DC and AC parameters 30 2 43 Doc ID 7531 ky M41ST85W Contents 6 Package mechanical data 34 7 Part numbering 40 8 Environmental information 41 9 Revision history 42 Doc ID 7531 3 43 List of tables M41ST85W List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table2. Description M41ST85W Table 1 Signal names Conditioned chip enable output EX External chip enable IRQ FT OUT Interrupt frequency test out output open drain PFI Power fail input PFO Power fail output RST Reset output open drain RSTIN1 Reset 1 Input RSTIN2 Reset 2 Input SCL Serial clock input SDA Serial data input output SQW Square wave output WDI Watchdog input Voc Supply voltage Vout Voltage output Vss Ground Vpar Battery supply voltage NC No connect NF No function 8 43 1 For 28 pin 300 mil embedded crystal SOIC only Figure 2 28 pin SOIC connections saw 4 28 Vcc NC 12 27 NC 13 26 9 IRQ FT OUT NC C 4 25 NC OJ 5 24 E NC NC C76 23 E NC NC co 7 22 M41ST85W 8 21 CONC RSTIN1 20 E3sCL RSTIN2 19 EX NC NC E 11 18 RST NC E 12 17 PFO D 13 16 CO SDA Vss 14 15 EF ECON 103659 3 Doc ID 7531 Rev 11 M41ST85W Description Figure 3 28 300 mil SOIC connections NF JAO 28 Vcc NF 32 27 NF 26 31RQ FT OUT NF C 4 25 C VOUT NC OO 5 24 1 NC NC 46 23 PFI NC C7 22 C SCL sow ra M41ST85W 21 WDI CJ 9 20 NC RSTIN1 19 ERST RSTIN2 LE 11 18 CI NC PFO C4 12 17 7 SDA NC 13 16 7 Vss CJ 14 15 VBAT AI06370d Note No function NF pins should be tied to Pins 1 2 8 and 4 are internally shorted together Do
3. Table 11 characteristics M41ST85W Sym Parameter Test condition Unit Min Typ Max C Battery current OSC ON TA 25 C Voo 0 V Vaar 3 V 400 500 nA Battery current OSC OFF 50 nA lcc1 Supply current f 400 kHz 0 75 mA 2 Supply current standby 0 50 119 Input leakage current OV lt lt 1 Input leakage current 25 2 25 nA lo Output leakage current OV lt Vin lt 1 current active gt Voc 0 3 V 100 lout2 Vout current battery backup gt 0 3 V 100 Input high voltage 0 7 0 3 V Vy Input low voltage 0 3 0 3Voc V Battery voltage 2 5 3 0 3 56 V Vou Output high voltage 1 0 mA 2 4 Pull up supply voltage open drain RST IRQ FT OUT 3 6 battery backup loura 1 0 pA 2 5 2 9 3 5 V ee Output low voltage Io 3 0 mA 0 4 V Output low voltage open drain lo 10 mA 0 4 V Power fail deselect 2 55 2 60 2 70 V V PFI input threshold 3 V W 1 225 1 250 1 275 V PFI pri hysteresis PFI rising 20 70 mV Vso Battery backup switchover 2 5 V 1 Valid for ambient operating temperature T4 40 85 C Vec 2 7 to 3 6 V except where noted 2 Measured with Vout and Egon open 3 RSTIN1 and RSTIN2 internally pulled up to through 100 resist
4. M41ST85W 3 0 3 3 V combination serial RTC NVRAM supervisor and microprocessor supervisor Features Automatic battery switchover and WRITE protect for Internal serial RTC and External low power SRAM LPSRAM m 400 kHz I C serial interface m 3 0 3 3 V operating voltage 2 710 3 6 V m Ultralow battery supply current of 500 nA max m RoHS compliant Lead free second level interconnect Serial RTC features m 400 kHz 12 W 44 bytes of general purpose NVRAM m Counters for Seconds minutes hours day date month and year Century Tenths hundredths of seconds Clock calibration register allows compensation for crystal variations over temperature m Programmable alarm with repeat modes Functions in battery back up mode Power down timestamp HT bit 2 510 5 5 V oscillator operating voltage Microprocessor supervisor features m Programmable watchdog 62 5 ms to 128 s time out period m Early power fail warning circuit PFI PFO with 1 25 V precision reference October 201 1 SNAPHAT battery amp crystal SOH28 d TUS SOX28 m Power on reset low voltage detect Open drain reset output Reset voltage 2 60 V nom Two reset input pins Watchdog can be steered to reset output NVRAM supervisor features m Non volatizes external LPSRAM Automatically switches to back up battery and de
5. eee pee eee ee es 41 Doc ID 7531 5 43 Description M41ST85W 6 43 Description The M41ST85W is a combination serial real time clock microprocessor supervisor and NVRAM supervisor It is built in a low power CMOS SRAM process and has a 64 byte memory space with 44 bytes of NVRAM and 20 memory mapped registers see Table 2 on page 20 The RTC registers are configured in binary coded decimal BCD format The M41ST85W combines 400 kHz 12 serial RTC with an automatic backup battery switchover circuit for powering an external LPSRAM as well as the internal RTC When power begins to fail the switchover automatically connects to the backup battery to keep the RTC and external LPSRAM alive in the absence of system power Access to the LPSRAM is also cut off via a chip enable gate function thereby write protecting the memory A programmable watchdog and power on reset low voltage detect function are the key elements in the microprocessor supervisor section The real time clock includes a built in 32 768 kHz oscillator crystal controlled which provides the time base for the timekeeping and calendar functions Eight of the 20 clock registers provide the basic clock calendar functions while the other 12 bytes provide status control for the alarm watchdog and squarewave functions RTC addresses and data are transferred serially via the two line bidirectional 2 interface The built in address register is
6. Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Refer also to the STMicroelectronics SURE Program and other relevant quality documents Table 8 Absolute maximum ratings Symbol Parameter Value Unit Teta Storage temperature Voc off oscillator SNAPHAT 40 to 85 off SOIC 55 to 150 5 2 260 C Tsip Lead solder temperature for 10 seconds 28 240 Input or output voltage 0 3 to 0 3 V Voc Supply voltage 0 3 to 4 6 V lo Output current 20 mA Pp Power dissipation 1 W 1 For SOH28 package lead free pb free lead finish reflow at peak temperature of 260 C the time above 255 C must not exceed 30 seconds 2 The SOX28 package has lead free pb free lead finish but cannot be exposed to peak reflow temperature in excess of 240 C Reflow at peak temperature of 240 C the time above 235 C must not exceed 20 seconds Negative undershoots below 0 3 V are not allowed any pin while in the battery backup mode Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets Do
7. Table 15 4 SNAPHAT housing for 48 mAh battery amp crystal mechanical data millimeters inches Symbol Typ Min Max Typ Min Max A 9 78 0 3850 Al 6 73 7 24 0 2650 0 2850 A2 6 48 6 99 0 2551 0 2752 A3 0 38 0 0150 0 46 0 56 0 0181 0 0220 21 21 21 84 0 8350 0 8598 14 22 14 99 0 5598 0 5902 eA 15 55 15 95 0 6122 0 6280 eB 3 20 3 61 0 1260 0 1421 L 2 03 2 29 0 0799 0 0902 Doc ID 7531 Rev 11 35 43 Package mechanical data M41ST85W Figure 23 4 SNAPHAT housing for 120 mAh battery amp crystal package outline A2 A3 y L D eB E SHTK A Note Drawing is not to scale Table 16 4 SNAPHAT housing for 120 mAh battery amp crystal mechanical data millimeters inches Symbol Typ Min Max Typ Min Max A 10 54 0 415 A1 8 00 8 51 0 315 0 335 A2 7 24 8 00 0 285 0 315 A3 0 38 0 015 0 46 0 56 0 018 0 022 21 21 21 84 0 835 0 860 E 17 27 18 03 0 680 0 710 eA 15 55 15 95 0 612 0 628 eB 3 20 3 61 0 126 0 142 L 2 03 2 29 0 080 0 090 36 43 Doc ID 7531 Rev 11 ky M41ST85W Package mechanical data Figure 24 SOX28 28 lead plastic small outline 300 mils embedded crystal package outline SO E ddd h x 45 Note Drawing is not to scale Table 17 SOX28 28 lead plastic small outline 300 mils embedded crystal mechanical data
8. contains the STOP bit ST Setting this bit to a 1 will cause the oscillator to stop If the device is expected to spend a significant amount of time on the shelf the oscillator may be stopped to reduce current drain When reset to 0 the oscillator restarts within one second The eight clock registers may be read one byte at a time or in a sequential block The control register address location 08h may be accessed independently Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read If a clock address is being read an update of the clock registers will be halted This will prevent a transition of data during the READ 3 1 Power down time stamp When a power failure occurs the halt update bit HT will automatically be set to 1 This will prevent the clock from updating the TIMEKEEPER registers and will allow the user to read the exact time of the power down event Resetting the HT bit to 0 will allow the clock to update the TIMEKEEPER registers with the current time For more information see application note AN1572 3 2 TIMEKEEPER registers The M41ST85W offers 20 internal registers which contain clock alarm watchdog flag square wave and control data These registers are memory locations which contain external user accessible and internal copies of the data usually referred to as BiPORT TIMEKEEPER cells The external copies are independen
9. The SNAPHAT battery crystal top is inserted atop the IC package after the completion of the surface mount assembly process which avoids potential battery and crystal damage due to the high temperatures required for device surface mounting The unique design allows the battery to be replaced thus extending the life of the RTC and NVRAM indefinitely The SNAPHAT top is keyed to prevent reverse insertion The SNAPHAT IC and SNAPHAT tops are shipped separately The ICs are available in plastic anti static tubes or in tape amp reel form The SNAPHAT tops are shipped in plastic anti static tubes The part numbers are Doc ID 7531 Rev 11 ky M41ST85W Description M4T28 BR12SH1 48 mAh and M4T32 BR12SH1 120 mAh For the extended temperature requirement the 120 mAh MAT32 BR12SH6 is available For more information see Table 21 on page 40 Caution Do not place the SNAPHAT battery crystal top in conductive foam as this will drain the lithium button cell battery The 300 mil SOX embedded crystal SOIC typically requires a user supplied battery for non volatile operation Capacitor backup can also be implemented with this package Figure 1 Logic diagram 1 Vcc VBAT SCL E SDA e RST EX e IRQ FT OUT RSTIN1 M41ST85W SQW RSTIN2 Q _ PFO WDI VOUT PFI Vss 103658 1 28 pin 300 mil embedded crystal SOIC only ky Doc ID 7531 Rev 11 7 43
10. 22 4 43 Signal names Dua Perea bed OP Redon eee 8 TIMEKEEPER register 20 Alarm repeat 0 1 23 Square wave output 25 Reset AC characteristics 26 eL 28 Default values iue ee e E 28 Absolute maximum 05 1 1 0 29 DC and AC measurement 30 Capacitance 1 7 4 30 DC characteristics ge cx ea egg ex ER RR Roe e E eed 31 AC 32 Power down up AC 33 28 28 lead plastic small outline battery SNAPHAT package mechanical data 34 4 pin housing for 48 mAh battery amp crystal mechanical data 35 4 pin SNAPHAT housing for 120 mAh battery amp crystal mechanical data 36 SOX28 28 lead plastic small outline 300 mils embedded crystal mechanical data 37 Carrier tape dimensions for SOH28 and SOX28 pac
11. Alarm 10 minutes Alarm minutes Al min 00 59 1 Alarm 10 seconds Alarm seconds Al sec 00 59 OFh WDF AF 0 BL 0 0 0 0 Flags 10h 0 0 0 0 0 Reserved 11h 0 0 0 0 0 Reserved 12h 0 0 0 0 0 Reserved 13h RS3 RS2 RS1 RSO 0 0 0 0 SQW Keys 5 Sign bit RBO RB1 Watchdog resolution bits FT Frequency test bit WDS Watchdog steering bit ST Stop bit ABE Alarm in battery backup mode enable bit 0 Must be set to zero RPT1 RPT5 Alarm repeat mode bits BL Battery low flag read only WDF Watchdog flag read only BMBO BMB4 Watchdog multiplier bits CEB Century enable bit CB Century bit OUT Output level AF Alarm flag read only SQWE Square wave enable RSO RS3 SQW frequency HT Halt update bit AFE Alarm flag enable flag TR trec bit 3 20 43 Doc ID 7531 Rev 11 M41ST85W Clock operation 3 3 Calibrating the clock The M41ST85W is driven by a quartz controlled oscillator with a nominal frequency of 32 768 Hz The devices are tested not exceed 35 ppm parts per million oscillator frequency error at 259C which equates to about 1 53 minutes per month When the Calibration circuit is properly employed accuracy improves to better than x2 ppm at 25 C The oscillation rate of crystals changes with temperature see Figure 13 on page 22 Therefore the M41ST85W design employs periodic counter correction The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divi
12. a nominal value write protection continues for trec by inhibiting Econ The RST signal also remains active during this time see Figure 20 on page 33 Note Most low power SRAMs on the market today can be used with the M41ST85W RTC SUPERVISOR There are however some criteria which should be used in making the final choice of an SRAM to use The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM This allows inputs to the M41ST85W and SRAMs to be Don t Care once Vcc falls below Vpep min The SRAM should also guarantee data retention down to Voc 2 0 volts The chip enable access time must be sufficient to meet the system needs with the chip enable output propagation delays included If the SRAM includes a second chip enable pin E2 this pin should be tied to Vour ki Doc ID 7531 Rev 11 17 43 Operating modes M41ST85W 18 43 If data retention lifetime is a critical parameter for the system it is important to review the data retention current specifications for the particular SRAMs being evaluated Most SRAMs specify a data retention current at 3 0 volts Manufacturers generally specify a typical condition for room temperature along with a worst case condition generally at elevated temperatures The system level requirements will determine the choice of which value to use The data retention current value of the SRAMs can then be added to the Igar value of the M41ST85W to determine
13. incremented automatically after each WRITE or READ data byte The M41ST85W has built in power sense circuit which detects power failures and automatically switches to the backup battery when a power failure occurs During an outage the power to sustain the SRAM and clock operations is typically supplied by a small lithium button cell battery as is the case when using the SNAPHAT package option Functions available to the user include a non volatile time of day clock calendar alarm interrupts watchdog timer and programmable squarewave generator Other features include a power on reset as well as two additional debounce reset inputs RSTIN1 and RSTIN2 which can also generate an output reset RST The eight registers for basic clock calendar functions contain the century year month date day hour minute second and tenths hundredths of a second in 24 hour BCD format Corrections for 28 29 leap year valid until year 2100 30 and 31 day months are made automatically The M41ST85W is offered in two 28 lead SOIC packages The 300 mil SOH28 SNAPHAT IC package mates with ST s SNAPHAT battery crystal top ordered separately SNAPHAT battery options include 48 mAh and 120 mAh ST s 300 mil SOX28 embedded crystal IC includes the 32 KHz crystal and is perfect for applications where a low profile is a must The SOH28 SNAPHAT SOIC includes sockets with gold plated contacts at both ends for direct connection to the SNAPHAT top
14. location R W START i SLAVE ADDRESS n im H 1 e gt M 100602 Doc ID 7531 Rev 11 15 43 Operating modes M41ST85W Figure 10 Read mode sequence oc tc BUS ACTIVITY lt o n WORD _ SDA LINE ADDRESS An DATA n 1 BUS ACTIVITY ic s 5 gt lt lt lt lt lt SLAVE 1 SLAVE ADDRESS ADDRESS Lr 90 DATAmX 100899 lt 2 Figure 11 Alternate read mode sequence tr n BUS ACTIVITY 9 SDA LINE DATA n 1 DATA n X BUS ACTIVITY as 5 lt lt lt lt lt i 9 SLAVE 2 ADDRESS 100895 16 43 Doc ID 7531 Rev 11 3 M41ST85W Operating modes 2 3 Write mode In this mode the master transmitter transmits to the M41ST85W slave receiver Bus protocol is shown in Figure 12 Following the START condition and slave address a logic 0 R W 0 is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on chip address pointer The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the RAM on the reception of an acknowledge clock The M41ST85W slave receiver will send an acknowledge clock to the master transmitter after it has received t
15. set If AFE alarm flag enable is also set the alarm condition activates the IRQ FT OUT pin as shown in Figure 15 To disable alarm write 0 to the alarm date register and to RPT5 RPT1 If the address pointer is allowed to increment to the flag register address an alarm condition will not cause the interrupt flag to occur until the address pointer is moved to a different adaress It should also be noted that if the last address written is the Alarm Seconds the adaress pointer will increment to the flag address causing this situation to occur The IRQ FT OUT output is cleared by a READ to the flags register A subsequent READ of the flags register is necessary to see that the value of the alarm flag has been reset to 0 The IRQ FT OUT pin can also be activated in the battery backup mode The IRQ FT OUT will go low if an alarm occurs and both ABE alarm in battery backup mode enable and AFE are set The ABE and AFE bits are reset during power up therefore an alarm generated during power up will only set AF The user can read the flag register at system boot up to determine if an alarm was generated while the M41ST85W was in the deselect mode during power up Figure 16 on page 24 illustrates the backup mode alarm timing Alarm interrupt reset waveform Table 3 ACTIVE FLAG IRQ FT OUT 103664 Alarm repeat modes RPT5 RPT4 RPT3 RPT2 RPT1 Alarm setting Once per second a Once per minute Once per
16. 1 Reel dimensions for 24 mm carrier tape SOH28 and SOX28 packages Table 19 Carrier t A arrier tape p max 24 mm 330 mm SOH28 SOX28 13 inch B min 1 5 mm c D min 13 mm 0 2 mm Ao Emm N min 60 mm G 24 4 mm 2 0 mm Note parameters 3 Doc ID 7531 Rev 11 The dimensions given in Table 19 incorporate tolerances that cover all variations on critical 39 43 Part numbering M41ST85W 7 Part numbering Table 20 Ordering information scheme Example M41ST 85W MH 6 E Device type M41ST Supply voltage and write protect voltage 85W Vec 2 7 to 3 6 V 2 55V lt Vppp 2 70 V Package SOH28 MX SOX28 Temperature range 6 40 to 85 C Shipping method For SOH28 ECOPACK package tubes F ECOPACK package tape amp reel For SOX28 Blank ECOPACK package tubes 9 TR ECOPACK package tape amp reel 1 The 28 pin SOIC package SOH28 requires the SNAPHAT battery crystal package which is ordered separately under the part number M4TXX BR12SHx in plastic tube see Table 27 2 The SOX28 package includes an embedded 32 768 Hz crystal 3 Not recommended for new design Contact local ST sales office for availability Caution Do not place the SNAPHAT battery package 4 125 in conductive foam as it will drain the lithium button cell battery For
17. aining how much calibration a given M41ST85W may require The first involves setting the clock letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time Calibration values including the number of seconds lost or gained in a given period can be found in application note AN934 TIMEKEEPER calibration This allows the designer to give the end user the ability to calibrate the clock as the environment requires even if the final product is packaged in a non user serviceable enclosure The designer could provide a simple utility that accesses the calibration byte The second approach is better suited to a manufacturing environment and involves the use of the IRQ FT OUT pin The pin will toggle at 512 Hz when the stop bit ST D7 of 01h is 0 the frequency test bit FT D6 of 08h is 1 the alarm flag enable bit AFE D7 of OAh is 0 and the watchdog steering bit WDS D7 of 09h is 1 or the watchdog register 09h 0 is reset Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature For example a reading of 512 010124 Hz would indicate a 20 ppm oscillator frequency error requiring a 10 XX001010 to be loaded into the calibration byte for correction Note that setting or changing the calibration byte does not affect the frequency test output frequency The IRQ FT OUT pin is an open drain output which requir
18. ally performs battery voltage monitoring upon power up and at factory programmed time intervals of approximately 24 hours The battery low BL bit bit D4 of flags register OFh will be asserted if the battery voltage is found to be less than approximately 2 5 V The BL bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests either during the next power up sequence or the next scheduled 24 hour interval If a battery low is generated during a power up sequence this indicates that the battery is below approximately 2 5 volts and may not be able to maintain data integrity in the SRAM Data should be considered suspect and verified as correct A fresh battery should be installed If a battery low indication is generated during the 24 hour interval check this indicates that the battery is near end of life However data is not compromised due to the fact that a nominal Vcc is supplied In order to insure data integrity during subsequent periods of battery backup mode the battery should be replaced The SNAPHAT top may be replaced while Vcc is applied to the device This will cause the clock to lose time during the interval the SNAPHAT battery crystal top is disconnected The M41ST85W only monitors the battery when a nominal Vcc is applied to the device Thus applications which require extensive durations in the battery backup mode should be powered up periodically at least once every few month
19. c ID 7531 Rev 11 29 43 DC and parameters M41ST85W 5 DC and AC parameters This section summarizes the operating and measurement conditions as well as the DC and AC characteristics of the device The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters Table 9 DC and AC measurement conditions Parameter M41ST85W Voc supply voltage 2 7 to 3 6 V Ambient operating temperature 40 to 85 C Load capacitance C 50 pF Input rise and fall times lt 50 ns Input pulse voltages 0 2 to 0 8Vcc Input and output timing ref voltages 0 3 to 0 7Vcc Note Output High Z is defined as the point where data is no longer driven Figure 18 testing input output waveforms 0 8Vcc 0 2Vcc 102568 Table 10 Capacitance Symbol Parameter 2 Min Max Unit Cin Input capacitance 7 pF Cour Output capacitance 10 pF tip Low pass filter input time constant SDA and SCL 50 ns 1 Effective capacitance measured with power supply at 5 V Sampled only not 100 tested 2 At 25 C f 1 MHz 3 Outputs are deselected 30 43 Doc ID 7531 Rev 11 ki M41ST85W DC and AC parameters
20. c ID 7531 Rev 11 9 43 Description M41ST85W Figure 4 Block diagram REAL TIME CLOCK CALENDAR 44 BYTES USER RAM RTC w ALARM amp CALIBRATION WATCHDOG SDA 2 gt iRQ FT OUT Crystal SQUARE WAVE SQW WDI VOUT RSTIN1 RSTIN2 EX PFI COMPARE PFO 1 25V Internal A103932 1 Open drain output 2 Crystal integrated into SOIC package for MX package option 10 43 Doc ID 7531 Rev 11 M41ST85W Description Figure 5 Hardware hookup Regulator M41ST85W Unregulated Voltage VOUT ECON LPSRAM From MCU RSTIN1 RST To RST RSTIN2 SQW To LED Display Pushbutton Reset PFO To NMI PFI 1 IRO FT OUT To INT AT 103660 1 Required for embedded crystal MX package only Doc ID 7531 Rev 11 11 43 Operating modes M41ST85W 2 2 1 12 43 Operating modes The M41ST85W clock operates as a slave device on the serial bus Access is obtained by implementing a start condition followed by the correct slave address DOh The 64 bytes contained in the device can then be accessed sequentially in the following order Tenths hundredths of a second register Seconds register Minutes register Century hours register Day register Date register Month register Year register Control register 10 Watchdog register ON oA F WON 11 16 Ala
21. de by 256 stage as shown in Figure 14 on page 22 The number of times pulses which are blanked subtracted negative calibration or split added positive calibration depends upon the value loaded into the five calibration bits found in the control register Adding counts speeds the clock up subtracting counts slows the clock down The calibration bits occupy the five lower order bits D4 DO in the control register 08h These bits can be set to represent any value between 0 and 31 in binary form Bit D5 is a sign bit 1 indicates positive calibration indicates negative calibration Calibration occurs within a 64 minute cycle The first 62 minutes in the cycle may once per minute have one second either shortened by 128 or lengthened by 256 oscillator cycles If a binary 1 is loaded into the register only the first 2 minutes in the 64 minute cycle will be modified if a binary 6 is loaded the first 12 will be affected and so on Therefore each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125 829 120 actual oscillator cycles that is 4 068 or 2 034 ppm of adjustment per calibration step in the calibration register Assuming that the oscillator is running at exactly 32 768 Hz each of the 31 increments in the calibration byte would represent 10 7 or 5 35 seconds per month which corresponds to a total range of 5 5 or 2 75 minutes per month Two methods are available for ascert
22. e added to Setting Alarm Clock Registers section added temp voltage info to tables Table 10 11 6 12 13 addition of default values Table 7 22 Jun 2001 2 2 Note added to clock operation section 26 Jul 2001 3 Change in product maturity 07 Aug 2001 3 1 Improve text in Setting the Alarm Clock section 20 Aug 2001 3 2 Change Vpry values in document 06 Sep 2001 33 DC characteristics Vgar changed changed PFI hysteresis Rising spec added and crystal electrical characteristics table removed Table 11 6 03 Dec 2001 34 Changed READ WRITE mode sequences Figure 10 12 change in Vpgp lower limit for 5V M41ST85Y part only Table 11 20 01 May 2002 3 5 Change trec definition Table 6 modify reflow time and temperature footnote Table 8 03 Jul 2002 3 6 Modify DC characteristics table footnote default values Table 11 7 15 Nov 2002 37 Added embedded crystal MX package option corrected initial power up condition cover page Figure 1 3 4 5 24 Table 1 7 20 24 Jan 2003 3 8 Update diagrams Figure 4 5 24 update values Table 13 5 6 7 25 Feb20 03 4 New Si changes Table 13 5 6 corrected dimensions Figure 24 Table Reformatted correct dimensions update Lead free information Figure 20 13 16 20 May2004 5 Table 8 16 20 15 Jun 2004 Update characteristics add package shipping Figure 3 Table 1 11 20 13 Sep 2004 Update maximum ratings Table 8 Updated template Lead free te
23. e square wave function which is output on the SQW pin RS3 RSO bits located in 13h establish the square wave output frequency These frequencies are listed in Table 4 Once the selection of the SQW frequency has been completed the SQW pin can be turned on and off under software control with the square wave enable bit SQWE located in register OAh Table 4 Square wave output frequency Square wave bits Square wave RS3 RS2 RS1 RSO Frequency Units 0 0 0 0 None 0 0 0 1 32 768 kHz 0 0 1 0 8 192 kHz 0 0 1 1 4 096 kHz 0 1 0 0 2 048 kHz 0 1 0 1 1 024 kHz 0 1 1 0 512 Hz 0 1 1 1 256 Hz 1 0 0 0 128 Hz 1 0 0 1 64 Hz 1 0 1 0 32 Hz 1 0 1 1 16 Hz 1 1 0 0 8 Hz 1 1 0 1 4 Hz 1 1 1 0 2 Hz 1 1 1 1 1 Hz 3 7 Power on reset The M41ST85W continuously monitors Voc When Vec falls to the power fail detect trip point the RST pulls low open drain and remains low on power up for trec after Vog passes Vpep max The RST is an open drain output and an appropriate pull up resistor should be chosen to control rise time ky Doc ID 7531 Rev 11 25 43 Clock operation M41ST85W 3 8 Reset inputs RSTIN1 amp RSTIN2 The M41ST85W provides two independent inputs which can generate an output reset The duration and function of these resets is identical to a reset generated by a power cycle Table 5 and Figure 17 illustrate the AC reset characteristics of this function Pulses sho
24. es a pull up resistor to for proper operation A 500 to 10 k resistor is recommended in order to control the rise time The FT bit is cleared on power down ky Doc ID 7531 Rev 11 21 43 Clock operation M41ST85W Figure 13 Crystal accuracy across temperature Frequency ppm AF Kx T Tof 0 036 ppm C 0 006 ppm C 25 5 30 20 10 0 10 20 30 40 50 60 70 80 Temperature 107888 Figure 14 Calibration waveform 22 43 NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION x gt _ L Lo T LOTIT L 100594 Doc ID 7531 Rev 11 M41ST85W Clock operation 3 4 Note Figure 15 Setting alarm clock registers Address locations OAh OEh contain the alarm settings The alarm can be configured to go off at a prescribed time on a specific month date hour minute or second or repeat every year month day hour minute or second It can also be programmed to go off while the M41ST85W is in the battery backup to serve as a system wake up call Bits RPT5 RPT 1 put the alarm in the repeat mode of operation Table 3 shows the possible configurations Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting When the clock information matches the alarm clock settings based on the match criteria defined by 5 1 the AF alarm flag is
25. fter setting the slave address see Figure 9 Following the WRITE mode control bit R W 0 and the acknowledge bit the word address is written to the on chip address pointer Next the START condition and slave address are repeated followed by the READ mode control bit R W 1 At this point the master transmitter becomes the master receiver The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter see Figure 10 on page 16 The address pointer is only incremented on reception of an acknowledge clock The M41ST85W slave transmitter will now place the data byte at address An 1 on the bus the master receiver reads and acknowledges the new byte and the address pointer is incremented to An 2 This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter The system to user transfer of clock data will be halted whenever the address being read is a clock address 00h to 07h The update will resume either due to a stop condition or when the pointer increments to a non clock or RAM address This is true both in READ mode and WRITE mode An alternate READ mode may also be implemented whereby the master reads the M41ST85W slave without first writing to the volatile address pointer The first address that is read is the last one stored in the pointer see Figure 11 on page 16 Figure 9 Slave address
26. he slave address and again after it has received the word address and each data byte Figure 12 Write mode sequence tr a BUS ACTIVITY o c o WORD SDA LINE ADDRESS An DATAn DATA n 1 DATA n X 5 USAC lt lt lt lt lt SLAVE ADDRESS 100591 2 4 Data retention mode With valid Vcc applied the M41ST85W can be accessed as described above with READ or WRITE cycles Should the supply voltage decay the M41ST85W will automatically deselect write protecting itself and any external SRAM when Vcc falls between Vpep max and Vprp min This is accomplished by internally inhibiting access to the clock registers At this time the reset pin RST is driven active and will remain active until returns to nominal levels External RAM access is inhibited in a similar manner by forcing Econ to a high level This level is within 0 2 volts of the Econ will remain at this level as long as Voc remains at an out of tolerance condition When falls below the battery backup switchover voltage Vso power input is switched from the Vcc pin to the SNAPHAT battery and the clock registers and external SRAM are maintained from the attached battery supply All outputs become high impedance The is capable of supplying 100 pA of current to the attached memory with less than 0 3 volts drop under this condition On power up when returns to
27. hour Once per month Once per day o a Once per year o o Doc ID 7531 Rev 11 23 43 Clock operation M41ST85W Figure 16 Backup mode alarm waveform ABE AFE Bits in Interrupt Register AF bit Flags Register IRQ FT OUT lt HIGH Z 4 HIGH Z gt 103920 3 5 Note Note 24 43 Watchdog timer The watchdog timer can be used to detect an out of control microprocessor The user programs the watchdog timer by setting the desired amount of time out into the watchdog register address 09h Bits 4 store a binary multiplier and the two lower order bits RB1 RBO select the resolution where 00 1 16 second 01 1 4 second 10 1 second and 11 4 seconds The amount of time out is then determined to be the multiplication of the five bit multiplier value with the resolution For example writing 00001110 in the watchdog register 3 1 or 3 seconds The accuracy of the timer is within the selected resolution If the processor does not reset the timer within the specified period the M41ST85W sets the WDF watchdog flag and generates a watchdog interrupt or a microprocessor reset The most significant bit of the watchdog register is the watchdog steering bit WDS When set to a 0 the watchdog will activate the IRQ FT OUT pin when timed out When WDS
28. in to Vss fall time of less than teg may cause corruption of RAM data Programmable see Table 6 on page 28 Doc ID 7531 Rev 11 33 43 Package mechanical data M41ST85W 6 Package mechanical data In order to meet environmental requirements ST offers these devices in different grades of packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com is an ST trademark Figure 21 SOH28 28 lead plastic small outline battery SNAPHAT package outline A2 A C Note Drawing is not to scale Table 14 50 28 28 lead plastic small outline battery SNAPHAT package mechanical data millimeters inches Symbol Typ Min Max Typ Min Max A 3 05 0 120 A1 0 05 0 36 0 002 0 014 A2 2 34 2 69 0 092 0 106 B 0 36 0 51 0 014 0 020 0 15 0 32 0 006 0 012 D 17 71 18 49 0 697 0 728 8 23 8 89 0 324 0 350 e 1 27 0 050 3 20 3 61 0 126 0 142 H 11 51 12 70 0 453 0 500 0 41 1 27 0 016 0 050 0 8 0 8 N 28 28 CP 0 10 0 004 34 43 Doc ID 7531 Rev 11 ky M41ST85W Package mechanical data Figure 22 4 pin SNAPHAT housing for 48 mAh battery amp crystal package outline eB SHTK A Drawing is not to scale Note
29. in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2011 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 7531 43 43
30. is set to 1 the watchdog will output a negative pulse on the RST pin for teo The watchdog register FT AFE ABE and SQWE bits will reset to a 0 at the end of a watchdog time out when the WDS bit is set to a 1 The watchdog timer can be reset by two methods 1 a transition high to low or low to high can be applied to the watchdog input pin WDI or 2 the microprocessor can perform a WRITE of the watchdog register The time out period then starts over WDI pin should be tied if not used In order to perform a software reset of the watchdog timer the original time out period can be written into the watchdog register effectively restarting the count down cycle Should the watchdog timer time out and the WDS bit is programmed to output an interrupt a value of 00h needs to be written to the watchdog register in order to clear the IRQ FT OUT Doc ID 7531 Rev 11 ky M41ST85W Clock operation pin This will also disable the watchdog function until it is again programmed correctly A READ of the flags register will reset the watchdog flag bit D7 register OFh The watchdog function is automatically disabled upon power up and the watchdog register is cleared If the watchdog function is set to output to the IRQ FT OUT pin and the frequency test function is activated the watchdog function prevails and the frequency test function is denied 3 6 Square wave output The M41ST85W offers the user a programmabl
31. kages 38 Reel dimensions for 24 mm carrier tape SOH28 SOX28 packages 39 Ordering information 40 SNAPHAT battery crystal 2 2 40 Document revision history 42 Doc ID 7531 M41ST85W List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Logic nune queen Rie De eda eden Res bodas Dede AR Rc 7 28 pin SOIC connections 8 28 pin 300 mil SOIC connections 9 MERE 10 Hardware 11 Serial bus data transfer sequence 14 Acknowledgement sequence 14 Write cycle timing RTC amp external SRAM control signals 14 Slave address location 4 15 Read
32. lock pulse A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge related clock pulse Of course setup and hold times must be taken into account A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave In this case the transmitter must leave the data line high to enable the master to generate the STOP condition Doc ID 7531 Rev 11 13 43 Operating modes M41ST85W Figure 6 Serial bus data transfer sequence DATA LINE STABLE DATA VALID CLOCK WE mr rdum c XE NE D START CHANGE OF STOP CONDITION DATA ALLOWED CONDITION 100587 Figure 7 Acknowledgement sequence CLOCK PULSE FOR START ACKNOWLEDGEMENT SCL FROM MASTER 7 BY TRANSMIT 7 OUTPUT OOOO BY RECEIVER 100601 Figure 8 Write cycle timing RTC amp external SRAM control signals tEXPD tEXPD ECON 103663 14 43 Doc ID 7531 Rev 11 M41ST85W Operating modes 2 2 Note Read mode In this mode the master reads the M41ST85W slave a
33. millimeters inches Symbol Typ Min Max Typ Min Max A 2 44 2 69 0 096 0 106 A1 0 15 0 31 0 006 0 012 A2 2 29 2 39 0 090 0 094 B 0 41 0 51 0 016 0 020 0 20 0 31 0 008 0 012 D 17 91 18 01 0 705 0 709 ddd 0 10 0 004 E 7 57 7 67 0 298 0 302 e 1 27 0 050 H 10 16 10 52 0 400 0 414 L 0 51 0 81 0 020 0 032 a 0 8 0 8 28 28 2 Doc ID 7531 Rev 11 Package mechanical data M41ST85W Figure 25 Carrier tape for SOH28 and SOX28 package T TOP COVER TAPE CENTER LINES Pi Kk OF CAVITY ee o o A4 USER DIRECTION OF FEED AMO03073v1 Table 18 Carrier tape dimensions for SOH28 and SOX28 packages 4 Bulk Package Ww D E Po P2 F Ao Bo Ko Unit Qty 24 00 150 175 400 200 11 50 12 90 18 70 3 20 16 00 0 30 SORS i 0 10 0 10 30 10 0 10 3010 0 10 0 10 0 10 20 05 996 24 00 150 175 400 200 11 50 12 70 18 20 320 16 00 0 30 2 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 05 1000 38 43 Doc ID 7531 Rev 11 ky M41ST85W Package mechanical data Figure 26 Reel schematic Full radius 40mm min Access hole At slot location Tape slot In core for Tape start 2 5mm min width G measured At hub AM04928v
34. mode 1 16 Alternate read mode lt 16 Write mode 17 Crystal accuracy across 22 Calibration waveform 22 Alarm interrupt reset 23 Backup mode alarm 24 RSTIN1 amp RSTIN2 timing 1 26 AC testing input output 30 Bus timing requirements sequence 32 Power down up mode AC 33 28 28 lead plastic small outline battery SNAPHAT package outline 34 4 pin SNAPHAT housing for 48 mAh battery amp crystal package outline 35 4 pin SNAPHAT housing for 120 mAh battery amp crystal package outline 36 SOX28 28 lead plastic small outline 300 mils embedded crystal package outline 37 Carrier tape for SOH28 SOX28 package 38 Reel cee pee beds eben 39 Recycling symbols
35. nt refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend
36. or WDI internally pulled down to Vgg through 100 resistor gt Outputs deselected will reduce battery life External SRAM must match RTC supervisor chip Vcc specification For rechargeable backup max be considered Voc For PFO and SQW pins CMOS Conditioned output Econ can only sustain CMOS leakage current in the battery backup mode Higher leakage currents 9 For IRQ FT OUT RST pins open drain if pulled up to supply other than this supply must be equal to or less than 3 0 V when Vcc 0 V during battery backup mode Doc ID 7531 Rev 11 31 43 DC and AC parameters M41ST85W Figure 19 Bus timing requirements sequence f BUF tHD STA tHD STA tSU DAT H T1SU STA tSU STO E S SR d 100589 Table 12 characteristics Symbol Parameter Min Max Unit SCL clock frequency 0 400 kHz tBur Time the bus must be free before a new transmission can start 1 3 us texpp EX to Econ propagation delay 15 ns tF SDA and SCL fall time 300 ns 2 Data hold time 0 us tup sta START condition hold time after this period the first clock pulse is generated 600 ns tHIGH Clock high period 600 ns Clock low period 1 3 us SDA and SCL rise time 300 ns tsu pat Data setup time 100 ns tsu sta START condition setup time only
37. other options or for more information on any aspect of this device please contact the ST sales office nearest you Table 21 SNAPHAT battery crystal table Part number Description Package eae O M4T28 BR12SH Lithium battery 48 mAh and crystal SNAPHAT top SH M4T32 BR12SH Lithium battery 120 mAh and crystal SNAPHAT top SH 40 43 Doc ID 7531 Rev 11 M41ST85W Environmental information 8 Environmental information Figure 27 Recycling symbols This product contains a non rechargeable lithium lithium carbon monofluoride chemistry button cell battery fully encapsulated in the final product Recycle or dispose of batteries in accordance with the battery manufacturer s instructions and local national disposal and recycling regulations Doc ID 7531 Rev 11 41 43 Revision history M41ST85W 9 Revision history Table 22 Document revision history Date Revision Changes Aug 2000 1 First issue 24 Aug 2000 1 1 Block diagram added Figure 4 12 Oct 2000 1 2 trec table removed cross references corrected 18 Dec 2000 2 Reformatted TOC added and PFI input leakage current added Table 1 1 Addition of information table changed one added Table 2 6 changed PFI PFO graphic see Figure 4 change to DC and AC characteristics order information 18 Jun 2001 2 1 Table 11 12 20 not
38. ral milliseconds before the regulated Vcc input to the M41ST85W or the microprocessor drops below the minimum operating voltage During battery backup the power fail comparator turns off and PFO goes or remains low This occurs after drops below Vpep min When power returns PFO is forced high irrespective of for the write protect time which is the time from Vpgp max until the inputs are recognized At the end of this time the power fail comparator is enabled and PFO 26 43 Doc ID 7531 Rev 11 M41ST85W Clock operation 3 10 3 11 Note 3 12 Note follows PFI If the comparator is unused should be connected to Vas and PFO left unconnected Century bit Bits D7 and D6 of clock register O3h contain the Century Enable bit CEB and the Century bit CB Setting CEB to 1 will cause CB to toggle either from a 0 to 1 or from 1 to 0 at the turn of the century depending upon its initial state If CEB is set to a 0 CB will not toggle Output driver pin When the FT bit AFE bit and watchdog register are not set the IRQ FT OUT pin becomes an output driver that reflects the contents of D7 of the control register In other words when D7 OUT bit and 06 FT bit of address location 08h are 0 then the IRQ FT OUT pin will be driven low The IRQ FT OUT pin is an open drain which requires an external pull up resistor Battery low warning The M41ST85W automatic
39. relevant for a repeated start condition 600 ns tsu sto STOP condition setup time 600 ns 1 Valid for ambient operating temperature 40 to 85 C Vcc 2 7 to 3 6 V except where otherwise noted 2 Transmitter must internally provide a hold time to bridge the undefined region 300 ns max of the falling edge of SCL 32 43 Doc ID 7531 Rev 11 M41ST85W DC and AC parameters Figure 20 Power down up mode AC waveforms Vcc MPEDAmax s a a 8 ene tDR PFO INPUTS DON T CARE RECOGNIZED RST HIGH Z PER CONTROL INPUT PER CONTROL INPUT ECON 103661 Table 13 Power down up characteristics Symbol Parameter Min Typ Max Unit p Vpep max to Vpep min Vec fall time 300 us ten Vpep min to Vss Vec fall time 10 us tpp EX at before power down 0 us to PFO propagation delay 15 25 us Vprp min to Vec rise time 10 Hs tre Vss to Vppp min Vcc rise time 1 Hs trec Power up deselect time 40 200 ms 1 Valid for ambient operating temperature T4 40 to 85 C Vcc 2 7 to 3 6 V except where otherwise noted 2 Vpep max to Vpep min fall time of less than may result in deselection write protection not occurring until 200 us after passes Vprp min Vprp m
40. rm registers 17 19 Reserved 20 Square wave register 21 64 User RAM The M41ST85W clock continually monitors for an out of tolerance condition Should Vcc fall below Vprp the device terminates an access in progress and resets the device address counter Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out of tolerance system When falls below Vgo the device automatically switches over to the battery and powers down into an ultralow current mode of operation to conserve battery life As system power returns and Voc rises above Vgo the battery is disconnected and the power supply is switched to external Vcc Write protection continues until Voc reaches Vprp min plus trec For more information on battery storage life refer to application note AN1012 2 wire bus characteristics The bus is intended for communication between different ICs It consists of two lines a bi directional data signal SDA and a clock signal SCL Both the SDA and SCL lines must be connected to a positive supply voltage via a pull up resistor The following protocol has been defined e Data transfer be initiated only when the bus is not busy e During data transfer the data line must remain stable whenever the clock line is high e Changesin the data line while the clock line is high will be interpreted as control signals Doc ID 7531 Rev 11 k
41. rter than and gu will not generate a reset condition RSTIN1 and RSTIN2 are each internally pulled up to through a 100 resistor Figure 17 RSTIN1 amp RSTIN2 timing waveforms RSTIN1 tRLRH1 RSTIN2 RST 103665 Note With pull up resistor Table 5 Reset AC characteristics Symbol Parameter Min Max Unit RSTIN1 low to RSTIN1 high 200 ns 9 RSTIN2 low to RSTIN2 high 100 ms 1 I RSTIN1 high to RST high 40 200 ms tRoHRH I RSTIN2 high to RST high 40 200 ms 1 Valid for ambient operating temperature T4 40 to 85 C Vcc 2 7 to 3 6 V except where noted 2 Pulse width less than 50 ns will result in no RESET for noise immunity 3 Pulse width less than 20 ms will result in no RESET for noise immunity 4 Programmable see Table 6 on page 26 3 9 Power fail input output The power fail input PFI is compared to an internal reference voltage 1 25 V If PFI is less than the power fail threshold the power fail output PFO will go low This function is intended for use as an undervoltage detector to signal a failing power supply Typically PFI is connected through an external voltage divider see Figure 5 on page 11 to either the unregulated DC input if it is available or the regulated output of the Vcc regulator The voltage divider can be set up such that the voltage at falls below seve
42. s in order for this technique to be beneficial Additionally if a battery low is indicated data integrity should be verified upon power up via a checksum or other technique Doc ID 7531 Rev 11 27 43 Clock operation M41ST85W Bit D7 of clock register 04h contains the t ec bit TR refers to the automatic continuation of the deselect time after Vcc reaches Vprp This allows for a voltage settling time before WRITEs may again be performed to the device after a power down condition The bit will allow the user to set the length of this deselect time as defined by Table 6 3 14 Initial power on defaults Upon initial application of power to the device the following register bits are set to 0 state watchdog register FT AFE ABE SQWE and TR The following bits are set to 1 state ST OUT and HT see Table 7 Table 6 trec definitions trec time trec bit TR STOP bit ST Units Min Max 0 96 98 ms 1 40 2000 ms X 50 2000 Us 1 Default setting Table 7 Default values Condition ST HT FT sawe Watchdoy register Initial power up 0 1 1 1 0 0 0 0 0 Subsequent power up with battery backup 9 de Seta ee ng d 9 1 WDS BMBO BMB4 RBO 1 2 State of other control bits undefined 3 Unchanged 28 43 Doc ID 7531 Rev 11 97 M41ST85W Maximum ratings 4 Caution Caution 4
43. selects write protects external LPSRAM via chip enable gate Power fail deselect write protect voltage 2 60 V nom Switchover 2 50 V Battery monitor battery low flag Other features Programmable squarewave generator 1 Hz to 32 KHz m 40 C to 85 C operation Package options 28 lead SNAPHAT IC SOH28 SNAPHAT battery crystal top to be ordered separately 28 lead embedded crystal SOIC SOX28 Doc ID 7531 Rev 11 1 43 www st com Contents M41ST85W Contents 1 Description M 6 2 Operating 12 2 1 2 wire bus characteristics 12 2 1 1 Bus not bUSY 5 ee 13 2 1 2 Start data transfer 13 2 1 3 Stop data transfer 13 2 1 4 Data valid bee Ree Re 13 2 1 5 Acknowledge 13 2 2 Head Mode 15 2 3 Write MOE EH 17 2 4 Data retention 17 3 Clock operation 19 3 1 Power down 1 19 3 2 registers 19 3 3 1
44. t of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy The internal divider or clock chain will be reset upon the completion of a WRITE to any clock address The system to user transfer of clock data will be halted whenever the address being read is a clock address 00h to 07h The update will resume either due to a stop condition or when the pointer increments to a non clock or RAM address TIMEKEEPER and alarm registers store data in BCD control watchdog and square wave registers store data in binary format ki Doc ID 7531 Rev 11 19 43 Clock operation M41ST85W Table 2 TIMEKEEPER register map Data Function range D7 06 05 04 03 02 01 BCD format 00h 0 1 seconds 0 01 seconds Seconds 00 99 01h ST 10 seconds Seconds Seconds 00 59 02h 0 10 minutes Minutes Minutes 00 59 03h CEB CB 10 hours Hours 24 hour format Century hours 0 1 00 23 04h TR 0 0 0 0 Day of week Day 01 7 05h 10 date Date day of month Date 01 31 06h 0 10M Month Month 01 12 07h 10 years Year Year 00 99 08h OUT FT S Calibration Control 09h WDS 4 BMB3 BMB2 1 1 RBO Watchdog OAh AFE 5 ABE AI 10M Alarm month Al month 01 12 OBh RPT4 RPT5 Al 10 date Alarm date Al date 01 31 OCh RPT3 HT Al 10 hour Alarm hour Al hour 00 23 ODh RPT2
45. the total current requirements for data retention The available battery capacity for the top of your choice can then be divided by this current to determine the amount of data retention available see Table 21 on page 40 For a further more detailed review of lifetime calculations please see application note AN1012 Doc ID 7531 Rev 11 ky M41ST85W Clock operation 3 Clock operation The eight byte clock register see Table 2 on page 20 is used to both set the clock and to read the date and time from the clock in a binary coded decimal format Tenths hundredths of seconds seconds minutes and hours are contained within the first four registers Note A WRITE to any clock register will result in the tenths hundredths of seconds being reset to 00 and tenths hundreaths of seconds cannot be written to any value other than 00 Bits D6 and D7 of clock register O3h century hours register contain the CENTURY ENABLE bit and the CENTURY bit CB Setting to a 1 will cause CB to toggle either from O to 1 or from 1 to 0 at the turn of the century depending upon its initial state If CEB is set to a 0 CB will not toggle Bits DO through D2 of register O4h contain the day day of week Registers 05h 06 and 07h contain the date day of month month and years The ninth clock register is the control register this is described in the clock calibration section Bit D7 of register 01
46. xt removed 5V references Figure 1 2 3 4 5 Table 5 10 200 8 8 9 11 12 13 20 21 Reformatted document minor textual changes added lead free second level 03 Oct 2007 9 interconnect information to cover page and Section 6 Package mechanical data updated Table 8 Added Section 8 Environmental information updated Table 8 Section 6 Package 16 Dec 2008 10 mechanical data minor reformatting Updated Table 20 Ordering information scheme as shipping in tubes is not 03 Oct 2011 11 recommended for new design updated Section 8 Environmental information added Figure 25 26 and Table 18 19 42 43 Doc ID 7531 Rev 11 M41ST85W Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this docume
47. y M41ST85W Operating modes Accordingly the following bus conditions have been defined Bus not busy Both data and clock lines remain high Start data transfer A change in the state of the data line from high to low while the clock is high defines the START condition Stop data transfer A change in the state of the data line from low to high while the clock is high defines the STOP condition Data valid The state of the data line represents valid data when after a start condition the data line is stable for the duration of the high period of the clock signal The data on the line may be changed during the low period of the clock signal There is one clock pulse per bit of data Each data transfer is initiated with a start condition and terminated with a stop condition The number of data bytes transferred between the start and stop conditions is not limited The information is transmitted byte wide and each receiver acknowledges with a ninth bit By definition a device that gives out a message is called transmitter the receiving device that gets the message is called receiver The device that controls the message is called master The devices that are controlled by the master are called slaves Acknowledge Each byte of eight bits is followed by one acknowledge bit This acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related c
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