ST M41T56 Serial real-time clock (RTC) with 56 bytes NVRAM handbook
Contents
1. 18 4 mm Note al The dimensions given in Table 13 incorporate tolerances that cover all variations on critical parameters Doc ID 6104 Rev 9 23 27 Part numbering M41T56 7 24 27 Part numbering Table 14 Ordering information scheme Example M41T 56 M Device type M41T Supply voltage and write protect voltage 56 Voc 45t0 5 5 V Package M SO8 Temperature range 6 40 C to 85 C Shipping method E Lead free package ECOPACK tubes F Lead free package ECOPACK tape amp reel 1 Not recommended for new design Contact local ST sales office for availability Doc ID 6104 Rev 9 M41T56 References 8 References e Thecrystal component supplier KDS as cited in Table 8 Crystal electrical characteristics on page 18 can be contacted at http www kds info index en htm ky Doc ID 6104 Rev 9 25 27 Revision history M41T56 9 Revision history Table 15 Document revision history Date Revision Changes Mar 1999 1 0 First issue 23 Dec 1999 1 1 SOH28 package added 21 Mar 2000 1 2 Series resistance max value changed Table 8 30 Nov 2000 1 3 Added PSDIP8 package 25 Jan 2001 1 4 Corrected graphic measurements of PSDIP8 Figure 18 Table 14 16 Feb 2001 2 0 Reformatted table added Table 16 06 Apr 2001 24 Add temp voltage information to characteristics Table 7 Ta2. The devices that are controlled by the master are called slaves Acknowledge Each byte of eight bits is followed by one acknowledge bit This acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge related clock pulse Of course setup and hold times must be taken into account A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave In this case the transmitter must leave the data line high to enable the master to generate the STOP condition Figure 4 Serial bus data transfer sequence DATA LINE STABLE l l DATA VALID CLOCK Ti yf NFL START CHANGE OF STOP CONDITION DATA ALLOWED CONDITION Al00587 Doc ID 6104 Rev 9 ky M41T56 Operation d Figure 5 Acknowledge sequence CLOCK PULSE FOR START ACKNOWLEDGEMENT SCLK FROM DY TRANSMIT we XX X is BY TRANSMITTER M V LSB DATA OUTPUT
3. d M41T56 DC and AC parameters al Table 9 Power down up mode AC characteristics Symbol Parameter Min Max Unit tpp SCL and SDA at Vu before power down 0 ns trp Vprp min to Vss Vcc fall time 300 US tRB Vss to Vprp min Vec rise time 100 US tREC SCL and SDA at Vu after power up 10 US 1 Valid for ambient operating temperature T4 40 to 85 C Vcc 4 5 to 5 5 V except where noted Table 10 Power down up trip points DC characteristics Symbol Parameter 1 2 Min Typ Max Unit Vprp Power fail deselect voltage 1 2 Vgar 1 25 Vpar 1 285 VRAT V Vso Battery back up switchover voltage VRAT V 1 All voltages referenced to Vas 2 Valid for ambient operating temperature T4 40 to 85 C Vcg 4 5 to 5 5 V except where noted Doc ID 6104 Rev 9 19 27 Package mechanical data M41T56 6 20 27 Package mechanical data In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark Doc ID 6104 Rev 9 ky M41T56 Package mechanical data Figure 15 SO8 8 pin plastic small package outline h x 45 A2 A Q ccc 0 25 mm GAUGE PLANE SO A 1 Dra
4. GI M41T56 Serial real time clock RTC with 56 bytes NVRAM Features December 201 1 Counters for seconds minutes hours day date month years and century 32 KHz crystal oscillator integrating load capacitance 12 5 pF providing exceptional oscillator stability and high crystal series resistance operation Serial interface supports IC bus 100 kHz protocol Ultra low battery supply current of 450 nA typ at 3 V 5 V 10 supply voltage Timekeeping down to 2 5 V Automatic power fail detect and switch circuitry 56 bytes of general purpose RAM Software clock calibration to compensate crystal deviation due to temperature Automatic leap year compensation Operating temperature of 40 C to 85 C Available in an 8 lead 150 mil plastic SOIC SO8 RoHS compliant Lead free second level interconnect SO8 150 mil width Doc ID 6104 Rev 9 1 27 www st com Contents M41T56 Contents 1 Description ee ANA REUS Eer 2 Operation vax vs we EL RR RRR R K RR RRR RR 2 1 2 wire bus characteristics s ussas anan 2 1 1 Bus not busy a 2 1 2 Start data transfer 2 1 3 Stop data transfer aa 2 1 4 Data valid anra baria mi eee 2 1 5 Acknowledge 2 2 Read mode 2 3 Write mode 2 4 Data retention mode 3 Clock operation e lt lt lt eee eee eee 3 1 Clock calibration cade RE RR rh 3 2
5. AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2011 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philip
6. 77 ag BY RECEIVER N Al00601 Figure 6 Bus timing requirements sequence SDA fi tBUF Hu tHD STA tHD STA SCL A A i i i i tSU STA m tSU STO E i SA T Al00589 Doc ID 6104 Rev 9 9 27 Operation M41T56 2 2 10 27 Table 2 AC characteristics Symbol Parameter Min Max Unit fscL SCL clock frequency 0 100 kHz tiow Clock low period 4 7 US tHiGH Clock high period 4 US tn SDA and SCL rise time 1 US te SDA and SCL fall time 300 ns hance START condition hold time l 4 E after this period the first clock pulse is generated T START condition setup time 7 47 T only relevant for a repeated start condition tsy par Data setup time 250 ns tup par Data hold time 0 US tsu sto STOP condition setup time 4 7 US Time the bus must be free before a new Jour transmission can start k HS 1 Valid for ambient operating temperature T4 40 to 85 C Vcc 4 5 to 5 5 V except where noted 2 Transmitter must internally provide a hold time to bridge the undefined region 300 ns max of the falling edge of SCL Read mode In this mode the master reads the M41T56 slave after setting the slave address see Figure 7 on page 11 and Figure 8 on page 11 Following the WRITE mode control bit RAW 0 and the acknowledge bit the word address A is written to the on chip address pointer Next the START condition and slave addr
7. Output driver DIE ee paaa aem ERR RARE 3 3 Initial power on defaults 4 Maximum ratings ss x x x x x x x x x eee eee 5 DC and AC parameters 6 Package mechanical data 7 Part numbering sss x x wx ees ane a a o 8 References ie A aa x x x x e e MAMBABAE NGA RE EVE EE 9 Revision history eee 2 27 Doc ID 6104 Rev 9 M41T56 List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Signal NAMES ae deg puru Puce PRIDE LED DP DEAD dud e neces endet vas 6 AC characteristics rr 10 Register map iussu Erio mi emen on qa e ape ee Oed Eur uer qon ane eor as a POR d s 13 Absolute maximum ratings 0 n 16 Operating and AC measurement conditions a 17 Capacitance ehh 17 DC characteristics sa dae ee da a da da ad areas eae ee d 18 Crystal electrical characteristics eens 18 Power down up mode AC characteristics llle 19 Power down up trip points DC characteristics 19 SO8 8 pin plastic small outline package mechanical data aaa 21 Carrier tape dimensions for SO8 package 150 mil body width 22 Reel dimensions for 12 mm carrier tape SO8 package 150 mil body width 23 Ordering information scheme 6c cc eee eens 24 Document revision histo
8. characteristics of the device The parameters in the following DC and AC characteristics tables are derived from tests performed under the measurement conditions listed in Table 5 Operating and AC measurement conditions Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters Table5 Operating and AC measurement conditions Parameter Value Unit Supply voltage Vcc 4 5 to 5 5 V Ambient operating temperature TA 40 to 85 C Load capacitance C 100 pF Input rise and fall times lt 5 ns Input pulse voltages 0to3 V Input and output timing ref voltages 1 5 1 Output Hi Z is defined as the point where data is no longer driven Figure 13 AC measurement I O waveform 0 8Vcc 0 2Vcc Al02568 Table 6 Capacitance Symbol Parameter 1 2 Min Max Unit Cin Input capacitance SCL 7 pF Cour Output capacitance SDA FT OUT 10 pF tip Low pass filter input time constant SDA and SCL 0 25 1 us 1 Effective capacitance measured with power supply at 5V sampled not 100 tested 2 At25 C f 1 MHz 3 Outputs deselected ky Doc ID 6104 Rev 9 17 27 DC and AC parameters M41T56 Table 7 DC characteristics Symbol Parameter Test condition Min Typ Max Unit lu Input leakage current OV lt Vin lt Mee 1 HA lo Output leakage current OV lt Vout Vec 1 H
9. supply All outputs become high impedance On power up when Vcc returns to a nominal value write protection continues for tpgc For a further more detailed review of battery lifetime calculations please see application note AN1012 Figure 10 Write mode sequence tC a BUS ACTIVITY E Iz o MASTER N c N WORD SDA LINE ADDRESS n DATA n DATA n 1 DATA n X BUS ACTIVITY O 5 5 5 5 1 i Es lt lt E SLAVE ADDRESS Al00591 Doc ID 6104 Rev 9 ky M41T56 Clock operation 3 Note Clock operation The eight byte clock register see Table 3 is used to both set the clock and to read the date and time from the clock in a binary coded decimal format Seconds minutes and hours are contained within the first three registers Bits D6 and D7 of clock register 2 hours register contain the century enable bit CEB and the century bit CB Setting CEB to a 1 will cause CB to toggle either from 0 to 1 or from 1 to 0 at the turn of the century depending upon its initial state If CEB is set to a O CB will not toggle Bits DO through D2 of register 3 contain the day day of week Registers 4 5 and 6 contain the date day of month month and years The final register is the control register this is described in the clock calibration section Bit D7 of register O contains the stop bit ST Setting this bit to a 1 will cause the oscillator to stop If the device is expected to spend a sign
10. 2566 Doc ID 6104 Rev 9 ky M41T56 Operation 2 2 1 Operation The M41T56 clock operates as a slave device on the serial bus Access is obtained by implementing a start condition followed by the correct slave address DOh The 64 bytes contained in the device can then be accessed sequentially in the following order Seconds register Minutes register Century hours register Day register Date register Month register Years register Control register RAM 0 D MM The clock continually monitors Vcc for an out of tolerance condition Should Voc fall below Vprp the device terminates an access in progress and resets the device address counter Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out of tolerance system When Ve falls below Vaar the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life Upon power up the device switches from battery to Vcc at Vpar and recognizes inputs when Vcc goes above Vppp volts 2 wire bus characteristics This bus is intended for communication between different ICs It consists of two lines one bidirectional for data signals SDA and one for clock signals SCL Both the SDA and the SCL lines must be connected to a positive supply voltage via a pull up resistor The following protocol has been defined e Datatrans
11. A leen Supply current Switch frequency 100 kHz 300 UA Icce Supply current standby SCL SDA Vcc 0 3 V 100 UA Vu Input low voltage 0 3 1 5 V Vin Input high voltage 3 Vcc 0 8 V VoL Output low voltage Jo 5mA Voc 4 5 V 0 4 V Vos Battery supply voltage 2 5 3 3 5 V Ilgar Battery supply current Pu es he Nice V 450 550 nA 1 Valid for ambient operating temperature T4 40 to 85 C Vcc 4 5 to 5 5 V except where noted 2 STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 or equivalent as the battery supply Table 8 Crystal electrical characteristics Symbol Parameter 1 2 Min Typ Max Unit fo Resonant frequency 32 768 kHz Rs Series resistance 60 kQ CL Load capacitance 12 5 pF 1 These values are externally supplied for the SO8 package STMicroelectronics recommends the KDS DT 38 1TA 1TC252E127 Tuning Fork Type thru hole or the DMX 26S 1TJS125FH2A212 SMD quartz crystal for industrial temperature operations For contact information on this crystal type see Section 8 References on page 25 2 Load capacitors are integrated within the M41T56 Circuit board layout considerations for the 32 768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account Figure 14 Power down up mode AC waveforms IBAT 4 DATA RETENTION TIME Al00595 18 27 Doc ID 6104 Rev 9
12. S 5 5 5 5 i A lt lt lt lt lt i i 9 SLAVE 3 ADDRESS Al00895 ky Doc ID 6104 Rev 9 11 27 Operation M41T56 2 3 2 4 12 27 Write mode In this mode the master transmitter transmits to the M41T56 slave receiver Bus protocol is shown in Figure 10 on page 12 Following the START condition and slave address a logic 0 RAW 0 is placed on the bus and indicates to the addressed device that word address A will follow and is to be written to the on chip address pointer The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the RAM on the reception of an acknowledge clock The M41T56 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte see Figure 7 on page 1 1 Data retention mode With valid Vcc applied the M41T56 can be accessed as described above with READ or WRITE cycles Should the supply voltage decay the M41T56 will automatically deselect write protecting itself when Vcc falls between Vprp max and Vprp min This is accomplished by internally inhibiting access to the clock registers and SRAM When Vcc falls below the battery backup switchover voltage Vso power input is switched from the Vcc pin to the battery and the clock registers and SRAM are maintained from the attached battery
13. T bit will be set to a O and the OUT bit will be set to a 1 All other register bits will initially power on in a random state ky Doc ID 6104 Rev 9 15 27 Maximum ratings M41T56 4 Caution 16 27 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Table 4 Absolute maximum ratings Symbol Parameter Value Unit TA Ambient operating temperature 40 to 85 C Tsra Storage temperature Vcc off oscillator off 55 to 125 C Tai nU Lead solder temperature for 10 seconds 260 Ke Vio Input or output voltages 0 3 to 7 Voc Supply voltage 0 3 to 7 V lo Output current 20 mA Pp Power dissipation 0 25 W 1 For SO package Lead free Pb free lead finish Reflow at peak temperature of 260 C The time above 255 C must not exceed 30 seconds Negative undershoots below 0 3 V are not allowed on any pin while in the battery backup mode Doc ID 6104 Rev 9 M41T56 DC and AC parameters 5 DC and AC parameters This section summarizes the operating and measurement conditions as well as the DC and AC
14. ble 2 correct series resistance Table 8 17 Jul 2001 2 2 Basic formatting changes 02 Aug 2002 23 Modify reflow time and temperature footnote Table 4 modify crystal electrical g characteristics table footnotes Table 8 removed PSDIP8 package 07 Nov 2002 2 4 Correct figure name Features on page 1 15 Jun 2004 3 0 Reformatted add lead free information update characteristics Figure 11 Table 4 Table 14 Changed document to new template amalgamated diagrams in Features on page 1 41 Sep 2006 4 amended footnotes in Table 3 Register map updated Package mechanical data in P Section 6 Package mechanical data small text changes for entire document removed lead packages from Table 14 ECOPACK compliant 09 Oct 2006 5 Updated package mechanical data in Figure 15 SO8 8 pin plastic small package outline 40 Apr 2007 6 Updated package information references that only SO8 available cover page Section 1 p Section 4 Table 4 Table 8 and Table 14 Added lead free second level interconnect information to cover page and Section 6 06 Nov 2007 7 Package mechanical data updated Table 4 footnote 1 in Table 8 addition of Section 8 References 13 Dec 2007 8 Updated cover page and Section 8 References Updated footnote 7 of Table 4 Absolute maximum ratings updated ECOPACK text in 06 Dec 2011 9 Section 6 Package mechanical data added footnote 7 to Table 14 Ordering information scheme added Figure 16 17 Table 12 13 updated title minor
15. curs within a 64 minute cycle The first 62 minutes in the cycle may once per minute have one second either shortened by 128 or lengthened by 256 oscillator cycles If a binary 1 is loaded into the register only the first 2 minutes in the 64 minutes cycle will be modified if a binary 6 is loaded the first 12 will be affected and so on Therefore each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125 829 120 actual oscillator cycles that is 4 068 or 2 034 ppm of adjustment per calibration step in the calibration register Assuming that the oscillator is in fact running at exactly 32 768Hz each of the 31 increments in the calibration byte would represent 10 7 or 5 35 seconds per month which corresponds to a total range of 45 5 or 2 75 minutes per month Two methods are available for ascertaining how much calibration a given M41T56 may require The first involves simply setting the clock letting it run for a month and comparing it to a known accurate reference like WWV broadcasts While that may seem crude it allows the designer to give the end user the ability to calibrate his clock as his environment may require even after the final product is packaged in a non user serviceable enclosure All the designer has to do is provide a simple utility that accessed the calibration byte The second approach is better suited to a manufacturing environment and involves the use of some test equ
16. ess are repeated followed by the READ mode control bit R W 1 At this point the master transmitter becomes the master receiver The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter The address pointer is only incremented on reception of an acknowledge bit The M41T56 slave transmitter will now place the data byte at address A 1 on the bus The master receiver reads and acknowledges the new byte and the address pointer is incremented to A 2 This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter An alternate READ mode may also be implemented whereby the master reads the M41T56 slave without first writing to the volatile address pointer The first address that is read is the last one stored in the pointer see Figure 9 on page 11 Doc ID 6104 Rev 9 ky M41T56 Operation Figure 7 Slave address location R W START E SLAVE ADDRESS In im 4 1g tn i o i HMHG Al00602 Figure 8 Read mode sequence H H E tc BUS ACTIVITY E lt E MASTER o m o H SDA LINE DATA n 1 BUS ACTIVITY SLAVE SLAVE ADDRESS ADDRESS 5 E 05 DATA n X Oe O lt O Fa Al00899 Figure 9 Alternative read mode sequence E a BUS ACTIVITY Iz O MASTER o s o SDA LINE DATA n 1 DATA n X BUS ACTIVITY 1
17. fer may be initiated only when the bus is not busy e During data transfer the data line must remain stable whenever the clock line is high e Changesin the data line while the clock line is high will be interpreted as control signals Accordingly the following bus conditions have been defined Bus not busy Both data and clock lines remain high Start data transfer A change in the state of the data line from high to low while the clock is high defines the START condition Doc ID 6104 Rev 9 7 27 Operation M41T56 2 1 3 8 27 Stop data transfer A change in the state of the data line from low to high while the clock is high defines the STOP condition Data valid The state of the data line represents valid data when after a start condition the data line is stable for the duration of the high period of the clock signal The data on the line may be changed during the low period of the clock signal There is one clock pulse per bit of data Each data transfer is initiated with a start condition and terminated with a stop condition The number of data bytes transferred between the start and stop conditions is not limited The information is transmitted byte wide and each receiver acknowledges with a ninth bit By definition a device that gives out a message is called transmitter the receiving device that gets the message is called receiver The device that controls the message is called master
18. ificant amount of time on the shelf the oscillator may be stopped to reduce current drain When reset to a 0 the oscillator restarts within one second The seven clock registers may be read one byte at a time or in a sequential block The control register address location 7 may be accessed independently Provision has been made to assure that a clock update does not occur while any of the seven clock addresses are being read If a clock address is being read an update of the clock registers will be delayed by 250 ms to allow the READ to be completed before the update occurs This will prevent a transition of data during the READ This 250 ms delay affects only the clock register update and does not alter the actual clock time Table3 Register map Address Data Function range D7 D6 D5 D4 D3 D2 D1 DO BCD format 0 ST 10 Seconds Seconds Seconds 00 59 1 X 10 Minutes Minutes Minutes 00 59 2 CEB CB 10 hours Hours Century hours 0 1 00 23 3 X X X X X Day Day 01 07 4 X X 10 date Date Date 01 31 5 X X X 10M Month Month 01 12 6 10 years Years Year 00 99 7 OUT FT S Calibration Control 1 Keys S Sign bit FT Frequency test bit ST Stop bit OUT Output level X Don t care CEB Century enable bit CB Century bit 2 When CEB is set to 1 CB toggles from 0 to 1 or from 1 to 0 every 100 years dependent upon the initial value set When CEB is se
19. ipment When the frequency test FT bit the seventh most significant bit in the control register is set to a 1 and the oscillator is running at 32 768 Hz the FT OUT pin of the device will toggle at 512 Hz Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature For example a reading of 512 01024 Hz would indicate a 20 ppm oscillator frequency error requiring a 10 XX001010 to be loaded into the calibration byte for correction Setting or changing the calibration byte does not affect the frequency test output frequency Doc ID 6104 Rev 9 ky M41T56 Clock operation Figure 11 Crystal accuracy across temperature Frequency ppm Kx T To K 0 036 ppm C 0 006 ppm C2 To 25 C 5 C 40 30 20 10 0 10 20 30 40 50 60 70 80 Temperature C Al00999b Figure 12 Clock calibration NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION Al00594B 3 2 Output driver pin When the FT bit is not set the FT OUT pin becomes an output driver that reflects the contents of D7 of the control register In other words when D6 of location 7 is a 0 and D7 of location 7 is a 0 and then the FT OUT pin will be driven low Note The FT OUT pin is open drain which requires an external pull up resistor 3 3 Initial power on defaults Upon initial application of power to the device the F
20. lendar function and are configured in binary coded decimal BCD format Addresses and data are transferred serially via a two line bidirectional bus The built in address register is incremented automatically after each WRITE or READ data byte The M41T56 clock has a built in power sense circuit which detects power failures and automatically switches to the battery supply during power failures The energy needed to sustain the RAM and clock operations can be supplied from a small lithium coin cell Typical data retention time is in excess of 10 years with a 50 mAh 3 V lithium cell The M41T56 is supplied in an 8 lead plastic SOIC package Figure 1 Logic diagram Vcc VBAT OSCI OSCO SCL M41T56 SDA FT OUT Vss Al02304B Doc ID 6104 Rev 9 5 27 Description M41T56 Table 1 Signal names OSCI Oscillator input OCSO Oscillator output FT OUT Frequency test output driver open drain SDA Serial data address input output SCL Serial clock VRAT Battery supply voltage Vec Supply voltage Vss Ground Figure 2 8 pin SOIC connections M41T56 OSC 8 H Vcc OSCO E42 7 PI FT OUT VBAT L3 6 HI SCL Vss L14 BJ SDA AI02306B Figure 3 M41T56 block diagram C DIVIDER OSCO os 6 27 FT OUT VOLTAGE Voc SENSE CONTROL V and SS SWITCH LOGIC VBAT CIRCUITRY SCL SERIAL BUS INTERFACE SDA ADDRESS REGISTER CONTROL RAM 56 x 8 I j Al0
21. pines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 6104 Rev 9 27 27
22. ry 26 Doc ID 6104 Rev 9 3 27 List of figures M41T56 List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 4 27 Logic diagrami 0 4 nes bbw REENEN eek Rea pena ker EEN Rode c n a Rn 5 8 pin SOIC connections 000 rn 6 M41T56 block diagram s c ss r r R a R RRR a 6 Serial bus data transfer sequence aa 8 Acknowledge sequence cece ete ees 9 Bus timing requirements sequence 9 Slave address location tetas 11 Read mode sequence s e x enr 11 Alternative read mode sequence lssleeeeeeeee eh 11 Write mode sequence e e e eh rr 12 Crystal accuracy across temperature eee ene eee 15 Clock calibration ee duse REOR t e Ren Lee eis ROS RO o ee Ed Rab CD NN 15 AC measurement I O waveform rs 17 Power down up mode AC waveforms cece ees 18 S08 8 pin plastic small package outline 0 21 Carrier tape for SO8 package 150 mil body width 22 Reel schematic ega eee ede ed raices ae ore eR ker PD Edna DALAG KG RR e N 23 Doc ID 6104 Rev 9 ky M41T56 Description Description The M41T56 is a low power serial real time clock RTC with 56 bytes of NVRAM A built in 32 768 Hz oscillator external crystal controlled and the first 8 bytes of the RAM are used for the clock ca
23. t to 0 CB does not toggle Doc ID 6104 Rev 9 13 27 Clock operation M41T56 3 1 Note 14 27 Clock calibration The M41T56 is driven by a quartz controlled oscillator with a nominal frequency of 32 768 Hz The devices are tested not to exceed 35 ppm parts per million oscillator frequency error at 25 C which equates to about 1 53 minutes per month With the calibration bits properly set the accuracy of each M41T56 improves to better than 2 ppm at 25 C The oscillation rate of any crystal changes with temperature see Figure 11 on page 15 Most clock chips compensate for crystal frequency and temperature shift error with cumbersome trim capacitors The M41T56 design however employs periodic counter correction The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage as shown in Figure 11 on page 15 The number of times pulses are blanked subtracted negative calibration or split added positive calibration depends upon the value loaded into the five bit calibration byte found in the control register Adding counts speeds the clock up subtracting counts slows the clock down The calibration byte occupies the five lower order bits D4 D0 in the control register addr 7 This byte can be set to represent any value between 0 and 31 in binary form Bit D5 is the sign bit 1 indicates positive calibration 0 indicates negative calibration Calibration oc
24. textual updates 26 27 Doc ID 6104 Rev 9 ky M41T56 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE
25. wing is not to scale Table 11 8 SO8 8 pin plastic small outline package mechanical data millimetres inches Symbol Typ Min Max Typ Min Max A 1 75 0 069 Al 0 10 0 25 0 004 0 010 A2 1 25 0 049 b 0 28 0 48 0 011 0 019 C 0 17 0 23 0 007 0 009 ccc 0 10 0 004 D 4 90 4 80 5 00 0 193 0 189 0 197 E 6 00 5 80 6 20 0 236 0 228 0 244 E1 3 90 3 80 4 00 0 154 0 150 0 157 e 1 27 0 050 h 0 25 0 50 0 010 0 020 k 0 8 0 8 L 0 40 1 27 0 016 0 050 L1 1 04 0 041 1 Drawing is not to scale GI Doc ID 6104 Rev 9 21 27 Package mechanical data M41T56 Figure 16 Carrier tape for SO8 package 150 mil body width TAPE CENTER LINES gt KK OF CAVITY USER DIRECTION OF FEED AM03073v1 Table 12 Carrier tape dimensions for SO8 package 150 mil body width Package 22 27 Doc ID 6104 Rev 9 ky M41T56 Package mechanical data Figure 17 Reel schematic Full radius 40mm min Access hole At slot location Tape slot In core for Tape start 2 5mm min width G measured At hub AM04928v1 Table 13 Reel dimensions for 12 mm carrier tape SO8 package 150 mil body width A max 330 mm 13 inch B min 1 5 mm D min 20 2 mm N min 60 mm G 12 4 mm 2 0 mm T max
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ST M41T56 Serial real time clock (RTC) with 56 bytes NVRAM handbook