ST M24256-B M24128-B handbook
Contents
1. reliability Refer also to the STMicroelectronics SURE Program and other relevant quality docu ments 2 2 JEDEC Std JESD22 A114A C1 100 pF R1 1500 Q R2 500 Q 2 11 25 M24256 B M24128 B DC AND AC PARAMETERS This section summarizes the operating and mea surement conditions and the DC and AC charac teristics of the device The parameters in the DC and AC Characteristic tables that follow are de rived from tests performed under the Measure Table 7 Operating Conditions M24xxx B Parameter ment Conditions summarized in the relevant tables Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame Supply Voltage ters Unit 4 5 5 5 Table 8 Operating Conditions M24xxx BV Parameter Supply Voltage Unit 2 5 3 6 Table 9 Operating Conditions M24xxx BW Parameter Supply Voltage Table 10 Operating Conditions M24xxx BR Parameter Symbol Voc Supply Voltage Ambient Operating Temperature Table 11 Operating Conditions M24xxx BS Parameter Symbol Voc Supply Voltage V Table 12 AC Measurement Conditions Parameter Load Capacitance Input Levels 100 pF Input and Output Timing Reference Levels 0 3Vcc to 0 7Vcc 12 25 2 M24256 B M24128 B Figure 10 AC Measurement I O Waveform Input Levels Input and Output Timing Reference Leve2. 18 25 M24256 B M24128 B PACKAGE MECHANICAL PDIP8 8 pin Plastic DIP 0 25mm lead frame Package Outline PDIP B Notes 1 Drawing is not to scale PDIP8 8 pin Plastic DIP 0 25mm lead frame Package Mechanical Data inches SZA 19 25 M24256 B M24128 B SO8 narrow 8 lead Plastic Small Outline 150 mils body width Package Outline Note Drawing is not to scale SO8 narrow 8 lead Plastic Small Outline 150 mils body width Package Mechanical Data inches 2 20 25 M24256 B M24128 B SO8 wide 8 lead Plastic Small Outline 200 mils body width Package Outline Note Drawing is not to scale SO8 wide 8 lead Plastic Small Outline 200 mils body width Package Mechanical Data inches 2 21 25 M24256 B M24128 B TSSOP8 8 lead Thin Shrink Small Outline Package Outline TSSOP8AM Notes 1 Drawing is not to scale TSSOP8 8 lead Thin Shrink Small Outline Package Mechanical Data inches Min 2 22 25 M24256 B M24128 B PART NUMBERING Table 22 Ordering Information Scheme Example M24256 B W MN 6 T Device Type M24 IC serial access EEPROM Device Function 256 256 Kbit 82K x 8 128 128 Kbit 16K x 8 Operating Voltage blank Vcc 4 5 to 5 5V V2 Voc 2 5 to 3 6V Wt Vcc 2 5 to 5 5V R3 Vcc 1 8 to 5 5V S Vcc 1 8 t
3. 400kHz rise fall time lt 30ns Stand by Supply Current Vin Vss or Voc Vcc 2 5 V Input Low Voltage SCL SDA Input Low Voltage Di E2 E1 E0 WC 0 3 Input High Voltage z Vit E2 E1 E0 SCL SDA WC 0 7Vec Output Low Voltage lo 2 1 MA Voc 2 5 V 04 14 25 M24256 B M24128 B Table 18 DC Characteristics M24xxx BR Test Condition Parameter in addition to those in Table 10 Input Leakage Current Vin Vss or Voc SCL SDA device in Stand by mode Output Leakage Current Vout Vss or Vcc SDA in Hi Z Supply Current Voc 1 8V fo 100kHz rise fall time lt 30ns Stand by Supply Current Vin Vss or Voc Vcc 1 8 V Input Low Voltage SCL SDA Input Low Voltage E2 E1 E0 WC Note 1 This is Preliminary Data Table 19 DC Characteristics M24xxx BS Test Condition Parameter in addition to those in Table 11 Input Leakage Current Vin Vss or Voc SCL SDA device in Stand by mode Output Leakage Current Vout Vss or Vcc SDA in Hi Z Supply Current Voc 1 8V fo 400kHz rise fall time lt 30ns Stand by Supply Current Vin Vss or Voc Vcc 1 8 V Input Low Voltage SCL SDA Input Low Voltage L E2 E1 E0 WC 0 3 Input High Voltage a VH E2 E1 E0 SCL SDA WG 0 7Voc OL Output Low Voltage lo 0 7 MA Voc 1 8 V ENN Note 1 This is Preliminary Data V 2 15 25 M24256 B M24128 B Table 20 AC Characteristics M24xxx B M2
4. Operation y Continue the Continue the WRITE Operation Random READ Operation AI01847C Step 1 the bus master issues a Start condition Minimizing System Delays by Polling On ACK followed by a Device Select Code the first byte During the internal Write cycle the device discon of the new instruction nects itself from the bus and writes a copy of the Step 2 if the device is busy with the internal data from its internal latches to the memory cells Write cycle no Ack will be returned and the bus The maximum Write time tw is shown in Tables master goes back to Step 1 If the device has 20 and 21 but the typical time is shorter To make terminated the internal Write cycle it responds use of this a polling sequence can be used by the with an Ack indicating that the device is ready bus master to receive the second part of the instruction the The sequence as shown in Figure 8 is first byte of this instruction having been sent Initial condition a Write cycle is in progress duning Stap 1 2 8 25 Figure 9 Read Mode Sequences M24256 B M24128 B ACK NO ACK CURRENT ADDRESS eed READ RW RANDOM ADDRESS SEQUENTIAL CURRENT READ SEQUENTIAL RANDOM READ ACK NO ACK nen r DEV SEL BYTE ADDR BYTE ADDR I DEV SEL READ NO ACK DATA OUT RW NO ACK rs ACK RW AI01105C Note 1 The seven most significant bits of the Device Select Code of a Random Read in the 15
5. and 4 bytes must be identical Read Operations Read operations are performed independently of the state of the Write Control WC signal Random Address Read A dummy Write is performed to load the address into the address counter as shown in Figure 9 but without sending a Stop condition Then the bus master sends another Start condition and repeats the Device Select Code with the RW bit set to 1 The device acknowledges this and outputs the contents of the addressed byte The bus master must not acknowledge the byte and terminates the transfer with a Stop condition SZ Current Address Read The device has an internal address counter which is incremented each time a byte is read For the Current Address Read operation following a Start condition the bus master only sends a Device Se lect Code with the RW bit set to 1 The device ac knowledges this and outputs the byte addressed by the internal address counter The counter is then incremented The bus master terminates the transfer with a Stop condition as shown in Figure 9 without acknowledging the byte Sequential Read This operation can be used after a Current Ad dress Read or a Random Address Read The bus 9 25 M24256 B M24128 B master does acknowledge the data byte output and sends additional clock pulses so that the de vice continues to output the next byte in sequence To terminate the stream of bytes the bus master must not acknowledge th
6. are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners 2002 STMicroelectronics All Rights Reserved STMicroelectronics group of companies Australia Brazil Canada China Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States www st com SZA 25 25
7. the I C bus defini tion The device behaves as a slave in the 1 C protocol with all memory operations synchronized by the serial clock Read and Write operations are initiat ed by a Start condition generated by the bus mas ter The Start condition is followed by a Device Select Code and RW bit as described in Table 2 terminated by an acknowledge bit When writing data to the memory the device in serts an acknowledge bit during the gih bit time 2 25 following the bus masters 8 bit transmission When data is read by the bus master the bus master acknowledges the receipt of the data byte in the same way Data transfers are terminated by a Stop condition after an Ack for Write and after a NoAck for Read Power On Reset Vcc Lock Out Write Protect In order to prevent data corruption and inadvertent write operations during power up a Power On Re set POR circuit is included The internal reset is held active until Vcc has reached the POR thresh old value and all operations are disabled the de vice will not respond to any command In the same way when Vcc drops from the operating voltage below the POR threshold value all operations are disabled and the device will not respond to any command A stable and valid Vcc must be applied before applying any logic signal When the power supply is turned on Vcc rises from Vss to Voc min passing through a value Vin in between The V and S versions of the devic
8. 0 0 M24128 BR DD SI M24256 B M24128 B 256Kbit and 128Kbit Serial IPC Bus EEPROM With Three Chip Enable Lines FEATURES SUMMARY m Compatible with I2C Extended Addressing Figure 1 Packages m Two Wire I C Serial Interface Supports 400 kHz Protocol m Single Supply Voltage 4 5V to 5 5V for M24xxx B 2 5V to 3 6V for M24xxx BV 2 5V to 5 5V for M24xxx BW 1 8V to 5 5V for M24xxx BR 1 8V to 3 6V for M24xxx BS Hardware Write Control BYTE and PAGE WRITE up to 64 Bytes RANDOM and SEQUENTIAL READ Modes Self Timed Programming Cycle Automatic Address Incrementing Enhanced ESD Latch Up Behavior More than 100 000 Erase Write Cycles More than 1 Million Erase Write cycles for the products specified in Table 22 SO8 MN m More than 40 Year Data Retention 150 mil width SCS TSSOP8 DW 169 mil width November 2002 1 25 M24256 B M24128 B SUMMARY DESCRIPTION These 1 C compatible electrically erasable programmable memory EEPROM devices are organized as 32Kx8 bits M24256 B and 16K x 8 bits M24128 B Figure 2 Logic Diagram M24256 B M24128 B AI02809 Table 1 Signal Names EO E1 E2 Chip Enable SCL Serial Clock VCC Supply Voltage These devices are compatible with the IC memo ry protocol This is a two wire serial interface that uses a bi directional data bus and serial clock The devices carry a built in 4 bit Device Type Identifier code 1010 in accordance with
9. 4xxx BW a t t Time between Stop Condition and Next Start Condition F tpLipLe ote SDA Fall Time Write Time Note 1 For a reSTART condition or following a Write cycle 2 Sampled only not 100 tested 3 To avoid spurious START and STOP conditions a minimum delay is placed between SCL 1 and the falling or rising edge of SDA 4 The Write Time of 5 ms only applies to M24128 B and M24128 BW devices bearing the process letter B in the package marking on the top side of the package on the right side otherwise the Write Time is 10 ms For further details please contact your nearest ST sales office and ask for a copy of the M24128 Product Change Notice 2 16 25 M24256 B M24128 B Table 21 AC Characteristics M24xxx BV M24xxx BR M24xxx BS pom me Ferme ae era o CEE CO o t t Time between Stop Condition and Next Start DEE BUE Condition twr Write Time R tr R tr DH AA Note 1 For a reSTART condition or following a Write cycle 2 Sampled only not 100 tested 3 To avoid spurious START and STOP conditions a minimum delay is placed between SCL 1 and the falling or rising edge of SDA 17 25 M24256 B M24128 B Figure 11 AC Waveforms tCHDX tCLDX SDA tCHDH tDHDL START SDA gt Change i STOP START Condition Condition Condition tW tCHDX STOP Write Cycle START Condition Condition SDA Out Data Valid AI00795C 2
10. 7 is sent first 2 E0 E1 and E2 are compared against the respective external pins on the memory device Table 3 Most Significant Byte Table 4 Least Significant Byte Oi eee eee 4 25 SI DEVICE OPERATION The device supports the Ko protocol This is sum marized in Figure 5 Any device that sends data on to the bus is defined to be a transmitter and any device that reads the data to be a receiver The device that controls the data transfer is known as the bus master and the other as the slave device A data transfer can only be initiated by the bus master which will also provide the serial clock for synchronization The M24xxx B device is always a slave in all communication Start Condition Start is identified by a falling edge of Serial Data SDA while Serial Clock SCL is stable in the High state A Start condition must precede any data transfer command The device continuously monitors except during a Write cycle Serial Data SDA and Serial Clock SCL for a Start condition and will not respond unless one is given Stop Condition Stop is identified by a rising edge of Serial Data SDA while Serial Clock SCL is stable and driv en High A Stop condition terminates communica tion between the device and the bus master A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand by mode A Stop condition at the end of a Write command triggers the internal EE
11. PROM Write cycle Acknowledge Bit ACK The acknowledge bitis used to indicate a success ful byte transfer The bus transmitter whether it be bus master or slave device releases Serial Data SDA after sending eight bits of data During the 9th clock pulse period the receiver pulls Serial Table 5 Operating Modes M24256 B M24128 B Data SDA Low to acknowledge the receipt of the eight data bits Data Input During data input the device samples Serial Data SDA on the rising edge of Serial Clock SCL For correct device operation Serial Data SDA must be stable during the rising edge of Serial Clock SCL and the Serial Data SDA signal must change only when Serial Clock SCL is driv en Low Memory Addressing To start communication between the bus master and the slave device the bus master must initiate a Start condition Following this the bus master sends the Device Select Code shown in Table 2 on Serial Data SDA most significant bit first The Device Select Code consists of a 4 bit Device Type Identifier and a 3 bit Chip Enable Address E2 E1 E0 To address the memory array the 4 bit Device Type Identifier is 1010b Up to eight memory devices can be connected on a single I C bus Each one is given a unique 3 bit code on the Chip Enable E0 Et E2 inputs When the Device Select Code is received on Seri al Data SDA the device only responds if the Chip Enable Address is the same as th
12. Serial Data SDA to Vcc Fig ure 4 indicates how the value of the pull up resistor can be calculated M24256 B M24128 B Chip Enable EO E1 E2 These input signals are used to set the value that is to be looked for on the three least significant bits b3 b2 b1 of the 7 bit Device Select Code These inputs must be tied to Vcc or Vss to establish the Device Select Code Write Control WC This input signal is useful for protecting the entire contents of the memory from inadvertent write op erations Write operations are disabled to the en tire memory array when Write Control WC is driven High When unconnected the signal is in ternally read as ViL and Write operations are al lowed When Write Control WC is driven High Device Select and Address bytes are acknowledged Data bytes are not acknowledged Figure 4 Maximum RL Value versus Bus Capacitance Cpus for an I C Bus Voc 20 G 16 U x A o L g 12 A Ra MASTER c Eg gt BUS E 8 4 AE 0 10 100 1000 CBus pF AI01665 ky 3 25 M24256 B M24128 B Figure 5 I C Bus Protocol i SDA gt SDA gt i START Input Change STOP Condition Condition START Condition STOP Condition AI00792B Table 2 Device Select Code Device Type Identifier Chip Enable Address b7 b6 b5 b4 b3 b2 b1 peso _ 0 o AW Note 1 The most significant bit b
13. e the M24xxx BV and M24xxx BS ignore all instruc tions until a time delay of try has elapsed after the moment that Vcc rises above the Vin threshold However the correct operation of the device is not guaranteed if by this time Vcc is still below Vcc min No instructions should be sent until the later of tpu after Vcc passed the Vin threshold Vcc passed the Vcc min level These values are specified in Table 14 Figure 3 DIP SO and TSSOP Connections M24256 B M24128 B Al02810B Note 1 See page 19 onwards for package dimensions and how to identify pin 1 2 SIGNAL DESCRIPTION Serial Clock SCL This input signal is used to strobe all data in and out of the device In applications where this signal is used by slave devices to synchronize the bus to a slower clock the bus master must have an open drain output and a pull up resistor must be con nected from Serial Clock SCL to Vcc Figure 4 indicates how the value of the pull up resistor can be calculated In most applications though this method of synchronization is not employed and so the pull up resistor is not necessary provided that the bus master has a push pull rather than open drain output Serial Data SDA This bi directional signal is used to transfer data in or out of the device It is an open drain output that may be wire OR ed with other open drain or open collector signals on the bus A pull up resistor must be connected from
14. e last byte and must generate a Stop condition as shown in Figure 9 The output data comes from consecutive address es with the internal address counter automatically incremented after each byte output After the last memory address the address counter rolls over and the device continues to output data from memory address 00h 10 25 Acknowledge in Read Mode For all Read commands the device waits after each byte read for an acknowledgment during the gth bit time If the bus master does not drive Serial Data SDA Low during this time the device termi nates the data transfer and switches to its Stand by mode 2 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause per manent damage to the device These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im Table 6 Absolute Maximum Ratings Symbol Parameter PDIP 10 seconds SO 20 seconds max TSSOP 20 seconds max Lead Temperature during Soldering Input or Output range Supply Voltage Electrostatic Discharge Voltage Human Body model Note 1 IPC JEDEC J STD 020A V voltage range all other voltage ranges V voltage range all other voltage ranges M24256 B M24128 B plied Exposure to Absolute Maximum Rating con ditions for extended periods may affect device
15. e value on the Chip Enable E0 E1 E2 inputs The 8 bit is the Read Write bit RW This bit is set to 1 for Read and 0 for Write operations If a match occurs on the Device Select code the corresponding device gives an acknowledgment on Serial Data SDA during the 9 bit time If the device does not match the Device Select code it deselects itself from the bus and goes into Stand by mode 1 Bytes Initial Sequence 1 START Device Select RW 1 Za START Device Select RW 0 Address 1 reSTART Device Select RW 1 gt 1 Similar to Current or Random Address Read START Device Select RW 0 Note 1 X Vigor Vir 2 START Device Select RW 0 5 25 M24256 B M24128 B Figure 6 Write Mode Sequences with WC 1 data write inhibited ACK BYTE WRITE PAGE WRITE NO ACK NO ACK 1 DATAINN sd PAGE WRITE cont d Write Operations Following a Start condition the bus master sends a Device Select Code with the RW bit reset to 0 The device acknowledges this as shown in Figure 7 and waits for two address bytes The device re sponds to each address byte with an acknowledge bit and then waits for the data byte Writing to the memory may be inhibited if Write Control WC is driven High Any Write instruction with Write Control WC driven High during a pe riod of time from the Start condition until the end of the two address bytes will not modify the memory contents and the acc
16. ide package added References to PSDIP8 changed to PDIP8 and Package Mechanical data updated 5 R voltage range added Package mechanical data updated for TSSOP8 and TSSOP14 01 Jun 2001 2 packages according to JEDECIMO 153 Document promoted from Preliminary Data to Full Data Sheet TSSOP14 package removed 16 POZO 6 Absolute Max Ratings and DC characteristics updated for M24256 BV 09 Nov 2001 Specification of Test Condition for Leakage Currents in the DC Characteristics table improved 21 Mar 2002 il cycle endurance for M24256 B and M24256 BW products with process 18 Oct 2002 3 0 Document reformatted Parameters changed are 1 million Erase Write cycle endurance and 5 i ms write time for M24128 B and M24128 BW products with process letter B Superfluous and incorrectly present 100kHz AC Characteristics table for M24256 BR 20 Nov 2002 rea eg 24 25 M24256 B M24128 B Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products
17. ls 0 8VCC 0 2Vcc Al00825B Table 13 Input Parameters Cn input cs other Input Capacitance other pins EE Roa lm BEE ara sow Sroa m wo Note 1 Ta 25 C f 400 kHz 2 Sampled only not 100 tested Table 14 M24xxx BV Power Up Timing and Vin Threshold sym CCIE ESITI Threshold Voltage Note 1 These parameters are characterized only Table 15 DC Characteristics M24xxx B Symbol Parameter Test Condition y in addition to those in Table 7 Input Leakage Current Vin Vss or Voc SCL SDA device in Stand by mode Output Leakage Current Vout Vss or Voc SDA in Hi Z Supply Current Voc 5V fo 400kHz rise fall time lt 30ns Stand by Supply Current Vin Vss or Vcc Vec 5 V Input Low Voltage E2 E1 E0 WC Input High Voltage E2 E1 E0 SCL SDA WC Output Low Voltage loL 3 mA Vcc 5 V 2 13 25 M24256 B M24128 B Table 16 DC Characteristics M24xxx BV SCL SDA device in Stand by mode Voc 2 7V fo 400KHz rise fall time lt 30ns Stand by Supply Current Vin Vss or Voc Vcc 2 7 V Input Low Voltage SCL SDA Input Low Voltage z E2 E1 E0 WC 0 3 Input High Voltage 0 7Voc E2 E1 E0 SCL SDA WC Vin Table 17 DC Characteristics M24xxx BW Test Condition Symbol in addition to those in Table 9 lu Input Leakage Current Vin Vss or Vec SCL SDA device in Stand by mode lcc Supply Current Voc 2 5V fo
18. o 3 6V Package BN PDIP8 MN SO8 150 mil width MW SO8 200 mil width DW TSSOP8 169 mil width Temperature Range 6 40 to 85 C Option T Tape amp Reel Packing Note 1 Available only on request by preference please use MN SO8 150 mil width package instead 2 Available for the M24256 B only 3 Available for the M24128 B only 4 M24256 B and M24256 BW bearing the process letter V in the package marking and M24128 B and M24128 BW bearing the process letter B in the package marking on the top side of the package on the right side guarantee more than 1 million Erase Write cycle endurance For more information about these devices and their device identification please contact your nearest ST sales office and ask for the Product Change Notice For a list of available options speed package device please contact your nearest ST Sales Of etc or for further information on any aspect of this fice 2 23 25 M24256 B M24128 B REVISION HISTORY Table 23 Document Revision History Date Rev Description of Revision 28 Dec 1999 TSSOP8 package added E2 E1 EO must be tied to Vcc or Vss er Low Pass Filter Time Constant changed to Glitch Filter 22 Nov 2000 V voltage range added V voltage range changed to 2 5V to 3 6V 30 Jan 2001 24 Lead Soldering Temperature in the Absolute Maximum Ratings table amended Write Cycle Polling Flow Chart using ACK illustration updated SO8 w
19. ompanying data bytes are not acknowledged as shown in Figure 6 Each data byte in the memory has a 16 bit two byte wide address The Most Significant Byte Ta ble 3 is sent first followed by the Least Significant Byte Table 4 Bits b15 to bO form the address of the byte in memory When the bus master generates a Stop condition immediately after the Ack bit in the 10 bit time 6 25 NO ACK DEV SEL BYTE ADDR BYTE ADDR DATA IN R W K NO ACK ACK ACK AC DEV SEL BYTE ADDR BYTE ADDR DATA IN 1 DATA IN 2 L AI01120C slot either at the end of a Byte Write or a Page Write the internal memory Write cycle is triggered A Stop condition at any other time slot does not trigger the internal Write cycle During the internal Write cycle Serial Data SDA is disabled internally and the device does not re spond to any requests Byte Write After the Device Select code and the address bytes the bus master sends one data byte If the addressed location is Write protected by Write Control WC being driven High the device replies with NoAck and the location is not modified If in stead the addressed location is not Write protect ed the device replies with Ack The bus master terminates the transfer by generating a Stop con dition as shown in Figure 7 Page Write The Page Write mode allows up to 64 bytes to be written in a single Write cycle provided that they are all located in the same ro
20. w in the memory that is the most significant memory address bits ky b14 b6 for M24256 B and b13 b6 for M24128 B are the same If more bytes are sent than will fit up to the end of the row a condition known as roll over occurs This should be avoided as data starts to become overwritten in an implementation dependent way The bus master sends from 1 to 64 bytes of data each of which is acknowledged by the device if M24256 B M24128 B Write Control WC is Low If Write Control WC is High the contents of the addressed memory loca tion are not modified and each data byte is fol lowed by a NoAck After each byte is transferred the internal byte address counter the 6 least sig nificant address bits only is incremented The transfer is terminated by the bus master generat ing a Stop condition Figure 7 Write Mode Sequences with WC 0 data write enabled ACK BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN k T R W N PAGE WRITE fe p R W N WC cont d PAGE WRITE A DATA INN cont d d ACK ACK AI01106C 2 7 25 M24256 B M24128 B Figure 8 Write Cycle Polling Flowchart using ACK WRITE Cycle in Progress START Condition DEVICE SELECT with RW 0 ACK Returned First byte of instruction YES with RW 0 already gt decoded by the device Next Operation is Addressing the Memory Send Address ReSTART and Receive ACK DATA for the WRITE
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ST M24256 B M24128 B handbook