ST M24128-BW M24128-BR M24256-BW M24256-BR handbook
Contents
1. STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 2 25 252. Each one is given a unique 3 bit code on the Chip Enable E0 E1 E2 inputs When the Device Select Code is received the de vice only responds if the Chip Enable Address is the same as the value on the Chip Enable E0 E1 E2 inputs The 8 bit is the Read Write bit RW This bit is set to 1 for Read and 0 for Write operations If a match occurs on the Device Select code the corresponding device gives an acknowledgment on Serial Data SDA during the 9 bit time If the device does not match the Device Select code it deselects itself from the bus and goes into Stand by mode Mode RW bit WC Bytes Initial Sequence Current Address Read 1 X 1 START Device Select RW 1 0 X START Device Select RW 0 Address Random Address Read 1 1 X reSTART Device Select RW 1 Sequential Read 1 X gt 1 Similar to Current or Random Address Read Byte Write 0 Vu 1 START Device Select RW 0 Page Write 0 Vi lt 64 START Device Select RW 0 Note 1 X V y or Vic Y 7 25 M24128 BW M24128 BR M24256 BW M24256 BR Figure 6 Write Mode Sequences with WC 1 data write inhibited Ec a T R W kr 09 STOP Write Operations Following a Start condition the bus master sends a Device Select Code with the R W bit RW reset to 0 The device acknowledges this as shown in Figure 7 and waits for two address bytes The de vice responds to each address byte with an ac knowl
3. Plastic Small Outline 150 mils body width Package Mechanical Data mm inches Symp Typ Min Max Typ Min Max A 1 35 1 75 0 053 0 069 A1 0 10 0 25 0 004 0 010 C 0 19 0 25 0 007 0 010 e 0 050 H 5 80 6 20 0 228 0 244 h 0 25 0 50 0 010 0 020 L 0 40 0 90 0 016 0 035 a 0 8 0 8 N 8 8 cP 0 10 0 004 2 20 25 M24128 BW M24128 BR M24256 BW M24256 BR Figure 14 SO8 wide 8 lead Plastic Small Outline 200 mils body width Package Outline Note Drawing is not to scale Table 18 SO8 wide 8 lead Plastic Small Outline 200 mils body width Package Mechanical Data mm inches Symb Typ Min Max Typ Min Max A 2 03 0 080 A1 0 10 0 25 0 004 0 010 mM OJO U o io o o a o lla a o oO o 00 o p po A o p po 00 5 20 5 40 0 205 0 213 1 27 0 050 H 7 70 8 10 0 303 0 319 L 0 50 0 80 0 020 0 031 0 10 0 10 8 8 CP 0 10 0 004 2 21 25 M24128 BW M24128 BR M24256 BW M24256 BR Figure 15 TSSOP8 8 lead Thin Shrink Small Outline Package Outline Note Drawing is not to scale TSSOP8AM Table 19 TSSOP8 8 lead Thin Shrink Small Outline Package Mechanical Data mm inches Zame Typ Min Max Typ Min Max A 0 0472 Al 0 0020 0 0059 A2 0 0315 0 0413 b 0 0075 0 0118 c 0 0035 0
4. To make use of this a polling sequence can be bus master goes back to Step 1 If the device used by the bus master has terminated the internal Write cycle it The sequence as shown in Figure 8 is responds with an Ack indicating that the device is ready to receive the second part of the instruction the first byte of this instruction having been sent during Step 1 x 10 25 M24128 BW M24128 BR M24256 BW M24256 BR Figure 9 Read Mode Sequences CURRENT ADDRESS RW START RANDOM ADDRESS READ RW START SEQUENTIAL CURRENT START SEQUENTIAL RANDOM RW START ACK NO ACK 1 DATA OUT N i 1 STOP STOP ija i a DEV SEL BYTE ADDR BYTE ADDR if DEV SEL DATA OUT E ir DEV SEL DATA OUT 1 READ ACK NO ACK MENE READ NO ACK RW START STOP NO ACK qr DATA OUT N daa mk STOP e i E E i DEV SEL BYTE ADDR BYTE ADDR i DEV SEL DATA OUT 1 READ RW START Al01105C Note 1 The seven most significant bits of the Device Select Code of a Random Read in the 1 and 4th bytes must be identical Read Operations Read operations are performed independently of the state of the Write Control WC signal After the successful completion of a Read opera tion the device s internal address counter is incre mented by one to point to the next byte address Random Address Read A dummy Write is first performed to load the ad dress into this ad
5. changed 16 Apr 2004 5 0 e ed Soldering temperature information clarified for ROHS compliant devices M24xxx B M24xxx BV and M24xxx BS removed from the datasheet Product List summary table added Power On Reset paragraph updated 13 Jun 2005 6 0 Figure 4 Maximum RP Value versus Bus Parasitic Capacitance C for an I2C Bus updated ZL and ZH definition changed Icc and Icc1 updated in Table 12 DC Characteristics M24128 BW M24256 BW Device Grade information further clarified to Table 20 Ordering Information Scheme 24 25 ky M24128 BW M24128 BR M24256 BW M24256 BR Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners O 2005 STMicroelectronics All rights reserved
6. input signals are used to set the value that is to be looked for on the three least significant bits b3 b2 b1 of the 7 bit Device Select Code These inputs must be tied to Vcc or Vss to establish the Device Select Code When not connected left floating these in puts are read as Low 0 0 0 Write Control WC This input signal is useful for protecting the entire contents of the memory from inadvertent write operations Write opera tions are disabled to the entire memory array when Write Control WC is driven High When uncon nected the signal is internally read as Vir and Write operations are allowed When Write Control WC is driven High Device Select and Address bytes are acknowledged Data bytes are not acknowledged Figure 4 Maximum Rp Value versus Bus Parasitic Capacitance C for an 12C Bus Vcc 20 S 16 2 o Rp gt S 12 a s am Eb MASTER E fc 100kHz SC x oO 4 fc 400kHz c 1 10 100 1000 C pF Al01665b ky 5 25 M24128 BW M24128 BR M24256 BW M24256 BR Figure 5 12C Bus Protocol a AAA ie SDA SDA gt START STOP i Input Change KA Condition Condition SCL E 1 2 3 7 8 9 START Condition SCL 1 2 3 7 8 9 SDA se XA Ack STOP Condition Al00792B Table 3 Device Select Code Device Type Identifier Chip Enable Address RW b7 b6 b5 b4 b3 b2 b1 b0 Device Sel
7. lead frame Package Mechanical Data 19 Figure 13 SO8 narrow 8 lead Plastic Small Outline 150 mils body width Package Outline 20 Table 17 SO8 narrow 8 lead Plastic Small Outline 150 mils body width Package Mechanical Data 20 Figure 14 SO8 wide 8 lead Plastic Small Outline 200 mils body width Package Outline 21 Table 18 SO8 wide 8 lead Plastic Small Outline 200 mils body width Package Mechanical Data 21 Figure 15 TSSOP8 8 lead Thin Shrink Small Outline Package Outline 22 Table 19 TSSOP8 8 lead Thin Shrink Small Outline Package Mechanical Data 22 PART NUMBERING vota O he areata ee a te a eae aa 23 Table 20 Ordering Information Scheme a 23 REVISION HISTORY ii see ee ee ee ae ee eee ee eee A 24 Table 21 Document Revision History 0 0 0 cee eee 24 Y 3 25 M24128 BW M24128 BR M24256 BW M24256 BR SUMMARY DESCRIPTION These IZC compatible electrically erasable pro grammable memory EEPROM devices are orga nized as 32K x 8 bits M24256 BW and M24256 BR and 16K x 8 bits M24128 BW and M24128 BR Figure 2 Logic Diagram Vcc E0 E2 SDA M24256 B SCL M24128 B WC Vss Al02809 Table 2 Signal Names E0 E1 E2 Chip Enable SDA Serial Data SCL Serial Clock WC Write Control Vcc Supply Voltage Vss Ground IZC uses a two wire serial interface comprising a bi directional dat
8. the ST ECOPACK 7191395 specification and the European directive on Restrictions on Hazardous Substances RoHS 2002 95 EU 2 AEC Q100 002 compliant with JEDEC Std JESD22 A114A C1 100pF R1 15000 R2 500Q Y 13 25 M24128 BW M24128 BR M24256 BW M24256 BR DC AND AC PARAMETERS This section summarizes the operating and mea surement conditions and the DC and AC charac teristics of the device The parameters in the DC and AC Characteristic tables that follow are de rived from tests performed under the Measure ment Conditions summarized in the relevant tables Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame ters Table 8 Operating Conditions M24128 BW M24256 BW Symbol Parameter Min Max Unit Voc Supply Voltage 2 5 5 5 V Ta Ambient Operating Temperature 40 85 C Table 9 Operating Conditions M24128 BR M24256 BR Symbol Parameter Min Max Unit Vec Supply Voltage 1 8 5 5 V Ta Ambient Operating Temperature 40 85 C Table 10 AC Measurement Conditions Symbol Parameter Min Max Unit CL Load Capacitance 100 pF Input Rise and Fall Times 50 ns Input Levels 0 2Vcc to 0 8Vcc V Input and Output Timing Reference Levels 0 3Vcc to 0 7Vcc V Figure 10 AC Measurement I O Waveform Input Levels 0 8Vcc 0 2Vcc Input and Output Timing Reference Levels
9. the device continues to output data from memory address 00h 12 25 Acknowledge in Read Mode For all Read commands the device waits after each byte read for an acknowledgment during the 9 bit time If the bus master does not drive Serial Data SDA Low during this time the device termi nates the data transfer and switches to its Stand by mode INITIAL DELIVERY STATE The device is delivered with all the memory array bits set to 1 each byte contains FFh x M24128 BW M24128 BR M24256 BW M24256 BR MAXIMUM RATING Stressing the device outside the ratings listed in Table 7 may cause permanent damage to the de vice These are stress ratings only and operation of the device at these or any other conditions out side those indicated in the Operating sections of Table 7 Absolute Maximum Ratings this specification is not implied Exposure to Ab solute Maximum Rating conditions for extended periods may affect device reliability Refer also to the STMicroelectronics SURE Program and other relevant quality documents Symbol Parameter Min Max Unit TA Ambient Operating Temperature 125 C TsTG Storage Temperature 150 26 TLEAD Lead Temperature during Soldering See note C Vio Input or Output range 6 5 V Vec Supply Voltage 6 5 V VESD Electrostatic Discharge Voltage Human Body model 3000 V Note 1 Compliant with JEDEC Std J STD 020C for small body Sn Pb or Pb assembly
10. 0079 CP 0 0039 D 0 1142 0 1220 e E 0 2441 0 2598 E1 0 1693 0 1772 L 0 0177 0 0295 L1 a 0 8 22 25 2 PART NUMBERING Table 20 Ordering Information Scheme Example Device Type M24128 BW M24128 BR M24256 BW M24256 BR M24256 M24 IC serial access EEPROM Device Function 256 256 Kbit 32K x 8 128 128 Kbit 16K x 8 Operating Voltage W MN 6 W3 Voc 2 5 to 5 5V R Voc 1 8 to 5 5V Package BN PDIP8 MN SO8 150 mil width MW SO8 200 mil width DW TSSOP8 169 mil width Device Grade 6 Industrial temperature range 40 to 85 C Device tested with standard test flow Option blank Standard Packing T Tape and Reel Packing Plating Technology T P blank Standard SnPb plating P or G Lead Free and RoHS compliant For a list of available options speed package etc or for further information on any aspect of this device please contact your nearest ST Sales Office Y 23 25 M24128 BW M24128 BR M24256 BW M24256 BR REVISION HISTORY Table 21 Document Revision History Date Rev Description of Revision 28 Dec 1999 2 1 TSSOP8 package added E2 E1 EO must be tied to Vcc or Vss 24 Feb 2000 2 2 ow Pass Filter Time Constant changed to Glitch Filter 22 Nov 2000 2 3 V voltage range added V voltage range changed to 2 5V to 3 6V 30 Jan 2001 24 Lead Soldering Temperatu
11. Al00825B 14 25 2 Table 11 Input Parameters M24128 BW M24128 BR M24256 BW M24256 BR Symbol Parameter1 2 Test Condition Min Max Unit Cin Input Capacitance SDA 8 pF Cin Input Capacitance other pins 6 pF Zi Vin lt 0 3 Voc 30 kQ Input Impedance WC Zu Vin gt 0 7Vcc 500 kQ Pulse width ignored tus Input Filter on SCL and SDA Single glitch no m Note 1 TA 25 C f 400kHz 2 Sampled only not 100 tested Table 12 DC Characteristics M24128 BW M24256 BW Y Symbol Parameter in sddltionto tiese alls 8 EOS Mass ij Unit lu Input Leakage Current Vin Vss or Vcc UN 2 uA SCL SDA device in Stand by mode ILo Output Leakage Current Vout Vss or Vcc SDA in Hi Z p_i 2 yA Voc 2 5V f 400kHz rise fall time lt 30ns 1 mA loc Supply Current Voc 5V f 400kHz rise fall time lt 30ns 2 mA Vin Vss or Vcc Voc 2 5V 2 uA lcc1 Stand by Supply Current TE EEES E T T Vi Input Low Voltage SCL SDA 0 3Vec V MEA Voce v VoL Output Low Voltage lo 2 1 mA Vec 2 5 V 0 4 V Table 13 DC Characteristics M24128 BR M24256 BR Symbol Parameter in ad PM larva a 9 Min Max Unit lu Input Leakage Current Vin Vss or Vcc 2 uA SCL SDA device in Stand by mode llo Output Leakage Current Vout Vss or Vcc SDA in Hi Z 2 yA lcc Supply Current Voc 1 8V fe 100kHz rise fall time lt 30ns 0 8 mA lcc1 Stan
12. O O M24128 BRBN 0 0 571 M24128 BW M24128 BR M24256 BW M24256 BR 256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable Lines FEATURES SUMMARY Compatible with 12C Extended Addressing m Two Wire IZC Serial Interface Supports 400kHz Protocol m Single Supply Voltage 2 5 to 5 5V for M24128 BW M24256 BW 1 8 to 5 5V for M24128 BR M24256 BR Hardware Write Control BYTE and PAGE WRITE up to 64 Bytes Self Timed Programming Cycle Automatic Address Incrementing Enhanced ESD Latch Up Protection More than 1 Million Erase Write Cycles More than 40 Year Data Retention Table 1 Product List Figure 1 Packages RANDOM and SEQUENTIAL READ Modes Part Number M24128 BW Reference 128 Kbits M24128 BR M24256 BW M24256 BR 256 Kbits June 2005 8 1 PDIP8 BN SO8 MN 150 mil width we 1 SO8 MW 200 mil width cS N TSSOP8 DW 169 mil width e di 1 25 M24128 BW M24128 BR M24256 BW M24256 BR TABLE OF CONTENTS FEATURES SUMMARY 20500 sae eee se A A ee Ae 1 rable Product List ait ssa Sb khan A e Rete A 1 Figure 1 Packages comia tee Sy eh a O a Pe ee ee ek 1 Figure 2 Logic Diagram cid a ee ee a A 4 Table 2 Signal Names 00 ccc e 4 Power On Reset 02 6 ia sale Sie ee Pk ee a eh eed 4 Figure 3 DIP SO and TSSOP Connections ees 4 SIGNAL DESCRIPTION jcc a
13. a line and a clock line The devic es carry a built in 4 bit Device Type Identifier code 1010 in accordance with the I C bus definition The device behaves as a slave in the IZC protocol with all memory operations synchronized by the serial clock Read and Write operations are initiat ed by a Start condition generated by the bus mas 4 25 ter The Start condition is followed by a Device Select Code and Read Write bit RW as de scribed in Table 3 terminated by an acknowl edge bit When writing data to the memory the device in serts an acknowledge bit during the 9 bit time following the bus master s 8 bit transmission When data is read by the bus master the bus master acknowledges the receipt of the data byte in the same way Data transfers are terminated by a Stop condition after an Ack for Write and after a NoAck for Read Power On Reset In order to prevent inadvertent Write operations during Power Up a Power On Reset POR circuit is implemented At Power Up the device will not respond to any in struction until Vcc has reached the POR threshold voltage this threshold is lower than the Vcc mini mum operating voltage defined in Table 8 and Ta ble 9 In the same way as soon as Vcc drops from the normal operating voltage below the POR threshold voltage all the operations are disabled and the device will not respond to any instruction Prior to selecting and issuing instructions to the memory a valid
14. and stable Vcc voltage must be applied This voltage must remain stable and valid until the end of the transmission of the instruction and for a Write instruction until the completion of the internal write cycle tw Figure 3 DIP SO and TSSOP Connections M24256 B M24128 B Al02810B Note See PACKAGE MECHANICAL section for package dimen sions and how to identify pin 1 2 M24128 BW M24128 BR M24256 BW M24256 BR SIGNAL DESCRIPTION Serial Clock SCL This input signal is used to strobe all data in and out of the device In applica tions where this signal is used by slave devices to synchronize the bus to a slower clock the bus master must have an open drain output and a pull up resistor must be connected from Serial Clock SCL to Vcc Figure 4 indicates how the value of the pull up resistor can be calculated In most applications though this method of synchro nization is not employed and so the pull up resis tor is not necessary provided that the bus master has a push pull rather than open drain output Serial Data SDA This bi directional signal is used to transfer data in or out of the device It is an open drain output that may be wire OR ed with other open drain or open collector signals on the bus A pull up resistor must be connected from Se rial Data SDA to Vcc Figure 4 indicates how the value of the pull up resistor can be calculated Chip Enable E0 E1 E2 These
15. d by Supply Current V Vss or Vcc Vec 1 8 V 1 yA Input Low Voltage SCL SDA 0 3 Vec V Vi Input Low Voltage 0 5 v E2 E1 E0 WC Vin athe EO SCL SDA WC a V VoL Output Low Voltage 0 2 V 15 25 M24128 BW M24128 BR M24256 BW M24256 BR Table 14 AC Characteristics M24128 BW M24256 BW Test conditions specified in Table 8 Symbol AM Parameter Min Max Unit fc Clock Frequency kHz toHoL Clock Pulse Width High ns teLcH Clock Pulse Width Low ns tcHicH2 Clock Rise Time ns toxcx tsu DAT Data In Set Up Time ns teLox tHD DAT Data In Hold Time ns tcLax DH Data Out Hold Time ns ii Stop Condition and Next Start 1300 nS tw twR Write Time 5 ms Note 1 For a reSTART condition or following a Write cycle 2 Sampled only not 100 tested 3 To avoid spurious START and STOP conditions a minimum delay is placed between SCL 1 and the falling or rising edge of SDA 16 25 x M24128 BW M24128 BR M24256 BW M24256 BR Table 15 AC Characteristics M24128 BR M24256 BR Test conditions specified in Table 9 Symbol AM Parameter Min Max Unit fc Clock Frequency kHz toHoL Clock Pulse Width High ns teLcH Clock Pulse Width Low ns tcHicH2 Clock Rise Time ns toxcx tsu DAT Data In Set Up Time ns teLox tHD DAT Data In Hold Time ns tcLax DH Data Out Hold Time ns ii Stop Condition and Next Start 1300 e tw twR Write Time 10 m
16. dress counter as shown in Fig ure 9 but without sending a Stop condition Then the bus master sends another Start condition and repeats the Device Select Code with the RW bit set to 1 The device acknowledges this and out ky puts the contents of the addressed byte The bus master must not acknowledge the byte and termi nates the transfer with a Stop condition Current Address Read For the Current Address Read operation following a Start condition the bus master only sends a De vice Select Code with the R W bit set to 1 The de vice acknowledges this and outputs the byte addressed by the internal address counter The counter is then incremented The bus master ter minates the transfer with a Stop condition as shown in Figure 9 without acknowledging the byte 11 25 M24128 BW M24128 BR M24256 BW M24256 BR Sequential Read This operation can be used after a Current Ad dress Read or a Random Address Read The bus master does acknowledge the data byte output and sends additional clock pulses so that the de vice continues to output the next byte in sequence To terminate the stream of bytes the bus master must not acknowledge the last byte and must generate a Stop condition as shown in Figure 9 The output data comes from consecutive address es with the internal address counter automatically incremented after each byte output After the last memory address the address counter rolls over and
17. ect Code 1 0 1 0 E2 E1 E0 RW Note 1 The most significant bit b7 is sent first 2 E0 E1 and E2 are compared against the respective external pins on the memory device Table 4 Most Significant Byte Table 5 Least Significant Byte b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 bO 6 25 ky M24128 BW M24128 BR M24256 BW M24256 BR DEVICE OPERATION The device supports the IZC protocol This is sum marized in Figure 5 Any device that sends data on to the bus is defined to be a transmitter and any device that reads the data to be a receiver The device that controls the data transfer is known as the bus master and the other as the slave de vice A data transfer can only be initiated by the bus master which will also provide the serial clock for synchronization The M24xxx B device is al ways a slave in all communication Start Condition Start is identified by a falling edge of Serial Data SDA while Serial Clock SCL is stable in the High state A Start condition must precede any data transfer command The device continuously monitors except during a Write cycle Serial Data SDA and Serial Clock SCL for a Start condition and will not respond unless one is given Stop Condition Stop is identified by a rising edge of Serial Data SDA while Serial Clock SCL is stable and driv en High A Stop condition terminates communica tion b
18. edge bit and then waits for the data byte Writing to the memory may be inhibited if Write Control WC is driven High Any Write instruction with Write Control WC driven High during a pe riod of time from the Start condition until the end of the two address bytes will not modify the memory contents and the accompanying data bytes are not acknowledged as shown in Figure 6 Each data byte in the memory has a 16 bit two byte wide address The Most Significant Byte Ta ble 4 is sent first followed by the Least Signifi cant Byte Table 5 Bits b15 to b0 form the address of the byte in memory 8 25 BYTE WRITE i DEV SEL BYTE ADDR BYTE ADDR DATA IN i K NO ACK ACK ACK AC e i DEV SEL BYTE ADDR BYTE ADDR DATA IN 1 DATA IN 2 L PAGE WRITE E T R W Er o WC cont d NO ACK NO ACK 1 PAGE WRITE DATAINN l cont d za Al01120C When the bus master generates a Stop condition immediately after the Ack bit in the 10 bit time slot either at the end of a Byte Write or a Page Write the internal memory Write cycle is triggered A Stop condition at any other time slot does not trigger the internal Write cycle After the Stop condition the delay tw and the suc cessful completion of a Write operation the de vice s internal address counter is incremented automatically to point to the next byte address af ter the last one that was modified During the internal Write cycle Serial Data SDA is d
19. ee 11 Read Operations ss cee o ee Ble ee eae ee te eee 11 Random Address Read cocoa Seas ee ee eee ee eG ees bee elias Sea 11 Current Address Read vivio ai ee ed A ee ee 11 Sequential Reads 0 o a a ee ee eee eet ee eee eee ee 12 Acknowledge in Read Mode 00 cece cece eee eee a 12 INITIAL DELIVERY STATE a cee ie ee Sl eee ed ee ae 12 MAXIMUM RATING 0 00 Bee ee ee eee ee ee ee eee a 13 Table 7 Absolute Maximum RatingS 0 0 00 cee ete eee 13 2 25 ISTA M24128 BW M24128 BR M24256 BW M24256 BR DCEANDAC PARAMETERS t esca a E a a i is 14 Table 8 Operating Conditions M24128 BW M24256 BW ooococcccccoc eee 14 Table 9 Operating Conditions M24128 BR M24256 BR 000 cee eee eee eee 14 Table 10 AC Measurement Conditions aa 14 Figure 10 AC Measurement I O Waveform a 14 Table 11 Input Parameters nanana naaa eee 15 Table 12 DC Characteristics M24128 BW M24256 BW 0 04 15 Table 13 DC Characteristics M24128 BR M24256 BR 2 2 15 Table 14 AC Characteristics M24128 BW M24256 BW a a 44 16 Table 15 AC Characteristics M24128 BR M24256 BR 04 aa 17 Figure 11 AC Waveforms ai ra mensie AAT AE TR EEE A AE A E AEE EA a pE 18 PACKAGE MECHANICAL aea na e a a o aja El tate a E a at a a a 19 Figure 12 PDIP8 8 pin Plastic DIP 0 25mm lead frame Package Outline 19 Table 16 PDIP8 8 pin Plastic DIP 0 25mm
20. etween the device and the bus master A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand by mode A Stop condition at the end of a Write command triggers the internal EE PROM Write cycle Acknowledge Bit ACK The acknowledge bit is used to indicate a success ful byte transfer The bus transmitter whether it be bus master or slave device releases Serial Data SDA after sending eight bits of data During the 9th clock pulse period the receiver pulls Serial Table 6 Operating Modes Data SDA Low to acknowledge the receipt of the eight data bits Data Input During data input the device samples Serial Data SDA on the rising edge of Serial Clock SCL For correct device operation Serial Data SDA must be stable during the rising edge of Serial Clock SCL and the Serial Data SDA signal must change only when Serial Clock SCL is driv en Low Memory Addressing To start communication between the bus master and the slave device the bus master must initiate a Start condition Following this the bus master sends the Device Select Code shown in Table 3 on Serial Data SDA most significant bit first The Device Select Code consists of a 4 bit Device Type Identifier and a 3 bit Chip Enable Address E2 E1 E0 To address the memory array the 4 bit Device Type Identifier is 1010b Up to eight memory devices can be connected on a single 12C bus
21. isabled internally and the device does not re spond to any requests Byte Write After the Device Select code and the address bytes the bus master sends one data byte If the addressed location is Write protected by Write Control WC being driven High the device replies br M24128 BW M24128 BR M24256 BW M24256 BR with NoAck and the location is not modified If in stead the addressed location is not Write protect ed the device replies with Ack The bus master terminates the transfer by generating a Stop con dition as shown in Figure 7 Page Write The Page Write mode allows up to 64 bytes to be written in a single Write cycle provided that they are all located in the same row in the memory that is the most significant memory address bits b15 b6 are the same If more bytes are sent than will fit up to the end of the row a condition known as roll over occurs This should be avoided as data starts to become overwritten in an implemen tation dependent way The bus master sends from 1 to 64 bytes of data each of which_is acknowledged by the device if Write Control WC is Low If Write Control WC is High the contents of the addressed memory loca tion are not modified and each data byte is fol lowed by a NoAck After each byte is transferred the internal byte address counter the 6 least sig nificant address bits only is incremented The transfer is terminated by the bus master generat i
22. ng a Stop condition Figure 7 Write Mode Sequences with WC 0 data write enabled ACK ACK ACK ACK BYTE WRITE i DEV SEL BYTE ADDR BYTE ADDR DATA IN tc T O R W o n WG ACK ACK ACK ACK a PAGE WRITE ll DEV SEL BYTE ADDR BYTE ADDR DATA IN 1 DATA IN 2 ald gt lt R W gt 2 WC cont d ACK ACK PAGE WRITE DATA INN cont d d a O E n Al01106C Y 9 25 M24128 BW M24128 BR M24256 BW M24256 BR Figure 8 Write Cycle Polling Flowchart using ACK WRITE Cycle in Progress START Condition DEVICE SELECT with RW 0 ACK Retumed First byte of instruction YES with RW 0 already gt decoded by the device Next Operation is Addressing the Memory Send Address and Receive ACK ReSTART v Continue the Continue the WRITE Operation Random READ Operation Al01847C Minimizing System Delays by Polling On ACK Initial condition a Write cycle is in progress During the internal Write cycle the device discon Step 1 the bus master issues a Start condition nects itself from the bus and writes a copy of the followed by a Device Select Code the first data from its internal latches to the memory cells byte of the new instruction The maximum Write time tw is shown in Table _ Step 2 if the device is busy with the internal 14 and Table 15 but the typical time is shorter Write cycle no Ack will be returned and the
23. o eee de eee eel oe eee Mg eee Me ee ja 5 Serial Clock SOL sacs a tas Shake ala da Gen Baa data Re a ea Ba eG 5 Serial Data SDA poanta ganja Tee G a Gah eee Sia Sa oes Pee Sa wae 5 Chip Enable E0 E1 E2 ani rpari ni eta a ete eens 5 Write Gontrol WO cesos a GST ak Adi A barge a a kn rad aA 5 Figure 4 Maximum RP Value versus Bus Parasitic Capacitance C for an I2C Bus 5 Figure 5 I2C Bus Protocol a 6 Table 3 Device Select Code 0 ae 6 Table 4 Most Significant Byte 0 aa 6 Table 5 Least Significant Byte 00 6 DEVICE OPERATION amer nn e a e a Oa ee ace 7 Start Condition 2 54 eo ak es ee at ere we Pe ee eee ee 7 Stop Condition Sirk eed eee ee oe ee ie ee ee a ia 7 Acknowledge Bit ACK ocio cairo ee inten beset a dada 7 Data Input teeta ae ee ee hae ee ae e E ta ee ge ee 7 Memory Addressing icsi serwi deee la a a ete 7 Table 6 Operating Modes 0 7 Figure 6 Write Mode Sequences with WC 1 data write inhibited o o o oo o 8 Write Operations 0306 4 23 saree ia a da lei 8 Byte WE A ko si A LS I Od E aad O o ay enih 8 Page Writes 2 30 Saga daa Lane AA ae ed e ea den da dar 9 Figure 7 Write Mode Sequences with WC 0 data write enabled o o oo ooooo o 9 Figure 8 Write Cycle Polling Flowchart using ACK a 10 Minimizing System Delays by Polling On ACK 204 aaa cece eee eee 10 Figure 9 Read Mode SequencesS 000 0c eee e
24. re in the Absolute Maximum Ratings table amended i Write Cycle Polling Flow Chart using ACK illustration updated SO8 wide package added References to PSDIP8 changed to PDIP8 and Package Mechanical data updated R voltage range added Package mechanical data updated for TSSOP8 and TSSOP14 01 Jun 2001 2 5 packages according to JEDEC MO 153 Document promoted from Preliminary Data to Full Data Sheet TSSOP14 package removed ias EN Absolute Max Ratings and DC characteristics updated for M24256 BV 09 Nov 2001 2 7 Specification of Test Condition for Leakage Currents in the DC Characteristics table improved 21 Mar 2002 2 8 1 million Erase Write cycle endurance for M24256 B and M24256 BW products with process letter V 18 Oct 2002 3 0 Document reformatted Parameters changed are 1 million Erase Write cycle endurance and 5 i ms write time for M24128 B and M24128 BW products with process letter B 20 Nov 2002 31 Superfluous and incorrectly present 100kHz AC Characteristics table for M24256 BR removed 02 Jun 2003 3 2 Initial delivery state specified R and S ranges are no longer Preliminary Data Package f mechanical data for unavailable package removed Table of contents and Pb free options added Minor wording changes in Summary 22 Oct 2003 4 0 Description Power On Reset Memory Addressing Write Operations Read Operations ViL min improved to 0 45V SO8W package added Absolute Maximum Ratings for Vio min and Vcc min
25. s Note 1 For a reSTART condition or following a Write cycle 2 Sampled only not 100 tested 3 To avoid spurious START and STOP conditions a minimum delay is placed between SCL 1 and the falling or rising edge of SDA Y 17 25 M24128 BW M24128 BR M24256 BW M24256 BR Figure 11 AC Waveforms SCL SDA In SCL SDA In SCL SDA Out 18 25 tCHCL tCLCH Ls tCHDX 1CLDX SDA tCHDH tDHDL START SDA gt Change STOP START Condition Input Condition Condition tCHDH e tw tCHDX STOP Write Cycle START Condition Condition Data Valid Al00795C lt M24128 BW M24128 BR M24256 BW M24256 BR PACKAGE MECHANICAL Figure 12 PDIP8 8 pin Plastic DIP 0 25mm lead frame Package Outline PDIP B Note Drawing is not to scale Table 16 PDIP8 8 pin Plastic DIP 0 25mm lead frame Package Mechanical Data inches may Min Max A 0 210 Al 0 015 A2 0 115 0 195 b 0 014 0 022 b2 0 045 0 070 0 008 0 014 D 0 355 0 400 0 300 0 325 E1 0 240 0 280 E 3 eA eB 0 430 L 3 30 2 92 3 81 0 130 0 115 0 150 L 19 25 M24128 BW M24128 BR M24256 BW M24256 BR Figure 13 SO8 narrow 8 lead Plastic Small Outline 150 mils body width Package Outline hx 45 e gt e SO a Note Drawing is not to scale Table 17 SO8 narrow 8 lead
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ST M24128 BW M24128 BR M24256 BW M24256 BR handbook