ST TDA7468 TWO BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR WITH BASS ALC SURROUND handbook
Contents
1. 8dB STEPS 8dB 16 24dB 32dB 40dB 1010 0 48dB 56dB VOLUME 2 8dB 16dB 0 sch a 2 2 2 o Oo 2 o A 24dB VOLUME 0 to 87dB Table 11 VOLUME setting 1 Volume 1dB step dB Volume1 8dB step dB Volume2 8dB step dB Target Volume dB 0 4 2 8 4 5 6 7 13 14 15 12 23 BED 2 3 4 S 6 7 E d TDA7468 Table 11 VOLUME setting 1 continua Target Volume dB 16 17 Volume1 1dB step dB Volume1 8dB step dB Volume2 8dB step dB 18 19 0 16 zi 2 3 4 5 6 7 0 24 4 2 8 4 5 6 7 0 732 1 2 3 4 5 6 7 0 40 1 2 3 4 5 6 7 Target Volume dB 56 57 0 4 2 8 4 5 6 7 Volume 1dB step dB Volume1 8dB step dB Volume2 8dB step dB 1 13 23 TDA7468 Table 11 VOLUME setting 1 continua 58 2 60 4 58 7 64 0 56 67 3 70 6 71 7 72 0 56 16 73 1 74 2 75 77 5 79 7 780 0 756 724 81 4 82 2 84 4 87 7 Table 12 VOLUME setting 2 Target Volume dB Volume1 1dB step dB 0 0 1 1 2 22. L 0 4 1 27 0 016 0 050 S 8 max OUTLINE AND MECHANICAL DATA SO 28 ci al d 21 23 TDA7468 10 REVISION HISTORY Table 16 Revision History Date Revision Description of Changes January 2004 1 First Issue EDOCS DMS June 2004 2 Changed the Style sheet in compliance to the new Corporate Technical Pubblications Design Guide March 2006 3 Updated figure 19 SO28 Mechanical Data amp Package Dimensions 30 Apr 2010 4 Updated title and added environmental compliance statement for package 22 23 d TDA7468 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third
3. Input Gain 2dB step Volume Control 1dB step Treble Control 2dB step 14 14 dB Bass Control 24 step 14 414 dB Mute Attenuation 86 dB 7 3 23 7468 ELECTRICAL CHARACTERISTICS refer to the test circuit Tamp 25 Vs 9V f 1KHz all controls flat OdB unless otherwise specified Symbol Parameter Test Condition Min Typ Max Unit SUPPLY Vs Supply Voltage 5 9 10 V 15 Supply Current 9 mA SVR Ripple Rejection 60 90 dB INPUT STAGE RiN Input Resistance 35 Clipping Level THD 0 3 2 SIN Input Separation 80 Ginmin Minimum Input Gain 1 Ginmax Maximum Input Gain Gstep Step Resolution Input Resistance 35 50 65 Gmic1 Mic Input Gain 1 14 dB Gmic2 Mic Input Gain 2 10 dB Gmica Mic Input Gain 6 dB Gmin4 Mic Input Gain 4 0 dB MiXmic Mixing Rate 50 K SURROUND Rin Input Resistance 35 50 65 KQ Ginmin Minimum Input Gain 1 0 1 dB Ginmax Maximum Input Gain 12 dB Inverting Gain Minimum Mixing Rate 0 96 Mixmax Maximum Mixing Rate 100 96 Crosstal Crosstalk of Mux Output to 10096 40 dB k IS Buffer Gain VOLUME CONTROL 1 Vol 1 Control Range 63 dB Vol 1 Max Attenuation 61 AgrEP1 Vol 1 Step Resolution 0 5 Match Matching CRANGE Vol 2 Control Range Avmax2 Vol 2 Max Attenuation 22 AsrEP2
4. ViL Input Low Voltage 1 V Input High Voltage 2 5 lin Input Current Vin 0 4V 5 Output Voltage lo 1 6mA 0 4 0 8 V 5 23 TDA7468 Figure 4 TEST CIRCUIT deis 9 8 deis deis deis pz Sprit 01 1 gpeg XIN ql8viHvA 9313411999 S3HO41V1 SNd 221 ssva deis deis gpz dee gpz urb gpg 0 Ott des gpeg 8 378381 30001 34001 EW KE 01 Q ER 9 9 apo IA deis apz n b 0 0 ueb ng 193788 c 6 23 TDA7468 3 APPLICATION SUGGESTIONS The first and the last stages are volume control blocks The control range is 0 to 63dB mute with 1dB step resolution for this first one 0 to 24dB mute with 8dB step resolution for the last one The very high resolution allows the implementation of systems free from any noisy acoustical effect The TDA7468D audioprocessor provides 2 bands tones control 3 1 Bass Stages The Bass cell has an internal resistor 44KQ typical Several filter types can be implemented connecting external components to the Bass IN and OUT pins The fig 5 refers to basic T Ty
5. address byte containing the TDA7468D address a subaddress bytes sequence of data byte acknowledge A stop condition P CHIP ADDRESS SUBADDRESS DATA 1 to DATA 1 MSB LSB MSB LSB MSB LSB ER EI D96AU420 ACK Acknowledge S Start Stop A Address B Auto Increment 6 EXAMPLES 6 1 No Incremental Bus The TDA7468D receives a start condition the correct chip address a subaddress with the B 0 no in cremental bus N data all these data concern the subaddress selected a stop condition CHIP ADDRESS SUBADDRESS DATA MSB LSB MSB LSB MSB LSB Esp s po e ros BATA ES D96AU421 6 2 Incremental Bus The TDA7468D receive a start conditions the correct chip address a subaddress with the B 1 incre mental bus now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from XXX1000 to XXX1111 of DATA are ignored The DATA 1 concern the subaddress sent and the DATA 2 concern the subaddress sent plus one in the loop etc and at the end it receivers the stop condition CHIP ADDRESS SUBADDRESS DATA 1 to DATAn MSB LSB MSB LSB MSB LSB D96AU422 Table 5 POWER ON RESET CONDITION MSB LSB 07 06 a 9 23 TDA7468 7 DATA BYTES Address HEX 10001000 Table 6 FUNCTION SELECTION First byte subaddress LSB SUBADDR
6. Figure 3 BLOCK DIAGRAM 3880 deis gpg We pz deis gpg pz CTOSSV8 17 1559 deis gpz YL deis ott 55 55 1 deis gpz yL 1 deis 0 y 1 gp9 deis 59 gpg deis n gpeg 95194934 3AVM d1VH OV ssva XIN 8 0 v8soLnve6d EA apo NN deis apz 010 ureb Jeng 199135 LAdNI XNN VYNI TNI LIN XIIN OIIN 2 23 TDA7468 Table 2 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vs Operating Supply Voltage 10 5 V Tag 55 to 150 Table 3 THERMAL DATA Symbol Parameter Value Unit Rth Lon Thermal Resistance Junction pins 85 C W Table 4 QUICK REFERENCE DATA Symbol Parameter Min Typ Max Unit Vs Supply Voltage 5 9 10 V VcL Max input signal handling THD Total Harmonic Distortion V 1Vrms f 1KHz Total Harmonic Distortion V 0 1Vrms f 1KHz S N Signal to Noise Ratio Vout 1Vrms 048 Sc Channel Separation f 1KHz
7. 3 3 4 4 5 5 6 6 7 7 14 23 Volume1 8dB step dB Volume2 8dB step dB TDA7468 Table 12 VOLUME setting 2 continua Target Volume dB Volume1 1dB step dB Volume1 8dB step dB Volume2 8dB step dB 8 0 9 1 10 2 11 3 12 4 13 5 14 6 15 7 16 0 16 17 1 18 2 19 3 20 4 21 5 22 6 23 7 24 0 16 25 1 26 2 27 3 28 4 29 5 30 6 81 7 32 0 16 16 33 1 84 2 35 3 36 4 37 5 38 6 39 7 40 0 16 24 41 1 42 2 43 3 44 4 45 5 46 6 47 7 15 23 d TDA7468 Table 12 VOLUME setting 2 continua Target Volume dB Volume 1dB step dB Volume1 8dB step dB Volume2 8dB step dB 48 0 24 24 49 1 50 2 51 3 52 4 53 5 54 6 55 7 56 0 32 24 57 1 58 2 59 3 60 4 61 5 62 6 63 7 64 0 40 24 65 1 66 2 67 3 68 4 69 5 70 6 71 7 72 0 48 24 73 1 74 2 75 3 76 4 77 5 78 6 79 7 80 0 56 24 81 1 82 2 83 3 84 4 85 5 86 6 87 7 d 16 23 Table 13 TREBLE amp BASS SELECTION TDA7468 MSB 3 o Jg e S TREBLE 14dB 12dB 10dB 8dB 6dB 2 ojo o o 4dB 2dB mm 1448 12dB 10dB 8dB 6dB
8. 4dB 2dB o o hl sch Och Osch Olli Oil OCH OdB BASS 14dB o o 12dB 10 8dB 6dB 4dB 2dB 14dB 12dB 10dB 8dB 4dB O ME gt 7 When BASS is programmed the range 14dB OdB ALC is automatically switched to OFF LSB D5 04 03 02 01 MUTE ON OFF d 17 23 TDA7468 Table 15 BASS ALC LSB BASS ALC D7 ALC Mode OFF Release Current Circuit ON OFF Attack Time Resistor Threshold 700mVrms 485mVrms 170mVrms Attack Mode 0 MODE 2 Adaptive Figure 10 BASS ALC THD Figure 9 BASS ALC Threshold curve DOOAU1100 THD D99AU1101A Supply Voltage 9 0V Supply Voltage 9 0V 10 Frequency 60Hz Frequency 60Hz Bassfilter 60 2 284 boost Bassfilter 60 2 284 boost Internal release circuit ON Internal release ci
9. 57 TDA7468 TWO BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR WITH BASS ALC SURROUND 1 FEATURES a INPUT MULTIPLEXER 4 STEREO INPUTS SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES ONE STEREO OUTPUT BASS ALC TREBLE AND BASS CONTROL IN 2 0dB STEPS VOLUME CONTROL IN 1 0dB STEPS TWO SPEAKER ATTENUATORS TWO INDEPENDENT SPEAKER CONTROL IN 1 04 STEPS FOR BALANCE FACILITY INDEPENDENT MUTE FUNCTION ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS a EXTERNALLY ADJUSTABLE SURROUND 2 DESCRIPTION The TDA7468D is a volume tone bass and treble balance Left Right processor for quality audio Figure 2 PIN CONNECTION Top view Figure 1 Package SO28 Table 1 Order Codes Part Number Package TDA7468D SO28 TDA7468D13TR Tape amp Reel applications in Hi Fi systems Selectable input gain is provided Control of all the functions is accomplished by serial bus The AC signal setting is obtained by resistor net works and switches combined with operational amplifiers Thanks to the used BIPOLAR CMOS Technology Low Distortion Low Noise and DC stepping are obtained Vs MIC IN1 L IN2 L IN3 L INA L MUX L IS TREBLE L BASSI L BASSO OUT L DGND SCL 1 2 3 4 5 6 7 8 9 D99AU1057 April 2010 GND CREF IN1 R IN2 R INS INA R MUX R IS R TREBLE R BASSI R BASSO R OUT R ALC SDA Rev 4 1 23 TDA7468
10. ESS INPUT SELECT amp MIC INPUT GAIN SURROUND VOLUME LEFT VOLUME RIGHT X X gt nun ojojoj o oa k TREBLE amp BASS OUTPUT BASS ALC B 1 INCREMENTAL BUS ACTIVE B 0 NO INCREMENTAL BUS X INDIFFERENT 0 1 Table 7 INPUT SELECTION amp MIC MSB D7 D6 D5 D4 INPUT SELECT 0 0 0 LIE 1 0 IN1 IN2 HET wWpRE IN4 MUTE IN5 ON IN5 OFF MIC Gain 14dB Gain 6dB 0 0 1 Gain OdB OFF 10 23 d Table 8 INPUT GAIN SELECTION TDA7468 MSB LSB INPUT GAIN D7 D6 D5 D4 D3 D2 D1 DO 2dB STEPS 0 0 0 OdB 0 0 1 2dB 0 1 0 4dB 0 1 1 6dB 1 0 0 8dB 1 0 1 10 1 1 0 12dB 1 1 1 14dB GAIN 0 to 30dB Table 9 SURROUND MSB SURROUND SURROUND MODE 1 ON 0 OFF GAIN 0 0 0 1 1 0 1 1 1248 MIXING 1 0 1 non inverting 7596 1 1 0 non inverting 50 1 1 1 mute BUFFER GAIN 1 0 0 6dB d TDA7468 Table 10 VOLUME MSB D7 Jg LSB VOLUME D1 DO 14 STEPS 1dB 2dB 0 0 1 7dB 0
11. Vol 2 Step Resolution 7 Match2 Matching AvyMAx1 Vol 1 Vol 2 Max Attenuation AvMAX2 4 23 ky ELECTRICAL CHARACTERISTICS continua refer to the test circuit Tamp 25 Vs 9V f 1KHz all controls flat OdB unless otherwise TDA7468 specified Symbol Parameter Test Condition Min Typ Max Unit BASS CONTROL Gb Control Range Max Boost cut 12 0 14 0 16 0 BsrEP Step Resolution 1 2 3 dB Internal Feedback Resistance 33 44 55 BASS ALC CONTROL Attack Time Resistor 1 12 5 Attack Time Resistor 2 25 Attack Time Resistor 3 Attack Time Resistor 4 100 Thresh1 Threshold 1 Thresh2 Threshold 2 Thresh3 Threshold 3 Thresh4 Threshold 4 TREBLE CONTROL Gt Control Range Max Boost cut 13 0 414 0 15 0 dB Tstep Step Resolution 1 2 3 dB Rt Internal Resistance 25 KQ AUDIO OUTPUTS Clipping Level THD 0 3 2 5 Vrms RL Output Load Resistance 2 KQ DC Voltage Level 4 5 V GENERAL ENO Output Noise BW 20Hz to 20KHz 1 All gains OdB output muted flat 10 15 uV S N Signal to Noise Ratio All gains OdB Vo 1Vrms 100 dB Sc Channel Separation Left Right 90 dB d Distortion Ay 0 Vi 0 1Vims 0 1 96 Ay 0 1 0 01 K Sc Channel Separation left right 90 dB Total Tracking Error 0 1 dB BUS INPUT
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13. pe Bandpass Filter starting from the filter component values R1 internal and R2 C1 C2 external the centre frequency Fc the gain Av at max boost and the filter Q factor are computed as follows 2 m JR1 R2 C1 C2 R2 2 R2 C1 Ri C1 A V R2 1 R2 C2 Q _ 2 1 2 R2 1 2 C2 Viceversa once Fc and Rj internal value are fixed the external components values will be ed 2 Ayt 2 1 C1 Fo 1 0 3 2 The treble stage is a high pass filter whose time constant is fixed by an internal resistor 25 typical and an external capacitor connected between treble pins and ground 3 3 CREF The suggested 10uF reference capacitor CREF value be reduced to 4 7uF if the application requires faster power ON Figure 5 Ri internal IN OUT D95AUS13 d 7 23 TDA7468 4 BUS INTERFACE Data transmission from microprocessor to the TDA7468D and vice versa takes place through the 2 wires 2 BUS interface consisting of the two lines SDA and SCL pull up resistors to positive supply voltage must be connected 4 1 Data Validity As shown in fig 6 the data on the SDA line must be stable during the high period of the clock The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW 4 2 Start and Stop Conditions As shown in fig 7 a start condition i
14. rcuit ON Attack mode 12 5kohm mode2 adaptive 1 Attack mode 12 5kohm mode2 adaptive 1 Threshold Threshold2 IBI 0 1 Threshold3 5 8 5 5 B EA ER E Threshold4 5 0 01 Fim 0 1 0 001 0 1 1 VIN VRMS 0 01 0 1 1 Vin Vams 0 01 572 18 23 TDA7468 8 Figure 11 PINS IN1 L IN1 R IN2 L IN2 Figure 15 PINS BASSI L BASSI R IN3 L IN3 INA L 4 R IS IS R MIC Vs Ve 20 204A 45K GND 50K BASSO L BASSO R D99AU1096 GND Vref D99AU1092 Figure 16 PINS BASSO L BASSO R Figure 12 PINS OUT L OUT R IMUX L MUX R 9 Vs 20uA 20 45 100 GND BASSI L BASSI R D99AU1097 GND UR Figure 17 PIN ALC Figure 13 PINS TREBLE L TREBLE R Vs Vs 20uA 23K D99AU1098 GND D99AU1094 Figure 18 PIN CREF Vs Figure 14 PINS SCL SDA 20uA Vs 25K 25 GND D99AU1099 GND D99AU1095 19 23 TDA7468 9 PACKAGE MECHANICAL DATA In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade defi nitions and product status are available at www st com ECOPACK is an ST trademark d 20 23 TDA7468 Figure 19 5028 Mechanical Data amp Package Dimensions DIM A al b b1
15. s a HIGH to LOW transition of the SDA line while SCL is HIGH The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH 4 3 Byte Format Every byte transferred on the SDA line must contain 8 bits Each byte must be followed by an acknowledge bit The MSB is transferred first 4 4 Acknowledge The master uP puts a restive HIGH level on the SDA line during the acknowledge clock pulse see fig 4 The peripheral audio processor that acknowledges has to pull down LOW the SDA line during this clock pulse The audio processor which has been addressed has to generate an acknowledge after the reception of each byte otherwise the SDA line remains at the HIGH level during the ninth clock pulse time In this case the master transmitter can generate the STOP information in order to abort the transfer 4 5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor the can use a simpler transmission simply it waits one clock without checking the slave acknowledging and sends the new data This approach of course is less protected from misworking Figure 6 Data Validity on the 5 DATA LINE CHANGE STABLE DATA DATA VALID ALLOWED D99AU1031 1 SDA MSB EENEG ACKNOWLEDGMENT START D99AU1033 FROM RECEIVER d 8 23 TDA7468 5 SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises A start condition S
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ST TDA7468 TWO BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR WITH BASS ALC SURROUND handbook