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ATMEL TS68332 handbook

1. 16 78 MHz 20 97 MHz Number Symbol Parameter Min Max Min Max Unit F1 f Frequency of operation 32 768 kHz crystal 0 13 16 78 0 13 20 97 MHz 1 Clock period 59 6 47 7 ns 1A tEcyc ECLK period 476 381 a ns 1B eye External clock input period 59 6 47 7 ns 2 3 tow Clock pulse width 24 18 8 ns 2A 3A teow ECLK pulse width 236 183 ns 2B 3B External clock input high low time 29 8 23 8 ns 4 5 tort Clock rise and fall time 5 5 ns 4A 5A ta Rise and fall time All outputs except CLKOUT 8 8 ns 4B 5B Tus External clock rise and fall time 5 5 ns 6 Clock high to address FC SIZE valid 0 29 0 23 ns 7 MM address Data FC SIZE high 0 59 0 47 8 chHAZn Clock high to address FC SIZE RMC invalid 0 0 ns 9 lores Clock low to AS DS CS asserted 2 25 0 23 ns 9A ix AS to DS or CS asserted read 15 15 10 10 ns 9C bons Clock low to IFETCH IPIPE asserted 2 22 2 22 ns 11 Address FC SIZE valid to AS CS and DS 15 _ 10 _ m read asserted 12 Clock low to AS DS CS negated 2 29 2 23 ns 12A Tout Clock low to IFETCH IPIPE negated 2 22 2 22 ns 13 E to address FC SIZE invalid 15 _ 10 _ 14 tswa AS CS and DS read width asserted 100 80 ns 14A tswaw DS CS width asserted write 45 36 ns 14B ie and DS read width asserted fast write 40 _ 32 _ 25 15 tsn AS DS CS width negated 40 32
2. SSA 1N0y70 34X 1 1 8 NASQQA SSA 10N0 3z3344 251 X 19SQ 1dX8 Vss ADDR9 ADDR10 Vss ADDR13 Vss Vpp VsTBY ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 Vpp Vpp ADDR17 Vpp ADDR11 ADDR12 ADDR14 ADDR15 ADDR16 ADDR18 PQSO MISO PQS1 MOSI PQS2 SCK PQS3 PCS0 SS PQS4 PCS1 PQS5 PCS2 PQS6 PCS3 ISQ H9 33l OSQ 3dldl Qxa 1 50 SSA AIMEL 2118A HIREL 03 02 Applicable Documents MIL STD 883 Requirements General Design And Construction Terminal Connections Lead Material and Finish Package Electrical Characteristics AMEL This drawing describes the specific requirements for the microcontroller 68332 at 16 78 MHz and 20 97 MHz in compliance either with MIL STD 883 class B Atmel Grenoble standard 1 MIL STD 883 test methods and procedures for electronics 2 MIL I 38535 general specifications for microcircuits 3 DSCOC Drawing 5962 91501 The microcircuits are in accordance with the applicable document and as specified herein Depending on the package the terminal connections shall be as shown in Figure 2 and Figure
3. VCO LOCK VDD 512 clocks lt 14 clocks RESET Bus State Address and Control 2 3 4 Unknown Signals Thee stated Notes 1 Internal startup time 2 SSP read here 3 PC read here 4 First instruction fetched here System Integration The TS68332 system integration module SIM consists of five sudmodules that control Module the microcontroller unit MCU system start up initialization configuration and external bus with a minimum of external devices The fives submodules that make up the SIM shown in Figure 21 are as follows e System Configuration and Protection e Clock Synthesizer e Selects e External Bus Interface System Test System Configuration and The SIM module allows the user to control some features of system configuration by Protection Submodule writing bits in the Module Configuration Register This register also contains read only status bits that show the state of some of the SIM features This MCU is designed with the concept of providing maximum system safe guards Many of the functions that normally must be provided in external circuits are incorpo rated in this MCU The features provided in the system configuration and protection submodule are as follows System Configuration The module configuration register allows the user to configure the system according to the particular system requirements 2118A HIREL 03 02 Internal Bus Monitor Halt
4. 1568332 A18 Features Low power Operation Including Special STOP Mode Frequency 16 78 MHz at 5V 1096 Supply and 20 97 MHz at 5V x 5 Software Programmable Technology 1p High density Complementary Metal Oxide Semiconductor HCMOS Static Design Package 132 pin Ceramic Leaded Chip Carrier CERQUAD and 132 pin Ceramic Pin T Grid Array Modular Architecture in a Single Chip CPU 32 bit 6800 Family Upward Object code Compatible With The 68010 New Instructions For Controller Applications H 19 Intelligent 16 bit Timer 16 Independent Programmable Channels Any Channel Can Perform Any Time Function for Example Input Capture Output performance Compare Pulse Width Modulation etc hi Two timer Count Registers with 2 bit Programmable Prescalers 32 bit Integ rated Selectable Channel Priority Levels Reduced CPU Intervention M ntrol ler RISC like CPU Within the Two Serial I O Subsystems Enhanced 68HC11 type Serial Communications Interface SCI Universal Asynchronous Recover Transmitter UART with Parity PS 1968332 Enhanced 68HC11 type Serial Peripheral Interface With RAM Queue QSPI On chip Memory 2 Kbytes Standby RAM On chip Programmable Chip select Logic Up to 12 Signals for Memory and Peripheral Interface with I O Select System Failure Protection 68HC11 type Computer Operating Properly COP Watchdog Timer 68HC11 type Periodic
5. ns 16 Clock high to AS DS high impedance 59 47 ns 17 Tesi AS DS CS negated to R W negated 15 10 ns 18 1 Clock high to high 0 29 0 23 ns 20 Tobis Clock high to R W low 0 29 0 23 ns 21 R W asserted to AS CS asserted 15 10 ns 22 sux R W low to DS CS asserted write 70 54 ns 23 tcupo Clock high to data out valid 29 23 ns 14 1960332 mmm 2118A HIREL 03 02 Table 6 AC Timing and Vppsyy 5 0 10 for 16 78 MHz and 5 0 5 for 20 97 MHz Vas 0 Tc 55 C to 125 or 40 C to 85 C Continued 16 78 MHz 20 97 MHz Number Symbol Parameter Min Max Min Max Unit 24 m Re 7 to negating edge of AS CS fast 15 _ 10 _ 25 DS CS negated to data out invalid data out hold 15 10 ns 26 tbvsa Data out valid to DS CS asserted write 15 10 ns 27 Data in valid to clock low data setup 5 5 ns E tseLcL 22 setup time is ns 28 TM to DSACK 1 0 BERR HALT 0 80 0 60 s 29 tenia DS CS negated to data in invalid data in hold 0 0 ns 29A on DS CS negated to date in high impedance 55 48 ns 30 telp CLKOUT low to data in invalid fast cycle hold 15 10 2 ns 30A Loro CLKOUT low to data in high impedance 90 72 ns 31 toap DSACK 1 0 asserted to data in valid 5
6. 5 CL 2 AMEL 2118A HIREL 03 02 20 AMEL Figure 9 Fast Termination Read Cycle Timing Diagram S0 1 4 5 0 CLKOUT oe TXT DAT 2 ul we 1 568332 mem 2118A HIREL 03 02 TS68332 Figure 10 Fast Termination Write Cycle Timing Diagram CLKOUT pleer ADOR 23 0 FC 2 0 512115 al gl RN DATA 15 0 BKPT AMEL 2118A HIREL 03 02 AMEL Figure 11 Bus Arbitration Timing Diagram Active Bus Case 50 1 2 53 4 5 om XD 15 0 S RW 7 DSACK1 oO 22 568332 mem 2118 03 02 TS68332 Figure 12 Bus Arbitration Timing Diagram Idle Bus Case gt pe DATA 15 0 ET l T vil U Figure 13 Show Cycle Timing Diagram 50 541 542 543 50 1 2 ADOR 23 0 2 al al MCN 2 DATA 15 0 5 141 i SHOW CYCLE START OF EXTERNAL gt 3 Note Show cycles can stretch during S42 when bus accesses take longer than two cycles due to IMB module wait state insertion AMEL 2 2118A HIREL 03 02 Figure 14 Chip Select Timing Diagram 1 52 53 54 55 50 1 52 53 S4 5 CLKOUT lt gt oma Xs FC 2 0 mH 225 4 1 a DNE 4 Om 2 4 e ES EY DA
7. Commercial Atmel Temperature Frequency Part Number Norms Package Range Tc MHz Drawing Number TS68332VR16 Atmel Grenoble Standard PGS 132 40 85 16 78 Atmel Grenoble datasheet TS68332MR16 Atmel Grenoble Standard PGS 132 55 125 16 78 Atmel Grenoble datasheet TS68332VA16 Atmel Grenoble Standard CERQUAD 132 40 85 16 78 Atmel Grenoble datasheet TS68332MA16 Atmel Grenoble Standard CERQUAD 132 55 125 16 78 Atmel Grenoble datasheet TS68332VR20 Atmel Grenoble Standard PGS 132 40 85 20 97 Atmel Grenoble datasheet TS68332MR20 Atmel Grenoble Standard PGS 132 55 125 20 97 Atmel Grenoble datasheet TS68332VA20 Atmel Grenoble Standard CERQUAD 132 40 85 20 97 Atmel Grenoble datasheet TS68332MA20 Atmel Grenoble Standard CERQUAD 132 55 125 20 97 Atmel Grenoble datasheet 54 19560332 memme 2118A HIREL 03 02 TS 68332 M R B C 16 A Manufacturer s Prefix Speed MHz 16 16 MHz 20 20 MHz Screening level Standard B C MIL STD 883 class B DSCC DESCOx Mxx Lead finish 1 Tinned for PGA Temperature range M 55 125 C 40 85 0 70 C A CERQUAD 132 Hot solder dip Gulwing leads Note For availability of different versions contact your Atmel sales office AIMEL 2118A HIREL 03 02 7568332 55 AIMEL Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose CA 95131
8. Take Illegal Instruction Trap JMP JSR Jump Jump to Subroutine LEA LINK LPSTOP LSL LSR Load Effective Address Link and Allocate Low Power Stop Logical Shift Left and Right MOVE MOVE CCR MOVE SR MOVE USP MOVEA MOVEC MOVEM MOVEP MOVEQ MOVES MULS MULS L MULU MULU L Move Move Condition Code Register Move Status Register Move User Stack Pointer Move Address Move Control Register Move Multiple Registers Move Peripheral Move Quick Move Alternate Addree Space Signed Multiply Unsigned Multiply NBCD NEG NEGX NOP Negate Decimal with Extend Negate Negate with Extend No Operation OR ORI Logical Inclusive OR Logical Inclusive OR Immediate PEA Push Effective Address RESET ROL ROR ROXL ROXR RTD RTE RTR RTS Reset External Devices Rotate Left and Right Rotate with Extend Left and Right Return and De allocate Return from Exception Return and Restore Codes Return from Subroutine 2118A HIREL 03 02 AIMEL 33 Bus Operation Function Codes Address Bus Address Strobe Data Bus Data Strobe AMEL Table 7 Instruction Set Summary Continued Mnemonic Description SBCD Subtract Decimal with Extend Scc Set Conditionally STOP Stop SUB Subtract SUBA Subtract Address SUBI Subtract Immediate SUBQ Subtract Quick SUBX Subtract with Extend SWAP Swap Register Words TBLS TBLSN Signed Uns
9. terms are related by the equation jc 4 is device related and cannot be influenced by the user However is user depen dent and can be minimized by such thermal management techniques as heat sinks ambient air cooling and thermal convection Thus good thermal management on the part of the user can significantly reduce so that approximately equals Substi tution of for in equation 1 will result in a lower semiconductor junction temperature The microcircuits shall meet all mechanical environmental requirements of either MIL STD 883 for class B devices or screened according to Atmel Grenoble standards devices The document where are defined the marking are identified in the related reference doc uments Each microcircuit are legible and permanently marked with the following information as minimum Atmel logo Manufacturer s part number Class B identification Date code of inspection lot e ESD identifier if available e Country of manufacturing Quality Conformance Inspection DESC MIL STD 883 Electrical Characteristics General Requirements Is in accordance with MIL M 38535 and method 5005 of MIL STD 883 Group A and B inspections are performed on each production lot Group C and D inspection are per formed on a periodical basis static and dynamic electrical characteristics specified and the relevant measurement conditions are given below For ins
10. 3 Lead material and finish shall be any option of MIL STD 853 The macrocircuits are packaged in hermetically sealed ceramic packages which con form to case outlines of MIL M 38510 appendix C when defined 132 PIN SQ PGA UP PAE outline 132 PIN Ceramic CERQUAD The following ratings define the conditions under which the device operates without damage Sections of the device may not operate normally while being exposed to the electrical extremes and contains circuitry to protect against damage from high static voltages or electrical fields It is advised however that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage i e either Vss or 8 1568332 2118A HIREL 03 02 Table 2 Absolute Maximum Ratings Symbol Parameter Test Conditions Min Max Unit Supply Voltage 0 3 47 0 V Vi Input Voltage 0 3 7 0 V Low Power Operation 600 mW Max Power Dissipation Stand By Mode 500 mW M Suffix 55 125 15222 Operating Temperature Vies E 385 Ta Storage Temperature 55 150 C Lead Temperature Max 5 Sec Soldering 270 C Table 3 Thermal Characteristics at 25 C Package Symbol Parameter Value Unit Thermal Resistance Ceramic Ju
11. 78 MHz 20 97 MHz Mode select hold time 0 3 0 4 ns 77 teeta RESET assertion time 4 4 love 78 t RESET rise time 1914 10 10 1 RSTR Notes 16 All AC timing is shown with respect to 20 Vpp and 70 levels unless otherwise noted Minimum system clock frequency is four times the crystal frequency subject to specified limits When an external clock is used minimum high and low times are based on a 50 duty cycle The minimum allowable period is reduced when the duty cycle of the external clock signal varies The relationship between external clock input duty cycle and minimum is expressed Minimum txcyc period minimum 50 external input duty cycle tolerance Parameters for an external clock signal applied while the internal PLL is disabled MODCLK pin held low during reset Does not pertain to an external VCO reference applied while the PLL is enabled MODCLK pin held high during reset When the PLL is enabled the clock synthesizer detects successive transitions of the reference signal If transitions occur within the correct clock period rise fall times and duty cycle are at critical Specification 9A is the worst case skew between AS and DS or CS The amount of skew depends on the relative loading of these signals When loads are kept within specified limits skew will not cause AS and DS to fall outside the limits shown in specificat
12. Monitor Spurious Interrupt Monitor Software Watchdog Periodic Interrupt Timer 2118A HIREL 03 02 The MCU provides an internal bus monitor to monitor the DSACKx response time for all internal bus accesses An option allows the monitoring of internal to external bus accesses There are four selectable response times that allow for the response speed of peripherals used in the system A bus error signal is asserted internally if the DSACKx response time is exceeded When operating as a bus master the BERR signal is not asserted externally Figure 21 System Integration Module Block Diagram System Configuration and Protection EE ee iGEKOUT Clock Synthesiser e MODCK Chip Selects Upper Address Chip Selects EE E E EE E Exterrial Bus E External Bus Interface RESET 1 TSTME FREEZE QUOT A halt monitor causes reset to occur if the internal halt HALT is asserted by the CPU If no interrupt arbitration occurs during an interrupt acknowledge IACK cycle the BERR signal is asserted internally The watchdog asserts RESET if the software fails to service the software watchdog for a designated period of time presumably because it is trapped in a loop or lost There are four selectable time out periods and a prescaler may be used for long time out periods The MCU provides a timer to generate periodic inte
13. Springs CO 80906 TEL 81 3 3523 3551 TEL 1 719 576 3300 FAX 81 3 3523 7581 FAX 1 719 540 1759 Atmel Smart Card ICs Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 Scotland TEL 44 1355 803 000 FAX 44 1355 242 743 e mail literature atmel com Web Site http www atmel com Atmel Corporation 2002 Atmel Corporation makes no warranty for the use of its products other than those expressly contained in the Company s standard warranty which is detailed in Atmel s Terms and Conditions located on the Company s web site The Company assumes no responsibility for any errors which may appear in this document reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products expressly or by implication Atmel s products are not authorized for use as critical components in life support devices or systems is the registered trademarks of Atmel Other terms and product names may be the trademarks of others Printed on recycled paper 2118A HIREL 03 02 0M
14. The instruction pipe PIPE output indicates the start of each new instruction and each mid instruction pipeline advance The instruction fetch FETCH output identifies the bus cycles in which the operand is loaded into the instruc tion pipeline Pipeline flushes are also signaled with IFETCH Monitoring these two signals allows a bus analyzer to synchronize itself to the instruction stream and monitor its activity An external breakpoint trap on any memory access Table 7 Instruction Set Summary Mnemonic Description ABCD Add Decimal with Extend ADD Add ADDA Add Address ADDI Add Immediate ADDQ Add Quick ADDX Add with Extend AND Logical AND ANDI Logical AND Immediate ASL ASR Arithmetic Shift Left and Right Bcc Branch Conditionally BCHG Test Bit and Change BCLR Test Bit and Clear BGND Background BKPT Breakpoint BRA Branch BSET Test Bit and Set BSR Branch to Subroutine BTST Test Bit CHK CHK2 Check Register Against Upper and Lower Bounds CLR Clear CMP Compare CMPA Compare Address CMPI Compare Immediate CMPM Compare Memory to Memory CMP2 Compare Register Against Upper and Lower Bounds DBcc Test Condition Decrement and Branch DIVS DIVSL Signed Divide DIVU DIVUL Unsigned Divide 2118A HIREL 03 02 Table 7 Instruction Set Summary Continued Mnemonic EOR EORI EXG EXT EXTB Description Logical Exclusive OR Logical Exclusive OR Immediate Exchange Registers Sign Extend ILLEGAL
15. as LIMP mode The clock frequency generated will not have an associated timing spec but should be around 9 MHz Typical microcomputer systems require external hardware to provide select signals to external peripherals This MCU integrates these functions on chip in order to provide the cost speed and reliability benefits of a higher level of integration The chip select sig nals can also be programmed as output enable read or write strobe signals Since initialization software would probably reside in a peripheral memory device con trolled by the chip select circuits a CSBOOT register provides default reset values to support bootstrap operation The chip select submodule supports the following programmable features 40 1568332 2118A HIREL 03 02 Twelve Programmable Chip select Circuits Variable Block Sizes Both 8 bit and 16 bit Ports Supported Read Only Write Only or Read write Capability Address Strobe and Data Strobe Timing Option Internal DSACK Generation with Wait States Address Space Checking Interrupt Priority Level Checking Discrete Output 68000 type Peripheral Support 2118A HIREL 03 02 Twelve chip select signals are available CSBOOT and CS10 tro CSO These signals use the CSBOOT pin bus arbitration pins BR BG and BGACK function code pins 2 and address pins A23 A19 The pin is dedicated to a single func tion becaus
16. instructions to store register contents in memory The seven basic addressing modes are as follows register direct register indirect register indirect with index program counter indirect with displacement program counter indirect with index absolute immediate Included in the register indirect addressing modes are the capabilities to post increment pre decrement and offset The program counter relative mode also has index and offset capabilities In addition to these addressing modes many instructions implicitly specify the use of the status register stack pointer and or program counter 30 1568332 mem 2118A HIREL 03 02 Instructions 68000 Family Compatibility It is the philosophy of the 68000 family that all user code programs can execute unchanged on a more advanced processor and supervisor mode programs and excep tion handlers should require only minimal alteration The CPU32 be thought of as an intermediate member of the 68000 family Object code from an TS68000 or 68010 be executed on the CPU32 and many of the instruction and addressing mode extensions of the 1568020 are also supported Refer to the CPUS2 reference manual for a detailed comparison of the CPU32 and 568020 instruction set see also Table 7 New Instructions Two new instructions have been added to the TS68000 instruction set for use in control ler applications They are low power stop LPSTOP and table lookup and interp
17. output e Input Capture input Transition Counter e Output Compare Pulse Width Modulation e Synchronized Pulse Width Modulation e Period Measurement With Additional Transition Defect Period Measurement With Missing Transition Detect e Position synchronized Pulse Generator e Stepper Motor e Period pulse width Accumulator The previous pre programmed functions are related to the TPU Rom mask set A cur rently in use for the 7568332 MCU as the standard TPU maskset The advanced TPU affords for the first time high resolution timing and multiple time function capability flexibility in the timer system pins High resolution timing is limited by CPU overhead required for servicing timing tasks such as period measurement pulse measurement pulse width modulated waveform generation etc On the TPU high resolution timing is achieved by two main capabilities reduced latency reduced service time which free the CPU to focus on other responsibilities The TPU provides a higher resolution than the CPU could achieve and creates no CPU overhead for servicing timing tasks Latency is the interval of time from an even to the start of event servicing The ability of the TPU to service its own interrupts or events reduces latency and the CPU is not required to service each input transition capture that occurs on a pin or to determine each match time required for waveform synthesis Once configured by the host CPU the self contai
18. the user privilege level and to the supervisor stack pointer in the user privilege level In addition the address registers may be used for word and long word operations All of the 16 general purpose registers D7 DO A7 A0 may be used as index registers PC contains the address of the next instruction to be executed by the CPU32 AMEL 2118A HIREL 03 02 AMEL The status register SR stores the processor status It contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program The vector base register VBR contains the base address of the exception vector table in memory The displacement of an exception vector is added to the value in this regis ter to access the vector table Alternate function code registers SFC and DFC contain 3 bit function codes Function codes can be considered extensions of the 24 bit linear address that optionally provide as many as eight 16 Mbyte address spaces These address spaces are designated as either user or supervisor space and as either program or data space There is a CPU space to allow the CPU to acquire specific control information not usually associated with read or write bus cycles The function code signals FC2 FCO select the appropriate address space Figure 18 User Programming Model 28 31 16 15 8 7 0 DO D1 D2 D3 D4 Data Registers 05 06 0
19. 0 46 ns 33 BAN Clock low to BG asserted negated 29 23 ns 35 tsraca asserted to BG asserted not asserted 1 1 tovc 37 BGACK asserted to BG negated 1 2 1 2 teye 39 icu BG width negated 2 2 tovc 39A tea BG width asserted 1 1 teye 46 tRwa R W width asserted write or read 150 115 ns 46A tawas R W width asserted fast write or read cycle 90 70 ns er AVEC HALT 5 5 UE 47B Asynchronous input hold time 15 12 ns 48 tanga DSACK 1 0 asserted to BERR HALT asserted 30 30 ns 53 Data out hold from clock high 0 0 ns 54 Clock high to data out high impedance 28 23 ns 55 trapc R W asserted to data bus impedance change 40 32 ns 56 tunpw RESET pulse width reset instruction 512 512 57 tenun BERR negated to HALT negated rerun 0 0 ns 70 teci pp Clock low to data bus driven show 0 29 0 23 ns 71 tecips Data setup time to clock low show 15 10 ns 72 teci pH Data hold from clock low show 10 10 ns 73 tekst BKPT input setup time 15 10 ns 74 texut BKPT input hold time 10 10 ns 75 tuss Mode select setup time 20 20 tcvc 2118A HIREL 03 02 AMEL 15 AMEL Table 6 AC Timing and Vppsyn 5 0 10 for 16 78 MHz and 5 0 5 for 20 97 MHz Vas 0 Voc Tc 55 C to 125 or 40 C to 85 C Continued 76 Number Symbol Parameter Min Max Min Max Unit 16
20. 118A HIREL 03 02 Table 1 Signal Index Continued Signal Name Mnemonic Function Development Serial In Out DSI DSO Clock DSCLK Serial and clock for background debug mode TPU Channels TP15 TPO channel input output Serial and clock for background debug mode TPU Clock In T2CLK External clock source to the TPU SCI Receive Data RXD Serial input to the SCI SCI Transmit Data TXD Serial output from the SCI Peripheral Chip Select PCSS3 PCSO QSPI peripheral chip selects Slave Select SS Places the QSPI in slave mode QSPI Serial Clock SCK Furnishes the clock from the QSPI in master mode or to the QSPI in slave mode Master in Slave out MISO Furnishes serial input to the QSPI in master mode and serial output from the QSPI in slave mode Master out Slave in MOSI Furnishes serial output from the QSPI in master mode and serial input to the QSPI in slave mode Standby RAM VsTBY Power supply for RAM Synchronizer Power Power supply to System Hower Vss Power supply and return to the Return 2118A HIREL 03 02 AIMEL AMEL Figure 2 PGA Terminal Designation 010101010 0101010 S8 98 95 01010 S 9X CE GE GG GE Gi 2 2 9 x X 9x Gi G3 2 2 GX G
21. 15 Vsg RAM standby voltage Specified Vpp applied 0 0 5 5 0 0 5 25 V Vss 3 0 5 5 3 0 5 25 V 16 leg RAM standby current 97 Normal RAM operation gt 0 5V 10 10 Transient condition 0 5 gt Vpp 2 3 3 mA Vss 0 5V Standby operation lt Vss 0 5V 60 50 17 Power dissipation 690 766 mW 18 Cin Input capacitance All input only pins 10 10 All input output pins 20 20 19 C Load capacitance Group 1 I O pins CLKOUT FREEZE QUOT IPIPE 90 90 pF Group 2 pins and CSBOOT BG CS 100 100 Group 3 I O pins 130 130 Group 4 I O pins 200 200 Notes 1 Applies to Port E 7 4 SIZ 1 0 AS DS Port F 7 0 IRQ 7 1 MODCLK Port QS 7 0 TXD PCS 3 1 PCS0 SS SCK MOSI MISO TRUCH 15 0 T2CLK BKPT DSCLK IFETCH RESET RXD TSSTME TSC EXTAL when PLL enabled 2 Input only pins EXTAL TSTME TSC BKPT T2CLK RXD Output only pins CSBOOT BG CS CLKOUT FREEZE QUOT I PIPE Input output pins Group 1 DATA 15 0 IFETCH TPUCH 15 01 Group 2 Port C 6 0 ADDR 22 19 CS 9 6 FC 2 0 C S 5 3 Port E 7 0 SIZ 1 0 AS DS AVEC RMC DSACK 1 0 Port F amp 0 IRQ 7 1 MODCLK Port QS 7 3 TXD PCS 3 1 PCSO SS ADDR23 CS10 ECLK ADDR 18 0 R W BERR BR CSO BGACK CS2 Group 3 HALT RESET Group 4 MISO MOSI SCK 3 Does not apply to HALT an
22. 4 byte exception vector table consisting of 256 exception vectors Exception vectors contain memory addresses of routines that begin execution at the completion of exception processing i e an interrupt routine The processor is always in one of four processing states normal exception halted or background The normal processing state is that associated with instruction execution the bus is used to fetch instructions and operands and to store results The exception processing state is associated with interrupts trap instructions tracing and other exception conditions The exception may be internally generated explicitly by an instruc tion or by an unusual condition arising during the execution of an instruction Externally exception processing can be forced by an interrupt a bus error or a reset The halted processing state is an indication of catastrophic hardware failure For example if during the exception processing of a bus error another bus error occurs the processor assumes that the system is unusable and halts The background processing state is ini tiated by breakpoints execution of special instructions or a double bus fault Background processing allows interactive debugging of the system via a simple serial interface Addressing in the CPU32 is register oriented Most instructions allow the results of the specified operation to be placed either in a register or directly in memory this flexibility eliminates the need for extra
23. 68000 family processors include an instruction by instruction trac ing facility as an aid to program development The CPU32 also allows the user to trace only those instructions causing a change in program flow Breakpoint Instruction An emulator may insert software breakpoints into the target code to indicate when a breakpoint has occurred On the CPU32 this function is provided via illegal instructions 4848 484F to serve as breakpoint instructions Unimplemented Instruction Emulation During instruction execution when an attempt is made to execute an illegal instruction an illegal instruction exception occurs Unimple mented instructions F line A line utilize separate exception vectors to permit efficient emulation of unimplemented instructions in software AMEL s 2118A HIREL 03 02 Background Debug Mode Deterministic Opcode Tracking On chip Breakpoint Hardware AMEL Microcomputer systems generally provide a debugger implemented in software for system analysis at the lowest level The background debug mode in the CPU32 is unique in that the debugger has been implemented in CPU microcode Registers can be viewed and or altered memory can be read or written to and test features can be invoked Incorporating these capabilities on chip simplifies the environment in which the in circuit emulator operates CPU 32 function code outputs are augmented by two supplementary signals to monitor the instruction pipeline
24. 7 31 16 15 0 A1 2 Address Registers 4 5 6 31 16 15 0 A7 USP User Stack Pointer 31 16 15 0 CCR Condition Code Register 1568332 mem 2118A HIREL 03 02 TS68332 Figure 19 Supervisor Programming Model Supplement 31 16 15 0 15 8 7 0 SR Status Register Pl Data Types Organization In Registers System Features Virtual Memory 2118A HIREL 03 02 SFC Alternate Function DFC Code Registers Six basic data types are supported e bits e packaged binary coded decimal digits byte integers 8 bits word integers 16 bits long word integers 32 bits quad word integers 64 bits The eight data registers can store data operands of 1 8 16 32 and 64 bits and addresses of 16 or 32 bits The seven address registers and the two stack pointers are used for address operands of 16 or 32 bits The PC is 32 bits wide The CPU32 includes a number of features to aid system implementation These include a privilege mechanism separation of address spaces multilevel priority interrupts trap instructions and a trace facility The privilege mechanism provides user and supervisor privilege states privileged instructions and external distinction of user and supervisor state references The pro cessor separates references between program and data space This permits sharing of code segments that access separate data segments The 2 sup
25. CPU intervention AMEL s 44 AMEL Wraparound Transfer Mode Wraparound transfer mode allows for automatic continu ous re execution of the preprogrammed queue entries Newly transferred data replaces previously transferred data Wraparound simplifies interfacing with A D converters by automatically providing the CPU with the latest conversions in the QSPI RAM Conse quently serial peripherals appear as memory mapped parallel devices to the CPU Programmable Transfer Length The number of bits in a serial transfer is programmable from 8 to 16 bits inclusive For example 10 bits could be used for communicating with an external 10 bits A D convertor Likewise a vacuum fluorescent display driver might require a 12 bits serial transfer The programmable length simplifies interfacing to serial peripherals that require different data lengths Programmable Transfer Delay An inter transfer delay may be programmed from approximately 1 to 500 us using a 16 78 MHz system clock For example A D con vertor may require time between transfers to complete a new conversion The default delay is 1 us The programmable length of delay simplifies interfacing to serial peripher als that require delay time between data transfers Programmable Queue Pointer The QSPI has a pointer that points to the queue location containing the data for the next serial transfer The CPU can switch from one task to another in the QSPI by writing to the queue poin
26. CS2 PQS4 PCS1 lt 1 _ PQS3 PCSO SS PCSO SS PQS2 SCK PQS1 MOSI PQSO MISO lt MODCLK clock lt TSC TEST T DSCLK QUOT IFETCH DSI lt E DSO lt CONTROL CONTROL 2118A HIREL 03 02 gt FREEZE QUOT 7568332 Signal Description AMEL Figure 1 illustrates the functional signal groups and Table 1 lists the signals and their function Table 1 Signal Index Signal Name Mnemonic Function Address Bus A23 24 bit address bus Data Bus 015 DO 16 bit data bus used to transfer byte or word data per bus cycle Data Bus Function Codes FC2 FCO Identify the processor state and the address space of the current bus cycle Boot Chip Select CSBOOT 2 boot stat up ROM containing user s reset vector and initialization Chip Selects CS10 CSO Enables peripherals at programmed addresses Bus Request BR Indicates that an external device requires bus mastership Bus Grant BG n that current bus cycle is complete and the 568332 has relinquished the Bus Grant Acknowledge BGACK Indicates that an external device has assumed bus mastership 1222 Provides asynchronous data transfers and dynamic bus sizing Autovector AVEC Requests an automatic vector during an interrupt acknowledge cycle Read Modify Write Cycle RMC Identifies the bus cycle as part of an indivisible read modify write cycle Address S
27. EL 0 SYSTEM CONFIGURATION 2 DEVELOPMENT IMB SUPPORT AND TEST PINS CHANNEL CONTROL PARAMETER RAM Flexibility Channel Orthogonality Inter channel Communication Programmable Channel Service Priority MICROENGINE CONTROL STORE CONTROL AND DATA EXECUTION UNIT CHANNEL 15 The TPU has the flexibility to be configured to directly solve the user s timer require ments This flexibility is attained through five capabilities channel orthogonality inter channel communication programmable channel service priority Selection of timing functions emulation capability Traditionally timer systems have been limited by the specific functions of channel pins dedicated to perform time functions such as input capture output compare or pulse accumulation All channels of the TPU contain identical hardware and are functionally equivalent in operation such that any channel can be configured to perform any time function The user controls the combination of time functions the only constraint is the number of pins available for timing functions The TPU s ability to service itself requires a continuous flow of direct and indirect com munication Direct communication is accomplished through a change channel feature in which any channel of the TPU can operate another channel to affect its state Indirect communication is provided by a link feature in whic
28. Interrupt Timer 68000 Family Spurious Interrupt Halt and Bus Time out Monitors Up to 48 Discrete I O Pins Description The TS68332 is a 32 bit microcontroller combining high performance data manipula tion capabilities with powerful peripheral subsystems TS68332 is the first member of the 68300 family of modular embedded controllers featuring fully static high speed complementary metal oxide semiconductor technology Based on the powerful TS68020 the 32 instruction processing module provides enhanced sys tem performance and utilizes the extensive software base of the 68000 family Rev 2118A HIREL 03 02 AMEL Screening Quality AMEL This product is manufactured in full compliance with MIL STD 883 class e DSCC 5962 91501 e Or according to Atmel Grenoble standard Introduction R suffix A suffix PGA 132 CERQUAD 132 Ceramic Pin Grid Array Ceramic Leaded Chip Carrier Figure 1 is a block diagram of the TS68332 showing the major components The pin descriptions are provided in Table 1 The TS68332 contains intelligent peripheral mod ules such as the Time Processor Unit TPU which provides 16 microcoded channels for performing time related activities from simple input capture or output compare to complicated motor control or pulse width modulation High speed serial communications are provided by the Queued Serial Module QSM with synchronous and asynchronous protocols available 2 K
29. Na Avoid use of plastic rubber or silk in MOS areas f Maintain relative humidity above 50 if practical AMEL s ATMEL Packaging Information Figure 26 132 Pin Grid Array PGA 52 0 170 0 195 0 100 BSC 0 04 0 06 1 016 1 524 0 100 BSC 2 54 BSC 00000 000000000000 000000000000 1234 5 6 7 8 9 10 11 12 13 0 017 0 022 0 43 0 55 gt 2118A HIREL 03 02 Figure 27 132 lead CERQUAD 1 08 0 008 pt 27 43 10 2 020 0 008 9 v O12 GJ 0 860 0 900 21 85 22 86 0 51 0 020 G5 r x v 2 6 m PIN ONE INDENT 0 64 BSC olo 55 S H SIN 9 94 ale zi E 8 X TUUTUTUUUUUUUUTUUUTUUUUUUUUUU UU U U T LII 7 90 51 0 020 9 v Olz 20 0 008 MITI O v Olz 6 0 155 0 178 0 025 3 94 4 52 i gp P RR ml C3 0 10 0 004 SEATING PLANE 0 020 0 030 0 51 0 76 0 025 BSC 0 005 0 008 0 019 0 039 0 13 0 20 0 50 1 00 21020 0 008 GT 9 v G z 6 Notes Dimensioning and tolerancing per ansi Y14 5M 1982 Controlling dimensions inch Dim A and B define maximum ceramic body dimensions including glass protrusion and mismatch of cera
30. Output High Voltage 9 0 8 mA Group 1 2 4 0 8 Vpp 0 8 V input output and all output pins 9 VoL Output Low Voltage 1 6 mA Group 1 pins 0 4 0 4 V CLKOUT FREEZE QUOT IPIPE 5 3 mA Group 2 4 0 4 0 4 V pins CSBOOT BG CS lo 12 mA Group 3 0 4 0 4 V 10 Three State Control Input High Voltage 1 6 Vpp 9 1 1 6 Vpp 9 1 11 Data Bus Mode Select Pull up Current Vin DATA 15 0 120 120 Vin Vin DATA 15 0 15 15 12 Vpp supply current lbo RUN 124 140 mA RUN emulation mode E 134 150 Sipp LPSTOP 32 768 kHz crystal VCO off STSIM 0 350 350 pA Sipp LPSTOP external clock input frequency maximum z 5 5 mA AMEL 2118A HIREL 03 02 AMEL Table 4 DC Characteristics and Vppsyn 5 0Vpc 10 for 16 78 MHz and 5 0Vpc 5 for 20 97 MHz Vss OVpc 55 C to 125 C or 40 C 10 85 C Continued 16 78 MHz 20 97 MHz Number Symbol Parameter Min Max Min Max Unit 13 Vbpsyn Clock synthesizer operating voltage 4 5 5 5 4 75 5 25 V 14 Vopsyn Supply current 92 768 kHz crystal VCO on maximum fsys 1 2 IppsvN External clock maximum fsys x 5 6 mA Sippsyn_ LPSTOP 32 768 kHz crystal VCO off STSIM 0 150 150 32 768 kHz crystal powered down 100 100
31. REL 03 02 SCI Submodule 2118A HIREL 03 02 Figure 24 Organization of the QSPI RAM ENTRY 000 020 0 Word Byte The SCI submodule is used to communicate with external devices and other MCUS via an asynchronous serial bus The SCI is fully compatible with the SCI systems found on other Atmel MCUs such as the 68HC11 and 68HCO5 families It has all of the capabili ties of previous SCI systems as well as several significant new features Features Standard SCI features are listed below followed by a list of additional features offered Standard SCI Two wire Systems Feature e Standard Non Return to Zero NRZ Mark space Format Advanced Error Detection Mechanism Detects Noise Duration Up To 1 16 of A Bit time e Full duplex Operation Software Selectable Word Length 8 or 9 bits Words Separate Transmitter And Receiver Enable Bits Be Interrupt Driven Separate Interrupt Enable Bits Standard SCI Receiver Features e Receiver Wake Up Function Idle or Address Mark Bit Detect Framing Error Detect Noise Detect e Overrun Detect e Receive Data Register Full Flag Standard SCI Transmitter Features Transmit Data Register Empty Flag Transmit Complete Flag Send Break QSM enhanced SCI Two wire Systems Features AMEL Standby RAM with emulation Overview RAM Array Addressing AMEL 18 bits Programma
32. TA 15 0 Ha Note AS and DS timing shown for reference only Figure 15 Reset and Mode Select Timing Diagram ESET 15 0 24 568332 mem 2118A HIREL 03 02 Functional Description Module Memory Map The RAM array is positioned by the base address register in the RAM CTRL block Reset forces the RAM array to be disabled Unimplemented blocks are mapped externally Figure 16 Module Memory Map YFFOOO RAM ARRAY 2 0K BYTES YFF800 YFFAOO SIM RESERVED YFFBOO RAM CTL YFFB40 RESERVED SYFFCOO QSM YFFEOO TPU YFFFFF Note 111 where M is the modmap signal state on the IMB which reflects the state of the modmap bit in the module configuration register of the system integration module Y 7 or F CPU32 Overview The CPU32 the instruction processing module of the 68300 family is based on the industry standard TS68000 core processor with many features of the 68010 and TS68020 as well as unique features suited for high performance controller applications The CPU32 is designed to provide a significant increase in performance over existing microcontroller CPUs to meet the demand for higher performance requirements for the 1990s while maintaining source code and binary code compatibility with the 68000 family Ease of programming is an important consideration in using a microcontroller An instruction format implementing a register memory interaction philosophy p
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34. X 2 x uU gt lt 2 4 5 6 7 8 9 10 11 12 13 1 1568332 mem 6 1 03 02 Figure 3 CERQUAD Terminal Designation SSA 52 004 004 50 10 19 550 20 22 952 6 1 1S9 0cdHQQV rOd 8S9 LeHQQv SOd 6S9 eedaav 9od 0189 6 SSA 021 GLHONdL VIHONdL ELHONdL ZLHONdL SSA LELHONdL OLHONdL 6HONdL 8HONdL dd SSA ZHONdL 9HONdL SHONdL PHONdL OHONdL SSA BGACK CS2 BG CS1 BR CSO CSBOOT DATAO DATA10 DATA11 Vpp PEO DSACKO PE1 DSACK1 PE2 AVEC PE5 DS VDD Vss DATA12 VDD DATA1 DATA2 DATA3 VDD Vss DATA4 DATA5 DATA6 DATA7 Vss DATA8 DATA9 DATA13 DATA14 DATA15 ADDRO SSA SY 0215 93 X 19000W 03d 1Oul 13d cOul cdd vOul vdd SOul G3d 9 3439 LINH 195399 gt o E
35. alid until RESET is released This specification also applies to the period required for PLL lock after changing the W and Y frequency control bits in the synthesizer control register SYNCR while the PLL is running and to the period required for the clock to lock after LPSTOP 6 Internal VCO frequency fyco is determined by SYNCR W and Y bit values The SYNCR X bit controls a divide by two cir cuit that is not in the synthesizer feedback loop When X 0 the divider is enabled and fsys fyco 4 When X 1 the divider is disabled and fyco 2 X must equal one when operating at maximum specified 7 Stability is the average deviation from the programmed frequency measured over the specified interval at maximum fsys Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal Noise injected into the PLL circuitry via Vppsyn and Vss and variation in crystal oscillator frequency increase the Cstab percentage for a given interval When clock stability is a critical constraint on control system operation this parameter should be mea sured during functional testing of the final system AMEL 2118A HIREL 03 02 AMEL Table 6 AC Timing and Vppsyn 5 0 10 for 16 78 MHz and 5 0 5 for 20 97 MHz Vss 0 Voc Tc 55 C to 125 C or 40 C to 85 C
36. ble Baud Rate Modulus Counter Even odd Parity Generation And Detection QSM enhanced SCI Receiver Features Two Detect Modes e Receiver Active Flag 13 bit Programmable Baud Rate Modulus Counter A baud rate modulus counter has been added to provide the user with more flexibility in choosing the crystal frequency for the system clock The modulus counter allows the SCI baud rate generator to produce standard transmission frequencies for a wide range of system clocks The user is no longer constrained to select crystal frequencies based on the desired serial baud rate This counter baud rates from 64 baud to 524 baud with a 16 78 MHz system clock Even odd Parity Generation and Detection The user now has the choice either of seven or eight data bits plus one parity bit or of eight or nine data bits with no parity bit Even or odd parity is available The transmitter automatically generates the parity bit for a transmitted byte The receiver detects when a parity error has occurred on a received byte and sets a parity error flag Two ldle line Detect Modes Standard Atmel Grenoble SCI systems detect an idle line when 10 or 11 consecutive bit times are all ones Used with the receiver wake up mode the receiver can be awakened prematurely if the message preceding the start of the idle line contained ones in advance of its stop bit The new second idle line detect mode only starts counting idle time after a valid stop bit is received w
37. bytes of fully static standby RAM allow fast two cycle access for system and data stacks and variable storage with provision for battery back up There is a System Integration Module SIM which includes twelve chip selects to enhance sys tem integration for fast external memory or peripheral access The powerful 32 bit CPU CPU 32 is based on the industry standard TS68020 These modules are connected on chip via the Intermodule Bus IMB and provide reduced system part count size cost of implementation and increased reliability 2 1568332 Y 2118A HIREL 03 02 Figure 1 Block Diagram of TS68332 gt CSBOOT ADDR23 CS10 PORTC gt PC6 ADDR22 CS9 PC5 ADDR21 CS8 PC4 ADDR20 CS7 PC3 ADDR19 CS6 gt PC2 FC2 CS5 gt 1 1 54 CONTROL gt PCO FCO CS3 BGACK CS2 BG CS1 BR CSO ADDR 18 0 gt 5171 gt gt PE6 SIZO gt 5 05 gt PEA AS gt CONTROL PORTE PE2 AVEC PE1 DSACK1 PEO DSACKO DATA 15 0 gt RW RESET HALT CONTROL PORT F BERR PF7 IRQ7 PF6 IRO6 PF5 IRQ5 PFA IRQ4 PF3 IRQ3 PF2 IRQ2 PFO MODCLK CLKOUT XTAL EXTAL XFC VDDSYN TSC VSTBY TPUCH 15 0 TPUCH 15 0 T2CLK T2CLK 2 s e a lt PQS7 TXD lt TXD PQS6 PCS3 lt PCS3 QS5 PCS2 lt P
38. ce memory or peripheral then responds by placing the requested data on the correct portion of the data bus for a read cycle or latching the data on a write cycle and asserting the DSACK1 DSACKO combination that corresponds to the port size to end the cycle If no slave responds or the access is invalid external control logic asserts the or BERR and HALT signal s to abort or retry the bus cycle respectively With an external device that has a fast access time the chip select circuit fast termina tion option can provide a two cycle external bus transfer Since the chip select circuits are driven from the system clock the bus cycle termination is inherently synchronized with the system clock The bus architecture requires assertion of DSACKx from an external device to signal that a bus cycle is complete DSACKx or AVEC is not asserted in these cases external device does not respond interrupt vector is provided e Various other application dependent errors occur This MCU has bus error input BERR when no device responds by asserting DSACKx or within an appropriate period of time after the MCU asserts the AVEC This allows the cycle to terminate and the MCU to enter exception processing for the error condition Another signal that is used for bus exception control is the halt signal HALT This signal can be asserted by an external device for debugging purposes to cause single bus operation or in c
39. cess timing of the RAM module remains consistent with the TPU ROM control store The TPU s high speed versatile architecture and time functions facilitate its use in many control applications such as stepper motors and angle based engine control Control of a stepper motor or an angle based automotive engine usually requires high CPU overhead These applications show how the SM PMA PPM and time functions minimize the overhead associated with these applications and provide sophistication and flexibility for a wide variety of applications Further detailed information on the TPU is found in the TPU reference manual Microcircuit are prepared for delivery in accordance with MIL M 38510 Atmel Grenoble offers a certificate of compliance with each shipment of parts affirming the products are in compliance either with MIL STD 883 or Atmel Grenoble standard and guaranteeing the parameters are tested at extreme temperatures for the entire tem perature range MOS devices must be handled with certain precautions to avoid damage due to accu mulation of static charge Input protection devices have been designed in the chip to minimize the effect of this static buildup However the following handling practices are recommended Device should be handled on benches with conductive and grounded surface b 9 Ground test equipment tools and operator Do not handle devices by the leads Store in conductive foam or carriers 2
40. ck Control Timing and Vppsyy 5 0 10 for 16 78 MHz and 5 0 Voc 5 for 20 97 MHz Vss 0 55 to 125 or 40 C to 85 C 16 78 20 97 Number Symbol Parameter Min Max Min Max Unit 1 Tar PLL reference frequency range 25 50 25 50 kHz 2 bs System frequency dc 16 78 dc 20 97 MHz On chip PLL system frequency 0 131 16 78 0 131 20 97 MHz External clock operation dc 16 78 dc 20 97 MHz 3 fioi PLL lock time 9905 20 20 ms 4 bas VCO frequency 9 2 fey max 2 fsys max MHz 5 Limp mode clock frequency SYNCR X bit 0 fsys max 2 f max 2 MHz SYNCR X bit 1 fsys max fsys max MHz 6 CLKOUT stability 9902 Short term 5 us interval 05 05 05 05 96 Long term 500 ys interval 0 05 0 05 0 05 0 05 96 Notes 1 Allinternal registers retain data at 0 Hz 2 This parameter is periodically sampled rather than 100 tested 3 Assumes that a low leakage external filter network is used to condition clock synthesizer input voltage Total external resis tance from XFC pin due to external leakage must be greater than 15 to guarantee this specification Filter network geometry can vary depending upon operating environment 4 Proper layout procedures must be followed to achieve specifications 5 Assumes that stable Vppsyy is applied and that the crystal oscillator is stable Lock time is measured from the time Vpp and Vopsyn are v
41. ctions are permitted to execute in the lower privileged user level but all instructions are available at the supervisor level This scheme allows a separation of supervisor and user levels and so the supervisor can protect system resources from uncontrolled access The pro cessor uses the privilege level indicated by the S bit in the status register to select either the user or supervisor privilege level and either the USP or SSP for stack operations The user programming model remains unchanged from previous 68000 family micropro cessors The supervisor programming model which supplements the user programming model is used exclusively by the CPU32 system programmers who utilize the supervisor privilege level to implement sensitive operating system functions The supervisor pro gramming model contains all the controls to access and enable the special features of the CPU32 application software written to run at the non privileged user level migrates to the CPU32 from any 68000 platform without modification The programming models are shown in Figure 18 and Figure 19 Registers Registers 07 00 are used as data registers and readily support 8 bit byte 16 bit word and 32 bit long word operand lengths for all operations Registers A6 AO and the user and supervisor stack pointers are address registers that may be used as soft ware stack pointers of base address registers Register A7 is a register that applies to the user stack pointer in
42. d RESET because they are open drain pins Does not apply to Port QS 7 0 TXD PCS 3 1 50 55 SCK MOSI MISO in wired OR mode Use of an active pull down device is recommended Total operating current is the sum of the appropriate lpp and lag values Ipp values lpp values include supply cur rents for device modules powered by Vppg and pins 6 Current measured with system clock frequency of 16 78 MHz all modules active edi 12 1568332 Y 7 8 The RAM module will not switch into standby mode as long as does not exceed Vp by more than 0 5 volt The RAM array cannot be accessed while the module is in standby mode When is transitioning during power up or power down sequence Vsg is applied current flows between the Vsrgy and Vpp pins which causes standby current to increase toward the maximum transient condition specification System noise on the and pins can contribute to this condition Power dissipation measured at specified system clock frequency all modules active Power dissipation can be calculated using the expression Maximum Ippsyw lag includes supply currents for all device modules powered by Vppg Vpp pins 10 This parameter is periodically sampled rather than 100 tested Dynamic Switching The INTERVAL numbers refer to the timing diagram Characteristics Table 5 Clo
43. d that the cycle may terminate These signals also indicate to the MCU the size of the port for the bus cycle just completed The bus error BERR signal is also a bus cycle termination indicator and can be used in the absence of to indicate a bus error condition It can also be asserted in con junction with DSACKx to indicate a bus error condition provided it meets the appropriate timing Additionally the BERR and HALT signals can be asserted simulta neously in lieu of or in conjunction with the DSACKx signals The internal bus monitor can be used to generate the BERR signal for internal and inter nal to external transfers An external bus master must provide its own BERR generation and drive the BERR pin since the internal BERR monitor has no information about transfers initiated by an external bus master Finally the autovector AVEC signal can be used to terminate interrupt acknowledge cycles indicating that the MCU should internally generate a vector number to locate an interrupt handler routine AVEC is ignored during all other bus cycles The MCU dynamically interrupts the port size of the addressed device during each bus signal allowing operand transfers to or from 8 and 16 bit ports During an operand transfer cycle the slave device signals its port size byte or word and indicates comple tion of the bus cycle to the MCU through the use of the DSACKx encodings and assertion results Refe
44. e it must function after a reset with no initialization the other chip select circuits share functions on their output pins All 12 chip select circuits are independently programmable from the same list of selectable features Each chip select circuit has an individual base register and option register which contain the programmable character istics of that chip select Using these address lines as chip select signals does not restrict the large linear address space of the MCU since the chip select logic always uses the internal address lines The block size starting from the specified base address can be programmed as 2K 8K 16K 64K 128K 256K 512Kbytes or 1 Mbyte Eight bit ports are accessible on both odd and even addresses when connected to data bus bits 15 8 Sixteen bit ports can be accessed as odd bytes even bytes or words Chip selects can be asserted synchronized with read write or both read and write Chip select signals can be synchronized with either address strobe or data strobe so that control signals such as output enable or write enable can be easily generated The port programmed in the pin assignment register can be referenced for generating DSACK and the proper number of wait states for a particular device programmed by the user Supervisor user and CPU space accesses can be optionally checked In the IACK cycle the acknowledged interrupt level can be compared with the user specified level programmed in th
45. e option field If autovector option is selected AVEC is internally asserted Port C pins A22 A19 and FC2 FCO can be programmed for discrete output with data stored in the pin data register CSPDR 68000 type peripherals that require an E clock for synchronization can be supported Chip select is asserted synchronized with the E clock on pin A23 providing correct data bus timing for the MCU AMEL n Test Submodule QSM Queued Serial Module QSM Pins QSPI Submodule AMEL The test submodule is a primary tool to support all types of testing such as production test and user self test that is integrated into the MCU The submodule supports scan based testing of various modules in the MCU The scan test employed here consists of the test submodule performing the following steps e Serially shifting stimulus data to an idle module under test MUT e activating the module under test e Serially shifting response data back from the module under test e latching the response data for interrogation by the bus master The further information to the System Integration Module Manual The queued serial module QSM provides the microcontroller unit MCU with two serial communication interfaces divided into two submodules the queued serial peripheral interface QSP and the serial communications interface SCI The QSPI is full duplex synchronous serial interface for communicating with peripherals and other MCUs It i
46. ed on the QSPI e full duplex three wire synchronous transfers half duplex two wire synchronous transfers master or slave operation programmable master bit rates programmable clock polarity and phase end of transmission interrupt flag master master mode fault flag e easily interfaces to simple expansion parts A D converters EEPROMs display drivers etc A programmable queue allows the QSPI to perform up to 16 serial transfers without CPU intervention Each transfer corresponds to a queue entry containing all the infor mation needed by the QSPI to independently complete one serial transfer This unique feature greatly reduces CPU QSPI interaction resulting in increased CPU and system throughput Once the CPU has set up the queue of QSPI commands and enables the QSPI the QSPI operates independently of the CPU The QSPI executes all of the commands in its queue sets a flag indicating that it has finished and then either interrupts the CPU or waits for CPU intervention Programmable Peripheral Chip Selects Four peripheral chip select pins allow the QSPI to access up to 16 independent peripherals by decoding the four peripheral chip select signals Up to four independent peripherals can be selected by direct connection to a chip select pin The peripheral chip selects simplify interfacing to two or more serial peripherals by providing dedicated peripheral chip select signals and thus alleviating the need for
47. h any channel can lonk to one more channels including itself to signal a need for future service As a result the user can reference the operation of one channel to the occurrence of a specific action on another channel Applications may require different priorities of event service The channel service priority may be programmed to one of three levels high middle and low The scheduler allows calculation of worst case latency for event servicing and ensures servicing of all chan nels by preventing permanent blockage 50 1568332 mem 2118A HIREL 03 02 Selection of Timing Functions Emulation Capability Applications Preparation For Delivery Packaging Certificate of Compliance Handling 2118A HIREL 03 02 The available timing functions can be programmed to operate on any channel Parame ter registers associated with each channel are used as general purpose time operands The TPU cannot resolve all timer problems using predefined time functions alone there fore development of user defined time functions is allowed in emulation mode Using the RAM module of the MCU as a writable control store provides TPU emulation In TPU emulation mode an auxiliary bus connection is made between the RAM module and the TPU module and access to the RAM module via the intermodule bus is dis abled A 9 bits address bus a 32 bits data bus and control lines transfer information between the modules To ensure exact emulation the ac
48. hich ensures correct idle line detection Receiver Active Flag RAF Receiver Active Flag RAF indicates the status of the receiver It is set when a possible start bit is detected and is cleared when an idle line is detected RAF is also cleared if the start bit is determined to be line noise This flag can be used to prevent collisions in systems with multiple masters For further information refer to the System Integration Module Manual The TS68332 contains 2 Kbytes of standby RAM This section describes the operation and control of the RAM module The Ram module contains 2048 bytes of fully static RAM powered by in normal operation The entire array may be used as standby RAM if power is supplied to the pin Switching between Vpp and occurs automatically The RAM may be used as general purpose memory for the MCU providing fast two clock accesses to the CPU Typically the RAM is used for program control stacks and frequently modified data variables The CPU may read or write byte word or long word data The RAM may also be used as microcode control memory for the Time Processor Unit TPU The TPU must be placed in emulation mode to use the RAM in this manner which allows users to develop their own microcode primitives The RAM array can be placed anywhere in the address map of the array base address RAMBAR provided that it is on a 2 Kbytes boundary and does not overlap the three RAM module cont
49. ift instructions fast bus interface with dynamic bus port sizing improved execution handling for controller applications enhanced addressing modes scaled index address register indirect with base displacement and index expanded PC relative modes 32 bit branch displacements breakpoint instruction instruction set enhancements high precision multiply and divide trap on condition codes upper and lower bounds checking enhanced breakpoint instruction trace on change of flow table lookup and interpolate instruction low power stop instruction hardware breakpoint signal background mode 16 78 MHz and 20 97 MHz operating frequency at 55 C to 125 fully static implementation 26 1568332 mem 2118A HIREL 03 02 TS68332 Figure 17 CPU32 Block Diagram Control Unit lt Instruction Prefetch and Decode Data Bus Bus Control Bus Control Execution Unit Address Bus Programmer s Model The programming model of the CPU32 consists of two groups of registers user model and supervisor model which correspond to the user and supervisor privilege levels Executing at the user privilege level user programs can only use the registers of the user model Executing at the supervisor level system software uses the control regis ters of the supervisor level to perform supervisor functions The supervisor level has higher privileges than the user level Not all instru
50. igned Table Lookup TBLU TBLUN and Interpolate TAS Test Operand and Set TRAP Trap TRAPcc Trap Conditionally TRAPV Trap on Overflow TST Test Operand UNLK Unlink This section provides a functional description of the bus and the signals that control it Operation of the bus is the same whether the MCU or an external device is the bus mas ter the names and description of bus cycles are from the point of view of the bus master The MCU architecture supports byte word and long word operands allowing access to 8 bit and 16 bit data ports through use of asynchronous cycles controlled by the data transfer SIZ1 and 5120 and data size acknowledge pins DSACK1 and The function code signals FC2 FCO select one of eight 16 Mbyte address space to which the address applies The address bus signals A23 AO define the address of the byte or the most signifi cant byte to be transferred during a bus cycle The address is valid while AS asserted The Address Strobe AS is a timing signal that indicates the validity of an address on the address bus and of many control signals The data signals D15 comprise a bi directional non multiplexed parallel bus that contains the data being transferred to or from the MCU A read or write operation may transfer 8 or 16 bits of data 1 or 2 bytes in one bus cycle The Data Strobe DS is a timing signal that applies to the data bus For a read cycle the MCU asserts DS
51. iming control Its intelligence enables the servicing of timing events without CPU intervention This device uses a private microengine for a processor a scheduler input output channels ROM instructions and shared access data RAM to operate independently and simultaneously with the CPU see Figure 25 Consequently the setup and service time for each timer event is minimized A time of delay approach is used where all time functions are related to one of two 16 bits free running TCRs Time functions are synthesized by combining the two time prim itives match and capture events By performing these time primitives in hardware the TPU can precisely determine the time when a match event is to occur and then specify the state of the output pin accordingly The TPU can also accurately record the time at which an input transition occurs and can perform calculations based on the time of the occurrence An event register for each channel provides for simultaneity of match cap ture event occurrences on all channels When a match or input capture event requiring service occurs on a channel the channel generates a service request to the scheduler The scheduler prioritizes the request with other pending service requests When the microengine is idle the scheduler causes the microengine to execute a microcode sequence When the microengine is busy the new sequence begins when the code being executed ends The microengine performs the function which
52. ion 9 If multiple chip selects are used CS width negated specification 15 applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select The CS width negated specification between multiple chip selects does not apply to chip selects being used for synchronous cycles Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast cycle reads The user is free to use either hold time Maximum value is equal to t 2 25 ns If the asynchronous setup time specification 47A requirements are satisfied the DSACK 1 0 low to data setup time spec ification 31 and DSACK 1 0 low to BERR low setup time specification 48 can be ignored The data must only satisfy the data in to clock low setup time specification 27 for the following clock cycle BERR must satisfy only the late low to clock low setup time specification 27A for the following clock cycle 10 To ensure coherency during every operand transfer BG will not be asserted in response to BR until after all cycles of the current operand transfer are complete and RMC is negated In the absence of DSACK 1 0 BERR is an asynchronous input using the asynchronous setup time specification 47 12 After external RESET negation is detected a short transition period approximately 2 elapses then the SIM drives RESET low for 512 t 13 E
53. is defined by the content of the control store using parameters from the parameter RAM and from the event registers etc as needed The following is an example Channel X is generating a periodic waveform and presently the output is high When the value of the TCR used by that channel increments to match the value of the event regis ter of channel X a match event occurs The event switches the output to low and generates a new service request to the scheduler The scheduler than schedules and initiates service of channel X by the microengine When execution of the sequence begins the microengine uses the execution unit To obtain from the parameter RAM the value representing the duration of counts for which channel X should remain low and To add to this value the value from the content of the event register of channel X The content of the event register is then replaced by this sum the channel control is set for a match event on the same TCR and the pin control is set to cause the output pin for channel X to switch high when the event occurs A channel interrupt which signals the end of service to the CPU may be asserted if the time function provides for it and the interrupt is enabled The microengine is then free to service the next event determined by the scheduler AMEL s AMEL Figure 25 TPU Simplified Block Diagram HOST TIMER INTERFACE CONTROL SCHEDULER SERVICE REQUESTS CHANNELS CHANN
54. l logic to determine the cause of reset and synchronize it if necessary If an external device drives the RESET pin low the reset control logic holds RESET asserted internally until the external RESET is released When the reset control logic detects that the external RESET is no longer being driven it drives RESETlow for an additional 512 cycles to guarantee this length of reset to the entire system If RESET is asserted from any other source the reset control logic asserts RESET for a minimum of 512 cycles and until the source of reset is negated Figure 20 is a timing diagram of the power up reset operation showing the relationship between RESET Vpp and bus signals During the reset period the entire bus except for non tri statable signals which are driven to their inactive state three states Once RESET negates all control signals are driven to their inactive state the data bus is in read mode and the address bus is driven After this the first bus cycle for RESET exception processing begins RESET should be asserted for at least 590 clock periods to ensure that the MCU resets Resetting the MCU causes any bus cycle in progress to terminate as if DSACKx or BERR has been asserted In addition the MCU initializes registers appropriately for a reset exception For further information refer to the System Integration Module Manual AMEL s AMEL Figure 20 Initial Reset Operation Timing CLKOUT
55. mic body top and bottom Datum plane W is located at the underside of leads where leads exit package body Datums X Y and Z to be determined where center leads exit package body at datum W Dim S and V to be determined at seating plane datum T Dim A and B to be determined at datum plane T AIMEL 2118A HIREL 03 02 Ordering Information Hi Rel Product AMEL Commercial Atmel Temperature Frequency Part Number Norms Package Range Tc C MHz Drawing Number TS68332MRB C16 MIL STD 883 PGA 132 55 125 16 78 Atmel Grenoble datasheet TS68332MR1B C16 MIL STD 883 PGA 132 tin 55 125 16 78 Atmel Grenoble datasheet TS68332MAB C16 MIL STD 883 CERQUAD 132 55 125 16 78 Atmel Grenoble datasheet TS68332MRB C20 MIL STD 883 PGA 132 55 125 20 97 Atmel Grenoble datasheet TS68332MR1B C20 MIL STD 883 PGA 132 tin 55 125 20 97 Atmel Grenoble datasheet TS68332MAB C20 MIL STD 883 CERQUAD 132 55 125 20 97 Atmel Grenoble datasheet TS68332DESC01ZA MIL STD 883 PGA 132 tin 55 125 16 78 5962 9150101MZA TS68332DESC01ZC MIL STD 883 PGA 132 55 125 16 78 5962 9150101MZC TS68332DESCO2ZC MIL STD 883 PGA 132 55 125 20 97 5962 9150102 7 TS68332DESC01XA MIL STD 883 CERQUAD 132 55 125 16 78 5962 9150101 TS68332DESC02XA MIL STD 883 CERQIAD 132 55 125 20 97 5962 9150102MXA Standard Product
56. nction to ambient TBD C W Thermal Resistance Ceramic Junction to case 10 C W Thermal Resistance Ceramic Junction to ambient TBD C W CERQUAD 132 Thermal Resistance Ceramic Junction to case 10 C W Power Considerations 2118A HIREL 03 02 The average chip junction temperature Tj can be obtained from Pp Oja 1 T4 Ambient Temperature Package Thermal Resistance Junction to Ambient C W Pint Vcc Watts Chip Internal Power Pio Power Dissipation on Input and Output Pins User Determined For most applications lt and can be neglected An approximate relationship between Pp and T if Pio is neglected is Pp K Ty 273 2 Solving equations 1 and 2 for gives Pp TA 273 Oy Pp 3 where K is a constant pertaining to the particular part K can be determined from equa tion 3 by measuring at equilibrium for a known T4 Using this value of the values of Pp and T can be obtained by solving equations 1 and 2 iteratively for any value of AMEL o Mechanical and Environment Marking AMEL total thermal resistance of a package 0 4 can be separated into two components and representing the barrier to heat flow from the semiconductor junction to the package case surface 0 and from the case to the outside ambient Oca These
57. ned TPU performs complex time functions requiring high resolution with little or no CPU intervention AMEL a Service Time Features AMEL Service is the time expended servicing an event In older microcontroller unit MCU timer functions the service time is constrained because the MCU instruction set is not optimized for time function synthesis The TPU instruction set is optimized and time functions are synthesized with fewer instructions than the CPU Instructions execute faster and service time is reduced Instructions executed by the TPU are not user soft ware but firmware special purpose microcode written by Atmel Grenoble to perform as set time functions Microcode is placed into the TPU control store ROM when the device is manufactured 16 channels each channel associated with a pin Each channel can perform any time function Each time function may be assigned to more than one channel at a given time Each channel has an event register comprised of the following 16 bits capture register 16 bits compare match register 16 bits greater than or equal to comparator Each channel can be synchronized to one or both of the two 16 bits free running timer count registers TCR1 and TCR2 1 is clocked from the output of a prescaler The prescaler s input is the internal TPU system clock divided by either 4 or 32 The four settings of the prescaler are divide by 1 2 4 and 8 Channels using TRC1 have the ca
58. olate TBL Low Power Stop LPSTOP In applications where power consumption is a consider ation the CPU32 forces the device into a low power standby mode when immediate processing is not required The low power stop mode is entered by executing the LPSTOP instruction The processor will remain in this mode until a user specification or higher interrupt level or reset occurs Table Lookup and Interpolate TBL To maximize throughput for real time applications reference data is often pre calculated and stored in memory for quick access The storage of each data point would require an inordinate amount of memory The table instruction requires only a sample of data points stored in the array reducing memory requirements This single instruction allows intermediate values to be recovered by lin ear interpolation thus significantly increasing CPU throughput compared with earlier interpolation methods which used several instructions The results are optionally rounded with the round to nearest algorithm Development Support The following features have been implemented on the CPU32 to enhance the instru mentation and development environment e 68000 family development support e background debug mode deterministic opcode tracking hardware breakpoints 68000 Family Development All 68000 family members include features to facilitate applications development These Support features include the following Trace On Instruction
59. ombination with BERR a retry of a bus cycle in error 36 1568332 mem 2118A HIREL 03 02 Bus Arbitration Reset Operation 2118A HIREL 03 02 The bus design of the MCU provides for a single bus master at any one time either the MCU or an external device One or more of the external devices on the bus can have the capability of becoming bus master Bus arbitration is the protocol by which an exter nal device becomes bus master the bus controller in the MCU manages the bus arbitration signals so that the MCU has the lowest priority External devices that need to obtain the bus must assert the bus arbitration signals in a certain sequence Systems that include several devices that can become bus master require external circuitry to assign priorities to the devices so that when two or more external devices attempt to become bus master at the same time the one having the highest priority becomes the bus master first The protocol is explained fully in the SIM manual however here is the basic sequence of events e external device asserts the bus request signal BR The MCU asserts the bus grant signal to indicate that the bus is available BG The external device asserts the bus grant acknowledge signal BGACK to indicate that it has assumed bus mastership Bus arbitration requests are recognized during normal processing HALT assertion when the CPU has halted due to a double bus fault The MCU has reset contro
60. pability to resolve down to the TPU system clock divided by four TCR2 is clocked from the output of a prescaler The prescaler s input is the external TCR2 pin The four settings of the prescaler are divide by 1 2 4 and 8 Channels using the TCR1 have the capability to resolve down to the PRU system clock divided by 8 TCR2 may be used as a hardware pulse accumulator clocked from the external TCR2 pin or as a gated pulse accumulator or the clock that increments All channels have at least six 16 bits parameter registers Channels 14 and 15 each have eight 16 bits parameter registers All parameter registers are contained in a dual port RAM accessible from both the TPU and CPU A scheduler with three priority levels segregates high middle and low priority time functions Any channel may be assigned to one of these three priority levels time functions are microcoded Emulation and development support is provided for all time function features such as breakpoint freeze and single step giving internal register accessibility Coherent transfer capability for two parameter is provided in hardware Coherent transfer capability for N parameters may be performed as a TPU microcode function Refer to Development support in the TPU reference manual for further details on this feature 48 1568332 mem 2118A HIREL 03 02 General Concept 2118A HIREL 03 02 The TPU is an intelligent semi autonomous peripheral dedicated to t
61. pection purpose refer to relevant specification e DSCC last issue on request to our marketing services Table 4 Static electrical characteristics for all electrical variants Table 6 Dynamic electrical characteristics for 6832 16 16 78 MHz For static characteristics test methods refer to IEC 748 2 method number where existing For dynamic characteristics test methods refer to clause 5 4 hereafter of this specification 10 1568332 mem 2118A HIREL 03 02 Static Characteristics Table 4 DC Characteristics and Vppsyy 5 0 10 for 16 78 MHz and 5 0 5 for 20 97 MHz Vss OVpc 55 C to 125 C 40 C to 85 C 16 78 2 20 97 MHz Number Symbol Parameter Min Max Min Max Unit 1 Vin Input High Voltage 0 7 Vpp 0 3 0 7 Vpp Vppt0 3 V 2 Input Low Voltage Vss 0 3 0 2 Vpp Vgg 0 8 0 2 V 3 Vuys Input Hysteresis 0 5 0 5 V 4 lin Input Leakage Current Vin Vpp Vss Input only pins 2 5 2 5 2 5 2 5 5 loz High Impedance off state Leakage Current 2 Vin Voo OF Ves All input output 2 5 2 5 2 5 2 5 and output pins 6 CMOS Output High Voltage 9 10 0 Group 1 2 4 Vpp 0 2 Vpp 0 2 V input output and all output pins and all output pins 7 VoL CMOS Output High Voltage 10 0 Group 1 2 4 0 2 0 2 V input output and all output pins 8
62. ports seven priority levels for 199 memory vectored interrupts For each interrupt the vector location can be provided externally or generated internally The sev enth level provides a non maskable interrupt capability To simplify system development instructions are provided to check internal processor conditions and allow software traps The trace facility allows instruction by instruction tracing of program execution without alteration of the program or special hardware The full addressing range of the CPU32 on the 568332 is 16 Mbyte in each of eight address spaces Even though most systems implement a smaller physical memory the system can be made to appear to have a full 16 Mbyte of memory available to each user program by using virtual memory techniques AMEL Loop Mode Instruction Execution Vector Base Register Processing States Addressing Modes AMEL The CPU32 has several features that provide efficient execution of program loops One of these features is the looping primitive instruction To increase the performance of the CPU32 a loop mode has been added to the processor The loop mode is used by a single word instruction that does not change program flow Loop mode is implemented in conjunction with the instruction Once in loop mode the processor performs only the data cycles associated with the instruction and suppresses all instruction fetches The VBR contains the base address of the 102
63. r to Table 9 for DSACKx encodings and assertion results For example if the MCU is executing an instruction that reads a long word operand from a 16 bit port the MCU latches the 16 bits of valid data and runs another bus cycle to obtain the other 16 bits Dynamic bus sizing requires that the portion of the data bus for a transfer to or from a particular port size be fixed For example an 8 bit port must reside on data bus bits 15 8 The SIZx signals also form part of the bus sizing protocol These outputs indicate the remaining number or bytes to be transferred during the current bus cycle AMEL Bus Operation Fast Termination Cycles Bus Exception Control Cycles AMEL Table 9 DSACK Codes and Results DSACK1 Result 1 1 Insert wait states i rent bus cycle Negated Negated nsert wait states in cur y Complete cycle Data bus port size is 8 bits Negated Asserted y P i Complete cycle Data bus port size is 16 bits Asserted Negated y P 0 0 R d Asserted Asserted Mod The MCU bus is used in an asynchronous manner The external devices connected to the bus can operate at clock frequencies different from the clock for the MCU Bus oper ation uses the handshake lines AS DS DSACK1 DSACKO BERR and HALT to control data transfers Decoding the size outputs and lower address line AO provides strobes that select the active portion of the data bus The slave devi
64. redominates in the design and all data resources are available to all operations requiring those resources All capabilities and functions of this module are detailed fully in the CPU32 reference manual AMEL 2118A HIREL 03 02 AMEL Block Diagram The major clocks depicted operate in a highly independent fashion that maximizes con currency of operation while managing the essential synchronization of instruction execution and bus operation The bus controller loads instructions from the data bus into the decode unit The sequencer and control unit provide overall chip control managing the internal buses registers and functions of the execution unit Architecture Summary The CPU32 architecture includes several important features that provide both power and versatility to the user The CPU32 is source and object code compatible with the TS68000 and 68010 All user state programs can be executed unchanged The major CPU32 features as follows 32 bit internal data path and arithmetic hardware 32 bit internal address bus 24 bit external address bus eight 32 bit general purpose data registers seven 32 bit general purpose address registers separate user and supervisor stack pointers and address spaces separate program and data address spaces full interrupt processing fully upward object code compatible with 68000 family virtual memory implementation loop mode of instruction execution fast multiply divide and sh
65. rol registers used for control and testing RAMBAR can be written only once after reset This prevents the RAM array being accidentally remapped by software 46 1568332 2118A HIREL 03 02 Emulation Mode Operation TPU Overview High resolution Timing Latency 2118A HIREL 03 02 The RAM array may be used as the microcode control store for the TPU module This mode of operation is selected from within the TPU See Development support in the TPU manual for a complete description The TPU is connected to the RAM via a dedicated bus While in emulation mode the access timing of the RAM module matches the timing of the TPU microinstruction ROM to ensure accurate emulation Normal accesses via the IMB are inhibited and the control register have to effect allowing external RAM to emulate the 2K RAM array at the same addresses The further information refer to the System Integration Module Manual The TPU performs simple as well as complex timing tasks independently from the CPU making it the latest advance in timer systems Viewed as a special purpose microcom puter this processor performs two operations match and capture on one operand TIME Every occurrence of either action is called an event The servicing of these events by the TPU replaces the servicing of interrupts by the host Central Processing Unit CPU The timing functions currently synthesized are the following Discrete Input
66. rrupts The periodic interrupt time period can vary from 122 us 15 94 us with a 32 768 kHz crystal used to generate the system clock AIMEL 39 Clock Synthesizer Chip select Submodule AMEL Figure 22 Clock Submodule Block Diagram MISO BITO MOSI QSPI Sub module PSC1 PSC2 PSC3 Interface Logic TxD BIT7 SCI Sub module RxD Note Must be low leakage capacitor The clock synthesizer Figure 22 can operate from an on chip phase locked loop PLL using an external crystal connected between the EXTAL and XTAL pins as a reference frequency source A 32 768 kHz watch crystal provides an inexpensive reference but the reference crystal frequency can be any frequency from 25 50 kHz Outside the 25 50 kHz range an external oscillator can be used with the on chip synthesizer and VCO or the frequency can be driven directly into the EXTAL pin the XTAL pin should be left floating for this case The system clock frequency is programmable from 131 kHz to the maximum clock fre quency with a resolution of 131 kHz A separate power pin Vppsyn is used to allow the clock circuits to run with the rest of the MCU powered down and to provide increased noise immunity for the clock circuits If for some reason the external signal is removed from the device then the clock synthesizer will generate its own internal clock signal to allow the device to enter some kind of error recovery routine This is known
67. s enhanced by the addition of a RAM queue for receive and transmit data The SCI is a full duplex universal asynchronous receiver transmitter UART serial interface These submodules operate independently see Figure 23 The QSM has nine external pins Eight of these pins can be used as general purpose I O pins If the pin is not being user for its submodule function The ninth pin RXD is an input only used exclusively by the SCI submodule pins are identified as follows MISO Master In Slave Out MOSI Master Out Slave In SCK Serial Clock PCSO SS Peripheral Chip Select 0 Slave Select PCS3 PCS1 Peripheral Chip Selects 3 1 TXD Transmit Data Receive Data The QSPI submodule communicates with external peripherals and other MCUs via a synchronous serial bus The QSPI is fully compatible with the Serial Peripheral Interface SPI systems found on other Atmel Grenoble devices such as the 68HC11 and 68HCO05 families It has all of the capabilities of the standard SPI system as well as sev eral new features The following paragraphs describe the main feature of the QSPI 42 1568332 mem 2118A HIREL 03 02 QSPI Features QSPI Enhanced Features 2118A HIREL 03 02 7568332 Figure 23 QSM Block Diagram QSPI Sub module Interface Logic TxD BIT7 SCI Sub module RxD Standard SPI features are listed below followed by a list of the additional features offer
68. ter changing the location in the queue that is to be transferred next Otherwise the pointer increments after each serial trans fer By segmenting the queue multiple task support can be provided by the QSPI Continuous Transfer Mode The continuous transfer mode allows the user to exchange an uninterrupted bit stream with a peripheral A minimum of 8 bits and a maximum of 256 bits may be transferred in a single burst without CPU intervention Longer transfers are possible however minimal CPU intervention is required to prevent loss of data A 1microsecond pause using a 16 78 MHz system clock is inserted between each entry transfer QSPI RAM The QSPI uses an 80 byte block of dual access static RAM that can be accessed by both the QSPI and the CPU Because of sharing the length of time taken by the CPU to access the QSPI RAM when the QSPI is enabled may be longer than when the QSPI is disabled From one to four CPU wait states may be inserted by the QSPI in the process of reading or writing The RAM is divided into three segments receive data transmit data and command control Receive data is information received from a serial device external to the MCU Transmit data is information stored by the CPU for transmission to an external periph eral chip Command control contains all the information needed by the QSPI to perform the transfer Figure 24 illustrates the organization of the RAM 1568332 2118A HI
69. to signal the external device to place data on the bus For a write cycle DS signals to the external devices that the data to be written is valid on the bus 34 1568332 2118A HIREL 03 02 Bus Control Signals Bus Cycle Termination Signals Dynamic Bus Sizing 2118A HIREL 03 02 The MCU initiates a bus cycle by driving the address size function code and read write outputs At the beginning of a bus cycle the size signals SIZ1 SIZO are driven along with the function code signals SIZ1 and SIZO indicate the number of bytes remaining to be transferred during an operand cycle consisting of one or more bus cycles Table 8 shows the encoding of SIZ1 and SIZO The read write R W signal determines the direction of the transfer during a bus cycle The read modify write cycle signal is asserted at the beginning of the first bus cycle of a read modify write operation and remains asserted until completion of the final bus cycle of the operation Table 8 Size Signal Encoding SIZ1 SIZ2 Transfer Size 0 1 Byte 1 0 Word 1 1 3 Byte 0 0 Long Word During bus cycles external devices assert the data transfer and size acknowledge sig nals DSACK1 and or DSACKO as part of the bus protocol During a read cycle this signals the MCU to terminate the bus cycle and to latch the data During a write cycle this indicates that the external device has successfully stored the data an
70. trobe AS Indicates that a valid address is on the address bus Data Strobe DS During a read cycle DS indicates that an external device should place valid data on the data bus During a write cycle DS indicates that valid data is on the data bus Size SIZ1 SIZO Indicates the number of bytes remaining to be transferred for this cycle Read Write R N Indicates the direction of data transfer on the bus Interrupt Request Level IRQ7 IRQO Provides an interrupt priority level to the CPU Reset RESET System reset Halt HALT Suspend external bus activity Bus Error BERR Indicates that an erroneous bus operation is being attempted System Clockout CLKOUT Internal system clock Crystal Oscillator Connection for an external crystal to the internal oscillator circuit External Filter Capacitor XFC Connection pin for an external capacitor to filter the circuit of the phase locked loop Clock Mode Select MODCK Selects the source of the internal system clock Instruction Fetch FETCH Mise Ms Sr an instruction word pre fetch and when the Instruction Pipe IPIPE Used to track movement of words through the instruction pipeline Breakpoint BKPT Signals a hardware breakpoint to the CPU Freeze FREEZE Indicates that the CPU has acknowledged a breakpoint Quotient Out QUOT Serial and clock for background debug mode Test Mode Enable TSTME Hardware enable for test mode Three State Control TSC Places all output drivers in a high impedance state 4 1960332 memme 2
71. xternal assertion of the RESET input can overlap internally generated resets To insure that an external reset is recog nized in all cases RESET must be asserted for at least 590 CLKOUT cycles 14 External logic must pull RESET high during this period in order for normal MCU operation to begin 15 Address access time 2 5 WS Chip select access time 2 WS teye torsa topicu Where WS number of wait states When fast termination is used 2 clock bus WS 1 1568332 n Test Conditions Specific to the Device Time Definitions The times specified in Table 6 as dynamic characteristics are defined in Figure 4 to Fig ure 15 below by a reference number given the column of the tables together with the relevant figure number Figure 4 Clkout Output Timing Diagram Note Timing shown with respect to 20 and 70 Vpp Figure 5 External Input Timing Diagram EXTAL Note Timing shown with respect to 20 and 70 Vpp Pulse width shown with respect to 50 Figure 6 ECLK Output Timing Diagram ECLK Note Timing Shown With Respect To 20 And 7 AMEL 2118A HIREL 03 02 AMEL Figure 7 Read Cycle Timing Diagram 50 1 2 3 S4 S5 ast 8 Lj oie 18 TS68332 2118A HIREL 03 02 TS68332 Figure 8 Write Cycle Timing Diagram 50 51 52 S 54

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