ST TS616 handbook
Contents
1. Electrical characteristics TS616 Figure 8 Closed loop gain vs frequency Figure 9 Closed loop gain vs frequency Ay 4 Voc 2 5V Rp 91 00 Rg 300Q Ry 2100 Ay 4 Vec 2 5V Rip 1 kQ Rin 320 3600 R 2100 Voc 6V Ee Rg 560 3300 Ri 250 a _Voc 6V Fi 6200 Ri 360 2700 RI 25Q o gain gain 4 12 7 20 12 7 160 Vec 2 5V Vec 2 5V 10 phase 10 phase Vec 6V 40 Vcc 6V 4 180 8 8 20 A 200 B 6 Vcc 2 5V i 9 6 Vec 2 5V ER SS 440 9 7 220 9 wt Vcc 6V g q Vcc 6V S D a o a nd 60 a 4 240 0 on 0 260 2 2 100 280 4 4 120 300 100 ik 10k 100k 1M 10M 100M 100 ik 10k 100k 1M 10M 100M Frequency Hz Frequency Hz Figure 10 Closed loop gain vs frequency Figure 11 Closed loop gain vs frequency Ay 8 Voc 2 5V R2. 9 H gt OD Dz IS eal gt Spee HES gt b ra gt e s E Q ES o x El H gt r gt 2 ker o Es Q o 2 E lt a g gt OD 2 4 E F E 5 E 5 2 E n gt eoz H gt ea epa H gt za 4 mi eeu 5 gt H gt sa ees S 5 Ola Oo o 8 zx 3 a KI 21 37 Printed circuit board layout considerations TS616 Figure 58 Component locations top side Figure 59 Component locations bottom side El GE Ig 5 a RIT ran C IJ R216 C 7 ras 7 R220 C 7 J210 ra 020 EVAL616AA Figure 61 Bottom side board layout d 22 37 TS616 Noise measurements 7 Noise measurements The noise model is shown in Figure 62 where e eh input voltage noise of the amplifier e iNn negative input current noise of the amplifier e iNp positive input current noise of the amplifier Figure 62 Noise model output V HP3577 Input noise 8nV lHz
3. Ay 1 Vcc 2 5V Rip 1 kQ Rin 1 kQ R 102 H Vcc 6V Rp 680Q R n 6802 R 252 gain Vcc 6V lain o 20 0 160 E Vcc 2 5V ir Vec 2 5V e hose Jo ES phase Vec 6V 180 4 P 4 20 200 3 E Voo 2 5V Es 3 B E MI 4 40 6 20 9 8
4. Temperature C 450 20 Vec 6V 400 l Z 350 a 10 3 o 2 7i 0500 gt 05 55b 0 0 Vec 2 5V o 20 0 20 40 60 80 e 20 9 o 40 60 80 Temperature C Temperature C Figure 40 lout Vs temperature Figure 41 lout vs temperature Open loop Ver 6 V R 10 Q Open loop Vcc x2 5 V Rj 25 Q 300 300 250 250 200 P EE 200 150 150 100 Isource 100 50 50 Isource z z E 50 E 50 100 100 E 2 9 150 2 150 200 200 250 Isink 250 Isink 800 300 350 350 400 A i 400 PO AT M 450 450 40 20 0 20 40 60 80 40 20 0 20 40 60 80 Temperature C Temperature C Figure 42 CMR vs temperature Figure 43 SVR vs temperature Open loop no load Open loop no load 70 68 84 66 Vec 6V 64 82 Vec 6V m 9 a kJ L E 60 80 a a SCH 7 56 Vec 2 5V 78 52 76 Vec 2 5V 50 40 20 0 20 40 60 80 40 20 0 20 40 60 80 Temperature C d 15 37 Safe operating area TS616 4 16 37 Safe operating area Figure 44 shows the safe operating zone for the TS616 The curve shows the input level vs the input frequency a characteristic curve which must be considered in order to ensure a good application design In th
5. 370 kHz amp 400 kHz 370 kHz 8 400 kHz Ay 1 5 Rib 1kQ Voc 2 5 V Ri 14 Q diff Ay 1 5 Rip 1kQ Voc 2 5 V R 28 Q diff 30 30 40 40 50 50 o o IM2 M2 m gt 90 770kHz 30kHz gt 00 IM2 IM3 IM2 770kHz z 70 SE Zant y 3 70 LI 340ktiz 430kHz 30kHz S 80 N 80 ann 90 IM3 90 IM3 1140kHz 1170ktiz 1140kHz 1170kHz 100 100 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 Differential Output Voltage Vp p Differential Output Voltage Vp p Figure 48 Intermodulation vs gain Figure 49 Intermodulation vs load 370 kHz amp 400 kHz 370 kHz 8 400 kHz Vout 6 Von Voc 2 5 V R 20 Q diff Ay 1 5 Rip 1kQ Vout 56 Von Voc 2 5 V 30 30 40 40 IM3 IM3 50 340kHz 430kHz 1140kHz 1170kHz 50 340kHz 430kHz 1140kHz 1170kHz a 60 IM2 a 60 7 WG bed 30K 30kHz IM2 2 g E 7 770kHz ko 3 S o S 50 E 5 90 90 100 100 110 110 1 0 1 5 2 0 2 5 3 0 3 5 4 0 0 20 40 60 80 100 120 140 160 180 200 Closed Loop Gain Linear Differential Load Q 18 37 d TS616 Intermodulation distortion product Intermodulation vs output amplitude Figure 50 Figur
6. Figure 22 lj vs power supply Figure 23 Voy amp VoL VS power supply Open loop no load Open loop R 25 Q 7 6 B Vou lipt 4 6 ES JA S a 2 2 1 e o 2 8 1 Va 2 S lip 3 4 1 5 0 5 6 7 8 9 10 11 12 5 6 T 8 9 10 n 12 V V Vo V Figure 24 Isource VS output amplitude Figure 25 Isource VS output amplitude Voc 6 V open loop no load Voc 2 5 V open loop no load 700 700 600 600 _ 500 _ 500 q ki E E 400 400 3 300 3 300 2 2 200 200 100 100 0 0 0 1 2 3 4 5 6 0 0 0 5 1 0 1 5 2 0 2 5 Vout V Vout V 12 37 ky TS616 Electrical characteristics Figure 26 Lok vs output amplitude Figure 27 Lenk vs output amplitude Vcc 6 V open loop no load 0 100 200 300 400 Isink mA 500 600 6 5 4 3 2 1 0 Vout V Voc 2 5 V open loop no load 0 100 200 300 400 Isink mA 500 600 700 2 5 2 0 1 5 1 0 0 5 0 0 Vout V Figure 28 Maximum output amplitude vs load Figure 29 Bandwidth vs temperature Ay 4 Rp 620 Q Vcg 6 V
7. 130 10k 100k 1M 10M Frequency Hz Ky 27 37 Choosing the feedback circuit TS616 9 Choosing the feedback circuit As described in Figure 67 on page 29 the TS616 requires a 6202 feedback resistor to optimize the bandwidth with a gain of 12 dB for a 12 V power supply Nevertheless due to production test constraints the TS616 is tested with the same feedback resistor for 12 V and 5 V power supplies 910 9 Table 5 Closed loop gain feedback components Vcc V Gain Rip 9 1 750 2 680 4 620 se 8 510 1 680 2 680 4 620 8 510 1 1 1k 2 1k 4 910 sa 8 680 1 1k 2 1k 4 910 8 680 28 37 TS616 Choosing the feedback circuit 9 1 The bias of an inverting amplifier A resistance is necessary to achieve good input biasing such as resistance R shown in Figure 66 The magnitude of this resistance is calculated by assuming the negative and positive input bias current The aim is to compensate for the offset bias current which could affect the input offset voltage and the output DC component Assuming Ib Ib Rin Ry and a zero volt output the resistance R is R Rin Rip Figure 66 Compensation of the input bias current Rm 9 2 Active filtering Figure 67 Low pass active filtering Sallen
8. Ay 4 Rp 910 2 12 80 a _ Vec 6V Vec 6V Load 250 10 45 ca 8 40 eege TT ER gt R I 6 35 gt 4 Vec 2 5V 30 25 TRA 0 20 O T LL 9 d 0 50 100 150 200 40 20 0 20 40 60 80 Ri ap 2 Temperature C Figure 30 Transimpedance vs temperature Figure 31 Icc vs temperature Open loop 30 25 20 40 20 0 20 40 60 80 Temperature C Open loop no load 14 ESS e n n 12 2 Icc for Vec 2 5V 6 Icc for Vec 6V 4 T 2 E o 32 4 6 Icc for Vcc x6V 9 lcc for Vcc x2 5V 10 12 14 40 20 0 20 40 60 80 Temperature C d 13 37 Electrical characteristics TS616 Figure 32 Slew rate vs temperature Figure 33 Slew rate vs temperature Ay 4 Rp 910 Q Voc 6 V R 25 Q Ay 4 Rp 910 Mee 2 5 V Rj 10 Q 600 200 A 2 A 150 400 1 300 100 T 200 Positive SR 50 100 Positive amp Negative SH Positive amp Negative SR 2 9 o R
9. Table 4 Vec 2 5 V Rp 910 Q Tamp 25 C unless otherwise specified continued Symbol Parameter Test conditions Min Typ Max Unit Noise and distorsion eN Equivalent input noise voltage F 100kHz 2 5 nV VHz iNp oo input noise current F 100kHz 15 pANHz iNn SEH input noise current F 100kHz 21 pANHz 2nd harmonic distortion Vout Bop Ay 12 dB SS differential configuration F 110kHz R 20 Q diff Si SES 3rd harmonic distortion Vout Don Ay 12dB HDS differential configuration F 110 kHz R 202 diff 29 SS F1 100 kHz F2 110 kHz Vout 6 Vp p Ay 12dB 86 2nd order intermodulation Ee 202 dift IM2 product dBc differential configuration F1 370kHz F2 400kHz Vout 6Vp p Ay 12dB 88 D 202 diff F1 100kHz F2 110kHz Vout 6Vp p Ay 12dB 90 3rd order intermodulation SC 200 ditt IM3 product dBc differential configuration F1 370kHz F2 400kHz Vout 6Vp p Ay 12dB 85 D 202 diff 8 37 ky TS616 Electrical characteristics Figure 2 Load configuration Figure 3 Load configuration R 252 R 25 Q Vcc 6 V Vcc 5V 6V 502 502 Q cable cable 49 90 250 d 330 500 500 Dev w V V V Figure 4 Closed loop gain vs frequency Figure 5 Closed loop gain vs frequency Ay 1 Voc 2 5V Rp 1 1 kQ R 102 Voc 6V Rip 7500 R 250
10. N2 R2 The closed loop gain is The six noise sources are R2 Vi eNx 1 eNx 1 22 V2 iNnx R2 R2 V3 iNpx R3x 1 iNp x x 5 V4 x V4kTR1 V5 J4kTR2 V6 1 Be AKTRS We assume that the thermal noise of a resistance R is V4kTRAF where AF is the specified bandwidth On a 1 Hz bandwidth the thermal noise is reduced to V4kTR where k is Boltzmann s constant equal to 1374 1028J K T is the temperature K 23 37 Noise measurements TS616 7 1 24 37 The output noise eNo is calculated using the Superposition Theorem However eNo is not the sum of all noise sources but rather the square root of the sum of the square of each noise source as shown in Equation 1 Equation 1 Yo V1 4 v2 4 va A v4 4 v5 4 V6 Equation 2 No eN x g iNn x R2 iNp x RS x g 2 2 E At x 4kTR1 4kTR2 1 Be x 4kTR3 The input noise of the instrumentation must be extracted from the measured noise value The real output noise value of the driver is Equation 3 eNo Measured instrumentation The input noise is called the Equivalent Input Noise as it is not directly measured but is evaluated from the measurement of the output divided by the closed loop gain eNo g After simplification of the fourth and the fifth term of Equation 2 we obtain Equation 4 2 eN x g iNn x R2 A iNp x R3 x g gx 4KTR2 1 fe x
11. AYI TS616 Dual wide band operational amplifier with high output current Features Low noise 2 5 nVWHz m High output current 420 mA m Very low harmonic and intermodulation distortion m High slew rate 420 V us m 3dB bandwidth 40 MHz gain 12 dB on 25 Q single ended load W 20 7 Vp p differential output swing on 50 2 load 12 V power supply m Current feedback structure m 5Vto 12 V power supply m Specified for 20 O and 50 Q differential load Applications m Line driver for xDSL m Multiple video line driver Description The TS616 is a dual operational amplifier featuring a high output current of 410 mA This driver can be configured differentially for driving signals in telecommunication systems using multiple carriers The TS616 is ideally suited for xDSL high speed asymmetrical digital subscriber line applications This circuit is capable of driving a 10 Q or 25 Q load on a range of power supplies 32 5 V 5 V 16 V or 12 V The TS616 is capable of reaching a 3 dB bandwidth of 40 MHz on 25 O load with a 12 dB gain This device is designed for high slew rates and demonstrates low harmonic distortion and intermodulation September 2008 SO 8 Exposed pad Plastic micropackage Pin connections top view Output VCC Inverting Input1 Output2 Non Inverting Input1 VCC Inverting Input2 Non Inverting Input2 dice Cross Section View Showing Exposed Pad This
12. 30 lips Positive input bias current uA Tmin lt Tamb lt Tmax 7 Tamb 1 1 11 lip Negative input bias current pA Tmin lt Tamb lt Tmax 1 2 Zin Input impedance 71 kQ Ziy Input impedance 62 Q Cina Input capacitance 1 5 pF C d jecti ti AVig 1V 55 61 CMR ommon mode rejection ratio ic dB 20 log AV AV 9 Tone Taib Tmax 60 BUB Supply voltage rejection ratio AVcc 2V to 2 5V 63 79 P 20 log AV c AVio Tae Tan Tmax 78 l g Total supply current per No load 11 5 15 MA operator Dynamic performance and output characteristics Vout 2Vp p RL 100 2 4 2 Rot Open loop transimpedance MQ Tmin lt Tamb lt Tmax 1 5 E Small signal Vout lt 20mVp 3dB bandwidth Ay 12dB R 100 20 28 MHZ BW Full power bandwidth Latge signal Va EE 20 D 102 Small signal Vouts 20mVp Gain flatness 0 1dB Ay 12dB Ri 100 5 7 MHz T Rise time Vout 2 8Vp p Ay 12dB R 102 11 ns Tr Fall time Vout 2 8Vp p Ay 12dB R 102 11 5 ns Tg Settling time Vout 2 2Vp p Ay 12dB R 10 39 ns SR Slew rate Vout 2 2Vp p Ay 12dB R 102 100 130 V us Vou High level output voltage R 210 connected to GND 1 5 1 7 V VoL Low level output voltage R 210 connected to GND 1 9 1 7 V Vout 1 25V 300 400 Output sink current Tmin lt Tamb lt Tmax 360 lout mA Vout 1 25Vp 200 270 Output source current Tmin lt Tamb lt Tmax 240 ky 7 37 Electrical characteristics TS616
13. 4Vp 320 490 Output sink current Tmin lt Tamb lt Tmax 395 lout mA Vout 4Vp 330 420 Output source current T min lt Tamb lt Tmax 370 Noise and distortion eN Equivalent input noise voltage F 100kHz 2 5 nV VHz iNp Equivalent input noise current F 100kHz 15 pA VHz iNn Equivalent input noise current F 100kHz 21 pA VHz 2nd harmonic distortion Vout 14Vp p Ay 12dB k SES differential configuration F 110kHz R 502 diff a SES 3rd harmonic distortion Vout 14Vp p Ay 12dB E SES differential configuration F 110kHz R 502 diff 83 dec F1 100kHz F2 110kHz Vout 16Vp p Ay 12dB 76 we 2nd order intermodulation product RL 502 diff dBc differential configuration F1 370kHz F2 400kHz Vout 16Vp p Ay 12dB 75 RL 502 diff F1 100kHz F2 110kHz Vout 16Vp p Ay 12dB 88 IM3 3rd order intermodulation product RL 500 diff dBc differential configuration F1 370kHz F2 400kHz Vout 16Vp p Ay 12 B 87 RL 502 diff 6 37 ky TS616 Electrical characteristics Table 4 Vec 22 5 V Rip 910 Q Tamb 25 C unless otherwise specified Symbol Parameter Test conditions Min Typ Max Unit DC performance Tamb 0 2 2 5 Vio Input offset voltage pal mV Tmin Tamb lt Tmax 1 AV _ Differential input offset voltage Tamb 25 C 2 5 mV Tamb 4
14. 4k Measurement of eN If we assume a short circuit on the non inverting input R3 0 Equation 4 becomes Equation 5 No JeN x g iNn x R2 gx 4kTR2 In order to easily extract the value of eN the resistance R2 will be chosen as low as possible On the other hand the gain must be large enough e Ri 10Q R2 910 Q R3 0 Gain 92 e Equivalent input noise 2 57 nV VHz e Input voltage noise eN 2 5 nV VHz TS616 Noise measurements 7 2 Measurement of Nn To measure the negative input current noise iNn we set R3 0 and use Equation 5 This time the gain must be lower in order to decrease the thermal noise contribution e Ri 100Q R2 910Q R3 0 gain 10 1 e Equivalent input noise 3 40 nVWHz e Negative input current noise iNn 221 pA VHz 7 3 Measurement of iNp To extract iNp from Equation 3 a resistance R3 is connected to the non inverting input The value of R3 must be chosen in order to keep its thermal noise contribution as low as possible against the iNp contribution R1 100 Q R2 910 Q R3 100 Q Gain 10 1 Equivalent input noise 3 93 nV VHz Positive input current noise Np 15 pA VHz Conditions Frequency 100 kHz Voc 2 5 V Instrumentation HP3585A Spectrum Analyzer the input noise of the HP3585A is 8 nV VHz 25 37 Power supply bypassing TS616 8 8 1 26 37 Power supply bypassing Correct power supply bypassing is very important for optimizing performance in high frequency ranges Bypass
15. INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2008 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 37 37 K
16. Key Ci Ri R2 e IN Ca OUT V 250 iva R o Ra 9100 From the resistors Rp and Rg we can directly calculate the gain of the filter in a classic non inverting amplification configuration Rip Rg Ay 9 1 We assume the following expression as the response of the system 8 Vout 8 g lo Vin 142012 dol M a KI 29 37 Choosing the feedback circuit TS616 The cutoff frequency is not gain dependent and so becomes 1 JR1R2C1C2 The damping factor is calculated by the following expression Q 1 Ge 24 CiR C R C R C R g The higher the gain the more sensitive the damping factor is When the gain is higher than 1 it is preferable to use some very stable resistor and capacitor values In the case of R1 R2 Rip A Yonn 30 37 ky TS616 Increasing the line level using active impedance matching 10 Increasing the line level using active impedance matching With passive matching the output signal amplitude of the driver must be twice the amplitude on the load To go beyond this limitation an active matching impedance can be used With this technique it is possible to maintain good impedance matching with an amplitude on the load higher than half of the output driver amplitude This concept is shown in Figure 68 for a differential line Figure 68 TS616 as a differential line driver with active im
17. capacitors should be placed as close as possible to the IC pins to improve high frequency bypassing A capacitor greater than 1 F is necessary to minimize the distortion For better quality bypassing a capacitor of 10 nF is added using the same implementation conditions Bypass capacitors must be incorporated for both the negative and the positive supply Figure 63 Circuit for power supply bypassing Vcc Single power supply The TS616 can operate with power supplies ranging from 12 V to 5 V The power supply can either be single 12 V or 5 V referenced to ground or dual such as 6 V and 2 5 V In the event that a single supply system is used new biasing is necessary to assume a positive output dynamic range between 0 V and Vcc supply rails Considering the values of Voy and VoL the amplifier will provide an output dynamic from 0 5 V to 10 6 V on 25 Q load for a 12 V supply and from 0 45 V to 3 8 V on 10 Qload for a 5 V supply The amplifier must be biased with a mid supply nominally Vcc 2 in order to maintain the DC component of the signal at this value Several options are possible to provide this bias supply such as a virtual ground using an operational amplifier or a two resistance divider which is the cheapest solution A high resistance value is required to limit the current consumption On the other hand the current must be high enough to bias the non inverting input of the am
18. diff Voc 6V Ct AAA A A A A o IM3 90kHz 120kHz 310kHz 320kHz n o IM2 210kHz d IM2 and IM3 dBc 3 E Q eo o 6 8 10 12 14 16 18 20 22 Differential Output Voltage Vp p m ES Intermodulation vs frequency range Figure 54 Ay 4 Rip 620 kQ R 50 Q diff Vout 16 Vpp Voc 6 V 60 Quadratic Summation of all IM2 and IM3 components generated by each two tones signal 65 70 f1 100kHz 75 H f2 110kHz f1 1MHz 7 f1 400kHz 12 1 1MHz m 80 f1 200kHz H f2 430kHz 3 12 230kHz 85 90 95 100 100k 200k 300k 400k 500k 600k 700k 800k 900k 1M 1 1M Frequency Hz ky 19 37 Printed circuit board layout considerations TS616 6 Printed circuit board layout considerations In the ADSL frequency range printed circuit board parasites can affect the closed loop performance The use of a proper ground plane on both sides of the PCB is necessary to provide low inductance and a low resistance common return The most important factors affecting gain flatness and bandwidth are stray capacitance at the output and inverting input To minimize capacitance the space between
19. pad must be connected to a Vcc copper area on the PCB 1 37 www st com Contents TS616 Contents 1 Typical application weu NN NNN ew eee eee ee montem m mmm m nnm 3 2 Absolute maximum ratings and operating conditions 4 3 Electrical characteristics 5 4 Safe operating area o ooocoooooccoc ana 16 5 Intermodulation distortion product 2ssssssrnnn n 17 6 Printed circuit board layout considerations 20 6 1 Thermal information 20 7 Noise measurements 00 cece eee eene 23 7 1 Measurement Of eN 24 7 2 Measurement of Nn aaa aaa n na nn nn ana 25 7 3 Measurement or IND degt Rock EEN ESA tee eek ee tees aa a 25 8 Power supply bypassing eee BB 26 8 1 Single power supply ki 532 kt diri n dj ira oi 26 8 2 Channel separation and crosstalk 27 9 Choosing the feedback circuit st anan nn na nannan 28 9 1 The bias of an inverting amplifier eeeeeooooon 29 9 2 Active tilterning wes caravista 29 10 Increasing the line level using active impedance matching 31 11 Package information vg eeh EEN ee NR RR RR COR Bee e a 34 12 Ordering information tat knn n nn n nn a wan nn n nan nn nn an 36 13 Revision history is ENNER EE Ee e ERR a ee a n 36 2137 kI TS616 Typical application 1 Typical application Figure 1 shows a schematic of a typical xDSL application using the TS616 Fig
20. 616 11 34 37 Package information In order to meet environmental requirements ST offers these devices in ECOPACK packages These packages have a Lead free second level interconnect The category of second level interconnect is marked on the package and on the inner box label in compliance with JEDEC Standard JESD97 The maximum ratings related to soldering conditions are also marked on the inner box label ECOPACK is an ST trademark ECOPACK specifications are available at www st com TS616 Package information Figure 71 SO 8 exposed pad package mechanical drawing SEATING La hx45 Table 7 SO 8 exposed pad package mechanical data Dimensions Millimeters Inches Ref Min Typ Max Min Typ Max A 1 350 1 750 0 053 0 069 Al 0 000 0 150 0 001 0 0059 A2 1 100 1 650 0 043 0 065 B 0 330 0 510 0 013 0 020 0 190 0 250 0 007 0 010 D 4 800 5 000 0 189 0 197 D1 3 10 0 122 E 3 800 4 000 0 150 0 157 El 2 41 0 095 e 1 270 0 050 H 5 800 6 200 0 228 0 244 h 0 250 0 500 0 010 0 020 L 0 400 1 270 0 016 0 050 k Od 8d Od 8d ddd 0 100 0 004 Y 35 37 Ordering information TS616 12 Ordering information Table 8 Order codes Part number Temperature range Package Packaging Marking TS616ID
21. A Tmin lt Tamb lt Tmax 7 2 Tamb 3 15 lip Negative input bias current UA T min lt Tamb lt Tmax 3 1 ZiN Input impedance 82 kQ Zin Input impedance 54 Q Ci Input capacitance 1 pF us Common mode rejection ratio AVic 4 5V 58 64 di 20 log AVig AVio Tone Tamb Tmax 62 BUR Supply voltage rejection ratio AV co 2 5V to 6V 72 81 di 20 log AVcc AVio Taie ai lt Tmax 80 loc Total supply current per operator No load 13 5 17 mA Dynamic performance and output characteristics Vout 7Vp p Du 252 5 13 5 Rot Open loop transimpedance MQ Tmin lt Tamb lt Tmax 5 7 a Small signal Vo lt 20mVp 3dB bandwidth Ay 12dB R 250 25 40 MHz Large signal Vout 3Vp BW Full power bandwidth Ay 12dB R 250 26 Small signal Tamp 20mVp Gain flatness 0 1dB Ay 12dB R 250 7 MHz Tr Rise time Vout 6Vp p Ay 12dB R 252 10 6 ns Ty Fall time Vout 6Vp p Ay 12dB Ry 252 12 2 ns Ts Settling time Vout 6Vp p Ay 12dB Ry 25Q 50 ns SR Slew rate Vout 6Vp p Ay 12dB R 252 330 420 V us Vou High level output voltage R 252 connected to GND 4 8 5 05 V VoL Low level output voltage RL 252 Connected to GND 5 3 5 1 V ky 5 37 Electrical characteristics TS616 Table 3 Vec 6 V Be 910 Q Tamp 25 C unless otherwise specified continued Symbol Parameter Test conditions Min Typ Max Unit Vout
22. Vcc 6V 8 Vcc s6V 2 EI a EI a 10 60 77 40 240 12 80 12 260 2 100 R 280 16 16 120 3 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M Frequency Hz Frequency Hz Figure 6 Closed loop gain vs frequency Figure 7 Closed loop gain vs frequency Ay 2 Voc t2 5V Rp 1 kQ Ri 100 Ay 2 Vec 2 5V Rip 1 kQ Rin 51 00 Ri 1 oQ Voc 6V Rip 6800 R 250 Voc 6V Ri 6809Q Rin 750 6200 R 252 40 8 140 gain de gain 6 7 20 8 160 TA Vcc 2 5V 4 phase Vcc 2 5V 4 phase 40 Vcc 6V 180 2 gt 2 a 0 Vcc 2 5V 20 z a l RESCH 200 2 S Ja g e 220 8 Vec 6V S 52 Vcc 6V S Oo a o a Self 60 TT s 240 6 80 6 260 S 100 E 280 10 10 120 300 100 1k 10k 100k 1M 10M 100M 100 ik 10k 100k 1M 10M 100M Frequency Hz Frequency Hz ky 9 37
23. W Tube TS616 40 C to 85 C SO 8 TS616IDWT Tape amp reel TS616 13 Revision history Date Revision Changes 1 Nov 2002 1 First release Moved note in Table 3 to Section 9 Choosing the feedback circuit on page 28 Figure 43 in Revision 1 entitled Group Delay has been removed because the results presented were not technically meaningful Simplified mathematical representations of the intermodulation 03 Dec 2004 2 product in Section 5 Intermodulation distortion product on page 17 In Section 6 Printed circuit board layout considerations on page 20 change from The copper area can be connected to Vcc available on pin 4 to The copper area must be connected to Vcc available on pin 4 In Section 9 1 The bias of an inverting amplifier on page 29 change of section title and correction of referred figure to Figure 66 Format update 24 Oct 2006 3 Corrected package mechanical data for SO 8 exposed pad 16 Apr 2007 4 Corrected package error in Table 8 Order codes 26 Sep 2008 5 Corrected package error in Table 8 Order codes 36 37 d TS616 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s t
24. dentification of both Equation 7 and Equation 8 the synthesized impedance is with Rs1 Rs2 Rs Equation 9 Rs Ro R2 R3 32 37 DI TS616 Increasing the line level using active impedance matching Figure 70 Equivalent schematic Ro is the synthesized impedance Ro lout I Vi Gi O 1 2RL Let us write Vo kVo where k is the matching factor varying between 1 and 2 If we assume that the current through R3 is negligible we can calculate the output resistance Ro kVoRL Ro KVORL_ RL 2Rs1 After choosing the k factor Rs will be equal to 1 2RL k 1 For a good impedance matching we assume that Equation 10 1 Ro AL From Equation 9 and Equation 10 we derive Equation 11 R2 _ _ 2RS R3 RL By fixing an arbitrary value of R2 Equation 11 becomes R2 R3 gt ans RL Finally the values of R2 and R3 allow us to extract R1 from Equation 6 so that Equation 12 2R2 R2 R2 ASE A e Aa R3 Ri with GL the required gain Table 6 Components calculation for impedance matching implementation GL is fixed for the application requirements GL Vo Vi 0 5 1 2R2 R1 R2 R3 1 R2 R3 GL gain for the loaded system R1 2R2 2 1 R2 R3 GL 1 R2 R3 R2 R4 Arbitrarily fixed R3 R5 R2 1 Rs 0 5RL Rs 0 5RL k 1 Load viewed by each driver kRL 2 33 37 Package information TS
25. e This is done for all couples of connected pin combinations while the other pins are floating 5 Machine model a 200 pF capacitor is charged to the specified voltage then discharged directly between two pins of the device with no external series resistor internal resistor lt 5 This is done for all couples of connected pin combinations while the other pins are floating 6 Charged device model all pins and the package are charged together to the specified voltage and then discharged directly to the ground through only one pin This is done for all pins 7 An output current limitation protects the circuit from transient currents Short circuits can cause excessive heating Destructive dissipation can result from short circuits on amplifiers Table 2 Operating conditions Symbol Parameter Value Unit Voc Power supply voltage 2 5 to 6 V Vicm Common mode input voltage Vcc 1 5 V to Voec 1 5 V V d TS616 Electrical characteristics 3 Electrical characteristics Table 3 Vec 6 V Be 910 Q Tamp 25 C unless otherwise specified Symbol Parameter Test conditions Min Typ Max Unit DC performance Tamb 1 3 5 Vio Input offset voltage mV Tmin lt Tamb lt Tmax 1 6 AVio Differential input offset voltage Tamb 25 C 2 5 mV Tamb 5 30 libs Positive input bias current y
26. e s Figure 16 Negative slew rate Figure 17 Negative slew rate Ay 4 Rp 620 Q Vec 6 V R 25 Q Ay 4 Rp 910 Q Voc 2 5 V R 10 Q 4 2 2 1 5 0 5 0 gt gt 2 1 4 2 0 0 10 0n 20 0n 30 0n 40 0n 50 0n 0 0 10 0n 20 0n 30 0n 40 0n 50 0n Time s Time s Figure 18 Negative slew rate Figure 19 Negative slew rate Ay 4 Rip 620 Q Vcc 6 V R 25 Q Ay 4 Rp 2 910 Q Voc 2 5 V R 10 Q l 2 2 g 3 ER gt 3 gt 2 4 0 0 10 0n 20 0n 30 0n 40 0n 50 0n 2 0 0 10 0n 20 0n 30 0n 40 0n 50 0n Time s Time s d 11 37 Electrical characteristics TS616 Figure 20 Input voltage noise level Figure 21 Icc vs power supply Ay 92 Rp 910 Q Input connected to GND via 25 Q 5 0 c 6V z Output 4 5 4 0 q 3 5 3 0 nput Voltage Noise nV VHz 2 5 100 1k 10k 100k 1M Frequency Hz Open loop no load 30 20 Icc 10 E o o A 10 20 Icc 30 0 1 2 3 4 5 6 7 8 9 10 11 12 Voc V
27. e 51 Intermodulation vs output amplitude 370 kHz amp 400 kHz Ay 4 Rp 620 kQ R 200 Q diff Voc 6 V 30 370 kHz amp 400 kHz Ay 4 Rp 620 kQ R 50 Q diff Voc 6 V 30 IM2 A 40 30kHz IM2 50 IM2 770kHz 50 IM3 IM2 E 30kHz gt 1140kHz 1170kHz 770kHz 3 60 IM3 B ou T 1140kHz 1170kHz V e 340kHz 430kHz 70 70 t z K B FE S 80 340kHz 430kHz S 80 y a 90 90 100 100 110 He 0 2 4 6 8 10 12 14 16 18 20 22 0 2 4 6 8 10 12 14 16 18 20 22 Differential Output Voltage Vp p Differential Output Voltage Vp p Figure 52 Intermodulation vs output Figure 53 Intermodulation vs output amplitude amplitude 100 kHz 8 110 kHz Ay 4 R o 620 kQ R 200 Q diff Voc 6 V EE 40 50 IM3 90kHz 120kHz IM2 210kHz o o a IM3 320kHz o o IM2 and IM3 dBc ad o o 100 2 4 6 8 10 12 14 16 18 20 22 Differential Output Voltage Vp p 100 kHz 8 110 kHz Ay 4 Rp 620 kQ R 50 Q
28. e dash lined zone the consumption increases and this increased consumption could do damage to the chip if the temperature increases Figure 44 Safe operating area 700 Vec 6V 600 h Ta 25 C G 12dB T R 1000 H gt E 400 5 SAFE 300 OPERATING AREA 200 100 0 1M 10M 100M Frequency Hz TS616 Intermodulation distortion product Intermodulation distortion product The non ideal output of the amplifier can be described by the following series due to a non linearity in the input output amplitude transfer 2 Vout Co C y Vin CoVin CpVin n where the single tone input is V Asinat and Cg is the DC component C V is the fundamental C is the amplitude of the harmonics of the output signal Voy A one frequency one tone input signal contributes to a harmonic distortion A two tone input signal contributes to a harmonic distortion and an intermodulation product This intermodulation product or rather the study of the intermodulation distortion of a two tone input signal is the first step in characterizing the amplifiers capability for driving multi tone signals The two tone input is equal to Vin Asin t Bsinoyt giving t Co C4 Asina t Bsinw t C Asina t Dana A C Asina t Bsinat In this expression we can extract distortion terms a
29. erms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL
30. fb 6200 R b 9100 2 o bai ba 100 g 3 50 o 200 a Negative SR 300 100 400 AA AAA ls RV 150 800 gt 600 200 40 20 0 20 40 60 80 40 20 0 20 40 60 80 Temperature C Temperature C Figure 34 lip vs temperature Figure 35 lip vs temperature Open loop no load lw HA lag HA Open loop no load 5 Vcc 6V Vec 2 5V Vec 2 5V 1 1 EA 1 0 40 20 0 20 40 60 80 40 20 0 20 40 60 80 Temperature C Temperature C Figure 36 Voy VS temperature Figure 37 Vo vs temperature Open loop Open loop 0 Vcc 2 5 1 Load 100 2 S s z ER gt gt 4 Vec 6V Load 259 5 Vcc x2 5 Load 100 Lu 20 0 20 40 60 80 Sa 20 0 20 40 60 80 Temperature C Temperature C 14 37 ky TS616 Electrical characteristics Figure 38 Differential V vs temperature Figure 39 Vio vs temperature Open loop no load Open loop no load
31. nd intermodulation terms from a single sine wave second order intermodulation terms IM2 by the frequencies a and y 0 with an amplitude of C2A and third order intermodulation terms IM3 by the frequencies 20 20 09 Lo 2 and y 2 with an amplitude of 3 4 C3A We can measure the intermodulation product of the driver by using the driver as a mixer via a summing amplifier configuration In doing this the non linearity problem of an external mixing device is avoided Figure 45 Non inverting summing amplifier for intermodulation measurements 1kQ 49 90 Vin1 Vini 3000 v2 1 1 2 out am 1000 SE 502 Rout2 L1 Y 49 90 49 90 1kQ ei j e Vcc 1kQ e Fe 49 90 V 17 37 Intermodulation distortion product TS616 The following graphs show the IM2 and the IM3 of the amplifier in different configurations The two tone input signal was generated by the multisource generator Marconi 2026 Each tone has the same amplitude The measurement was performed using a HP3585A spectrum analyzer Intermodulation vs output amplitude Figure 46 Figure 47 Intermodulation vs output amplitude
32. p 6802 Rg 240 1 602 R 10Q Ay 8 Voc 2 5V Rp 6802 R n 160 1800 R 210 a Vco 8V Rip 5100 Rg 270 1002 Ry 25Q oo _ Voc 6V Rg 5100 Rip 150 1100 Rj 25Q gain gain 19 F 20 18 J 160 16 ase Ve Sa 16 n Vec 2 5V p Voc 6V Jo pnase VoccaGV J 180 14 14 D 12 Vcc 2 5V 19 e a d SE q 200 2 2 Veo s6V fr 1 8 10 GE Steeg D a Oo a 8 60 Re 4 240 6 4 80 6 Y 260 4 100 4 280 2 2 120 300 100 ik 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M Frequency Hz Frequency Hz Figure 12 Positive slew rate Figure 13 Positive slew rate Ay 4 Rp 9102 Voc 6 Rj 250 Ay 4 Rip 910 Q Voc 2 5V R 102 4 2 2 1 S s HE 8 gt gt 2 1 BC 10 0n 20 0n 30 0n 40 0n 50 0n E 10 0n 20 0n 30 0n 40 0n 50 0n Time s Time s 10 37 TI TS616 Electrical characteristics Figure 14 Positive slew rate Figure 15 Positive slew rate Ay 4 Rp 620 Q Voc 6 V R 25 Q 4 Ay 4 Rip 910 Q Vec 2 5 V R 10 Q 2 2 1 s S 50 gt gt 2 1 4 2 0 0 10 0n 20 0n 30 0n 40 0n 50 0n 0 0 10 0n 20 0n 30 0n 40 0n 50 0n Time s Tim
33. pedance matching 100n ete A KN 1k Vi eee Vi Hou Togo e e GND y e e 100n 1 n Hybrid amp 100 Transformer Component calculation Let us consider the equivalent circuit for a single ended configuration as shown in Figure 69 Figure 69 Single ended equivalent circuit Vi Ve R1 Rs1 R2 R3 Vo 1 2 RL 31 37 Increasing the line level using active impedance matching TS616 First let s consider the unloaded system We can assume that the currents through R1 R2 and R3 are respectively 2Vi Vi Vo9 Vi Vo Di R2 and ag As Vor equals Vo without load the gain in this case becomes G Vo noload _ Ri R3 Vi The gain for the loaded system is given by Equation 6 Equation 6 2R2 R2 GL Vo withload _ 1_ Ri R3 7 Vi a R R3 The system shown in Figure 70 is an ideal generator with a synthesized impedance acting as the internal impedance of the system From this the output voltage becomes Equation 7 Vo ViG Ro lout where Ro is the synthesized impedance and lout the output current On the other hand Vo can be expressed as Equation 8 2R2 R2 vi 1 TL 2 R1 R3 Rsilout 1 R2 1 R2 R3 R3 Vo By i
34. plifier If we consider this bias current 30 pA max as the 196 of the current through the resistance divider to keep a stable mid supply two resistances of 2 2 kQ can be used in the case of a 12 V power supply and two resistances of 820 O can be used in the case of a 5 V power supply The input provides a high pass filter with a break frequency below 10 Hz which is necessary to remove the original 0 volt DC component of the input signal and to fix it at Vcc 2 Figure 64 shows a schematic of a 5 V single power supply configuration TS616 Power supply bypassing Figure 64 Circuit for 5 V single supply 5V 10uF IN 100uF Bin M our AEN 1kQ 102 R1 8202 E V 1 Rib 114F fone 8200 Ca 8 2 Channel separation and crosstalk Figure 65 shows an example of crosstalk from one amplifier to a second amplifier This phenomenon accentuated at high frequencies is unavoidable and intrinsic to the circuit itself Nevertheless the PCB layout also has an effect on the crosstalk level Capacitive coupling between signal wires distance between critical signal nodes and power supply bypassing are the most significant factors Figure 65 Crosstalk vs frequency Ay 4 Rfy 620 Q Vcc 6 V Vout 2 Vp 50 60 70 80 90 100 CrossTalk dB 110 120
35. signal lines and ground plane should be maximized Feedback component connections must be as short as possible in order to decrease the associated inductance which affects high frequency gain errors It is very important to choose the smallest possible external components for example surface mounted devices SMD in order to minimize the size of all DC and AC connections 6 1 Thermal information The TS616 is housed in an exposed pad plastic package As described in Figure 55 this package has a lead frame upon which the dice is mounted This lead frame is exposed as a thermal pad on the underside of the package The thermal contact is direct with the dice This thermal path provides an excellent thermal performance The thermal pad is electrically isolated from all pins in the package It must be soldered to a copper area of the PCB underneath the package Through these thermal paths within this copper area heat can be conducted away from the package The copper area must be connected to Vcc available on pin 4 Figure 55 Exposed pad package Figure 56 Evaluation board ES S J205 4206 4207 4208 J209 a Emu Culm bz m MSS mm Side View Bottom View Sat K a d Cross Section View 20 37 ky TS616 Printed circuit board layout considerations Figure 57 Schematic diagram
36. ure 1 Differential line driver for xDSL applications kI 3 37 Absolute maximum ratings and operating conditions TS616 2 4 37 Absolute maximum ratings and operating conditions Table 1 Absolute maximum ratings Symbol Parameter Value Unit Voc Supply voltage 1 7 V Vid Differential input voltage 2 V Vin Input voltage range 3 6 V Toper Operating free air temperature range 40 to 85 C Tag Storage temperature 65 to 150 C Tj Maximum junction temperature 150 C Rthic Thermal resistance junction to case 16 C W Rihja Thermal resistance junction to ambient area 60 C W P Maximum power dissipation at Tamp 25 C for 2 w max Tj 150 C ESD HBM human body model 1 5 kV only pins MM machine model 2 kV 1 4 7 8 CDM charged device model 200 V ESD HBM human body model 1 5 kV only pins MM machine model 2 kV 2 3 5 6 CDM charged device model 100 V Output short circuit 7 P WN The magnitude of input and output voltage must never exceed Voc 0 3 V All voltage values except differential voltage are with respect to network terminal Differential voltages are non inverting input terminal with respect to the inverting input terminal Human body model a 100 pF capacitor is charged to the specified voltage then discharged through a 1 5 KQ resistor between two pins of the devic
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