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TEXAS INSTRUMENTS ADS1218 handbook

1. 25 ADS1218 40 5 27 SBAS187 INSTRUMENTS PACKAGE DRAWING MTQF019A JANUARY 1995 REVISED JANUARY 1998 S PQFP G48 PLASTIC QUAD FLATPACK 0 13 NOM 1 12 m 5 50 TYP 7 20 6 80 50 e Planet 8 80 0 05 MIN Seating Plane t A 0 08 1 20 MAX 4073176 B 10 96 NOTES A Alllinear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 026 28 49 5 ADS1218 INSTRUMENTS SBAS187 X3 Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 3 Oct 2003 PACKAGING INFORMATION ORDERABLE DEVICE STATUS 1 PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY ADS1218Y 250 ACTIVE TQFP PFB 48 250 ADS1218Y 2K ACTIVE TQFP PFB 48 2000 1 The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetim
2. 4 Eee lacu 6 nl licEudeldeule meec u 7 TYPICAL CHARACTERISTICS 8 e d d ias HOURS 12 15 REGISTER BANK TOPOLOGY 15 DETAILED REGISTER DEFINITIONS unma a RR 4444 UAR nunnana nunnana nnna nna 17 COMMAND DEFINITIONS 2 5 19 ADS1218 COMMAND RD nunne NR RISE AR RR R NR 24 SERIAL PERIPHERAL cad ac nura minu auda anne opua 25 DIGITAL INTE REA GE 25 DEFINITION OF
3. 0 1 1 5 Vper PGA OFFSET DAC Offset DAC Range Offset DAC Monotonicity Offset DAC Gain Error Offset DAC Gain Error Drift Vper 2 PGA 10 1 Bits 96 SYSTEM PERFORMANCE Resolution No Missing Codes Integral Non Linearity Offset Error Offset Drift Gain Error Gain Error Drift Common Mode Rejection Normal Mode Rejection Output Noise Power Supply Rejection sinc End Point Fit Before Calibration After Calibration at DC fom 60Hz fpata 10Hz fom 50Hz fparA 50Hz fom 60Hz fpata 60Hz 50 50 2 fgig 60Hz 60Hz 7 5 0 02 0 005 0 5 130 120 120 100 100 Bits 24 Bits 10 0015 96 of FS ppm of FS ppm of FS C 96 ppm C dB dB dB dB dB dB See Typical Characteristics at DC dB 20 log AVoyr AVpp 2 49 5 INSTRUMENTS 95 dB ADS1218 SBAS187 ELECTRICAL CHARACTERISTICS AVpp 5V Cont All specifications Tmn to Tmax AVpp 5 DVpp 2 7 to 5 25V 19 2kHz fosc 2 4576MHz PGA 1 Buffer ON 150kQ fpArA 10 2 Veger REF IN REF 1 2 5V unless otherwise specified ADS1218 PARAMETER CONDITIONS MIN MAX VOLTAGE REFERENCE INPUT Reference Input Range VREF Common Mode Rejection Common Mode Rejection Bias Current REF IN REF IN Veer REF IN REF IN at DC fvrercm 60Hz 60Hz Vngr 2
4. 1110 1000 Encoding 22 49 5 INSTRUMENTS CSFL Calculate Checksum for all FLASH Pages Description Calculate the checksum for all FLASH pages The checksum is calculated as a sum of all the bytes with the carry ignored AII bits are included in the checksum calcula tion there is no masking of bits Operands None Bytes 1 1110 1100 Data Transfer Sequence Encoding 1110 1100 SELFCAL Offset and Gain Self Calibration Description Starts the process of self calibration The Offset Control Register OCR and the Full Scale Register FSR are updated with new values after this operation Operands None Bytes 1 1111 0000 Data Transfer Sequence Encoding Dour xxxx Dy C 1111 0000 SELFOCAL Offset Self Calibration Description Starts the process of self calibration for offset The Offset Control Register OCR is updated after this operation Operands None Bytes 1 1111 0001 Data Transfer Sequence C 1111 0001 Encoding ADS1218 SBAS187 SELFGCAL Gain Self Calibration Description Starts the process of self calibration for gain The Full Scale Register FSR is updated with new values after this operation Operands None Bytes 1 1111 0010 Data Transfer Sequence Encoding 1111 0010 Dour 2000 SYSOCAL System Offset Calibration Description Starts the system offset calibration
5. Burr Brown Products from Texas Instruments ADS1218 SBAS187 SEPTEMBER 2001 8 Channel 24 Bit ANALOG TO DIGITAL CONVERTER with FLASH Memory FEATURES 24 BITS NO MISSING CODES 0 0015 INL 22 BITS EFFECTIVE RESOLUTION PGA 1 19 BITS PGA 128 4K BYTES OF FLASH MEMORY PROGRAMMABLE FROM 2 7V TO 5 25V PGA FROM 1 TO 128 SINGLE CYCLE SETTLING MODE PROGRAMMABLE DATA OUTPUT RATES UP TO 1kHz PRECISION 1 25V 2 5V REFERENCE ACCURACY 0 2 DRIFT 5ppm C EXTERNAL DIFFERENTIAL REFERENCE OF 0 1V TO 2 5V ON CHIP CALIBRATION PIN COMPATIBLE WITH ADS1216 SPI COMPATIBLE 2 7V TO 5 25V lt 1mW POWER CONSUMPTION AGND AVpp O DESCRIPTION The ADS1218 is a precision wide dynamic range delta sigma Analog to Digital A D converter with 24 bit resolution and FLASH memory operating from 2 7V to 5 25V supplies The delta sigma A D converter provides up to 24 bits of no missing code performance and effective resolution of 22 bits The eight input channels are multiplexed Internal buffering can be selected to provide a very high input impedance for direct connection to transducers or low level voltage signals Burn out current sources are provided that allow for the detection of an open or shorted sensor An 8 bit Digital to Analog D A converter provides an offset correction with a range of 50 of the FSR Full Scale Range The PGA
6. PDWN DSYNC RESET DRDY Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet Copyright 2001 Texas Instruments Incorporated TEXAS INSTRUMENTS www ti com ABSOLUTE MAXIMUM RATINGS AVpp to AGND DVpp to DGND Input Current Input Current Digital Input Voltage to GND Digital Output Voltage to GND Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature soldering 10s 0 3V to 6V 0 3V to 6V 100mA Momentary 10mA Continuous GND 0 5V to AVpp 0 5V 6V to 6V 0 3V to 0 0 3V to DVpp 0 3V 0 3V to DVpp 0 3V 40 C to 85 C 60 C to 100 C NOTE 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device Exposure to absolute maximum conditions for extended periods may affect device reliability PACKAGE ORDERING INFORMATION PRODUCT PACKAGE LEAD SPECIFIED TEMPERATURE RANGE PACKAGE DESIGNATOR PACKAGE MARKING ORDERING NUMBER ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD Texas Instruments recommends that all integrated circuits be handled with appropriate precautions Failure to observe proper handling and installation procedures can cause dam
7. Programmable Gain Amplifier provides selectable gains of 1 to 128 with an effective resolution of 19 bits at a gain of 128 The A D conversion is accomplished with a second order delta sigma modulator and programmable sinc filter The reference input is differential and can be used for ratiometric conversion The on board current DACs Digital to Analog Converters operate independently with the maximum current set by an external resistor The serial interface is SPI compatible Eight bits of digital T O are also provided that can be used for input or output The ADS1218 is designed for high resolution measurement applications in smart transmitters industrial process control weight scales chromatography and portable instrumentation pac Vaerour VREF Veer Xour APPLICATIONS INDUSTRIAL PROCESS CONTROL 225 LIQUID GAS CHROMATOGRAPHY BLOOD ANALYSIS SMART TRANSMITTERS PORTABLE INSTRUMENTATION WEIGHT SCALES AEN PRESSURE TRANSDUCERS SPI is a registered trademark of Motorola A PRODUCTION DATA information is current as of publication date Products conform to specifications the terms of Texas Instruments 1 standard warranty Production processing does not necessarily include testing of all parameters O 125V or Clock Generator 2 5V Reference 2nd Order Modulator Controller 4K Bytes FLASH WREN Serial Interface Dn
8. defines the ratio between the output of the modulator and the output Data Rate Valid values for the Decimation Ratio are from 20 to 2047 Larger Decimation Ratios will have lower noise and vice versa 49 5 25 INSTRUMENTS Effective Resolution the effective resolution of the ADS1218 in a particular configuration can be expressed in two different units bits rms referenced to output and Vrms referenced to input Computed directly from the converter s output data each is a statistical calculation The conversion from one to the other is shown below BITS rms BIPOLAR Vrms UNIPOLAR Vrms En PGA 149nV 597nV 2 39uV 9 55uV 38 2uV 152 7uV 610uV Filter Selection the ADS1218 uses a sinx x filter or sinc filter Actually there are three different sinc filters that can be selected A fast settling filter will settle in one tpATA cycle The sinc filter will settle in two cycles and have lower noise The sinc will achieve the lowest noise and highest number of effective bits but requires three cycles to settle The ADS1218 will operate with any one of these filters or it can operate in an auto mode where it will select the fast settling filter after a new channel is selected and will then switch to sinc followed by sinc This allows fast settling response and still achieves low noise after the necessary number of tpATA cycles fosc the frequency of the crystal oscillator or CMOS compatible input signal at t
9. fosc 2 45MHz 500 2 15 1 05 0 0 5 1 15 2 ppm of FS Vaerour YS LOAD CURRENT OFFSET DAC OFFSET vs TEMPERATURE 2 55 200 170 140 110 Vngrour V a Offset ppm of FSR oa e 2 45 100 0 5 0 0 5 1 0 1 5 2 0 2 5 sU gH des Vnerou Current Load mA Temperature C 10 49 5 ADS1218 INSTRUMENTS SBAS187 Normalized Gain TYPICAL CHARACTERISTICS Cont AVpp 5 DVpp 5 fosc 2 4576MHz PGA 1 150 10Hz REF IN REF IN 2 5V unless otherwise specified OFFSET DAC GAIN vs TEMPERATURE 1 00020 1 00016 1 00012 1 00008 1 00004 1 00000 0 99996 0 99992 0 99988 0 99984 0 99980 0 99976 50 30 10 10 30 50 70 90 Temperature IDAC NORMALIZED vs TEMPERATURE 50 30 10 10 30 50 70 90 Temperature IDAC DIFFERENTIAL NON LINEARITY RANGE 1 150 Vrer 2 5V 0 32 64 96 128 160 192 224 255 IDAC Code ADS1218 SBAS187 IDAC Match ppm lour Normalized Vout 1 000 i 1 000 Y 25 0 999 0 999 IDAC MATCHING vs TEMPERATURE 50 30 10 10 30 50 70 90 Temperature C IDAC INTEGRA
10. 004 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FSRO Address 0D Full Scale Register Least Significant Byte Reset Value 24 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FSRO7 FSRO6 FSROS FSRO4 FSRO3 FSRO2 FSRO FSROO 5 1 Address Full Scale Register Middle Byte Reset Value 904 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FSR15 FSR14 FSR13 FSR12 FSRO11 FSR10 FSRO9 FSRO08 FSR2 Address OF Full Scale Register Most Significant Byte Reset Value 674 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 FSR23 FSR22 FSR21 FSR20 FSRO19 FSR18 FSR17 FSR16 ADS1218 SBAS187 COMMAND DEFINITIONS The commands listed below control the operation of the ADS1218 Some of the commands are stand alone com mands e g RESET while others require additional bytes e g WREG requires command count and the data bytes Commands that output data require a minimum of four fosc cycles before the data is ready e g RDATA RDATA Read Data RDATAC Read Data Continuously STOPC Stop Read Data Continuously RREG Read from REG Bank RRAM Read from RAM Bank aaa CREG Copy REGs to RAM Bank CREGA Copy REGS to all RAM Banks WREG Write to REG WRAM Write to RAM Bank aaa RF2R Read FLASH page to RAM WR2F Write RAM to FLASH page CRAM Copy RAM Bank aaa to REG CSRAMX Calc RAM Bank Checksum CSARAMX Calc all RAM Bank Checksum CSREG
11. 2 20 Indefinite 10 AVpp 1 see Typical Characteristics INSTRUMENTS 600 5 75 0 25 15 ppm V 96 ADS1218 SBAS187 ELECTRICAL CHARACTERISTICS AVpp 3V Cont All specifications Ty to Tmax AVpp DVpp 2 7V to 5 25V 19 2kHz fosc 2 4576MHz PGA 1 Buffer ON 75 10 2 Vnee REF IN REF IN 1 25V unless otherwise specified ADS1218 PARAMETER CONDITIONS MIN MAX POWER SUPPLY REQUIREMENTS Power Supply Voltage AVpp Analog Current lapc lyagr Ipac PDWN 0 or SLEEP ADC Current PGA 1 Buffer OFF PGA 128 Buffer OFF PGA 1 Buffer ON PGA 128 Buffer ON Vrer Current lype Ipac Current Ipac Excludes Load Current Digital Current Normal Mode DVpp 3V SLEEP Mode DVpp 3V Read Data Continuous Mode DVpp 3V PDWN 0 Power Dissipation PGA 1 Buffer OFF REFEN 0 Ibacs OFF DVpp TEMPERATURE RANGE Operating Storage NOTES 1 Calibration can minimize these errors 2 is change in digital result 3 12pF switched capacitor at clock frequency DIGITAL CHARACTERISTICS to Tmax DVpp 2 7V to 5 25V Digital Input Output Logic Family Logic Level Vi DVpp Vi 0 2 DVpp Von VoL DGND 0 4 Input Leakage li 10 Master Clock Rate fosc 5 Master Clock Period tosc NOTE 1 For FLASH E W operations the SPEED bit in the
12. Bytes through dedicated instructions The on chip FLASH can be used to store non volatile data The FLASH data is separate from the configuration registers and Bank 0 therefore can be used for any purpose in addition to device 18 bytes configuration The FLASH page data is read and written in 128 byte blocks through the RAM banks i e all RAM banks map to a single page of FLASH as shown in Figure 5 REGISTER BANK TOPOLOGY Bank 2 16 bytes Page 0 _ 128 bytes The operation of the device is set up through individual registers The set of the 16 registers required to configure the device is referred to as a Register Bank as shown in Figure 5 Doo E 411111 Reads and Writes to Registers and RAM occur on a byte basis However copies between registers and RAM occurs Bank 7 on a bank basis The RAM is independent of the Registers 16 i e the RAM can be used as general purpose RAM The ADS1218 supports any combination of eight analog Doo E L E e o o o inputs With this flexibility the device could easily support eight unique configurations one per input channel In order to facilitate this type of usage eight separate register banks are available Therefore each configuration could be written once and recalled as needed without having to serially retransmit all
13. CREGA 1600 tosc Periods WR2F 76 850 SPEED 0 tosc Periods 101 050 SPEED 1 tosc Periods SELFGCAL SELFOCAL SYSOCAL SYSGCAL 4 DRDY Periods SELFCAL 14 DRDY Periods RESET Command SCLK or Pin 16 tosc Periods SCLK Reset First HIGH Pulse tosc Periods SCLK Reset LOW Pulse tosc Periods SCLK Reset Second HIGH Pulse tosc Periods SCLK Reset Third HIGH Pulse tosc Periods Pulse Width tosc Periods DOR Data Not Valid tosc Periods NOTE 1 Load 20pF 10kO to DGND ADS1218 49 5 7 SBAS187 INSTRUMENTS TYPICAL CHARACTERISTICS AVpp 5V DVpp 45V fosc 2 4576MHz PGA 1 Rpac 150 10Hz Vper REF IN REF IN 2 5V unless otherwise specified ENOB rms ENOB rms ENOB rms EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 PGA2 PGA4 PGA1 PGA2 PGA4 PGA8 20 19 8 48 PGA16 PGA32 PGA128 1 m 17 o Z 16 PGA16 PGA32 PGA64 PGA128 15 14 Sinc Filter 18 Sinc Filter Buffer ON 0 500 1000 1500 2000 0 500 1000 1500 2000 f f Decimation Ratio 2 Decimation Ratio DATA DATA EFFECTIVE NUMBER OF BITS EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO vs DECIMATIO
14. O Fast Settling Modulator Output FILTER SETTLING TIME SETTLING TIME FILTER Conversion Cycles i NOTE 1 With Synchronized Channel Changes AUTO MODE FILTER SELECTION CONVERSION CYCLE a LC RE FIGURE 2 Filter Step Responses settling filter for the next two conversions the first of which should be discarded It will then use the sinc followed by the sinc filter to improve noise performance This combines the low noise advantage of the sinc filter with the quick response of the fast settling time filter The frequency response of each filter is shown in Figure 3 SINC FILTER RESPONSE 3dB 0 262 foara 15 76Hz 30 60 90 120 150 180 210 240 270 300 Frequency Hz SINC FILTER RESPONSE 348 0 318 19 11Hz 0 30 60 90 120 150 180 210 240 270 300 Frequency Hz FAST SETTLING FILTER RESPONSE 8dB 0 469 28 125Hz 30 60 90 120 150 180 210 240 270 300 Frequency Hz NOTE foara 60Hz FIGURE 3 Filter Frequency Responses ADS1218 49 5 13 SBAS187 INSTRUMENTS VOLTAGE REFERENCE The voltage reference used for the ADS1218 can either be internal or external The power up configuration for the voltage reference is 2 5V internal The selection for the voltage reference is made through the status configuration register The internal voltag
15. TEMPERATURE RANGE Operating Storage NOTES 1 Calibration can minimize these errors 2 A is change in digital result 3 12pF switched capacitor at fgsamp clock frequency ADS1218 SBAS187 49 TEXAS INSTRUMENTS ELECTRICAL CHARACTERISTICS AVpp 3V All specifications Tmn to Tmax AVpp DVpp 2 7V to 5 25V 19 2kHz fosc 2 4576MHz PGA 1 Buffer ON Rpac 75kQ fpata 10HZz Vrer REF IN REF IN 1 25V unless otherwise specified PARAMETER CONDITIONS ANALOG INPUT An0 7 Ancom Analog Input Range Full Scale Input Voltage Range Input Impedance Input Current Bandwidth Fast Settling Filter Sinc Filter Sinc Filter Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources Buffer OFF Buffer ON In In See Block Diagram Buffer OFF Buffer ON 3dB User Selectable Gain Ranges Modulator OFF T 25 AGND 0 1 AGND 0 05 TYP 5 PGA 0 5 0 469 1 0 318 foata 0 262 9 5 2 ADS1218 0 1 1 5 Vper PGA OFFSET DAC Offset DAC Range Offset DAC Monotonicity Offset DAC Gain Error Offset DAC Gain Error Drift Vper 2 PGA 10 2 Bits 96 SYSTEM PERFORMANCE Resolution No Missing Codes Integral Non Linearity Offset Error Offset Drift Gain Error Gain Error Drift Common Mode Rejection Nor
16. called self calibration This is handled with three commands One command does both offset and gain calibration There is also a gain calibration command and an offset calibration command Each calibration process takes seven periods to complete Therefore it takes 14 tpATA periods to complete both an offset and gain calibration For system calibration the appropriate signal must be applied to the inputs The system offset command requires a zero differential input signal It then computes an offset that will nullify offset in the system The system gain command requires a positive full scale differential input signal It then computes a value to nullify gain errors in the system Each of these calibrations will take seven tpara periods to complete Calibration should be performed after power on a change in temperature a change in decimation ratio or a change in the PGA Calibration will remove the offset in the ODAC register Therefore changes to the ODAC register must be done after calibration At the completion of calibration the DRDY signal will go LOW to indicate that calibration is complete and valid data is available DIGITAL FILTER The Digital Filter can use either the fast settling sinc or sinc filter as shown in Figure 2 In addition the Auto mode changes the sinc filter after the input channel or PGA is changed When switching to a new channel it will use the fast Adjustable Digital Filter
17. process For a system offset calibration the input should be set to differential and the ADS1218 computes the OCR register value that will compensate for offset errors The Offset Control Register OCR is updated after this operation Operands None Bytes 1 1111 0011 Data Transfer Sequence Encoding 11110011 Dour xxxx SYSGCAL System Gain Calibration Description Starts the system gain calibration process For a system gain calibration the differential input should be set to the reference voltage and the ADS1218 computes the FSR register value that will compensate for gain errors The FSR is updated after this operation Operands None Bytes 1 1111 0100 Data Transfer Sequence Encoding 1111 0100 Dour amp xxxx ADS1218 SBAS187 DSYNC Sync DRDY Description Synchronizes the ADS1218 to the serial clock edge Operands None Bytes 1 Encoding 1111 1100 Data Transfer Sequence Dw 1111 1100 Dour XXXX xxxx SLEEP Sleep Mode Description Puts the ADS1218 into alow power sleep mode To exit sleep mode strobe SCLK Operands None Bytes 1 1111 1101 Data Transfer Sequence Encoding 1111 1101 Dour amp xxxx Description Restore the registers to their power up values This command will also stop the Read Continuous mode It does not affect the contents of RAM Reset to Powerup Values Operands None B
18. the RAM bank The number of bytes to read will be one plus the value of the second byte Operands Bytes 2 Encoding 0010 0aaa xnnn nnnn Data Transfer Sequence Read Two RAM Locations Starting from 20 0010 0010 X x000 0001 oH XXXX XXXX H H NOTE 1 For wait time refer to timing specification 20 49 5 INSTRUMENTS CREG Copy Registers to RAM Bank Description Copy the 16 control registers to the RAM bank specified in the op code Refer to timing specifications for command execution time Operands a Bytes 1 0100 Data Transfer Sequence Copy Register Values to RAM Bank 3 0100 0011 CREGA Registers to RAM Banks Description Duplicate the 16 control registers to all the RAM banks Refer to timing specifications for command execution time Encoding Operands None Bytes 1 0100 1000 Data Transfer Sequence 0100 1000 Write to Register Encoding WREG Description Write to the registers starting with the register specified as part of the instruction The number of registers that will be written is one plus the value of the second byte Operands r n Bytes 2 Encoding 0101 rr xxxx nnnn Data Transfer Sequence Write Two Registers Starting from 06 DIO 0101 0110 X xxxx 0001 X Data for DIO X Data DIR ADS1218 SBAS187 WRAM Write to RAM Description Write up to 128 RAM locations starting at the beginning of the RAM bank sp
19. value is defined with 11 bits for a range of 20 to 2047 This register is the least significant 8 bits The 3 most significant bits are contained in the M DECI register The default data rate is 10Hz with a 2 4576MHz crystal M DECI Address 094 Mode and Decimation Register Reset Value 074 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DRDY swooe SMODEO WREN DEC10 DECO9 bit 7 DRDY Data Ready Read Only This bit duplicates the state of the DRDY pin bit 6 U B Data Format 0 Bipolar default 1 Unipolar ANALOG INPUT DIGITAL OUTPUT Ox7FFFFF 0 000000 0 800000 0 000000 0 000000 18 49 5 INSTRUMENTS bit 5 4 SMODEI SMODEO Settling Mode 00 Auto default 01 Fast Settling filter 10 Sinc filter 11 Sinc Flash filter bit 3 WREN Write Enable 0 Flash Writing Disabled default 1 Flash Writing Enabled This bit is AND d with the WREN pin to enable or disable Flash Writing and Erasing bit 2 0 DECIO 9 DECOS Most Significant Bits of the Decimation Value Address Offset Calibration Coefficient Least Significant Byte Reset Value 004 bit 7 bit 6 bits bit4 bit2 bit 1 bit 0 Address Offset Calibration Coefficient Middle Byte Reset Value 004 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCR2 Address 0 Offset Calibration Coefficient Most Significant Byte Reset Value
20. 10 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 o o SPEED REFEN REFHI BUF EN BIT ORDER bit 7 5 Factory Programmed Bits bit 4 SPEED FLASH Access Clock Speed 0 2 30MHz gt fosc gt 3 12MHz default 1 3 12MHz gt fosc gt 4 13MHz bit 3 REF EN Internal Voltage Reference Enable 0 Internal Voltage Reference Disabled 2 Internal Voltage Reference Enabled default bit 2 REF HI Internal Reference Voltage Select 0 Internal Reference Voltage 1 25V Internal Reference Voltage 2 5V default bit 1 BUF EN Buffer Enable 0 Buffer Disabled Buffer Enabled default bit O0 BIT ORDER Set Order Bits are Transmitted 0 Most Significant Bit Transmitted First default Least Significant Bit Transmitted First Data is always shifted into the part most significant bit first Data is always shifted out of the part most significant byte first This configuration bit only controls the bit order within the byte of data that is shifted out MUX Address 014 Multiplexer Control Register Reset Value 01 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PSEL3 PSEL2 PSEL1 PSELO NSEL3 NSEL2 NSEL1 NSELO bit 7 4 PSEL3 PSEL2 PSEL1 PSELO Positive Channel Select 0000 AINO default 0001 2 AINI 0010 AIN2 0011 AIN3 0100 AIN4 0101 AINS 0110 AIN6 0111 AIN7 AINCOM except when all bits are 1 s 1111 Temperature Sensor Diode Anode bit 3 0 NSEL3 NS
21. 1_2 IDAC1 1 IDAC1_0 The DAC code bits set the output of DAC2 from 0 to full scale The value of the full scale current is set by this Byte and DAC2 range bits in ACR register 49 5 17 INSTRUMENTS ODAC Address 055 Offset DAC Setting Reset Value 004 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 Offset Sign 0 Positive 1 Negative VREF 52 bit 6 ffset e tO OMNES S PGA NOTE Calibration will cancel the value in the ODAC register Therefore writing to the ODAC register should be done after calibration DIO Address 06y Digital YO Reset Value 00g bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ser oer o o on oor A value written to this register will appear on the digital I O pins if the pin is configured as an output in the DIR register Reading this register will return the value of the digital I O pins DIR Address 074 Direction control for digital I O Reset Value FF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DIR7 0185 DIR4 DIR3 DIR2 DIR1 Each bit controls whether the Digital I O pin is an output 0 or input 1 The default power up state is as inputs DECO Address 084 Decimation Register Least Significant 8 bits Reset Value 804 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DECO7 6 5 DECO4 DECO3 DECO2 DECO The decimation
22. 5V ON CHIP VOLTAGE REFERENCE Output Voltage Short Circuit Current Source Short Circuit Current Sink Short Circuit Duration Drift Noise Output Impedance Startup Time REF HI 1 at 25 REF HI 0 Sink or Source BW 0 1Hz to 100Hz Sourcing 50 Indefinite 5 10 3 50 IDAC Full Scale Output Current Maximum Short Circuit Current Duration Monotonicity Compliance Voltage Output Impedance PSRR Absolute Error Absolute Drift Mismatch Error Mismatch Drift Rpac 150k Range 1 Rpac 150k Range 2 Rpac 150 Range 15kQ Range 3 Rpac 10kQ Rpac 02 Rpac 150kQ Vout AVpp 2 Individual IDAC Individual IDAC Between IDACs Same Range and Code Between IDACs Same Range and Code 0 5 1 2 20 Indefinite see Typical Characteristics 400 5 75 0 25 15 10 Minutes Bits AVpp 1 V ppm V 96 POWER SUPPLY REQUIREMENTS Power Supply Voltage Analog Current lyagr lpac ADC Current Vngr Current Current Ipac Digital Current Power Dissipation AVpp PDWN 0 or SLEEP PGA 1 Buffer OFF PGA 128 Buffer OFF PGA 1 Buffer ON PGA 128 Buffer ON Excludes Load Current Normal Mode DVpp 5V SLEEP Mode DVpp 5V Read Data Continuous Mode DVpp 5V PDWN LOW PGA 1 Buffer OFF REFEN 0 Ipacs OFF DVpp 5V V nA uA uA uA uA HA uA uA uA uA nA
23. 9986 50 30 10 10 30 50 70 90 Temperature ADS1218 49 5 SBAS187 INSTRUMENTS CMRR dB INL ppm of FS 130 120 110 100 50 CMRR vs FREQUENCY 1 10 PGA1 Frequency of CM Signal Hz 100 1k 10k 100k OFFSET vs TEMPERATURE PGA16 PGA64 PGA128 50 30 10 10 30 50 70 90 Temperature INTEGRAL NON LINEARITY vs INPUT SIGNAL 40 C 85 C TYPICAL CHARACTERISTICS Cont 45V DVpp 5 fosc 2 4576MHz PGA 1 150 10Hz Vper REF IN REF IN 2 5 unless otherwise specified CURRENT vs TEMPERATURE ADC CURRENT vs PGA 5V Buffer ON lbiciTAL 800 Buffer OFF i lANALOG 0 1 700 600 y IANALOG DIGITAL AVpp Buffer ON Buffer OFF lapc a 8 Current uA 50 30 10 10 30 50 70 90 4 8 16 32 64 128 Temperature PGA Setting DIGITAL CURRENT HISTOGRAM OF OUTPUT DATA SPEED 0 Normal fosc 4 91MHz 4000 Normal fosc 2 45MHz Current uA Number of Occurrences SLEEP
24. Calc REG Checksum CSRAM Calc RAM Bank Checksum CSARAM Calc all RAM Banks Checksum CSFL Calc FLASH Checksum SELFCAL Self Cal Offset and Gain SELFOCAL Self Cal Offset SELFGCAL Self Cal Gain SYSOCAL Sys Cal Offset SYSGCAL Sys Cal Gain DSYNC Sync DRDY SLEEP Put in SLEEP Mode RESET Reset to Power Up Values Operands n count 0 to 127 r register 0 to 15 don t care RAM bank address 0 to 7 f FLASH page address 0 to 31 gt 1 nnnn of reg 1 0010 0aaa xnnn nnnn of bytes 1 0100 0aaa 0100 1000 0101 xxxx nnnn of reg 1 0110 xnnn nnnn of bytes 1 100f fff f 89x 101f fff f 1100 1101 1101 1000 D84 1101 1111 1110 0aaa 1110 1000 E8 1110 1100 EC 1111 0000 FO 1111 0001 F1 1111 0010 F2 1111 0011 F34 1111 0100 F44 1111 1100 FC 1111 1101 1111 1110 FE NOTE 1 The data received by the A D is always MSB First the data out format is set by the BIT ORDER bit in ACR reg TABLE III Command Summary RDATA Read Data Description Read a single data value from the Data Output Register DOR which is the most recent conversion result This is a 24 bit value Operands None Bytes 1 0000 0001 Data Transfer Sequence NOTE 1 For wait time refer to timing specification Encoding ADS1218 SBAS187 RDATAC Description Read Data Continuous mode enables
25. EL2 NSEL1 NSELO Negative Chan nel Select 0000 AINO 0001 AINI default 0010 AIN2 0011 AIN3 0100 AIN4 0101 AINS 0110 AIN6 0111 AIN7 lxxx AINCOM except when all bits are 1 s 1111 Temperature Sensor Diode Cathode Analog GND ADS1218 SBAS187 ACR Address 025 Analog Control Register Reset Value 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 BOCS Burnout Current Source 0 Disabled default 1 Enabled IDAC Current REF _ 2 1 DAC Code 8 bit 6 5 IDACORI IDAC2RO Full Scale Range Select for IDAC2 00 Off default 01 Range 1 10 Range 2 11 Range 3 bit 4 3 IDACIRI IDACIRO Full Scale Range Select for IDACI 00 Off default 01 Range 1 10 Range 2 11 Range 3 bit 2 0 PGA2 PGA1 PGAO Programmable Gain Ampli fier Gain Selection 000 1 default 001 22 010 4 01128 100 16 101 32 110 64 111 2 128 IDACI Address 035 Current DAC 1 Reset Value 004 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IDAC1 7 IDAC1_6 IDAC1 5 IDAC1_4 IDAC1_3 IDAC1 2 IDAC1_1 IDAC1_0 The DAC code bits set the output of DACI from 0 to full scale The value of the full scale current is set by this Byte Rpac and the DACI range bits in ACR register IDAC2 Address 044 Current DAC 2 Reset Value 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IDAC2 7 IDAC2 6 IDAC2 5 IDAC2_4 IDAC1 3 IDAC
26. L NON LINEARITY RANGE 1 150 Veer 2 5V INL LSB 0 32 64 96 128 160 192 224 255 IDAC Code 49 5 INSTRUMENTS OVERVIEW INPUT MULTIPLEXER The input multiplexer provides for any combination of differential inputs to be selected on any of the input chan nels as shown in Figure 1 For example if channel 1 is selected as the positive differential input channel any other channel can be selected as the negative differential input channel With this method it is possible to have up to eight fully differential input channels In addition current sources are supplied that will source or sink current to detect open or short circuits on the input pins Burnout Current Source On D Burnout Current Source On AGND d FIGURE 1 Input Multiplexer Configuration TEMPERATURE SENSOR An on chip diode provides temperature sensing capability When the configuration register for the input MUX is set to all 1s the diode is connected to the input of the A D converter All other channels are open The anode of the diode is connected to the positive input of the A D converter and the cathode of the diode is connected to negative input of the A D converter The output of IDACI is connected to the anode to bias the diode and the cathode of the diode is also connected to grou
27. N RATIO 22 PGA2 PGA4 21 1 PGA2 POAT PGA8 20 m 17 M PGA16 PGA32 PGA128 1 2 16 5 15 2 PGA64 PGA128 14 Sinc Filter 1 25V Buffer OFF 1 Sinc Filter 1 25V Buffer ON 12 0 500 1000 1500 2000 0 500 1000 1500 2000 f f Decimation Ratio 00 Decimation Ratio DATA foata EFFECTIVE NUMBER OF BITS FAST SETTLING FILTER vs DECIMATION RATIO EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 21 PGA1 PGA2 PGA4 PGA8 20 19 18 17 j T m PGA32 PGA64 PGA128 2 16 a PGA16 15 14 z 1 Sinc Filter Fast Settling Filter 13 12 0 500 1000 1500 2000 0 500 1000 1500 2000 f f Decimation Ratio Decimation Ratio 2 DATA DATA 49 5 ADS1218 INSTRUMENTS SBAS187 TYPICAL CHARACTERISTICS Cont 5 DVpp 45V fosc 2 4576MHz PGA 1 150kO 10Hz Vper REF IN REF IN 2 5V unless otherwise specified NOISE vs INPUT SIGNAL Noise rms ppm of FS PSRR vs FREQUENCY 120 110 100 PSRR dB o Offset ppm of FS 1 10 100 1k 10k 100k Frequency of Power Supply Hz GAIN vs TEMPERATURE 1 00010 1 00006 1 00002 0 99998 0 99994 Gain Normalized 0 99990 0 9
28. S1218 INSTRUMENTS SBAS187 SERIAL PERIPHERAL INTERFACE The Serial Peripheral Interface SPI allows a controller to communicate synchronously with the ADS1218 The ADS1218 operates in slave only mode SPI Transfer Formats During an SPI transfer data is simultaneously transmitted and received The SCLK signal synchronizes shifting and sampling of the information on the two serial data lines Diy and Dour The CS signal allows individual selection of an ADS1218 device an ADS1218 with CS HIGH is not active on the bus Clock Phase and Polarity Controls POL The clock polarity is specified by the POL pin which selects an active HIGH or active LOW clock and has no effect on the transfer format Serial Clock SCLK SCLK a Schmitt Trigger input to the ADS1218 is gener ated by the master device and synchronizes data transfer on the Dy and Dour lines When transferring data to or from the ADS1218 burst mode may be used i e multiple bits of data may be transferred back to back with no delay in SCLKs or toggling of CS Chip Select CS The chip select CS input of the ADS1218 must be exter nally asserted before a master device can exchange data with the ADS1218 CS must be LOW before data transactions and must stay LOW for the duration of the transaction DIGITAL INTERFACE The ADS1218 s programmable functions are controlled using a set of on chip registers as outlined previously Data is written to these registers vi
29. SETUP register must be set appropriately and the device operating frequency must be 2 3MHz lt lt 4 13MHz FLASH CHARACTERISTICS Tmn to TyAx DVpp 2 7V to 5 25V unless otherwise specified Operating Current Page Write DVpp 5V During WR2F Command DVpp During WR2F Command Page Read DVpp 5V During RF2R Command mA DVpp During RF2R Command Endurance E W Cycles Data Retention at 25 Years DVpp for Erase Write V ADS1218 49 TEXAS 5 SBAS187 INSTRUMENTS PIN CONFIGURATION 48 DO D1 D2 D3 04 05 06 07 AGND Vnerour VREF VREF ADS1218 PIN DESCRIPTIONS Analog Power Supply Analog Ground Analog Input 0 Analog Input 1 Analog Input 2 Analog Input 3 Analog Input 4 Analog Input 5 Analog Input 6 Analog Input 7 Analog Input Common Analog Ground Analog Power Supply Vrer Bypass CAP Current DAC1 Output Current DAC2 Output Current DAC Resistor 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Digital Ground Buffer Enable DSYNC DGND DVpp DRDY 5 SCLK Dour D0 D7 AGND Active High FLASH Write Enable VnErFour VREF VREF 49 5 INSTRUMENTS Active LOW resets the entire chip Clock Input Clock Output used with crystal or resonator Active LOW Power Down The power down function shuts down the analog and digital circuits Serial Clock Polarity Active LOW Synchron
30. This would enable the user to recall calibration coefficients for every 4 C change in temperature over the industrial tempera ture range which could be used to correct for drift errors Checksum commands are also included which can be used to verify the integrity of FLASH The following two commands can be used to manipulate the FLASH First the contents of FLASH can be written to with the WR2F write RAM to FLASH command This com mand first erases the designated FLASH page and then writes the entire content of RAM all banks into the desig nated FLASH page Second the contents of FLASH can be read with the RF2R read FLASH to RAM command This command reads the designated FLASH page into the entire contents of RAM all banks In order to ensure maximum endurance and data retention the SPEED bit in the SETUP register must be set for the appropriate frequency Writing to or erasing FLASH can be disabled either through the WREN pin or the WREN register bit If the WREN pin is LOW OR the WREN bit is cleared then the WR2F command has no effect This protects the integrity of the FLASH data from being inadvertently corrupted Accessing the FLASH data either through read write or erase may effect the accuracy of the conversion result Therefore the conversion result should be discarded when accesses to FLASH are done ADS1218 SBAS187 DETAILED REGISTER DEFINITIONS SETUP Address 004 Setup Register Reset Value 11011
31. a of one least significant bit It is computed as follows Full Scale Range 2N where N is the number of bits in the digital output LSB Weight tpara the inverse of fpara or the period between each data output GENERAL EQUATIONS DIFFERENTIAL PGA OFFSET FULL SCALE DIFFERENTIAL PGA SHIFT GAIN SETTING FULL SCALE RANGE INPUT 50 RANGE RANGE INPUT VOLTAGES RANGE VREF 2e PGA 2 5V 2 5V 1 25V 1 25V 0 625V 0 625V 312 5mV 312 5mV 156 25mV 156 25mV 78 125mV 78 125mV 39 0625mV 39 0625mV 19 531mV 312 5mV 156 25mV 78 125 39 0625mV 19 531 9 766mV 1 25V 2 e VREF 0 625V PGA NOTES 1 With 2 5V reference 2 The ADS1218 allows common mode voltage long as the absolute input voltage AP AN does below AGND or above TABLE V Full Scale Range versus PGA Setting 26 49 5 INSTRUMENTS ADS1218 SBAS187 TOPIC INDEX TOPIC PAGE ABSOLUTE MAXIMUM RATINGS RR DARAN RR R RA DES AR ARR NR RR ORAN RR RR ARR NR dna rad 2 PACKAGE AND ORDERING INFORMATION 2 ELECTRICAL CHARACTERISTICS AVpp 5V xn xU y Na NOUO Len nx nv Ge Vx 2 ELECTRICAL CHARACTERISTICS AVpp 3V
32. a the part s serial interface and read access to the on chip registers is also provided by this interface The ADS1218 s serial interface consists of four signals CS SCLK and The Dy line is used for transferring data into the on chip registers while the Doyr line is used for accessing data from the on chip registers SCLK is the serial clock input for the device and all data transfers either on Dy or take place with respect to this SCLK signal The DRDY line is used as a status signal to indicate when data is ready to be read from the ADS1218 s data register DRDY goes LOW when a new data word is available in the DOR register It is reset HIGH when a read operation from the data register is complete It also goes HIGH prior to the updating of the output register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated ADS1218 SBAS187 CS is used to select the device It can be used to decode the ADS1218 in systems where a number of parts are connected to the serial bus The timing specification shows the timing diagram for interfacing to the ADS1218 with CS used to decode the part The ADS1218 serial interface can operate in three wire mode by tying the CS input LOW In this case the SCLK and Doyr lines are used to communicate with the ADS1218 and the status of DRDY can be obtained by interrogating bit 7 of the M DECI reg
33. age Electrostatic discharge can cause damage ranging from perfor mance degradation to complete device failure Texas Instruments recommends that all integrated circuits be handled and stored using appropriate ESD protection methods TRANSPORT MEDIA QUANTITY ADS1218Y TQFP 48 PFB 409 to 85 C ADS1218Y ADS1218Y 250 Tape and Reel 250 ADS1218Y 2K Tape and Reel 2000 NOTE 1 Models with a slash of ADSIDUE will get a single 2000 piece Tape and Reel ELECTRICAL CHARACTERISTICS AVpp 5V All specifications Tmn to Tmax AVpp 5V DVpp 2 7V to 5 25V fmon 19 2kHz fosc 2 4576MHz PGA 1 Buffer ON 150kQ 10Hz Vner REF IN REF 1 2 5V unless otherwise specified ADS1218 are available only in Tape and Reel in the quantities indicated e g 2K indicates 2000 devices per reel Ordering 2000 pieces PARAMETER CONDITIONS MIN ANALOG INPUT An0 7 Ancom Analog Input Range Full Scale Input Voltage Range Differential Input Impedance Input Current Bandwidth Fast Settling Filter Sinc Filter Sinc Filter Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources Buffer OFF Buffer ON In In See Block Diagram Buffer OFF Buffer ON AGND 0 1 AGND 0 05 3dB 3dB 3dB User Selectable Gain Ranges Modulator OFF 25 0 318 foata 0 262 9 5 2
34. e buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subjectto Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using components To minimize the risks associated with customer products a
35. e last SCLK on the DSYNC command The modulator is held in RESET until the next edge of SCLK is detected Synchronization occurs on the next rising edge of the system clock after the first SCLK after the DSYNC command POWER UP SUPPLY VOLTAGE RAMP RATE The power on reset circuitry was designed to accommodate digital supply ramp rates as slow as 1V 10ms To ensure proper operation the power supply should ramp monotoni cally The POR issues the RESET command as described below RESET There are three methods of reset The RESET pin the RESET command and the SCLK Reset pattern They all perform the same function After a reset the FLASH data values from Page 0 are loaded into RAM subsequently data values from Bank 0 of RAM are loaded into the configura tion registers ADS1218 SBAS187 MEMORY basis Also the RAM can be directly read or written through Three types of memory are used on the ADS1218 registers the serial interface on power up The banks allow separate RAM and FLASH 16 registers directly control the various storage of settings for each input functions PGA DAC value Decimation Ratio etc and can be directly read or written to Collectively the registers contain all the information needed to configure the part such as data format mux settings calibration settings decimation ratio etc Additional registers such as conversion data are accessed 128 Bytes 4k
36. e reference is selectable as either 1 25V or 2 5 AVpp 5V only The pin should have a 0 1uF capacitor to AGND The external voltage reference is differential and is repre sented by the voltage difference between the pins and The absolute voltage on either pin Vppp and Vggp can range from AGND to AVpp however the differential voltage must not exceed 2 5V The differential voltage reference provides easy means of performing ratiometric measurement Vncap PIN This pin provides a bypass cap for noise filtering on internal circuitry only The recommended capacitor is a 0 001 ceramic If an external is used this pin can be left unconnected CLOCK GENERATOR The clock source for the ADS1218 can be provided from a crystal ceramic resonator oscillator or external clock When the clock source is a crystal or ceramic resonator external capacitors must be provided to ensure start up and a stable clock frequency This is shown in Figure 4 and Table I Crystal or Ceramic Resonator FIGURE 4 Crystal or Ceramic Resonator Connection CLOCK PART SOURCE FREQUENCY C C NUMBER Crystal ECS ECSD 2 45 32 ECS ECSL 4 91 ECS ECSD 4 91 CTS MP 042 4M9182 Crystal Crystal Crystal TABLE I Typical Clock Sources 14 49 5 INSTRUMENTS DIGITAL I O INTERFACE The ADS1218 has eight pins dedicated for digital I O The default p
37. ecified as part of the instruc tion The numberof bytes written is RAM is one plus the value of the second byte Operands Bytes 2 Encoding 0110 0aaa xnnn nnnn Data Transfer Sequence Write to Two RAM Locations starting from 104 Data for Data for RF2R Read FLASH Page to RAM Description Read the selected FLASH page to the RAM Operands f Bytes 1 100f ffff Data Transfer Sequence Read FLASH Page 2 to RAM Encoding 1000 0010 Dour xxxx WR2F Write RAM to FLASH Description Write the contents of RAM to the selected FLASH page Operands f Bytes 1 101f ffff Data Transfer Sequence Write RAM to FLASH page 31 Dy 1011 1111 Encoding ADS1218 SBAS187 CRAM Copy RAM Bank to Registers Description Copy the selected RAM Bank to the Configura tion Registers This will overwrite all of the registers with the data from the RAM bank Operands a Bytes 1 1100 0aaa Data Transfer Sequence Copy RAM Bank 0 to the Registers 1100 0000 CSRAMX Calculate RAM Bank Checksum Description Calculate the checksum of the selected RAM Bank The checksum is calculated as a sum of all the bytes with the carry ignored The ID DRDY and DIO bits are masked so they are not included in the checksum Encoding Operands a Bytes 1 1101 Data Transfer Sequence Calculate Checksum for RAM Bank 3 1101 0011 CSARAMX Calculate the Checksum f
38. he input of the ADS1218 frequency or speed at which the modulator of the ADS1218 is running This depends on the SPEED bit as given by the following equation m om fosc 5V SV SUPPLY ANALOG INPUT ANALOG SV SUPPLY ANALOG INPUT fsamp the frequency or switching speed of the input sampling capacitor The value is given by one of the follow ing equations SAMPLING FREQUENCY f 1 2 4 8 fan p 086 face SAMP mfactor fosc 4 finis SAMP mfactor fosc 8 64 128 f samp 2086 fpara the frequency of the digital output data produced by ADS1218 is also referred to as the Data Rate fuon fosc Decimation Ratio mfactor e Decimation Ratio fpATA Full Scale Range FSR as with most A D converters the full scale range of the ADS1218 is defined as the input which produces the positive full scale digital output minus the input which produces the negative full scale digital output The full scale range changes with gain setting as shown in Table V For example when the converter is configured with a 2 5 V reference and is placed in a gain setting of 2 the full scale range is 1 25V positive full scale minus 1 25V nega tive full scale 2 5V Least Significant Bit LSB Weight this is the theoretical amount of voltage that the differential voltage at the analog input would have to change in order to observe a change in the output dat
39. ister This scheme is suitable for interfacing to microcontrollers If CS is required as a decoding signal it can be generated from a port pin DEFINITION OF TERMS Analog Input Voltage the voltage at any one analog input relative to AGND Analog Input Differential Voltage given by the following equation IN IN Thus a positive digital output is pro duced whenever the analog input differential voltage is posi tive while a negative digital output is produced whenever the differential is negative For example when the converter is configured with a 2 5 V reference and placed in a gain setting of 1 the positive full scale output is produced when the analog input differen tial is 2 5V The negative full scale output is produced when the differential is 2 5V In each case the actual input voltages must remain within the to AVpp range Conversion Cycle the term conversion cycle usually refers to a discrete A D conversion operation such as that performed by a successive approximation converter As used here a conversion cycle refers to the ty 474 time period However each digital output is actually based on the modu lator results from several time periods FILTER SETTING MODULATOR RESULTS fast settling 1 tpArA time period sinc 2 toata time period sinc 3 tpata time period Data Rate The rate at which conversions are completed See definition for Decimation Ratio
40. ization Control Digital Ground Digital Power Supply Active LOW Data Ready Active LOW Chip Select Serial Clock Schmitt Trigger Serial Data Input Schmitt Trigger Serial Data Output Digital 0 7 Analog Ground Voltage Reference Output Positive Differential Reference Input Negative Differential Reference Input ADS1218 SBAS187 TIMING SPECIFICATIONS Dout NOTE 1 Bit Order 0 ADS1218 SCLK Reset Waveform Resets On Falling Edge 2 RESET DSYNC PDWN DDR Update Timing TIMING SPECIFICATION TABLES t SCLK Period 4 tosc Periods DRDY Periods SCLK Pulse Width HIGH and LOW ns CS LOW to first SCLK Edge Setup Time ns Valid to SCLK Edge Setup Time ns Valid Dy to SCLK Edge Hold Time ns Delay between last SCLK edge for Diy and first SCLK edge for Dour RDATA RDATAC RREG WREG RRAM WRAM tosc Periods CSREG CSRAMX CSRAM tosc Periods CHKARAM CHKARAMX tosc Periods SCLK Edge to Valid New ns SCLK Edge to Dour Hold Time ns Last SCLK Edge to Doy Tri State tosc Periods NOTE Dour goes tri state immediately when CS goes HIGH CS LOW time after final SCLK edge ns Final SCLK edge of one op code until first edge SCLK of next command RREG WREG RRAM WRAM CSRAMX CSARAMX CSRAM CSARAM CSREG SLEEP RDATA RDATAC STOPC 4 tosc Periods DSYNC RESET 16 tosc Periods CSFL 33 000 tosc Periods CREG CRAM 220 tosc Periods RF2R 1090 tosc Periods
41. mal Mode Rejection Output Noise Power Supply Rejection End Point Fit Before Calibration After Calibration at DC fom 60Hz 10Hz fom 50Hz 50Hz fom 60Hz 60Hz fgig 50Hz 50Hz fgig 60Hz 60Hz at DC dB 20 log AVgyt AVpp 1 0 130 120 120 100 100 Bits 24 Bits 10 0015 96 of FS ppm of FS ppm of FS C 96 dB dB dB dB dB dB see Typical Characteristics 90 VOLTAGE REFERENCE INPUT Reference Input Range VREF Common Mode Rejection Common Mode Rejection Bias Current REF IN REF IN Veer REF IN REF IN at DC fvrercm 60Hz foara 60Hz Vrer 1 25 ON CHIP VOLTAGE REFERENCE Output Voltage Short Circuit Current Source Short Circuit Current Sink Short Circuit Duration Drift Noise Output Impedance Startup Time REF HI 0 at 25 C Sink or Source BW 0 1Hz to 100Hz Sourcing 100A 50 Indefinite 5 10 3 50 IDAC Full Scale Output Current Maximum Short Circuit Current Duration Monotonicity Compliance Voltage Output Impedance PSRR Absolute Error Absolute Drift Mismatch Error Mismatch Drift Rpac 75kQ Range 1 Rpac 75kQ Range 2 Rpac 75kQ Range 3 Rpac 15kQ Range 3 Rpac 10kQ Rpac 02 Rpac 75kQ Vout AVpp 2 Individual IDAC Individual IDAC Between IDACs Same Range and Code Between IDACs Same Range and Code 35 TEXAS 0 5 1
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43. nd to complete the circuit In this mode the output of IDACI is also connected to the output pin so some current may flow into an external load from IDACI rather than the diode 12 49 5 INSTRUMENTS BURNOUT CURRENT SOURCES When the Burnout bit is set in the ACR configuration register two current sources are enabled The current source on the positive input channel sources approximately 2 of current The current source on the negative input channel sinks ap proximately 2 This allows for the detection of an open circuit full scale reading or short circuit 0V differential reading on the selected input differential pair INPUT BUFFER The input impedance of the ADS1218 without the buffer is 5 With the buffer enabled the input voltage range 18 reduced and the analog power supply current is higher The buffer is controlled by ANDing the state of the BUFEN pin with the state of the BUFFER bit in the ACR register IDAC1 AND IDAC2 The ADS1218 has two 8 bit current output DACs that can be controlled independently The output current is set with Rpac the range select bits in ACR register and 8 bit digital value in the IDAC register The output current 8 RpAC 2RANGE D DAC CODE With 2 5 and 150kQ to the full scale output can be selected to be 0 5 1 2mA The compliance voltage range is 0 to within of AVpp When the internal voltage
44. oking at linear and bank addressing syntax we have the following comparison in the linear memory map the address Ox14 is equivalent to bank 1 and offset Ox4 Simply stated the most significant four bits represent the bank and the least significant four bits repre sent the offset The offset is equivalent to the register address for that bank of memory FLASH Reads and Writes to FLASH occur on a Page basis Therefore the entire contents of RAM is used for both Read and Write operations The FLASH is independent of the Registers i e the FLASH can be used as general purpose FLASH Upon power up or reset the contents of FLASH Page 0 are loaded into RAM subsequently the contents of RAM Bank 0 are loaded into the configuration register Therefore the user can customize the power up configuration for the de vice Care should be taken to ensure that data for FLASH Page 0 is written correctly in order to prevent unexpected operation upon power up 16 49 5 INSTRUMENTS The ADS1218 supports any combination of eight analog inputs and the FLASH memory supports up to 32 unique Page configurations With this flexibility the device could support 32 unique configurations for each of the eight analog input channels For instance the on chip temperature sensor could be used to monitor temperature then different calibration coefficients could be recalled for each of the eight analog input channels based on the change in temperature
45. or all RAM Banks Description Calculate the checksum of all RAM Banks The checksum is calculated as a sum of all the bytes with the carry ignored The ID DRDY and DIO bits are masked so they are not included in the checksum Encoding Operands None Bytes 1 1101 1000 Data Transfer Sequence 1101 1000 Encoding 49 TEXAS 21 INSTRUMENTS CSREG Calculate the Checksum of Registers Description Calculate the checksum of all the registers The checksum is calculated as a sum of all the bytes with the carry ignored The ID DRDY and DIO bits are masked so they are not included in the checksum Operands None Bytes 1 1101 1111 Data Transfer Sequence 1101 1111 CSRAM Calculate RAM Bank Checksum Description Calculate the checksum of the selected RAM Bank The checksum is calculated as a sum of all the bytes with the carry ignored bits are included in the checksum calculation there is no masking of bits Encoding Operands Bytes 1 1110 Data Transfer Sequence Calculate Checksum for RAM Bank 2 Encoding 11100010 Dour xxxx CSARAM Calculate Checksum for all RAM Banks Description Calculate the checksum of all RAM Banks The checksum is calculated as a sum of all the bytes with the carry ignored bits are included in the checksum calculation there is no masking of bits Operands None Bytes 1 1110 1000 Data Transfer Sequence
46. ower up condition for the digital I O pins are as inputs All of the digital I O pins are individually configurable as inputs or outputs They are configured through the DIR control register The DIR register defines whether the pin is an input or output and the DIO register defines the state of the digital output When the digital I O are configured as inputs DIO is used to read the state of the pin SERIAL INTERFACE The serial interface is standard four wire SPI compatible Dy Dour SCLK and CS The ADS1218 also offers the flexibil ity to select the polarity of the serial clock through the POL pin The serial interface can be clocked up to fosc 4 If CS goes HIGH the serial interface is reset When CS goes LOW a new command is expected The serial interface operates independently of DRDY DRDY is used to indicate availability of data in the DOR In order to ensure the validity of the data being read DOR timing requirements must be met DSYNC OPERATION DSYNC is used to provide for synchronization of the A D conversion with an external event Synchronization can be achieved either through the DSYNC pin or the DSYNC command When the DSYNC pin is used the filter counter is reset on the falling edge of DSYNC The modulator is held in reset until DSYNC is taken HIGH Synchronization occurs on the next rising edge of the system clock after DSYNC is taken HIGH When the DSYNC command is sent the filter counter is reset after th
47. reference of the ADS 1218 is used it is the reference for the IDAC An external reference may be used for the IDACs by disabling the internal reference and tying the external refer ence input to the Vpgrour pin PGA The Programmable Gain Amplifier PGA can be set to gains of 1 2 4 8 16 32 64 or 128 Using the PGA can actually improve the effective resolution of the A D converter For instance with a PGA of 1 on a 5V full scale range the A D converter can resolve to V With a PGA of 128 on a 40mV full scale range the A D converter can resolve to 75nV With a PGA of 1 on a 5V full scale range it would require a 26 bit A D converter to resolve 75nV PGA OFFSET DAC The input to the PGA can be shifted by half the full scale input range of the PGA by using the ODAC register The ODAC Offset DAC register is an 8 bit value the MSB is the sign and the seven LSBs provide the magnitude of the offset Using the ODAC register does not reduce the performance of the converter MODULATOR The modulator is a single loop second order system The modulator runs at a clock speed fmop that is derived from the external clock fosc The frequency division is deter mined by the SPEED bit in the SETUP register J 0 fogc 128 1 fosc 256 ADS1218 SBAS187 CALIBRATION The offset and gain errors in the ADS1218 or the complete system can be reduced with calibration Internal calibration of the ADS1218 is
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49. the con tinuous output of new data on each DRDY This command eliminates the need to send the Read Data Command on each DRDY This mode may be terminated by either the STOP Read Continuous command or the RESET command Read Data Continuous Operands None Bytes 1 0000 0011 Data Transfer Sequence Command terminated when uuuu uuuu equals STOPC or RESET DRDY MSB Mid Byte LSB NOTE 1 For wait time refer to timing specification Encoding 49 TEXAS 19 INSTRUMENTS STOPC Description Ends the continuous data output mode Stop Continuous Operands None Bytes 1 0000 1111 Data Transfer Sequence 0000 1111 Read from Registers Encoding RREG Description Output the data from up to 16 registers starting with the register address specified as part of the instruction The number of registers read will be one plus the second byte If the count exceeds the remaining registers the addresses will wrap back to the beginning Operands Bytes 2 Encoding 0001 rrr xxxx nnnn Data Transfer Sequence Read Two Registers Starting from Register 01 MUX 0001 0001 0000 0001 XXXX XXXX Dour XXXX Jem MUX ACR NOTE 1 For wait time refer to timing specification RRAM Read from RAM Description Up to 128 bytes can be read from RAM starting at the bank specified in the op code reads start at the address for the beginning of
50. the configuration data Checksum commands are also in c L E Cl cluded which can be used to verify the integrity of RAM The RAM provides eight banks with a bank consisting of 16 bytes The total size of the RAM is 128 bytes Copies between the registers and RAM are performed on a bank FIGURE 5 Memory Organization BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Dp sP REF EN REF HI BUFEN BIT ORDER PSEL2 PSEL1 PSELO NSEL3 NSEL2 NSEL1 NSELO Bocs DAC oes 05 pos ons ons ons ons DR DECO7 DECO6 DECO5 DECOA DECO2 DECO1 DECOO OCRO OC OCRO06 OCR05 OCR04 OCRO03 OCR02 OCR01 OCRO00 OCR1 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCRO08 OCR2 21 20 OCR19 OCR18 OCR17 OCR16 FSRO FSR1 FSR2 TABLE Registers ADS1218 49 TEXAS 15 SBAS187 INSTRUMENTS The RAM address space is linear therefore accessing RAM is done using an auto incrementing pointer Access to RAM in the entire memory map can be done consecutively without having to address each bank individually For example if you were currently accessing bank 0 at offset OxF the last location of bank 0 the next access would be bank 1 and offset 0 0 Any access after bank 7 and offset OxF will wrap around to bank 0 and Offset 0 0 Although the Register Bank memory is linear the concept of addressing the device can also be thought of in terms of bank and offset addressing Lo
51. ytes 1 1111 1110 Data Transfer Sequence Dy 1111 1110 Encoding 49 TEXAS 23 INSTRUMENTS LSB 0000 0001 0100 foror om soo soos oro mo mor mo 0001 b ju b rreg rreg rreg rreg rreg rreg rreg rreg rreg rreg rreg rreg 4 5 6 7 8 9 A B bi 1 bi ni a EE IBEX ER EE EC RETE 0100 Ebo 22 Sa s s crega 0110 wram wram wram wram wram wram wram wram 1 2 3 4 5 6 7 0111 1000 rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r 0 1 2 3 4 5 6 7 8 9 A B C D E F 1001 rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r rf2r 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1010 21 21 21 21 21 wr2f wr2f wr2f 21 wr2f 21 wr2f wr2f wr2f 21 wr2f 0 1 2 3 4 5 6 7 8 9 A B C D E F 1011 21 21 21 21 21 21 wr2f 21 wr2f wr2f wr2f 21 wr2f wr2f wr2f 10 11 12 13 14 15 16 17 18 19 1B 1C 1D 1E 1F 1101 x x x x csramx csramx csramx csramx csramx csramx csramx csramx csramx 0 1 2 3 4 5 6 7 1110 x x x csfl x x x csram 0 1 csram2 csram 3 csram 4 csram 5 csram 6 csram 7 csram 1111 self self self Sys Sys x x x x X x x dsync sleep reset cal ocal gcal ocal gcal x Reserved TABLE IV ADS1218 Command Map 24 49 5 AD

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