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TEXAS INSTRUMENTS ADS1210 ADS1211 handbook

1. FIGURE 43 Single Supply High Accuracy Thermocouple Interface with Cold Junction Compensation BURR BROWN ADS1210 1211 38 1N4148 Ro 13kQ ADS1211U P FIGURE 44 Dual Supply High Accuracy Thermocouple Interface with Cold Junction Compensation REF200 O ADS1210 DRDY DSYNC SDOUT SDIO SCLK DVpp FIGURE 45 Low Cost Bridge Transducer Interface with Current Excitation 39 ADS1210 1211 BURR BROWN TOPIC INDEX TOPIC PAGE dz ujicpe 1 APPLICATIONS 12i cecctet eio ccen eicit dep eraat acc rise aaua 1 DESCRIPTION renti eren teet tagen etae cu s cu tris eco eess 1 SPEGIPICATIONS 2 pte ote utere tte ente 2 ABSOLUTE MAXIMUM RATINGS sssssseeeeene s 3 ELECTROSTATIC DISCHARGE SENSITIVITY sse 3 PACKAGE INFORMATION 2 1 eit rccte esee eret eter aget ii 3 ORDERING INFOBMHNATION nett etate hn tecnici e ranae nicae 3 ADS1210 SIMPLIFIED BLOCK DIAGRAM ADS1210 PIN GONFIGURATION ertet ee fs ADS1210 PIN DEFINITIONS ADS1211 SIMPLIFIED BLOCK DIAGRAM ADS1211P and ADS1211U PIN CONFIGURATION eee 5 ADS1211P and ADS1211U PIN DEFINITIONS ssseeee 5 A
2. 25 SDIO Input to Output Transition Timing 25 DRDY Rise and Fall Vito trece ertet 25 DSYNC to Xy Timing for Synchronizing Multiple ADSI210 N18 3 selected ciel 26 Exactly Synchronizing Multiple ADS1210 11s to Asynchronous DSYNC Signal sese 26 Timing of Data Output Register Update ssss 26 Flowchart for Writing and Reading Register Data Master Mode 27 Flowchart for Writing and Reading Register Data Slave Mode 28 Resetting the ADS1210 11 Slave Mode Only Three Wire Interface with an 8xC32 Microprocessor Three Wire Interface with an 8xC51 Microprocessor Four Wire Interface with an 8xC32 Microprocessor 32 Full Interface with an 8xC51 Microprocessor 32 Full Interface with a 68HC11 Microprocessor 33 Isolated Four Wire Interface eese 33 Source Current vs Voy for SDOUT Under Worst Case Conditions eese 34 Sink Current vs Vo for SDOUT Under Worst Case Conditions Affect of Synchronization on Output Data Timing 34 Bridge Transducer Interface with Voltage Excitation 36 Bridge Transducer Interface with Current Excitation 36 PT 100 nterface ee co pibe emeret ed aee ird drain 37 Complete 4 20mA Receiver esee 37 Sing
3. FIGURE 31 Full Interface with a 8xC51 Microprocessor BURR BROWN ADS1210 1211 AnP REF y AN REF our 68HC11 AGND AVpp Vsus MODE CS ADS1210 DRDY DSYNC SDOUT Xin SDIO Xo r SCLK DGND DVpp FIGURE 32 Full Interface with a 68HC11 Microprocessor AnP REF y AinN REF oyt AGND AVpp Veins MODE CS lt ADS1210 DRDY DSYNG SDOUT Xu SDIO Xour SCLK DGND DVpp FIGURE 33 Isolated Four Wire Interface Isolation In addition the digital outputs of the ADS1210 11 can in The serial interface of the ADS1210 11 provides for simple some cases drive opto isolators directly Figures 34 and 35 isolation methods An example of an isolated four wire show the voltage of the SDOUT pin versus source or sink interface is shown in Figure 33 The ISO150 is used to current under worst case conditions Worst case conditions transmit the digital signals over the isolation barrier for source current occur when the analog input differential BURR BROWN 33 ADS1210 1211 SOURCE CURRENT R 49 9kQ REF1004 42 5V R 49 9kQ REF1004 FIGURE 35 Sink Current vs
4. 0 ADS1210 BURR BROWN ADS1210 ADS1211 24 Bit ANALOG TO DIGITAL CONVERTER FEATURES DELTA SIGMA A D CONVERTER 23 BITS EFFECTIVE RESOLUTION AT 10Hz AND 20 BITS AT 1000Hz DIFFERENTIAL INPUTS PROGRAMMABLE GAIN AMPLIFIER FLEXIBLE SPI COMPATIBLE SSI INTERFACE WITH 2 WIRE MODE PROGRAMMABLE CUT OFF FREQUENCY UP TO 15 6kHz INTERNAL EXTERNAL REFERENCE ON CHIP SELF CALIBRATION ADS1211 INCLUDES 4 CHANNEL MUX APPLICATIONS INDUSTRIAL PROCESS CONTROL INSTRUMENTATION BLOOD ANALYSIS SMART TRANSMITTERS PORTABLE INSTRUMENTS WEIGH SCALES PRESSURE TRANSDUCERS AGND AVpp REFour O O O Second Order AY Modulator ADS1211 Only ADS1210 11 Modulator Control E DESCRIPTION The ADS1210 and ADS1211 are precision wide dynamic range delta sigma analog to digital converters with 24 bit resolution operating from a single 5V supply The differential inputs are ideal for direct connection to transducers or low level voltage sig nals The delta sigma architecture is used for wide dynamic range and to guarantee 22 bits of no missing code performance An effective resolution of 23 bits is achieved through the use of a very low noise input amplifier at conversion rates up to 10Hz Effective resolutions of 20 bits can be maintained up to a sample rate of kHz through the use of the unique Turbo modulator mode of operation The dynamic range of the converter
5. 5V nominal Reference Output 2 5V nominal Reference Input Dua oMWANOanoRwWD ak ek GRE Se i le aN DOO fw BURR BROWN ADS1210 1211 4 ADS1211 SIMPLIFIED BLOCK DIAGRAM AGND AVpp REFgyr REF O O O O Micro Controller Dios Order Instruction Register Third Order STO 9 D Fil Command Register vm igital Filter Data Output Register Offset Register tt Full Scale Register Serial Interface Eu E MODE DROY Modulator Control ADS1211P AND ADS1211U PIN CONFIGURATION ADS1211P AND ADS1211U PIN DEFINITIONS TOP VIEW DIP SOIC DESCRIPTION Inverting Input Channel 3 Noninverting Input Channel 2 Inverting Input Channel 2 Noninverting Input Channel 1 Inverting Input Channel 1 Analog Ground Bias Voltage Output 3 3V nominal Chip Select Input Control Input to Synchronize Serial Output Data System Clock Input System Clock Output for Crystal or Resonator Digital Ground Digital Supply 45V nominal Clock Input Output for serial data transfer Serial Data Input can also function as Serial Data Output Serial Data Output Data Ready SCLK Control Input Master 1 Slave 0 Analog Supply 5V nominal Reference Output 2 5V nominal Reference Input Noninverting Input Channel 4 Inverting Input Channel 4 Noninverting Input Channel 3 ADS1211P ADS1211U HARON UAOCPANOOAAWD k udo fetis al c o 0 m m O N N W N
6. AnP REF n AnN REF out AGND AVpp Vens MODE cs ADS1210 DRDY DSYNC SDOUT Xu SDIO Xour SCLK DGND DVpp Q D Q D Q ok Q CLK lt 1 2 74HC74 1 2 74HC74 FIGURE 28 Three Wire Interface with a 8xC32 Microprocessor P1 0 8xC51 AnP REF y AinN REF our AGND AVpp Vas MODE CS ADS1210 DRDY DSYNC SDOUT Xin SDIO Xour SCLK DGND DVpp FIGURE 29 Three Wire Interface with a 8xC51 Microprocessor BURR BROWN 31 ADS1210 1211 Four wire Interface Figure 30 shows a four wire interface with a 8xC32 micro processor Again the Slave Mode is being used Multi wire Interface Figures 31 and 32 show multi wire interfaces with a 8xC51 or 68HC11 microprocessor In these interfaces the mode of the ADS1210 11 is actually controlled dynamically This could be extremely useful when the ADS1210 11 is to be used in a wide variety of ways For example it might be desirable to have the ADS1210 11 produce data at a steady rate and to have the converter operating in the Continuous Read Mode But for system calibration the Slave Mode might be preferred because multiple instructions can be issued per conversion period Note that the MODE input should not be changed in the middle of a serial transfer This could result in misoperation of the device A Master Slave Mode change will not affect the output data
7. Conversions proceed as usual over the next three cycles in order to fill the digital filter DRDY remains HIGH during this time On the start of the fourth cycle DRDY goes LOW indicating valid data and resumption of normal operation System Offset Calibration A system offset calibration is performed after the bits 010 have been written to the Command Register Operation Mode bits MD2 through MDO This initiates the following sequence see Figure 6 At the start of the next conversion cycle the DRDY signal will not go LOW but will remain HIGH and will continue to remain HIGH throughout the calibration sequence The offset calibration will be per formed on the differential input voltage present at the converter s input over the next three conversion periods four in Slave Mode When this is done the Operation System Offset Normal Calibration Mode l Mode Analog Possibly Possibly Input Valid Valid Conversion Data Data 1 I l Offset Calibration on System olse um NOTES 1 SOC System Offset Calibration instruction 2 In Slave Mode this function requires 4 cycles FIGURE 6 System Offset Calibration Timing BURR BROWN ADS1210 1211 14 Mode bits are reset to 000 Normal Mode A single conver sion is done with DRDY HIGH After this conversion the DRDY signal goes LOW indicating resumption of normal operation Normal operation returns within a single c
8. ho AB BURR BROWN 5 ADS1210 1211 ADS1211E PIN CONFIGURATION ADS1211E PIN DEFINITIONS TOP VIEW DESCRIPTION Inverting Input Channel 3 Noninverting Input Channel 2 Inverting Input Channel 2 Noninverting Input Channel 1 Inverting Input Channel 1 Analog Ground Bias Voltage Output 3 3V nominal Not Internally Connected Not Internally Connected Chip Select Input Control Input to Synchronize Serial Output Data System Clock Input System Clock Output for Crystal or Resonator Digital Ground Digital Supply 5V nominal Clock Input Output for serial data transfer Serial Data Input can also function as Serial Data Output Serial Data Output Data Reagy Not Internally Connected Not Internally Connected SCLK Control Input Master 1 Slave 0 Analog Supply 5V nominal Reference Output 2 5V nominal Reference Input Noninverting Input Channel 4 Inverting Input Channel 4 Noninverting Input Channel 3 1 2 3 4 5 6 7 8 8 10 11 12 13 14 15 16 17 hk o m m mirer A o0omm o m m m m o Oo O BURR BROWN ADS1210 1211 6 TYPICAL PERFORMANCE CURVES At Ta 25 C AVpp DVpp 5V fy 10MHz programmable gain amplifier setting of 1 Turbo Mode Rate of one REFo disabled Vgi4s disabled and external 2 5V reference unless otherwise noted Effective Resolution in Bits rms Effective Resolution in Bits rms Effective R
9. In the bipolar mode the ADS1210 11 oper ates normally In the unipolar mode the conversion result is limited to positive values only zero included This bit only controls what is placed in the Data Output Register It has no effect on internal data When cleared the very next conversion will produce a valid bipolar result BD Byte Order Bit The BD bit controls the order in which bytes of data are read either most significant byte first or least significant byte as follows so evre ACCESS ORDER Most Significant Default to Least Significant Byte Least Significant to Most Significant Byte Note that when BD is clear and a multi byte read is initiated A3 A0 of the Instruction Register is the address of the most significant byte and subsequent bytes reside at higher ad dresses If BD is set then A3 AO is the address of the least significant byte and subsequent bytes reside at lower ad dresses The BD bit only affects read operations it has no affect on write operations MSB Bit Order Bit The MSB bit controls the order in which bits within a byte of data are read either most significant bit first or least significant bit as follows BIT ORDER 0 Most Significant Bit First Default 1 Least Significant Bit First The MSB bit only affects read operations it has no affect on write operations BURR BROWN ADS1210 1211 20 SDL Serial Data Line Bit The SDL bit controls which
10. noise can originate from switching power supplies very fast microprocessors or digital signal processors For either supply high frequency noise will generally be rejected by the digital filter except at interger multiplies of fmop Just below and above these frequencies noise will alias back into the passband of the digital filter affecting the conversion result If one supply must be used to power the ADS1210 11 the AV py supply should be used to power DVpp This connec tion can be made via a 10 resistor which along with the decoupling capacitors will provide some filtering between DVpp and AVpp In some systems a direct connection can be made Experimentation may be the best way to determine the appropriate connection between AVpp and DV py GROUNDING The analog and digital sections of the design should be care fully and cleanly partitioned Each section should have its own ground plane with no overlap between them AGND should be connected to the analog ground plane as well as all other analog grounds DGND should be connected to the digital ground plane and all digital signals referenced to this plane The ADS1210 11 pinout is such that the converter is cleanly separated into an analog and digital portion This should allow simple layout of the analog and digital sections of the design 35 For a single converter system AGND and DGND of the ADS1210 11 should be connected together underneath the converter Do not jo
11. AnP REF iy AinN REF our AGND AVpp Vens MODE C8 ADS1210 DRDY Note that the Xy input can also be controlled It is possible with some microcontrollers and digital signal processors to produce a continuous serial clock which could be connected to the Xj input The frequency of the clock is often settable over some range Thus the power dissipation of the ADS1210 11 could be dynamically varied by changing both the Turbo Mode and Xj input trading off conversion speed and resolution for power consumption I O Recovery If serial communication stops during an instruction or data transfer for longer than 4 ty A74 the ADS1210 11 will reset its serial interface This will not affect the internal registers The main controller must not continue the transfer after this event but must restart the transfer from the beginning This feature is very useful if the main controller can be reset at any point After reset simply wait 8 tpara before starting serial communication v UU U UU UD U U DSYNC SDOUT SDIO SCLK DVpp D Q D CLK 4 Q CLK 1 2 74HC74 1 2 74HC74 AnP REFN AN REF our AGND AVpp Veias MODE CS ADS1210 pnpy P1 0 8xC51 Voc P1 1 P0 0 P0 1 P0 2 P0 3 DSYNC SDOUT P0 4 Xin SDIO Xour SCLK P0 5 DGND DVpo P0 6
12. Analog Possibly Possibly Input Valid Valid Conversion Data Full Scale Calibration on System Full Scale Valid Data NOTES 1 SFSC System Full Scale Calibration instruction 2 In Slave Mode this function requires 4 cycles FIGURE 7 System Full Scale Calibration Timing Normal operation returns within a single conversion cycle because it is assumed that the input voltage at the converter s input is not removed immediately after the full scale calibra tion is performed In this case the digital filter already contains a valid result For full system calibration offset calibration must be per formed first and then full scale calibration The calibration error will be a sum of the rms noise on the conversion result and the input signal noise See the System Calibration Limits section for information regarding the limits on the magni tude of the system full scale voltage Pseudo System Calibration The Pseudo System Calibration is performed after the bits 100 have been written to the Command Register Operation Mode bits MD2 through MDO This initiates the following sequence see Figure 8 At the start of the next conversion cycle the DRDY signal will not go LOW but will remain HIGH and will continue to remain HIGH throughout the calibration sequence The offset calibration will be performed on the differential input voltage present at the converter s input over the next three conversion periods four in S
13. DRDY goes LOW the ADS1210 11 Instruction Register will not be entered Instead the Instruc tion Register contents will be re used and the new contents of the Data Output Register or some part thereof will be transmitted This will occur as long as CS is LOW and not toggled This mode of operation is called the Continuous Read Mode and is shown in the read flowcharts of Figures 25 and 26 It is also shown in the Timing Diagrams of Figures 18 and 19 in the Timing section Note that once CS has been taken HIGH the Continuous Read Mode will be enabled but not entered and can never be disabled The mode is actually entered and exited as described above Power On Conditions for SDIO Even if the SDIO connection will be used only for input there is one important item to consider regarding SDIO This only applies when the ADS1210 11 is in the Master Mode and CS will be tied LOW At power up the serial I O lines of most microcontrollers and digital signal processors will be in a tri state condition or they will be configured as inputs When power is applied to the ADS1210 11 it will begin operating as defined by the default condition of the Com mand Register see Table X in the System Configuration section This condition defines SDIO as the data output pin Since the ADS1210 11 is in the Master Mode and CS is tied LOW the serial clock will run whenever DRDY is LOW and an instruction will be entered and executed If the SDIO line
14. Each contains a programmable gain amplifier PGA a second order delta sigma modulator a programmable digi tal filter a microcontroller including the Instruction Com mand and Calibration registers a serial interface a clock generator circuit and an internal 2 5V reference The ADS1211 includes a 4 channel input multiplexer In order to provide low system noise common mode rejec tion of 115dB and excellent power supply rejection the design topology is based on a fully differential switched capacitor architecture Turbo Mode a unique feature of the ADS1210 11 can be used to boost the sampling rate of the input capacitor which is normally 19 5kHz with a 10MHz clock By programming the Command Register the sam pling rate can be increased to 39kHz 78kHz 156kHz or 312kHz Each increase in sample rate results in an increase in performance when maintaining the same output data rate The programmable gain amplifier PGA of the ADS1210 11 can be set to a gain of 1 2 4 8 or 16 substantially increasing the dynamic range of the converter and simplify ing the interface to the more common transducers see Table D This gain is implemented by increasing the number of samples taken by the input capacitor from 19 5kHz for a gain of 1 to 312kHz for a gain of 16 Since the Turbo Mode and PGA functions are both implemented by varying the sampling frequency of the input capacitor the combination of PGA gain and Turbo Mode Rate is limited t
15. Vog for SDOUT Under Worst Case Conditions voltage is 5V and the output format is Offset Binary FFFFFF For sink current the worst case condition oc curs when the analog input differential voltage is OV and the output format is Two s Complement 0000004 Note that SDOUT is tri stated for the majority of the conversion period and the opto isolator connection must take this into account Synchronization of Multiple Converters The DSYNC input is used to synchronize the output data of multiple ADS1210 11s Synchronization involves configur ing each ADS1210 11 to the same Decimation Ratio and Turbo Mode setting and providing a common signal to the X inputs Then the DSYNC signal is pulsed LOW see Figure 22 in the Timing section This results in an internal reset of the modulator count for the current conversion Thus all the converters start counting from zero at the same time producing a DRDY LOW signal at approximately the same point see Figure 36 BURR BROWN ADS1210 1211 Note that an asynchronous DSYNC input may cause mul tiple converters to be different from one another by one Xj clock cycle This should not be a concern for most applica tions However the Timing section contains information on exactly synchronizing multiple converters to the same Xqy clock cycle FIGURE 36 Affect of Synchronization on Output Data Timing LAYOUT POWER SUPPLIES The ADS1210 11 requires the digital supply DVpp
16. When the internal reference REFoyr is con nected to the reference input REF V gis is 3 3V nominal REFO Reference Output Bit The REFO bit controls the internal reference REFoyr state either on 2 5V or off disabled as follows REFO INTERNAL REFERENCE REF oy STATUS cx 0 Off High Impedance 1 On 2 5V Default The internal reference circuitry consumes approximately 1 6mA of steady state current with no external load See the Reference Output section for full details on the internal reference BURR BROWN ADS1210 1211 DF Data Format Bit The DF bit controls the format of the output data either Two s Complement or Offset Binary as follows EM FORMAT ANALOG INPUT DIGITAL OUTPUT E 3 Two s Complement Full Scale Default Zero Full Scale 7FFFFF 0000004 8000004 FFFFFF 800000 000000 Full Scale Zero Full scale Offset Binary These two formats are the same for all bits except the most significant which is simply inverted in one format vs the other This bit only applies to the Data Output Register it has no effect on the other registers U B Unipolar Bit The U B bit controls the limits im posed on the output data as follows wove urs U B 0 Bipolar None Default 1 Unipolar Zero to Full Scale only The particular mode has no effect on the actual full scale range of the ADS1210 11 data format or data format vs input voltage
17. also includes complete on board calibra tion that can correct for internal offset and gain errors or limited external system errors Internal calibration can be run when needed or automatically and continuously in the background System calibration can be run as needed and the appropriate input voltages must be provided to the ADS1210 11 For this reason there is no continuous System Calibra tion Mode The calibration registers are fully readable and writable This feature allows for switching between various configurations different data rates Turbo Mode Rates and gain settings without re calibrating The various settings rates modes and registers of the ADS1210 11 are read or written via a synchronous serial interface This interface can operate in either a self clocked mode Master Mode or an externally clocked mode Slave Mode In the Master Mode the serial clock SCLK fre quency is one half of the ADS1210 11 Xj clock frequency This is an important consideration for many systems and may determine the maximum ADS1210 11 clock that can be used The high resolution and flexibility of the ADS1210 11 allow these converters to fill a wide variety of A D conversion tasks In order to ensure that a particular configuration will meet the design goals there are several important items which must be considered These include but are certainly not limited to the needed resolution required linearity desired input bandwidth pow
18. and the main controller Consult Making Use of DSYNC in the Serial Interface section for more information MD2 MD0 Operating Mode Bits The MD2 MDO bits initiate or enable the various calibration sequences as follows wa wor woo oPcratma mone Normal Mode Self Calibration System Offset Calibration System Full Scale Calibration Pseudo System Calibration Background Calibration Sleep Reserved eek eh Cy CO CO CO 0 0 1 1 0 0 1 1 o oO Oo oO The Normal Mode Background Calibration Mode and Sleep Mode are permanent modes and the ADS1210 11 will remain in these modes indefinitely All other modes are temporary and will revert to Normal Mode once the appro priate actions are complete See the Calibration and Sleep Mode sections for more information Data Deci Rate mation Hz Ratio MEO e EG ES LN og 0000 35 co i E N eve EG MES ev EG EH seasea a mox OOOO OO Om Oro O O O Hl OHG Table XI Decimation Ratios vs Data Rates Turbo Mode rate of 1 and 10MHz clock G2 G0 PGA Control Bits The G2 G0 bits control the The input capacitor sampling frequency and modulator rate gain setting of the PGA as follows can be calculated from the following equations SAMP Ge TMR fygn 512 fuop TMR fyxqy 512 where G is the gain setting and TMR is the Turbo Mode Rate The sampling frequency of the input capacitor directly relates to t
19. consisting of minimal analog signal processing basic filtering and gain a self contained microcontroller and one clock source high resolution could be achieved by powering all components by a common power supply In addition all components could share a common ground plane Thus there would be no distinctions between analog and digital power and ground The layout should still include a power plane a ground plane and careful decoupling In a more extreme case the design could include multiple ADS1210 11s extensive analog signal processing one or more microcontrollers digital signal processors or micro processors many different clock sources and interconnec tions to various other systems High resolution will be very difficult to achieve for this design The approach would be to break the system into as many different parts as possible For example each ADS1210 11 may have its own analog processing front end its own analog power and ground possibly shared with the analog front end and its own digital power and ground The converter s digital power and ground would be separate from the power and ground for the system s processors RAM ROM and glue logic BURR BROWN ADS1210 1211 APPLICATIONS The ADS1210 11 can be used in a broad range of data acquisition tasks The following application diagrams show the ADS1210 and or ADS1211 being used for bridge trans ducer measurements temperature mea
20. error perform a calibration read the desired calibration register change the error value perform another calibration read the new value and use these values to interpolate an intermediate value BURR BROWN ADS1210 1211 Offset Calibration on Internal cdi 2 i DRDY zn i Self Calibration Mode I Full Scale Calibration on Internal didi 1 Normal Analog Input eee i NOTES 1 SC Self Calibration instruction 2 In Slave Mode this function requires 4 cycles FIGURE 5 Self Calibration Timing Self Calibration A self calibration is performed after the bits 001 have been written to the Command Register Operation Mode bits MD2 through MDO This initiates the following sequence at the start of the next conversion cycle see Figure 5 The DRDY signal will not go LOW but will remain HIGH and will continue to remain HIGH throughout the calibration sequence The inputs to the sampling capacitor are discon nected from the converter s analog inputs and are shorted together An offset calibration is performed over the next three conversion periods four in Slave Mode Then the input to the sampling capacitor is connected across REF and a full scale calibration is performed over the next three conversions After this the Operation Mode bits are reset to 000 normal mode and the input capacitor is reconnected to the input
21. is HIGH as it might be with an active pull up then the instruction is a read operation and SDIO will become an output every DRDY LOW period for 32 serial clock cycles When the serial port on the main controller is enabled signal contention could result 29 The recommended solution to this problem is to actively pull SDIO LOW If SDIO is LOW when the ADS1210 11 enters the instruction byte then the resulting instruction is a write of one byte of data to the Data Output Register which results in no internal operation If the SDIO signal cannot be actively pulled LOW then another possibility is to time the initialization of the controller s serial port such that it becomes active between adjacent DRDY LOW periods The default configuration for the ADS1210 11 produces a data rate of 814Hz a conver sion period of 1 2ms This time should be more than ad equate for most microcontrollers and DSPs to monitor DRDY and initialize the serial port at the appropriate time Master Mode The Master Mode is active when the MODE input is HIGH All serial clock cycles will be produced by the ADS1210 11 in this mode and the SCLK pin is configured as an output The frequency of the serial clock will be one half of the Xn frequency Multiple instructions cannot be issued during a single conversion period in this mode only one instruction per conversion cycle is possible The Master Mode will be difficult for some microcontrollers pa
22. of current In addition loading the reference with a dynamic or variable load is not recommended This can result in small changes in reference voltage as the load changes Finally for designs approaching or exceeding 20 bits of effective resolution a low noise external reference is recommended as the internal reference may not provide adequate performance BURR BROWN ADS1210 1211 FIGURE 12 10V Input Configuration Using V grs The circuitry which generates the 2 5V reference can be disabled via the Command Register and will result in a lower power dissipation The reference circuitry consumes a little over 1 6mA of current with no external load When the ADS1210 11 is in its default state the internal reference is enabled Vans The VgjAs output voltage is dependent on the reference input REF voltage and is approximately 1 33 times as great This output is used to bias input signals such that bipolar signals with spans of greater than 5V can be scaled to match the input range of the ADS1210 11 Figure 12 shows a connection diagram which will allow the ADS1210 11 to accept a 10V input signal 40V full scale range This method of scaling and offsetting the 20V differential input signal will be a concern for those requiring minimum power dissipation Vgj4s will supply 1 68mA for every chan nel connected as shown For the ADS1211 the current draw is within the specifica
23. the Vpyag circuitry consumes approximately 1mA with no external load On power up external signals may be present before Vpras is enabled This can create a situation in which a negative voltage is applied to the analog inputs 2 5V for the circuit shown in Figure 12 reverse biasing the negative input protection diode This situation should not be a problem as long as the resistors R and R limit the current being sourced by each analog input to under 10mA a potential of OV at the analog input pin should be used in the calculation DIGITAL OPERATION SYSTEM CONFIGURATION The Micro Controller MC consists of an ALU and a register bank The MC has two states power on reset and convert In the power on reset state the MC resets all the registers to their default state sets up the modulator to a stable state and performs self calibration at a 850Hz data rate After this it enters the convert mode which is the normal mode of operation for the ADS1210 11 The ADS1210 11 has 5 internal registers as shown in Table VII Two of these the Instruction Register and the Com mand Register control the operation of the converter The Data Output Register DOR contains the result from the most recent conversion The Offset and Full Scale Calibra tion Registers OCR and FCR contain data used for correct ing the internal conversion result before it is placed into the DOR The data in these two registers may be the result of a calibrati
24. to be no greater than the analog supply AVpp 0 3V In the majority of systems this means that the analog supply must come up first followed by the digital supply Failure to observe this condition could cause permanent damage to the ADS1210 11 Inputs to the ADS1210 11 such as SDIO Am or REF should not be present before the analog and digital supplies are on Violating this condition could cause latch up If these signals are present before the supplies are on series resistors should be used to limit the input current see the Analog Input and V gjAs sections of this data sheet for more details concerning these inputs The best scheme is to power the analog section of the design and AV pp of the ADS1210 11 from one 5V supply and the digital section and DVpp from a separate 5V supply The analog supply should come up first This will ensure that Aq and REF do not exceed AVpp and that the digital inputs are present only after AVpp has been established and that they do not exceed DVpp The analog supply should be well regulated and low noise For designs requiring very high resolution from the ADS1210 11 power supply rejection will be a concern See the PSRR vs Frequency curve in the Typical Performance Curves section of this data sheet for more information The requirements for the digital supply are not as strict However high frequency noise on DVpp can capacitively couple into the analog portion of the ADS1210 11 This
25. 1211 10 For example when the converter is configured with a 2 5V reference and placed in a gain setting of 2 the typical input voltage range is 1 25V to 3 75V However an input range of OV to 2 5V or 2 5V to 5V would also cover the converter s full scale range Voltage Span tThis is simply the magnitude of the typical analog input voltage range For example when the converter is configured with a 2 5V reference and placed in a gain setting of 2 the input voltage span is 2 5V Least Significant Bit LSB Weight This is the theoreti cal amount of voltage that the differential voltage at the analog input would have to change in order to observe a change in the output data of one least significant bit It is computed as follows Full Scale Range 2 N LSB Weight where N is the number of bits in the digital output Effective Resolution The effective resolution of the ADS1210 11 in a particular configuration can be expressed in two different units bits rms referenced to output and microvolts rms referenced to input Computed directly from the converter s output data each is a statistical calcu lation based on a given number of results Knowing one the other can be computed as follows 10V 20 log pom __ 1 76 ER in Vrms ER in bits rms 6 02 10V Gay 6 02 ER in bits rms 1 76 IE RE ER in Vrms The 10V figure in each calculation represents the full scale ran
26. 3 show the digital filter response for a data rate of 50Hz and 60Hz respectively NORMALIZED DIGITAL FILTER RESPONSE 2 3 Frequency Hz FILTER RESPONSE 150 Frequency Hz FILTER RESPONSE Gain dB M FILTER RESPONSE Gain dB 150 Frequency Hz FILTER RESPONSE Gain dB AU 60 Frequency Hz FIGURE 3 Digital Filter Response at a Data Rate of 60Hz If the effective resolution at a 50Hz or 60Hz data rate is not adequate for the particular application then power line fre quencies could still be rejected by operating the ADS1210 11 at 25 30Hz 16 7 20Hz 12 5 15Hz etc If a higher data rate is needed then power line frequencies must either be rejected before conversion with an analog notch filter or after conversion with a digital notch filter running on the main controller BURR BROWN ADS1210 1211 Filter Equation The digital filter is described by the following transfer function 3 rex sin KPdo H f MOD Nes DE f mop where N is the Decimation Ratio This filter has a sin x x 3 response and is referred to a sinc filter For the ADS1210 11 this type of filter allows the data rate to be changed over a ve
27. CURVES CONT At T4 25 C AVpp DVpp 5V fxi 10MHz programmable gain amplifier setting of 1 Turbo Mode Rate of 1 REFoy7 disabled Vgis disabled and external 2 5V reference unless otherwise noted POWER DISSIPATION vs TURBO MODE RATE POWER DISSIPATION vs TURBO MODE RATE REF oyz Enabled External Reference REFoyr 50 0 40 0 z 400 c 30 0 2 2 10MHz oO oO B a E 8 a a 5MHz p ce g 200 72 5MHz o o n n 1MHz 20 0 10 0 1 2 4 8 16 1 2 4 8 16 Turbo Mode Rate Turbo Mode Rate PSRR vs FREQUENCY CMRR vs FREQUENCY 85 0 120 0 80 0 g x 75 0 B 115 0 79 z n o 70 0 65 0 110 0 0 1 1 10 100 1k 10k 100k 0 1 1 10 100 1k Frequency Hz Frequency Hz LINEARITY vs TEMPERATURE 60Hz Data Rate 8 A09 C 6 5 C E 4259C 2 4 rer TE 55 C 2 eS ae se 4850 g 2 A E A 9 0 z s m sleet PERENNEM NM 6 5 4 8 2 i 0 1 2 3 4 5 Analog Input Differential Voltage V BURR BROWN ADS1210 1211 8 THEORY OF OPERATION The ADS1210 and ADS1211 are precision high dynamic range self calibrating 24 bit delta sigma A D converters capable of achieving very high resolution digital results
28. DITIONS MIN TYP ANALOG INPUT Input Voltage Range With Vegas 2 Input Impedance G Gain TMR Turbo Mode Rate Programmable Gain Amplifier User Programmable 1 2 4 8 or 16 Input Capacitance Input Leakage Current At 25 C At Twin to Tmax SYSTEMS PERFORMANCE Resolution No Missing Codes fparA 60Hz Integral Linearity foata 60Hz 0 0015 foara 1000Hz TMR of 16 0 0015 Unipolar Offset Error 4 See Note 5 Unipolar Offset Drift 9 1 Gain Error See Note 5 Gain Error Drift 6 1 Common Mode Rejection At DC 25 C 115 At DC Ty to Trax 115 Normal Mode Rejection Output Noise See Typical Performance Curves Power Supply Rejection DC 50Hz and 60Hz VOLTAGE REFERENCE Internal Reference REF yr Drift Noise Load Current Source or Sink Output Impedance External Reference REF n Load Current Vesias Output Using Internal Reference Drift Load Current Source or Sink DIGITAL INPUT OUTPUT Logic Family TTL Compatible CMOS Logic Level all except Xn Vin l4 54A Vit I 5pA Vou lou 2 TTL Loads VoL lo 2 TTL Loads Xin Input Levels Vi Vu Xin Frequency Range fxn Output Data Rate fpata User Programmable fxn 500kHz Data Format User Programmable Two s Complement or Offset Binary SYSTEM CALIBRATION Offset and Full Scale Limits Ves Full Scale Differential Voltage 8 0 7 2 REFn G Ves Vos Vos Offset Differential Voltage 1 3 2 REFiy G The information provided
29. DS1211E PIN CONFIGURATION nnen eene 6 ADS12T1E PIN DEFINITIONS ien rtr knee rente 6 TYPICAL PERFORMANCE CURVES esses 7 THEORY OF OPERATION cc s ssccssssesesssecsessseeensseesnsscesenssees 9 DEFINITION OP TERMS sescenti Rn Ea Renan ARE 10 DIGITAL IONI S M 11 Filter Equation Filter Settling TURBO MODE rase FEE EHE EC BREED RIEEEEH EO UE UU D LIE AN PROGRAMMABLE GAIN AMPLIFIER c cccceeeeeeeeeeeeeeeeeereeeteeeneees 13 SOFTWARE QUAIN ais cni epp tee ctr prb o er Pp po eed credula 13 CALIBRATION ew T I 13 Solf Callbrelioli auo RS Her a D EFE E alia its 14 System Offset Calibration 2 iere t ee deem 14 System Full Scale Calibration eene 14 Pseudo System Calibration eene 15 Background Calibration System Calibration Offset and Full Scale Calibration Limits 16 SLEEP MODE aste rd a Pda cubes aie 16 BURR BROWN ADS1210 1211 40 DIGITAL OPERATION TOPIC PAGE ANALOG OPERATION ccccscssssssssssessessesssseeseesevsevsnvsesseseseeee 17 ANALOG INPUT m 17 SYSTEM CONFIGURATION cc eceseeseeseesesseeceeesreseeeeseesceaeesseeeseetseas 18 Instruction Register INSR seen 19 Command Register CMR essssessseereenneeennrrnnrt nenne 19 Data Output Register DOR eie Heer 21 Offset Calibrati
30. DSYNC signal to the Xy signal can be ignored For other multiple converter applications this one Xqy clock cycle difference could be a problem These types of applications would include using the DRDY and or the SCLK output from one ADS1210 11 as the master signal for all converters To ensure exact synchronization to the same Xj edge the timing relationship between the DSYNC and Xy signals as shown in Figure 22 must be observed Figure 23 shows a simple circuit which can be used to clock multiple ADS1210 11s from one ADS1210 11 as well as to ensure that an asynchronous DSYNC signal will exactly synchro nize all the converters FIGURE 22 DSYNC to Xj Timing for Synchronizing Mutliple ADS1210 11s 1 2 74AHC74 Asynchronous SERIAL INTERFACE The ADS1210 11 includes a flexible serial interface which can be connected to microcontrollers and digital signal processors in a variety of ways Along with this flexibility there is also a good deal of complexity This section de scribes the trade offs between the different types of interfac ing methods in a top down approach starting with the overall flow and control of serial data moving to specific interface examples and then providing information on vari ous issues related to the serial interface Multiple Instructions The general timing diagrams which appear throughout this data sheet show serial communication to and from the ADS1210 11 occurring d
31. Exact Synchronization of Multiple Converters only Falling Edge of X to DSYNC Not Valid LOW for Exact Synchronization of Multiple Converters only Falling Edge of Last SCLK for Register Data to Rising Edge of First SCLK of next INSR Slave Mode CS Tied LOW Rising Edge of CS to Falling Edge of CS Slave Mode Using CS Falling Edge of DRDY to First SCLK Rising Edge Slave Mode CS Tied LOW TABLE XV Digital Timing Characteristics 23 0 5 100 0 4 tyi 0 4 tyi 55 ixi 4 bay 0 5 txin 5 tyin 10 5 5 ixi ADS1210 1211 10 MHz BURR BROWN f M 8 H 3 p m EN n 3 F lm m ww 7 Write Register Data oww Read Register Data using SDIO o T Read Register Data using SDOUT FIGURE 16 Serial Interface Timing CS LOW Master Mode Write Register Data int mo oum Read Register Data using SDIO re ra oo Read Register Data using SDOUT FIGURE 17 Serial Interface Timing CS LOW Slave Mode Write Register Data Read Register Data using SDIO Read Register Data using SDOUT Continuous Read of Data Output Register using SDIO Continuous Read of Data Output Register using SDOUT FIGURE 18 Serial Interface Timing Using CS Master Mode BURR BROWN ADS1210 1211 24 f s lig wI I IwIw T 7 Write Register Data nm mni No pouty
32. Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 FIGURE INDEX TITLE PAGE Normalized Digital Filter RESPONSE riisci 11 Digital Filter Response at a Data Rate of 50Hz 11 Digital Filter Response at a Data Rate of 60Hz 11 Asynchronous ADS1210 11 Analog Input Voltage Step or ADS1211 Channel Change to Fully Settled Output Data 12 S l Calibration Tilmifig totae reete etes 14 System Offset Calibration Timing see 14 System Full Scale Calibration 14 Pseudo System Calibration Timing essss 15 Background Calibration 5er ettet pet 15 Sleep Mode to Normal Mode Timing ess 17 Analog Input SIr ctUfe 5 or nee ence 17 10V Input Configuration Using Vgis s sssssseesssstssstnseensee 18 Xin Clock Timing e inate Serial Input Output Timing Master Mode Serial Input Output Timing Slave Mode Serial Interface Timing CS LOW Master Mode 24 Serial Interface Timing CS LOW Slave Mode 24 Serial Interface Timing Using CS Master Mode 24 Serial Interface Timing Using CS Slave Mode
33. HIGH External Serial Clock LOW Data In Valid to External SCLK Falling Edge Setup External SCLK Falling Edge to Data In Not Valid Hold Data Out Valid to External SCLK Falling Edge Setup External SCLK Falling Edge to Data Out Not Valid Hold Falling Edge of DRDY to First SCLK Rising Edge Master Mode CS Tied LOW Falling Edge of Last SCLK for INSR to Rising Edge of First SCLK for Register Data Master Mode Falling Edge of Last SCLK for Register Data to Rising Edge of DRDY Master Mode Falling Edge of Last SCLK for INSR to Rising Edge of First SCLK for Register Data Slave Mode Falling Edge of Last SCLK for Register Data to Rising Edge of DRDY Slave Mode Falling Edge of DRDY to Falling Edge of CS Master and Slave Mode Falling Edge of CS to Rising Edge of SCLK Master Mode Rising Edge of DRDY to Rising Edge of CS Master and Slave Mode Falling Edge of CS to Rising Edge of SCLK Slave Mode Falling Edge of Last SCLK for INSR to SDIO Tri state Master Mode SDIO as Output to Rising Edge of First SCLK for Register Data Master and Slave Modes Falling Edge of Last SCLK for INSR to SDIO Tri state Slave Mode SDIO Tri state Time Master and Slave Modes Falling Edge of Last SCLK for Register Data to SDIO Tri State Master Mode Falling Edge of Last SCLK for Register Data to SDIO Tri state Slave Mode DRDY Fall Time DRDY Rise Time Minimum DSYNC LOW Time DSYNC Valid HIGH to Falling Edge of Xi for
34. Read Register Data Using SDIO SDOUT X OUM ouT1 OUTO Read Register Data Using SDOUT DRDY tye cs SCLK toy Continuous Read of Data Output Register using SDIO i 7 Continuous Read of Data Output Register using SDOUT FIGURE 19 Serial Interface Timing Using CS Slave Mode Master Mode SDIO SCLK Slave Mode SDIO SDIO is an input SDIO is an output NOTE 1 CS is optional FIGURE 20 SDIO Input to Output Transition Timing FIGURE 21 DRDY Rise and Fall Time BURR BROWN 25 ADS1210 1211 Synchronizing Multiple Converters A negative going pulse on DSYNC can be used to synchro nize multiple ADS1210 11s This assumes that each ADS1210 is driven from the same master clock and is set to the same Decimation Ratio and Turbo Mode Rate The affect that this signal has on data output timing in general is discussed in the Serial Interface section The concern here is what happens if the DSYNC input is completely asynchronous to this master clock If the DS YNC input rises at a critical point in relation to the master clock input then some ADS1210 11s may start up one Xj clock cycle before the others Thus the output data will be syn chronized but only to within one Xj clock cycle For many applications this will be more than adequate In these cases the timing symbols which relate the
35. aken LOW Alternatively SDIO can be forced HIGH after putting the ADS1210 11 to sleep and then taken LOW when the Sleep Mode is to be exited Finally if CS is not being used tied LOW and the ADS1210 11 is in the Slave Mode then simply sending a normal Instruction Register command will re establish communication Once serial communication is resumed the Sleep Mode is exited by changing the MD2 MDO bits to any other mode When a new mode other than Sleep has been entered the ADSI210 11 will execute a very brief internal power up sequence of the analog and digital circuitry Once this has been done one normal conversion cycle is performed before the new mode is actually entered At the end of this conversion cycle the new mode takes effect and the converter will respond accordingly The DRDY signal will remain HIGH through the first conversion cycle It will also remain HIGH through the second even if the new mode is the Normal Mode If the VgjAs generator and or the internal reference have been disabled then they must be manually re enabled via the appropriate bits in the Command Register In addition the internal reference will have to charge the external bypass capacitor s and possibly other circuitry There may also be considerations associated with Vgj4s and the settling of external circuitry All of these must be taken into account when determining the amount of time required to resume normal operation The timing dia
36. al resistors and VgiAs as described in the text Other ranges are possible 3 Input impedance is higher with lower fq 4 Applies after calibration 5 After system calibration these errors will be of the order of the effective resolution of the converter Refer to the Typical Performance Curves which apply to the desired mode of operation 6 Recalibration can remove these errors 7 The specification also applies at fpara i where i is 2 3 4 etc 8 Voltages at the analog inputs must remain within AGND to AVpp 9 The common mode rejection test is performed with a 100mV differential input ABSOLUTE MAXIMUM RATINGS Analog Input Current 2 e drei Voltage 100mA Momentary 10mA Continuous 0 3V to AVpp 0 3V PACKAGE ORDERING INFORMATION PACKAGE DRAWING TEMPERATURE NUMBER PRODUCT PACKAGE AV pp to DVpp 0 3V to 6V AVpp to AGND DVpp to DGND AGND to DGND REF Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Lead Temperature soldering 10s Power Dissipation Any package ADS1210P ADS1210U ADS1211P ADS1211U ADS1211E 18 Pin Plastic DIP 18 Lead SOIC 24 Pin Plastic DIP 24 Lead SOIC 28 Lead SSOP 40 C to 85 C 40 C to 85 C 40 C to 85 C 40 C to 85 C 0 3V to AVpp 0 3V 40 C to 85 C 0 3V to DVpp 0 3V 0 3V to DVpp 0 3V NOTE 1 For detailed drawing and dimension table please see end of data sheet
37. cant Bit TABLE XIII Offset Calibration Register The contents of the OCR are in Two s Complement format This is not affected by the DF bit in the Command Register Full Scale Calibration Register FCR The FCR is a 24 bit register which contains the full scale correction factor that is applied to the conversion result before it is placed in the Data Output Register see Table XIV In most applications the contents of this register will be the result of either a self calibration or a system calibration Vost Significant Bit Byte 2 Byte 1 Byte 0 Least Significant Bit TABLE XIV Full Scale Calibration Register The FCR is both readable and writable via the serial inter face For applications requiring a more accurate full scale calibration multiple calibrations can be performed each resulting FCR value read the results averaged and a more precise calibration value written back to the FCR BURR BROWN ADS1210 1211 22 The actual FCR value will change from part to part and with configuration temperature and power supply Thus the actual FCR value for any arbitrary situation cannot be accurately predicted That is a given system full scale error cannot be corrected simply by measuring the error exter nally computing a correction factor and writing that value to the FCR In addition be aware that the contents of the FCR are not used to directly correct the conversion result Rather the correction is a
38. citor sampling fre quency Thus higher gain settings result in a lower analog input impedance Ayn Impedance Q 10MHZ fyjy 4 3E6 GeSTMR where TMR is the Turbo Mode Rate Because the modulator speed does not depend on the gain setting the input imped ance seen at REFqy does not change The PGA can be set to gains of 1 2 4 8 or 16 These gain settings with their resulting full scale range and typical voltage range are shown in Table I Keep in mind that higher Turbo Mode Rates result in fewer available gain settings as shown in Table II SOFTWARE GAIN The excellent performance flexibility and low cost of the ADS1210 11 allow the converter to be considered for de signs which would not normally need a 24 bit ADC For example many designs utilize a 12 bit converter and a high gain INA or PGA for digitizing low amplitude signals For some of these cases the ADS1210 11 by itself may be a solution even though the maximum gain is limited to 16 To get around the gain limitation the digital result can simply be shifted up by n bits in the main controller resulting in a gain of n times G where G is the gain setting While this type of manipulation of the output data is obvious it is easy to miss how much the gain can be increased in this manner on a 24 bit converter For example shifting the result up by three bits when the ADS1210 11 is set to a gain of 16 results in an effective gain of 128 At lower
39. data rates the converter can easily provide more than 12 bits of resolution Even higher gains are possible The limitation is a combination of the needed data rate desired noise performance and desired linearity CALIBRATION The ADS1210 11 offers several different types of calibra tion and the particular calibration desired is programmed via the Command Register In the case of Background Calibration the calibration will repeat at regular intervals indefinitely For all others the calibration is performed once and then normal operation is resumed Each type of calibration is covered in detail in their respec tive section In general calibration is recommended imme diately after power on and whenever there is a significant change in the operating environment The amount of change which should cause a re calibration is dependent on the application effective resolution etc Where high accuracy is important re calibration should be done on changes in temperature and power supply In all cases re calibration should be done when the gain Turbo Mode or data rate is changed After a calibration has been accomplished the Offset Cali bration Register and the Full Scale Calibration Register contain the results of the calibration The data in these registers are accurate to the effective resolution of the ADS1210 11 s mode of operation during the calibration Thus these values will show a variation or noise equiva lent to a re
40. ential voltage is given by the follow ing equation AP A N Thus a positive digital output is produced whenever the analog input differential voltage is positive while a negative digital output is produced when ever the differential is negative For example when the converter is configured with a 2 5V reference and placed in a gain setting of 2 the positive full scale output is produced when the analog input differential is 2 5V The negative full scale output is produced when the differential is 2 5V In each case the actual input voltages must remain within the AGND to AVpp range see Table I Actual Analog Input Voltage The voltage at any one analog input relative to AGND Full Scale Range FSR As with most A D converters the full scale range of the ADSI210 11 is defined as the input which produces the positive full scale digital output minus the input which produces the negative full scale digital output For example when the converter is configured with a 2 5 V reference and is placed in a gain setting of 2 the full scale range is 2 5V positive full scale minus 2 5V negative full scale 5V Typical Analog Input Voltage Range This term de scribes the actual voltage range of the analog inputs which will cover the converter s full scale range assuming that each input has a common mode voltage that is greater than REF m PGA and smaller than AVpp REFjy PGA BURR BROWN ADS1210
41. er consumption goal and sen sor output voltage The remainder of this data sheet discusses the operation of the ADSI210 11 in detail In order to allow for easier comparison of different configurations effective resolu ton is used as the figure of merit for most tables and graphs For example Table III shows a comparison between data rate and 3dB input bandwidth versus PGA setting at a Turbo Mode Rate of 1 and a clock rate of 10MHz See the Definition of Terms section for a definition of effective resolution BURR BROWN ADS1210 1211 DATA RATE Hz 3DB FREQUENCY HZ EFFECTIVE RESOLUTION BITS RMS G 1 G 2 G 4 G 8 G 16 TABLE III Effective Resolution vs Data Rate and Gain Setting Turbo Mode Rate of 1 and a 10MHz clock DEFINITION OF TERMS An attempt has been made to be consistent with the termi nology used in this data sheet In that regard the definition of each term is given as follows Analog Input Differential Voltage For an analog signal that is fully differential the voltage range can be compared to that of an instrumentation amplifier For example if both analog inputs of the ADS1210 are at 2 5V then the differ ential voltage is OV If one is at OV and the other at 5V then the differential voltage magnitude is 5V But this is the case regardless of which input is at OV and which is at 5V while the digital output result is quite different The analog input differ
42. esolution in Bits rms EFFECTIVE RESOLUTION vs DATA RATE 1MHz Clock 24 Turbo 16 22 20 Turbo 8 18 Turbo 1 7 16 Turbo 2 14 Turbo 4 12 1 10 100 1k Data Rate Hz EFFECTIVE RESOLUTION vs DATA RATE 5MHz Clock 24 Turbo 16 22 Turbo 8 20 Turbo 1 18 P Turbo 2 16 Turbo 4 14 12 10 100 1k Data Rate Hz EFFECTIVE RESOLUTION vs DATA RATE 10 100 1k Data Rate Hz Effective Resolution in Bits rms Effective Resolution in Bits rms RMS Noise ppm EFFECTIVE RESOLUTION vs DATA RATE 2 5MHz Clock 24 Turbo 16 22 7 20 Turbo 8 N 18 Turbo 1 Pd 16 Turbo 2 14 Turbo 4 12 1 10 100 1k Data Rate Hz EFFECTIVE RESOLUTION vs DATA RATE 10MHz Clock 24 Turbo 8 Turbo 16 22 20 Turbo 1 1 18 Turbo 2 16 14 Turbo 4 12 10 100 1k Data Rate Hz RMS NOISE vs INPUT VOLTAGE LEVEL 60Hz Data Rate 2 5 2 0 0 5 5 0 40 3 0 2 0 10 0 10 20 30 40 50 Analog Input Differential Voltage V BURR BROWN ADS1210 1211 TYPICAL PERFORMANCE
43. ffset voltage In the following discussion keep in mind that these voltages are differential voltages For example with the internal reference 2 5V and a gain of two the previous equations become after some manipulation Vps 3 25 lt Vos lt Vrs 1 75 If Vps is perfect at 2 5V positive full scale then Vos must be greater than 0 75V and less than 0 75V Thus when offset calibration is performed the positive input can be no more than 0 75V below or above the negative input If this range is exceeded the ADS1210 11 may not calibrate properly This calculation method works for all gains other than one For a gain of one and the internal reference 2 5V the equation becomes With a 5V positive full scale input Vos must be greater than 5V and less than 1 5V Since the offset represents a common mode voltage and the input voltage range in a gain of one is OV to 5V a common mode voltage will cause the actual input voltage to possibly go below OV or above 5V The specifications also show that for the specifications to be valid the input voltage must not go below AGND by more than 30mV or above AVpp by more than 30mV BURR BROWN ADS1210 1211 16 This will be an important consideration in many systems which use a 2 5V or greater reference as the input range is constrained by the expected power supply variations In addition the expected full scale voltage will impact the allowable offset voltage and v
44. function of the FCR value This function is linear and two known points can be used as a basis for interpolating intermediate values for the FCR Consult the Calibration section for more details The con tents of the FCR are in unsigned binary format This is not affected by the DF bit in the Command Register TIMING Table XV and Figures 13 through 21 define the basic digital timing characteristics of the ADS1210 11 Figure 13 and the associated timing symbols apply to the Xjy input signal Figures 14 through 20 and associated timing symbols apply to the serial interface signals SCLK SDIO SDOUT and CS and their relationship to DRDY The serial interface is discussed in detail in the Serial Interface section Figure 21 and the associated timing symbols apply to the maximum DRDY rise and fall times SCLK Internal SDIO as input SDOUT or SDIO as output FIGURE 14 Serial Input Output Timing Master Mode External SDIO as input SDOUT or SDIO as output FIGURE 15 Serial Input Output Timing Slave Mode men mmm o Xin Clock Frequency Xin Clock Period Xin Clock High Xin Clock LOW Internal Serial Clock HIGH Internal Serial Clock LOW Data In Valid to Internal SCLK Falling Edge Setup Internal SCLK Falling Edge to Data In Not Valid Hold Data Out Valid to Internal SCLK Falling Edge Setup Internal SCLK Falling Edge to Data Out Not Valid Hold External Serial Clock
45. ge of the ADS1210 11 in a gain setting of 1 This means that both units are absolute expressions of resolution the performance in different configurations can be directly com pared regardless of the units Comparing the resolution of different gain settings expressed in bits rms requires ac counting for the PGA setting Main Controller A generic term for the external microcontroller microprocessor or digital signal processor which is controlling the operation of the ADS1210 11 and receiving the output data fyj The frequency of the crystal oscillator or CMOS compatible input signal at the Xj input of the ADS1210 11 fmop Lhe frequency or speed at which the modulator of the ADS1210 11 is running given by the following equation _ fxm Turbo Mode 512 fwop fsAMp Ihe frequency or switching speed of the input sampling capacitor The value is given by the following equation _ fyyy Turbo Mode Gain Setting 512 fsamp fpATA tpara Lhe frequency of the digital output data produced by the ADS1210 11 or the inverse of this the period respectively fpara is also referred to as the data rate fqn Turbo Mode 1 t 512e Decimation Ratio 1 PATA f Arta fpara Conversion Cycle The term conversion cycle usually refers to a discrete A D conversion operation such as that performed by a successive approximation converter As used here a conversion cycle refers to the tpara time pe
46. gram shown in Figure 10 does not take into account the settling of external circuitry Sleep Mode pa Change to Normal Mode Occurs Here One 1 Other Data Normal Modes Not Conversion Start Here Valid Valid Data Valid Data NOTE 1 Assuming that the external circuitry has been stable for the previous three tpara periods FIGURE 10 Sleep Mode to Normal Mode Timing ANALOG OPERATION ANALOG INPUT The input impedance of the analog input changes with ADS1210 11 clock frequency fxm gain G and Turbo Mode Rate TMR The relationship is Ap Impedance Q 10MHz fq 4 3E6 G TMR Figure 11 shows the basic input structure of the ADS1210 The ADS1211 includes an input multiplexer but this has little impact on the analysis of the input structure The impedance is directly related to the sampling frequency of the input capacitor The Xj clock rate sets the basic sam pling rate in a gain of 1 and Turbo Mode Rate of 1 Higher gains and higher Turbo Mode Rates result in an increase of the sampling rate while slower clock Xj frequencies result in a decrease Rew 8kQ typical Qi High Impedance gt 1GQ a f Cint Switching Frequency 8pF Typical fsamp P Vom FIGURE 11 Analog Input Structure This input impedance can become a major point of consid eration in some designs If the source impedance of the input signal is significant or if there is passive filtering p
47. gular conversion result For those cases where this error must be reduced it is tempting to consider running the calibration at a slower data rate and then increasing the converter s data rate after the calibration is complete Unfortunately this will not work as expected The reason is that the results calculated at the slower data rate would not be valid for the higher data rate Instead the calibration should be done repeatedly After each calibration the results can be read and stored After the desired number of calibrations the main controller can compute an average and write this value into the calibration registers The resulting error in the calibration values will be reduced by the square root of the number of calibrations which were averaged The calibration registers can also be used to provide system offset and gain corrections separate from those computed by the ADS1210 11 For example these might be burned into E PROM during final product testing On power on the main controller would load these values into the calibration registers A further possibility is a look up table based on the current temperature Note that the values in the calibration registers will vary from configuration to configuration and from part to part There is no method of reliably computing what a particular calibration register should be to correct for a given amount of system error It is possible to present the ADS1210 11 with a known amount of
48. he analog input impedance The modulator rate relates to the power consumption of the ADS1210 11 and the output data rate See the Turbo Mode Analog Input and Reference Input sections for more details The gain is partially implemented by increasing the input capacitor sampling frequency which is given by the follow ing equation DR12 DRO0 Decimation Ratio Bits The DR12 DRO bits control the decimation ratio of the ADS1210 11 In essence fsamp G TMR fxm 512 these bits set the number of modulator results which are used in where G is the gain setting and TMR is the Turbo Mode the digital filter to compute each individual conversion result Rate The product of G and TMR cannot exceed 16 The Since the modulator rate depends on both the ADS1210 11 sampling frequency of the input capacitor directly relates to clock frequency and the Turbo Mode Rate the actual output the analog input impedance See the Programmable Gain data rate is given by the following equation Amplifier and Analog Input sections for more details fpATA fxm TMR 512 e Decimation Ratio 1 CHI CH0 Channel Selection Bits The CH1 and CHO bits where TMR is the Turbo Mode Rate Table XI shows control the input multiplexer on the ADS1211 as follows various data rates and corresponding decimation ratios with a 1OMHz clock Valid decimation ratios are from 19 to Hg AcmvENPUT 8000 Outside of this range the digital filter will compute Channe
49. he desired perfor mance a Turbo Mode Rate of 2X will result in the same effective resolution Table VI provides a comparison of effective resolution at various clock frequencies data rates and Turbo Mode Rates Xy CLOCK TURBO FREQUENCY MODE MHz RATE EFFECTIVE RESOLUTION Bits rms TABLE VI Effective Resolution vs Data Rate Clock Frequency and Turbo Mode Rate Gain set ting of 1 The Turbo Mode Rate TMR is programmed via the Sam pling Frequency bits of the Command Register Due to the increase in input capacitor sampling frequency higher Turbo Mode settings result in lower analog input impedance Ayn Impedance Q 10MHz fy y 4 3E6 GeTMR where G is the gain setting Because the modulator rate also changes in direct relation to the Turbo Mode setting higher values result in a lower impedance for the REFyy input REF Impedance Q 10MHz fyj 1EG TMR The Turbo Mode Rate can be set to 1 2 4 8 or 16 Consult the graphs shown in the Typical Performance Curves for full details on the performance of the ADS1210 11 operating in different Turbo Mode Rates Keep in mind that higher Turbo Mode Rates result in fewer available gain settings as shown in Table II PROGRAMMABLE GAIN AMPLIFIER The programmable gain amplifier gain setting is programmed via the PGA Gain bits of the Command Register Changes in the gain setting G of the programmable gain amplifier results in an increase in the input capa
50. herein is believed to be reliable however BURR BROWN assumes no responsibility for inaccuracies or omissions BURR BROWN assumes no responsibility for the use of this information and all use of such information shall be entirely at the user s own risk Prices and specifications are subject to change without notice No patent rights or licenses to any ofthe circuits described herein are implied or granted to any third party BURR BROWN does not authorize or warrant any BURR BROWN product for use in life support devices and or systems BURR BROWN ADS1210 1211 2 SPECIFICATIONS CONT All specifications Tmn to Tmax AVpp DVpp 5V fxn 10MHz programmable gain amplifier setting of 1 Turbo Mode Rate of 1 REFour disabled Vgias disabled and external 2 5V reference unless otherwise specified ADS1210U P ADS1211U P E PARAMETER CONDITIONS MIN TYP POWER SUPPLY REQUIREMENTS Power Supply Voltage Power Supply Current Analog Current Digital Current Additional Analog Current with REFou Enabled Veias Enabled Power Dissipation No Load TMR of 16 fyiy 2 5MHz fxn 2 5MHz TMR of 16 Sleep Mode TEMPERATURE RANGE Specified Storage NOTES 1 In order to achieve the converter s full scale range the input must be fully differential AjyN 2 REFiy AjyP If the input is single ended AN or AnP is fixed then the full scale range is one half that of the differential range 2 This range is set with extern
51. ice versa as the combination of the two must remain within the power supply and ground potentials regardless of the results obtained via the range calculation shown previously There are only two solutions to this constraint either the system design must ensure that the full scale and offset voltage variations will remain within the power supply and ground potentials or the part must be used in a gain of 2 or greater SLEEP MODE The Sleep Mode is entered after the bits 110 have been written to the Command Register Operation Mode bits MD2 through MDO This mode is exited by entering a new mode into the MD2 MD0 bits The Sleep Mode causes the analog section and a good deal of the digital section to power down For full analog power down the Vpras generator and the internal reference must also be powered down by setting the BIAS and REFO bits in the Command Register accordingly The power dissipa tion shown in the Specifications Table is with the internal reference and the Vpyas generator disabled To initiate serial communication with the converter while it is in Sleep Mode one of the following procedures must be used If CS is being used simply taking CS LOW will enable serial communication to proceed normally If CS is not being used tied LOW and the ADS1210 11 is in the Master Mode then a falling edge must be produced on the SDIO line If SDIO is LOW the SDIO line must be taken HIGH for 2 tyi periods minimum and then t
52. iming Characteristics eee 23 BURR BROWN ADS1210 1211
53. in the ground planes but connect the two with a moderate signal trace For multiple converters connect the two ground planes at one location as central to all of the converters as possible In some cases experimen tation may be required to find the best point to connect the two planes together The printed circuit board can be de signed to provide different analog digital ground connec tions via short jumpers The initial prototype can be used to establish which connection works best DECOUPLING Good decoupling practices should be used for the ADS1210 11 and for all components in the design All decoupling capacitors but specifically the 0 1uF ceramic capacitors should be placed as close as possible to the pin being decoupled A 1uF to 1OUF capacitor in parallel with a 0 1uF ceramic capacitor should be used to decouple AVpp to AGND At a minimum a 0 luF ceramic capacitor should be used to decouple DVpp to DGND as well as for the digital supply on each digital component SYSTEM CONSIDERATIONS The recommendations for power supplies and grounding will change depending on the requirements and specific design of the overall system Achieving 20 bits or more of effective resolution is a great deal more difficult than achiev ing 12 bits In general a system can be broken up into four different stages Analog Processing Analog Portion of the ADS1210 11 Digital Portion of the ADS1210 11 Digital Processing For the simplest system
54. l 1 Default results incorrectly due to inadequate or too much data Channel 2 Channel 3 Channel 4 Data Output Register DOR The DOR is a 24 bit register which contains the most recent conversion result see Table XII This register is updated with a new result just prior to DRDY going LOW If the contents of the DOR are not read within a period of time defined by 1 fbara 12 1 fxm then a new conversion result will overwrite the old DRDY is forced HIGH prior to the DOR update unless a read is in progress For the ADS1210 CH1 and CHO must always be zero The channel change takes effect when the last bit of byte 2 has been written to the Command Register Output data will not be valid for the next three conversions despite the DRDY signal indicating that data is ready On the fourth time that DRDY goes LOW after a channel change has been written to the Command Register valid data will be present in the Most Significant Bit Byte 2 Data Output Register see Figure 4 SF2 SF0 Turbo Mode Rate Bits The SF2 SFO bits Byte 1 control the input capacitor sampling frequency and modula tor rate as follows Byte 0 Least Significant Bit TABLE XII Data Output Register TURBO AVAILABLE MODE PGA RATE SETTINGS The contents of the DOR can be in Two s Complement or Offset Binary format This is controlled by the DF bit of the Command Register In addition the contents can be limited to unipolar data only with
55. lave Mode Then the input to the sampling capacitor is discon nected from the converters analog input and connected across REFqy A gain calibration is performed over the next three conversions After this the Operation Mode bits are reset to 000 normal mode and the input capacitor is then reconnected to the Valid Data Valid Data Calibration on System Offset DRDY Serial VO i i Ei DATA Pseudo System Calibration Mode I Hesse e Full Scale Calibration on Internal Full Scale input Conversions proceed as usual over the next three cycles in order to fill the digital filter DRDY remains HIGH during this time On the next cycle the DRDY signal goes LOW indicating valid data and resumption of normal operation The system offset calibration range of the ADS1210 11 is limited and is listed in the Specifications Table For more information on how to use these specifications see the System Calibration Limits section To calculate Vos use 2 e REF GAIN for Vgs Background Calibration The Background Calibration Mode is entered after the bits 101 have been written to the Command Register Operation Mode bits MD2 through MDO This initiates the following continuous sequence see Figure 9 At the start of the next conversion cycle the DRDY signal will not go LOW but will remain HIGH The inputs to the sampling capacitor are disconnected from the converter s analog input and shorted t
56. le Supply High Accuracy Thermocouple Dual Supply High Accuracy Thermocouple Single Supply High Accuracy Thermocouple Interface with Cold Junction Compensation eeseees 38 Dual Supply High Accuracy Thermocouple Interface with Cold Junction Compensation eeceees 39 Low Cost Bridge Transducer Interface with Current Excitation 39 41 TABLE Table Table Il Table Ill Table IV Table V Table V Table VII Table VIII Table IX Table X Table X Table XII Table XIII Table XIV Table XV TABLE INDEX TITLE PAGE Full Scale Range vs PGA Setting sess 9 Available PGA Settings vs Turbo Mode Rate 9 Effective Resolution vs Data Rate and Gain Setting 10 Effective Resolution cs Data Rate and Turbo Mode Rate 12 Noise Level vs Data Rate and Turbo Mode Rate 12 Effective Resolution vs Data Rate Clock Frequency and Turbo Mod FIBIB esiqeizcs isst eeii 12 ADS1210 11 Registers rie rte 18 duca er Er P 19 PAO AQ Addressing e entiende desiix imn dein eus Fu Mapas 19 Organization of the Command Register and Default Status 19 Decimation Ratios vs Data Rates 0 ee eee 21 Data Output Flegister rece tecti inn 21 Offset Calibration Register seee 22 Full Scale Calibration Register sssss 22 Digital T
57. ly Settled Output Data TURBO MODE The ADS1210 11 offers a unique Turbo Mode feature which can be used to increase the modulator sampling rate by 2 4 8 or 16 times normal With the increase of modulator sampling frequency there can be a substantial increase in BURR BROWN ADS1210 1211 the effective resolution of the output data at a given data rate but there is also an increase in power dissipation For Turbo Mode Rates 2 and 4 the increase is slight For rates 8 and 16 the increase is more substantial See the Typical Perfor mance Curves for more information In a Turbo Mode Rate of 16 the ADS1210 11 can offer 20 bits of effective resolution at a 1kHz data rate A comparison of effective resolution versus Turbo Mode Rates and output data rates is shown in Table IV while Table V shows the corresponding noise level in u Vrms Effective Resolution Bits rms TABLEIV Effective Resolution vs Data Rate and Turbo Mode Rate Gain setting of 1 and 1OMHz clock NOISE LEVEL uVrms DATA TURBO TURBO TURBO TURBO TURBO RATE MODE MODE MODE MODE MODE Hz RATE 1 RATE 2 RATE 4 RATE 8 RATE 16 TABLE V Noise Level vs Data Rate and Turbo Mode Rate Gain setting of 1 and 10MHz clock The Turbo Mode feature allows trade offs to be made between the ADS1210 11 Xy clock frequency power dissi pation and effective resolution If a 5MHz clock is available but a 1OMHz clock is needed to achieve t
58. n calibration is initiated and proceeds over the next three conversions After this the input capaci tor is once again connected to the analog input Conversions proceed as usual over the next three cycles in order to fill the digital filter DRDY remains HIGH during this time On the next cycle the DRDY signal goes LOW indicating valid data the input to the sampling capacitor is shorted and an offset calibration is initiated At this point the Background Calibration sequence repeats In essence the Background Calibration Mode performs continuous self calibration where the offset and gain cali brations are interleaved with regular conversions Thus the data rate is reduced by a factor of 6 The advantage is that the converter is continuously adjusting to environmental changes such as ambient or component temperature due to airflow variations The ADS1210 11 will remain in the Background Calibra tion Mode indefinitely To move to any other mode the Command Register Operation Mode bits MD2 through MDO must be set to the appropriate values System Calibration Offset and Full Scale Calibration Limits The System Offset and Full Scale Calibration range of the ADS1210 11 is limited and is listed in the Specifications Table The range is specified as Ves Vos D lt 1 3 2 REF y GAIN Vis Vos D gt 0 7 2 REFg GAIN where Vg is the system full scale voltage and Vos is the absolute value of the system o
59. nput to output transition External device generates n serial clock cycles and receives specified register data via SDIO SDIO transitions to tri state condition Is Next Instruction a Write See text for restrictions To Write Flowchart Using CS and Continuous Read Mode The serial interface may make use of the CS signal or this input may simply be tied LOW There are several issues associated with choosing to do one or the other The CS signal does not directly control the tri state condition of the SDOUT or SDIO output These signals are normally in the tri state condition They only become active when serial data is being transmitted from the ADS1210 11 If the ADS1210 11 is in the middle of a serial transfer and SDOUT or SDIO is an output taking CS HIGH will not tri state the output signal If there are multiple serial peripherals utilizing the same serial I O lines and communication may occur with any peripheral at any time then the CS signal must be used The ADS1210 11 may be in the Master Mode or the Slave Mode In the Master Mode the CS signal is used to hold off serial communication with a ready DRDY LOW ADS1210 11 until the main controller can accommodate the communica tion In the Slave Mode the CS signal is used to enable communication with the ADS1210 11 The CS input has another use If the CS state is left LOW after a read of the Data Output Register has been performed then the next time that
60. o 16 see Table II For example when using a Turbo Mode Rate of 8 156kHz at 1OMHz the maximum PGA gain setting is 2 ANALOG ANALOG INPUT INPUT UTILIZING Vgjs 2 EXAMPLE EXAMPLE VOLTAGE VOLTAGE GAIN RANGE RANGE SETTING V V 0 to 5 1 25 to 3 75 1 88 to 3 13 2 19 to 2 81 2 34 to 2 66 NOTE 1 With a 2 5V reference such as the internal reference 2 This example utilizes the circuit in Figure 12 Other input ranges are possible 3 The ADS1210 11 allows common mode voltage as long as the absolute input voltage on AP or ANN does not go below AGND or above AVpp TABLE II Available PGA Settings vs Turbo Mode Rate The output data rate of the ADS1210 11 can be varied from a few hertz to as much as 15 625kHz trading off lower resolution results for higher data rates In addition the data rate determines the first null of the digital filter and sets the 3dB point of the input bandwidth see the Digital Filter section Changing the data rate of the ADS1210 11 does not result in a change in the sampling rate of the input capacitor The data rate effectively sets the number of samples which are used by the digital filter to obtain each conversion result A lower data rate results in higher resolution lower input bandwidth and different notch frequencies than a higher data rate It does not result in any change in input impedance or modulator frequency or any appreciable change in power consumption The ADS1210 11
61. of bytes of the read or write operation as follows A3 A0 Address Bits These four bits select the begin ning register location which will be read from or written to as shown in Table IX Each subsequent byte will be read from or written to the next higher location If the BD bit in the Command Register is set each subsequent byte will be read from the next lower location This bit does not affect the write operation If the next location is not defined in Table IX then the results are unknown Reading or writing contin ues until the number of bytes specified by MB1 and MBO have been transferred Css ss uo essen eve 0 0 Data Output Register Byte 2 MSB Data Output Register Byte 1 Data Output Register Byte 0 LSB Command Register Byte 3 MSB Command Register Byte 2 Command Register Byte 1 Command Register Byte 0 LSB Offset Cal Register Byte 2 MSB Offset Cal Register Byte 1 Offset Cal Register Byte 0 LSB Full Scale Cal Register Byte 2 MSB Full Scale Cal Register Byte 1 Full Scale Cal Register Byte 0 LSB Note MSB Most Significant Byte LSB Least Significant Byte TABLE IX A3 A0 Addressing e 0000000 00 0 0 00 00 00 0020 0 0 1 1 1 1 0 0 0 1 1 1 e 19 Each serial communication starts with the 8 bits of the INSR being sent to the ADS1210 11 This directs the remainder of the communication cycle which consists of n bytes being read from
62. ogether An offset calibration is performed over the next three conversion periods in Slave Mode the very first offset calibration requires four periods and all subsequent offset calibrations require three periods Then the input capacitor is reconnected to the input Conversions proceed as usual over the next three cycles in order to fill the digital filter DRDY remains HIGH during this time On the next cycle the DRDY signal goes LOW indicating valid data Normal Analog Input Conversion Bc omo cene o mns NOTES 1 PSC Pseudo System Calibration instruction 2 In Slave Mode this function requires 4 cycles FIGURE 8 Pseudo System Calibration Timing Normal Background Calibration Mode Mode Offset i Analog i Calibration on l i li Input Internal Offset Conversion DRDY Serial 1 0 MM A _ 5 1 4 58 Full Scale Calibration on Internal Full Scale nra Cycle Repeats with Offset Calibration i i I Conversion li ji E 58 NOTES 1 BC Background Calibration instruction 2 In Slave Mode the very first offset calibration will require 4 cycles All subsequent offset calibrations will require 3 cycles FIGURE 9 Background Calibration Timing 15 BURR BROWN ADS1210 1211 Also during this cycle the sampling capacitor is discon nected from the converter s analog input and is connected across REFyy A gai
63. oller must read and write to the ADS1210 11 blindly Writes to the internal regis ters such as the Command Register or Offset Calibration Register might occur during an update of the Data Output Register This can result in invalid data in the DOR A two wire interface can be used if the main controller can read and or write to the converter either much slower or much faster that the data rate For example if much faster the main controller can use the DRDY bit to determine when data is becoming valid polling it multiple times during one conversion cycle Thus the controller obtains some idea of when to write to the internal register If much slower then reads of the DOR might always return valid data multiple conversions have occurred since the last read of the DOR or since any write of the internal registers gt 256 by lt 400 txin Reset Occurs at Falling Edge i gt 5 tay gt gt 512 b lt 900 txin gt 1024 tay lt 1200 tyin FIGURE 27 Resetting the ADS1210 11 Slave Mode only BURR BROWN ADS1210 1211 Three Wire Interface Figure 29 shows a different type of three wire interface with Figure 28 shows a three wire interface with a 8xC32 micro a 8xC51 microprocessor Here the Master Mode is used processor Note that the Slave Mode is being selected and The interface signals consist of SDOUT SDIO and SCLK the SDIO pin is being used for input and output
64. on Register OCR 22 Full Scale Calibration Register FCR sees 22 TIMING cioe etie rea o Betis has e ces 22 Synchronizing Multiple Converters s 26 SERIALINTERFA CE etri mti er ei n mr iieri dis t PE 26 Multiple INSU CHONG M 26 Using CS and Continuous Read Mode ssss 29 Power On Conditions for SDIO 12 scccccaese ciseieccecntessaecsscsesitscezcaennsecene 29 Master Mode MEET 29 Slave Mode Making Use of DSYNG vsin iiaii iiaii arina 30 Reset Power On Reset and Brown Out 90 Two Wire Interface 2 nr eerie Lien eno eed 30 Three Wire Interface eee eie ne lee 30 Four Wire Interface ettet rece retener 30 Multi Wire Interfaco cione c cete ce cei eee 32 leuc MC Lm 32 Isolation Synchronization of Multiple Converters ee 34 LAV OUD 35 POWER SUPPLIES dti nei initrd O ENE 35 GRBOUNDING ri itte A ieee eee 35 DECOUPLING i 35 SYSTEM CONSIDERATIONS nsii piierne deesse coeant Certa oca 35 APPLICATIONS ccsssssssssnsensnssssssssssnsceseenssasssenseassoesaessenassansanee 36 FIGURE Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22
65. on routine or they may be values which have been written directly via the serial interface 8 Bits 24 Bits 32 Bits 24 Bits 24 Bits Instruction Register Data Output Register Command Register Offset Calibration Register Full Scale Calibration Register TABLE VII ADS1210 11 Registers Communication with the ADS1210 11 is controlled via the Instruction Register INSR Under normal operation the INSR is written as the first part of each serial communication The instruction that is sent determines what type of communication will occur next It is not possible to read the INSR The Command Register CMR controls all of the ADS1210 11 s options and operating modes These include the PGA gain setting the Turbo Mode Rate the output data rate decimation ratio etc The CMR is the only 32 bit register within the ADS1210 11 It and all the remaining registers may be read from or written to Instruction Register INSR The INSR is an 8 bit register which commands the serial interface either to read or to write n bytes beginning at the specified register location Table VIII shows the format for the INSR MS B LSB ww wer veo o as a2 A j ao TABLE VIII Instruction Register R W Read Write Bit For a write operation to occur this bit of the INSR must be 0 For a read this bit must be 1 as follows MB1 MBO Multiple Bytes Bits These two bits are used to control the word length number
66. onversion cycle because it is assumed that the input voltage at the converter s input is not removed immediately after the offset calibration is performed In this case the digital filter already contains a valid result For full system calibration offset calibration must be per formed first and then full scale calibration In addition the offset calibration error will be the rms sum of the conversion error and the noise on the system offset voltage See the System Calibration Limits section for information regarding the limits on the magnitude of the system offset voltage System Full Scale Calibration A system full scale calibration is performed after the bits 011 have been written to the Command Register Operation Mode bits MD2 through MDO This initiates the following sequence see Figure 7 At the start of the next conversion cycle the DRDY signal will not go LOW but will remain HIGH and will continue to remain HIGH throughout the calibration sequence The full scale calibration will be per formed on the differential input voltage 2 REF G present at the converter s input over the next three conver sion periods four in Slave Mode When this is done the Operation Mode bits are reset to 000 Normal Mode A single conversion is done with DRDY HIGH After this conversion the DRDY signal goes LOW indicating resump tion of normal operation Normal Mode Normal System Full Scale Calibration Mode 1
67. or Appendix C of Burr Brown IC Data Book ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD Burr Brown recommends that all integrated circuits be handled with ap propriate precautions Failure to observe proper handling and installation procedures can cause damage Electrostatic discharge can cause damage ranging from performance degradation to complete device failure Burr Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods BURR BROWN 3 ADS1210 1211 ADS1210 SIMPLIFIED BLOCK DIAGRAM AGND AVpp REF gyt REF N O O O lt gt 2 5V 3 3V Bias Reference Generator Micro Controller Q ee Order Instruction Register NI Third Order Command Register en Digital Filter Data Output Register Offset Register ee a Full Scale Register Modulator Control ADS1210 PIN CONFIGURATION ADS1210 PIN DEFINITIONS TOP VIEW DIP SOIC DESCRIPTION Noninverting Input Inverting Input Analog Ground Bias Voltage Output 3 3V nominal Chip Select Input Control Input to Synchronize Serial Output Data System Clock Input System Clock Output for Crystal or Resonator Digital Ground Digital Supply 5V nominal Clock Input Output for serial data transfer Serial Data Input can also function as Serial Data Output Serial Data Output Data Ready SCLK Control Input Master 1 Slave 0 Analog Supply
68. or written to the ADS1210 11 The read write bit the number of bytes n and the starting register address are defined as shown in Table VIII When the n bytes have been transferred the INSR is complete A new communication cycle is initiated by sending a new INSR under restrictions outlined in the Interfacing section Command Register CMR The CMR controls all of the functionality of the ADS1210 11 The new configuration takes effect on the negative transition of SCLK for the last bit in each byte of data being written to the command register The organization of the CMR is shown in Table X Vost Significant Bit Byte 3 DSYNC DRDY NOTE 1 DSYNC is Write only DRDY is Read only BIAS REFO DF ua a MSB SDL Defaults Byte 2 MD2 MD1 MDO G2 G1 GO CH1 CHO 000 Normal Mode 000 Gain 1 00 Channel 1 Defaults Byte 1 SF2 SF1 SFO DR12 DR11 DR10 DR9 DR8 000 Turbo Mode Rate of 1 00000 Defaults Byte 0 Least Significant Bit DR7 DR6 DR5 DR4 DR3 DR2 DR1 DRO 00000 0001 0111 23 Data Rate of 814Hz Defaults TABLE X Organization of the Command Register and Default Status BIAS Bias Voltage Bit The BIAS bit controls the VgiAs output state either on 1 33 e REF or off disabled as follows SS Va GENERATOR Vans STATUS 0 Off Disabled Default 1 On 1 33 REF jy The Vprag circuitry consumes approximately 1mA of steady state current with no external load See the Vprag section for full details
69. pin on the ADS 1210 11 will be used as the serial data output pin either SDIO or SDOUT as follows SERIAL DATA OUTPUT PIN 0 SDIO 1 SDOUT Default If SDL is LOW then SDIO will be used for both input and output of serial data see the Timing section for more details on how the SDIO pin transitions between these two states In addition SDOUT will remain in a tri state condi tion at all times Important Note Since the default condition is SDL LOW SDIO has the potential of becoming an output once every data output cycle if the ADS1210 11 is in the Master Mode This will occur until the Command Register can be written and the SDL bit set HIGH See the Interfacing section for more information DRDY Data Ready Bit The DRDY bit is a read only bit which reflects the state of the ADS1210 11 s DRDY output pin as follows DRDY MEANING 0 Data Ready 1 Data Not Ready DSYNC Data Synchronization Bit The DSYNC bit is a write only bit which occupies the same location as DRDY When a one is written to this location the affect on the ADS1210 11 is the same as if the DSYNC input pin had been taken LOW and returned HIGH That is the modulator count for the current conversion cycle will be reset to zero sync mamme 0 No Change in Modulator Count 1 Modulator Count Reset to Zero The DSYNC bit is provided in order to reduce the number of interface signals that are needed between the ADS1210 11
70. r power is stable If this requirement cannot be met or if the circuit has brown out considerations the timing diagram of Figure 27 can be used to reset the ADS1210 11 This timing applies only when the ADS1210 11 is in the Slave Mode and accomplishes the reset by controlling the duty cycle of the SCLK input In general a reset is required after power up after a brown out has been detected or when a watchdog timer event has occured If the ADS1210 11 is in the Master Mode a reset of the device is not possible If the power supply does not meet the minimum ramp rate requirement or brown out is of concern low on resistance MOSFETs or equivalent should be used to control power to the ADS1210 11 When powered down the device should be left unpowered for at least 300ms before power is reapplied An alternate method would be to control the MODE pin and temporarily place the ADS1210 11 in the Slave Mode while a reset is initiated as shown in Figure 27 Two Wire Interface For a two wire interface the Master Mode of operation may be preferable In this mode serial communication occurs only when data is ready informing the main controller as to the status of the ADS1210 11 The disadvantages are that the ADS1210 11 must have a dedicated serial port on the main controller only one instruction can be issued per data ready period and the serial clock may define the maximum clock frequency of the converter In the Slave Mode the main contr
71. riod However each digital output is actually based on the modu lator results from the last three tpara time periods DIGITAL FILTER The digital filter of the ADS1210 11 computes the output result based on the most recent results from the delta sigma modulator The number of modulator results that are used depend on the decimation ratio set in the Command Regis ter At the most basic level the digital filter can be thought of as simply averaging the modulator results and presenting this average as the digital output While the decimation ratio determines the number of modu lator results to use the modulator runs faster at higher Turbo Modes These two items together with the ADS1210 11 clock frequency determine the output data rate fx Turbo Mode 512 Decimation Ratio 1 fpATA Also since the conversion result is essentially an average the data rate determines where the resulting notches are in the digital filter For example if the output data rate is 1kHz then a IkHz input frequency will average to zero during the 1ms conversion cycle Likewise a 2kHz input frequency will average to zero etc In this manner the data rate can be used to set specific notch frequencies in the digital filter response see Figure 1 for the normalized response of the digital filter For example if the rejection of power line frequencies is desired then the data rate can simply be set to the power line frequency Figures 2 and
72. rior to the ADS1210 11 then a significant portion of the signal can be lost across this external impedance How significant this effect is depends on the desired system performance There are two restrictions on the analog input signal to the ADS1210 11 Under no conditions should the current into or out of the analog inputs exceed 10mA In addition while the analog signal must reside within this range the linearity of the ADS1210 11 is only guaranteed when the actual analog input voltage resides within a range defined by AGND 30mV and AVpp 30mV This is due to leakage paths which occur within the part when AGND and AVpp are exceeded For this reason the OV to 5V input range gain of 1 with a 2 5V reference must be used with caution Should AV py be 4 75V the analog input signal would swing outside of the guaranteed specifications of the device Designs utilizing this mode of operation should consider limiting the span to a slightly smaller range Common mode voltages are also a significant concern in this mode and must be carefully analyzed An input voltage range of 0 75V to 4 25V is the smallest span that is allowed if a full system calibration will be performed see the Calibration section for more details This also assumes an offset error of zero A better choice would be 0 5V to 4 5V a full scale range of 9V This span would allow some offset error gain error power supply drift and common mode voltage while still p
73. roviding full system calibration over reasonable variation in each of these parameters The actual input voltage exceeding AGND or AVpp should not be a concern in higher gain settings as the input voltage range will reside well within OV to 5V This is true unless the common mode voltage is large enough to place positive full scale or negative full scale outside of the AGND to AVpp range REFERENCE INPUT The input impedance of the REF input changes with clock frequency fxm and Turbo Mode Rate TMR The relationship is REF Impedance Q 10MHZ fyiy 1EG TMR Unlike the analog input the reference input impedance has a negligible dependency on the PGA gain setting The reference input voltage can vary between 2V and 3V A nominal voltage of 2 5V appears at REFoyr and this can be directly connected to REFqy Higher reference voltages will cause the full scale range to increase while the internal circuit noise of the converter remains approximately the same This will increase the LSB weight but not the internal noise resulting in increased signal to noise ratio and effec tive resolution Likewise lower reference voltages will de crease the signal to noise ratio and effective resolution REFERENCE OUTPUT The ADS1210 11 contains an internal 2 5V reference Tolerances drift noise and other specifications for this reference are given in the Specification Table Note that it is not designed to sink or to source more than 1mA
74. rs In regards to the DSYNC input pin this case was discussed under Synchronizing Multiple Converters in the Timing section In regards to the DSYNC bit it will be difficult to set all of the converters DSYNC bits at the same time unless all of the converters are in the Slave Mode and the same instruction can be sent to all of the converters at the same time The second use of DSYNC is to reset the modulator count to zero in order to obtain valid data as quickly as possible For example if the input channel is changed on the ADS1211 the current conversion cycle will be a mix of the old channel and the new channels Thus four conversions are needed in order to ensure valid data However if the channel is changed and then DSYNC is used to reset the modulator count the modulator data at the end of the current conver sion cycle will be entirely from the new channel After two additional conversion cycles the output data will be com pletely valid Note that the conversion cycle in which DSYNC is used will be slightly longer than normal Its length will depend on when DSYNC was set Reset Power On Reset and Brown Out The ADS1210 11 contains an internal power on reset circuit If the power supply ramp rate is greater than 50mV ms this circuit will be adequate to ensure that the device powers up correctly Due to oscillator settling considerations commu nication to and from the ADS1210 11 should not occur for at least 25ms afte
75. rticularly when the Xy input frequency is greater than a few MHz as the serial clock may exceed the microcontroller s maximum serial clock frequency For the majority of digital signal processors this will be much less of a concern In addition if SDIO is being used as an input and an output then the transition time from input to output may be a concern This will be true for both microcontrollers and DSPs See Figure 20 in the Timing section Note that if CS is tied LOW there are special considerations regarding SDIO as outlined previously in this section Also note that if CS is being used to control the flow of data from the ADS1210 11 and it remains HIGH for one or more conversion periods the ADS1210 11 will operate properly However the result in the Data Output Register will be lost when it is overwritten by each new result Just prior to this update DRDY will be forced HIGH and will return LOW after the update Slave Mode Most systems will use the ADS1210 11 in the Slave Mode This mode allows multiple instructions to be issued per conversion period as well as allowing the main controller to set the serial clock frequency and pace the serial data transfer The ADS1210 11 is in the Slave Mode when the MODE input is LOW There are several important items regarding the serial clock for this mode of operation The maximum serial clock frequency cannot exceed the ADS1210 11 Xj frequency divided by 5 see Figure 15 in the Timing
76. ry wide range nearly four orders of magnitude However the 3dB point of the filter is 0 262 times the data rate And as can be seen in Figures 1 and 2 the rejection in the stopband frequencies higher than the first notch frequency may only be 40dB These factors must be considered in the overall system design For example with a 50Hz data rate a significant signal at 75Hz may alias back into the passband at 25Hz The analog front end can be designed to provide the needed attenuation to prevent aliasing or the system may simply provide this inherently Another possibility is increasing the data rate and then post filtering with a digital filter on the main controller Filter Settling The number of modulator results used to compute each conversion result is three times the Decimation Ratio This means that any step change or any channel change for the ADS1211 will require at least three conversions to fully settle However if the change occurs asynchronously then at least four conversions are required to ensure complete set tling For example on the ADS1211 the fourth conversion result after a channel change will be valid see Figure 4 Significant Analog Input Change or ADS1211 Channel Change Data Valid not Valid Valid Data Valid Val i Valid Data Data Serial yo DRDY t DATA FIGURE 4 Asynchronous ADS1210 11 Analog Input Volt age Step or ADS1211 Channel Change to Ful
77. s is further increased by provid ing a low noise programmable gain amplifier with a gain range of 1 to 16 in binary steps The ADS1210 and ADS1211 are designed for high resolution measurement applications in smart trans mitters industrial process control weigh scales chro matography and portable instrumentation Both con verters include a flexible synchronous serial interface which is SPI compatible and also offers a two wire control mode for low cost isolation The ADS1210 is a single channel converter and is offered in both 18 pin DIP and 18 lead SOIC pack ages The ADS1211 includes a 4 channel input multi plexer and is available in 24 pin DIP 24 lead SOIC and 28 lead SSOP packages Veias Micro Controller Third Order Digital Filter DSYNC C MODE DRDY International Airport Industrial Park Mailing Address PO Box 11400 Tucson AZ 85734 Street Address 6730 S Tucson Blvd Tucson AZ 85706 Tel 520 746 1111 Twx 910 952 1111 Internet http www burr brown com Cable BBRCORP Telex 066 6491 FAX 520 889 1510 Immediate Product Info 800 548 6132 1996 Burr Brown Corporation PDS 1284E Printed in U S A May 2000 SPECIFICATIONS All specifications Tmn to Tmax AVpp DVpp 5V fxn 10MHz programmable gain amplifier setting of 1 Turbo Mode Rate of 1 REFour disabled Vgiis disabled and external 2 5V reference unless otherwise specified ADS1210U P ADS1211U P E PARAMETER CON
78. section When using SDIO as the serial output the falling edge of the last serial clock cycle of the instruction byte will cause the SDIO pin to begin its transition from input to output Between three and four Xj cycles after this falling edge the SDIO pin will become an output This transition may be too fast for some microcontrollers and digital signal processors BURR BROWN ADS1210 1211 If a serial communication does not occur during any conver sion period the ADS1210 11 will continue to operate prop erly However the results in the Data Output Register will be lost when they are overwritten by the new result at the start of the next conversion period Just prior to this update DRDY will be forced HIGH and will return LOW after the update Making Use of DSYNC The DSYNC input pin and the DSYNC write bit in the Command Register reset the current modulator count to Zero This causes the current conversion cycle to proceed as normal but all modulator outputs from the last data output to the point where DSYNC is asserted are discarded Note that the previous two data outputs are still present in the ADS1210 11 internal memory Both will be used to com pute the next conversion result and the most recent one will be used to compute the result two conversions later DS YNC does not reset the internal data to zero There are two main uses of DSYNC In the first case DSYNC allows for synchronization of multiple converte
79. surement and 4 20mA receiver applications 1 2 OPA1013 AnP REF y AinN REF our AGND AVpp Vaas MODE CS aps1210 DRDY DSYNC SDOUT SDIO SCLK DVpp FIGURE 37 Bridge Transducer Interface with Voltage Excitation AnP REF y AnN REFouyr AGND AVpp Veias MODE CS apsi210 DRDY DSYNC SDOUT Xin SDIO Xa SCLK DGND DVpp FIGURE 38 Bridge Transducer Interface with Current Excitation BURR BROWN ADS1210 1211 36 REF200 100A ADS1210 DRDY DSYNC SDOUT Xn SDIO Xour SCLK DGND DVpp FIGURE 39 PT100 Interface AnP REF y AwN REF our AGND AVpp Vas MODE CS apsi210 DRDY DSYNC SDOUT Xn SDIO Xour SCLK DGND DVpp Termination ADS1210 DRDY DSYNC SDOUT SDIO Xour SCLK DGND DVpp FIGURE 41 Single Supply High Accuracy Thermocouple BURR BROWN 37 ADS1210 1211 AnP REF iy AN REF our AGND AVpp Veias MODE TS Apsi210 DRDY DSYNC SDOUT SDIO SCLK DVpp FIGURE 42 Dual Supply High Accuracy Thermocouple ADS1211U P 1N4148 Ro AGND 13kQ
80. te condition ADS1210 11 drives DRDY HIGH FIGURE 25 Flowchart for Writing and Reading Register Data Master Mode 27 SDIO input to output transition ADS1210 11 generates n serial clock cycles and transmits specified register data via SDIO SDIO transitions to tri state condition ADS1210 1211 BURR BROWN Start pod jus Writing Owenar ADS1210 11 drives DRDY LOW TS taken HIGH for 10 5 ty periods minimum see text if CS tied LOW External device generates 8 serial clock cycles and transmits instruction register data via SDIO External device generates n serial clock cycles and transmits specified register data via SDIO ADS1210 11 drives DRDY HIGH Is Next Instruction a Read More Instructions See text for restrictions To Read Flowchart Start Reading ADS1210 11 drives DRDY LOW Continuous Read Mode External device generates 8 serial clock cycles and transmits instruction register data via SDIO Use SDIO for output No SDOUT becomes active External device generates n serial clock cycles and transmits specified register data via SDOUT SDOUT returns to tri state condition ADS1210 11 drives DRDY HIGH More Instructions FIGURE 26 Flowchart for Writing and Reading Register Data Slave Mode BURR BROWN ADS1210 1211 28 To Write Flowchart CS taken HIGH for 10 5 ty periods minimum see text if CS tied LOW SDIO i
81. the U B bit of the Command Register Default BURR BROWN 21 ADS1210 1211 Offset Calibration Register OCR The OCR is a 24 bit register which contains the offset correction factor that is applied to the conversion result before it is placed in the Data Output Register see Table XIII In most applications the contents of this register will be the result of either a self calibration or a system calibration The OCR is both readable and writeable via the serial interface For applications requiring a more accurate offset calibration multiple calibrations can be performed each resulting OCR value read the results averaged and a more precise offset calibration value written back to the OCR The actual OCR value will change from part to part and with configuration temperature and power supply Thus the actual OCR value for any arbitrary situation cannot be accurately predicted That is a given system offset could not be corrected simply by measuring the error externally com puting a correction factor and writing that value to the OCR In addition be aware that the contents of the OCR are not used to directly correct the conversion result Rather the correction is a function of the OCR value This function is linear and two known points can be used as a basis for interpolating intermediate values for the OCR Consult the Calibration section for more details Vost Significant Bit Byte 2 Byte 1 Byte 0 Least Signifi
82. tions for VgjAs but at 12mW the power dissipation is significant If this is a concern resistors R and R can be set to 9kQ and R and Ry to 3kO This will reduce power dissipation by one third In addition these resistors can also be set to values which will provide any arbitrary input range In all cases the maximum current into or out of Vpyas should not exceed its specification of 10mA Note that the connection diagram shown in Figure 12 causes a constant amount of current to be sourced by Vgjs This will be very important in higher resolution designs as the voltage at VgjAs Will not change with loading as the load is constant However if the input signal is single ended and one side of the input is grounded the load will not be constant and Vgjas Will change slightly with the input signal Also in all cases note that noise on Vpgj4s introduces a common mode error signal which is rejected by the converter The 3k resistors should not be used as part of an anti alias filter with a capacitor across the inputs The ADS1210 samples charge from the capacitor which has the effect of introducing an offset in the measurement This might be acceptable for relative differential measurements The circuitry to generate Vgj4s is disabled when the ADS1210 11 is in its default state and it must be enabled via the Command Register in order for the VgiAs voltage to BURR BROWN ADS1210 1211 18 be present When enabled
83. uring the DRDY LOW period see Figures 4 through 10 and Figure 36 This communication represents one instruction that is executed by the ADS1210 11 resulting in a single read or write of register data However more than one instruction can be executed by the ADS1210 11 during any given conversion period see Fig ure 24 Note that DRDY remains HIGH during the subse quent instructions There are several important restrictions on how and when multiple instructions can be issued during any one conversion period Internal Update of DOR FIGURE 24 Timing of Data Output Register Update The first restriction is that the converter must be in the Slave Mode There is no provision for multiple instructions when the ADS1210 11 is operating in the Master Mode The second is that some instructions will produce invalid results if started at the end of one conversion period and carried into the start of the next conversion period DSYNC O D Q Strobe CLK QG 1 6 74AHC04 ADS1210 11 ADS1210 11 ADS1210 11 FIGURE 23 Exactly Synchronizing Multiple ADS1210 11s to an Asynchronous DSYNC Signal BURR BROWN ADS1210 1211 For example Figure 24 shows that just prior to the DRDY signal going LOW the internal Data Output Register DOR is updated This update involves the Offset Calibration Register OCR and the Full Scale Register FSR If the OCR or FSR are being written their final
84. value may not be correct and the result placed into the DOR will certainly not be valid Problems can also arise if certain bits of the Command Register are being changed Note that reading the Data Output Register is an excep tion If the DOR is being read when the internal update is Start Writing ADS1210 11 drives DRDY LOW ADS1210 11 generates 8 serial clock cycles and receives Instruction Register data via SDIO ADS1210 11 generates n serial clock cycles and receives specified register data via SDIO ADS1210 11 drives DRDY HIGH initiated the update is blocked The old output data will remain in the DOR and the new data will be lost The old data will remain valid until the read operation has com pleted In general multiple instructions may be issued but the last one in any conversion period should be complete within 12 Xy clock periods of the next DRDY LOW time In this usage complete refers to the point where DRDY rises in Figures 17 and 19 in the Timing Section Consult Figures 25 and 26 for the flow of serial data during any one conversion period Start Reading ADS1210 11 drives DRDY LOW Continuous Read Mode ADS1210 11 generates 8 serial clock cycles and receives Instruction Register data via SDIO Use SDIO for output No SDOUT becomes active from tri state ADS1210 11 generates n serial clock cycles and transmits specified register data via SDOUT SDOUT returns to tri sta

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