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TEXAS INSTRUMENTS ADS1201 handbook

1. 0 1 1 10 100 1000 Frequency Hz TYPICAL SINK CURRENT 0 05 10 15 20 25 30 35 40 45 5 0 Vor V BURR BROWN ADS1201 ppm o PSRR dB lour mA LINEARITY PSRR vs FREQUENCY 70 68 66 64 62 60 0 1 1 0 10 100 1k 10k 100k Frequency Hz TYPICAL SOURCE CURRENT 0 0 05 10 15 20 25 30 35 40 45 5 0 Vor V TYPICAL PERFORMANCE CURVES Cont At Ta 25 C AVpp DVpp 5V MCLK 320kHz REFen LOW BIASey LOW and external 2 5V reference unless otherwise specified CMRR vs Vp 110 105 100 95 CMRR dB 90 85 80 0 05 10 1 5 GENERAL DESCRIPTION The ADS1201 is a single channel second order CMOS analog modulator designed for high resolution conversions from dc to 1000Hz The output of the converter MOUT provides a stream of digital ones and zeros The time average of this serial output is proportional to the analog input voltage The combination of an ADS1201 and a processor that is programmed to implement a digital filter results in a high resolution A D converter system This system allows flexibility with the digital filter design and is capab
2. 2nd Order Modulator gt gt bp 1 Bit DAC out of the analog inputs exceed 10mA In addition the linearity of the device is guaranteed only when the analog voltage applied to either input resides within the range defined by AGND gt 30mV and lt AVpp 30mV If either of the inputs exceed these limits the input protection diodes on the front end of the converter will begin to turn on This will induce leakage paths resulting in nonlinearities in the conversion process For this reason the OV to 5V input range must be used with caution Should AVpp be 4 75V the analog input signal would swing outside the guaranteed specifications of the device Designs utilizing this mode of operation should consider limiting the span to a slightly smaller range Com mon mode voltages are also a significant concern and must be carefully analyzed Modulator The modulator sampling frequency MCLK can be oper ated over a range of 20kHz to 1MHz The frequency of MCLK can be increased to improve the performance of the converter or adjusted to comply with the clock requirements of the application The modulator topology is fundamentally a 2nd order charge balancing A D converter as the one conceptualized in Fig ure 4 The analog input voltage and the output of the 1 bit DAC is differentiated providing an analog voltage at X and X3 The voltage at X and X are presented to their indi vidual integrators The out
3. the MCLK frequency MCLK duty cycle power FS Analog Input FS Analog Input FIGURE 8 Analog Input versus Modulator Output of the ADS1201 GAIN OFFSET seo bescmeron mw rw wax unns CAL and GAIN OFFSET Rise Time 10 CAL and GAIN OFFSET Fall Time 10 GAIN OFFSET to CAL Setup Time 0 GAIN OFFSET to CAL Hold Time 25 Tuou NOTE 1 Tuck is the clock period of MCLK FIGURE 9 Timing Diagram for the Calibration Feature of the ADS1201 BURR BROWN ADS1201 Normal Mode Offset Calibration Analog inputs shorted to ground internally Full Scale Calibration Analog inputs are referenced to Vref internally 0 1 0 0 1 0 TABLE III Calibration Enable supply Vegp or temperature The amount of change which could cause a re calibration is dependent on the application and effective resolution of the system The results of the calibration calculations are stored in two registers in the processor chip see Figure 1 These two calibration results can then be used to calibrate the input signal results with one of the following formulas Equivalent Calibrated Output Code FSC FO FOz FO3 FO where FO Filter output code of an applied input voltage FO Filter output code of the offset calibration FO Filter output code of the gain calibration FSC Desired full scale output With a simple sinc filter the calibrated A D conversion would equal Equivalent Calibrated Input Vo
4. 0 0 ADSDOI O O BURR BROWNO LES ADS1201 High Dynamic Range DELTA SIGMA MODULATOR FEATURES DESCRIPTION O 130dB DYNAMIC RANGE The ADS1201 is a precision 130dB dynamic range O FULLY DIFFERENTIAL INPUT delta sigma AX modulator operating from a single O TWO WIRE INTERFACE 5V supply The differential inputs are ideal for direct O INTERNAL EXTERNAL REFERENCE connection to transducers or low level signals With the appropriate digital filter and modulator rate the O ON CHIP SWITCHES FOR CALIBRATION device can be used to achieve 24 bit analog to digital A D conversion with no missing codes Effective resolution of 20 bits can be maintained with a digital A P P Ll CATI O N S filter bandwidth of 1kHz at a modulator rate of 320kHz O INDUSTRIAL PROCESS CONTROL The ADS1201 is designed for use in high resolution O INSTRUMENTATION measurement applications including smart transmit O SMART TRANSMITTERS ters industrial process control weigh scales chroma O PORTABLE INSTRUMENTS tography and portable instrumentation It is available in a 16 lead SOIC package O WEIGH SCALES O PRESSURE TRANSDUCERS AVpp AGND REF i REF our Ea 2 5V Bias O BIASEn Reference Generator Second Order AL Modulator CAL GAIN OFFSET DVpp DGND International Airport Industrial Park Mailing Address PO Box 11400 Tucson AZ 85734 Street Address 6730 S Tucson Blvd Tucson AZ 85706 Tel 520 746 1111 Twx 910 952 1111 Internet
5. GH DVpp enabled LOW disabled GAIN OFFSET Digital Input Gain Offset Calibration Select Input with CAL LOW HIGH gain configuration CAL LOW offset configuration Digital Input Calibration Control Input HIGH GAIN OFFSET normal operation LOW gain or offset calibration configuration Digital Input Digital Ground Digital Input Digital Supply 5V nominal Digital Input Modulator Clock Input CMOS compatible Digital Output Modulator Output Digital Input REFoyy Voltage Enable Input HIGH enabled LOW disabled ADS1201 DGND BIASEN PACKAGE ORDERING INFORMATION PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER MEDIA ARSIana SoL 16 21 40 C ba 85 AA ADS1201U Rails ADS1201U 1K Tape and Reel NOTE 1 Models with a slash are available only in Tape and Reel in the quantities indicated e g 1K indicates 1000 devices per reel Ordering 1000 pieces of H U 1K will get a wee 1000 piece Tape and Reel BURR BROWN 3 ADS1201 TYPICAL PERFORMANCE CURVES At Ta 25 C AVpp DVpp 5V MCLK 320kHz REFey LOW BIASey LOW and external 2 5V reference unless otherwise specified 110 105 CMRR dB 100 95 lour MA 0 rms NOISE CMRR vs FREQUENCY
6. S1201 to accept a 10V input signal 20V full scale range If BIASpy is HIGH the voltage at Vpyas will be 3 3V assumes a 2 5V nominal Vrgp Serial Data Out Clock In GAIN OFFSET BIASEn Clock Period Clock HIGH Clock LOW Clock Rise Time Clock Fall Time DOUT Valid after Clock Rising Edge FIGURE 7 Timing Diagram for the Digital Interface of the ADS1201 BURR BROWNO ADS1201 OoOo Pasw E Vs LOW High Impedance HIGH 1 33V Vrer TABLE II Bias Enable When enabled the Vpyag circuitry consumes approximately ImA with no external load The maximum current into or out of Vas should not exceed 10mA On power up external signals may be present before Vpyas is enabled This can create a situation in which a negative voltage is applied to the analog inputs reverse biasing the negative input protection diode of the ADS1201 This situ ation should not be a problem as long as the resistors R and R limit the current being sourced by each analog input to be under 10mA A potential of OV at the analog input pin AP or A yN should be used in the calculation DIGITAL OUTPUT The timing diagram for the ADS1201 data retrieval is shown in Figure 7 MCLK initiates the modulator process for the ADS1201 and is used as a system clock by the ADS1201 as well as a framing clock for data out The modulator output data which is a serial stream is available on the MOUT pin Typically MOUT is read o
7. ection has been made between the ADS1201 supply pins via a 100 resistor The combination of this resistor and the decoupling capacitors provides some filtering between DV pp and AVpp BURR BROWNO ADS 1201 The analog supply should be well regulated and low noise For designs requiring very high resolution from the ADS 1201 power supply rejection will be a concern The requirements for the digital supply are not strict However high frequency noise on DVpp can capacitively couple into the analog portion of the ADS1201 This noise can originate from switching power supplies microprocessors or digital signal processors For either supply high frequency noise will generally be rejected by the external digital filter at integer multiples of MCLK Just below and above these frequencies noise will alias back into the pass band of the digital filter affecting the conversion result Inputs to the ADS1201 such as Am REF and MCLK should not be present before the analog and digital supplies are on Violating this condition could cause latch up If these signals are present before the supplies are on series resistors should be used to limit the input current If one supply must be used to power the ADS1201 the system s analog supply should be used to power both AVpp and DVpp Experimentation may be the best way to deter mine the appropriate connection between AVpp and DVpp GROUNDING The analog and digital sections of the de
8. hown in Figure 5a The capacitor in this circuit is absolutely required if low noise performance is desired An external reference can be used to reduce the noise in the conversion process If an external reference is used care should be taken to insure that the selected reference has low noise performance The appropriate connection circuit of an external reference is shown in Figure 5b The reference must be configured with appropriate capacitors to reduce the high frequency noise that may be contributed by the reference The input impedance of REFy changes with the modulator clock frequency The relationship is 1E12 Typical REF Input Impedance _ _ 50 fick X X3 X4 OH Integrator 1 Integrator 2 VREF Comparator FIGURE 4 Block Diagram of a Second Order Modulator REFen MOUT MCLK External VREF DVpp ADS1201 ANP DGND CAL a Internal Reference Xe D A Converter DVpo ADS1201 ANP DGND AN CAL AGND GAIN OFFSET Veias BIASEn b External Reference FIGURE 5 Two Voltage Reference Connection Alternatives for the ADS1201 BURR BROWNO ADS1201 The reference input voltage can vary between 2V and 3V Higher reference voltages will cause the full scale range to increase while the internal circuit noise of the converter remains approximately the same This will increase the LSB weight but not the internal noise resulting in increased signal to no
9. http www burr brown com Cable BBRCORP Telex 066 6491 FAX 520 889 1510 Immediate Product Info 800 548 6132 1997 Burr Brown Corporation PDS 1417C Printed in U S A October 1999 SPECIFICATIONS At Ta 25 C AVpp DVpp 5V MCLK 320kHz REFen LOW BIASen LOW and external 2 5V reference unless otherwise specified PARAMETER ANALOG INPUT Absolute Input Voltage Range Differential Input Voltage Range Input Impedance Input Capacitance Input Leakage Current ADS1201U CONDITIONS MIN With Veias With Veias At Tmn to Tmax TYP See Note 2 250 4 SYSTEM PERFORMANCE Dynamic Range Integral Linearity Error Offset Error 2 Offset Drift 3 Gain Error 2 Gain Error Drift 3 Common Mode Rejection Power Supply Rejection 10Hz Bandwidth 5 60Hz Bandwidth 5 1kHz Bandwidth 5 60Hz Bandwidth 5 1kHz Bandwidth 5 See Note 7 1 See Note 7 1 100 80 0 0015 0 0015 REFERENCE Internal Reference REFour Drift Noise Load Current Output Impedance External Reference REF y Load Current Veias Output Drift Load Current Source or Sink Using Internal Reference 2 5 25 50 2 DIGITAL INPUT OUTPUT Logic Family Logic Levels Vin MCLK Vi MCLK Von MOUT Vo MOUT MCLK Frequency liq 5uA l 5pA lo 2 TTL Loads lo 2 TTL Loads TTL Compatible CMOS DVpp 0 3 0 8 0 4 1 POWER SUPPLY REQUIREMENTS Power Supply Voltage Supp
10. ise ratio Likewise lower reference voltages will decrease the signal to noise ratio The internal reference which generates 2 5V can be dis abled when an external reference is used This internal reference is disabled with the REF y pin When the refer ence is disabled the supply current AVpp of the converter will reduce by approximately 1 6mA REFERENCE OUTPUT VREFoyr The ADS1201 contains an internal 2 5V reference When using this feature REF y must be HIGH see Figure 5 Tolerances drift noise and other specifications for this PO CS E Ro O High Impedance 2 5V nominal TABLE I Reference Enable Veias Data Valid Data Valid Data Valid J Data Valid AGND reference are given in the Specifications table Note that this reference is not designed to sink or to source more than 1mA of current In addition loading the reference with a dynamic or variable load is not recommended This can result in small changes in reference voltage as the load changes VOLTAGE BIAS OUTPUT Veas The Vas Output voltage is dependent on the reference input REF voltage and is approximately 1 33 times as great The output of Vpyas is used to bias input signals of greater than 5V If a resistor network is used in combination with the Vpyas output the signal range can be scaled and level shifted to match the input range of the ADS1201 Figure 6 shows a connection diagram which will allow the AD
11. le of A D conversion results that have a dynamic range that exceeds 130dB see Figure 1 Analog Supply AnP AinN 6 vens ADS1201 AGND GAIN OFFSET BIASEN 25 30 35 40 45 Von V THEORY OF OPERATION The differential analog input of the ADS1201 is imple mented with a switched capacitor circuit This switched capacitor circuit implements a 2nd order modulator stage which digitizes the input signal into a binary output stream The input stage of the converter can be configured to sample an analog signal or to perform a calibration which quantifies offset and gain errors The sample clock MCLK provides the switched capacitor network and modulator clock signal for the A D conversion process as well as the output data framing clock Different frequencies for this clock allows for a variety of performance solutions in resolution and signal bandwidth The analog input signal is continuously sampled by the A D converter and compared to an internal or external voltage reference A digital stream appears at the output of the converter This digital stream accurately repre sents the analog input voltage over time REFEN MOUT MCLK Digital DVpp Supply 0 1uF Processor DGND CAL FIGURE 1 Connection Diagram for the ADS1201 Delta Sigma Modulator Including External Processor BURR BROWNO ADS 1201 1 Bit Data Stream 2nd Order Charge Bala
12. ll as for the digital supply on each digital component DVpp ADS1201 AnP DGND AN CAL FIGURE 10 Power Supply Connection Using One Power Plane and One Digital Plane Isolated Power Opto Coupler DVpp ADS1201 AnP DGND REF200 ANN CAL AGND GAIN OFFSET Opto Coupler Veias B IASgn FIGURE 11 Bridge Transducer Interface with Current Excitation BURR BROWNO 11 ADS1201 Isolated Power Opto Coupler DVpp ADS1201 AnP DGND AN CAL AGND GAIN OFFSET Opto Coupler Veias BIASen FIGURE 12 PT100 Interface with Current Excitation REFEN MOUT MCLK DVop ADS1201 AnP DGND AN CAL AGND GAIN OFFSET Veias BIASEn FIGURE 13 Geophone Interface BURR BROWNO ADS1201 12 Isolated Power Opto Coupler DVop ADS1201 AnP DGND AN CAL AGND GAIN OFFSET Opto Coupler BIASen Veias Floating Positive Supply 6 Opto Coupler DVop ADS1201 AnP DGND AnN CAL AGND GAIN OFFSET Opto Coupler Veias BIASen FIGURE 15 Moto
13. ltage N4 No Vrer N3 No where N number of ones counted or digital equivalent after filtering over given time ty with an applied input voltage No number of ones counted or digital equivalent after filtering during offset calibration where t42 ty N3 number of ones counted or digital equivalent after filtering during gain calibration where t 3 ty A system calibration can be performed by applying two known voltage levels to the input of the converter In this situation the GAIN OFFSET and CAL gy pins are not used Rather the digital output of these two known voltages are accumulated by the processor With this data the processor can determine the calibration register values that are appro priate for the application LAYOUT CONSIDERATIONS POWER SUPPLIES The ADS1201 requires the digital supply DVpp to be no greater than the analog supply AVpp Failure to observe this condition could cause permanent damage to the ADS1201 The best scheme is to power the analog section of the design and AVpp from one 5V line and the digital section and DV pp from a separate 5V line from the same supply If there are separate analog and digital power supplies for the ADS1201 a good design approach would be to have the analog supply come up first followed by the digital supply Another approach that can be used to control the analog and digital power supply differences is shown in Figure 10 In this circuit a conn
14. ly Current Analog Current Digital Current Additional Analog Current REFour Enabled Veias Enabled Total Power Dissipation Specified Performance No Load No Load REFour Veias Disabled TEMPERATURE RANGE Specified Performance NOTES 1 This range is set with external resistors and Vg as as described in the text Other ranges are possible 2 After the on chip offset and gain calibration functions have been employed 3 Re calibration can reduce these errors 4 Input impedance changes with MCLK 5 Assume brick wall digital filter is used 6 20 Log full scale rms noise 7 After calibration these errors will be of the order of the effective resolution The information provided herein is believed to be reliable however BURR BROWN assumes no responsibility for inaccuracies or omissions BURR BROWN assumes no responsibility for the use of this information and all use of such information shall be entirely at the user s own risk Prices and specifications are subject to change without notice No patent rights or licenses to any of the circuits described herein are implied or granted to any third party BURR BROWN does not authorize or warrant any BURR BROWN product for use in life support devices and or systems BURR BROWNO ADS 1201 ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC Analog Input Current pew ne DISC HARG E SENSITIVITY Voltage AGND 0 3V to AVpp 0 3V AVpp to DVop _0 3V to 6V Thi
15. n the falling edge of MCLK Under any situation with MCLK the duty cycle must be kept constant for reliable repeatable results Modulator Output Analog Input An input differential signal of OV will ideally produce a stream of ones and zeros that are HIGH 50 of the time and LOW 50 of the time A differential input of 5V will produce a stream of ones and zeros that are HIGH 90 of the time A differential input of 5V will produce a stream of ones and zeros that are HIGH 10 of the time The input voltage versus the output modulator signal is shown in Figure 8 OFFSET and GAIN CALIBRATION The ADS1201 offers a self calibration function that is imple mented with the GAIN OFFSET and CALfy pins Both conditions provide an output stream of data similar to normal operation where the converter is configured to sample an input signal at Ayy The offset and gain errors of the ADS1201 are calibrated independently For best operation the offset should be calibrated first followed by the gain The calibration imple mentation timing diagram is shown in Figure 9 The calibra tion mode pins control the calibration functions of the ADS1201 Calibration should be performed once and then normal operation can be resumed Calibration of offset and gain is recommended immediately after power on and whenever there is a significant change in the operating environment Significant changes in the operating environment include a change of
16. ncing A D Converter Processor for Filtering FIGURE 2 Block Diagram of the ADS 1201 ANALOG INPUT STAGE Analog Input The input design topology of the ADS1201 is based on a fully differential switched capacitor architecture This input stage provides the mechanism to achieve low system noise high common mode rejection 100dB and excellent power supply rejection The input impedance of the analog input is dependent on the input capacitor and modulator clock fre quency MCLK which is also the sampling frequency of the converter Figure 3 shows the basic input structure of the ADS1201 The relationship between the input impedance of the ADS1201 and the modulator clock frequency is A y Input Impedance Q no 12 fuer The input impedance becomes a consideration in designs where the source impedance of the input signal is signifi cant In this case it is possible for a portion of the signal to be lost across this external source impedance The impor tance of this effect depends on the desired system perfor mance There are two restrictions on the analog input signal to the ADS 1201 Under no conditions should the current into or High e Impedance gt 1GQ Cir 12pF t Ate typ Switching Frequency MCLK High Impedance gt 1GQ FIGURE 3 Input Impedance of the ADS1201 BURR BROWN ADS1201
17. put of these integrators progress in a negative or positive direction When the value of the signal at X4 equals the comparator reference voltage the output of the comparator switches from negative to positive or positive to negative depending on its original state When the output value of the comparator switches from a HIGH to LOW or vise versa the 1 bit DAC responds on the next clock pulse by changing its analog output voltage at X causing the integrators to progress in the opposite direction The feedback of the modulator to the front end of the integrators force the value of the integrator output to track the average of the input REFERENCE CIRCUIT There are two reference circuits included in the ADS1201 converter Vpgr REFN REFoyr and Vpyas The circuitry for Vppr is configured to allow the user to utilize the internal reference on the chip or provide an external reference to the converter see Figure 5 The second reference Vas iS derived from Vegp whether it is internal or external Vpyas 1s exclusively an output reference This ratiometric relation ship between Vppr and Vpyas reduces system errors when two separate bias voltages are required in the application REFERENCE INPUT REF y The reference input REFy of the ADS1201 can be config ured so that the 2 5V nominal internal or external reference can be used in the conversion process If the internal refer ence is used the correct connection configuration is s
18. r Controller Sensing Circuit BURR BROWNO a ADS1201
19. s integrated circuit can be damaged by ESD Burr Brown AVpp to AGND 0 3V to 6V recommends that all integrated circuits be handled with a EO Eme E appropriate precautions Failure to observe proper handling euE Ea I 00 A A E A REF Voltage to AGND 0 3V to AVpp 0 3V and installation procedures can cause damage Digital Input Vottage to DONE s la ov ESD damage can range from subtle performance degradation Digital Output Voltage to DGND 0 3V to DVpp 0 3V 8 A 8 aa Pp 8 5 Lead Temperature soldering 10s to complete device failure Precision integrated circuits may Internal Power Dissipation be more susceptible to damage because very small parametric NOTE 1 Stresses above those listed under Absolute Maximum Ratings may changes could cause the device not to meet its published cause permanent damage to the device Exposure to absolute maximum specifications conditions for extended periods may affect device reliability PIN CONFIGURATION PIN DESCRIPTIONS op View AVop Analog Input Analog Supply 5V nominal REFour Analog Output Internal Reference Voltage Output 2 5V nominal REF in Analog Input Reference Voltage Input NIC Not Internally Connected AnP Analog Input Noninverting Input REFen AN Analog Input Inverting Input MOUT AGND Analog Input Analog Ground Veias Analog Output Bias Voltage Output nominally MCLK 3 3V with 2 5V reference BIASEN Digital Input Bias Voltage Enable Input HI
20. sign should be carefully and cleanly partitioned Each section should have its own ground plane with no overlap between them AGND should be connected to the analog ground plane as well as all other analog grounds DGND should be connected to the digital ground plane and all digital signals referenced to this plane The ADS1201 pinout is such that the converter is cleanly separated into an analog and digital portion This should allow simple layout of the analog and digital sections of the design For a signal converter system AGND and DGND of the ADS1201 can be connected together Do not join the ground planes but connect the two with a moderate signal trace underneath the converter For multiple converters connect the two ground planes at one location as central to all of the converters as possible In some cases experimentation may be required to find the best point to connect the two planes together Experimentation may be the best way to determine the appropriate connection between AGND and DGND DECOUPLING Good decoupling practices should be used for the ADS1201 and for all components in the design All decoupling capaci tors specifically the 0 1uF ceramic capacitors should be placed as close as possible to the pin being decoupled A 1uF and 10uF capacitor in parallel with the 0 1uF ceramic capacitor should be used to decouple AVpp to AGND At a minimum a 0 1uF ceramic capacitor should be used to decouple DVpp to DGND as we

TEXAS INSTRUMENTS ADS1201 handbook

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