ANALOG DEVICES OP184/OP284/OP484 handbook
Contents
1. 25 C S c Z z Z 20 T 10 2 a 1 3 z 8 0 i tt z o Oo 10 2 ul ul a o 7 o G g 20 gt M s a 30 2 0 3 40 0 22 5 5 0 37 5 10 12 5 15 17 5 20 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M SUPPLY VOLTAGE Volts FREQUENCY Hz FREQUENCY Hz Figure 11 Supply Current vs Supply Figure 14 Open Loop Gain and Phase Figure 17 Closed Loop Gain vs Voltage vs Frequency No Load Frequency 2 kQ Load 50 80 Vg 15V 60 Ta E 40 i T 25 C re 50 NO LOAD 5 lsc i 1 4 a 40 0 z E 30 sc 1 o q 5 z 30 45 Z S o i E Isc 20 90 8 2 1 S 20 8 10 135 E a lsc Z E 5 2 G 180 tc ul w a 2 10 40 225 4 d w Vg 5V Vc 2 BV z 20 270 0 30 50 25 0 25 50 75 100 125 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M TEMPERATURE C FREQUENCY Hz FREQUENCY Hz Figure 12 Short Circuit Current vs Figure 15 Open Loop Gain and Phase Figure 18 Closed Loop Gain vs Temperature vs Frequency No Load Frequency 2 kQ Load 80 60 Vg 43V 60 va 2 50 RL 2kO A 4 Ta 25 C is NO LOAD t CR AT m2. Vg gt Voyr 0 1V OPTIONAL ON OFF CONTROL INPUT CMOS HI OR OPEN ON LO OFF Vin COMMON O Figure 55 shows such a regulator set up using an OP284 plus a low Rps ou P channel MOSFET pass device Part of the low dropout performance of this circuit is provided by Q1 which has a rating of 0 11 Q with a gate drive voltage of only 2 7 V T his relatively low gate drive threshold allows operation of the regulator on supplies as low as 3 V without compromise to over all performance T he circuit s main voltage control loop operation is provided by U 1B half of the OP284 This voltage control amplifier ampli fies the 2 5 V reference voltage produced by three terminal U 2 a REF192 The regulated output voltage Voy is then Vout ouT 1 R3 For the example here aV aur of 4 5 V with Voyr2 2 5 V re quires a U 1B gain of 1 8 times so R3 and R2 are chosen for a ratio of 1 2 1 or 10 0 kQ 8 06 kQ using closest 196 values Note that for the lowest Vour dc error R2 R3 should be main tained equal to R1 as here and the R2 R 3 resistors should be stable close tolerance metal film types T hetable in Figure 55 summarizes R1 R3 values for some popular voltages H owever note that in general the output can be anywhere between Voyrt2 to the 12 V maximum rating of Q1 While the low voltage saturation characteristic of Q1 is a key part of the low dropout another component is a low current sense comparison threshold wit
3. 0P184 0P284 0P484 ELECTRICAL CHARACTERISTICS Vg 3 0 V Vem 1 5 V Ty 25 C unless otherwise noted Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage OP 184 284E Grade Vos N ote 1 65 WV 40 C lt T4 125 C 165 W Offset Voltage OP184 284F Grade Vos 125 W 40 C lt T 125 C 350 WW Offset Voltage 484E Grade Vos 100 uV 40 C lt T lt 125 C 2001 uV Offset Voltage 484F Grade Vos 150 WW 40 C lt T 125 C 450 uV Input Bias Current lg 60 300 nA 40 C lt T 125 C 500 nA Input Offset C urrent los 40 C lt T a 125 C 50 nA Input Voltage Range 0 3 V Common M ode Rejection Ratio CMRR Vem 20V to3V 60 dB Common M ode Rejection Ratio CMRR Vem 20V to3V 40 C lt Ta lt 125 C 56 dB OUTPUT CHARACTERISTICS Output Voltage H igh VoH I 1 0 mA 2 85 V Output Voltage Low VoL IL 1 0 mA 125 mV POWER SUPPLY Power Supply Rejection Ratio PSRR Vs 1 25 V to 1 75 V 76 dB Supply Current Amplifier Icy Vo 1 5V 40 C lt T lt 125 C 1 15 mA DYNAMIC PERFORMANCE Gain Bandwidth Product GBP 3 MHz NOISE PERFORMANCE Voltage N oise D ensity en f 1kHz 3 9 nV Hz NOTES Input Offset Voltage measurements are performed by automated test equipment approximately 0 5 seconds after application of power Specifications subject to change without notice REV 0 3 0P184 0P284 0P464 ELECTRICAL
4. 4 REV 0 OP184 0P284 0P484 ABSOLUTE MAXIMUM RATINGS SupplyVoltage 18V m Input Voltage 4 x ccce 8 ve pet ede 18V 1 F Y Ej li 8 Differential Input Voltage oana 0 6 V E ess au Output Short Circuit Duration to GND Indefinite t ng 7 Storage T emperature Range S HEN P S Packages 65 C to 150 C 2 A Operating T emperature Range 3 m rl OP184 OP284 OP484E F 40 C to 125 C Junction T emperature Range P SPackages 65 C to 150 C Lead T emperature Range Soldering 60 sec 300 C Package Type Oya gc Units 8 Pin Plastic DIP P 103 43 C W OP284 Die Size 0 065 x 0 092 Inch 5 980 Sq Mils 8 Pin SOIC S 158 43 C W Substrate Die Backside Is Connected to V 14 Pin Plastic DIP P 83 39 C W Transistor Count 62 14 Pin SOIC S 92 27 C W NOTES absolute maximum ratings apply to both DICE and packaged parts unless otherwise noted F or input voltages greater than 0 6 volts the input current should be limited to less than 5 mA to prevent degradation or destruction of the input devices 70 is specified for the worst case conditions i e 0j is specified for device in socket for cerdip and P D IP packages 9a is specified for device soldered in circuit board for SOIC package ORDERING GUIDE Temperature Package Package Model Range Descriptio
5. Av 100k OPEN _ 9 eq 0 3yuVp p 300pF CURRENT NOISE DENSITY pA VHz 1 10 100 1000 FREQUENCY Hz Figure 30 Current Noise Density Figure 33 0 1 Hz to 10 Hz Noise Figure 36 Small Signal Transient vs Frequency Response tas 1 ts 7 Ay 100k 100 a3 en 0 3MVp p_ 400mV pras _ Ri 2kQ mE EE 29 Car T T NT ARKA T eee TT NW tr SEP gi ie ee STEP SIZE Volts 0 1 2 3 4 5 6 SETTLING TIME us Figure 31 Settling Time vs Step Size Figure 34 0 1 Hz to 10 Hz Noise Figure 37 Small Signal Transient Response REV 0 9 0P184 0P284 0P464 200mV Mi Figure 38 Small Signal Transient Response Response e lt L H THD N Figure 39 Small Signal Transient 0 1 Ap Vo 0 75V Ay 1000 s 0 010 Vg 2 5V 1 R 2kO Vo 2 5V 0 001 Vo 1 5V 0 0005 20 100 1k 10k 20k FREQUENCY Hz Figure 40 Total Harmonic Distortion vs Frequency APPLICATIONS Functional Description T he OP 284 and OP 484 are precision single supply rail to rail operational amplifiers Intended for the portable instrumenta tion marketplace the OP 184 0 P 284 0 P 484 combines the at tributes of precision wide bandwidth and low noise
6. 2kQ 2 4 4 0 V us Full Power Bandwidth BWp 1 Distortion R 2 2 KQ Vo 2 29 V p p 35 kHz Settling T ime ts T o 0 0196 10 V Step 4 Gain Bandwidth Product GBP 4 25 MHz Phase M argin Qo 50 D egrees NOISE PERFORMANCE Voltage N oise en p p 0 1Hzto 10 Hz 0 3 uV p p Voltage N oise D ensity en f 1kHz 3 9 nV Hz Current N oise D ensity in 0 4 pA NHS NOTES 1Input Offset Voltage measurements are performed by automated test equipment approximately 0 5 seconds after application of power Specifications subject to change without notice WAFER TEST LI MITS Vs 5 0 V Vem 2 5 V Ty 25 C unless otherwise noted Parameter Symbol Conditions Limit Units Offset Voltage OP284 Vos 65 uV max Offset Voltage OP484 Vos 75 uV max Input Bias Current lp 300 nA max Input Offset Current los 50 nA max Input Voltage Range Vem V toV V min Common M ode Rejection Ratio CMRR Vem 1V to 4V 86 dB min Power Supply Rejection Ratio PSRR Ve 2Vto 1l8V 90 dB min Large Signal Voltage Gain Avo RL 2kQ 50 V mV min Output Voltage High Vou I 1 0 mA 4 85 V min Output Voltage Low Voi I 1 0 mA 125 mV max Supply Current A mplifier Icy Vo 0V RL e 1 25 mA max NOTE Electrical tests and wafer probe to the limits shown Due to variations in assembly methods and normal yield loss yield after packaging is not guaranteed for standard product dice Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing
7. 0 50 0 75 Vs 5V 40 C lt T lt 125 C 10 21425 1 5 OFFSET VOLTAGE DRIFT TCVog uV C Distribution QUANTITY 200 100 40 C lt T lt 125 C 0 0 25 0 50 0 75 1 0 1 25 1 5 OFFSET VOLTAGE DRIFT TCVog uV C Figure 6 Input Offset Voltage Drift Distribution INPUT BIAS CURRENT nA 40 25 85 125 TEMPERATURE C Figure 7 Bias Current vs Temperature INPUT BIAS CURRENT nA e eo 0 15 10 5 0 5 10 15 COMMON MODE VOLTAGE Volts Figure 8 Input Bias Current vs Common Mode Voltage 1 000 Vg 15V gt E SOURCE 1 U e amp D 100 SINK S gt E 2 n E 2 o 10 0 01 0 1 1 10 LOAD CURRENT mA Figure 9 Output Voltage to Supply Rail vs Load Current 12 1 1 Vs 15V 1 0 0 9 0 8 Vs 45V 0 7 Vs 43V 0 6 SUPPLY CURRENT AMPLIFIER mA 0 5 40 25 85 125 TEMPERATURE C Figure 10 Supply Current vs Temperature REV 0 0P184 0P284 0P464 a 60 E Vg 5V A 2 RL 2kQ E 40 T
8. 40 0 ES d 30 7 9 z 30 45 P t G 20 a 2o 90 i Q 1 b 1 o 9 10 135 E 9 g 0 3 5 8 10 N 0 180 B a 10 225 E 220 20 270 a 30 30 0 40 10k 100k 1M 10M 50 25 0 25 50 75 100 125 10 100 1k 10k 100k 1M 10M FREQUENCY Hz TEMPERATURE C FREQUENCY Hz Figure 13 Open Loop Gain and Phase Figure 16 Open Loop Gain vs Figure 19 Closed Loop Gain vs vs Frequency No Load Temperature Frequency 2 kQ Load REV 0 0P184 0P284 0P484 Typical Performance Characteristics 300 270 240 Vg 5V Ty 25 C 210 180 150 120 OUTPUT IMPEDANCE Q 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 20 Output Impedance vs Frequency Ay 100 180 M Ay 10 OUTPUT IMPEDANCE 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 21 Output Impedance vs Frequency 270 Ys 3V Ay 100 T 25 C OUTPUT IMPEDANCE Q 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 22 Output Impedance vs Frequency MAXIMUM OUTPUT SWING Vp p 1k 10k 100k 1M 10M FREQUENCY Hz Figure 23 Maximum Output Swing vs Frequency 25 N eo a
9. CHARACTERISTICS Vs 15 0 V Vy 0 V T 25 C unless otherwise noted Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage OP 184 284E Grade Vos Note 1 100 WW 40 C T4 125 C 200 W Offset Voltage 284F Grade Vos 175 W 40 C lt T a 125 C 375 UV Offset Voltage 484E Grade Vos 150 UW 40 C T4 125 C 300 W Offset Voltage 484F Grade Vos 250 UV 40 C lt T a 125 C 500 WW Input Bias Current lp 80 300 nA 40 C T4 125 C 500 nA Input Offset Current los 40 C TA 125 C 50 nA Input Voltage Range 15 115 V Common M ode Rejection Ratio CMRR Vey 14 0 V to 14 0 V 40 C lt T a lt 125 C 86 90 dB Common M ode Rejection Ratio CMRR Vem 15 0 V to 15 0 V 80 dB Large Signal Voltage G ain Avo R 2 KQ 10V lt Vo lt 10V 150 1000 V mV R 2 kQ 40 C TA 125 C 75 V mV Offset Voltage Drift E Grade AV os AT 0 2 2 00 V C Bias Current D rift Alg AT 150 pA C OUTPUT CHARACTERISTICS Output Voltage High Vou IL 1 0 mA 114 8 V Output Voltage Low VoL l 1 0 mA 14 875 V Output Current lout 10 mA POWER SUPPLY Power Supply Rejection Ratio PSRR Vs 2 0 V to 18 V 40 C lt T TA lt 125 C 90 dB Supply Current Amplifier Icy Vo 0V 40 C TAX 125 C 1 75 mA Supply Current Amplifier Icy Vo 18V 40 C lt T 125 C 2 0 mA DYNAMIC PERFORMANCE Slew Rate SR R
10. D IS 130E 21 MODEL DX D MODEL DEN D RS 100 KE 12E 15 AF 1 MODEL DIN D RS 5 358 KF 56E 15 AF 1 MODEL QIN NPN BF 200 VA 200 IS 0 5E 16 MODEL QIP PNP BF 100 VA 60 IS 0 5E 16 MODEL QON NPN BF 200 VA 200 IS 0 5E 16 RC 50 MODEL QOP PNP BF 200 VA 200 IS 0 5E 16 RC 160 ENDS 18 REV 0 OP184 0P284 0P484 OUTLINE DIMENSIONS Dimensions shown in inches and mm 8 Lead E poxy DIP P Suffix 0 430 10 92 0 348 8 84 S n 4 0 280 7 11 0 240 6 10 0 325 8 25 0 300 7 62 PIN1 0 060 1 52 0 210 5 33 0 015 0 36 to 4 95 max U L dazd 0 115 2 93 0 160 4 06 T NE 3 30 0 115 2 93 H SEATING 0 015 0 381 0 022 0 zoey lac 0 070 1 77 SEATIN 0 008 10 204 0 014 0 356 9 54 0 045 1 15 BSC amp Lead SO S Suffix 0 1968 5 00 7 0 1890 4 80 y 8 s 0 2440 6 20 0 1574 4 00 0 2284 5 80 0 1497 3 80 1 4 e PIN1 0 0688 1 75 0 0196 0 50 0 0532 1 35 F 0 0099 0 25 0 0098 0 25 CHIETI 0 0040 0 10 gt fe ie 8 0 0500 0 0192 0 49 T pz TH 27 SEATING 1 27 0 0148 0 35 0 0098 0 25 0 0760 0 41 PLANE BSC 0 0075 0 19 l REV 0 19 14 Lead E poxy DIP P Suffix 0 795 20 19 0 725 18 42 m 0 280 7 11 0 240 6 10 0 325 8 25 0 060 1 52 0 300 7 62 0 195 4 95 PIN 1 0 015 0 38 0 115 2 93 0 210 5 33 t max N LJ LJ L L LU L 0 130 0 160 4 06 Ns N 30 Ti MIN 0 115 2 93
11. T he top trace was taken with a 1 nF load and the bottom trace was taken with the 50 Q 100 nF snubber network in place T he amount of overshoot and ringing is dramatically reduced T able below illustrates a few sample snubber networks for large load capacitors REV 0 0P184 0P284 0P464 pt pee 1nF LOAD ONLY SNUBBER IN CIRCUIT Ez E LJIDBEE EN Figure 54 Overshoot and Ringing Is Reduced by Adding a Snubber Network in Parallel with the 1 nF Load Tablel Snubber Networks for Large Capacitive Loads Load Capacitance Snubber Network C1 Rs Cs 1 nF 50 Q 100 nF 10 nF 20 Q 1 uF 100 nF 5 Q 10 uF A Low Dropout Regulator with Current Limiting M any circuits require stable regulated voltages relatively close in potential to an unregulated input source This low dropout type of regulator is readily implemented with a rail to rail out put op amp such as the OP 284 because the wide output swing allows easy drive to a low saturation voltage pass device Fur thermore it is particularly useful when the op amp also enjoys a rail rail input feature as this factor allows it to perform high side current sensing for positive rail current limiting T ypical ex amples are voltages developed from 3 V to 9 V range system sources or anywhere where low dropout performance is required for power efficiency T he 4 5 V case here works from 5 V nomi nal sources with worst case levels down to 4 6 V or less
12. applications T he value of this capacitor should be adjusted depending on the required closed loop bandwidth of the circuit The R4 C2 time constant creates a pole at a frequency equal to 1 f B 398 2rnR4C2 REV 0 5pF 40pF R1 P1 R4 Figure 49 A Single Supply 3 V Low Noise Instrumenta tion Amplifier A 2 5 V Reference from a 3 V Supply In many single supply applications the need for a 2 5 V refer ence often arises M any commercially available monolithic 2 5 V references require at least a minimum operating supply of 4V The problem is exacerbated when the minimum operating supply voltage is 3 V The circuit illustrated in Figure 50 is an example of a 2 5 V reference that operates from a single 3 V supply T he circuit takes advantage of the OP 284 s rail to rail input output voltage ranges to amplify an AD 589 s 1 235 V output to 2 5 V The OP284 s low T CVos of 1 5 UVAec helps to maintain an output voltage temperature coefficient which is dominated by the temperature coefficients of R2 and R3 In this circuit with 100 ppm C TCR resistors the output voltage exhibits a temperature coefficient of 200 ppm C Lower tempco resistors are recommended for more accurate performance over temperature O ne measure of the performance of a voltage reference is its capability to recover from sudden changes in load current While sourcing a steady state load current of 1 mA this circuit recovers to 0
13. equivalent circuit shown in Figure 41 the OP284 does not have any internal current limiting resistors thus fault currents can quickly rise to damaging levels T his input current is not inherently damaging to the device provided that it is limited to 5 mA or less For the OP284 once the input exceeds the negative supply by 0 6 V the input cur rent quickly exceeds 5 mA If this condition continues to exist an external series resistor should be added at the expense of ad ditional thermal noise Figure 44 illustrates a typical noninvert ing configuration for an overvoltage protected amplifier where the series resistance Rs is chosen such that R Vin MAX V sUPPLY x 5mA REV 0 Figure 44 A Resistance in Series with an Input Limits Overvoltage Currents to Safe Values For example a 1 kO resistor will protect the O P284 against input signals up to 5 V above and below the supplies For other configurations where both inputs are used then each input should be protected against abuse with a series resistor Again in order to ensure optimum dc and ac performance it is recom mended to balance source impedance levels For more informa tion on the general overvoltage characteristics of amplifiers please refer to the 1993 System A pplications G uide Section 1 pages 56 69 T his reference textbook is available from the Ana log Devices Literature C enter Output Phase Reversal Some operational amplifiers designed for
14. ig ui e 0 015 0 381 0 100 0 070 1 77 SEATING 2 54 0 045 1 15 BSC 0 022 0 558 0 014 0 356 0 008 0 204 14 Lead Narrow Body SO S Suffix 0 3444 8 75 0 3367 8 55 8 0 2440 6 20 0 2284 5 80 0 1574 4 00 0 1497 3 80 PIN 1 0 0688 1 75 0 0196 0 50 4 0 0532 1 35 TY 0 0099 0 25 coment PEO i 0 0040 0 10 je gt e T 8 lhe 0 0500 0 0192 0 49 0 0 0500 1 27 SEATING 1 27 0 0138 0 35 0 0098 0 25 0 0160 0 41 PLANE BSC 0 0075 0 19 0 41 96 6 8T 9TZ2 V S f NI GALNIdd 20
15. so that the circuit generates a5 V output when the DAC output is at full scale If other output voltage ranges are needed such as 0 V Vout 4 095 V the gain can easily be changed by adjusting the values of R2 and R3 A High Side Current Monitor In the design of power supply control circuits a great deal of design effort is focused on ensuring a pass transistor s long term reliability over a wide range of load current conditions Asa result monitoring and limiting device power dissipation is of prime importance in these designs T he circuit illustrated in Figure 52 is an example of a 3 V single supply high side cur rent monitor that can be incorporated into the design of a volt age regulator with fold back current limiting or a high current power supply with crowbar protection T his design uses an OP284 s rail to rail input voltage range to sense the voltage drop across a 0 1 Q current shunt A p channel MOSFET used as the feedback element in the circuit converts the op amp s dif ferential input voltage into a current T his current is then ap plied to R2 to generate a voltage that is a linear representation of the load current T hetransfer equation for the current monitor is given by M onitor O utput xax suse jen 14 For the element values shown the M onitor Output s transfer characteristic is 2 5 V A M1 Si9433 MONITOR OUTPUT Figure 52 A High Side Load Current Monitor Capacitive Load Drive Cap
16. to make it a superb choice in those single supply applications that require both ac and precision dc performance Other low supply voltage applications for which the OP 284 is well suited are active filters audio microphone preamplifiers power supply control and tele com To combine all of these attributes with rail to rail input output operation novel circuit design techniques are used Vpos O Figure 41 OP284 Equivalent Input Circuit For example Figure 41 illustrates a simplified equivalent circuit for the OP 184 0 P284 0 P 484 s input stage It is comprised of an N PN differential pair Q1 Q2 and a PNP differential pair Q3 Q4 operating concurrently Diode network D 1 D2 serves to clamp the applied differential input voltage to the O P284 thereby protecting the input transistors against avalanche dam age Input stage voltage gains are kept low for input rail to rail operation T he two pairs of differential output voltages are con nected to the O P284 s second stage which is a compound folded cascode gain stage It is also in the second gain stage where the two pairs of differential output voltages are combined into a single ended output signal voltage used to drive the output 10 stage A key issue in the input stage is the behavior of the input bias currents over the input common mode voltage range Input bias currents in the OP284 are the arithmetic sum of the base currents in Q1 Q3 and in Q2 Q4 Asa result of this de
17. 01 of the programmed output voltage in 1 5 us for a total change in load current of 1 mA 2 5VREF 3 R2 P1 100kQ 100kQ 5kQ RESISTORS 1 100ppm C POTENTIOMETER 10 TURN 100ppm C Figure 50 A 42 5 V Reference that Operates on a Single 43 V Supply 13 0P184 0P284 0P464 A 5V Only 12 Bit DAC Swings Rail to Rail T he OP 284 is ideal for use with a CM OS DAC to generate a digitally controlled voltage with a wide output range Figure 51 shows a DAC8043 used in conjunction with the AD 589 to gen erate a voltage output from 0 V to 1 23 V TheDAC is actually operating in voltage switching mode where the reference is connected to the current output lour and the output voltage is taken from the Veer pin T his topology is inherently noninvert ing as opposed to the classic current output mode which is inverting and not usable in single supply applications 45V Q lour DAC8043 VREF GND CLK SR1 LD D O Vout pag 5V DIGITAL CONTROL R3 R2 R4 2320 32 4kO 100kQ 1 1 1 Figure 51 A 5 V Only 12 Bit DAC Swings Rail to Rail In this application the OP284 serves two functions First it buffers the high output impedance of the DAC s V nse pin which is on the order of 10 kQ The op amp provides a low impedance output to drive any following circuitry Second the op amp amplifies the output signal to provide a rail to rail out put swing In this particular case the gain is set to 4 1
18. 10kQ IN 10V STEP Figure 48 Output Overload Recovery Test Circuit A Single Supply 3 V Instrumentation Amplifier T he OP284 s low noise wide bandwidth and rail to rail input output operation makes it ideal for low supply voltage applica tions such asin an two op amp instrumentation amplifier as shown in Figure 49 The circuit utilizes the classic two op amp instrumentation amplifier topology with four resistors to set the gain The transfer equation of the circuit is identical to that of a noninverting amplifier Resistors R2 and R3 should be closely matched to each other as well as resistors R1 P1 and R4 to ensure good common mode rejection performance Resistor networks should be used in this circuit for R2 and R3 because they exhibit the necessary relative tolerance matching for good performance M atched networks also exhibit tight relative resis tor temperature coefficients for good circuit temperature stabil ity Trimming potentiometer P1 is used for optimum dc CMR adjustment and C1 is used to optimize ac CMR With the cir cuit values as shown circuit CM R is better than 80 dB over the frequency range of 20 Hz to 20 kHz Circuit RTI Referred to Input noise in the 0 1 Hz to 10 Hz band is an impressively low 0 45 uV p p Resistors RP1 and RP2 serve to protect the OP284 s inputs against input overvoltage abuse Capacitor C2 can be included to the limit circuit bandwidth and therefore wide bandwidth noise in sensitive
19. LE AT 40MHz DC2 11 2 DC T Q5 4 9 99 QIP 1 G4 98 29 28 98 1 Q6 9 9 99 QIP 1 R19 29 98 1 Q7 3 10 50 QIN 1 C9 29 98 3 979E 9 Q8 10 10 50 QIN 1 R1 99 5 4E3 POLE AT 40MHz R2 99 6 4E3 T R3 7 50 4E3 G5 98 30 29 98 1 RA 8 50 4E3 R20 30 98 1 IREF 9 10 50 5E 6 C10 30 98 3 979E 9 EOS 1 11 POLY 2 22 98 14 98 25E 6 1E 2 1 10S 2 1 5E 9 OUTUT STAGE CIN 1 2 2E 12 GN1 98 1 17 98 1E 3 ISY 99 50 0 276E 3 GN2 98 2 23 98 1E 3 GIN 50 31 POLY 1 30 98 862574E 6 505 879E 6 RIN 31 50 2 75E6 VOLTAGE NOISE SOURCE WITH FLICKER NOISE VB 99 32 0 7 Q11 32 31 33 QON 1 VN1 13 98 DC2 R21 33 34 4 5E3 VN2 98 15 DC2 I1 34 50 50E 6 DN1 13 14 DEN R22 99 35 6E3 DN2 14 15 DEN Q12 36 36 35 QOP 1 12 36 50 50E 6 CURRENT NOISE SOURCE WITH FLICKER NOISE R23 99 37 2 6E3 R24 34 38 5E3 VN3 16 98 DC2 Q13 39 36 37 QOP 1 VN4 98 18 DC2 Q14 39 38 40 QON 1 5 DN3 16 17 DIN R25 40 50 40 DN4 17 18 DIN Q15 39 39 41 QON 1 R26 41 42 1E3 2ND CURRENT NOISE SOURCE WITH FLICKER R27 99 43 220 NOISE Q16 44 44 43 QOP 1 5 N Q17 44 39 42 QON 1 VN5 19 98 DC 2 R28 42 50 2E3 VN6 98 24 DC 2 VSCP 99 97 DC 0 REV 0 17 0P184 0P284 0P464 FSCP 46 99 VSCP 1 RSCP 46 99 40 Q20 44 46 99 QOP1 Q18 45 44 97 QOP 4 5 Q19 45 34 51 QON 4 5 VSCN 51 50 DCO FSCN 50 47 VSCN 1 RSCN 47 50 40 Q21 34 47 50 QON1 CC2 31 45 20E 12 CFl 31 34 15E 12 CF2 31 42 15E 2 COI 34 45 15E 12 CO2 42 45 5r 12 D3 45 99 DX D4 50 45 DX MODEL DC
20. U U OPI amp amp ES ANALOG DEVICES Precision Rail to Rail Input amp Output Operational Amplifiers OP 184 0P284 0P484 FEATURES Single Supply Operation Wide Bandwidth 4 MHz Low Offset Voltage 65 kV Unity Gain Stable High Slew Rate 4 0 V s Low Noise 3 9 nV VHz APPLICATIONS Battery Powered Instrumentation Power Supply Control and Protection Telecom DAC Output Amplifier ADC Input Buffer GENERAL DESCRIPTION T he OP 184 0 P 184 0 P284 0 P 484 are single dual and quad single supply 4 M Hz bandwidth amplifiers featuring rail to rail inputs and outputs T hey are guaranteed to operate from 3 to 36 or 1 5 to 18 volts and will function with a single supply as low as 1 5 volts T hese amplifiers are superb for single supply applications re quiring both ac and precision dc performance T he combination of bandwidth low noise and precision makes the OP 184 0 P 284 OP484 useful in a wide variety of applications including filters and instrumentation Other applications for these amplifiers include portable telecom equipment power supply control and protection and as amplifi ers or buffers for transducers with wide output ranges Sensors requiring a rail to rail input amplifier include H all effect piezo electric and resistive transducers T he ability to swing rail to rail at both the input and output en ables designers to build multistage filters in single supply sys tems and maintain high sign
21. a function of the source resistance level N ote that the lowest noise figure for the O P284 occurs at a source resistance level of 10 kQ However Figure 46 shows that this source resistance level and the OP 284 generate approximately 14 nV NHz of total equivalent circuit noise Signal levels in the application would invariably be increased to maximize circuit SN R not an option in low voltage single supply applications NOISE FIGURE dB 100k 100 1k 10k TOTAL SOURCE RESISTANCE Rs 2 Figure 47 OP284 Noise Figure vs Source Resistance In single supply applications it is therefore recommended for optimum circuit SN R to choose an operational amplifier with the lowest equivalent input noise voltage and to choose source resistance levels consistent in maintaining low total circuit noise REV 0 OP184 0P284 0P484 RP1 1kQ 3V Overdrive Recovery T he overdrive recovery time of an operational amplifier is the time required for the output voltage to recover to its linear re gion from a saturated condition T he recovery time is important in applications where the amplifier must recover quickly after a large transient event T he circuit shown in Figure 48 was used to evaluate the OP 284 s overload recovery time The OP284 takes approximately 2 hs to recover from positive saturation and approximately 1 hs to recover from negative saturation R1 R2 10kQ
22. ability T he OP 284 exhibits excellent capacitive load driving capabili ties It can drive up to 1 nF as shown in Figure 27 H owever even though the device is stable a capacitive load does not come without penalty in bandwidth T he bandwidth is reduced to under 1 M Hz for loads greater than 2 nF A snubber network on the output doesn t increase the bandwidth but it does sig nificantly reduce the amount of overshoot for a given capacitive load A snubber consists of a series R C network Rs Cs as shown in Figure 53 connected from the output of the device to ground This network operates in parallel with the load capaci tor C to provide the necessary phase lag compensation T he value of the resistor and capacitor is best determined empirically Vour V N 100mVp p Rg 50Q DL Cs 1nF 100nF Figure 53 Snubber Network Compensates for Capacitive Load T he first step is to determine the value of the resistor Rs A good starting value is 100 Q typically the optimum value will be less than 100 Q T his value is reduced until the small signal transient response is optimized Next Cs is determined 10 uF is a good starting point T his value is reduced to the smallest value for acceptable performance typically 1 uF For the case of a 10 nF load capacitor on the OP 284 the optimal snubber network is a 20 Q in series with 1 uF The benefit is immedi ately apparent as shown in the scope photo in Figure 54
23. al to noise ratios T he OP184 O P284 O P484 are specified over the HOT extended industrial 40 C to 125 C temperature range T he single and dual are available in 8 pin plastic DIP plus SO surface mount packages T he quad OP484 is available in 14 pin plastic DIPs and 14 lead narrow body SO packages REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices PIN CONFIGURATIONS 8 Lead E poxy DIP P Suffix 8 Lead SO S Suffix NC NO CONNECT 8 Lead E poxy DIP P Suffix amp Lead SO S Suffix 14 Lead E poxy DIP P Suffix 14 Lead Narrow Body SO S Suffix Analog Devices Inc 1996 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 617 329 4700 Fax 617 326 8703 0P164 0P264 0P464 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Vs 5 0 V Vem 2 5 V T 25 C unless otherwise noted Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage OP 184 284E Grade Vos Note 1 65 uV 40 C T4 125 C 165 uv Offset Voltage OP 184 284F Grade Vos 125 V 40 C lt T a 125 C 350 UV Offset V oltag
24. e 484E Grade Vos 75 uV 40 C lt Ta lt 125 C 175 V Offset Voltage 484F Grade Vos 150 V 40 C T4 125 C 450 uv Input Bias C urrent lp 60 300 nA 40 C T4 125 C 500 nA Input Offset Current los 2 50 nA 40 C lt T a 125 C 50 nA Input Voltage Range 0 5 V Common M ode Rejection Ratio CMRR Vcu 0Vto5V 60 dB Common M ode Rejection Ratio CMRR Vem 2 1 0V to 4 0 V 40 C lt T a 125 C 86 dB Large Signal Voltage Gain Avo RL 2kO 1V lt Vo lt 4V 50 240 V mV R 2 kQ 40 C TA 125 C 25 V mV Bias Current D rift Alg AT 150 pA C OUTPUT CHARACTERISTICS Output Voltage High Vou IL 1 0 mA 4 85 V Output Voltage Low VoL IL 1 0 mA 125 mV Output Currrent lout 6 5 mA POWER SUPPLY Power Supply Rejection Ratio PSRR Vs 2 0 V to 10 V 40 C lt T lt 125 C 76 dB Supply C urrent A mplifier Isy Vo 2 5V 40 C lt T a 125 C 1 25 mA Supply Voltage Range Vs 3 36 V DYNAMIC PERFORMANCE Slew Rate SR R 2kQ 1 65 2 4 V us Settling T ime ts To0 01 1 0 V Step 2 5 us Gain Bandwidth Product GBP 3 25 MHz Phase M argin o 45 D egrees NOISE PERFORMANCE Voltage N oise en p p 0 1Hzto10Hz 0 3 uV p p Voltage N oise D ensity en f 1kHz 3 9 nV Hz Current N oise D ensity in 0 4 pANHz NOTES 1Input Offset Voltage measurements are performed by automated test equipment approximately 0 5 seconds after application of power Specifications subject to change without notice REV 0
25. edance ac ground over the operating frequency range of the filter T he filter section uses a OP484 in a twin T configuration whose frequency selectivity is very sensitive to the relative matching of the capacitors and resistors in the twin T section M ylar is the material of choice for the capacitors and the relative matching of the capacitors and resistors determines the filter s pass band symmetry Using 1 resistors and 5 capacitors produces satisfactory results REV 0 0P184 0P284 0P464 OP284 SPICE M acro model 9 94 Rev A DN5 19 23 DIN i ARG ADI DN6 23 24 DIN Copyright 1995 by Analog D evices GAIN STAGE Refer to READM E DOC file for License Statement U se of EREF 98 0 POLY 2 99 0 50 0 0 0 5 0 5 this model G1 98 20 POLY 2 6 5 8 7 0 0 5E 3 0 5E 3 indicates your acceptance of the terms and provisions in the R9 20 98 1E3 License Statement COMMON MODE STAGE WITH ZERO AT 100Hz Node assignments ECM 98 21 POLY 2 1 98 2 98 0 0 5 0 5 N noninverting input R10 21 22 1 T inverting input R11 22 98 100E 6 N positive supply C4 21 22 1 592E 3 negative supply T output NEGATIVE ZERO AT 20M Hz im mm i SSUBCKT OP284 1 2 995045 El 27 98 20 98 1E6 R17 27 28 1 INPUT STAGE R18 28 98 1E 6 C8 25 26 7 958E 9 Q1 5 2 3 QIN 1 ENZ 25 98 27 28 1 Q2 6 11 3 QIN 1 VNZ 26 98 DC0 Q3 7 2 4 QIP 1 FNZ 27 28 VNZ 1 Q4 8 11 4 QIP 1 l DC1 2 11 DC PO
26. eo MAXIMUM OUTPUT SWING Vp p oa 1k 10k 100k 1M 10M FREQUENCY Hz Figure 24 Maximum Output Swing vs Frequency CMRR dB 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 25 CMRR vs Frequency 160 140 120 100 PSRR dB T 25 C 80 60 Vg 15 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 26 PSRR vs Frequency OVERSHOOT CAPACITIVE LOAD pF Figure 27 Small Signal Overshoot vs SLEW RATE V us Capacitive Load 0 50 25 0 25 50 75 100 125 TEMPERATURE C Figure 28 Slew Rate vs Temperature REV 0 OP184 0P284 0P484 30 25 a N D l z 20 2 e o gt T E 5 15 S a o 7 a m EU 5 2 K 10 100 1000 0 1 2 3 4 5 6 100 1k 10k 100k 1M 10M FREQUENCY Hz SETTLING TIME hs FREQUENCY Hz Figure 29 Voltage Noise Density Figure 32 Settling Time vs Step Size Figure 35 Channel Separation vs Frequency vs Frequency 32 5V lt Vg lt 18V Vg 15V to
27. er 10 ms A 3 V 50Hz 60 Hz Active Notch Filter with False Ground T o process signals in a single supply system it is often best to use a false ground biasing scheme A circuit that uses this approach is illustrated in Figure 56 In this circuit a false ground circuit biases an active notch filter used to reject 50 H z 60 Hz power line interference in portable patient monitoring equip ment Notch filters are quite commonly used to reject power line frequency interference which often obscures low frequency 16 physiological signals such as heart rates blood pressure read ings EEGs EKGs et cetera This notch filter effectively squelches 60 Hz pickup at a filter Q of 0 75 Substituting 3 16 kQ resistors for the 2 67 kQ in the twin T section R1 through R5 configures the active filter to reject 50 Hz interference 2 67kO NOTE FOR 50Hz APPLICATIONS CHANGE R1 R4 TO 3 1kQ AND R5 TO 1 58kO 3 16kQ 2 Figure 56 A 43 V Single Supply 50 60 Hz Active Notch Filter with False Ground Amplifier A3 is the heart of the false ground bias circuit It simply buffers the voltage developed at R9 and R10 and is the reference for the active notch filter Since the OP484 exhibits a rail to rail input common mode range R9 and R10 are chosen to split the 3 V supply symmetrically An in the loop compen sation scheme is used around the OP484 that allows the op amp to drive C6 a 1 uF capacitor without oscillation C6 maintains a low imp
28. h good dc accuracy H ere this is provided by current sense amplifier U 1A which is provided a 20 mV reference from the 1 235 V AD589 reference diode D2 and the R7 R8 divider When the product of the output current and the Rs value matches this voltage threshold the current control loop is activated and U 1A drives Q1 s gate through D 1 T his causes the overall circuit operation to enter current mode control with a current limit lL m r defined as _ VR D2 R7 LIMIT Rs R7 R8 Q1 SI9433DY D1 1N4148 Der 2 OP284 8 06kO Vour 4 5V 350mA OUTPUT TABLE SEE TABLE Mour RI R2 R3 5 0V 4 99k 10 0k 10 0k 4 5V 4 53k 8 06k 10 0k c6 3 3V 2 43k 3 24k 10 0k 10uF 3 0V 1 69k 2 00k 10 0k Figure 55 A Low Dropout Regulator with Current Limiting REV 0 15 0P184 0P284 0P464 Obviously it is desirable to keep this comparison voltage small since it becomes a significant portion of the overall dropout voltage Here the 20 mV reference is higher than the typical offset of the OP 284 but still reasonably low as a percentage of Vout lt 0 596 In adapting the limiter for other l m r levels sense resistor Rs should be adjusted along with R7 R8 to main tain this threshold voltage between 20 mV and 50 mV Performance of the circuit is excellent For the 4 5 V output version the measured dc output change for a 225 mA load change was on the order of a few microvolts while the dropout voltage at this same c
29. n Option OP184EP 40 C to 125 C 8 Pin Plastic DIP N 8 OP184ES 40 C to 125 C 8 Pin SOIC SO 8 OP184FP 40 C to 125 C 8 Pin Plastic DIP N 8 OP184FS 40 C to 125 C 8 Pin SOIC SO 8 OP284EP 40 C to 125 C 8 Pin Plastic DIP N 8 OP284ES 40 C to 125 C 8 Pin SOIC 30 8 OP484 Die Size 0 080 x 0 110 Inch 8 800 Sq Mils OP284FP 40 C to 125 C 8 Pin Plastic DIP N 8 OP284FS 40 C to 125 C 8 Pin SOIC S0 8 Substrate Die Backside Is Connected to V Transistor Count 120 OP484EP 40 C to 125 C 14 Pin Plastic DIP N 14 OP484ES 40 C to 125 C 14 Pin SOIC SO 14 OP484FP 40 C to 125 C 14 Pin Plastic DIP N 14 OP484FS 40 C to 125 C 14 Pin SOIC SO 14 REV 0 z Figure 1 Simplified Schematic OP184 0P284 0P484 Typical Performance Characteristics QUANTITY QUANTITY QUANTITY 0 100 75 50 25 0 25 50 INPUT OFFSET VOLTAGE pV 75 100 Figure 2 Input Offset Voltage Distribution N eo 0 100 75 50 25 0 25 50 INPUT OFFSET VOLTAGE pV 75 100 Figure 3 Input Offset Voltage Distribution 0 125 100 75 50 25 0 25 50 75 100 125 INPUT OFFSET VOLTAGE uV Figure 4 Input Offset Voltage Distribution QUANTITY Figure 5 Input Offset Voltage Drift 300 250 M o o a o o o a eo 0 0 0 25
30. s dominant 100 FREQUENCY 1kHz T 25 C OP284 EQUIVALENT RESISTOR THERMAL NOISE ONLY EQUIVALENT THERMAL NOISE nV VHz 1k 10k 100k TOTAL SOURCE RESISTANCE Rs 2 Figure 46 OP284 Total Noise vs Source Resistance sT2 Since circuit SN R isthe critical parameter in the final analysis many times the noise behavior of a circuit is expressed in terms of its noise figure NF Noise figure is defined to bethe ratio of a circuit s output signal to noise to its input signal to noise An expression for a circuit s NF in dB and in terms of the opera tional amplifier s voltage and current noise parameters defined previously is given by NF dB 10 log Goal op 23 lass T where NF dB Noise figure of the circuit expressed in dB Rs Effective or equivalent source resistance presented to amplifier eoa OP284 noise voltage spectral power 1 Hz BW inoa OP284 noise current spectral power 1 Hz BW eps Source resistance thermal noise voltage power 4kT Rs Circuit noise figure is straightforward to calculate because the signal level in the application is not required to determine it H owever many designers using NF calculations as the basis for achieving optimum SNR believe that low noise figure is equal to low total noise In fact the opposite is true as illustrated in Figure 47 Here the noise figure of the OP284 is expressed as
31. se in one device It is the first device in the industry to exhibit an input noise voltage spectral density of less than 4 nV NHz at 1 kHz It was also designed specifically for low noise single supply applications and as such some discussion on circuit noise concepts in single supply applications is appropriate 11 0P184 0P284 0P464 Referring to the op amp noise model circuit configuration illus trated in Figure 45 the expression for an amplifier s total equivalent input noise voltage for a source resistance level Rs is given by er 42 amp inoa XR ans J units in VHZ where Rs 2R Effective or equivalent circuit source resistance amp o4 Op amp equivalent input noise voltage spectral power 1HzBW inoa Op amp equivalent input noise current spectral power 1 Hz BW er Source resistance thermal noise voltage power 4kT R k Boltzmann s constant 1 38 x 107 J K and T Ambient temperature of the circuit in K elvin 273 15 T4 C R eNR eNOA NOISELESS NOISELESS OP AMP Rg 2R NOISELESS Figure 45 Op Amp Noise Circuit Model Used to Determine Total Circuit Equivalent Input Noise Voltage and Noise Figure As a design aid Figure 46 illustrates the total equivalent input noise of the OP284 and the total thermal noise of a resistor for comparison N ote that for source resistance less than 1 kQ the equivalent input noise voltage of the OP284 i
32. second gain stage U nder output short circuit conditions this input current level is approximately 100 uA With transistor current gains around 200 the short circuit current limits are typically 20 mA The output stage also exhibits voltage gain T his is accomplished by use of common emitter amplifiers and as a result the voltage gain of the output stage thus the open loop gain of the device exhibits a dependence to the total load resistance at the output of the OP284 Input Overvoltage Protection As with any semiconductor device if conditions exist where the applied input voltages to the device exceed either supply voltage then the device s input overvoltage l V characteristic must be considered When an overvoltage occurs the amplifier could be damaged depending on the magnitude of the applied voltage and the magnitude of the fault current Figure 43 illustrates the over voltage I V characteristic of the O P284 T his graph was generated with the supply pins connected to GN D and a curve tracer s collector output drive connected to the input INPUT CURRENT mA 5 4 3 2 1 0 1 2 3 4 5 INPUT VOLTAGE Volts Figure 43 Input Overvoltage l V Characteristics of the OP284 As shown in the figure internal p n junctions to the OP284 en ergize and permit current flow from the inputs to the supplies when the input is 1 8 V more positive and 0 6 V more negative than the respective supply rails As illustrated in the simplified
33. sign approach the input bias currents in the OP284 not only exhibit different amplitudes but also exhibit different polarities T his effect is best illustrated in Figure 8 It is therefore of para mount importance that the effective source impedances con nected to the OP284 s inputs be balanced for optimum dc and ac performance In order to achieve rail to rail output the O P284 output stage design employs a unique topology for both sourcing and sinking current T his circuit topology is illustrated in Figure 42 As previously mentioned the output stage is voltage driven from the second gain stage T he signal path through the output stage is inverting that is for positive input signals Q1 provides the base current drive to Q6 so that it conducts sinks current For negative input signals the signal path via Q1 Q2 D 1 Q4 Q3 provides the base current drive for Q5 to conduct source cur rent Both amplifiers provide output current until they are forced into saturation which occurs at approximately 20 mV from negative rail and 100 mV from the positive supply rail Vpos INPUT FROM SECOND GAIN STAGE Vout VNEG Figure 42 OP284 Equivalent Output Circuit REV 0 OP184 0P284 0P484 R2 T hus the saturation voltage of the output transistors sets the limit on the OP284 s maximum output voltage swing Output short circuit current limiting is determined by the maximum signal current into the base of Q1 from the
34. single supply opera tion exhibit an output voltage phase reversal when their inputs are driven beyond their useful common mode range T ypically for single supply bipolar op amps the negative supply deter mines the lower limit of their common mode range With these devices external clamping diodes with the anode connected to ground and the cathode to the inputs prevent input signal ex cursions from exceeding the devices negative supply i e GND preventing a condition that could cause the output volt age to change phase JFET input amplifiers may also exhibit phase reversal and if so a series input resistor is usually re quired to prevent it T he OP284 is free from reasonable input voltage range restric tions provided that the input voltages no greater than the supply voltages are applied Although the device s output will not change phase large currents can flow through the input protec tion diodes as was shown in Figure 43 T herefore the technique recommended in the Input Overvoltage Protection section should be applied in those applications where the likelihood of input voltages exceeding the supply voltages is high Designing Low Noise Circuits in Single Supply Applications In single supply applications devices like the OP 284 extend the dynamic range of the application through the use of rail to rail operation In fact the OP284 family isthe first of its kind to combine single supply rail to rail operation and low noi
35. urrent level was about 30 mV The current limit as shown is 400 mA which allows the circuit to be used at levels up to 300 mA or more While the Q1 device can actually support currents of several amperes a practical current rating takes into account the SO 8 device s 2 5 W 25 C dissipation A short circuit current of 400 mA at an input level of 5 V will cause a 2 W dissipation in Q1 so other input conditions should be considered carefully in terms of Q1 s potential overheating Of course if higher powered devices are used for Q1 this circuit can support outputs of tens of amperes as well as the higher Vout levels noted above T he circuit shown can be used either as a standard low dropout regulator or it can also be used with ON OFF control By driving Pin 3 of U1 with the optional logic control signal V the output is switched between ON and OFF Note that when the output is OFF in this circuit it is still active i e not an open cir cuit This is because the OFF state simply reduces the voltage input to R1 leaving the U 1A B amplifiers and Q1 still active When ON OFF control is used resistor R10 should be used with U 1 to speed ON OFF switching and to allow the output of the circuit to settle to a nominal zero voltage Components D3 and R11 also aid in speeding up the ON OFF transition by providing a dynamic discharge path for C2 OFF ON transition time is less than 1 ms while the ON OFF transition is longer but und
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ANALOG DEVICES OP184/OP284/OP484 handbook