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ST ST802RT1A ST802RT1B handbook

1. Table 6 CFGO CFG1 configuration mii cfgO mii cfg1 MII mode 0 X RMII mode 1 0 Reserved 1 1 Table 7 Auto negotiation advertisement register Forced mode an en an 0 an 1 10M Half duplex 0 0 0 10M Full duplex 0 0 1 100M Half duplex 0 1 0 100M Full duplex 0 1 1 Advertised mode an en 0 1 10M Half full duplex 1 0 0 100M Half full duplex 1 0 1 10M Half duplex 1 1 0 100M Half duplex 10M Half Full duplex 1 1 1 100M Half Full duplex 16 58 Doc ID 17049 Rev 1 ST802RT1A ST802RT1B Registers and descriptors description 6 Registers and descriptors description All of the management data control and status registers in the ST802RT1x s register set are accessed via a Write or Read operation on the serial MDIO port This access requires a protocol described in the management interface section 6 1 Register list Table 8 List of registers Address Scd Name d Register description 00h Od RNOO CNTRL 0 0000 Control register 01h 1d RNO1 STATS 0x7849 Status register 02h 2d RNO2 PHYID1 0 0203 identifier register Hi 03h RNO3 PHYID2 0x8461 PHY identifier register Lo 04h 4d RNO4 LDADV OXOSE1 Auto negotiation advertisement register 05h 5d RNO5S LPADV 0 0000 Auto negotiation link partner ability register
2. 16 AR OE ER pe a Say a 17 Abbreviations Rx X RUE Dee EE eee 18 RNOO 0d00 0x00 Control register eens 18 RNO1 0d01 0x01 Status register 0 0 eens 21 RNO2 0d02 0x02 PHY identifier register Hi 22 RNO3 0d03 0x03 PHY identifier register Lo 22 RNO4 0d04 0x04 Auto negotiation advertisement 23 RNO5 0d05 0x05 Auto negotiation link partner ability register 24 RNO6 0d06 0x06 Auto negotiation expansion 25 RNO7 0d07 0x07 Auto negotiation next page transmit register 26 RNO8 0d08 0x08 Auto negotiation link partner received next page register 26 RN10 0d16 0x10 RMII TEST control 27 RN11 0d17 0x11 Receiver configuration information and interrupt status register 28 12 0d18 0x12 Receiver event interrupts 29 RN13 0d19 0x13 100Base TX control 30 RN14 0d20 0x14 Receiver mode control 30 RN18 0d24 0x18 Auxiliary control 31 RN19 0d25
3. ST802RT1A ST802RT1B 10 100 real time Ethernet 3 3 V transceiver Features m IEEE802 3 10Base T and IEEE802 3u 100Base TX 100Base FX ST802RT1B only transceiver m Support for IEEE802 3x flow control m Provides full duplex operation in both 100 Mbps and 10 Mbps modes Register bit strap during HW reset Auto MDI X for 10 100 Mb s Auto negotiation Provides loop back mode for diagnostics Programmable LED display for operating mode and functionality signaling m MII interface m serial management interface m Optimized deterministic latency for real time Ethernet operation m Supports external transformer with turn ratio 1 414 1 on Tx Rx side m Self termination transceiver for external components and power saving Operation from single 3 3 V supply High ESD tolerance 48 pin LQFP 7 x 7 package Extended temp range 40 C to 105 C Power dissipation 315 mW typ Applications m industrial control m Factory automation m High end peripherals LOFP48 m Building automation m Telecom infrastructure Description The ST802RT1x is a high performance fast Ethernet physical layer interface for 10Base T 100Base TX and 100Base FX applications It is designed using advanced CMOS technology to provide MII and RMII interfaces for easy attachment to 10 100 media access controllers MAC The ST802RT1x supports the 100Base TX of IEEE802 3u and 10Base T of IEEE802 3
4. Duplex Fixed to 1 10 RESERVED used 0 RO P 9 RESERVED used 0 RO P 8 RESERVED used 0 RO P 7 RESERVED used 0 RO P 1 Accepts management frames with preamble suppressed MF Preamble 6 Suppression 0 gt Doesn t accept management frames without preamble 1 RO PP Controlled by RN14 1 Auto 1 gt Auto negotiation process completed registers 4 5 6 are now valid ja A 0 gt Auto negotiation process not completed 9 PE P Active only if auto negotiation is enabled else 0 1 Remote fault condition detected 0 gt No remote fault condition detected Set when link partner signals a remote fault condition 5 bit 4 Remote Fault 13 or a far end fault indicator was asserted Latched so the 0 RO LH occurrence of a remote fault causes the remote fault bit to become set and remain set until it is cleared by register read if no more fault is present AUO 1 gt PHY is able to perform auto negotiation 3 Negotiation P 9 1 RO P s Fixed to 1 Ability 1 Link is valid and established either for 10 and 100 Mb s 0 gt Link is down Link Status This bit is cleared at link failure and set after a register read if a 9 RO HE valid link is established 1 Jabber condition detected transmission exceeded max number of bytes gt iti tected 1 Jabber 0 gt dd cona ion de id ed 0 RO LH Set at jabber condition detection cleared only after register read if no
5. HW PROG PINS i TXP TXN RXP RXN LEDS 5 Doc ID 17049 Rev 1 7 58 System and block diagrams ST802RT1A ST802RT1B 3 System and block diagrams Figure 2 System diagram of the ST802RT1A B ETHERNET ST802RT1 MAC RJ 45 Transformer Figure 3 System diagram of the ST802RT1B in FX mode EE amon MAC 8 58 Doc ID 17049 Rev 1 ky ST802RT1A ST802RT1B Pin configuration 4 Pin configuration Figure 4 Pin configuration ST802RT1A DOT o t ew c rc o Ooonon a lt lt lt lt lt gt gt gt gt rt gt gt EEUE ESE Cozy 2010200 C9 ocqononmgct5ogo Z Q x 2 x coommcmopmnontutoscst E id 40 g 7 TX CLK LPBK EN TXD2 SCLK TXD3 MII CFG1 PWRDWN MDINT 9 RESERVED RESERVED GND ST802RT1A LED_LINK AN_EN LED_SPEED ANO LED_ACT AN1 RESERVED RXP GNDA TXN GNDA IREF VCCA Doc ID 17049 Rev 1 9 58 Pin configuration ST802RT1A ST802RT1B Figure 5 Pin configuration ST802RT1B WE O C n CY N A Qaaqaaa e lt lt lt lt o lt gt gt gt gt gt GE g x 2qoontt DZ gt XE gt
6. 17 6 2 Register description 18 7 Device operation 38 7 1 100Base TX transmit operation 38 7 2 100Base TX receive operation 39 7 3 10Base T transmit operation 40 7 4 10Base T receive operation 40 7 5 Loop back 40 7 6 Full duplex and half duplex operation 40 7 7 Auto negotiation operation 40 7 8 Power down interrupt 41 7 9 Power down operation 41 7 10 1 41 7 11 LED display operation 42 7 12 Reset operation 43 7 13 Preamble suppression 43 71 Remote TP 43 7 15 Transmit isolation 44 2 58 Doc ID 17049 Rev 1 ky ST802RT1A ST802RT1B Contents 10 7 16 Automatic MDI MDIX feature 44 7 17 RMII interface 44 7 18 45 7 19 FX ope
7. RNO6 ANEGX 0x0004 Auto negotiation expansion register 07h 7d RNO7 LDNPG 0 2001 Auto negotiation next page transmit register 08h 8d RNO8 LPNPG 0 0000 Auto negotiation link partner received next page register Extended registers 16d RN10 XCNTL 0x1200 RMII TEST control register 11h 17d RN11 XSTAT 0 0000 Receiver configuration information and interrupt status register 12h 18d RN12 XRCNT 0 0100 Receiver event interrupts register 13h 19d RN13 XCCNT 0 0140 100Base TX control register 14h 20d RN14 XDCNT OXOOOA Receiver mode control register 18h 24d RN18 AUXCS 0 0027 Auxiliary control register 19h 25d RN19 AUXSS 0 0000 Auxiliary status register 1Bh 27d RN1B AUXM2 OXOOOA Auxiliary mode 2 register 1Ch 28d RN1C TSTAT 0 0820 10 error and general status register 1Eh 30d RN1E AMPHY 0 0000 Auxiliary PHY register Shadow registers 1Fh 31d RN1F BTEST 0 0000 Shadow Registers enable register 1Bh 27d RS1B AUXS2 0 0000 MISC status error test shadow register ky Doc ID 17049 Rev 1 17 58 Registers and descriptors description ST802RT1A ST802RT1B 6 2 Register description Table 9 Abbreviations Legend Description RW Read write RO Read only SC Self clearing P Constant STRAP Bit with strap value LH Latched high LL Latched low Table 10 RNOO 0d00 0x00 Control register Bit Bit name Descri
8. Interrupt enabled 0 Interrupt disabled RW LK DWN EN DET LINK FAIL INTERRUPT ENABLE 1 Interrupt enabled 0 gt Interrupt disabled AUTO NEGOTIATION LCW RECEIVED INTERRUPT ENABLE 1 Interrupt enabled 0 Interrupt disabled RW RW PD FLT EN PARALLEL DETECTION FAULT INTERRUPT ENABLE 1 Interrupt enabled 0 Interrupt disabled RW PG RCVD EN RX FULL EN AUTO NEGOTIATION PAGE RECEIVED INTERRUPT ENABLE 1 Interrupt enabled 0 Interrupt disabled RECEIVE ERROR COUNTER FULL INTERRUPT ENABLE 1 gt Interrupt enabled 0 gt Interrupt disabled RW RW Doc ID 17049 Rev 1 29 58 Registers and descriptors description ST802RT1A ST802RT1B Table 22 RN13 0d19 0x13 100Base TX control register Bit Bit name Description Default HW Type P Type yp 15 14 RESERVED 006 RO P Disable RX err 1 RX error counter disabled 13 0 RW counter 0 gt Normal operation 1 Auto negotiation complete _ 12 Auto Neg Complete 0 gt Auto negotiation not completed 0 RO 11 9 RESERVED 000b RW 8 Enable DC rest 1 gt Baseline wander enabled DC restoration enabled 1 BW _ Baseline wander 0 gt Baseline wander disabled Enable NRZI to 1 gt nrz lt gt nrzi conversion enabled 7 1 RW NRZ
9. ON for 100Mb OFF for 10Mb LED act col ON for full duplex BLINK for collision BLINK for activity e Link LED On when 100 M or 10 M link is active It also blinks at 10 Hz for transmit and receive e Speed LED 100 Mbps on or 10 Mbps off Activity LED Blinks at 20 Hz when there is a half duplex activity on the media It is driven on continuously if full duplex configuration is detected or blinks when a collision is detected LED connections PIN Logic Level 0 1 VORIN Logic Level 1 42 58 Doc ID 17049 Rev 1 ST802RT1A ST802RT1B Device operation 7 12 7 13 7 14 Reset operation There are two ways to reset the ST802RT1x Hardware reset the ST802RT1x can be reset via the RESET pin pin 29 The active low reset input signal is required for at least 1 ms and at least one transition is required on the MDC pin 31 to ensure proper reset operation Software reset when bit 15 of register RNOO is set to 1 the ST802RT1x resets all the circuits and registers to their default values then clears bit 15 of RNOO to 0 Both hardware and software reset operations initialize all registers to their default values This process includes re evaluation of all hardware configurable registers Logic levels on several VO pins are detected during the hardware reset period to determine the initial functionality
10. Symbol Parameter Test conditions Min Typ Max Unit General DC Voc Supply voltage 3 15 3 3 3 45 V IDDQA Quiescent current analog 1 5 mA IDDQD Quiescent current digital 4 5 mA VIH Input high voltage 1 95 V VIL Input low voltage 0 85 V 10Base T voltage current characteristics Vida10 Input differential accept peak voltage 5MHz 10MHz 585 3100 mV Input differential reject peak voltage 5MHz 10MHz 0 585 mV Vod10 Output differential peak voltage 2200 2800 mV Link active transmitting 10096 Idd10 Digital current consumption receiving 100 18 mA 1 H itti 199 10 Analog current consumption Lirik active transmitting 100 77 mA receiving 100 100Base TX voltage current characteristics Vida100 Input differential accept peak voltage 200 1000 mV Vidr10O Input differential reject peak voltage 0 200 mV Vod100 Output differential peak voltage 950 1050 mV 1 H itti Idd100 Digital current consumption Link active transmitting 1007 25 mA receiving 100 i j itti IddA100 Analog current consumption Link active ra naQ 100 70 mA receiving 100 Ly Doc ID 17049 Rev 1 49 58 Electrical specifications and timings ST802RT1A ST802RT1B Table 35 General DC specification continued Symbol Parameter Tes
11. Updated by auto negotiation state machines Message It can be a message code annex 28C IEEE 802 3u or 00000000 10 0 Unformatted RW an unformatted code according to value set in RNO7 13 001b Code Field Next page Indicates whether this is the last next page to be transmitted Msg page Differentiates a message page from an unformatted page Ack2 Indicates that a device has the ability to comply with the message Toggle Used by the arbitration function to ensure synchronization with the link partner during next page exchange Message code field An eleven bit wide field encoding 2048 possible messages Unformatted code field An 11 bit wide field which may contain an arbitrary value Table 18 RNO8 0d08 0x08 Auto negotiation link partner received next page register 0 RW Bit Bit name Description Default Type type 1 gt LP desires next page transfer 13 Next Page 0 gt LP has no more Next Pages 0 RO 14 Acknowledge 1 gt LP acknowledges reception of the ability data word 0 RO 0 gt acknowledged 1 LP message page transmitting 1 19 Message Page 0 gt LP unformatted page transmitting RO 12 Acknowledge 2 1 gt LP will comply with message received 0 RO 0 gt LP cannot comply with message 1 gt Previous transmitted LP LCW toggle was 0 _ t Toggle 0 gt Previous transmitted LP LCW toggle was 1 0 10 0 a de It can be a message code annex 28C IEEE 802 3u or 0000000 RO Field a
12. 0x19 Auxiliary status 31 RN1B 0d27 Ox1B Auxiliary mode 2 33 RN1C 0d28 1 10Base T error and general status 34 RN1E 0d30 0x1E Auxiliary PHY 35 RN1F 0d31 Ox1F Shadow registers enable 36 RS1B 0427 0x1B Misc status error test shadow 37 LED Configuration ke ea EER ex ER RE Rer EROR E RR 42 Configuration of signal detect voltage levels 46 Management frame 48 Absolute maximum 5 49 General DC specification liiis 49 LOFP48 mechanical EE EE tee 54 Document revision history 57 Doc ID 17049 Rev 1 ky ST802RT1A ST802RT1B List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 ST802RT1x block 7 System diagram of the ST802RT1A B 8 Syst
13. 1 Next t f t 15 Next Page gt Next page transfer supported 0 RW _ 0 gt Next page transfer not supported 14 RESERVED 0 P 1 Advertises that this device has detected a remote fault 13 Remote Fault during auto negotiation 0 RW 0 gt No remote fault detected 12 RESERVED 0 11 peius 1 Asymmetric pause supported MAC level 0 RW 0 gt No MAC based full duplex flow control duplex 10 Pause full 1 gt Symmetric pause supported MAC level 1 RW duplex 0 gt No MAC based full duplex flow control 9 100BASE T4 0 gt 100BASE T4 not supported 0 RW 8 100BASE TX 1 gt 100BASE TX Full duplex is supported by the local device Stra RW _ full duplex 0 gt 100BASE TX Full duplex is not supported P 1 gt 100BASE TX is supported by the local device _ TOBBASESIN 0 gt 100BASE TX is not supported Strap FUN 6 10BASE T full 1 gt 10BASE T Full duplex is supported by the local device Stra RW 0 gt 10BASE T Full duplex is not supported P 1 gt is supported by the local device _ TOBASE T 0 gt 10BASE T is not supported Strap PM 4 0 Selector 00001 gt IEEE802 3u 00001b RW Next page The ST802RT1x supports next page capability Reserved Ignore output when read Remote fault Writing a 1 to bit 13 of the advertisement register causes a remote fault indicator to be sent to the link partner during auto negotiation Writing a O to this bit
14. CLK LPBK EN VCCA TXDO xox ST8S02RT1B TXD3 MII CFG1 8 PWRDWN MDINT 9 RESERVED RESERVED RXDV MII CFGO 8 RX CLK DVDD X1 x2 GND OVDD MDC MDIO RESET LED EN LED SPEED ANO LED ACT AN1 SDP lt lt lt lt lt lt QUE x doc wg Om cC ZHEZZAEOZO gt gt gt 10 58 Doc ID 17049 Rev 1 ki ST802RT1A ST802RT1B Pin description 5 Pin description Table 2 Pin description of the ST802RT1x 1x Name Type Description 1 TX_CLK LPBK_EN O S PD transmit clock 2 TX EN 1 PD MII transmit enable 3 GNDA Ground Analog ground 4 VCCA Supply Analog power supply 5 TXDO Transmit data MII RMII 6 TXD1 Transmit data MII RMII 7 TXD2 SCLK Transmit data MID RMII clock 50 Mhz 8 TXD3 MIl_CFG1 1 S PD Transmit data MIl multi function pin 9 PWRDWN MDINT 1 PU OD Power down management data interrupt 10 RESERVED I PD To be set to digital ground 11 RESERVED PD To be set to digital ground 12 GND Ground Digital ground 13 VCCA Supply Analog power supply 14 RXN Differential receive inputs 15 RXP 50 Differential receive inputs 16 GNDA Ground Analog ground 17 TXP Differential transmit outputs 18 TXN LO Differential transmit outputs 19 GNDA Ground Analog ground 20 GNDA Ground Analog ground 21 IREF VO Reference resistor DC r
15. Link code word received updated on read 0 gt LCW not yet received RO LH Link Partner Auto Negotiation Able 1 gt LP supports auto negotiation updated on read 0 gt LP does not support auto negotiation RO SP100 indicate Link Status 1 gt Speed is 100 Mb s 0 gt Speed is 10 Mb s 1 gt Link is up 10 100 Mb s 0 gt Link is down This bit is cleared at link failure and set after a register read if a valid link is established RO Set by auto negotiation 100BASE TX link control RO LL Auto negotiation enable 1 Auto negotiation enabled 0 gt Auto negotiation disabled Set by RNOO 12 if RN11 10 is O not FX mode RO 32 58 Jabber Detect 1 Jabber condition detected 0 gt No jabber condition detected Set at jabber condition detection cleared only after register read if no more jabber condition is present Fixed to 0 in 100Base X modes Doc ID 17049 Rev 1 RO Same as RNO1 1 LH ST802RT1A ST802RT1B Registers and descriptors description Table 26 RN1B 0d27 0x1B Auxiliary mode 2 register Bit Bit name Description Default RW Type p Type yp 15 12 RESERVED 0000b RO 11 10 RESERVED 006 RW 1 gt led link pad ON for link up BLINK for activity led speed pad ON for 100 Mb OFF for 10 Mb 9 LED Mode pad ON for full duplex BLINK for collision 0 RW led lin
16. this pin is connected to one of its terminals If an external clock source is used then this pin should be left open 17 TXP VO Differential transmit outputs 100Base TX 10Base T These pins output 18 TXN directly to the transformer When MDIX is enabled they can work as RXP RXN Signal detect ST802RT1B version only see Table 5 Connect a 100 Q resistor between TXn and VCCA and between TXp and VCCA to achieve the pseudo emitter coupled logic PECL levels for the optical 25 SDP transmitter The PECL logical low level PECL ow is approximately VCC 1 7 V 48 SDN the PECL logical middle level is approximately VCC 1 32 V and the PECL logical high level is approximately VCC 0 9 V RESERVED in ST802RT1A the pins must be grounded through a 1 2 resistor 15 RXP lO Differential receive inputs 100Base TX 10Base T These pins directly 14 RXN output to the transformer When MDIX is enabled they can work as TXP TXN 21 IREF Reference resistor DC regulator output Reference resistor connecting pin for reference current directly connect a 5 25 1 resistor to Vss Link LED In Mode 1 and Mode 2 this pin indicates the status of the link The Gi LED_LINK O PU LED is ON when the link is good Speed LED This pin is driven on continually when 10Mb s or 100Mb s network xi O PU operating speed is detected All modes gt ON 100Mb s OFF 10Mb s Activity collision LED This pin is driven on continu
17. 0 gt nrz nrzi conversion disabled 6 RESERVED 1 RW 5 Transmit Isolation 1 ee and TX 0 RW 0 gt Normal operation 000 gt Auto negotiation running 001 gt 10Base T half duplex 010 gt 100Base TX half duplex 011 gt Not used 4 2 CMode 100 gt Not used 000b RO 101 gt 10Base T full duplex 110 gt 100Base TX full duplex 111 Transmit isolation 1 MLT3 encoder and decoder disabled METS Disablg 0 gt MLT3 encoder and decoder enabled 9 1 gt scrambler and descrambler disabled Scrambler 0 gt scrambler and descrambler enabled 0 Descrambler 7 0 RW Scrambling descrambling are always disabled if Disable EDAM operating in FX mode Table 23 RN14 0d20 0x14 Receiver mode control register Bit Bit name Description Default FW Type 15 12 RESERVED 0000b RO P 11 RESERVED 0 RW 10 8 RESERVED 000b RO P 7 3 PHY ADDR Physical address management Strap RW 2 RESERVED 0 RO P 1 Accepts management frames with preamble Preamble suppressed 1 1 RW suppression 0 gt Doesn t accept management frames without preamble 0 RESERVED 0 RO P 30 58 Doc ID 17049 Rev 1 ST802RT1A ST802RT1B Registers and descriptors description Table 24 RN18 0d24 0x18 Auxiliary control register Bit Bit name Description Default RW Type p Type yp 15
18. Jabber disable 1 gt Disables jabber detection 10BaseT 0 RW 0 gt Normal operation 14 RESERVED 0 RW 13 8 RESERVED 000000b RO P 7 5 RESERVED 001b RW Power 1 gt Stops MDC clock when interface is idle 4 0 RW Saving 0 gt Normal operation 3 0 RESERVED 0111b RO Jabber disable 10BASE T operation only Bit 15 of the auxiliary control register allows the user to disable the jabber detect function defined in the IEEE standard This function shuts off the transmitter when a transmission request has exceeded a maximum time limit By writing a 1 to bit 15 of the auxiliary control register the jabber detect function is disabled Writing a O to this bit or resetting the chip restores normal operation Reading this bit returns the value of jabber detect disable power saving to reduce power consumption set this bit to 1 Table 25 RN19 0425 0x19 Auxiliary status register Bit Bit name Description Default EN Type P 1 Auto negotiation process completed Auto Negotiation 0 gt Auto negotiation process not completed 15 0 RO complete Active only if auto negotiation is enabled else 0 Same as RNO1 5 14 Auto negotiation 1 gt Auto negotiation completed ack state 0 RO LH ack 0 gt Auto negotiation did not complete ack state Auto negotiation 1 gt Auto negotiation entered ack state ack match completed 13 0 RO LH detect 0 gt Acknowled
19. MHz is converted to serial bit stream at 125 MHz by the parallel to serial function After being serialized the transmission serial bit stream is further converted from NRZ to NRZI format This NRZI conversion function can be bypassed if bit 7 of the RN13 register is cleared as 0 After being NRZI converted the NRZI bit stream is passed through the MLT3 encoder to generate the TP PMD specified MLT3 code The MLT3 code lowers the frequency and reduces the energy of the transmission signal in the UTP cable and also allows the system to meet the FCC specification for EMI Doc ID 17049 Rev 1 ST802RT1A ST802RT1B Device operation 7 2 Wave shaper and media signal driver In order to reduce the energy of the harmonic frequency of transmission signals the device provides the wave shaper prior to the line driver to smooth out but maintain symmetric the rising falling edge of the transmission signals The wave shaped signals include the 100Base TX and 10Base T and both are passed to the same media signal driver 100Base TX receive operation In the 100Base TX receiving operation the device provides the receiving functions of the PMD PMA and PCS for receiving incoming data signals through a category 5 UTP cable and an isolation transformer with a 1 414 1 turn ratio It includes the adaptive equalizer and baseline wander data conversions of to NRZI NRZI to NRZ and serial to parallel the PLL for clock and data recovery the
20. N in the RN12 register disables the PWRDWN MDINT input allowing the device to exit the power down state Interrupt mechanisms The interrupt function is controlled via register access All interrupt sources are disabled by default Setting bit 7 INT EN of RN12 0x12h enables interrupts to be output based on the interrupt mask set in the lower byte of RN12 0x12h The PWRDWN MDINT pin is asynchronously asserted low when an interrupt condition occurs The source of the interrupt can be determined by reading the lower byte of RN11 0x11h One or more bits in the RN11 is set denoting all currently pending interrupts Example To generate an interrupt on a change of link status the steps would be Doc ID 17049 Rev 1 41 58 Device operation ST802RT1A ST802RT1B 7 11 Table 31 Write 0180h to RN12 to set INT_EN and INT_OE_N Write 0010h to RN12 to set LK_DWN_EN Monitor PWRDWN MDINT When the PWRDWN MDINT pin asserts low the user should read the RN11 register to see if the LK_DWN is set i e which source caused the interrupt LED display operation The ST802RT1x provides 3 LED pins Table 37 contains a detailed description of the operating modes also described in Table 4 Pin functions of the ST802RT 1x LED configuration Mode Figure 6 RN1B 9 LED link ON for link up OFF for no link BLINK for link up activity ON for link up OFF for no link LED speed ON for 100Mb OFF for 10Mb
21. _ TE BeBe pee 0 gt AN 10Base T half duplex not selected 9 10 9 RESERVED 00b RO P 1 gt Restarts auto negotiation process ignored if auto negotiation is disabled 8 Auto De e 0 gt Normal operation 0 RW SC Self cleared after 21 MHz clock periods auto negotiation is started Same as RNOO CNTRL 9 1 Auto negotiation process completed Auto Negotiation 0 gt Auto negotiation process not completed 7 AME 0 RO complete Active only if auto negotiation is enabled else 0 Same as 19 AUXSS 15 and RNO1 STATS 5 Auto Negotiation 1 AN ack completed 6 Acknowledde 0 gt AN ack not yet completed 0 RO 9 Held high until tx is disabled or auto negotiation is Complete restarted 1 gt AN first ack received 5 Auto Negotiation 0 gt AN first ack not yet received 0 RO Acknowledge Held high until tx is disabled or auto negotiation is restarted Auto Negotiation 1 gt Auto negotiation in ability detect state 4 0 gt Auto negotiation not in ability detect state 0 RO y Same as RN19 AUXSS 12 SUPER ISOLATE 1 gt and RX isolated 0 gt Normal operation Super Isolate All MII inputs are ignored all MII outputs are tri stated no RW link pulses generated Same effect setting to 1 both RNOO 10 and RN13 5 2 RESERVED 0 RO P 1 0 RESERVED 00b RW ky Doc ID 17049 Rev 1 35 58 Registers and descriptors description ST802RT1A ST802RT1B HCD 10BaseT Bits 15 11 of the auxi
22. de scrambler and the decoder for 5B 4B Adaptive equalizer and baseline wander the high speed signals over the unshielded or shielded twisted pair cable induces amplitude attenuation and phase shifting Furthermore these effects depend on the signal frequency cable type cable length and the connectors of the cabling So a reliable adaptive equalizer and baseline wander to compensate for all the amplitude attenuation and phase shifting are necessary The transceiver provides robust circuits to perform these functions MLT3 to NRZI decoder and PLL for data recovery after receiving the proper MLT3 signals the device converts the MLT3 to NRZI code for further processing The compensated NRZI signals at 125 MHz are then passed to the phase lock loop circuits to extract the original data and synchronous clock Data conversions of NRZI data to NRZ and serial to parallel after data is recovered the signals are passed to the NRZI to NRZ converter to generate the 125 MHz serial bit stream This serial bit stream is packed to parallel 5B type for further processing The NRZI to NRZ conversion can be bypassed by clearing bit 7 of the RN13 register to O De scrambling and decoding of 5B 4B The parallel 5B type data is passed to the descrambler and 5B 4B decoder to extract the original nibble data Carrier sensing the carrier sense CRS signal is asserted when the ST802RT1x detects any 2 non contiguous zeros within any 10 bit boundary of the
23. loop back mode otherwise it returns a Speed selection If auto negotiation is enabled this bit has no effect on the speed selection However if auto negotiation is disabled by software control the operating speed of the ST802RT 1x can be forced by writing the appropriate value to bit 13 of the control register Writing a 1 to this bit forces 100BASETX operation while writing a 0 forces 10BASE T operation When this bit is read it returns the value of the software controlled forced speed selection only Auto negotiation enable Auto negotiation can be disabled by one of two methods hardware or software control If the EN input pin is driven to 0 auto negotiation is disabled by hardware control If bit 12 of the control register is written with a value of O auto negotiation is disabled by software control When auto negotiation is disabled in this manner writing a 1 to the same bit of the control register re enables auto negotiation If auto negotiation is disabled in this manner and the chip is reset the auto negotiation follows the strap configuration Writing to this bit has no effect when auto negotiation has been disabled by hardware control When read this bit returns the value most recently written to this location or 1 if it has not been written since the last chip reset Power down If set to 1 the channel is powered down If this bit is set for all channels then the IO pad directions ar
24. mode is automatically selected whenever a valid differential signal is detected at the SD and SD inputs when 50 and SD are tied low or left unconnected the respective PHY is forced in base T mode The data flow for 100BASE FX is Serialized data gt NRZI encoding gt multimode DAC gt PECL format To allow the detection of remote fault conditions in 100BASE FX the IEEE 802 3 standard far end fault is implemented as in the IEEE 802 3u standard Clause 24 24 3 2 1 by default FEF is on When FEF is on a PHY transmits a FEF indication whenever a receive channel failure is detected and also the PHY continuously monitors the receive channel when a valid signal is present When its link partner is indicating a remote error the PHY forces its link monitor into the link fail state setting the remote fault bit in the status register RNO1 In 100BASE FX mode there is no scrambling function and the data is only NRZI encoded the multimode DAC drives the PECL levels to an external fiber optic transmitter When there is no transmission the device generates IDLE symbols FX operation detect circuit This circuit decodes the information on the status of the optical link Particularly in the ANSI specification it is stated that the signal detect indicates the presence of the optical signal with sufficient quality to correctly identify a line state Both signals tied to ground No FX mode required SD gt SD gt FX mode is asser
25. of the ST802RT1x Some of these pins are used as outputs after the reset operation Care must be taken to ensure that the configuration setup does not interfere with normal operation Strap pins multiplexed with LED outputs should be weakly pulled up or weakly pulled down through resistors as shown in Figure 6 Preamble suppression Preamble suppression mode in the ST802RT1x is indicated by 1 in bit six of the RNO1 register and controlled by bit 1 in the RN14 register If it is determined that all PHY devices in the system support preamble suppression then a preamble is not necessary for each management transaction The first transaction following power up hardware reset requires 32 bits of preamble The full 32 bit preamble is not required for each additional transaction The ST802RT1x responds to management accesses without preamble but a minimum of one idle bit between management transactions is required as specified in IEEE 802 3u Remote fault The remote fault function indicates to a link partner that a fault condition has occurred by using the remote fault bit which is encoded in bit 13 of the link code word A local device indicates to its link partner that it has found a fault by setting the remote fault bit in the auto negotiation register to logic one and renegotiating with the link partner The remote fault bit remains at logic one until successful negotiation with the link code word occurs The bit then returns to 0 When the mess
26. or resetting the chip clears the remote fault transmission bit This bit returns the value last written to it or else O if no write has been completed since the last chip reset Asymmetric pause write 1 if asymmetric pause is supported by MAC when full duplex link is available 1 Advertise that the DTE MAC has implemented both the optional MAC control sub layer and the pause function as specified in clause 31 and annex 31B of 802 3u 0 No MAC based full duplex flow control Pause The use of this bit is independent of the negotiated data rate medium or link technology The setting of this bit indicates the availability of additional DTE capability when full duplex operation is in use This bit is used by one MAC to communicate symmetric pause capability to its link partner and has no effect on PHY operation Advertisement bits Bits 9 5 of the advertisement register allow the user to customize the ability information transmitted to the link partner The default value for each bit reflects the abilities of the ST802RT1x By writing a 1 to any of the bits the corresponding ability is transmitted to the link partner Writing a to any bit causes the corresponding ability to be Doc ID 17049 Rev 1 23 58 Registers and descriptors description ST802RT1A ST802RT1B suppressed from transmission Resetting the chip restores the default bit values Reading the register returns the values last written to the correspondi
27. 00BASE TX full duplex 0 RO full duplex O gt LP does not support 100BASE TX full duplex T 1 gt LP supports 100BASE TX _ f TOUBASESTAS 0 gt LP does not support 100BASE TX 9 i 6 10BASE T full 1 gt LP supports 10BASE T full duplex 0 RO _ duplex 0 LP does not support 10BASE T full duplex _ 1 gt LP supports 10BASE T _ TOBASE T 0 gt LP does not support 10BASE T 0 is 4 0 LP s binary encoded protocol selector 00000b RO LP next page Bit 15 of the link partner ability register returns a value of 1 when the link partner implements the next page function and has next page information that it wants to transmit LP ack Bit 14 of the link partner ability register is used by auto negotiation to indicate that a device has successfully received its link partner s link code word LP remote fault Bit 13 of the link partner ability register returns a value of 1 when the link partner signals that a remote fault has occurred The ST802RT1x simply copies the value to this register and does not act upon it 24 58 Doc ID 17049 Rev 1 ky ST802RT1A ST802RT1B Registers and descriptors description Reserved Ignore when read LP pause Indicates that the link partner pause bit is set LP selector field Bits 4 0 of the link partner ability register reflect the value of the Link partner s selector field These bits are cleared any time auto negotiation is restarted or the chip is reset Advertisement bits Bits 9 5 of t
28. 5 unshielded twisted pair cable through an isolation transformer with a turn ratio of 1 414 1 Data code groups encoder In normal MII mode application the device receives nibble type 4B data via the TxDO 3 inputs of the These inputs are sampled by the device on the rising edge of Tx clk and passed to the 4B 5B encoder to generate the 5B code group used by 100Base TX Idle code groups In order to establish and maintain the clock synchronization the device needs to keep transmitting signals to the medium The device generates idle code groups for transmission when there is no data sent by the MAC Start of stream delimiter SSD J K In a transmission stream the first 16 nibbles are SFD 1 byte and MAC preamble 7 byte In order to let partner delineate the boundary of a data transmission sequence and to authenticate carrier events the device replaces the first 2 nibbles of the MAC preamble with J K code groups End of stream delimiter ESD T R In order to indicate the termination of the normal data transmissions the device inserts 2 nibbles of T R code group after the last nibble of FCS Scrambling all the encoded data including the idle SSD and ESD code groups is passed to the data scrambler to reduce the EMI and spread the power spectrum using a 10 bit scrambler seed loaded at the beginning Parallel to serial data conversion NRZ to NRZI NRZI to MLT3 after being scrambled the transmission data with 5B type at 25
29. 802RT1x uses many of the functional pins as strap options The values of these pins are sampled during reset hardware or power up and used to strap the device into specific modes of operation The ST802RT1x provides simple strap options to automatically configure some device modes with no device register configuration necessary All strap pins have a weak internal pull up or pull down If the default strap value is needed to be changed they should not be connected directly to or GND and an external 2 2 resistor should The software reset and the power down through the PD pin cannot be used to change the strap configuration 1 LPBK EN S PD Loop back enable Mode Select This strapping option pair determines the operating mode of the MAC Data Interface Default operation No pull ups enables normal 38 CFGO mode of operation Strapping cfgO high causes the device to be 8 CFG1 S PD mode of operation determined by the status of the mii cfg1 strap Since the pins include internal pull downs the default values 0 See Table 6 for details and configurations Auto negotiation enable When high this enables auto negotiation with the capability set by the an 0 and an 1 pins When low this puts the part into Forced Mode with the capability set by the an 0 and an 1 pins an 0 an 1 These input pins control the forced or advertised operating mode 28 AN EN of the ST802RT1x according t
30. CLK pin 32 of 50 MHz is used as a timing reference for all transmitters and receivers By doubling the clock frequency relative to the MII four pins are saved in the data path which uses two transmit data inputs and two receive data outputs instead of four lines for each direction in the MII interface Since start of packet and end of packet timing information is preserved across the interface the MAC is able to derive the COL signal from the receive and transmit data delimiters saving another pin 44 58 Doc ID 17049 Rev 1 ky ST802RT1A ST802RT1B Device operation 7 18 7 19 FX mode operation Each port of the ST802RT1x may also be configured for 100BASE FX transmission over fiber optics via a pseudo ECL PECL interface In 100Base Fx mode scrambling and MLT3 to binary conversion are bypassed when transmitting whereas in reception adaptive equalization binary to MLT3 and descrambling are bypassed IEEE standard auto negotiation functions are also supported unless the device operates in100Base Fx mode When operating in 100Base Fx the device supports FEF far end fault logic to communicate remote fault detection The ST802RT1x provides a pseudo ECL interface suitable for driving a fiber optic interface Fiber ports cannot be enabled by auto negotiation but only either by hardware or through the MDIO interface When 100BASE FX is enabled pins SD and SD indicate the signal quality status on the fiber optic link 100 BASE FX
31. Ground RESERVED Not used in the ST802RT1A SDN Negative signal detect 100Base FX only Table 3 Abbreviations Legend Description Input Output VO Input output S Strap option OD Open drain PD Pull down PU Pull up 12 58 Doc ID 17049 Rev 1 ST802RT1A ST802RT1B Pin description Table 4 Pin functions of the ST802RT1x Pin n Name Type Function Data interface 5 TXDO Transmit data The media access controller MAC drives data to the ST802RT1x using these inputs TED 1 90 MII RMII tx data a txd1 MII RMII tx data 8 txd2 txd3 tx data 7 SCLK RMII clock 50 Mhz 2 TX EN I PD MII transmit enable The MAC asserts this signal when it drives valid data on the txd inputs MII transmit clock Normally the ST802RT1x drives tx clk 1 TX CLK O PD 25 MHz for 100 Mbps operation 2 5 MHz for 10 Mbps operation Receive error The ST802RT1x asserts this output when it receives invalid 40 RXER symbols from the network 42 RXD3 Receive data The ST802RT1x drives received data on these outputs 43 RXD2 O PD rxdO lt MII RMII rx data 44 RXD1 rxd1 MII RMII rx data 45 RXDO rxd2 rxd3 rx data 38 RXDV O PD Receive data valid RXDV CRSDV The ST802RT1x asserts CRSDV this signal when it drives valid data on rxd MII receive clock This continuous clock provides reference for rxd rx dv and 7 RX CLK rx er signals 3 25 MHz for 100 Mbps
32. RT1A ST802RT1B Registers and descriptors description Table 10 RNOO 0d00 0x00 Control register continued Bit Bit name Description Default RW Type type 1 gt Collision test enabled 7 Collision test 0 gt Normal operation 0 RW Active only in loop back mode RNOO 14 1 6 RESERVED Not used 0 RO P 5 RESERVED used 0 RO P 4 RESERVED Not used 0 RO P 3 RESERVED used 0 RO P 2 RESERVED used 0 RO P 1 RESERVED used 0 RO P 0 RESERVED used 0 RO P Soft reset In order to reset the ST802RT 1x by software control a 1 must be written to bit 15 of the control register using a serial management interface write operation The bit clears itself after the reset process is complete and does not need to be cleared using a second MII write Writes to other control register bits have no effect until the reset process is completed which requires approximately 1 millisecond Writing a O to this bit has no effect Since this bit is self clearing after a few cycles from a write operation it returns a 0 when read Local loop back The ST802RT1x may be placed into loop back mode by writing a 1 to bit 14 of the control register The loop back mode may be cleared by writing a 0 to bit 14 of the control register or by resetting the chip When this bit is read it returns a 1 when the chip is in software controlled
33. Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 58 58 Doc ID 17049 Rev 1
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35. age is sent that the remote fault bit is set to logic one the device sets the remote fault bit in the MII to logic one if the management function is present Doc ID 17049 Rev 1 43 58 Device operation ST802RT1A ST802RT1B 7 15 Transmit isolation Figure 7 Transmit isolation STA STE Ethernet ST802RT1 RxD xi TxD MII TX 100MH2 TP 10MHz Transmit isolation isolates the PHY from the and Tx interface and is activated by setting bit 5 of the 100Base TX control register RN13 5 As with isolate mode all MII inputs are ignored and all outputs are tri stated Additionally all link pulses are suppressed 7 16 Automatic MDI MDIX feature The automatic MDI MDIX feature compensates for using an external crossover cable With auto MDIX the ST802RT1x automatically detects what the other device is and switches the TX amp RX pins accordingly The state machine basically controls the switching of the tdp tdn and the rdp rdn signals prior to the auto negotiation communication The swapping occurs to allow FLP NLP to be transmitted and received in the event that the external cable connections have been swapped 7 17 RMII interface The reduced media independent interface RMII provides a low cost alternative to the IEEE 802 3u MII interface It can support 10 and 100 Mbit data rates with a single clock using independent 2 bit wide transmit and receive paths A single synchronous reference clock S
36. ally when a full duplex configuration is detected This pin is driven on at a 20 Hz blinking frequency ED LED ACT O PU when a collision status is detected in the half duplex configuration Mode 2 gt BLINK activity Mode 1 gt ON full duplex BLINK collision Reset active low This input must be held low for a minimum of 1 ms to reset 29 RESET the ST802RT1x During power up the ST802RT1x is reset regardless of the state of this pin Reset is not complete before 1 ms plus an MDC transition Power down This pin is an active low input in this mode and should be PU asserted low to put the device in a power down mode During power down 9 PWRDWN _ mode TXP TXN outputs and all LED outputs are 3 stated and the interface OD ms is isolated The power down functionality is achievable by software by asserting bit 11 of register RNOO 10 11 RESERVED PD No connection Should be pulled low for normal operation through an external resistor of 2 2 KO Digital power pins 32 OVDD Supply ring power supply 3 3 V 36 41 DVDD Supply Digital power 3 3 V bs GND Ground Digital ground Analog power pins Me Supply Analog power suppl 22 24 14 58 Doc ID 17049 Rev 1 ky ST802RT1A ST802RT1B Pin description Table 4 Pin functions of the ST802RT1x continued Pin n Name Type Description 3 16 19 20 GNDA Ground Analog ground 23 Strap pins be used The ST
37. cument revision history Date 02 Feb 2010 Revision 1 Initial release Changes Doc ID 17049 Rev 1 57 58 ST802RT1A ST802RT1B Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR
38. e forced and the device is in power down state Refer to Section 7 9 for a more detailed explanation of the power down operation Isolate The PHY may be isolated from its media independent interface MII by writing a 1 to bit 10 of the control register All outputs are tri stated except tx and all inputs are ignored Since the management interface is still active the isolate mode may Doc ID 17049 Rev 1 19 58 Registers and descriptors description ST802RT1A ST802RT1B 20 58 be cleared by writing a O to bit 10 of the control register or by resetting the chip When this bit is read it returns a 1 when the chip is in isolate mode otherwise it returns a 0 Restart auto negotiation Bit 9 of the control register is a self clearing bit that allows the auto negotiation process to be restarted regardless of the current status of the auto negotiation state machine In order for this bit to have an effect auto negotiation must be enabled Writing a 1 to this bit restarts the auto negotiation while writing a O to this bit has no effect Since the bit is self clearing after only a few cycles it always returns a when read Full duplex By default the ST802RT1x powers up in half duplex mode The chip can be forced into full duplex mode by writing a 1 to bit 8 of the control register while auto negotiation is disabled Half duplex mode can be resumed by writing a O to bi
39. e mechanical data 9 Package mechanical data In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark ky Doc ID 17049 Rev 1 53 58 Package mechanical data ST802RT1A ST802RT1B Table 36 LQFP48 mechanical data mm Dim Min Typ Max A 1 60 Al 0 05 0 15 A2 1 35 1 4 1 45 b 0 17 0 22 0 27 0 09 0 20 D 8 80 9 9 20 D1 6 80 7 7 20 D3 5 50 E 8 80 9 9 20 E1 6 80 7 7 20 ES 5 50 e 0 50 L 0 45 0 60 0 75 L1 1 K 0 3 5 7 54 58 Doc ID 17049 Rev 1 kr ST802RT1A ST802RT1B Package mechanical data Figure 14 Dimensions of the LQFP48 package DIMENSIONS IN mm GAUGE PLANE PIN 1 IDENTIFICATION SEATING PLANE 2I TOP VIEW DI 2 D ZR 0110596 ky Doc ID 17049 Rev 1 55 58 Package mechanical data ST802RT1A ST802RT1B Figure 15 LQFP48 footprint recommended data mm FOOTPRINT RECOMMENDED 0 27 48x 36 ERA RN NN aad t 9 20 Ti N a quami L 550 9 20 56 58 Doc ID 17049 Rev 1 ST802RT1A ST802RT1B Revision history 10 Revision history Table 37 Do
40. ed After the bit is read or if the chip is reset it reverts to O Extended register ability Because the ST802RT1x supports extended register capability this read only bit is always 1 The ST802RT1x extended registers with their bit functions are described in later sections of this document The PHY identifier registers 1 and 2 consist of a sum of the organizationally unique identifier OUI the vendor s model number and the model revision number ST s IEEE assigned OUI is 0 0080 1 Table 12 RNO2 0d02 0x02 PHY identifier register Hi Bit Bit name Description Default RW Type p type yp Organizationally unique identifier OUI bits 3 18 OUI bits 1 and 2 are fixed to 0 by standard ST OUI 0080E1 0209h Table 13 RNOS3 0903 0x03 PHY identifier register Lo Bit Bit name Description Default HW Type P type yp 15 10 OUILSBs Organizationally unique identifier OUI bits 19 24 100001b RO P MODEL 9 4 NUMBER Manufacturers model number 000110b RO P REVISION Allows identification of the revision of the device software oe NUMBER reading of the register ne 22 58 Doc ID 17049 Rev 1 ST802RT1A ST802RT1B Registers and descriptors description Table 14 RN04 0d04 0x04 Auto negotiation advertisement register ENS RW Bit Bit name Description Default Type type
41. ed and Duplex Mode are selected by programming RNOO register Power down interrupt The power down and interrupt functions are multiplexed on pin 9 of the device By default this pin functions as a power down input and the interrupt function is disabled Setting bit 8 INT OE N of RN12 0x12h configures the pin as active low interrupt output Power down operation To reduce power consumption the ST802RT1x is designed with a power down feature which can reduce power consumption significantly Since the power supply of the 100Base TX and 10Base T circuits are separated the ST802RT1x can turn off the circuit of either the 100Base TX or 10Base T when the other one is operating There is also a power down mode which can be selected by bit 11 in register RNOO During power down mode the TXP TXN outputs and all LED outputs are 3 stated and the MII interface is isolated During power down mode the management interface is still available for reading and writing device registers Power down mode can be exited by clearing bit 11 of register RNOO or by a hardware or software reset setting RNOO 15 1 An external control signal can be used to drive the pin PWRDWN MDINT low overcoming the weak internal pull up resistor Alternatively the device can be configured to initialize into a power down state by placing an external pull down resistor on the PWRDWN MDINT pin Since the device still responds to management register access setting the INT OE
42. egulator output bias resistor 22 Supply Analog power supply 23 GNDA Ground Analog ground 24 VCCA Supply Analog power supply RESERVED Not used in the ST802RT1A 25 SDP Positive signal detect for 100Base FX operation ST802RT1B only 26 LED ACT AN 1 Activity full duplex collision led 27 LED SPEED AN 0 Speed LED 28 LED LINK AN EN Link LED 29 Reset active low 30 MDIO VO PU Management data input output 31 MDC Management data clock Doc ID 17049 Rev 1 11 58 Pin description ST802RT1A ST802RT1B Table 2 Pin description of the ST802RT1x continued EE dx Name Type Description 32 OVDD Supply IO ring power supply 3 3 V 33 GND Ground Analog ground 34 X2 Xtal out 35 X1 Xtal in 25 MHz 36 DVDD Supply Digital power 3 3 V 37 RX CLK MII receive clock 38 RXDV MIL CFGO O 5 PD data valid MII RXDV CRSDV multi function 39 CRS TXD4 carrier sense transmit data 4 40 RXER RXD4 Receive error receive data 4 41 DVDD Supply Digital power 3 3 V 42 RXD3 PHYADDR4 PD Receive data MII Phy4 43 RXD2 PHYADDR3 5 PD Receive data MII Phy3 44 RXD1 PHYADDR2 O S PD Receive data MII RMII Phy2 45 RXDO PHYADDR1 O S PD Receive data MII RMII Phy1 46 COL PHYADDRO 5 collision detection PhyO 47 GND Ground
43. em diagram of the ST802RT1B in FX 8 Pin configuration STSO2RT1A tees 9 Pin configuration STSO2RT1B 10 LED enk ee se ee es ee ee ke ee ER ee ek ee ee ke hr 42 Transmit isolation m men 44 PECL levels us pace Pediat are exon URS RD cn ET Dae TURA ie OR n 46 Implementation of the PECL TX 47 Implementation of the PECL RX section 47 Normal link pulse 5 51 Fast link pulse timing Es EE se EE Re Ge eee 51 management clock 52 Dimensions of the LQFP48 package 55 LQFP48 footprint recommended data mm 56 Doc ID 17049 Rev 1 5 58 Features ST802RT1A ST802RT1B 1 1 1 2 1 3 6 58 Features Physical layer The ST802RT1x integrates the entire physical layer functions of 100Base TX 10Base T and 100Base FX B version only e Optimized deterministic latency for real time Ethernet operation e Provides full duplex operation in both 100 Mbps and 10 Mbps modes e Provides auto negotiation NWAY function of full half duplex operation for both 10 and 100 Mbps e Provides MLT 3 transceiver wit
44. etected 3 Detect 0 gt No MLT3 errors detected 0 RO 2 0 RESERVED Not used 0 RW ky Doc ID 17049 Rev 1 37 58 Device operation ST802RT1A ST802RT1B 7 7 1 38 58 Device operation The ST802RT1x includes 10 100 Base T Ethernet transceiver with interfaces for data and control from to the station management entity STE The ST802RT 1x integrates the IEEE802 3u compliant functions of PCS physical coding sub layer PMA physical medium attachment and PMD physical medium dependent for 100Base TX and the IEEE802 3 compliant functions of manchester encoding decoding and transceiver for 10Base T IEEE standard auto negotiation functions are also supported Media independent interface MII is a 4 bit interface transferring 10 Mbit data using a 2 5 MHz clock and 100 Mbit data using a 25 MHz clock RMII reduced media independent interface is a low pin count alternative capable of transferring 10 and 100 Mbit dibits data using a 50 MHz reference clock the functions and operation schemes are described in the sections that follow 100Base TX transmit operation In 100Base TX transmission the device provides the transmission functions of PCS PMA and PMD for encoding of MII data nibbles to five bit code groups 4B 5B scrambling serialization of scrambled code groups converting the serial NRZ code into NRZI code converting the NRZI code into MLT3 code and then driving the code into the category
45. ext page able Bit 3 of the auto negotiation expansion register returns a 1 when the link partner has next page capabilities It has the same value as bit 15 of the link partner ability register Page received Bit 1 of the auto negotiation expansion register is latched high when a new link code word is received from the link partner checked and acknowledged It remains high until the chip is reset LP auto negotiation able Bit 0 of the auto negotiation expansion register returns a 1 when the link partner is known to have auto negotiation capability Before any auto negotiation information is exchanged or if the link partner does not comply with IEEE auto negotiation the bit returns a value of 0 Doc ID 17049 Rev 1 25 58 Registers and descriptors description ST802RT1A ST802RT1B Table 17 RNO7 0407 0x07 Auto negotiation next page transmit register Bit Bit name Description Default RW Type type YP 15 Next Page 1 gt additional next page s will follow 0 RW _ 0 gt last page 14 RESERVED 0 RW 1 Message page transmitting Message Page 0 gt Unformatted page transmitting 12 Acknowledge 2 1 Local device will comply with message received 0 RW 0 gt Local device cannot comply with message 1 gt Previous transmitted LCW toggle was 0 11 Toggle 0 gt Previous transmitted LCW toggle was 1 0 RO
46. ge match not completed 42 LP auto 1 gt Auto negotiation in ability detect state 0 RO LH negotiation ability 0 gt Auto negotiation not in ability detect state 1 gt Pause is enabled Auto negotiation 0 gt Pause is disabled 11 om 0 RO pause Pause is active only after auto negotiation completion if both devices support symmetric pause RNO4 10 RNOS 10 Auto negotiation highest common denominator 000 gt No common denominator Auto negotiation 001 gt 10Base T half duplex HCD 010 gt 10 full duplex Open 011 gt 100Base TX half duplex 101 gt 100Base TX full duplex ky Doc ID 17049 Rev 1 31 58 Registers and descriptors description ST802RT1A ST802RT1B Table 25 RN19 0d25 0x19 Auxiliary status register continued Bit Bit name Parallel Detection Fault Description 1 gt A fault has been detected the parallel detection function updated on read 0 gt A fault has not been detected Default RW Type RO Type LH Remote Fault 1 gt Remote fault condition detected 0 gt No remote fault condition detected Set when link partner signaled a remote fault condition RNO5 bit 13 or a far end fault indicator was asserted Latched so the occurrence of a remote fault causes the remote fault bit to become set and remain set until it is cleared by register read if no more fault is present RO LH Page Received 1 gt
47. h DC restoration for base line wander compensation e Provides transmit wave shaper receive filters and adaptive equalizer e Provides loop back modes for diagnostics e Built in stream cipher scrambler de scrambler and 4B 5B encoder decoder e Supports external transformer with a turn ratio of 1 414 1 LED display The ST802RT1x supports three configurable light emitting diode LED pins The three supported LED configurations are link speed activity and collision Functions are multiplexed among the LEDs according to the LED mode selected through bit 9 of the Auxiliary mode 2 register RN1B 9 Since these LED pins are also used as strap options the polarity of the LED is dependent on whether the pin is pulled up or down See Table 26 and paragraph 7 11 for more details of LED mode selection Package 48 pin LQFP 7 x 7 mm Doc ID 17049 Rev 1 ky ST802RT1A ST802RT1B Device block diagram 2 Device block diagram Figure 1 ST802RT1x block diagram Serial management x d 8 4 9 9 gi amp 8 g 1 gt lt 4 A A gt lt MII RMII INTERFACES INTERFACE 10BASE T CONTROLLER 10BASE T 100BASE TX 100BASE TX REGISTERS 100BASE FX 100BASE FX TX CHANNEL RX CHANNEL AUTO NEGOTIATION I TRANSMITTER CLOCK RECEIVER GENERATION MDI MDIX
48. he link partner ability register reflect the abilities of the Link partner A 1 on any of these bits indicates that the link partner is capable of performing the corresponding mode of operation Bits 9 5 are cleared any time auto negotiation is restarted or the ST802RT1x is reset Table 16 RNO6 0d06 0x06 Auto negotiation expansion register Bit Bit name Description Default RW Type p type yp 15 5 RESERVED 00000000000 P Parallel 1 gt A fault has been detected via the parallel detection 4 function updated on read 0 RO LH Detection Fault 0 gt A fault has not been detected Link Partner 1 gt LP is next page able 3 Next Page Able 0 gt LP does not support next pages 0 ix 2 Next Page Able 1 Local device is next page able 1 P Fixed to 1 1 Page Received 1 gt Link code word received updated on read 0 RO LH 0 gt Link code word not yet received Link Partner e Auto Negotiation 1 gt LP supports auto negotiation updated on read 0 LH Able 0 gt LP does not support auto negotiation Reserved Ignore when read Parallel detection fault Bit 4 of the auto negotiation expansion register is a read only bit that gets latched high when a parallel detection fault occurs in the auto negotiation state machine For further details please consult the IEEE standard The bit is reset to 0 after the register is read or when the chip is reset LP n
49. i and 100Base FX of IEEE 802 3u B version only The ST802RT1x supports both half duplex and full duplex operation at 10 and 100 Mbps operation Its operating mode can be set using auto negotiation parallel detection or manual control It allows for the support of auto negotiation functions for speed and duplex detection The automatic MDI MDIX feature compensates for the use of a crossover cable With auto MDIX the ST802RT1x automatically detects what is on the other end of the network cable and switches the TX amp RX pin functionality accordingly Table 1 Device summary Order codes Temperature range Package ST802RT1AFR 40 to 105 C LQFP48 ST802RT1BFR 40 to 105 C LQFP48 February 2010 Doc ID 17049 Rev 1 1 58 www st com Contents ST802RT1A ST802RT1B Contents 1 dii e mn BE ge ee ie pn i I RE 6 1 1 Physical layer ad estare exe ene EL N ag ae 6 1 2 LED display tous BERE deve Sew kere es oe eee vhs Seat NES 6 1 3 asus nts itu e oe Wane ene VRBE d eed eee a 6 2 Device block diagram 7 3 System and block diagrams 8 4 Pin configuration 9 5 Pin description ss tees keel Es Rx REX Ga EGER FT FEE PEE 11 6 Registers and descriptors description 17 6 1 Register AR IE a feas Mie ere a aed icai d afro hs
50. it in the status register The far end fault is on by default in 100BaseFX off by default in 100Base TX and 10Base T modes and may be controlled by software and reset Mil management interface Internal register access is guaranteed through the management interface as specified in the IEEE 802 3u standard Clause 22 This serial interface consists of a Management Data Clock MDC pin and a Management Data I O MDIO pin The MDC pin is always driven by the station management entity STA while the MDIO pin can be driven by either the STA or the PHY depending on the operation in progress The logic value on the MDIO pin is sampled on the rising edge of the MDC clock signal The MDIO pin has an internal pull up used to keep the line to logic 1 when not driven Register read write operations are performed sending on the Management interface frames in the format shown in Table 33 Management frame format READ PRE ST 01 OP 10 PHYAD AAAAA REGAD RRRRR TA 20 D D IDLE WRITE 01 01 AAAAA RRRRR 10 D D 48 58 Both read write frames start with a preamble PRE composed of 32 consecutive logic 1s on the MDIO pin and corresponding 32 clock cycles on the MDC pin The management frame preamble can be suppressed as described in Section 7 13 The preamble is followed by a 2 bit start of frame ST consisting of a transition to l
51. it is set registers at addresses 1B are masked 0 RW sc Registers Enable by correspondent shadow registers Self clearing functionality added to this bit when shadow registers are enabled 6 0 RESERVED Not used 0000000b RO 36 58 Doc ID 17049 Rev 1 ky ST802RT1A ST802RT1B Registers and descriptors description Table 30 RS1B 0427 Ox1B Misc status error test shadow register Bit Bit name Description Default RW Type Type YP 1 gt enabled with no errors TX100 only _ 15 MLT3 Detect MLT3 disabled or MLT3 error TX100 CABLE LENGTH m 000 20 001 20 40 010 40 60 14 12 011 60 80 000b RO 9 100 lt 80 100 101 100 120 110 120 140 111 22140 11 RESERVED USED 0 RW LED Test 1 gt LED frequencies up by 8192 times 10 0 RW control 0 gt Normal operation 9 Descrambler 1 Descrambler locked on RX stream 0 RO _ Locked 0 Descrambler not locked False Carrier 1 False carrier detected 8 Detect 0 gt No false carrier detected 9 RO 7 1 End of stream delimiter missing detected 0 RO LH Detect 0 gt No end of stream delimiter detected RX Error 1 gt RX error detected 100BASE X 6 Detect 0 No errors detected RO 5 RESERVED Not used 0 RO LH Lock Error 1 gt Lock error detected Detect 0 gt No lock errors detected RO MLT3 Error 1 gt error d
52. k pad ON for link up led speed pad ON for 100 Mb OFF for 10 Mb led act pad BLINK for activity 8 RESERVED 0 RO P Block 10Base 1 gt Disables 10Base T echo data on DV 7 0 RW T echo 0 gt Normal operation 6 4 RESERVED 000b RW 0 gt Forces signal quality error generation 10Base T 3 MI SQE DIS half duplex 1 RW 1 Normal operation 2 1 RESERVED 01b RW 0 RESERVED 0 RO P Block 10BaseT echo Default 0 When enabled during 10BASE T half duplex transmit operation the TXEN signal does not echo onto the RXDV pin The TXEN echoes onto the CRS pin and the CRS de assertion directly follows the TXEN de assertion SQE disable Default 0 When asserted it disables SQE pulses when operating in 10BASE T half duplex mode Doc ID 17049 Rev 1 33 58 Registers and descriptors description ST802RT1A ST802RT1B Table 27 0d28 0x1C 10Base T error and general status register Bit Bit name Description Default ded Type 15 14 RESERVED 00 RW 1 MDI X configuration used Ts MODE Status 0 gt configuration used 12 MDIX Swap 1 MDIX force if not in fx mode 0 RW _ 0 gt 1 gt MDIX auto detection and negotiation disabled 11 MDIX Disable MDI MDIX auto detection enabled 1 10 RESERVED 0 RO P LH 1 gt Jabber condition detec
53. leted It remains 1 until the auto negotiation is restarted a link fault occurs or the chip is reset If auto negotiation is disabled or the process is still in progress the bit returns a 0 Auto negotiation ack This read only bit is set to 1 when the arbitrator state machine exits the acknowledged detect state It remains high until the auto negotiation process is restarted or the ST802RT1x is reset Auto negotiation ability This read only bit returns a 1 when the auto negotiation state machine is in the ability detect state It enters this state a specified time period after the auto negotiation process begins and exits after the first FLP burst or link pulses are detected from the link partner This bit returns 0 any time the auto negotiation state machine is not in the ability detect state Super isolate Writing a 1 to this bit places the ST802RT1x into the super isolate mode Similar to the isolate mode all MII inputs are ignored and all MII outputs are tri stated Additionally all link pulses are suppressed This allows the ST802RT1x to coexist with another PHY on the same adapter card with only one being activated at any time Table 29 RN1F 0431 Ox1F Shadow registers enable register Bit Bit name Description Default FN Type 15 8 RESERVED NOT USED 00000000b RO 1 gt Shadow registers enabled 0 gt Normal operation 7 Shadow When this b
54. liary PHY register are five read only bits that report the highest common denominator HCD result of the auto negotiation process Immediately upon entering the link pass state after each reset or restart auto negotiation only one of these five bits will be a 1 The link pass state is identified by a 1 in bit 6 or 7 of this register The HCD bits are reset to 0 every time auto negotiation is restarted or the ST802RT 1x is reset Note that for their intended application these bits uniquely identify the HCD only after the first link pass after reset or restart of auto negotiation On later link fault and subsequent re negotiations if the ability of the link partner is different more than one of the above bits may be active These bits are only set for full auto negotiation handshake and not for parallel detection of forced speed modes Note that bit 14 HCD T4 is never set in the ST802RT1x Reserved Ignore when read Restart auto negotiation A self clearing bit that allows the auto negotiation process to be restarted regardless of the current status of the state machine For this bit to work auto negotiation must be enabled Writing a 1 to this bit restarts auto negotiation Since the bit is self clearing it always returns a 0 when read The operation of this bit is identical to bit 9 of the control register Auto negotiation complete This read only bit returns a 1 after the auto negotiation process has been comp
55. more jabber condition is present Working on 10Base T only Fixed to 0 in 100Base X modes 0 Extended 1 ia extended register capabilities E Capability Fixed to 1 ky Doc ID 17049 Rev 1 21 58 Registers and descriptors description ST802RT1A ST802RT1B Reserved bits Ignore ST802RT 1x output when these bits are read Preamble suppression This bit is a read only bit and can be set by bit 1 of the RN14 register When read as a logic 1 the ST802RT 1x is able to accept management frames with or without the standard preamble pattern When preamble suppression is enabled RN14 1 1 only 2 preamble bits are required between successive management commands instead of the normal 32 Auto negotiation complete Bit 5 of the status register returns a 1 if the auto negotiation process has been completed and the contents of registers 4 5 and 6 are valid Link status The ST802RT1x returns a 1 on bit 2 of the status register when the link state machine is in link pass indicating that a valid link has been established Otherwise it returns 0 When a link failure occurs after the link pass state has been entered the link status bit is latched at 0 and remains so until the bit is read After the bit is read it becomes 1 if the link pass state has been entered again Jabber detect 10BASE T operation only The ST802RT1x returns a 1 on bit 1 of the status register if a jabber condition has been detect
56. n unformatted code according to value set in RNO8 13 00006 26 58 Doc ID 17049 Rev 1 ky ST802RT1A ST802RT1B Registers and descriptors description Next page Indicates whether this is the last next page Msg page Differentiates a message page from an unformatted page Ack2 Indicates that link partner has the ability to comply with the message Toggle Used by the arbitration function to ensure synchronization with the link partner during next page exchange Message code field An 11 bit wide field encoding 2048 possible messages Unformatted code field An 11 bit wide field which may contain an arbitrary value Table 19 RN10 0d16 0x10 RMII TEST control register RW Bit Bit name Description Default type Type 15 14 RESERVED 000b RO 13 RESERVED 000b RW 12 11 RESERVED 10b RO 10 RESERVED Ob RW 1 gt enabled MII Enabl Stra RW nabe 0 gt disabled enabled see bit 10 8 6 RESERVED 0006 RW 1 gt Far end fault enabled only if auto negotiation is 5 FEF Enable disabled 0 RW 0 gt Far end fault not enabled 43 RESERVED 00b RO 1 Extended FIFO mechanism for RMII enabled 2 FIFO Extended 0 gt Normal operation 0 RW This bit extends elasticity buffer size in RMII interface 1 Out of band signaling enabled 1 OOBS 0 gt Normal operation 0 BW To transfer info
57. ng bits or else the default values if no write has been completed since the last chip reset Even though bit 9 advertise 100BASE T4 is writable it should never be set since the ST802RT1x does not support T4 operation Advertised selector Bits 4 0 of the advertisement register contain the fixed value 00001 indicating that the chip belongs to the 802 3 class of PHY transceivers Table 15 RNOS 0d05 0x05 Auto negotiation link partner ability register Bit Bit name Description Default Rw Type type 1 gt Link part i t t f 15 LP Next Page gt in partner desires nex page ransfer 0 RO _ 0 gt Link partner does not desire next page transfer LP 1 gt Link partner acknowledges reception of the ability data 14 Acknowledge Word 0 9 Jo gt Acknowledge not yet received 13 LP Remote 1 gt Remote fault indicated by link partner 0 RO Fault 0 gt No remote fault indicated by link partner 12 RESERVED 0 RO Asymmetric 1 gt LP supports asymmetric pause MAC level clause 31 11 Pause full annex 31B of 802 3u 0 RO duplex 0 gt LP has no MAC based full duplex flow control _ 1 gt LP supports symmetric pause MAC level clause 31 10 ese annex 31B of 802 3u 0 RO 0 gt LP has MAC based full duplex flow control 1 LP supports 100BASE T4 _ 9 100BASE T4 0 gt LP does not support 100BASE T4 0 pu 8 100BASE TX 1 LP supports 1
58. nterrupt is pending 4 0 gt no link status changes 0 RO LH P Interrupt enabled by RN12 4 Auto Negotiation 1 gt acknowledge match interrupt is pending 3 Link Code Word 0 gt no link code word received 0 RO LH Received Interrupt enabled by RN12 3 EE de 1 gt Parallel Detection fault interrupt is pending 2 interrupt 0 gt No Parallel Detection faults 0 RO LH P Interrupt enabled by RN12 2 1 gt Auto negotiation page received interrupt is pending 1 E 0 gt no auto negotiation page received 0 RO LH Interrupt enabled by RN12 1 1 gt receive error buffer full interrupt is pending 64k packet errors 0 RX FULL 0 gt less than 64k error packets received 0 RO LH Interrupt enabled by RN12 0 Related counter is cleared after read 28 58 Doc ID 17049 Rev 1 ky ST802RT1A ST802RT1B Registers and descriptors description Table 21 RN12 0d18 0x12 Receiver event interrupts register Bit Bit name RESERVED Description NOT USED Default 0000000b RW Type RO Type INT OE N INTERRUPT OUTPUT ENABLE 1 PWRDWN MDINT is a power down input 0 gt PWRDWN MDINT is an interrupt output RW INT EN INTERRUPT ENABLE 1 Event interrupts enabled 0 gt Event interrupts disabled RW AN CMPL EN AUTO NEGOTIATION COMPLETED INTERRUPT ENABLE 1 gt Interrupt enabled 0 Interrupt disabled RW REMFLT DET EN REMOTE FAULT INTERRUPT ENABLE 1
59. o Table 7 The value on these pins is set by connecting the input pins to GND 0 VCC 1 through 2 2 resistors 27 AN 0 S PU These pins should NEVER be connected directly to GND or Vcc 26 AN 1 The value set at this input is latched into the ST802RT1x at Hardware Reset The float pull down statuses of these pins are latched into the basic mode control register and the auto negotiation advertisement register during hardware reset The default is 111 since these pins have internal pull up see Table 7 46 PHYADDRO PHY address 4 0 These pins are used to provide the address which is latched 45 PHYADDR1 into the internal receive mode control register RN14 0x14h after the reset 44 PHYADDR2 SPU PHYADDRO pin has weak internal pull up resistor 43 PHYADDR3 S PD PHYADDR 4 1 pins have weak internal pull down resistors 42 PHYADDR4 An external 2 2 kQ resistor should be used for pull up down the pins 4 Doc ID 17049 Rev 1 15 58 Pin description ST802RT1A ST802RT1B Table 5 Signal detect SDN SDP Mode Ground Ground TX mode Ground A positive voltage Undefined state Voltage gt 0 6 V Voltage gt 0 6 V Undefined state PECL ow PECLMID PECL ow FX mode asserted but no data valid on the line PECLHiGH PECL ow FX mode asserted but no data valid on the line PECL PECLHIGH PECLHIGH Undefined state PECL CLLOW PECLHIGH FX mode asserted link OK and data valid
60. ogic 0 and then back to logic 1 after which the operation code OP is transmitted to distinguish between read and write operations After the operation code the PHY address PHYAD and register address REGAD are sent each composed of 5 bits which have to be sent MSB first The turn around TA is a 2 bit time spacing placed between the register address and the data field inserted to avoid contention during a read transaction In a write operation the STA drives a logic 1 during the first bit time and a logic O during the second one In a read operation both STA and PHY are in high impedance during the first bit time and then the PHY drives 0 during the second one The data field contains the 16 bits to write to or read from the specified register and is followed by at least one IDLE bit which closes the frame ky Doc ID 17049 Rev 1 ST802RT1A ST802RT1B Electrical specifications and timings 8 Electrical specifications and timings Table 34 Absolute maximum ratings Parameter Value Unit Supply voltage 0 5 to 4 V Input voltage 0 5 to Vcc 0 5 V Output voltage 0 5 to Vcc 0 5 V Storage temperature 65 to 150 Ambient temperature 40 to 105 ESD protection 2 kV Note Absolute maximum ratings are those values beyond which damage to the device may occur Functional operation under these conditions is not implied Table 35 gt General DC specification
61. operation The 10Base T RX channel contains the Phy SMART sauelch circuits clock recovery circuits link pulse detector manchester to NRZ decoder and serial to parallel converter manchester decoding is performed on the data stream RMII mode Dibits are repeated 10 times so that any repeated dibit may be sampled on the 10 Mb clock edge Loop back operation The ST802RT1x provides an internal loop back option for both 100Base TX and 10Base T operations Setting bit 14 of the RNOO register to 1 enables the loop back option In the loop back operation the txp txn and rxp rxn lines are isolated from the media In 100Base TX internal loop back operation the data comes from the transmit output of the NRZ to NRZI converter then loop back to the receive path into the input of NRZI to NRZ converter In 10Base T loop back operation the data is sent through the transmit path and loop back from the output of the manchester encoder into the input of phase lock loop circuit of the receive path Full duplex and half duplex operation The ST802RT1x can operate in either full duplex or half duplex network applications In full duplex both transmit and receive can be operated simultaneously In full duplex mode the collision COL signal is meaningless and carrier sense CRS signal is asserted only when the ST802RT 1x is receiving In half duplex mode only transmit or receive can be operated at one time In half duplex mode the collision signal i
62. operation 2 5 MHz for 10 Mbps operation MII collision detection The ST802RT1x asserts this output when detecting a 46 COL collision This output remains high for the duration of the collision This signal is asynchronous and inactive during full duplex operation carrier sense During half duplex operation RNOO 8 0 the ST802RT1x 39 CRS asserts this output when either transmit or receive medium is non idle During full duplex operation RNOO 8 1 crs is asserted only when the receive medium is non idle MII control interface Management data clock Clock for the MDIO serial data channel One MDC 31 MDC transition is also required to complete a device reset Maximum frequency is 2 5 MHz 30 MDIO VO PU Management data input output Bi directional serial data channel for PHY communication 9 MDINT OD Management data interrupt Physical twisted pair interface Xtal in 25 Mhz 25 MHz reference clock input When an external 25 MHz 35 X1 crystal is used this pin must be connected to one of its terminals If an external 25 MHz oscillator clock source is used then this pin will be its input pin ky Doc ID 17049 Rev 1 13 58 Pin description ST802RT1A ST802RT1B Table 4 Pin functions of the ST802RT1x continued Pin n Name Type Description Xtal out 25 MHz reference clock output When an external 25 MHz crystal is 34 2 used
63. ption Default FW Type P type yp 1 gt software reset reset in process 0 gt normal operation 13 Soft This bit which is self clearing returns 1 until the reset process 9 PE is complete After this reset the configuration is not re strapped 1 Loop back enabled Local loop O gt Normal operation _ back Local loop back passes data from transmitting to receiving Strap serial conversion analog logic Speed 1 gt 100 Mb s 13 ection 0 gt 10 Mb s Strap RW Ignored if auto negotiation is enabled A 1 Auto negotiation is enabled 12 spi 0 gt Auto negotiation is disabled St RW id Bits 8 and 13 of this register are ignored if this bit is set high Not available in FX mode auto negotiation always disabled 11 Bowerdowa 7 Power down 0 RW 0 gt Normal operation 1 gt Isolates the core from the with the exception of the serial management 0 gt Normal operation 10 Isolate When this bit is set to 1 related pad outputs are forced to tri Strap RW state inputs are ignored MII isolate mode can be activated at initialization by strapping 00000 on physical address Auto 1 Restarts Auto negotiation process ignored if Auto 9 negotiation negotiation is disabled 0 RW SC restart 0 gt Normal operation 1 gt full duplex operation 8 Duplex mode 0 gt Half duplex operation Strap RW Ignored if auto negotiation is enabled 18 58 Doc ID 17049 Rev 1 ky ST802
64. ration detect circuit 45 720 PECL transmiter vaste saai E BERE DERDE hes wee ee cota DER AE 46 7 21 47 7 22 48 7 23 management interface 48 Electrical specifications timings 49 Package mechanical data 53 REVISION history 57 Doc ID 17049 Rev 1 3 58 List of tables ST802RT1A ST802RT1B List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 4 58 Device SUMMA OE oa eae Pasa Greate eae Sede eae n s 1 Pin description of the STSO2RT1x 11 Abbreviations ee Pas ee eee ee 12 Pin functions of the 5 802 1 13 Signal detect 2 Ged bed dequo pe Gee ER 16 CFGO CFG1 configuration llle 16 Auto negotiation advertisement
65. receiving bit stream CRS is de asserted when an ESD code group or idle code group is detected In half duplex mode CRS is asserted during packet transmission or receive In full duplex mode CRS is asserted only during packet reception RMII mode this uses a reference clock SCLK of 50 MHz 5B code groups are converted to 4 bit nibbles and the data is sent through a FIFO to the RMII receive data pins as dibits In case of an invalid code group in the data stream the RXER signal is asserted and the 4 bits of the receive data pins are driven with a specific code signalling the type of error detected For RMII mode the CRS and RXDV pins combine their functionality into the RXDV pin pin 38 The RXDV pin toggles at the end of a frame to indicate that the data is being emptied from the internal FIFOs Doc ID 17049 Rev 1 39 58 Device operation ST802RT1A ST802RT1B 7 3 7 4 7 5 7 6 7 7 40 58 10Base T transmit operation In 10Base T the device s TX channel includes the parallel to serial converter NRZ to manchester encoder link pulse generation and an internal physical ethernet wire interface Phy It also provides collision detection and SQE test for half duplex application RMII mode Uses a reference clock SCLK of 50 MHz The value on txd 1 0 must be valid such that txd 1 0 may be sampled every 10 cycle yielding the correct frame data To achieve this the dibits should be repeated 10 times 10Base T receive
66. rmation i e speed link duplex mode when TX EN CRS DV are de asserted RMII 1 2 0 RESERVED 0 RW ky Doc ID 17049 Rev 1 27 58 Registers and descriptors description ST802RT1A ST802RT1B Table 20 RN11 0d17 0x11 Receiver configuration information and interrupt status register RW Bit Bit name Description Default Type type 15 11 RESERVED 0000056 RO P 1 FX mode set 0 gt FX mode not set 10 FX MODE If set to 1 auto negotiation and scrambling is disabled This 0 RO bit can be set through an opportune hardware topology in ST802RT1B 1 gt 100 Mb s mode 9 Speed 0 gt 10 Mb s mode 0 RO This bit holds a valid value only if a link is already established 1 gt Full duplex mode enabled 8 Duplex 0 gt Half duplex mode enabled 0 RO This bit holds a valid value only if a link is already established 1 Pause is enabled 0 gt Pause is disabled i pause Pause is active only after auto negotiation completion if both 0 devices support symmetric pause RNO4 10 RNO5 10 1 gt Auto negotiation completed interrupt is pending 6 Auto neg interrupt 0 gt Auto negotiation not yet completed 0 RO LH Interrupt enabled by RN12 6 Remote fault 1 gt Remote fault condition interrupt is pending 5 interrupt 0 gt No remote fault condition detected 0 RO LH P Interrupt enabled by RN12 5 1 gt link status changed to fail i
67. s asserted when the transmit and receive signals collide and the carrier sense asserted during transmission and reception Auto negotiation operation The auto negotiation function is designed to provide the means to exchange information between the ST802RT1x and the network partner to automatically configure both to take maximum advantage of their abilities and both are setup accordingly The auto negotiation function can be controlled through auto negotiation enable bit 12 of the RNOO register or the an en strap pin 27 Doc ID 17049 Rev 1 ST802RT1A ST802RT1B Device operation 7 8 7 9 7 10 Auto negotiation exchanges information with network partner using the fast link pulses FLPs a burst of link pulses FLP s contain 16 bits of signaling information to advertise all supported capabilities determined by register RNO4 auto negotiation advertisement register to the remote partner Based on this information they identify their highest common capability by following the priority sequence below 1 100Base TX full duplex highest priority 2 100Base TX half duplex 3 10Base T full duplex 4 10Base T half duplex lowest priority During power up or reset if auto negotiation is found enabled then FLPs is transmitted and the auto negotiation function proceeds Otherwise the auto negotiation does not occur until the bit 12 of RNOO register is set to 1 When auto negotiation is disabled then the Network Spe
68. t 8 of the control register or by resetting the chip Collision test The COL pin may be tested during loop back by activating the collision test mode While in this mode asserting TXEN causes the COL output to go high within 512 bit times De asserting TXEN causes the COL output to go low within 4 bit times Writing a 1 to bit 7 of the control register enables the collision test mode Writing a O to this bit or resetting the chip disables the collision test mode When this bit is read it returns a 1 when the collision test mode has been enabled otherwise it returns 0 This bit should only be set while in loop back test mode Reserved bits Write ignored read as O Doc ID 17049 Rev 1 ky ST802RT1A ST802RT1B Registers and descriptors description Table 11 RNO1 0d01 0x01 Status register RW Bit Bit name Description Default Type type 15 100BASE T4 0 gt PHY not able to perform 100BASE T4 0 RO ABILITY Fixed to 0 14 100BASE X 1 gt PHY able to perform full duplex 100BASE X 1 RO P Full Duplex Fixed to 1 internally not used 100BASE X 1 gt PHY able to perform half duplex 100BASE X 13 1 RO P Half Duplex Fixed to 1 10BASE T 1 gt PHY able to perform full duplex 10BASE T 12 1 RO P Full Duplex Fixed to 1 internally not used 10BASE T 1 gt PHY able to perform half duplex 10BASE T 11 1
69. t conditions Min Typ Max Unit XTAL conditions bag X1 duty cycle 45 50 55 bat X1 frequency 25 50 125 MHz bat X1 tolerance 50 ppm 1 load capacitance 18 pF 10Base T normal link pulse NLP Tnps NLP start after reset 10 Mbps 16 ms Tnpw NLP width 10 Mbps 100 ns Tnpc NLP period 10 Mbps 8 24 ms Fast link pulse FLP AC timing specification Number of pulses in one burst 17 33 FLP width 100 00 ns Tflcpp Clock pulse to clock pulse period 111 125 139 us Tflcpd Clock pulse to data pulse period 55 5 62 5 69 5 us Tflow Burst width 2 ms Tflbp FLP burst period 8 16 24 ms EEN Ttlat bel ra on TXP TXN unt 100 Mb s 130 ns MII Management Interface AC timing specification Tmihl MDC clock high amp low time 160 ns Tmip MDC clock period 400 ns Tmis MDIO setup time STA sources MDIO 10 ns Tmih MDIO hold time STA sources MDIO 10 ns Tmidco clock to output delay PHY sources MDIO 0 300 ns 50 58 Doc ID 17049 Rev 1 ST802RT1A ST802RT1B Electrical specifications and timings Figure 11 Normal link pulse timings Tnpw FE 4 Tnpc Figure 12 Fast link pulse timing ki Doc ID 17049 Rev 1 51 58 Electrical specifications and timings ST802RT1A ST802RT1B Figure 13 management clock timing Tmihl Tmihl Tmip MDC Tmis pe Tmidco Tmih lt 52 58 Doc ID 17049 Rev 1 ST802RT1A ST802RT1B Packag
70. ted 0 gt No jabber condition detected 9 Jabber detect Set at jabber condition detection cleared only after register read 0 RO LH if no more jabber condition is present Fixed to 0 in 100Base X modes Same as RNO1 1 and RN19 0 8 Polarity 1 gt Polarity changed event 0 RO Changed 0 gt No polarity changes 7 0 RESERVED id RO MDIX status This bit indicates whether MDI or MDIX is in use MDIX swap Setting this bit forces the device to MDIX When this bit is 0 the MDIX status is determined by auto negotiation if auto MDIX is enabled MDIX disable Setting this bit disables auto detection and negotiation of MDIX Clearing this bit enables auto MDIX 34 58 Doc ID 17049 Rev 1 ky ST802RT1A ST802RT1B Registers and descriptors description Table 28 RN1E 0d30 Ox1E Auxiliary PHY register Bit Bit name Description Default p Type P Type yp 1 AN 100Base TX full duplex selected _ 15 HOD 100base Tx FDX 0 AN 100Base TX full duplex not selected 9 RO 1 gt AN 100Base T4 selected not supported 14 100BASE T4 0 gt 100Base T4 not selected 0 RO _ Internally fixed to 0 13 100base TX 1 gt AN 100Base TX half duplex selected 0 RO _ HDX 0 gt AN 100Base TX half duplex not selected 1 gt AN 10Base T full duplex selected 12 Heb IGBASEST FDA 0 gt AN 10Base T full duplex not selected 9 RO 1 gt AN 10Base T half duplex selected
71. ted but no data valid on the line SD gt SD gt FX mode asserted Link OK Doc ID 17049 Rev 1 45 58 Device operation ST802RT1A ST802RT1B These two signals can be either driven by standard CMOS levels or by PECL levels The data coming from the optical transceiver are PECL signals and need to be converted to CMOS level before being delivered to the data and clock recovery and then to the serial to parallel interface to be transmitted to the digital portion Table 32 Configuration of signal detect voltage levels SDn SDp Mode Ground Ground TX mode Ground Positive voltage Undefined state gt 0 6 Voltage 0 6 Undefined state PECLLOW PECLMID ow FX mode asserted but no data valid on the line PECLHIGH PECLMID ow FX mode asserted but data valid on the line PECLHIGH PECLHIGH Undefined state PECL ow PECLyip PECLHIGH FX mode asserted link OK and data valid Figure 8 PECL levels VDD 1 32 7 20 PECL transmitter This circuit is designed to acguire the data coming from the parallel to serial interface and NRZ to NRZI converter and to transmit it to the optical transceiver In this case the data is received by the transmitter in a CMOS format and is transmitted to the optical portion in a PECL format See Figure 8 the definition of PECL levels 46 58 Doc ID 17049 Rev 1 ki ST802RT1A ST802RT1B Device operation Figure 9 Implementa
72. tion of the PECL TX section 3 3V 3 3V STEPHY1b OPTICAL TRASDUCER 7 21 PECL receiver The data signals coming from the optical transceiver are in PECL format and need to be converted to CMOS level before being transmitted to the data and clock recovery and to the digital portion The data is sampled by the optical transceiver but the data stream is related to the clock of the transmitting transceiver so it needs to be recovered re sampled and aligned to the RX clock This function and all the timing involved are assumed to be compatible with that currently available for the 100TX twisted pair so no modifications are required for this circuit Figure 10 Implementation of the PECL RX section 3 3V 3 3V STEPHY1b OPTICAL TRASDUCER RXPn ky Doc ID 17049 Rev 1 47 58 Device operation ST802RT1A ST802RT1B 7 22 7 23 Table 33 Far end fault For 100Base FX mode which does not support auto negotiation the ST802RT1x implements the IEEE 802 3 standard far end fault mechanism for the indication and detection of remote error conditions If the far end fault is enabled a PHY transmits the far end fault indication whenever a receive channel failure is detected Each PHY also continuously monitors the receive channel when a valid signal is present When its link partner is indicating a remote error the PHY forces its link monitor into the link fail state and sets the remote fault b

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