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ST L99MM70XP handbook

1. Table 44 Status register 2 Status register 2 12h Bit 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECFD ECV OUTS OUTS OUT4 OUT4 OUTS OUT3 OUT2 OUT2 OUT1 OUT1 Mame Es Ls OUR OUTS OUT OUT6 ve is Hs ts He ts Hs is Hs ES Table 45 Status register 2 bits Bit name Comment ECFDLSOL ECVLSOL OUT9OL OUT80L OUT7OL The open load detection monitors the load current in each activated output stage If the load current is below the under current detection threshold for at least tyo 2ms the corresponding open load OUT6OL bitis set Due to the mechanical electrical inertia of typical loads a short activation of the outputs OUT5HSOL e g 3 ms can be used to test the open load status without changing the mechanical electrical state of the loads OUTSLSOL The open load detection of OUT1 HS and OUT1 LS can be masked by the configuration register OUT4HSOL Bit 4 9 F 74 The open load detection of ECFDLS ECVLS and OUT7 can be masked by the configuration OUT4LSOL register Bit 6 OUT3HSOL OUT3LSOL OUT2HSOL OUT2LSOL OUT1HSOL Maskable by the configuration register OUTILSOL an open load event is not considered in open load bit TW OL of global status register Na Doc ID 022637 Rev 1 61 68
2. SPI control and status registers L99MM70XP Table 46 Status register 3 Status register 3 13h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset Da 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIN LIN LIN WD WD Name perm TXD prem La UV OV timer timer rin E pon ECVO TSD2 TSD1 TW dom dom rec state state Table 47 Status register 3 bits Bit name Comment LIN perm dom If the bus state is dominant low for more than 12 ms a permanent dominant status is detected The status bit is set LIN TXD dom If TXD is in dominant state low for more than 12 ms the transmitter is disabled and this bit is set If TXD changes to dominant low state but RXD signal does not follow within 40 us the LIN perm rec Sg RUE transmitter is disabled and this bit is set Vccrail Vccrail Vcc lt 2 V for more than 2 ps UV Vg undervoltage detected If an over under voltage event is detected the outputs are disabled and one of these bits is set If the OVUVR bit is O the outputs are enabled automatically after OV Vg overvoltage detected an over under voltage event and the UV OV bit is reset If the OVUVR bit is 1 the outputs are enabled after clearing the UV OV bit by SPI command read and clear operation Watchdog state WDTIM1 Display which part of the total WD time 100 ms has been elapsed WDTIM1 WDTIMO Elapsed time 0 0 1 8 of the total WD time WDTIMO 0 1 lt 2 3 of
3. Figure 10 Watchdog timing WD trigger bit trigger event A A 4 a A NRES out H E Ik gt twor twor twor twor gt x QUEE time normal missing normal missing trigger operation trigger operation for long time GAPGMS00014 Figure 11 Watchdog late and safe window liy max gt ty min pi safe trigger late watchdog undefined area failure time GAPGMS00015 8 7 Current monitor output CM The voltages are referred to ground and currents are assumed positive when the current flows into the pin 8 V lt Vs lt 16 V Tamb 40 C 125 C unless otherwise specified Table 15 Current monitor output CM Symbol Parameter Test condition Min Typ Max Unit Current monitor output ratio 0V s Vgu S Veg 1 V 1 10000 lcm louT1 5 9 and 8 low on resistance CMr lcw louT 3 4 6 7 and 8 high on 1 2000 resistance 36 68 Doc ID 022637 Rev 1 ky L99MM70XP Electrical characteristics Table 15 Current monitor output CM continued Symbol Parameter Test condition Min Typ Max Unit 0OVXxVgoyS Vcc 1 V Current monitor accuracy loUTmin 500 mA louT9max 9 9 A ACCICMOUT1 5 9 and 8 low on res louri Smax 2 9 A lOUTSr 13A 496 1 8 2 CM acc mer FS Fs O0V lt Vom lt s Vcc 1 V I in 100 mA accl F OUT min A CMOUT2 3 4 6 7 and 8 hig
4. Figure 17 SPI input and output timing parameters t Do low to high DO eee high to low thin trin gt D podrien TA PER 0 8 Voc CLK peers 0 2 Voc GAPGMS00020 Figure 18 SPI maximum clock frequency E scu PG tscxti Fi tsa BP MicroController Master kag tsetup gt GAPGMS00021 Doc ID 022637 Rev 1 49 68 Electrical characteristics L99MM70XP 8 12 50 68 The maximum SPI clock frequency can be calculated as follows see Figure 18 tci kov total tci rise IC toi ki PCB tei kov slave tsetup HC fcu max lex tci kov total Example tci ov 25 ns 100 ns 250 ns 25 ns 400 ns fcu k max lt 1 25 MHz Input PWM 2 for Flash mode The voltages are referred to ground and currents are assumed positive when the current flows into the pin 6 V lt Vs x 18 V all outputs open Tamp 40 C 125 C unless otherwise specified Table 26 Input PWM2 for Flash mode Symbol Parameter Test condition Min Typ Max Unit Input low level PWM2 Vias P 1 Vs 13 5 V 61 725 84 V falling igh Vs 13 5 V Vpar Vasa Input high level PWM2 S BAT standby 74 8 4 9 4 V rising mode Vcc switches on VilashHYS Input voltage hysteresis Vs 13 5 V 0 6 0 8 1 0 V 1 Parameter guaranteed by design Doc ID 022637 Rev 1 L99MM70XP SPI control and status registers
5. GND OUT1 ECV ECFD VS OUT7 EC OUT8 ECDR PWM2 NRES PWM1 CP INH PWM3 OUT6 VS OUT4 OUT5 GND GAPGMS00006 Doc ID 022637 Rev 1 11 68 Description L99MM70XP 3 Description 3 1 Voltage regulator The L99MM70XP contains a fully protected low drop voltage regulator which is designed for very fast transient response The output voltage is stable with load capacitors 220 nF The voltage regulator provides 5 V supply voltage and up to 100 mA continuous load current for the external digital logic microcontroller etc In addition the regulator Vcc drives the L99MM70XP internal 5 V loads The voltage regulator is protected against overload and overtemperature An external reverse current protection has to be provided by the application circuitry to prevent the input capacitor from being discharged by negative transients or low input voltage The output voltage precision is better than 2 96 incl temperature drift and line load regulation for operating mode respectively 3 96 during low current mode Current limitation of the regulator ensures fast charge of external bypass capacitors The output voltage is stable for ceramic load capacitors 220 nF If device temperature exceeds TSD1 threshold all outputs OUTx LIN are deactivated except Vcc Hence the microcontroller has the possibility for interaction or error logging In case of exceeding TSD2 threshold TSD2 gt TSD1 also Vcc is deactivated
6. 4 3 N 10 O 1 2 Q FE 0 8 S 2 9 T 3 65 U 1 X 4 3 5 2 Y 6 9 7 5 Note D and E do not include mold Flash or protrusions Mold Flash or protrusions shall not exceed 0 15 mm per side 66 68 Doc ID 022637 Rev 1 ki L99MM70XP Revision history 11 Revision history Table 51 Document revision history Date 04 Jan 2012 Revision 1 Initial release Changes Doc ID 022637 Rev 1 67 68 L99MM70XP Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contai
7. 63 68 SPI control and status registers L99MM70XP Table 49 Status register 4 bits continued Bit name Comment SPIWake Indicates wake up from Vec standby mode via SPI These bits are latched until a read and LINWake Indicates wake up from Vcc standby mode via LIN ricer access on SRA INHWake Indicates wake up from Voc siangp mode via INH Q 64 68 Doc ID 022637 Rev 1 L99MM70XP Package and packaging information 10 10 1 10 2 Figure 19 Package and packaging information ECOPACK In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark PowerSSO 36 package information PowerSSO 36 package dimensions Ks Vp i rm SB SI Doc ID 022637 Rev 1 65 68 Package and packaging information L99MM70XP Table 50 PowerSSO 36 mechanical data Millimeters Symbol Min Typ Max A 2 15 2 45 A2 2 15 2 35 a1 0 0 10 b 0 18 0 36 C 0 23 0 32 p 10 10 10 50 E 7 4 7 6 e 0 5 e3 8 5 F 2 3 G 0 1 G1 0 06 H 10 1 10 5 h 0 4 k 0 8 L 0 55 0 85 M
8. Address Name Access Content 01h Control register 1 Read write Bridge control watchdog trigger 02h Control register 2 Read write High low side control EC control 03h Control register 3 Read write Bridge recovery mode bridge PWM mode LIN HS recovery and PWM mode LS recovery and PWM 04h Control register 4 Read write mode current monitor 11h Status register 1 Read clear Overcurrent diagnosis 12h Status register 2 Read clear Open load diagnosis 13h Status register 3 Read clear WD status supply voltage and EC diagnosis 14h Status register 4 Read clear LIN diagnosis thermal status Configuration 3Fh register Read write Table 31 ROM memory map Address Name Access Content 00h ID Header Read only 4300h ASSP ST SPI 01h Version Read only 0000h engineering sample 02h Product code 1 Read only 4800h dec 72 03h Product code 2 Read only 4800h ASCII H 3Eh SPI frame ID Read only 4200h watchdog available 24 bit ST SPI Na Doc ID 022637 Rev 1 53 68 SPI control and status registers L99MM70XP 9 1 6 Control registers Table 32 Control registers 1 Control register 1 01h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset state 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Mania OUTS OUTS OUT4
9. KY L99MM70XP Integrated microprocessor driven device intended for LIN controlled exterior mirrors Features 5 V low drop voltage regulator 150 mA max m Embedded LIN transceiver 2 0 2 1 compliant and SAEJ2602 compatible m Independent control of mirror adjustment motors m One full bridge for 3 A load Ron 300 ma m Two three half bridges for 0 5 A load Ron 1 6 Q m One configurable high side driver for up to 1 5 A load Ro 500 mg 10 Watt bulb control or 1600 ma LED control m Two high side driver for 0 5 A load Ron 1600 mQ m One low side driver 0 5 A load Ron 1600 mQ used as half bridge with high side driver for independent mirror axis control m One high side driver for 6 A load Ron 90 mQ m One high side driver for 0 5 A load Ron 1600 mQ to supply an external MOSFET to drive an EC glass m Integrated EC glass control via an external MOSFET with fast discharge path EC glass can be discharged to GND or to 1 V m Programmable soft start function to drive loads with higher inrush currents 56 A 51 5 A m Very low current consumption modes m All outputs short circuit and overtemperature PowerSSO 36 m Charge pump output for active reverse polarity protection via an external N channel MOSFET m STM standard serial peripheral interface for control and diagnosis m INH input for external CAN transceiver Applications m LIN controlled mirror Description The
10. OUT4 OUTS OUTS OUT2 OUT2 OUT1 OUT1 NINT RST cup Stby Go WD HS LS HS LS HS LS HS LS HS LS EN LEV Sel Stby Trig Table 33 Control registers 1 bits Bit name Comment OUT5HS OUT5LS OUT4HS OUT4LS WEE l ng If a bit is set the selected output driver is switched on If the corresponding PWM enable bit is set OUT3HS also the driver is activated only if the associated PWM input signal is high OUT3LS The outputs of OUT1 OUT5 are half bridges If the bits of the HS and LS drivers of the same half bridge are set both drivers are deactivated and the output is set to high impedance OUT2HS OUT2LS OUT1HS OUT1LS Enable NINT output NINTEN 0 RXD output has only RXD functionality 1 RXD output can work also as NINT output Select Vcc reset level RSTLEV 0 4 7V 1 3 5V Monitor the Icc current consumption during Vcc stangpgy mode ICMP 0 watchdog disabled only if lec lt Iomp 1 watchdog disabled Standby select sTBvsEL 0 VBArstandby 1 VCC standby This bit is a one shot bit it is read always O 1 execute standby mode GOSTBY This bit is a one shot bit it is read always O Watchdog trigger WDTRIG This bit has to be toggled regularly if the watchdog is active The watchdog can be triggered either by this bit or by bit O of the configuration register 54 68 Doc ID 022637 Rev 1 ky L99MM70XP SPI control and status registers Table 34 Control registers 2 Control register 2 02h
11. Bit 15 14 13 12 11 10 9 8 Y 6 5 4 3 2 1 0 Reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name reserved ECFDLS ECVLS OUT9 OUT8HS2 OUT8HS1 OUT7 OUT6 ECND EC5 EC4 EC3 EC2 EC1 ECO ECON Table 35 Control registers 2 bits Bit name Comment reserved Reserved bit has always to be written to O and reads always 0 1 switch on the ECFD LS driver 0 switch off the ECFD LS driver 1 switch on the ECV LS driver ECVLS 0 switch off the ECV LS driver If the ECVPWM1 bit CR4 Bit4 is also set then the ECV output is controlled by the PWM1 input 1 switch on the OUT9 HS driver OUT9 0 switch off the OUT9 HS driver If the OUT9PWM1 bit CR4 Bit1 1 is also set then the OUT9 output is controlled by the PWM1 input OUT8HS2 11 switch off the OUT8 HS driver 10 switch on the OUT8 HS driver high current mode 01 switch on the OUT8 HS driver low current mode OUT8HS1 00 switch off the OUT8 HS driver If the OUT8PWM bit CR4 Bit10 is also set then the OUT8 output is controlled by the PWM3 input 1 switch on the OUT7 HS driver 0 switch off the OUT7 HS driver If the OUT7PWM1 bit CR4 Bit9 is also set then the OUT7 output is controlled by the PWM1 input This bit is disabled if ECON 1 In this case OUT7 is switched on permanently 1 switch on the OUT6 HS driver OUT6 0 switch off the OUT6 HS driver If the OUT6PWMO bit CR4 Bit8 is also set th
12. Electrical characteristics L99MM70XP Figure 15 LIN transmit and receive timing P t rxpat ra Ungar V no i i time V LIN i i time V ro i t Rxpar I AG00029V1 8 11 SPI and PWM inputs 8 11 1 DC characteristics The voltages are referred to ground and currents are assumed positive when the current flows into the pin 6 V lt Vs x 18 V all outputs open Tamp 40 C 125 C unless otherwise specified Table 23 DC characteristics Symbol Parameter Test condition Min Typ Max Unit Inputs CSN CLK DI PWM1 PWM2 PWMS3 Vit Input voltage low level Vs 13 5V 0 3 Voc Vin Input voltage high level Vg 13 5 V 0 7 Voc V Vinys Input hysteresis Vs 13 5V 500 mV Rcsn in CSN pull up resistor Vs 13 5 V 0 lt Vogn lt 0 7 Voc 30 120 250 kQ Rok in CLK pull down resistor Vs 13 5 V Vg 1 5 V 30 60 150 kQ Rot in DI pull down resistor Vs 13 5 V Vp 1 5 V 30 60 150 kQ Rpwm1 in PWM1 pull down resistor Vg 13 5 V Vpwm1 1 5 V 30 60 150 kQ Rpwwe in PWM2 pull down resistor Vs 13 5 V Vpwm2 1 5 V 30 60 150 kQ PWM3 See Section 8 9 5 INH PWMS input Output DO VoL Output voltage low level log 2 5 mA Vg 13 5 V 0 3 Vcc V VoH Output voltage high level lon 5MA Vg 13 5 V 0 7 Voc 46 68 Doc ID 022637 Rev 1 Q L99MM70XP Electrical characteristics 8 11 2 8 11 3 Na AC characteristics The voltage
13. RDY Wake Wake Wake Table 49 Status register 4 bits Bit name Comment WDFAIL3 These bits are not clearable are WDFAIL2 cleared with a proper watchdog trigger Nr of watchdog fails mana WDFAIL1 or if the chip is sent to Veat standby by the watchdog WDFAILO Forced sleep This bit is set if the chip has been set to Vgar stangpy mode WD by the watchdog These bits are latched until a read and Forced sleep This bit is set if the chip has been set to Vgar standby mode clear access on SR4 TSD by a thermal shutdown DEVSTATE1 Signal device state DEV DEV State STATE1 STATE2 0 0 Active 0 1 VCC standby 1 0 Vear Standby or POR These bits are latched until a read and DEVSTATEO 1 1 Flash clear access on SR 4 The device state is updated with any state transition and with a read and clear command on status register 4 Therefore the first read operation after entering active mode or flash mode reads the last device state Read operations after a read and clear operation reads the current device state After power on reset the device state is VBAT standby VCCRestart2 VCCRestart1 Nr of TSD restart trials These bits si latcned unul a BAHANG clear access on SR 4 VCCRestartO Not ready This bit is set for 200us after switching from XO NOTRDY standby to active mode It is cleared automatically While oae cigarable it iS ceated the bit is set the output drivers are disabled y Na Doc ID 022637 Rev 1
14. Switching times hence the off time of the PWM input signal should be at least 300 us Doc ID 022637 Rev 1 19 68 Description L99MM70XP 3 10 4 3 10 5 20 68 Cross current protection The half bridges of the device are cross current protected by an internal delay time If one driver LS or HS is turned off the activation of the other driver of the same half bridge is automatically delayed by the cross current protection time After the cross current protection time is expired the slew rate limited switch off phase of the driver is changed to a fast turn off phase and the opposite driver is turned on with slew rate limitation Due to this behavior itis always guaranteed that the previously activated driver is completely turned off before the opposite driver starts to conduct Programmable soft start function Loads with startup currents higher than the overcurrent limits e g inrush current of lamps start current of motors and cold resistance of heaters can be driven by using the programmable soft start function i e overcurrent recovery mode Each driver has a corresponding overcurrent recovery bit If this bit is set the device automatically switches the outputs on again after a programmable recovery time The duty cycle in overcurrent condition can be programmed by the SPI interface to about 12 96 or 25 Yo The PWM modulated current provides sufficient average current to power up the load e g heat up the bulb unt
15. kV All pins charge device model 500 V 750 V Corner pins charge device model HBM with all unzapped pins grounded With external components According charged device model JEDEC JESD22 C101D PONS HBM human body model 100 pF 1 5 kQ according to MIL 883C Method 3015 7 or EIA JESD22A114 A For detailed information please see EMC report from IBEE Zwickau available on request Doc ID 022637 Rev 1 31 68 Thermal data L99MM70XP 7 Thermal data Table 7 Operating junction temperature Symbol Parameter Value Unit Tj Operating junction temperature 40 to 150 C Note Rinja typical value without PCB Table 8 Temperature warning and thermal shutdown Symbol Parameter Min Typ Max Unit Twon Thermal overtemperature warning threshold TO 130 140 150 C Tsp1 orr Thermal shutdown junction temperature 1 TO 140 150 160 C Tspeorr Thermal shutdown junction temperature 2 TO 150 160 170 C 1 Non overlapping Figure 9 Thermal data of PowerSSO 36 and PowerSO 36 Pad soldered 35 PowerSSO 36 double side 2 GND layers 30 4 PowerSSO 36 double side 2 GND layers Via s PSO 36 double side 2 GND layers 25 4 PSO 36 double side 2 GND layers Via s 20 o e I 4 15 N 10 4 51 0 T T T T 1 E 04 1 E 03 1 E 02 1 E 01 1 E 00 1 E 01 1 E 02 1 E 03 Time s GAPGMS00013 32 68 Doc ID 022637 Rev 1 ky L99MM70X
16. t in trin gt cSN HI min 80 Yo CSN 44 50 20 Yo 80 0 Output voltage ofadrver INSISTS Oe SSS Se MPE AAS xe se ter ene eet 90 4 4 20 ton ge 8096 utputvoltage I ERE EOM OFF state ON state 50 20 GAPGMS00016 ky Doc ID 022637 Rev 1 39 68 Electrical characteristics L99MM70XP 8 9 3 Current monitoring The voltages are referred to ground and currents are assumed positive when the current flows into the pin 8 V lt Vs 16 V Tamb 40 C 125 C unless otherwise specified Table 19 Current monitoring Symbol Parameter Test condition Min Typ Max Unit local llocs 3 5 A ii dicun Overcurrent threshold to supply or local GND Vg 13 5 V sink and source 0 75 1 25 A llocsl loca llocel Iloc7 Overcurrent threshold to supply Vg 13 5 V source 0 75 1 25 A Overcurrent threshold to supply in Vg 13 5 V source 15 2 5 A low on resistance mode llocs vercurrent threshold to supply in Vg 13 5 V source 0 35 0 65 A high on resistance mode llocg Overcurrent threshold to supply Vg 13 5 V source 6 10 A llocecvl Output current limitation to GND Vs 13 5 V sink 0 72 125 A llocEcrp l Duration of overcurrent troc Filter time of overcurrent signal conditionito ca bikes Bt bil 10 55 100 Hs Recove
17. 1 but are realized in different stand alone LIN transceivers microcontrollers to switch the application back to normal operation mode Dominant TXD time out A permanent low level on pin TXD would force the bus into a permanent dominant state blocking all network communication If pin TXD remains at low level for longer than the TXD dominant timeout tyom TXp the transmitter is disabled The status bit is latched and can be read and optionally cleared by SPI The transmitter remains disabled until the status register is cleared This feature can be disabled via SPI LIN BUS permanent recessive If TXD changes to low level but the bus does not follow within trec jy the transmitter is disabled The status bit is latched and can be read and optionally cleared by SPI The transmitter remains disabled until the status register is cleared LIN BUS permanent dominant If a dominant state on the bus persists for longer than tgomLin a permanent dominant status is detected The status bit is latched and can be read and optionally cleared by SPI The transmitter of the transceiver is not disabled Note A wake up caused by a message on the bus starts the voltage regulator and the microcontroller to switch the application back to normal operation mode 3 12 3 Wake up from LIN bus In standby mode the L99MM70XP can receive a wake up from LIN bus For the wake up feature the L99MM70XP logic differentiates two different conditions 22 68 Doc ID 0
18. 2 2 us edge 44 68 Doc ID 022637 Rev 1 ky L99MM70XP Electrical characteristics Table 22 LIN continued Symbol D1 Parameter Duty cycle 1 Test condition THgpec max 0 744 Vg THpom max 0 581 Vg Vs 7 to 18 V tpit 50 HS D1 tpus rec min 2 tpt Reus 1 kQ Cgus 1 nF Reus 660 Q Cpus 6 8 nF Reus 500 Q Cpus 10nF Min 0 396 Typ Max Unit D2 Duty cycle 2 THgec min 0 422 Vs THpom min 0 284 Vs Vs 7 6to 18 V toit 50 Us D2 tpus rec max 2 tpi Reus 1 kQ Cpus 1 nF Reus 660 Q Cpus 6 8 nF Reus 500 Q Cpus 10nF 0 581 D3 Duty cycle 3 THrec Max 0 778 Vs THpom max 0 616 Vs Vs 7 to 18V tpi 96ps D3 tgus_rec min 2 tpit Reus 1 kQ Cgus 1 nF Reus 660 Q Cpus 6 8 nF Reus 500 Q Ceus 10nF 0 417 D4 Duty cycle 4 THrec min 0 389 V s THpom min 0 251 Vg Vs 7 6 to 18V tp Q6uS D4 igus rec max 2 tpi Reus 1 kQ Cpus 1 nF Reus 660 Q Ceus 6 8 nF Reus 500 Q Ceus 10nF 0 590 tdom TXD tdom LIN TXD dominant time out BUS dominant time out 12 ms 12 ms trec LIN BUS recessive time out 40 us LIN Flash mo SRFLASH de LIN slew rate falling edge in Flash mode Active mode LIN slew rate 80 to 20 Vg Vg 13 5 V Reus 150Q9 Cpus 1nF 13 V us Q Doc ID 022637 Rev 1 45 68
19. 5 Programmable soft start function and the status bit is cleared automatically Otherwise the output stays off until the status bit is cleared The outputs are automatically switched off in case of passive mode Vg undervoltage Vs overvoltage thermal shutdown TSD1 and TSD2 or stuck at 1 0 condition at DI High side driver outputs The device provides a total of 4 high side outputs OUT6 7 8 9 to drive LED or defroster The high side outputs are protected against Overvoltage and undervoltage can be masked by SPI Overload short circuit e Overtemperature with pre warning If the output current exceeds the current shutdown threshold the output transistor is turned off and the corresponding diagnosis bit of the output is latched The status can be read and cleared from SPI If the overcurrent recovery mode is set for this output the output is switched on again in order to provide a soft start function see Section 3 10 5 Programmable soft start function and the status bit is cleared automatically Otherwise the output stays off until the status bit is cleared The outputs are automatically switched off in case of passive mode Vs undervoltage Vs overvoltage thermal shutdown TSD1 and TSD2 or stuck at 1 0 condition at DI Loss of ground or ground shift with externally grounded loads ESD structures are configured for nominal currents only If external loads are connected to different grounds the current load must be limited
20. 9 SPI control and status registers 9 1 Functional description of the SPI For a general description of the SPI please refer to chapter Serial peripheral interface ST SPI standard 9 1 1 SPI communication flow At the beginning of each communication the master can read the contents of the lt SPI frame ID register ROM address SEh of the slave device This 8 bit register indicates the SPI frame length 24 bit and the availability of additional features Each communication frame consists of a command byte which is followed by 2 data bytes The data returned on DO within the same frame always starts with the Global Status Bytes It provides general status information about the device It is followed by 2 data bytes i e in frame response For write cycles the Global Status Byte is followed by the previous content of the addressed register 9 1 2 Command byte Table 27 Command byte Command byte Data byte 1 Data byte 2 Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name OC1 OCO A5 A4 A3 A2 A1 AO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO OCx operation code Ax address Dx data bit Each communication frame starts with a command byte It consists of an operating code which specifies the type of operation Read Write Read and Clear Read Device Information and a 6 bit address If less than 6
21. ECFD to a low voltage against the internal source follower may lead to an overcurrent at pin ECFDHS or thermal shutdown Na Doc ID 022637 Rev 1 41 68 Electrical characteristics L99MM70XP Figure 13 Electrochrome mirror driver with mirror referenced to ground SPI Figure 14 Electrochrome mirror driver with mirror referenced to ECFD for negative discharge vs All components must be placed close together and connected with a very low impedance i B Drop Regulator DPPRDPPPDPI UI i 6 Bit resolution Fast i Discharge P npt reached Fast Discharge EC Mirror pitage too high Fast EC Glas dott aval Lee aT Brightening GAPGMS00017 SPI All components must be placed close together and connected with a very low impedance To 1 o 1D 6 Bit resolution Fast Discharge Fast EC Glas BO Brightening GAPGMS00018 42 68 Doc ID 022637 Rev 1 Na L99MM70XP Electrical characteristics 8 9 5 INH PWM3 input The voltages are referred to ground and currents are assumed positive when the current flows into the pin 8 V lt Vs 16 V Tamp 40 C 125 C unless otherwise specified Table 24 INH PWM3 input Symbol Parameter Test condition Min Typ Max Unit Wake up activate threshold
22. Hi threshold current monitor mI a os m Vcctai Vcc fail threshold Voc forced 2 V 8 5 Reset output Vcc supervision The voltages are referred to ground and currents are assumed positive when the current flows into the pin 4 V lt Vg 28 V Tamb 40 C 125 C unless otherwise specified Table 13 Reset output Vcc supervision Symbol Parameter Test condition Min Typ Max Unit Vvcc increasing CHI s00 4 6 47 485 V Vari Reset threshold voltage 7 G f vcc decreasing CR1 Bit4 0 4 5 4 6 4 7 V Threshold voltage 1 VRT1HYST hysteresis 0 1 Y Vvcc increasing CR Bit4 17 3 6 3 7 39 V Vnr2 Reset threshold voltage2 V vcc aecreasing CR1 Bit4 1 3 0 33 3 5 V Threshold voltage 2 VRT2HYST hysteresis 0 4 V Vnres Reset Pin low output voltage Vcc gt 1 V Ines 1 MA 0 2 0 4 V Rnres_ Reset pull up int resistor VunEs 4 V 60 110 204 ka P CNRES 100 pF tnn Reset reaction time yee en 40 us 1 Delay time see typp below Section 8 6 Watchdog 8 6 Watchdog 4 5 V Vs lt 28 V Tamb 40 C 125 C unless otherwise specified see Figure 10 and Figure 11 Table 14 Watchdog Symbol Parameter Test condition Min Typ Max Unit tw Watchdog cycle time 100 134 180 ms twor Watchdog reset pulse time 1 5 2 3 2 9 ms ky Doc ID 022637 Rev 1 35 68 Electrical characteristics L99MM70XP
23. LIN 2 1 transceiver 15 TXD Transmitter input of the LIN 2 1 transceiver Doc ID 022637 Rev 1 9 68 Pin definitions and functions L99MM70XP Table 2 Pin definition and functions continued Pin Symbol Function Power supply voltage external reverse protection required 16 Vs Reg for this input a ceramic capacitor as close as possible to GND and an electrolytic capacitor to buffer the voltage during negative transients is recommended 17 LIN LIN bus line High side driver output 6 The output is built by a high side switch and is intended for resistive loads hence the internal reverse diode from GND to the output is missing For ESD reason a diode to GND 23 OUT6 is present but the energy which can be dissipated is limited The high side driver is a power DMOS transistor with an internal parasitic reverse diode from the output to Vs bulk drain diode The output is overcurrent and open load protected Inhibit input 24 INH PWMS wake up from external CAN transceiver This pin has a second functionality The microcontroller can use the INH signal to provide a third PWM input for the output OUT8 Charge pump output 25 CP This output is provided to drive the gate of an external n channel power MOS used for reverse polarity protection see Figure 1 PWM1 input 26 PWM1 This input signal can be used to control the drivers OUT1 OUT5 OUT7 and OUT9 by an external PWM
24. see Figure 8 A timer is started and the voltage regulator is deactivated for trsp 1 s During this time all other wake up sources LIN are disabled After 1 s the voltage regulator tries to restart automatically If the restart fails 6 times without clearing and thermal shutdown condition still exists the L99MM70XP enters the Vgat standby mode In case of short to GND at Vcc after initial turn on Vcc lt 2 V for at least 4 ms the L99MM70XP enters the Veat standby mode Reactivation wake up of the device can be achieved with signals from LIN or INH 12 68 Doc ID 022637 Rev 1 ky L99MM70XP Description Figure 3 Voltage regulator operation Specification Parameters te V1 undervoltage Filter Time trr Reset Reaction Time twor Watchdog Reset Pulse Time V PoR Poweron Reset LLL lecccocneocoenenecccauudu threshold Control Registersare set to default values Vs UndervoltageBit istset t gt ter PAASA AA AA PARRE EP S 1 1 1 l 1 1 1 No Reset generated is set kai gt 4ms t t NResej VCC short detected uius gt High gt Vbatt standby l 1 Low a ee re aa GAPGMS00007 3 2 Power control in operating modes The L99MM70XP can be operated in 4 different operating modes e Active Flash e Vcc standby Vnpar standby 3 2 1 Active mode All functions are available After at most 300 us the outputs can be enabled 3 2 2 Flash mo
25. signal Low active reset output to the microcontroller zi pes internal pull up of typ 100kQ 28 PWM2 PWM2 input This input signal can be used to control the driver OUT6 by an external PWM signal 29 ECDR ECDR using the device in EC control mode this pin is used to control the gate of an external MOSFET High side driver output 8 30 OUT8 see OUT6 Note This output can be configured to supply a bulb with low on resistance ora LED with higher on resistance in a different application High side driver output 7 OUT6 31 OUT7 EC 599 m mi Note Beside the bit 8 in control register 2 this output can be switched on setting bit O for electrochrome control mode with higher priority ECFD 33 ECFD using the device in EC control mode this pin is used as virtual GND for the EC glass For EC glasses that require a negative discharge voltage this supplies the fast discharge voltage If no EC glass is used this pin must be connected to ground ECV Using the device in EC control mode this pin is used as voltage monitor input For fast 34 ECV discharge an additional low side switch is implemented This pin can be used as stand alone low side as well This output is intended for resistive loads only 10 68 Doc ID 022637 Rev 1 ky L99MM70XP Pin definitions and functions Figure 2 Pin connection top view GND VS OUT9 OUT9 OUT2 OUT3 VS CSN CM DO DI CLK VCC RXD TXD VS Reg LIN GND PowerSSO 36
26. the total WD time 1 1 lt 3 3 of the total WD time Overcurrent diagnosis CE In case of an overcurrent event on ECFDHS the status bit is set and the output driver is disabled ECFDHSOL The open load detection monitors the load current in the ECFDHS If the load current is below the under current detection threshold for at least tyo 2 ms the open load bit is set ECVNR ECV voltage not reached Two comparators monitor the voltage at pin ECV in electrochrome mode If this voltage is below above the programmed target these bits signal the difference after at least 32 us The bits are ECVO ECV voltage too high not latched and may toggle after at least 32 us if the ECV voltage has not yet reached the target TSD2 Thermal shutdown 2 gt 160 C TSD1 Thermal shutdown 1 gt 150 C TW Thermal warning 140 C 62 68 Doc ID 022637 Rev 1 ky L99MM70XP SPI control and status registers All bits except the WDTIM1 WDTIMO ECVNR and ECVO bits can be reset by a read and clear operation on SR4 Table 48 Status register 4 Status register 4 14h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset state 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 WD WD WD WD Forced Forced Dev Dev vcc vcc VCC NOT SPI LIN INH ame fail fail fail fail SleepWD SleepTSD State State Restart Restart Restart
27. undervoltage event 0 outputs are enabled automatically after an overvoltage undervoltage event OUT50R OUT4OR Overcurrent recovery enable 1 the output is automatically reactivated after a delay time with programmable duty cycle OUTSOR h CR3 Bit14 OUT2OR 0 clear status register to enable the output after an overcurrent event OUT1OR LIN flash mode LINFLASH 0 20 kbit s 1 100 kbit s Dominant TxD time out for the LIN interface LINTXDTout 1 enable the dominant TXD time out for the LIN interface 0 disable the dominant TXD time out for the LIN interface EC voltage limit ECVL 0 max EC voltage 1 2V 1 max EC voltage 1 5V OUT5PWM1 OUT4PWM1 OUT3PWM1 If the PWM enable bit is set and the output is enabled the output is switched on only if the PWM1 input is high and switched off if the PWM 1 input is low OUT2PWM1 OUT1PWM1 56 68 Doc ID 022637 Rev 1 ky L99MM70XP SPI control and status registers Table 38 Control register 4 Control register 4 04h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT9 OUT8 OUT7 OUT6 OUT9 OUT8 OUT7 OUT6 ECV ECV Name OR OR OR OR PWM1 PWM3 PWM1 PWM2 reserved OR reserved PWM1 CM3 CM2 CM1 CMO Table 39 Control register 4 bits Bit name Comment OUT9OR Overcurrent recovery enable OUT8OR 1 the output is automatically reactivated after a delay time with progra
28. 0 0 1 1 CM HS3 active 0 1 0 0 CM HS4 active CMS o 1 0 1 CM HS5 active pud 0 1 1 0 CM HS6 active CMO 0 1 1 1 CM HS7 active 1 0 0 0 CM HS8 active 1 0 0 1 CM HS9 active 1 0 1 0 reserved 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved 58 68 Doc ID 022637 Rev 1 Ly L99MM70XP SPI control and status registers Table 40 Configuration register Configuration register 3Fh Reset state Name ECFD OUT1HS OUTILS WD OUT7 OLMASK OLMASK TRIG OLMASK Table 41 Configuration register bits Bit name Comment The bits 15 to 8 of the configuration register have to be written to O and read always 0 i Mask the ECV ECFD HS and LS and OUT7 open load diagnostics bits status reg 2 bits 11 14 15 T7 AU an open load event is not considered in the open load bit TW OL of the global status register OUTIHS Mask the OUTHS1 open load diagnostic bit status reg 1 bit 1 OLMASK an open load event under current status bit of OUT1HS is not considered in open load bit TW OL of the global status register OUTILS Mask the OUTLS1 open load diagnostic bit status reg 1 bit 0 OLMASK 29 open load event under current status bit of OUT1LS is not considered in open load bit TW_OL of the global status register TW OL Mask the TW OL bit in global status byte MASK a temperature warning or open load event is not considered in the global error flag Trigger the watch
29. 0 07 Vs 0 1 Vs 0 175Vg V VTHrec 7 VTHdom Receiver tolerance VTHont center value 0 475 Vs 0 5 Vg 0 525 Vg V VTHrec VTHdom 2 Receiver wake up VTHwkup rising threshold 1 0 1 5 2 V voltage Receiver wake up VTHwkdwn falling threshold Vs 3 5 Vg 2 5 Vg 1 5 V voltage t Dominant time for Sleep mode edge recessive 64 T LINBUS wake up via bus dominant 050 H l AG AT TA AAP A 40 100 180 mA BUS LIM dominant state TxD 7 V V VLIN VSMAX Input leakage current IBUS PAS dom at the receiver incl Vtxp 5 V VLIN 0 V Vs 13 5V 1 mA pull up resistor Transmitter input lt lgus PAS rec Current in recessive NDS V 8 V lt Viin Vs lt 18 V 20 UA ciis Vlin 2 Vs state Transceiver input laus No cnp current if loss of GND E z Va 0 V lt Vus 18 v 1 1 mA EU f s 13 5V at device Input current if loss of IBUS NO BAT yaa at Device Vs GND 0V VEIN lt 18V 100 pA V LIN voltage level in Active mode Vrxp z 0 V 13 V LINdom dominant state lUN 40 mA LIN voltage level in _ VLINrec recessive state Active mode VTxD 5 V LUN 10 pA 0 8 Vs Vs V LIN output pull up _ LIN transceiver timing Active Mode taxDpd MAX tRXDpar taxDpat t Receiver propagation tRXpdf t 0 5 Vnxp t 0 45 Vun 6 RXDpd delay time tRXpar t 0 5 Vnxp t 0 55 VUN H Vs 13 5 V Crxp 20 pF Reus 1 kQ Cgus 1 nF Symmetry of receiver propagation delay E RXDpd sym time rising vs falling tRXDpd sym tRxDpar RXDpdf
30. 2 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 ky Device SUMMAary 1 6 eae Pin definition and functions 0 0 e ee eee eee Wake up events 0c ree Functional overview truth table Absolute maximum ratings llle ESD protection eee Operating junction temperature l l Temperature warning and thermal shutdown Supply and supply monitoring llli elei Oscillator iie m Power on reset VgREG eese een Voltage regulator Vog sss eee Reset output Vcc supervision llle Watchdog ess eero taasi idas aaka eR n Current monitor output CM 0000 eee eee Charge pump output CP eee On resistance aaah naa DI wipra nepietur RIT Switching times 0000 ee Current monitoring 0c c eee eee Electrochrome control a INH PWMS input CIN AA on eae tes ee as ee Seen DC characteristics liliis AC characteristics llle eese Dynamic characteristics llle Input PWM2 for Flash mode a Command byte res Operation code definition llle Global status byte 0 2 20 0c eee RAM memory map eae ROM memory map 0000 cee ee Control registers 1 llli Control registers 1 bits llle Control registers 2 llle Control registers 2 bits llle Control register 3 ee Con
31. 22637 Rev 1 ky L99MM70XP Description 3 13 Note Normal wake up Normal wake up can occur when the L99MM70XP was set in standby mode while a recessive state was present on the bus A dominant level at LIN for t gt tiinbus switches the L99MM70XP to active mode An interrupt is generated at the RXD NINT pin Wake up from short to GND condition If the L99MM70XP was set in standby mode while LIN was in dominant low state recessive level at LIN for tinpbus switches the L99MM70XP to active mode An interrupt is generated at the RXD NINT pin Serial peripheral interface ST SPI standard A 24 bit ST SPI is used for bi directional communication with the microcontroller During active mode the SPI e Triggers the watchdog e Controls the modes and status of all LO9MM70XP modules incl input and output drivers e Provides driver output diagnostic e Provides L99MM70XP diagnostic incl overtemperature warning L99MM70XP operation status During standby modes the SPI is generally deactivated The SPI can be driven by a microcontroller with its SPI peripheral running in following mode CPOL 0 and CPHA 0 For this mode input data is sampled by the low to high transition of the clock CLK and output data is changed from the high to low transition of CLK This device is not limited to microcontroller with a build in SPI Only three CMOS compatible output pins and one input pin are needed to communicate with the devi
32. 46 8 11 2 AC characteristics een 47 8 11 3 Dynamic characteristics llle 47 8 12 Input PWM2 for Flash mode 0c eee eee 50 SPI control and status registers lees 51 Doc ID 022637 Rev 1 3 68 Contents L99MM70XP 9 1 Functional description of the SPI 0 0 00 c cece eee 51 9 1 1 SPI communication flow liess 51 9 1 2 Command byte rns 51 9 1 3 Operation code definition 00 000 eee eee 51 9 1 4 Global status byte 0 0 a 52 9 1 5 Address mapping 0 000 e eee ees 53 9 1 6 Control registers 54 9 1 7 Status registers ees 60 10 Package and packaging information eL 65 10d ECOPACK us inaetic Ge ied EPNREMD beads DERPI ERSTE 65 10 2 PowerSSO 36 package information cece eee eee 65 11 Revision history dauswcesssasabhx d ERE EE BV AE NEA FERAT RE ERE 67 4 68 Doc ID 022637 Rev 1 ky L99MM70XP List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 4
33. 6 and PowerSO 36 000 0c cece ee eee 32 Watchdog timing RR RH 3 n 36 Watchdog late and safe window 2 2 e 36 Output switching times RR RI Rh 39 Electrochrome mirror driver with mirror referenced to ground 42 Electrochrome mirror driver with mirror referenced to ECFD for negative discharge 42 LIN transmit and receive timing II 46 SPI timing parameters s 48 SPI input and output timing parameters ee 49 SPI maximum clock frequency 0c eee 49 PowerSSO 36 package dimensions liliis 65 Doc ID 022637 Rev 1 7 68 Block diagram L99MM70XP 1 Block diagram Figure 1 Block diagram Veat STD17NF03 10k 100k vs cp VS VREG 300 md NG Charge oum Pump 600 mQ M OUT2 NRES 600 mQ 5V Voltage OUT3 M VCC Regulator 1600 mA o a 5 OUT4 L STSPI 300 md EO o OUT5 DI a 1800 mA AA DO 3 pa ae o OUT6 CLK 05 S CSN t 5 600 1800 mO 10 Watt progr Bulb or OUT8 LED Mode STM8A 5 90 ma 32 k Flash PWM Z PWM2 a OUT PWN3 INH 1600 mQ OUT7 CM CM MUX i EC Glass i ECDR ontrol Block i eoatveosoage 5nF Possibility m ECV 200 nF RX LIN2 0 2 1 CJ ESD EMC Transceiver OUTPUT according 4 SPI setting 2 x 1600 mQ Negative contact of EC glass LIN to be connected to GND GN
34. D 022637 Rev 1 ky L99MM70XP Contents 4 1 1 Overvoltage seiss nen 26 4 1 2 Undervoltage eve ver yee Pa weds ded Ob eee hee ceu Y 26 4 2 Diagnosis functions 42 4 cei e e e RR eR OR he RR RR he KG EE obo wars 27 4 3 Temperature warning and thermal shutdown 2055 28 4 4 Half bridge outputs 2212522206 RES d ER d ESS P ISP S Ag Pd Em rpg 28 4 5 High side driver outputs 62 0204 NG aaa ue RRRERE RI A4 Rd Ka bees 29 Absolute maximum ratings eese 30 ESD protection uuuos3reaekEs DA NBA HAKA E CR gessmanes KNANG 31 Thermal GGE AA ro St Sn RU RC DN D kh 32 Electrical characteristics 33 8 1 Supply and supply monitoring llle 33 8 2 dl Mew PEPPER MES 34 8 3 Power on reset Venga ua ia ea dac Relato R EO Rord dL Ri fa ec 34 8 4 Voltage regulator Vog kak vice xd PADA bae Ho CIE Rp 34 8 5 Reset output Vcc supervision n eee 35 8 6 Watchdog MARA 35 8 7 Current monitor output CM sees 36 8 8 Charge pump output CP ene 37 8 9 Outputs OUT1 OUT9 ECV ECFD 0 0 AA 37 8 9 1 On resistance n 37 8 9 2 Switching times ize BAL EX Rud e ed wurde ed eed 38 8 9 3 Current monitoring ses 40 8 9 4 Electrochrome control e eee tees 41 8 9 5 INH PWM3 input RII III 43 olo Ca AA eee he AA ee E AG 43 8 11 SPIand PWM inputs isse cdl ease CR UR RERO ERR On RR RR 46 8 11 4 DC characteristics een
35. D for standard EC glass ECFD for negative discharge possibility GAPGMS00005 8 68 Doc ID 022637 Rev 1 ky L99MM70XP Pin definitions and functions 2 Pin definitions and functions Table 2 Pin definition and functions Pin Symbol Function Ground 1 18 GND reference potential 19 36 Note For the capability of driving the full current at the outputs all pins of GND must be externally connected 2 7 32 Vs Powert Power supply voltage for outputs OUTX and ECFD external reverse protection required for this input a ceramic capacitor as close as possible to GND is recommended Note For the capability of driving the full current at the outputs all pins of Vs must be 22 Vs Power2 externally connected Pins 2 7 and 32 are internally connected too Pin 22 is the power supply for outputs OUTA 5 and 6 High side driver output 9 the output is built by a high side switch and is intended for resistive loads hence the internal reverse diode from GND to the output is missing For ESD reason a diode to GND OUT is present but the energy which can be dissipated is limited The high side driver is a 3 4 UT9 power DMOS transistor with an internal parasitic reverse diode from the output to Vs bulk drain diode The output is overcurrent and open load protected Note For the capability of driving the full current at the outputs both pins of OUT9 must be externally connected Half bridge outputs 1 2 3 4 5 the out
36. ID 022637 Rev 1 15 68 Description L99MM70XP Figure 4 Operating modes main states VS Vpor Vbat startup All registers set to default Chip reset set to 1 WD trigger every 100ms typ eo EM E We Vewne gt 8 4V typ ie FlashMode Veww lt 7 25V typ oo Active Mode Watchdog OFF x VCC ON Reset Generator active Watchdog active SPI command OR Thermal Shutdown OR VCC fail short to ground OR e 15 x WD fail SPI command Vewm gt 8 4V typ Vpwnz gt 8 4V typ Vbat Standby Mode VCC Standby Mode VCC ON dos a e Reset Generator active Reset Generator off NRES 7 low Watchdog Watchdog OFF Outputs OFF Thermal Shutdown TSD2 OR ICC gt Icmp AND ICMP 0 AND 15 x WD fail T OFF If ICC lt lemp or ICMP 1 GAPGMS00008 3 5 Interrupt In case of Vec standby mode and Icc gt Icmpris the device remains in standby mode the Vee regulator switches to high current mode and the watchdog is started No interrupt is generated 16 68 Doc ID 022637 Rev 1 Ly L99MM70XP Description 3 6 If bit NINTEN CR1 Bit5 default value is set is set the RXD pin works also as interrupt output in case of wake up by LIN or INH or SPI in Vcc siangpy mode This pin is pulled down for 56 us If it is not set RXD is pulled down for 56us only for LIN wake up Time out w
37. L99MM70XP is a microcontroller driven multifunctional system ASSP dedicated for LIN controlled wing mirror applications The device contains a voltage regulator to supply the microcontroller and a LIN2 1 physical layer Up to 3 DC motors and five grounded resistive loads can independently be driven with four five half bridges and five high side driver The EC glass control block provides overvoltage protection with a fast discharge path versus GND and a negative discharge path for future EC glass characteristics The integrated ST SPI controls all operation modes forward reverse brake and high impedance and provides all the diagnostic information protected Table 1 Device summary m Two thermal shutdown thresholds and early Order codes temperature warning Package m Current monitor output for all high side drivers Tube Tape and reel m Open load diagnostic for all outputs PowerSSO 36 L99MM70XP L99MM70XPTR m Overload diagnostic for all outputs m 3 PWM control signals for all outputs January 2012 Doc ID 022637 Rev 1 1 68 www st com Contents L99MM70XP Contents 1 Block diagram us acra on Ca ee C 80 DN rl UG C n 8 2 Pin definitions and functions seelllleeeeees 9 3 Description os ssasss ERE 6 be baa REA E EE RE EE RERO REGE E ds 12 3 1 Voltage regulator is shade AR KAKA Ru RERO ERE ER ERE TERRE RI REEE 12 3 2 Power control in operating modes sellers 13 3 2 1 Activo mode
38. P Electrical characteristics 8 Electrical characteristics 8 1 Supply and supply monitoring The voltages are referred to ground and currents are assumed positive when the current flows into the pin 6 V x Vs lt 18 V all outputs open Tamp 40 C 125 C unless otherwise specified Table 9 Supply and supply monitoring Symbol Parameter Test condition Min Typ Max Unit VsuvoN Vs undervoltage threshold voltage Vs increasing 5 7 7 2 V Vsuv ofr Vs undervoltage threshold voltage Vs decreasing 5 5 6 9 V Vsuv hyst Vs undervoltage hysteresis Vsuv ON Vsuv OFF 0 5 V Vsovorr Vs overvoltage threshold voltage Vs increasing 18 1 24 5 V VsovoN Vg overvoltage threshold voltage Vg decreasing 17 5 235 V Vsov nyst Vs overvoltage hysteresis Vsov orr Vsov on 1 V Ivs ey Current consumption in active mode Vs 13 5 V TXD LIN hign 1 7 20 mA lvsnEG ac Current consumption in active mode VSREQ sa pRO RIN Migh 6 12 mA VCC Current consumption in VBAT standby Ve 13 5 VINE 1 A VS BAT mode g 13 u Current consumption in Vpaz sear ode p BAT standby y 13 5 VOO 2 pA Current consumption in Vgar IVSREG BAT mode BATstandby Vereg 13 5 VO 1 8 16 pA Current consumption in Vpar IVSREG BAT mode BATstandby Vereg 13 5 VO 2 12 24 pA Current consumption in Vgar stangpy Va V 2135 V VS VBAT mode with a p
39. aa eiae bere Snare ow n nem a ge cm e Ropa 13 3 2 2 Flash mode a apa dees rox At b Rao een DER ioe des 13 3 2 3 VCC standby MOdeE n a sunsun iua teed ea eade orsus SR Re ees 14 3 2 4 VBAT standby MOQE aai o Ba KAG KAKA ene b ence ea eR ah AA NUR ede 14 3 8 Wake up events eel lee 14 3 4 Functional overview truth table llli 15 3 5 Interrupt ain hea ees ene a ke Ux We aa RO A wade RC GNG 16 3 6 Time out watchdog 144 aa na NG AGA ABAKADA D EC EQ GB kA ET AES PEL 17 3 7 Passive MOTEL uaa espe MEE Ra E n AE NE EE RR qx 18 3 8 Haset oulpul NRES kikagpanaaa aap BANNA Kha rre phe xs DAA 18 OS Meca educi et puede end ped aed E Rea e eue die e ene dna ence ees 19 3 10 Output drivers QUT1 OUTS suisse debate weet ees RR twee E RE 19 3410 1 Load condition s rres er a eee eee RR RE eo a ERGO ee ea eee ERE 19 3 10 2 Current monitor 0 00 tee 19 3 10 3 PWMinputs 0 IRI IRR IRI e 19 3 10 4 Cross current protection rers 20 3 10 5 Programmable soft start function cee eee 20 3 11 X Controller for electrochromic glass liliis 21 3 12 LIN bus interface rh 22 3 12 1 General features eese 22 3 12 2 LIN error handling BB IR 22 3 12 3 Wake up from LIN bus IIS 22 3 13 Serial peripheral interface ST SPI standard 23 4 Protection and diagnosis e eee eee 26 4 1 Power supply fail ees 26 2 68 Doc I
40. andby Forced Vpat standby after WD fail forced Vgar stangpy after overtemperature Watchdog timer state diagnosis of watchdog Passive mode SPI communication error Doc ID 022637 Rev 1 27 68 Protection and diagnosis L99MM70XP 4 3 4 4 28 68 Figure 8 Thermal shutdown protection and diagnosis OTodevC TSD TSD1 i agi a Al outputs except VCC off TSD2 Bit is set TSD1 Bitis set Wake up event SPI command Read and Clear Power on reset L Warning Vear standby All outputs off Standby Modes SPI command Read and Clear OR Power on reset Power on reset Active i Standby J GAPGMS00012 Temperature warning and thermal shutdown See Figure 8 Half bridge outputs The device provides a total of 5 half bridge outputs OUT1 2 3 4 5 to drive inductive loads e g motor The half bridges are protected against Overvoltage and undervoltage e Overload short circuit e Overtemperature with pre warning Doc ID 022637 Rev 1 ky L99MM70XP Protection and diagnosis 4 5 Note If the output current exceeds the current shutdown threshold the output transistor is turned off and the corresponding diagnosis bit of the output is latched The status can be read and cleared from SPI If the overcurrent recovery mode is set for this output the output is switched on again in order to provide a soft start function see Section 3 10
41. are assumed positive when the current flows into the pin 8 V Vg lt 16 V Tamp 40 C 125 C unless otherwise specified Table 18 Switching times Symbol Parameter Test condition Min Typ Max Unit Ur Vg 13 5 V td ONH P o a corresponding low side 20 40 80 us driver is not active N 2 3 Output delay time high side torfy s af y 9 Vg 13 5 V MAG 45 150 300 us 38 68 Doc ID 022637 Rev 1 Na L99MM70XP Electrical characteristics Table 18 Switching times continued Symbol Parameter Test condition F Output delay time low side kaa Ha ouad dONL driver on p 9 driver is not active 1 2 Min Typ Max Unit 15 30 70 us Output delay time low side Rioag 16 at OUT1 5 and OUT8 in low on resistance mode Rioad 4 at OUTY Boom tcc is the switch on delay time if complement in half bridge has to switch off Figure 12 Output switching times dOFFL driver off Vg 13 5 V MEANS 80 150 300 us ld HL tecONLS OFFHS ld oFF H Cross current protection time a 200 410 us ld LH tcc ONHS OFFLS 7 td OFF L dVour dt Slew rate of OUTx Vg 13 5 V WAG 0 1 02 0 6 V us Rioag 64 at OUT2 3 4 6 7 ECV ECFD and OUTS in high on resistance mode CSN low to high data from shit register is transferred to output power switches
42. atchdog During normal operation the watchdog monitors the microcontroller within a 100 ms trigger cycle In VBAT stangpy and flash program modes the watchdog circuit is automatically disabled After power on or standby mode the watchdog is started immediately with the normal cycle time 100 ms The microcontroller has to run its own setup and then to trigger the watchdog via the SPI The trigger is finally accepted when the CSN input becomes high after the transmission of the SPI word Writing 1 to the watchdog trigger bit restarts the watchdog Subsequently the microcontroller has to serve the watchdog by alternating the watchdog trigger bit within the safe trigger area refer to Figure 10 A correct watchdog trigger signal immediately starts the next cycle If the micro does not serve the watchdog in time the watchdog pulls low the NRES output for 2 ms At the same time the watchdog failure counter WDFAIL is incremented by 1 and the device enters passive mode After 8 watchdog failures in sequence the Vcc regulator is switched off for 200 ms If subsequently 7 additional watchdog failures occur the Vcc regulator is completely turned off and the device goes into Vgar stangpy mode until a wake up occurs In case of a watchdog failure the outputs OUTx are switched off and the device enters passive mode i e all control registers are set to default values Doc ID 022637 Rev 1 17 68 Description L99MM70XP Fig
43. bits are required the remaining bits are unused but are reserved Operation code definition Table 28 Operation code definition OC1 OCO Meaning 0 0 Write Mode 0 1 Read Mode 1 0 Read and Clear Mode 1 1 Read Device Information Doc ID 022637 Rev 1 51 68 SPI control and status registers L99MM70XP The Write Mode and Read Mode operations allow access to the RAM of the device A Read and Clear Mode operation is used to read a status register and subsequently clear its content The Read Device Information allows access to the ROM area which contains device related information such as ID Header Product Codes Silicon Version and lt SPI frame ID 9 1 4 Global status byte Table 29 Global status byte Global status byte 6 5 4 3 2 1 0 CO ER NRECE TW OL UV OV OC Vee FAIL PASSIVE 0 0 0 0 0 0 0 Bit Global error flag Failures of Bits 0 6 are always linked to the global error flag This flag is generated by an OR combination of all failure events of the device If the TW OL MSK bit is set in the configuration GL ER register TW OL is not used as an input to this bit GL ERis reflected via the DO pin while CSN is held low and no clock signal is available The flag remains as long as CSN is low This operation does not cause the communication error bit in the Global status bytes to be set Communication error If the number of clock pu
44. c or Vpo 50 7 Vcc t CLK fall BOvaid PAn S Ph Yar Tey alling unti vali CEKOV 9 Vbo 0 3 Voc Or Vpo 20 7 Voc 2 Cpo 100 pF Vs 13 5 V 50 1 230 s CSN setup time CSN low t i Vs 213 5V SCSN before rising edge of CLK o 400 is DI setup time DI stable before t Vs 13 5 V SDI rising edge of CLK S ngo ng DI hold time DI stable after t i Vs 13 5 V HI rising edge of CLK 5 200 n tucik minimum CLK high time Ve 13 5V 115 ns tici minimum CLK low time Ve 5 13 5V 115 ns t4csn minimum CSN high time Ve 13 5V 4 us lecik CLK setup time before CSN Vg 13 5 V 400 jii rising Doc ID 022637 Rev 1 47 68 Electrical characteristics L99MM70XP 48 68 Table 25 Dynamic characteristics continued Symbol Parameter Test condition Min Typ Max Unit t po DO rise time Cpo 100 pF Vg 13 5 V 80 140 ns tipo DO fall time Cpo 100 pF Vs 13 5 V 50 100 ns rise time of input signal DI f 13 5 V rin CLK CSN Marang pee ae fall time of input signal DI Va 135V tin letk CSN gem s a Figure 16 SPI timing parameters yt tro BI l CSN N N l l Pitcsnay te ra Lcsvor gt H DO 4 Data out X Data out l l E P gt VE Ke lakay gt i i M tscik w a ES m il eae eee mis it thok I4 lax gt DI lt Data in X Data in GAPGMS00019 Doc ID 022637 Rev 1 ky L99MM70XP Electrical characteristics
45. ce A fault condition can be detected by setting CSN to low If CSN 0 the DO pin reflects the global error flag fault condition of the device see Figure 7 This operation does not cause the communication error bit in the global status byte to be set Doc ID 022637 Rev 1 23 68 Description L99MM70XP Figure 7 SPI global error information output CSN high to low and CLK stays at low Global Error Flag is transfered to DO CSN N l QUU so XAXAMAAA_AAXXAAXXXAAAXXA 7 GAPGMS00011 Chip Select Not CSN The input pin is used to select the serial interface of this device When CSN is high the output pin DO is in high impedance state A low signal activates the output driver and a serial communication can be started The state during CSN 0 is called a communication frame Serial Data In DI The input pin is used to transfer data serially into the device The data applied to the DI are sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register At the rising edge of the CSN signal the contents of the shift register is transferred to data input register The writing to the selected data input register is only enabled if exactly 24 bits are transmitted within one communication frame i e CSN low If more or less clock pulses are counted within one frame the complete frame is ignored This safety function is implemented to avoid an activation of the output stages by a wron
46. de To disable the watchdog feature a Flash program mode is available The mode can be entered if the following condition occurs Vewwe 2 Vriash Watchdog is disabled but all other functions are the same as in active mode Na Doc ID 022637 Rev 1 13 68 Description L99MM70XP Note 3 2 3 3 2 4 3 3 14 68 High level for flash mode selection is Vpwm22 VFfiasn For all other operation modes standard 5 V logic signals are required Vec standby mode Outputs and internal loads are switched off To supply the microcontroller in a low power mode the voltage regulator Vcc remains active The intention of the Vcoc standby mode is to preserve the RAM contents A LIN wake up event sets the device into the active mode and forces the RXD pin to the low level A wake up over INH switches device in active mode and start the watchdog The wake up via SPI switches device in active mode A status bit indicates the wake up source During the Vcc standby mode the current at Vcc is monitored The transition from active mode to Vec stanaby mode is controlled by SPI VBar standby Mode To achieve minimum current consumption during Vgat standby mode all L99MM70XP functions are switched off In Vgat standby Mode the current consumption of the L99MM70XP is reduced to 8 pA The transition from active mode to Vp47 standby mode is controlled by SPI Wake up events A wake up from standby mode switches the device to acti
47. dog WDTRIG This bit has to be toggled regularly if the watchdog is active The watchdog can be triggered either by this bit or by bit O of the Control Register 1 4 Doc ID 022637 Rev 1 59 68 SPI control and status registers L99MM70XP 9 1 7 Status registers Table 42 Status register 1 Status register 1 11h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 1 0 Reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Name ECFDLS ECV OUT OUT OUT OUT OUT5 OUTS OUT4 OUT4 OUT3 OUT3 OUT2 OUT2 OUT1 OUT1 LS 9HS 8HS 7HS 6HS HS LS HS LS HS LS HC HS LS Table 43 Status register 1 bits Bit name ECFDLSOC ECVLSOC OUT9HSOC OUT8HSOC OUT7HSOC OUT6HSOC OUT5HSOC OUTSLSOC OUT4HSOC OUT4LSOC OUT3HSOC OUT3LSOC OUT2HSOC OUT2LSOC OUT1HSOC OUTILSOC Overcurrent diagnosis In case of an overcurrent event the corresponding status bit is set and the output driver is disabled If the overcurrent recovery enable bit is set the output is automatically reactivated after a delay time Comment resulting in a PWM modulated current with a programmable duty cycle If the overcurrent recovery bit is not set the microcontroller has to clear the overcurrent bit to reactivate the output driver 60 68 Doc ID 022637 Rev 1 a L99MM70XP SPI control and status registers
48. ed to pin ECDR for loop stability The target voltage is binary coded with a full scale range of 1 5 V If bit ECVL control register 3 bit 5 is set to 1 the maximum controller output voltage is clamped to 1 2 V without changing the resolution of bits EC lt 5 0 gt When programming the ECVLS driver to on state the voltage at pin ECV is pulled to ground by a 1 6 Ohm low side switch until the voltage at pin ECV is less than dVecypj higher than the target voltage fast discharge The status of the voltage control loop is reported via SPI Bit ECVO status register 3 bit 4 is set if the voltage at pin ECV is higher whereas bit ECVNR status register 3 bit 5 is set if the voltage at pin ECV is lower than the target value Both status bits are valid if the voltage is stable for at least the ECVO ECVNR filter time and are not latched Since OUT7 is the output of a high side driver it contains the same diagnose functions as the other high side drivers e g during an overcurrent detection the control loop is switched off In electrochrome mode OUT10 cannot be controlled by PWM mode For EMS reasons the loop capacitor at pin ECDR as well as the capacitor between ECV and GND have to be placed to the respective pins as close as possible see Figure 13 for details If the electrochrome element is connected between the pins ECV and ECFD instead between ECV and ground a negative voltage can be applied to the device by pulling ECFD to a higher va
49. en the OUT6 output is controlled by the PWM2 input ECFDLS OUT7 EC negative discharge ECND 0 EC negative discharge off 1 EC negative discharge on EC5 EC4 EC3 Reference value for difference voltage amplifier at pin ECV binary coded The full scale value is set in EC2 ECVL CR3 Bit5 If all EC bits are set to zero the reference value is OV EC1 ECO 1 EC control enabled ECON 0 EC control disabled If the EC control is enabled the output OUT7 is switched on permanently Na Doc ID 022637 Rev 1 55 68 SPI control and status registers L99MM70XP Table 36 Control register 3 Control register 3 03h Bit 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset state 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 LIN OCR OUTS OUT4 OUT3 OUT2 OUT1 LIN OUTS OUT4 OUTS OUT2 OUT1 Name reserved Ereg OVUVR OR OR OR OR OR Plash Hap ECVL pWM1 PWM1 PWM1 PWM1 PWM1 Table 37 Control register 3 bits Bit name Comment reserved Reserved bit has always to be written to 0 and reads always 0 OCR frequency This bit defines the overcurrent recovery frequency of a driver in overcurrent recovery mode OCRFREQ S AA 0 1 7 kHz 1 3 kHz Overvoltage undervoltage recovery OVUVR 1 clear status register to enable the outputs after an overvoltage
50. ending wake up SREG pns 800 1200 pA 2V LIN lt Vs 3 5 V wupend request ST Current consumption in Vec standby 9 IVS VCO mode with a pending wake up Vs VsreG 13 5 V 800 1200 pA 2V LIN Vs 3 5 V wupend request Bru Current consumption in Vec standby Vs 13 5 V voltage regulator Vcc IVS VCC mode active no wake up request 1 HA TUM Vs 13 5 V voltage regulator Voc Current consumption in Vcc S IvsREG VCO mode P CC standby active ng wake up request 10 45 70 pA lvcc 9 PR Vg 13 5 V voltage regulator V Current consumption in Vcc o ce IvsREG VCC mode p CC standby Wide Ho MR request 15 67 105 UA vcc 1 OUT1 OUTS9 ECDR ECV ECFD floating 2 Ttest 40 C 25 C 3 Trest 85 C This parameter is guaranteed by design 1577 Doc ID 022637 Rev 1 33 68 Electrical characteristics L99MM70XP 8 2 Oscillator The voltages are referred to ground and currents are assumed positive when the current flows into the pin 4 5 V x Vs x 28 V all outputs open Tamp 40 C 125 C unless otherwise specified Table 10 Oscillator Symbol Parameter Test condition Min Typ Max Unit Nar oman repeny e 29 lama 8 3 Power on reset VsREG All outputs open Tamb 40 C 125 C unless otherwise specified see Figure 3 Table 11 Power on reset Vsngc Symbol Parameter Test condition Min Typ Max Unit Venga increasing 2 8 3 8 4 5 V VpoR V
51. eplaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2012 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 68 68 Doc ID 022637 Rev 1 ky
52. ev 1 Ly L99MM70XP Description 3 10 3 10 1 3 10 2 3 10 3 If NRES is pulled low all control registers except the reset level bit RSTLVL and the configuration register are set to default In both cases the device enters passive mode Vcc fail The Vcg regulator output voltage is monitored In case of a drop below the Ve fail threshold Vcc lt 2 V typ for t gt 2 us the Voc fail bit is latched The fail bit is cleared by a dedicated SPI command If 4 ms after turn on of the regulator the Vcc voltage is below the Voc fail threshold the L99MM70XP identifies a short circuit condition at the regulator output and switch it off In case of Vcc short to GND failure the device enters Vgat standby mode automatically Output drivers OUT1 OUT9 Load condition Each half bridge is built by internally connected high side and low side power DMOS transistors Due to the built in reverse diodes of the output transistors inductive loads can be driven at the outputs OUT1 to OUTS without external free wheeling diodes The drivers OUT6 OUT7 OUT8 OUTS ECV and ECFD are intended to drive resistive loads Therefore only a limited energy E 1 mJ can be dissipated by the internal ESD diodes in freewheeling condition For inductive loads L gt 100 pH an external free wheeling diode connected between GND and the corresponding output is required Current monitor The current monitor output sources a current image at the cur
53. g communication frame Note Due to this safety functionality a daisy chaining of SPI is not possible Instead a parallel operation of the SPI bus by controlling the CSN signal of the connected IC s is recommended 24 68 Doc ID 022637 Rev 1 ky L99MM70XP Description Serial Data Out DO The data output driver is activated by a logical low level at the CSN input and goes from high impedance to a low or high level depending on the global error flag fault condition The first rising edge of the CLK input after a high to low transition of the CSN pin transfers the content of the selected status register into the data out shift register Each subsequent falling edge of the CLK shifts out the next bit Serial Clock CLK The CLK input is used to synchronize the input and output serial bit streams The Data Input DI is sampled at the rising edge of the CLK and the Data Output DO changes with the falling edge of the CLK signal ky Doc ID 022637 Rev 1 25 68 Protection and diagnosis L99MM70XP 4 4 1 26 68 Protection and diagnosis Power supply fail Overvoltage and undervoltage detection on Vs Power Overvoltage If the supply voltage Vs rises above the overvoltage threshold Vgoy for more than 56 us typ The outputs OUT1 9 ECV ECFD and LIN are switched to high impedance state load protection Electrochrome mode is switched off If the bit OVUVR is set to O the outputs are re enabled automatically
54. h on res louT2 3 4 6 7max 0 6 A louTXmax 0 3 A 1 FS full scale loytmax lcu 8 8 Charge pump output CP The voltages are referred to ground and currents are assumed positive when the current flows into the pin 8 V lt Vs 16 V Tamp 40 C 125 C unless otherwise specified Table 16 Charge pump output CP Symbol Parameter Test condition Min Typ Max Unit Vs 5 8V Icp 60 pA Vet 6 Vs 13 V Vcp Charge pump output voltage Vs 10 V Icp 80 pA Vs 8 Vs 13 V Vs 2 12 V lcp 100 pA Vs 10 Vs 13 V Vcp Vs 10 V lcp Charge pump output current Vs 18 5 V 95 150 300 pA 8 9 Outputs OUT1 OUTY ECV ECFD 8 9 1 On resistance The voltages are referred to ground and currents are assumed positive when the current flows into the pin 8 V lt Vg lt 16 V Tamp 40 C 125 C unless otherwise specified Table 17 8 On resistance Symbol Parameter Test condition Min Typ Max Unit Vg 13 5 V Tamb 25 C a00 aes ees lour1 5 1 5A Ron outi 5 On resistance to supply or GND UAE S ge Thy e Mino Meg 450 600 ma lour1 5 1 5A Vs 13 5V T 25 C S id 1600 2200 mo R On resistance to supply or GND loUT23 10 4 A SNO pey Vs 13 5 V Tamp 125 C 2500 3400 ma lour2 34 0 4 A ky Doc ID 022637 Rev 1 37 68 Electrica
55. if the overvoltage condition is removed If it is set to 1 then the overvoltage bit has to be cleared to re enable the outputs LIN is always automatically re enabled The overvoltage bit is set and can be cleared with a read and clear command Undervoltage If the supply voltage Vs drops below the under voltage threshold voltage Vsyy for more than 56 us typ The outputs OUT1 9 ECV ECFD and LIN are switched to high impedance state Electrochrome mode is switched off If the bit OVUVR is set to O the outputs are re enabled automatically if the under voltage condition is removed If it is set to 1 then the under voltage bit has to be cleared to re enable the outputs LIN is always automatically re enabled The under voltage bit is set and can be cleared with the read and clear command Doc ID 022637 Rev 1 ky L99MM70XP Protection and diagnosis 4 2 Diagnosis functions Digital diagnosis features are provided by SPI Vee reset threshold programmable Overtemperature including pre warning Open load status separately for each output OUT1 9 ECV ECFD Overload status separately for each output OUT1 9 ECV ECFD Vs supply Overvoltage undervoltage Vcc fail bit Chip reset bit start from power on reset Number of unsuccessful Vcc restarts after thermal shutdown Number of sequential watchdog failures LIN diagnosis permanent recessive dominant dominant TXD Device state wake up from Vcc stangpy OF VBAT st
56. il the load reaches operating condition The PWM frequency settles at 1 7 kHz and 3 kHz The device itself cannot distinguish between a real overload and a non linear load like a light bulb A real overload condition can only be qualified by time As an example the microcontroller can switch on the light bulbs by setting the overcurrent recovery bit for the first 50 ms After clearing the recovery bit the output is automatically switched off if the overload condition remains Figure 6 Example of programmable soft start function for inductive loads Load Current Unlimited Inrush Current Na Limited Inrush Current in programmable Recovery Mode Current Limitation GAPGMS00010 Doc ID 022637 Rev 1 ky L99MM70XP Description 3 11 Controller for electrochromic glass The voltage of an electrochromic element connected at pin ECV can be controlled to a target value which is set by the bits EC 5 05 Control register 2 bits 6 down to 1 Setting bit ECON control register 2 bit O enables this function An on chip differential amplifier and an external MOS source follower with its gate connected to pin ECDR and which drives the electrochrome mirror voltage at pin ECV form the control loop The drain of the external MOS transistor is supplied by OUT7 A diode from pin ECV anode to pin ECDR cathode has been placed on the chip to protect the external MOS source follower A capacitor of at least 5 nF has to be add
57. l characteristics L99MM70XP Table 17 On resistance continued Symbol Parameter Test condition Min Typ Max Unit Vo 213 5V T 425 C Na M ris 1600 2200 ma OUT6 7 0 R On resistance to suppl oat dd Vs 13 5 V Tamb 125 C re ee ee m loure 7 0 4 A Vs 13 5 V Tamp 25 C REESE m On resistance to supply in low louts 3 0 A resistance mode Vs 13 5 V Tamb 125 C 700 950 mQ ON OUTS Vs 18 5 V Tamb 25 C nv poses m On resistance to supply in high outs 0 8 A resistance mode Vg 13 5 V Tamb 125 C 2500 3400 mQ Ve 13 5 V T 25 C a 90 130 ma ourg 3 R On resist t ON OUT9 n resistance to supply Vs 185 V Tang 125 C m louro 3 0 A e Vs 13 5 V T 25 C ji ame 1600 2200 mo R On resistance to GND DUIECUEOHD AP ON ECVEGFD Vs 18 5 V Tamb 125 C 2500 3400 mt louTECv ECFD 0 4 A i Switched off output current Vout 0 V standby mode 5 2 pA LH nata Q high side drivers of OUT1 9 V yr 0 V active mode HOS x uA Switched off output current Vour Vs standby mode 80 120 pA low side drivers of OUT1 5 Vout Vs active mode 10 7 UA Switched off output current Vour 7 Vs standby mode 15 15 pA LL j Q low side drivers of ECV Vout Vs active mode 10 7 UA Switched off output current Vout 4V standby mode 80 120 pA low side drivers of ECFD Vour 4V active mode 40 7 UA 8 9 2 Switching times The voltages are referred to ground and currents
58. lINHh current 30 75 120 pA liNHPd INH pull down current Viny 13 5 V 30 70 120 pA IiNHhys Wake up current hysteresis 10 20 uA twu Minimum time for wake up 50 64 77 us 8 10 LIN Compatible to LIN 2 1 for baud rates up to 20 kBit s The voltages are referred to ground and currents are assumed positive when the current flows into the pin 7 V lt Vs 18 V Tamb 40 C 125 C unless otherwise specified Table 22 LIN Symbol Parameter Test condition Min Typ Max Unit LIN transmit data input pin TXD Input voltage VTXDLOW damnat level Active mode 0 3Vcc V Input voltage VIXDHIGH recessive level Active mode 0 7 Voc V VrxpHvs VrxpHiGH VrxpLow Active mode 500 mV Active mode Vg 13 5 V Rrxppu TXD pull up resistor 0 lt Vosn lt 0 7 Voc 50 100 150 k LIN receive data output pin RXD Output voltage _ VrxDLow dominant level Active mode Inxp 2 mA 0 3 Voc V Output voltage E VnxpHiGH recessive level Active mode Inxp 2 mA 0 7 Voc V LIN transmitter and receiver pin LIN Receiver threshold VtHdom voltage recessive to 0 4 Vs 0 45 Vs 0 5Vs V dominant state Receiver threshold VTHrec voltage dominant to 0 5 Vs 0 55 Vs 0 6Vs V recessive state ky Doc ID 022637 Rev 1 43 68 Electrical characteristics L99MM70XP Table 22 LIN continued Symbol Parameter Test condition Min Typ Max Unit Receiver threshold VTHhys hysteresis
59. lses within the previous frame is not 24 the frame is ignored and this bit CO ER is set CO ER is not set if CSN is held low without any clock to check the GL ER bit Chip reset C RESET Registers have been set to default NRECE NOT After power on NRECE is 0 and is set to 1 by a valid SPI communication C_RESETOR NRECE is also 0 if there was a communication error or if there was a reset due to stuck at 0 or CO ER stuck at 1 at the SPIDI input When NRECE is active 0 the gate drivers are switched off resistive path to source The gate drivers can only be activated after NRECE has been reset with an SPI command Thermal shut down due to an internal sensor All the gate drivers and the charge pump are TSD switched off resistive path to source The TSD bit has to be cleared through a software reset to reactivate the gate drivers and the charge pump TW_OL Thermal warning OR open load UV OV OC Under voltage OR overvoltage OR overcurrent Vcc rat Voc fail Device in passive mode This bit is set if the device enters passive mode due to watchdog failure Vcc under voltage thermal shutdown TSD2 or SPI data in stuck at O or 1 The bit is reset when the micro sends the first correct SPI frame after entering passive mode PASSIVE 4 52 68 Doc ID 022637 Rev 1 L99MM70XP SPI control and status registers 9 1 5 Address mapping Table 30 RAM memory map
60. lue than ECV which is connected to ground by a 1 6 Ohm low side switch In this mode the voltage at pin ECFD is controlled to the target value defined by the register EC lt 5 0 gt This is done using an on chip source follower transistor see Figure 14 for details The negative discharge is enabled by setting bit ECND control register 2 bit 7 to T During normal positive voltage control the low side driver at pin ECFD must be switched on to connect the electrochrome element to ground Pin ECDR is pulled resistively Recprpis to ground while not in electrochrome mode Doc ID 022637 Rev 1 21 68 Description L99MM70XP 3 12 LIN bus interface 3 12 1 General features Speed communication up to 20 kbit s High speed Flash mode 100 kbit s LIN 2 1 compliant SAEJ2602 compatible transceiver Function range from 40 V to 18 V DC at LIN pin GND disconnection fail safe at module level Off mode does not disturb network GND shift operation at system level Microcontroller Interface with CMOS compatible I O pins Pull up internal resistor ESD immunity against automotive transients per ISO7637 specification Matched output slopes and propagation delay In order to further reduce the current consumption in standby mode the integrated LIN bus interface offers an ultra low current consumption 3 12 2 LIN error handling The L99MM70XP provides the following 3 error handling features which are not described in the LIN Specifications V2
61. mmable duty cycle OUT70R CR3 Bit14 0 clear status register to enable the output after an overcurrent event OUT6OR OUT9PWM1 OUT8PWM3 If the PWM1 2 3 enable bit is set and the output is enabled the output is switched on only if the ELM 4 PWM1 2 8 input is high and switched off if the PWM1 2 3 input is low OUT7PWM OUTS is controlled by PWM3 OUT7 is controlled by PWM1 and OUT6 is controlled by PWM2 OUT6PWM2 reserved Reserved bit has always to be written to O and reads always 0 Overcurrent recovery enable 1 the output is automatically reactivated after a delay time with programmable duty cycle CR3 Bit14 0 clear status register to enable the output after an overcurrent event ECVOR reserved Reserved bit has always to be written to O and reads always 0 If the PWM1 enable bit is set and the output is enabled the output is switched on only if the PWM1 EC MENMI input is high and switched off if the PWM1 input is low 4 Doc ID 022637 Rev 1 57 68 SPI control and status registers L99MM70XP Table 39 Control register 4 bits continued Bit name Comment Current monitor the current image of the selected high side output is multiplexed to the CM output see table below CM3 CM2 CM1 CMO Current image of 0 0 0 0 CM deactivated 0 0 0 1 CM HS1 active 0 0 1 0 CM HS2 active
62. n dVecy Viarget Vecvs 5 4596 IWVecvl target and ECV llecpnl lt 1 PA iLSB 118sBQ V 3 y Difference voltage AVEcv Viarget ECV dVEcvnr betwesntargst below it Toggle bit5 1 Status reg 3 120 mV and ECV sets flag dVeevy Viena V f ECV 7 Vtarget ECV E WVecvhi if Vecy is above it Toggle bit 1 Status reg 3 ha m tFECVNR ECVNR filter time 32 us tFECO ECVO filter time 32 KS VECDRminHIGH lEcpR 10 pA 4 1 5 5 Output voltage range VECDRmaxLOW lecpR 10 pA 0 0 7 V Viarget gt VEcv 4 500 mV ba Veca 35V 100 10 HA lEcDR Current into ECDR Viarget lt Vgcy 500 mV VECDR 1 0 V Viarget 0 V 10 100 pA Vecy 0 5 V Bemas _ infast discharge modeand Econ 0 7 V ECON 0 ko ecdrdis l ge EC lt 5 0 gt 0 or ECON 0 while EC mode is off DNLgcrp Differential non linearity 1 1 LSB Voltage deviation between dVgcrp Viarget VECFD 5 5 IdVecrpl target and ECFD lgcep 100 pA 1LSB 15BQ V 3 _y 4 Difference voltage 4 QVEcrFD Viarget ECFD VEcFDnr between target Dew toggle status bit ECVNR 1 120 my and ECFD sets dV V 3 y i ECFD target ECFD z dVecrbhi flagifVgcepis 8bovelt toggle status bit ECVO 1 120 my 1 Bit ECVL 1 or 0 ECV voltage where lecpp can change sign 2 1LSB Least Significant Bit 23 8 mV 3 Viarget iS Set by bits EC 5 0 and bit ECVL tested for each individual bit 4 Nottested since pulling pin
63. ned therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and r
64. pon threshold a SF Venga decreasing 3 2 V 8 4 Voltage regulator Vcc The voltages are referred to ground and currents are assumed positive when the current flows into the pin 6 V lt Vspeg 28 V Tamb 40 C 125 C unless otherwise specified Table 12 Voltage regulator Vcc Symbol Parameter Test condition Min Typ Max Unit Voc Output voltage 5 0 V Output voltage tolerance li oAp 6 mA 50 mA P Voc active mode Venga 13 5 V aai NG V Output voltage tolerance li oAp 50 mA 100 mA 4259 active mode high current Vanga 13 5 V Es Output voltage tolerance li oAp O pA 6 mA V 2 5 3 5 96 STB Vcc standpy mode Venga 13 5 V ILoaD 50 mA VanEG 245V 0 2 0 4 V Vpp Drop out voltage eoe oor oom ILoaD 100 mA VsREG 45V 0 3 0 5 V lec Output current in active mode Max continuous load current 100 mA lccmax Short circuit output current Current limitation 400 600 950 MA Cload1 Load capacitor1 Ceramic 0 22 uF t Voc deactivation time after 1 TSD thermal shutdown Current consumption rising Rising current deactivated ICMPris threshold current monitor 1632 ams 34 68 Doc ID 022637 Rev 1 ky L99MM70XP Electrical characteristics Table 12 Voltage regulator Vcc continued Symbol Parameter Test condition Min Typ Max Unit ence Current consumption falling Falling current deactivated 13 27
65. put is built by a high side and a low side switch which are internally connected 35 5 OUT1 OUT2 The output stage of both switches is a power DMOS transistor 6 21 OUT3 OUTA B I 20 OUT5 Each driver has an internal parasitic reverse diode bulk drain diode high side driver from output to Vs low side driver from GND to output This output is overcurrent and open load protected Chip select not input 8 CSN this input is low active and requires CMOS logic levels The serial data transfer between the L99MM70XP and the microcontroller is enabled by pulling the input CSN to low level Current monitor output 9 CM depending on the selected multiplexer bits of the control register this output sources an image of the instant current through the corresponding high side driver with a ratio of 1 10000 or 1 2000 Serial data output 10 DO the diagnosis data is available via the SPI and this 3 state output The output remains in 3 state if the chip is not selected by the input CSN CSN high Serial data input 41 DI the input requires CMOS logic levels and receives serial data from the microcontroller The data is a 24 bit control word and the most significant bit MSB bit 23 is transferred first 12 CLK Serial clock input this input controls the internal shift register of the SPI and requires CMOS logic levels 13 vce Voltage regulator output 5 V supply e g microcontroller CAN transceiver 14 RXD Receiver output of the
66. rent monitor output which has two fixed ratios of the instantaneous current of the selected high side driver Outputs with a resistance of 500 mQ and higher have a ratio of 1 2000 and those with a lower resistance of 1 10000 The signal at output CM is blanked after switching on the driver until correct settlement of the circuitry at least for 32 us The bits O to 3 of the control register 3 define which of the outputs are multiplexed to the current monitor output CM The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open load or overload condition For example it can be used to detect the motor state starting free running stalled Moreover it is possible to control the power of the defroster more precisely by measuring the load current PWM inputs Each driver has a corresponding PWM enable bit which can be programmed by the SPI interface If the PWM enable bit is set in control register 2 or 3 the output is controlled by the logically AND combination of the PWM signal and the output control bit in control register 0 or 1 The outputs OUT1 5 7 9 ECV are controlled by the PWM1 input the output OUT6 is controlled by the input PMW2 and output OUTS is controlled by INH PWM3 Thus the three PWM inputs can be used to dim three lamps independently by external PWM signals Switching off the outputs a delay of maximum 300 us is introduced see also Table 18 in Section 8 9 2
67. ry frequency for OC recovery freco duty cycle bit 0 4 Kag Recovery frequency for OC recovery frec1 duty cycle bit 1 2 8 kHz llo pih 9 30 80 mA locos Under current threshold to supply or lloLo2l GND Vs 13 5 V sink and source lloLp3l 10 20 30 mA lloLp4l lloLoel Under current threshold to supply 10 20 30 mA llo pz Under current threshold to supply in 15 40 60 mA low on resistance mode Vg 13 5 V source loi pel Under current threshold to supply in 5 10 15 mA high on resistance mode Ilo pol Under current threshold to supply 30 150 300 mA lloLDECV Under current threshold to GND Vg 13 5 V sink 10 20 30 mA loLDECFD Duration of under current tFoL Filter time of under current signal condition to set the status bit 0 5 2 0 3 0 ms 4 40 68 Doc ID 022637 Rev 1 L99MM70XP Electrical characteristics 8 9 4 Electrochrome control The voltages are referred to ground and currents are assumed positive when the current flows into the pin 8 V lt Vs 16 V Tamp 40 C 125 C unless otherwise specified Table 20 Electrochrome control Symbol Parameter Test condition Min Typ Max Unit E ECVL 4 0 1 4 1 6 V VeTRL Maximum EC control voltage palapa ECVL 0 1 12 128 V DNLgcy _ Differential non linearity 1 1 LSB Voltage deviation betwee
68. s are referred to ground and currents are assumed positive when the current flows into the pin 6 V x Vs x 18 V all outputs open Tamp 40 C 125 C unless otherwise specified Table 24 AC characteristics Symbol Parameter Test condition Min Typ Max Unit Cour Output capacitance DO 10 pF 1 Input capacitance DI CSN m u Cin CLK PWM1 PWM2 PWM3 10 pF 1 Value of input capacity is not measured in production test Parameter guaranteed by design Dynamic characteristics The voltages are referred to ground and currents are assumed positive when the current flows into the pin 6 V lt Vs x 18 V all outputs open Tamp 40 C 125 C unless otherwise specified For definition of the parameters please see Figure 16 and Figure 17 Table 25 Dynamic characteristics Symbol Parameter Test condition Min Typ Max Unit DO enable from 3 state to Cpo 100 pF Ipo 1 MA pull CSNQVL low level up load to Vcc Vs 13 5 V 100 1 250 As DO enable from 3 state to Cpo 100 pF Ipo 1 mA pull CSNQVH high level down load to GND Vg 13 5 V Tuo ee Me DO disable from low level to Cho 100 pF Ipo 4 MA pull CSNQTL 3 state up load to Vcc Vs 13 5 V 380 LAGU nS DO disable from high level to Cpo 100 pF Ipo 4 mA pull t CSNQTH 3 state down load to GND Vs 13 5 V 980 7490 ins Vpo 0 3 Ve
69. to this nominal current Doc ID 022637 Rev 1 29 68 Absolute maximum ratings L99MM70XP 5 Note 30 68 Absolute maximum ratings Table 5 Absolute maximum ratings o Value Symbol Parameter test condition DC voltage Unit DC supply voltage jump start 0 3 to 28 V s Load dump 0 3 to 40 V Vg lt 5 2V 0 3toVg 0 3 V Vcc Stabilized supply voltage logic supply Ve55 2V 0 3 to 5 5 V Vpr VELK VTXD Vosn Vpo Logic input output voltage range 0 3 to Vcg 0 3 V VRxp VNRES Vom Vpwm1 Vewms Vpwm3 Logic input voltage 0 3 to Vg 0 3 V Vcp Charge pump output 25 to 39 Vourn ECDR EOV Static output voltage n 1 to 9 03t0 Vg 03 V ECFD IQUT2 3 46 7 ECV Output current 1 25 A ECFD VS REG lOUT1 5 8 9 Output current 5 A Ilys Power GND Maximum output current between pin 2 and 32 or 7 IPin to Pin and 32 1 1 A VLIN LIN bus I O voltage range 20 to 40 V 1 Values for the absolute maximum current through bond wire It doesn t consider maximum power dissipation or other limits All maximum ratings are absolute ratings Exceeding the limitation of any of these values may cause an irreversible damage of the integrated circuit Doc ID 022637 Rev 1 4 L99MM70XP ESD protection 6 4 ESD protection Table 6 ESD protection Parameter Value Unit All pins 2 kV All output pins OUT1 OUT9 ECV ECFD 4 kV LING x8
70. trol register 3 bits elles Control register 4 liliis Control register 4 bits 22e Configuration register llli Configuration register bits liliis Status register 1 lesse Status register 1 bits llle Status register 2 2 0 ee Status register 2 bits 6 0 0 ee Status register 3 2 2 eee Status register 3 bits llle Status register 4 2 eee Doc ID 022637 Rev 1 5 68 List of tables L99MM70XP Table 49 Status register 4 bits liiis Rh 63 Table 50 PowerSSO 36 mechanical data lilii eene 66 Table 51 Document revision history e en 67 6 68 Doc ID 022637 Rev 1 ky L99MM70XP List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Block diagram sse reirs atin ied bay bby Ere Are rema eee ree a e don ede bas 8 Pin connection top view RR m 11 Voltage regulator operation 00 n 13 Operating modes main states ee 16 Watchdog state diagram 1 6 en 18 Example of programmable soft start function for inductive loads 20 SPI global error information output 0 0 0 0 cee 24 Thermal shutdown protection and diagnosis lille 28 Thermal data of PowerSSO 3
71. ure 5 Watchdog state diagram f tand standby mode 8 7 x WD failures 8x WD failure Watchdog failure Reset No trigger NRES low for 2ms Watchdog active DON pus S 100 s watchdog time After 2 ms Peas Wake up event from VCC standby or flash mode Watchdog inactive Vbat standby VCC standby A Flash TA Wake up event from Vbat standby Go to standby or flash mode GAPGMS00009 3 7 Passive mode L99MM70XP enters passive mode in case of e Watchdog failure e Vcc under voltage NRES e Thermal shutdown TSD2 e SPI data in stuck at O or 1 In passive mode all control registers except the reset level bit RSTLVL and the configuration register are set to default so that all outputs are switched off The PASSIVE bit inside the global status byte is set to 1 The first valid SPI frame after entering the passive mode resets the PASSIVE bit to O and leaves passive 3 8 Reset output NRES If Voc is turned on and the voltage exceeds the Ve reset threshold the reset output NRES is pulled up by internal pull up resistor to Vcc voltage after a 2 ms reset delay time This is necessary for a defined start of the microcontroller when the application is switched on A low active reset pulse 2 ms is generated in case of Vcc drops below Vp configurable by SPI for more than 8 us Vcc under voltage e Watchdog failure 18 68 Doc ID 022637 R
72. ve mode This can be initiated by one or more of the following sources e Change ofthe LIN state at LIN bus interfaces e SPI access in Vcc standby mode CSN is low and first rising edge on CLK A current at the INH pin I gt 120 pA controlled by the CAN transceiver the CAN transceiver is not a part of the IC Table 3 Wake up events Wake up source Description LIN Always active INH Always active Device remains in Vcc stangpy mode with Vac watchdog enabled If loyp 0 and Vcc goes CC CMP into high current mode increased current consumption No interrupt is generated SPI access Always active except in VBAT standoy mode LIN wake up events in Vec standby mode generate a low pulse at RXD for 56 us Wake up from Vcc standby by SPI access might be used to check the interrupt service handler Doc ID 022637 Rev 1 ky L99MM70XP Description 3 4 Functional overview truth table Table 4 Functional overview truth table Operating modes Function Comments Active mode Vec standby VBAT standby static mode static mode Voltage regulator Vcc Vout 5 V On On Off NRES On On Off Window watchdog Voc monitor On on d o ud Off CMP 7 LIN LIN 2 1 On Off Off 1 Supply the processor in low current mode 2 The bus state is internally stored when going to standby mode A change of bus state leads to a wake up after exceeding of internal filter time Na Doc

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ST L99MM70XP handbook

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