Home

ST VND5T035AK-E handbook

1. LI I BULL TEU HUI e 1 0 1 Mal ll b 26 31 Doc ID 018942 Rev 4 OT VND5T035AK E Package and packing information Table 16 PowerSSO 24 mechanical data Millimeters Symbol Min Typ Max A 2 15 2 47 A2 2 15 2 40 al 0 0 075 b 0 33 0 51 c 0 23 0 32 D 10 10 10 50 E 7 4 7 6 e 0 8 e3 8 8 G 0 1 G1 0 06 H 10 1 10 5 h 0 4 k 5 L 0 55 0 85 N 10 X 4 1 4 7 Y 6 5 7 1 ky Doc ID 018942 Rev 4 27 31 Package and packing information VND5T035AK E 5 3 PowerSSO 24 packing information Figure 31 PowerSSO 24 tube shipment no suffix Base Q ty 49 Bulk Q ty 1225 Tube length 0 5 532 A 3 5 B 13 8 C 0 1 0 6 All dimensions are in mm GAPGCFT00002 Figure 32 PowerSSO 24 tape and reel shipment suffix TR t gt a 40mm min T Access hole Reel dimensions x at slot location p gt Z BaseQty 1000 J N Buk Qty 1000 y X A max 330 c B min 1 5 ll HEN LL N EL C 02 18 a j F 20 2 G 2 0 24 4 i 1 n Y i G measured N min 100 Full radius 4 ano T max 30 4 Tape siot Ni t Ps in core for v ins i
2. 1 40 50 25 0 25 50 75 100 125 150 175 Tc C GAPGCFT00463 Figure 17 Low level input voltage Figure 18 Input hysteresis voltage Vil V Vihyst V 1 40 0 39 1 20 4 0 38 1 00 4 0 37 0 80 4 0 36 0 60 4 0 35 0 40 4 020 4 0 34 0 00 0 33 50 25 0 25 50 75 100 125 150 175 50 25 0 25 50 75 100 125 150 175 Tc C To C GAPGCFT00464 GAPGCFT00465 18 31 Doc ID 018942 Rev 4 Ly VND5T035AK E Electrical specifications Figure 19 On state resistance vs Tease Figure 20 On state resistance vs Vcc Ron mOhm 70 00 60 00 4 50 00 4 40 00 4 30 00 4 20 00 4 10 00 4 0 00 GAPGCFT00466 Ron mOhm 70 00 T Tc 150C 60 00 i ME EET N ER as Dan iN 50 00 Tc2125C 40 00 Tc 25C 30 00 20 00 aaa ae Tc 40C 10 00 lout 3A 0 00 5 10 15 20 25 30 35 40 Vcc V GAPGCFT00467 Figure 21 lLIMH vs Tease Figure 22 Turn on voltage slope llimH A dVout
3. 055 24 PowerSSO 24 package dimensions 000 ccc cette 26 PowerSSO 24 tube shipment no suffix 0 00 EE EE EE Gee Ee ee de ke ee ee 28 PowerSSO 24 tape and reel shipment suffix TR EE RE Re eee eee 28 Doc ID 01894 Rev 4 OT VND5T035AK E Block diagram and pin description 1 Block diagram and pin description Figure 1 Block diagram Signal Clamp rf Control amp Diagnostic 2 Undervoltage Control amp Diagnostic 1 DRIVER e Limitation Over Current Temperature Limitation OFF state Open load VSENSEH Current Sense OVERLOAD PROTECTION ACTIVE POWER LIMITATION GND GAPGCFT00643 Table 1 Pin function Name Function Voc Battery connection OUT Power outputs GND Ground connection Voltage controlled input pins with hysteresis CMOS compatible They Control output Nig switch state C815 Analog current sense pins they deliver a current proportional to the load current In case of latch off for overtemperature overcurrent condition a low pulse on the FR Stby FR Stby pin is needed to reset the channel The device enters in standby mode if all inputs and the FR Stby pin are low Q Doc ID 018942 Rev 4 5 31 Block diagram and pin descript
4. OVERLOAD thermal shutdown OR power limitation GAPGCFTO000116 Table 11 Truth table T Fault reset Conditions standby Input Output Sense Standby L L L 0 Normal ration d 3 LL dM x H H Nominal X L L 0 veiled x H H Nominal Overt ture a E vertemperature f short to ground L H Cycling VSENSEH H H Latched VSENSEH Undervoltage X X L 0 L L H 0 Short to VBAT H L H VSENSEH X H H Nominal O load off stat s i pen load off state with pull up H L H VSENSEH X H H 0 Negative output X L Negative 0 voltage clamp 16 31 Doc ID 018942 Rev 4 ky VND5T035AK E Electrical specifications Table 12 Electrical transient requirements part 1 ISO 7637 2 Test levels Number of Burst cycle pulse Delays and 2004 E pulses or Ak repetition time impedance Test pulse I IV test times 1 450 V 600 V SUE 0 5s 5s 1 ms 50 Q pulses 2a 37V 50 V 2009 0 25 5s 50 us 2 Q pulses 3a 150 V 200 V th 90 ms 100 ms 0 1 us 50 Q 3b 150 V 200 V th 90 ms 100 ms 0 1 us 50 Q 4 12V 16V 1 pulse 100 ms 0 01 Q 5p 123 V 174 V 1 pulse 350 ms 1 Q 1 Valid in case of external load dump clamp 58 V maximum referred to ground Table 13 Electrical transient requirements part 2 ISO 7637 2 Test level results 2004 E Test pulse Hl IV 1 2a C C 3a C 3p E C e Ojojm oj oj o 5b 4 C G
5. 1 In order to guarantee the ISO transient classes a minimum 10KQ protection resistors are needed on logic pins Without capacitor between Vcc and GND With 10 nF between Vcc and GND External load dump clamp 58 V maximum referred to ground Table 14 Electrical transient requirements part 3 Class Contents C All functions of the device are performed as designed after exposure to disturbance One or more functions of the device are not performed as designed after exposure to E f disturbance and cannot be returned to proper operation without replacing the device 4 Doc ID 018942 Rev 4 17 31 Electrical specifications VND5T035AK E 2 4 Figure 13 Off state output current Electrical characteristics curves Figure 14 High level input current lloff uA 3 00 2 50 2 00 1 50 1 00 0 50 0 00 GAPGCFT00460 lih UA 4 00 3 50 3 00 2 50 2 00 1 50 1 00 0 50 0 00 Te C GAPGCFT00461 Figure 15 Input clamp voltage Figure 16 High level input voltage Vicl V 6 60 6 50 6 40 6 30 6 20 linz1mA 6 10 6 00 4 _ 50 25 0 25 50 75 100 125 150 175 Tc C GAPGCFT00462 Vih V 1 70 1 65 1 60 1 55 1 50 1 45
6. ky VNDSTO3SAK E Double channel high side driver with analog current sense for 24 V automotive applications Features Max transient supply voltage Voc 58V Operating voltage range Vcc 8 to 36V Typ on state resistance per ch Ron 35mQ Current limitation typ liM 42A Off state supply current Is 2 HA m General Very low standby current 3 0 V CMOS compatible input Optimized electromagnetic emission Very low electromagnetic susceptibility Compliant with European directive 2002 95 EC Fault reset standby pin FR_Stby m Diagnostic functions Proportional load current sense High current sense precision for wide range currents Off state open load detection Output short to Vcc detection Overload and short to ground latch off Thermal shutdown latch off Very low current sense leakage m Protections March 2012 Undervoltage shutdown Overvoltage clamp Load current limitation Self limiting of fast thermal transients Protection against loss of ground and loss of Voc Thermal shutdown Electrostatic discharge protection Datasheet production data PowerSSO 24 GAPGCFT00382 Application All types of resistive inductive and capacitive loads Description The VND5TOS35AK E is a monolithic device made using STMicroelectronics VIPower technology intended for driving resistive or inductive loads with one side connected to ground Active Vcc pin volt
7. 4V dK3 K3 _ Current sense ratio drift OUT diced i 5 5 a Tj 40 C to 150 C lout 0 A Vsense 0 V 0 1 m Analog sense leakage Vin 9 V Tj 40 C 150 C SENSEO current lout 0 A Vsense 0 V m Vin 5 V Ti 40 C 150 C Max analog sense output Vsense voltage x P lour 12 A Rgense SS KO 5 V Analog sense output VSENSEH voltage in fault Vec 24 V RSENSE 223 9 KQ 7 5 8 5 9 5 V condition Analog sense output ISENSEH en in fault condition Vcc 24 V Vsense 5 V 4 9 9 12 mA 2 Delay response time Vsense lt 4 V EL 0 2 A lt lout lt 12 A tpSENSE2H from rising edge of 200 400 us Isense 90 of ISENSE max INPUT pins see Figure 6 Delay response time Vsense lt 4 V At between rising edge of Isense 90 of IseENSEMAx 250 DSENSE2H output current and rising lour 90 of loytmax H edge of current sense lourMAx 3 A see Figure 10 Delay response time Vsense lt 4 V 0 2 A lt lout lt 12 A tDSENSE2L from falling edge of i 5 20 us Isense 10 of ISENSE max INPUT pins see Figure 6 1 Parameter guaranteed by design it is not tested 2 Fault condition includes power limitation overtemperature and open load in off state condition 12 31 Doc ID 018942 Rev 4 X VND5T035AK E Electrical specifications Note 7 Table 10 Openload detection VER
8. Please note that if the microprocessor ground is not shared by the device ground then the RGND Produces a shift Is on max Rap in the input thresholds and the status output values This shift varies depending on how many devices are ON in case of several high side drivers sharing the same Renp If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests Solution 2 is used see below Doc ID 018942 Rev 4 Ly VND5T035AK E Application information 3 1 2 3 2 3 3 Solution 2 diode Dgnp in the ground line A resistor Rawp 4 7 KQ should be inserted in parallel to Denp if the device drives an inductive load This small signal diode can be safely shared amongst several different HSDs Also in this case the presence of the ground network produces a shift 600 mV in the input threshold and in the status output values if the microprocessor ground is not common to the device ground This shift does not vary if more than one HSD shares the same diode resistor network Load dump protection Dig is necessary Voltage Transient Suppressor if the load dump peak voltage exceeds to Vcc maximum DC rating The same applies if the device is subject to transients on the Voc line that are greater than the ones shown in the ISO T R 7637 2 table MCU I Os protection If a ground protection network is used and negative transient is present on the Vcc line the contr
9. VER swy 5 V EE EE EER EE RR eee 13 Truth tables ER EE ee eed eee OE OG 16 Electrical transient requirements part 1 liliis essere 17 Electrical transient requirements part 2 liliis 17 Electrical transient requirements part 3 lilii sisse 17 Thermal parameters 00 00 ce ete teens 25 PowerSSO 24 mechanical data liiis ren 27 Device SUMMA so 4 244602 N beg EE EE EE N 29 Document revision history ie EE EE Ee ee eae 30 Doc ID 018942 Rev 4 3 31 List of figures VND5T035AK E List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 4 31 Block diaga sere irer es tem bead aaah ee eed page Rub a dope bdo 5 Configuration diagram PowerSSO 24 top view 00 EE Re ke dk ee ke 6 Current and voltage conventions se es EE Ee ee ee Se ren 7 TresetdefinitiOf ss sa cree eek ER EE Fo EEE eee RE RR R3 ADR RR EE BERE ee 10 Tstby definition EO EE EE EE OE ne EE da 11 Current sense delay characteristics ES SE Se EG EG ee eee 13 Openload off state delay timing EE EE EE EE ER Ee RE Re SR ee ee dee 13 Switching characteristics
10. ER DR RR Ex RC A RR 21 3 3 MOUTOSDprIOISClIDII scs cm xo Ram cages BESEER xao RE CR ees 21 3 4 Maximum demagnetization energy Voc 24 VV ee eee eee 22 4 Package and PCB thermal data lsuees 23 4 1 PowerSSO 24 thermal data 0 000 cece eee eee 23 5 Package and packing information eeesss 26 ss us EE EE EER EE A 26 5 2 PowerSSO 24 package information EE EE cee eee eee 26 5 3 PowerSSO 24 packing information llle 28 6 Order codes dasse Eie SE se e d RD DEE EEN RR eee 29 7 Revision history iese E EE RE eink EER EEN eee EN EE eN Re m DN N n n 30 2 31 Doc ID 018942 Rev 4 ky VND5T035AK E List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 PIN Pe 2 gee a tas head de MM det ades he do pase x rack tee enh Vott 5 Suggested connections for unused and not connected pins 0 00 eee 6 Absolute maximum ratings is EE EE ee tet ee 7 MNS nal data ss OE EE EE ee ae a eis Grace ee rr adu IE RAS x ARRAS QR RN 8 Power Sectio 1 ri EE NE EE eee eee derum 9 Switching VCC 224 V Tj225 C EE EE EE EG Se rn 9 Logic Inputs 2 OE d RE EE ER N BR aoe Eon ea eens 10 Protections and diagnostics llle 11 Current sense 8 V lt Vcg lt 36 V 26 ere 12 Openload detection
11. ON Input1 2 Low GAPGCFT00038 Doc ID 018942 Rev 4 Ly VND5T035AK E q Figure 10 Delay response time between rising edge of ouput current and rising edge of current sense Vin Atpsense2H lourmax l l lout l l l l l 90 loutmax SENSE IseNsEMAX 90 ISENSEMAX t GAPGCFT000115 Figure 11 Output voltage drop limitation Electrical specifications Vcc Vour T 150 C TE 25 C T 40 C OUT Von Ron T AG00074V1 Doc ID 018942 Rev 4 Electrical specifications VND5T035AK E Figure 12 Device behavior in overload condition FAULT_RESET l I IN I I I I I I I I I OUTPUT l I l l l l l l m L l 1 1 overloa L a l 4 n overload reset OVERLOAD L zl l 1l overload diag reset CHANNEL l ME T oe E E a 7 1 OUTPUT and CS controlled by INn 2 FAULT RESET from 0 to 1 no action on CS pin 3 overload latch off Inn high CS high 4 FAULT_RESET low AND Temp channeln lt overload_reset overload latch reset after t_reset 4 to 5 FAULT_RESET low AND IN high thermal cycling CS high 5 FAULT_RESET high latch off reset disabled 6 to 7 overload event and FAULT_RESET high latch off no thermal cycling 7 to 8 overload diagnostic disabled enabled by the input 8 overload latch off reset by FAULT RESET
12. Package and PCB thermal data 4 4 1 Figure 26 Package and PCB thermal data PowerSSO 24 thermal data PowerSSO 24 PC board PSSO24L LLL PSSO24L S8cm 2 PSSO24L 2cm 2 A GAPGCFT00418 1 Layout condition of Rin and Zip measurements PCB double layer thermal vias FR4 area 77 mm x 86 mm PCB thickness 1 6 mm Cu thickness 70 um front and back side Copper areas from minimum pad lay out to 8 cm Figure 27 Rihj amb VS PCB copper area in open box free air condition one channel ON Rruj amp C W 50 45 40 35 30 25 0 2 4 6 8 10 PCB Cu heatsink area cm GAPGCFT00436 Doc ID 018942 Rev 4 23 31 Package and PCB thermal data VND5T035AK E 24 31 Figure 28 PowerSSO 24 thermal impedance junction ambient single pulse one channel ON Zw C W 100 ep ap OPERE eo EE EE AE EE SUN 0 1 LUI ee 0 0001 0 001 0 01 0 1 1 10 100 1000 Time s GAPGCFTO0437 A Cu Footprint B Cu 2 cm C Cu 8 cm Figure 29 Thermal fitting model of a double channel HSD in PowerSSO 24 PdChi Tj I zr GAPGCFT0
13. d tape start i 2 5mm min width r Tapedimensions According to Electronic Industries Association EIA Standard 481 rev A Feb 1986 Tapewidth Ww 24 t p Tape Hole Spacing PO 0 1 4 COVER Component Spacirg P 12 TAPE Hole Diameter D 0 05 1 55 Hole Diameter D1 min 1 5 Hole Position F 0 1 11 5 Compatment Depth K max 2 85 7 User Direction of Feed Hole Spadng p1 0 1 2 End All dimensions are in mm 2 odioodioodq o ELE SEE EF Geek EE E 000090 0 0 M Start BY N 1 saled with cover tape User Direction of Feed User direction of feed 28 31 Doc ID 018942 Rev 4 Top No components Components No components cover ER AE tape 500mm min 500mm min MSs Empty components pockets i GAPGCFT00421 X VND5T035AK E Order codes 6 Order codes Table 17 Device summary Order codes Package Tube Tape and reel PowerSSO 24 VND5TO35AK E VNDSTOSSAKTR E ky Doc ID 018942 Rev 4 29 31 Revision history VND5T035AK E 7 Revision history Table 18 Document revision history Date Revision Changes 21 Sep 2011 1 Initial release Updated Table 2 Suggested connections for unused and not 19 Oct 2011 2 connected pins Added note on Table 13 Electrical transient requirements part 2 Changed document status from preliminary data to definitive 26 Oct 2011 3 datasheet Updated Figure 13 Off state output current 13 Mar 2012 4 Updated Section 3 4 Maximum
14. dt On V us 42 40 4 0 70 42 20 0 60 42 00 41 80 0 50 41 60 0 40 41 40 0 30 od Vec 24V E 0 20 RL BOhm 40 80 0 10 40 60 40 40 t t t t 1 0 00 50 25 0 25 50 75 100 125 150 175 50 25 0 25 50 75 100 125 150 175 Tc C Tc C GAPGCFT00468 GAPGCFT00469 Figure 23 Turn off voltage slope dVout dt Off V us 0 60 0 50 4 0 40 4 0 30 4 Vcc 24V ns RL 8Ohm 0 10 4 0 00 50 25 0 25 50 75 100 125 150 175 Tc C GAPGCFT00470 ky Doc ID 018942 Rev 4 19 31 Application information VND5T035AK E 3 3 1 20 31 Application information Figure 24 Application schematic 5V RE 1 i Rsense GAPGCFT000119 GND protection network against reverse battery Solution 1 resistor in the ground line Rgnp only This solution can be used with any type of load The following is an indication on how to dimension the Renp resistor 1 Renp lt 600 mV Isionymay 2 Renp 2 CVoo lenp where lanp is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet Power dissipation in Renp when Vcc lt 0 during reverse battery situations is Pp Voc Rend This resistor can be shared amongst several different HSDs Please note that the value of this resistor should be calculated with formula 1 where Ig on max becomes the sum of the maximum on state currents of the different devices
15. sections of this specification is not implied Exposure to the conditions reported in this section for extended periods may affect device reliability Table 3 Absolute maximum ratings Symbol Parameter Value Unit Voc DC supply voltage 58 V Vcc Reverse DC supply voltage 0 3 V lenp DC reverse ground pin current 200 mA lout DC output current Internally limited A lour Reverse DC output current 40 A lin DC input current 1 to 10 mA IFR sty Fault reset standby DC input current 1to 1 5 mA lcsENsE DC reverse CS pin current 200 mA VCSENSE Current sense maximum voltage s to V Maximum switching ener FMAX L 23 mH ae 32 V Teta 150 C lour lim yp D Doc ID 018942 Rev 4 7 31 Electrical specifications VND5T035AK E Table 3 Absolute maximum ratings continued Symbol Parameter Value Unit Maximum strain inductance in short circuit condition Lsmax R 300 A o T 40 uH L 300 MO Vaar 32 V Tisia 150 C lout lLMHmax Electrostatic discharge Human Body Model R 1 5 KQ C 100 pF IN42 4000 V Vesp C842 2000 V FR_Stby 4000 V OUT 5000 V Vcc 5000 V Vesp Charge device model CDM AEC Q1 00 01 1 750 V Tj Junction operating temperature 40 to 150 C Tstg Storage temperature 55 to 150 C 2 2 Thermal data Table 4 Thermal data Symbol Parameter Value Unit Rinj case Thermal resistance junction cas
16. stpy 5 V Symbol Parameter Test conditions Min Typ Max Unit Openload off state VoL voltage detection Vi 0 V 8 V lt Vcc lt 36 V 2 4 V threshold Output short circuit to tpsrkoN Vcc detection delay at See Figure 7 180 1800 us turn off Off state output current Vin 0 V Vsense 0 V IL otta at Vout 4V Vour rising from 0 V to 4 V ed 2 p Delay response from Vout 4 V V 0 V td vel output rising edge to V 90 of V 20 us VSENSE rising edge in E 39K SENSEH openload SENSE Output short circuit to tOFRSTK ON Vcc detection delay at See Figure 9 Input 2 low 50 us FRSTBY activation Figure 6 Current sense delay characteristics INPUT l ee LOAD CURRENT ee HE pci c Hi HE SENSE CURRENT TosENSE2H tosensea GAPGCFT000117 Figure 7 Openload off state delay timing Vout gt VoL Vin VSENSEH m fosron GAPGCFT000113 Vfr_stby high Doc ID 018942 Rev 4 13 31 Electrical specifications VND5T035AK E 14 31 Figure 8 Switching characteristics Vout A hin lir gt i i i 90 i i i dVourldton Bourton 10 t t ml t INPUT A Taton Tato r4 F4 gt t GAPGCFT000114 Figure 9 Output stuck to VCC detection delay time at FRSTBY activation FRsrav NI VsenseH NI i 1 Vcs 1 1 H NI 1 L 4 NI prRsTK
17. 0438 1 The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections power limitation or thermal cycling during thermal shutdown are not triggered Doc ID 018942 Rev 4 ky VND5T035AK E Package and PCB thermal data Equation 1 Pulse calculation formula Zrus RtH Zgyg 1 78 where tp T Table 15 Thermal parameters Area island cm Footprint 2 8 R1 C W 0 5 R2 C W 0 75 R3 C W 1 m R4 C W 7 7 R5 C W 9 9 8 R6 C W 28 17 10 R7 C W 0 5 R8 C W 0 75 C1 W s C 0 005 C2 W s C 0 05 C3 W s C 0 1 C4 W s C 0 5 C5 W s C 1 4 9 C6 W s C 2 2 5 17 C7 W s C 0 005 C8 W s C 0 05 Ly Doc ID 018942 Rev 4 25 31 Package and packing information VND5T035AK E 5 Package and packing information 5 1 ECOPACK In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark 5 2 PowerSSO 24 package information Figure 30 PowerSSO 24 package dimensions aT Hi EER LEAD CDPLANARITY 6 e NC x ij m WE d E i Y nnm 4 INI IIH EDDIE
18. NPUTn i l z lstby tsby GAPGCFT000111 Table 8 Protections and diagnostics Symbol Parameter Test conditions Min Typ Max Unit Voc 24V 30 42 55 A limu DC short circuit current 5V lt Vcec lt 36V 55 A Short circuit current lime during thermal cycling Vcc 24 V TR lt Tj lt Trsp 10 3 A Ttsp Shutdown temperature 150 175 200 C TR Reset temperature Tast 1 TRs 5 C TRs Thermal reset of status 135 C Thermal hysteresis T 7 C HYST TreD TR Turn off output voltage 3 A Vin 0 VOENAG clamp p a Vcc 58 Vcc 64 Vcc 70 v Output voltage drop lour 150 mA V 25 mV ON limitation Tj 40 C 150 C i Doc ID 018942 Rev 4 11 31 Electrical specifications VNDSTOSSAK E Table 9 Current sense 8 V lt Vcc lt 36 V Symbol Parameter Test conditions Min Typ Max Unit lout 1 A Vsense 2 V K4 lour lsENsE Tj 40 C 150 C 1952 2960 4150 Tj 25 C 150 C 2080 3840 l 1A V 2V dK K Current sense ratio drift OUT ENE 15 15 96 uii Tj 40 C to 150 C lout 3 A Vsense 4 V Ko lour lsENsE Tj 40 C 150 C 2490 2930 3440 Tj 25 C 150 C 2585 3265 3A V 24V dK K5 Current sense ratio drift OUT r SENSE 10 10 POS Tj 40 C to 150 C lout 12 A Vsense 4 V K3 lOUT ISENSE Tj 40 C 150 C 2770 ooo 3125 Tj 25 C 150 C 2755 3045 l 12A V
19. TIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2012 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Is
20. age clamp protects the device against low energy spikes The device integrates an analog current sense which delivers a current proportional to the load current Fault conditions such as overload overtemperature or short to Vcc are reported via the current sense pin Output current limitation protects the device in overload conditions The device latches off in case of overload or thermal shutdown The device is reset by a low level pass on the fault reset standby pin A permanent low level on the inputs and on the fault reset standby pins disables all outputs and sets the device in standby mode Doc ID 018942 Rev 4 1 31 This is information on a product in full production www st com Contents VND5T035AK E Contents 1 Block diagram and pin description eeesssee 5 2 Electrical specifications iss ss kk RR RR ee 7 2 1 Absolute maximum ratings iss EE EE ke ee ee 7 2 2 Thermal dela us sod eS ek HARE ERS ARR RAS ED REED ERA DE SE ED oe 8 2 3 Electrical characteristics sisse kr hx RR RERO RR Re 9 2 4 Electrical characteristics curves 000 ese eee eee 18 3 Application information ss ss ER RR RR RR RR RR RR RE RR RR RR 20 3 1 GND protection network against reverse battery EE EE Ee ee 20 3 1 1 Solution 1 resistor in the ground line RGND only 20 3 1 2 Solution 2 diode DGND in the ground line nananana uaaa 21 3 2 Load dump protection ER SE Ra ru aa
21. demagnetization energy Vcc 24 V 4 30 31 Doc ID 018942 Rev 4 VND5T035AK E Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRAN
22. e max with one channel ON 2 C W Rthj amb Thermal resistance junction ambient max See Figure 27 C W 4 8 31 Doc ID 018942 Rev 4 VND5T035AK E Electrical specifications 2 3 4 Electrical characteristics 8 V lt Voc lt 36 V 40 C lt T lt 150 C unless otherwise specified Table 5 Power section Symbol Parameter Test conditions Min Typ Max Unit Voc Operating supply 8 24 36 V voltage Vusp Undervoltage shutdown 3 5 5 V Undervoltage shutdown VusDhyst hysteresis as M lout 3A T 25 C 35 Ron On state resistance 2 mQ lout 3 A Tj 150 C 70 Vclamp Clamp voltage lg 20 mA 58 64 70 V Off state Vec 24 V Tj 25 C 2 2 5 2 UA Vin Vout Vsense 0 V ls Supply current On state Voc 24V Vin 5V 4 2 6 mA Vin Vout 0 V Voc 24 V N T 25 C o 0 01 3 n Lioft state output current H off Vin VouT 0V Vec 24 V 0 5 Tj 125 C Output Vec diode TT Ve voltage lout 3 A Tj 150 C 0 7 V 1 For each channel 2 PowerMOS leakage included Table 6 Switching Vcc 24 V T 25 C Symbol Parameter Test conditions Min Typ Max Unit ta on Turn on delay time R 8Q 46 us ta off Turn off delay time R 280 54 us dVour dto Turn on voltage slope RL280 0 55 V us dVour dtiom Turn off voltage slope RL 8Q 0 46 V us Switching e
23. ion VNDSTOSSAK E 6 31 Figure 2 Configuration diagram PowerSSO 24 top view Vee i OUT1 NC E OUT1 CS1 OUT1 IN1 C OUT1 NC L OUT1 FR_Stby OUT1 GND OUT2 NC OUT2 IN2 OUT2 CS2 OUT2 NC OUT2 Vec H ET OUT2 jf TAB Voc zT TG GAPGCFT00435 Table 2 Suggested connections for unused and not connected pins Connection pin CurrentSense N C Output Input FR_Stby Floating Not allowed xt X X X To ground Through TOKS X Not allowed Through TORS Through 10 KQ resistor resistor 1 X do not care Doc ID 018942 Rev 4 VND5T035AK E Electrical specifications 2 Note 2 1 Electrical specifications Figure 3 Current and voltage conventions Is Voc I Voc Ven IER stby Bus loutn n VER Stby 4 Weng Vou i Stby SENSEn INn T CSn ri T A Vinn n SENSEn GND v lGND Ven Voutn Vcc during reverse battery condition Absolute maximum ratings Stressing the device above the ratings listed in the Table 3 may cause permanent damage to the device These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating
24. nergy losses _ Won during ho RL 8Q 1 mJ W Switching energy losses R 82 0 65 mi OEE during twor L i Doc ID 018942 Rev 4 9 31 Electrical specifications VNDSTOSSAK E 10 31 Table 7 Logic inputs Symbol Parameter Test conditions Min Typ Max Unit Vi Input low level voltage 0 9 V lit Low level input current Vin 0 9 V 1 HA Vin Input high level voltage 2 1 V li High level input current Vy 2 2 1 V 10 HA Vichyst Input hysteresis voltage 0 25 V lin 1mA 5 5 7 V Vict Input clamp voltage s IN 1 mA 0 7 v Fault_reset_standby low VFR_Siby_ level voltage 0 9 j V Low level IFR_Stby_L fault_reset_standby current VER sty 09 V 1 HA Fault_reset_standby high VFR Stby H level voltage e ii High level H IFR Stby H fault reset standby current VFR_stby 2 1 V 10 pA V FR_Stby Fault_reset_standby 0 25 V hyst hysteresis voltage y Fault reset standby clamp FR_stby 15 MA 10 ms 11 15 V FR Stby CL voltage IER sty 1 mA 0 7 V treset Overload latch off reset time See Figure 4 2 24 US tstby Standby delay See Figure 5 120 1200 us Figure 4 Treset definition T reset gt FR_STBY E P We IN OUTPUT si EE NE Overload Channel Doc ID 018942 Rev 4 GAPGCFT000112 X VND5T035AK E Electrical specifications Figure 5 Tstby definition FR Stdby Jo LE l I qoo I
25. ol pins are pulled negative ST suggests that a resistor Rpro have to be inserted in line to prevent the microcontroller I Os pins to latch up The value of these resistors is a compromise between the leakage current of the microcontroller and the current required by the HSD I Os Input levels compatibility with the latch up limit of microcontroller I Os Vccpeak liatchup lt Rprot Vouuc Viu VaND liHmax Calculation example For Vccpeak 600 V and liatchup 2 20 mA Vouuc 2 4 5 V 30 KO lt Rorot lt 180 KQ Recommended Rprot value is 60 KQ Doc ID 018942 Rev 4 21 31 Application information VND5T035AK E 3 4 Note 22 31 Maximum demagnetization energy Vcc 24 V Figure 25 Maximum turn off current versus inductance 100 E 0 1 1 10 100 1000 L mH GAPGCFT00094 A Tjstart 150 C single pulse B Tjstart 100 C repetitive pulse C Tistart 125 C repetitive pulse Vins I Demagnetization Demagnetization Demagnetization SE 5 gt t GAPGCFT00048 Values are generated with R 0 2 In case of repetitive pulses Tistan at the beginning of each demagnetization of every pulse must not exceed the temperature specified above for curves A and B Doc ID 018942 Rev 4 OT VND5T035AK E
26. rael Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 018942 Rev 4 31 31
27. ses ER SE SR Ge ee Re Ee Re ER ed ee eke dee 14 Output stuck to VCC detection delay time at FRSTBY activation 14 Delay response time between rising edge of ouput current and rising edge of current SENSE comte adea eed he See Goatees ip owen aria ba a are Whe GE Se a af an tec a ie We eee 15 Output voltage drop limitation se se ke eke ee III 15 Device behavior in overload condition EE EE EE Ee eene 16 Off state output current 0 0 0 0 s 18 High level input current s rss se ss EE RE EE nead ER ee eer 18 Input clamp voltage ss ee ete 18 High level input voltage es Ee es ee ee ee ke ee ee ee ee ee ek ee ee ke ee ee 18 Low level input voltage es ee es ee ee RII a 18 Input hysteresis voltage ie se ee tees 18 On state resistance VS Tease ts Ms se ke Re ee ER RE hmm eee 19 On state resistance VS VOC sie ee EE ne 19 ILIMH VS Tease Dea a a MEE BE as Saas EE ims gn HE OS EIE RR By a a S Tah de ao nes 19 Turn on voltage slope 6 ie se se ee ete nn 19 Turn off voltage slope 6 tees 19 Application schematiC EE EG SE RR IRR I es 20 Maximum turn off current versus inductance ssaa aaaea 22 PowerSSO 24 PC board ie Ee Ee EE eee 23 Rthj amb vs PCB copper area in open box free air condition one channel ON 23 PowerSSO 24 thermal impedance junction ambient single pulse one channel ON 24 Thermal fitting model of a double channel HSD in PowerSSO 24

ST VND5T035AK-E handbook

Contents

Download Pdf Manuals

Related Search

Related Contents