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ANALOG DEVICES OP221 handbook

1. Supply Voltage Output Short Circuit Duration Indefinite Storage Temperature Range 65 C to 150 C Operating Temperature Range OP221A ec EXPE A ALAS 55 C to 125 C OP221IB nc xS ERE RS 25 C to 85 C OPZ221G cba eei idear 40 C to 85 C Lead Temperature Soldering 60 sec 300 C Junction Temperature Ty 65 C to 150 C Package Type Oya Note 2 Bic Unit 8 Lead Hermetic DIP Z 148 16 C W 8 Lead Plastic DIP P 103 43 C W 8 Lead SO S 158 43 C W NOTES Absolute maximum ratings apply to both DICE and packaged parts unless otherwise noted a is specified for worst case mounting conditions i e fa is specified for device in socket for TO Cerdip and PDIP packages elA is specified for device soldered to printed circuit board for SO package ORDERING INFORMATION Ta 25 C Packages Operating Package Vos MAX Cerdip Plastic Temperature Options pV 8 Lead 8 Lead Range 150 OP221AZ MIL Q 8 150 OP221 EZ IND 300 500 500 OP221GP XIND R 8 500 OP221GS XIND Burn in is available on commercial and industrial temperature range parts in CerDIP plastic DIP and TO can packages For devices processed in total compliance to MIL STD 883 add 883 after part number Consult factory for 883 data sheet 3Not for new design obsolete April 2002 DIE SIZE 0 097 X 0 063 I
2. 8 Lead SOIC Package R 8 0 1968 5 00 e 890 CM 8 5 0 1574 4 00 0 2440 6 20 0 1497 3 80 a 0 2284 5 80 v a AY o O PINA oo 0 0500 1 27 0 0196 0 50 BSC 0 0099 0 25 0 102 2 59 0 0098 0 25 y 0 094 2 39 y 0 0040 0 10 4 4 el F 8 gt le SEATING 99192 0 49 0 0098 0 25 05 0 0500 1 27 PLANE 0 0138 0 35 0 0075 0 19 00160 0 41 10 REV A Revision History Location Page 09 01 Data Sheet changed from REV 0 to REV A Edits t6 PIN CONNECTIONS 92 5 pe A Ex ee NE Bos e td ble Na ole ede 1 Global deletion of references to OP221B and OP221C 2 e e s 2 3 4 Edits to WAFER TEST LIMITS A dice phic rotten A ia eau dd led da da 4 Edits to ABSOLUTE MAXIMUM RATINGS 0 5 Edits to ORDERING GUIDE a a hah he 5 Edits to PACKAGE TYPE vr adas 5 REV A 11 V Z0 L 0 yze00D VSNNI G3LNIYd 12
3. SIMPLIFIED SCHEMATIC ACCESSIBLE IN CHIP FORM ONLY REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use norfor any infringements of patents or other rights ofthird parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Oo 0 s E Mi IH y y V Q T L O OUTPUT Q9 Q10 A T V One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 Analog Devices Inc 2002 0P22 1 SPEC FI GATI 0 NS Electrical Characteristics at V 2 5 V to 15 V T 25 C unless otherwise noted OP221A E OP221G Parameter Symbol Conditions Min Typ Max Min Typ Max Unit Input Offset Voltage Vos 75 150 250 500 uV Input Offset Current Ios Vem 0 0 5 3 1 5 7 nA Input Bias Current Ig Vem 0 55 100 70 120 nA Input Voltage Range IVR V 5 V V 0 V Note 2 0 3 5 0 3 5 v Vg 15V 15 13 5 15 13 5 Common Mode CMRR V 5V V 0V Rejection Ratio OV lt Vey lt 35V 90 100 75 85 VSs 15 V dB 15 V lt Vey lt 13 5 V 95 100 80 90 Power Supply PSRR Vs 12 5 V to 15 V 3 10 32 100 Rejection Ratio V 0V V 5Vto 30 V 6 18 57 180 EVV Large Signal Avo Vs 15 V Ri 10 kQ Voltage Gain Vo 10 V
4. 1500 800 V mV Output Voltage Vo V 5V V 0V 0 7 4 1 0 8 4 V Swing Ri 10 kQ Vs 15V Rp 10 kQ 13 8 413 5 Slew Rate SR Ri 10 kQ Note 1 0 2 0 3 0 2 0 3 V uS Bandwidth BW 600 600 kHz Supply Current Isy Vs 12 5 V No Load 450 550 550 650 uA Both Amplifiers Vs 15 V No Load 600 800 850 900 NOTES Sample tested Guaranteed by CMRR test limits 2 REV A SPECIFICATION Electrical Characteristics at Vs 2 5 V to 15 V 55 C lt T 125 for OP221A 25 T lt 85 for 0P221E 40 C lt T lt 85 for 0P2216 unless otherwise noted 0P221 OP221A E OP221G Parameter Symbol Conditions Min Typ Max Min Typ Max Unit Average Input TCVos 0 75 1 5 2 3 uV C Offset Voltage Input Offset Voltage Vos 150 300 400 700 uV Input Offset Current Ios Vcu 0 1 5 2 10 nA Input Bias Current Ig Vom 0 55 100 80 140 nA Input Voltage Range IVR V 5 V V 0V Note 2 0 3 2 0 3 2 V Vs 15V 15 13 2 15 13 2 Common Mode CMRR V 5 V V 0V Rejection Ratio 0 V lt Vey lt 3 V 85 90 70 80 Vs 15V dB 15 V s Vey lt 13 5 V 90 95 75 85 Power Supply PSRR Vs 2 5 V tot 15 V 6 18 57 180 Rejection Ratio V 0V V 25V to 30 V 10 32 100 320 HVIV Large Signal Avo Vs 15 V Ri 10 kQ V mV Voltage Gain Vo l0 V 1000 600 E Output Voltage Vo V 5V V 0V 0 8 3 8 0 9 3 7 Swing Ri 10 kQ V Vs 15 V Ri 10 KQ 13 5 13
5. 2 Supply Current Isy Vs 2 5 V No Load 500 650 600 750 uA Both Amplifiers Vs 15 V No Load 700 900 950 1000 NOTES 1Sample tested Guaranteed by CMRR test limits Matching Characteristics at V 15 V T 25 C unless otherwise noted OP221A E OP221G Parameter Symbol Conditions Min Typ Max Min Typ Max Unit Input Offset Voltage Match AVos 50 200 250 600 uV Average Noninverting Bias Current Ig 80 120 nA Noninverting Input lost 2 5 4 10 nA Offset Current Common Mode Rejection Ratio ACMRR Vem 15 V to 13 5 V 92 72 dB Match Note 1 Power Supply Rejection Ratio APSRR Vs 2 5 Vto 15 V 14 140 UV V Match Note 1 REV A 3 0P221 SPECIFICATION Matching Characteristics at V 15 V 55 C x T x 125 C for OP221A 25 C lt T 85 C for 0P221E 40 C lt T lt 85 C for 0P221G unless otherwise noted Grades E and G are sample tested OP221A E OP221G Parameter Symbol Conditions Min Max Min Typ Max Unit Input Offset Voltage Match AVos 400 400 800 uV Average Noninverting Ig Vem 0 100 140 nA Bias Current Input Offset ICAVos 2 3 5 uV C Voltage Tracking Noninverting Input Iost Vom 0 7 6 12 nA Offset Current Common Mode Rejection Ratio ACMRR Vey z 15 V to 13 2 V 87 12 80 dB Match Note 1 Power Supply Rejection Ratio APSRR 26 140 UV V Match Note 1 NOTES ACMRR is 20 logi Vem ACME where Vcy is the voltage applied to both noninverting i
6. E nV VHz 10 1 10 100 1k FREQUENCY Hz TPC 13 Voltage Noise Density vs Frequency REV A 14 L Ta 25 C Vg 15V gt 12 ki POSITIVE 2 10 a T 5 NEGATIVE O 8 s jej 6 x S 4 2 0 100 ik 10k 100k LOAD RESISTANCE Q TPC 11 Maximum Output Voltage vs Load Resistance CURRENT NOISE pAvHz FREQUENCY Hz TPC 13 Current Noise Density vs Frequency Ta 25 C 2 0 Vs 2 5V NEGATIVE z k POSITIVE 2 n E 2 O 10 z 2 x lt z 0 100 ik 10k 100k LOAD RESISTANCE Q TPC 12 Maximum Output Voltage vs Load Resistance 0P221 Figure 2a Noninverting Step Response Figure 3a Inverting Step Response Figure 2b Noninverting Step Response Figure 3b Inverting Step Response INPUT 100 OUTPUT INPUT 10kO JOKO OUTPUT Figure 4 TBD Figure 5 TBD 8 REV A SPECIAL NOTES ON THE APPLICATION OF DUAL MATCHED OPERATIONAL AMPLIFIERS Advantages of Dual Monolithic Operational Amplifiers Dual matched operational amplifiers provide the engineer with a powerful tool for designing instrumentation amplifiers and many o
7. NCH 6111 SQ MILS 2 464 X 1 600 MM 3 94 SQ MM 1 INVERTING INPUT A 2 NONINVERTING INPUT A 3 BALANCE A 4 V 5 BALANCE B 6 INVERTING INPUT B 7 NONINVERTING INPUT B 8 BALANCE B 9 V 10 OUT B 11 V 12 OUT A 13 V 14 BALANCE A NOTE ALL V PADS ARE INTERNALLY CONNECTED Figure 1 Dice Characteristics CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the OP221 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING mad ESD SENSITIVE DEVICE REV A 5 Typical Perfomance Characteristics 0P221 140 OPEN LOOP GAIN dB 25 0 TEMPERATURE C 25 50 75 100 125 TPC 1 Open Loop Gain at 15 V vs Temperature 120 100 Vg 2 15V Vg 5V OPEN LOOP GAIN dB 01 1 10 100 ik 10k 100k 1M 10M FREQUENCY Hz TPC 4 Open Loop Gain at 15 V vs Frequency Vg 15V PHASE MARGIN PHASE MARGIN Degrees SLEW RATE Ji 25 50 75 TEMPERATURE C 100 125 TPC 7 P
8. OO OP2210 0 0 ANALOG Dual Low Power Operational Amplifier DEVICES Single or Dual Supply FEATURES Excellent TCVos Match 2 pV C Max Low Input Offset Voltage 150 kV Max Low Supply Current 550 pA Max Single Supply Operation 5 V to 30 V Low Input Offset Voltage Drift 0 75 pV C High Open Loop Gain 1500 V mV Min High PSRR 3 p V V Wide Common Mode Voltage Range V to within 1 5 V of V Pin Compatible with 1458 LM158 LM2904 Available in Die Form GENERAL DESCRIPTION The OP221 is a monolithic dual operational amplifier that can be used either in single or dual supply operation The wide supply voltage range wide input voltage range and low supply current drain of the OP221 make it well suited for operation from batteries or unregulated power supplies The excellent specifications of the individual amplifiers combined with the tight matching and temperature tracking between channels PIN CONNECTIONS 8 Lead SO 8 Lead S Suffix HERMETIC DIP Z Suffix NC NO CONNECT NC lt NO CONNECT provide high performance in instrumentation amplifier designs The individual amplifiers feature very low input offset voltage low offset voltage drift low noise voltage and low bias current They are fully compensated and protected Matching between channels is provided on all critical parameters including input offset voltage tracking of offset voltage vs tem perature non inverting bias currents and common mode rejection
9. hase Margin Gain Bandwidth and Slew Rate vs Temperature N BANDWIDTH Hz 140 dc 120 100 80 60 40 OPEN LOOP GAIN dB E I N 25 0 25 50 75 TEMPERATURE C 100 125 TPC 2 Open Loop Gain at 5V vs Temperature CLOSED LOOP GAIN dB 1k FREQUENCY Hz 10k 100k 1M 10M TPC 5 Closed Loop Gain vs OPEN LOOP GAIN dB 140 120 100 0 x5 10 SUPPLY VOLTAGE V TPC 3 Open Loop Gain at vs S VOLTAGE GAIN dB upply Voltage 80 100 120 140 160 180 PHASE SHIFT Degrees 200 220 1M FREQUENCY Hz 10M TPC 6 Gain and Phase Shift vs Freguency Freguency 120 120 100 PSRR 100 80 80 a z 1 1 c 60 z 60 s o PSRR 5 40 40 Ta 25 C s 20 F v 15V 0 0 100 1k FREQUENCY Hz 10k 100k TPC 8 PSRR vs Frequency 1k FREQUENCY Hz 100 10k 100k TPC 9 CMRR vs Frequency REV A PEAK TO PEAK AMPLITUTDE V FREGUENCY Hz TPC 10 Maximum Output Swing vs Freguency 100 80 70 60 50 40 30 20 VOLTAGE NOIS
10. mon mode and differential voltage both appear at V1 The high open loop gain of the OP221 is very important in achieving good CMRR in this configuration Finite open loop gain of Al Aol causes undesired feedthrough of the common mode input For Ad Ao lt lt 1 the common mode error CME at the out put due to this effect is approximately 2 Ad Aol x VCM This circuit features independent adjustment of CMRR and differ ential gain Three Op Amp Configuration The three op amp circuit Figure 8 has increased common mode voltage range because the common mode voltage is not amplified as it is in Figure 7 The CMR of this amplifier is directly proportional to the match of the CMR of the input op amps CMRR can be raised even further by trimming the output stage resistors Ra 1 R2 R3y R2 R3 RA R3 R2 vo Ri 1 3 Ri R4 RO 8 Bt vem IF R1 R2 R3 R4 THEN Vo 2 1 BD v 2 R9 R4 o RO J Vo Figure 7 Two Op Amp Circuit Figure 8 Three Op Amp Circuit 0P221 OUTLINE DIMENSIONS Dimensions shown in inches and mm 8 Lead CERDIP Package Q 8 0 005 0 13 0 055 1 4 MIN MAX 0 310 7 87 0 220 5 59 SR ka 0 100 2 54 BSC 0 405 10 29 MAX 0 320 8 13 pe gt 0 290 7 37 0 060 1 52 0 200 5 08 0 015 0 38 MAX MANE 0 150 0 200 5 08 3 81 0 125 3 18 N y MIN gt 0 015 0 38 SEATING S cid d izbi 0 023 0 58 0 070 1 78 PLANE a 0 008 0 20 0 014 0 36 0 030 0 76
11. nputs and ACME is the difference in common mode input referred error APSRR is Input Referred Differential Error AVs Wafer Test Limits at V 2 5 V to 15 V T 25 C unless otherwise noted OP221N Parameter Symbol Conditions Limit Unit Input Offset Voltage Vos 200 UV Max Input Offset Current los Vom 0 3 5 nA Max Input Bias Current Ig Vom 70 85 nA Max Input Voltage Range IVR V 5V V 0V 0 3 5 V Min Max Vs 15 V 15 13 5 V Min Common Mode CMRR V 0 V V 5V 88 Rejection Ratio 0 V lt Vems 3 5 V Vs z 15 V dB Min 15 V s Vey lt 13 5 V 93 Power Supply PSRR Vs 2 5 V tot 15V 12 5 Rejection Ratio V 0V V 25V 1030 V 22 5 VimV Min Large Signal Avo Vs z 15V Voltage Gain R 10kQ 1299 V mV Max Output Voltage Swing Vo V 5 V V 0 V R 10 kQ 0 7 4 1 V Min Max Vs 15 V R 10 kQ 13 8 V Min Supply Current Isy Vs 2 5 V No Load 560 uA Max Both Amplifiers Vs 15 V No Load 810 NOTE Electrical tests are performed at wafer probe to the limits shown Due to variations in assembly methods and normal yield loss yield after packaging is not guaranteed for standard product dice Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing REV A ABSOLUTE MAXIMUM RATINGS Note 1 Supply Voltage 18 V Differential Input Voltage 30 V or Supply Voltage Input Voltage
12. ther differential input circuits These designs are based on the principle that careful matching between two operational amplifiers can minimize the effect of dc errors in the individual amplifiers Reference to the circuit shown in Figure 6 a differential in differential out amplifier shows how the reductions in error can be accomplished Assuming the resistors used are ideally matched the gain of each side will be identical If the offset voltages of each amplifier are perfectly matched then the net differential voltage at the amplifier s output will be zero Note that the output offset error of this amplifier is not a function of the offset voltage of the individual amplifiers but only a function of the difference degree of matching between the amplifiers offset voltages This error cancellation principle holds for a considerable number of input referred error parameters offset voltage offset voltage drift inverting and noninverting bias currents common mode and power supply rejection ratios Note also that the impedances of each input both common mode and differential mode are high and tightly matched an important feature not practical with single operation amplifier circuits Figure 6 Differential In Differential Out Amplifier REV A INSTRUMENTATION AMPLIFIER APPLICATIONS Two Op Amp Configuration The two op amp circuit Figure 7 is recommended where the common mode input voltage range is relatively limited the com

ANALOG DEVICES OP221 handbook

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