Home

ST VND5E050AJ-E/VND5E050AK-E handbook

1. 32 Rthj amb vs PCB copper area in open box free air condition one channel ON 33 PowerSSO 24 thermal impedance junction ambient single pulse one channel ON 34 Thermal fitting model of a double channel HSD in 550 24 34 PowerSSO 12 package 5 36 PowerSSO 24 package 5 38 PowerSSO 12 tube shipment no suffix 40 PowerSSO 12 tape and reel shipment suffix 40 PowerSS0 24 tube shipment no 5 41 Doc ID 14617 Rev 4 VND5E050AJ E VND5E050AK E List of figures Figure 48 PowerSSO 24 tape and reel shipment suffix 41 ky Doc ID 14617 Rev 4 5 44 Block diagram and pin description VND5E050AJ E VND5E050AK E 6 44 Block diagram and pin description Figure 1 Block diagram Signal Clamp Ice e e Undervoltage Control amp Diagnost
2. 8 2 1 Absolute maximum ratings 8 2 2 Thermal data 9 2 3 Electrical 5 5 9 2 4 Waveftorms ars boda bad VAG d 19 2 5 Electrical characteristics curves 22 3 Application information 25 3 1 GND protection network against reverse battery 25 3 1 1 Solution 1 resistor the ground line RGND only 25 3 1 2 Solution 2 diode DGND the ground line 26 3 2 Load dump 26 3 3 MCU OS 26 3 4 Current sense and 26 3 4 1 Short to VCC and off state open load detection 27 3 5 Maximum demagnetization energy 13 5V 29 4 Package and PCB thermal data 30 4 1 PowerSSO 12 thermal data 30 4 2 PowerSSO 24 thermal data 32 5 Package and packing information 36 Gi PME 36 5 2 PowerSSO 12 package information 36 5 3 PowerSSO 24 package information
3. 5 13 Open load off state delay 14 Switching characteristics 14 Delay response time between rising edge of output current and rising edge of current sense CS enabled sc cedente Rn dO ene en RR Se 15 Output voltage drop 15 lout IsENSE VS louT eth Sree ee P 16 Maximum current sense ratio drift vs load 16 Normal operation 19 Overload or short to 19 Intermittent 20 Off state open load with external 20 SNO VGC EACH E Cc T 21 Ty evolution in overload or short to GND 21 Off state output 22 High level input 22 Input clamp 22 Input low level eren DR num iore pda ee m d wee 22 Input high leVel css een he coms
4. De EA kale RC e e 22 Input hysteresis voltage 22 On state resistance vs 5 23 On state resistance vs 23 Undervoltage shutdown 23 Turn on voltage 5 23 os Ue ate RACE QUAS EUR RR wr RR n 23 Turn off voltage 5 23 CS DIS high level voltage 24 CS DIS clamp 24 CS DIS low level 24 Application 25 Current sense and 27 Maximum turn off current versus inductance for each 29 PowerSSO 12 PC 30 Rthj amb Vs PCB copper area in open box free air condition one channel ON 30 PowerSSO 12 thermal impedance junction ambient single pulse one channel ON 31 Thermal fitting model of a double channel HSD in 550 12 31 PowerSSO 24 PC
5. 38 5 4 PowerSSO 12 packing information 40 5 5 PowerSSO 24 packing information 41 6 Order codes Pn 42 7 Revision history 43 2 44 Doc ID 14617 Rev 4 ky VND5E050AJ E VND5E050AK E List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Pin fUnctioni iis enne pae eeu eA eda vus 6 Suggested connections for unused and not connected pins 7 Absolute maximum 8 Thermal data odes x Ro coram RU ES ais RR OR uc Re e e Ug E 9 Power Section xls esed sr xe bea duda pA denaro Peed gu Re ee ars 9 Switching VCC 13V Tj 25 10 LOGIC Cr 10 Protections and diagnostics 11 Current sense aV Vcec 18V 11 Open load detection 8 lt lt 18 13 UM 17 Electrical transient requirements part 1 18 Electrical transient requirements part 2 18 E
6. VND5E050AJ E VND5E050AK E Package and packing information 5 5 PowerSSO 24 packing information Figure 47 PowerSS0 24 tube shipment no suffix Base qty 49 Bulk qty 1225 Tube length 0 5 532 A 3 5 B 13 8 C 0 1 0 6 All dimensions are in mm Figure 48 PowerSSO 24 tape and reel shipment suffix TR EN ES REEL DIMENSIONS H 40mm Access hole at slot location 7N Base qty 1000 ENIM N Bulk qty 1000 A max 330 1 5 qe LEES C 50 2 18 E F 20 2 i b 21 0 244 Full adus 07 7 min 100 2 30 4 tape start i 2 5mm min width r TAPE DIMENSIONS According to Electronic Industries Association EIA Standard 481 rev A Feb 1986 Tape width 24 TOP Tape hole spacing PO 0 1 4 eid Component spacing P 12 Hole diameter D 50 05 1 55 Hole diameter D1 min 1 5 Hole position 0 1 11 5 Compartment depth 2 85 kh Hole spacing P1 0 1 2 Start End All dimensions are in mm No components Components No components cover h u ae tape 500mm min 500mm min Empty components pockets 49 sealed with cover tape v di User Direction
7. Trsp Tg Visi odium Output voltage 2A Vin 0 L 6mH 41 46 52 V lout 0 1 A Output voltage dro Von T 9 40 150 25 mV limitation see Figure 8 1 To ensure long term reliability under heavy overload or short circuit conditions protection and related diagnostic signals must be used together with a proper software strategy If the device is subjected to abnormal conditions this software must limit the duration and number of activation cycles Table 9 Current sense 8V Vcc 18V Symbol Parameter Test conditions Min Typ Max Unit K louT 0 05A Vsense 0 5V Vesp 0V 9 Tj 40 150 1440 2250 3630 lout Vsense 4V Vcsp 0V Ky lout IsENSE Tj 40 C 150 C 1740 2070 2820 Tj 25 C 150 C 1750 2070 2562 Current sense ratio lour 1 Vsense 4V dK K Vcsp 0V 15 15 96 Ty 40 C to 150 C Doc ID 14617 Rev 4 11 44 Electrical specifications VND5E050AJ E VND5E050AK E 12 44 Table 9 Current sense 8V Vcc 18V continued Symbol Parameter Test conditions Min Typ Max Unit lout 2A Vsense 4V Vcsp OV K2 lour lsENsE Tj 40 C 150 C 1900 2000 2395 T 25 C 150 C 1899 2000 2282 Current sense ratio lour 2 Vsense 4 V di Vcsp 0V 9 9 40 C to 150 lour 4 Vsense 4V Vcsp OV K3 lOUT SENSE Tj 40
8. kyy VND5E050AJ E VNDSE050AK E Double channel high side driver with analog current sense for automotive applications Features Max transient supply voltage Voc 41V Operating voltage range Vec 4 5 to 28 On state resistance per ch Ron 50 Current limitation typ lii MH 27 Off state supply current Is 2 pA 1 Typical value with all loads connected m General Inrush current active management by power limitation Very low standby current 3 0 CMOS compatible inputs Optimized electromagnetic emissions Very low electromagnetic susceptibility n compliance with the 2002 95 EC european directive Very low current sense leakage m Diagnostic functions Proportional load current sense High current sense precision for wide currents range Current sense disable Off state open load detection Output short to Vcc detection Overload and short to ground power limitation indication Thermal shutdown indication m Protections Undervoltage shutdown Overvoltage clamp Load current limitation Self limiting of fast thermal transients Protection against loss of ground and loss of Voc Over temperature shutdown with auto restart thermal shutdown July 2009 PowerSSO 24 n PowerSSO 12 Reverse battery protected see Figure 32 Electrostatic discharge protectio
9. Max Unit Voc Operating supply voltage 4 5 13 28 V Vusp Undervoltage shutdown 3 5 4 5 Undervoltage shutdown Vusphyst hysteresis 0 5 V louT 2 Tz 25 50 Row _ On state resistance lout 2A T 150 C 100 mQ lout 2A 5V T 25 C 65 Velamp Clamp voltage 15 20mA 41 46 52 V Doc ID 14617 Rev 4 9 44 Electrical specifications VND5E050AJ E VND5E050AK E 10 44 Table 5 Power section continued Symbol Parameter Test conditions Min Typ Max Unit Off state 13V 25 2 52 UA S ViN Vour VsENsE Vcsp 0V S upply current On state 13V 3 6 mA lour 0A Vin Vout Ov Voc 13V 0 0 01 3 Tj 25 C Off state output current 1 pA Vin VouT OV 13V 0 5 Tj 125 C Ve Output Vcc diode voltage 1 4A T 150 C 07 1 Foreach channel 2 PowerMOS leakage included Table 6 Switching Vcc 13V Tj 25 Symbol Parameter Test conditions Min Typ Max Unit Turn on delay time 6 50 see Figure 6 20 us Turn off delay time 6 50 see Figure 6 45 us dVour dt Turn on voltage slope 6 50 288 V us OUT C on L7 9 Figure 26 dVour dt Turn off voltage slope R 6 50 See V us OUT LT Figure 28 Switching energy E Won losses during tyon 6 50 see Figure 6 0 15 mJ Switching energy
10. 150 1969 1990 2210 T 25 C 150 C 1950 1990 2153 _ 4 Vsense 4 V dKyKs sense ratio 6 6 40 to 150 C lout Vsense 0V Vosp 5V Vin OV T 40 C 150 C 0 1 Analog sense Vesp OV Vin 5V T 40 C 150 C 0 2 ISENSEO leakage current HA lout 2A Vsense OV 0 1 T 2 40 150 Open load on state Vin 5V 8V lt V 18V lo current detection IN n lt 4 20 mA threshold SENSE 5 H Max analog sense V loyt 4 Vegp OV 5 V SENSE output voltage OUT CSD Analog sense VSENSEH output voltage in 13V RsENsE 3 9 KO 8 V fault condition Analog sense ISENSEH output current in Vcc 13V VaENsE 5V 9 mA fault condition e hes Vsense lt 4V 0 5A lt lout lt 4A ime from fallin tDSENSE1H edge of ISENSE 90 of ISENSEMAX 40 100 ps pin see Figure 4 response Y ense lt 4V 0 5A lt lout lt 4A ime from rising DSENSE1L edge of CS_DIS SENSE 10 of ISeNsEMAX 5 20 ps see Figure 4 Delay response Vsense lt 4V 0 5A lt lout lt 4A tpsENSE2H time from rising IseEnsE 90 of ISENSEMAX 80 250 us edge of INPUT pin see Figure 4 Doc ID 14617 Rev 4 VND5E050AJ E VND5E050AK E Electrical specifications 4 Table 9 Current sense 8V Vcc 18V continued Symbo
11. C W 26 20 15 C1 C7 W s C 0 001 C2 C8 W s C 0 0025 W s C 0 05 W s C 0 2 0 1 0 1 C5 W s C 0 27 0 8 1 C6 W s C 3 6 9 PowerSSO 24 thermal data Figure 39 PowerSSO 24 PC board PSS024L y PSS024L PSS024L 2cm 2 2 e Layout condition of Hy 2 measurements PCB Double layer Thermal Vias FR4 area 77mm x 86mm PCB thickness 1 6mm Cu thickness 70um front and back side Copper areas from minimum pad lay out to 8 Doc ID 14617 Rev 4 VND5E050AJ E VND5E050AK E Package and PCB thermal data Figure 40 Rthj amb vs PCB copper area in open box free air condition one channel ON RTHj amb C W 55 50 4 45 40 35 PCB Cu heatsink area cm 2 ki Doc ID 14617 Rev 4 33 44 VND5E050AJ E VND5E050AK E Package and PCB thermal data PowerSSO 24 thermal impedance junction ambient single pulse one Figure 41 channel ON 0 01 0 1 Time s 0 0001 0 001 Equation 2 pulse calculation formula 2 1 where 6 Figure 42 Thermal fitting model of a double channel HSD PowerSSO 24 P b The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections power limitation or thermal cycling during thermal shutdown ar
12. Renp resistor 1 Rann lt 600mV Isionymax 2 Rawp2 CVoo where is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet Power dissipation in Renp when lt 0 during reverse battery situations is Pp Voc Renp This resistor can be shared amongst several different HSDs Please note that the value of this resistor should be calculated with formula 1 where becomes the sum of the maximum on state currents of the different devices Please note that if the microprocessor ground is not shared by the device ground then the Renp Will produce a shift in the input thresholds and the status output values This shift will vary depending on how many devices are on in the case of several high side drivers sharing the same Doc ID 14617 Rev 4 25 44 Application information VND5E050AJ E VND5E050AK E 3 2 3 3 3 4 26 44 If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Section 3 1 2 Solution 2 diode DGND in the ground line Solution 2 diode the ground line A resistor 1 9 should be inserted in parallel to if the device drives an inductive load This small signal diode can be safely shared amongst several different HSDs Also in this case the pr
13. Worr losses during t os 6 50 see Figure 6 0 3 mJ Table 7 Logic inputs Symbol Parameter Test conditions Min Typ Max Unit Vu Input low level voltage 0 9 V li Low level input current Vin 0 9V 1 HA Vin Input high level voltage 2 1 V li High level input current Vin 2 1V 10 HA Vitnyst Input hysteresis voltage 0 25 V lin 1 mA 5 5 7 Vic Input clamp voltage mA 0 7 VcspL DIS low level voltage 0 9 V Low level CS DIS E lcspL current Vcsp 0 9V 1 pA Doc ID 14617 Rev 4 VND5E050AJ E VND5E050AK E Electrical specifications 4 Table 7 Logic inputs continued Symbol Parameter Test conditions Min Typ Max Unit CS_DIS high level voltage en b High level CS DIS current 2 1 V 10 pA CS DIS hysteresis Vesp hyst voltage 0 25 V 1 5 5 7 CS_DIS clamp voltage 1 0 7 Table 8 Protections and diagnostics 1 Symbol Parameter Test conditions Min Typ Max Unit xxl 13 19 27 38 A li DC short circuit current imh 28V 38 Short circuit current limL during thermal cycling 13V lt lt 7 Trsp Shutdown temperature 150 175 200 C TR Reset temperature Trst1 TRs 5 C Trs Thermal reset of status 135 C Thermal hysteresis Tuyst 7 ST
14. X X Through 1 KQ Through 22 KO Through 10 Through 10 KQ To ground X resistor resistor resistor resistor Doc ID 14617 Rev 4 7 44 Electrical specifications VND5E050AJ E VND5E050AK E 2 Note 2 1 8 44 Electrical specifications Figure 3 Current and voltage conventions 15 Ven losp OUTPUT1 Vespi ons Vouri lint CURRENT sense1 ae SENSE1 INPUT1 VSENSE1 4 lout2 N2 OUTPUT2 V INPUT2 IN2 CURRENT sense2 SENSE GND VsENsSE2 lenp Ven Voutn Vcc during reverse battery condition Absolute maximum ratings Stressing the device above the rating listed in the Absolute maximum ratings table may cause permanent damage to the device These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied Exposure to the conditions in table below for extended periods may affect device reliability Refer also to the STMicroelectronics SURE Program and other relevant quality document Table 3 Absolute maximum ratings Symbol Parameter Value Unit Voc DC supply voltage 41 V Reverse DC supply voltage 0 3 V laND DC reverse ground pin current 200 mA lout DC output curre
15. according to the following formula Rpp Voy Roy Rpp ub V E L off 2 r OUT Pull up ON z ER gt AV For the values of Voi min Voi max L ott2 r and IL ott2 See Table 10 Open load detection 8V lt Voc lt 18V Doc ID 14617 Rev 4 ky VND5E050AJ E VND5E050AK E Application information 3 5 Maximum demagnetization energy Vcc 13 5V Figure 34 Maximum turn off current versus inductance for each channel 100 TIT VGOHHT T TT 10 x 1 T T 0 1 1 L mH 10 100 Tjstart 150 C single pulse B Tistart 100 C repetitive pulse Tistart 125 C repetitive pulse Vine IL A Demagnetization Demagnetization Demagnetization Pal N m ma gt t Note Values are generated with 0 Q In case of repetitive pulses at beginning of each demagnetization of every pulse must not exceed the temperature specified above for curves and ky Doc ID 14617 Rev 4 29 44 Package and PCB thermal data VND5E050AJ E VND5E050AK E 4 4 1 Note 30 44 Package and PCB thermal data PowerSSO 12 thermal data Figure 35 PowerSSO 12 PC board PSSO12L PSSOL2L 7 PSSO12L 497 We 2cm 2 the 8cm 2 he Layout condition of Hy 2 measurements PCB Double layer Thermal Vias FR4 area 77mm x 86mm PCB thickness 1 6mm Cu thickness 70
16. the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different
17. 125 150 175 50 25 0 25 50 75 100 125 150 175 Tc C Figure 21 Input high level Figure 22 Input hysteresis voltage Vih V Vihyst V 4 1 0 9 3 5 0 8 3 0 7 2 5 0 6 2 0 5 0 4 15 0 3 1 0 2 0 5 0 1 0 0 50 25 0 25 50 75 100 125 150 175 50 25 0 25 50 75 100 125 150 175 22 44 Doc ID 14617 Rev 4 VND5E050AJ E VND5E050AK E Electrical specifications Figure 23 On state resistance vs Tease Figure 24 On state resistance vs Vcc Ron mOhm 300 250 lout 2A Vec 13V 200 150 100 50 Ron mOhm 100 150 80 T 125 60 25 40 40 20 0 0 5 10 15 20 25 30 35 40 Vcc V Figure 25 Undervoltage shutdown Figure 26 Turn on voltage slope Vusd V 50 25 0 25 50 75 100 125 150 175 dVout dt On V ms 1000 900 Vec 13V _ RI 6 5 Ohm 700 600 500 400 300 Figure 27 VS Tease Figure 28 Turn off voltage slope llimh A 40 35 Vcc 13V 30 25 20 50 25 0 25 50 75 100 125 150 175 4 dVout dt Off V ms 600 550
18. 500 veny 450 cH 400 350 300 250 1 50 25 0 25 50 75 100 125 150 175 Doc ID 14617 Rev 4 Electrical specifications VND5E050AJ E VND5E050AK E Figure 29 CS DIS high level voltage Figure 30 CS DIS clamp voltage Vesdh V Vesdcl V 4 10 3 5 9 8 1 mA 3 2 5 6 2 5 15 4 3 1 2 0 5 0 0 50 25 0 25 50 75 100 125 150 175 50 25 0 25 50 75 100 125 150 175 Figure 31 CS DIS low level voltage Vcsdl V 3 2 5 0 5 24 44 Doc ID 14617 Rev 4 VND5E050AJ E VND5E050AK E Application information 3 Note 3 1 3 1 1 Application information Figure 32 Application schematic 45V MCU Channel 2 has the same internal circuit as channel 1 GND protection network against reverse battery This section provides two solutions for implementing a ground protection network against reverse battery Solution 1 resistor in the ground line only This can be used with any type of load The following is an indication on how to dimension the
19. D5E050AK E 5 4 40 44 PowerSSO 12 packing information Figure 45 PowerSSO 12 tube shipment no suffix 2 5mm min width TAPE DIMENSIONS According to Electronic Industries Association EIA Standard 481 rev A Feb 1986 q ty 100 Bulk q ty 2000 Tube length x 0 5 532 i A 1 85 A B 6 75 C x 0 1 0 6 All dimensions are in mm Figure 46 PowerSSO 12 tape and reel shipment suffix TR d 40mm min e REEL DIMENSIONS x at slot location Base q ty 2500 Bulk q ty 2500 A max 330 B min 1 5 N o r C x 0 2 13 F 20 2 un G 2 0 124 m N min 60 Tees T max 18 4 in core for tape start Tape width 12 Tape hole spacing 04 4 EUM Component spacing P 8 TAPE Hole diameter D x 0 05 1 5 Hole diameter D1 min 1 5 7 Hole position F x 0 1 5 5 Compartment depth K max 45 Hole spacing P1 0 1 2 K All dimensions in mm User Direction of Feed End Y 9 d ra c Borrar Pod CE SUEDE ter i O000000 Start Top No components Components No components cover s ole 500 e Empty components pockets 500mm min S saled with cover tape User direction of feed Doc ID 14617 Rev 4
20. NSEH A On 34 Pwr Li CS DIS 4 LA VsENsEH 2 Ld CURRENT 22 GND Load Renor Rep To uC ADC Rsense VsENSE Short to Vcc and off state open load detection Short to Vec A short circuit between Vcc and output is indicated by the relevant current sense pin set to VseNnsEH during the device off state Small or no current is delivered by the current sense during the on state depending on the nature of the short circuit Off state open load with external circuitry Detection of an open load in off mode requires an external pull up resistor Rpy connecting the output to a positive supply voltage Vpy Doc ID 14617 Rev 4 27 44 Application information VND5E050AJ E VND5E050AK E 28 44 It is preferable Vpy to be switched off during the module stand by mode in order to avoid the overall stand by current consumption to increase in normal conditions i e when load is connected An external pull down resistor Rpp connected between output and GND is mandatory to avoid misdetection in case of floating outputs in off state see Figure 33 Current sense and diagnostic Rpp must be selected in order to ensure Vout lt unless pulled up by the external circuitry Pull up OFF Ren Diog Vormi 2V 22 is recommended For proper open load detection in off state the external pull up resistor must be selected
21. V 1 pulse 400ms 20 1 The above test levels must be considered referred to Voc 13 5V except for pulse 5b 2 Valid in case of external load dump clamp 40V maximum referred to ground Table 13 Electrical transient requirements part 2 ISO 7637 2 Test level results 2004E test pulse 1 3b C C 4 C C 5b 1 Valid in case of external load dump clamp 40V maximum referred to ground Table 14 Electrical transient requirements part 3 Class Contents C All functions of the device performed as designed after exposure to disturbance One or more functions of the device did not perform as designed after exposure to E disturbance and cannot be returned to proper operation without replacing the device 18 44 Doc ID 14617 Rev 4 VND5E050AJ E VND5E050AK E Electrical specifications 24 Waveforms Figure 11 Normal operation Normal operation INPUT lour VseENsE Vcs pis Figure 12 Overload or short to GND Overload or Short to GND INPUT Power Limitation Thermal cycling lour VseENsE Vcs pis SU Doc ID 14617 Rev 4 19 44 VND5E050AJ E VND5E050AK E Electrical specifications Intermittent overload Figure 13 Intermittent Overload INPUT VseENsE Figure 14 Off state open load with external circuitry OFF State Open Load wi
22. e not triggered Doc ID 14617 Rev 4 34 44 VND5E050AJ E VND5E050AK E Package and PCB thermal data Table 16 Thermal parameters Area island cm Footprint 2 8 R12 R7 C W 0 4 R2 R8 C W 2 R3 C W 6 R4 C W 7 7 R5 C W 9 9 8 R6 C W 28 17 10 1 C7 W s C 0 001 C2 C8 W s C 0 0022 C3 W s C 0 025 C4 W s C 0 75 C5 W s C 1 4 9 W s C 2 2 5 17 Doc ID 14617 Rev 4 35 44 Package and packing information VND5E050AJ E VND5E050AK E 5 5 1 5 2 36 44 Package and packing information order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACKO is an ST trademark PowerSSO 12 package information Figure 43 PowerSSO 12 package dimensions Doc ID 14617 Rev 4 VND5E050AJ E VND5E050AK E Package and packing information Table 17 PowerSSO 12 mechanical data Millimeters Symbol Min Typ Max A 1 25 1 62 A1 0 0 1 A2 1 10 1 65 B 0 23 0 41 C 0 19 0 25 D 4 8 5 0 E 3 8 4 0 e 0 8 H 5 8 6 2 h 0 25 0 5 L 0 4 1 27 k 0 8 X 1 9 2 5 Y 3 6 4 2 ddd 0 1 Doc ID 14617 Rev 4 37 44 Packa
23. esence of the ground network will produce a shift 600mV in the input threshold and in the status output values if the microprocessor ground is not common to the device ground This shift will not vary if more than one HSD shares the same diode resistor network Load dump protection Dig is necessary voltage transient suppressor if the load dump peak voltage exceeds the Vcc max DC rating The same applies if the device is subject to transients on the Vcc line that are greater than the ones shown in the ISO 7637 2 2004 E table MCU I Os protection If a ground protection network is used and negative transient are present on the line the control pins will be pulled negative ST suggests to insert a resistor Rprot in line to prevent the uC I Os pins to latch up The value of these resistors is a compromise between the leakage current of uC and the current required by the HSD I Os Input levels compatibility with the latch up limit of uC I Os VoCpeak llatchup lt Rprot lt liHmax Calculation example For 100V and liatchup 2 20MA 2 4 5V lt Rprot 180kO Recommended values 2 10kO Cext 1 OnF Current sense and diagnostic The current sense pin performs a double function see Figure 33 Current sense and diagnostic Current mirror of the load current in normal operation delivering a current proportional to the load one according to a kn
24. from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2009 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 44 44 Doc ID 14617 Rev 4 ky
25. ge and packing information VND5E050AJ E VND5E050AK E 5 3 38 44 PowerSSO 24 package information Figure 44 PowerSSO 24 package dimensions m t f S i LA tA f ot Pe N Ju m E MI SN le G c LEAD ICOPLANARITY ERE Y N 5 5 5 Lx m v I 2 Body Length i 8 2 7 NA E BOTTOM VIEW EH Doc ID 14617 Rev 4 ky VND5E050AJ E VND5E050AK E Package and packing information Table 18 PowerSSO 24 mechanical data 2 Millimeters Symbol Min Typ Max A 2 45 A2 2 15 2 35 a1 0 0 1 b 0 33 0 51 0 23 0 32 p 10 10 10 50 E 9 7 40 7 60 e 0 8 e3 8 8 F 2 3 G 0 1 H 10 1 10 5 h 0 4 k 0 8 L 0 55 0 85 1 2 0 8 5 2 9 3 65 U 1 0 N 10 X 4 1 4 7 Y 6 5 7 1 1 No intrusion allowed inwards the leads 2 Flash or bleeds on exposed die pad shall not exceed 0 5 mm per side 3 and E do not include mold Flash or protusions Mold Flash or protusions shall not exceed 0 15 mm per side 4 Doc ID 14617 Rev 4 39 44 Package and packing information VND5E050AJ E VN
26. ic 1 Power Clamp IN1 DRIVER E to IN2 Von CH1 O Limitation 5 pum re e 52 5 Open 10a 05 cH2 CS c DIS VseNseH 6 cst Current Sense OUT2 CS2 OUT1 OVERLOAD PROTECTION LOGIC 4 ACTIVE POWER LIMITATION m L GND Table 1 Pin function Name Function Voc Battery connection OUTPUT 5 Power output GND Ground connection Must be reverse battery protected by an external diode resistor network Voltage controlled input pin with hysteresis CMOS compatible Controls output INPUT 2 switch state RRENT cu Analog current sense pin delivers a current proportional to the load current SENSE 2 CS_DIS Active high CMOS compatible pin to disable the current sense pin Doc ID 14617 Rev 4 VND5E050AJ E VND5E050AK E Block diagram and pin description 4 Figure 2 Configuration diagram top view TAB Vec OUTPUT GND OUTPUT2 GND 17 112 Veo N C i OUTPUT2 INPUT2 2 11 QUTPUT2 INTE INPUT1 3 H0 QUTPUT2 INPUT OUTPUT2 CURRENT SENSE1 4 19 OUTPUT N C OUTPUT1 CURRENT SENSE2 5 18 5 OUTPUT CS DIS 8 777 Tj Vee CURRENT SENSE2 I OUTPUT1 CS DIS l l OUTPUT1 Vcc L OUTPUT1 TAB PowerSSO 12 PowerSSO 24 Table 2 Suggested connections for unused and not connected pins Connection pin Current sense N C Output Input CS DIS Floating Not allowed X X
27. l Parameter Test conditions Min Typ Max Unit Delay response time between rising VsENsE lt 4V At edge of output Isense 90 of Isensemax 40 DSENSE2H current and rising lour 90 of Ioytmax H edge of current loutmax 2A see Figure 7 sense Delay response Vsense lt 4V 0 5A lt lout lt 4A tpsENsEar time from falling Isense 10 of ISENSEMAX 80 250 us edge of INPUT pin see Figure 4 1 Parameter guaranteed by design it is not tested 2 Fault condition includes power limitation over temperature and open load off state detection Table 10 Open load detection 8V Vcc 18V Symbol Parameter Test conditions Min Typ Max Unit Open load off state See VoL voltage detection Vi 20V 2 Fiqure 5 4 V threshold Output short circuit to tpsrkoN Vcc detection delay at See Figure 5 180 1200 us turn off Off state output current Vin OV Vsense 0V 420 0 uA at Vour 4V Vour rising from OV to 4V Off state output current Vin OV Vsense VSENSEH 50 90 UA Loff at Vout 2V Vout falling from to 2V Delay response from isi Vout 4 V OV td_vol output rising edge to OUT IN 20 us VsENSE rising edge In VsENSE 90 of VsSENSEH open load Figure 4 Current sense delay characteristics INPUT pe cc CS DIS LOAD CURRENT SENSE CURRENT T tbSENSE2H lt gt DSENSE1L tpsENSE1H g
28. lectrical transient requirements part 3 18 Thermal 5 32 Thermal 5 35 PowerSSO 12 mechanical data 37 PowerSSO 24 mechanical data 39 Device SUMMAN REG E 42 Document revision history 43 Doc ID 14617 Rev 4 3 44 List of figures VND5E050AJ E VND5E050AK E List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 4 44 Block diagram deter deh wee ede the 6 Configuration diagram top view 7 Current and voltage conventions 8 Current sense delay
29. n Applications m Alltypes of resistive inductive and capacitive loads m Suitable as LED driver Description The VND5E050AJ E and VND5E050AK E are double channel high side drivers manufactured in the ST proprietary VIPower MO 5 technology and housed in the tiny PowerSSO 12 and PowerSSO 24 packages The VND5E050AJ E and VND5E050AK E are designed to drive 12V automotive grounded loads delivering protection diagnostics and easy 3V and 5V CMOS compatible interface with any microcontroller The devices integrate advanced protective functions such as load current limitation inrush and overload active management by power limitation over temperature shut off with auto restart and over voltage active clamp A dedicated analog current sense pin is associated with every output channel in order to provide Enhanced diagnostic functions including fast detection of overload and short circuit to ground through power limitation indication over temperature indication short circuit to Vcc diagnosis and on amp off state open load detection The current sensing and diagnostic feedback of the whole device can be disabled by pulling the CS DIS pin high to allow sharing of the external sense resistor with other similar devices Doc ID 14617 Rev 4 1 44 www st com Contents VND5E050AJ E VND5E050AK E Contents 1 Block diagram and pin description 6 2 Electrical specifications
30. nt Internally limited A lour Reverse DC output current 20 A lin DC input current 1 to 10 mA DC current sense disable input current 1to 10 mA 1 DC reverse CS pin current 200 mA Current sense maximum voltage bw i V Doc ID 14617 Rev 4 VND5E050AJ E VND5E050AK E Electrical specifications 2 2 2 3 4 Table 3 Absolute maximum ratings continued Symbol Parameter Value Unit Maximum switching energy single pulse Emax 104 L 00 Vpat 13 5V Tistart 150 C lout liim Electrostatic discharge human body model R 1 5KQ C 100pF Input 4000 Current sense 2000 V CS DIS 4000 V Output 5000 V Vcc 5000 V VEsp Charge device model CDM AEC Q100 01 1 750 V Ti Junction operating temperature 40 to 150 C Storage temperature 55 to 150 C Thermal data Table 4 Thermal data Max value Symbol Parameter Unit PowerSSO 12 PowerSSO 24 Thermal resistance junction case Rihi 2 7 2 7 C W thi case with one channel ON Rthj amb Thermal resistance junction ambient See Figure 36 See Figure 40 C W Electrical characteristics Values specified in this section are for 8 V Vcc 28 V 40 C T 150 C unless otherwise stated Table 5 Power section Symbol Parameter Test conditions Min Typ
31. of Feed User direction of feed ky Doc ID 14617 Rev 4 41 44 Order codes VND5E050AJ E VND5E050AK E 6 42 44 Order codes Table 19 Device summary Order codes Package Tube Tape and reel PowerSSO 12 VND5E050AJ E VND5EO050AJTR E PowerSSO 24 VND5E050AK E VND5E050AKTR E Doc ID 14617 Rev 4 ky VND5E050AJ E VND5E050AK E Revision history 7 Revision history Table 20 Document revision history Date Revision Changes 01 Apr 2008 1 Initial release 05 Mar 2009 2 Changed Table 18 PowerSSO 24 mechanical data Table 18 PowerSSO 24 mechanical data 19 Jun 2009 3 Changed L min value from 0 6 to 0 55 Changed L max value from 1 to 0 85 22 Jul 2009 4 Updated Figure 44 PowerSSO 24 package dimensions Doc ID 14617 Rev 4 43 44 VND5E050AJ E VND5E050AK E Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of
32. our A s 1 Parameter guaranteed by design it is not tested Doc ID 14617 Rev 4 ky VND5E050AJ E VND5E050AK E Electrical specifications 4 Table 11 Truth table Conditions Input Output Sense 0 Normal operation T 0 H Nominal Overtemperature Q H L VSENSEH L L 0 It Undervoltage 4 L 0 X Nominal no power limitation Overload H Cycling VsSENSEH power limitation Short circuit to GND L L 0 power limitation H L VSENSEH Open load off state L T T with external pull up Short circuit to V external pull up VSENSEH Nominal disconnected Negative output voltage L L 0 clamp 1 If the is high the SENSE output is at a high impedance its potential depends on leakage currents and external circuit Doc ID 14617 Rev 4 17 44 Electrical specifications VND5E050AJ E VND5E050AK E Table 12 Electrical transient requirements part 1 ISO 7637 2 Test levels Number of Burst cycle pulse repetition time Delays and 2004 E pulses or test pulse test times Impedance IV Min Max 1 75V 100V 5000 pulses 0 5s 5s 2 ms 100 2a 37V 50V 5000 pulses 0 2s 5s 50us 2Q 3a 100V 150V th 90ms 100ms 0 1us 50Q 3b 75V 100V th 90ms 100ms 0 1us 50Q 4 6V 7V 1 pulse 100ms 0 019 5b 65V 87
33. ow ratio Kx The current Isense can be easily converted to a voltage Vsenge by means of an external resistor Rgens_e Linearity between lour and Vsense is ensured up to 5V minimum see parameter in Table 9 Current sense 8V Vcoc 18V The Doc ID 14617 Rev 4 ky VND5E050AJ E VND5E050AK E Application information 3 4 1 current sense accuracy depends on the output current refer to current sense electrical characteristics Table 9 Current sense 18 e Diagnostic flag in fault conditions delivering a fixed voltage Vsensey up to a maximum current Isensex in case of the following fault conditions refer to Power limitation activation Over temperature Short to Vec in off state Open load in off state with additional external components A logic level high on CS DIS pin sets at the same time all the current sense pins of the device in a high impedance state thus disabling the current monitoring and diagnostic detection This feature allows multiplexing of the microcontroller analog inputs by sharing of sense resistance and ADC line among different devices Figure 33 Current sense and diagnostic Vi M Dx LA Main MOSn G a PU_CMD Overtemperature lout Kx R PU lt NS oao IsE
34. t tDSENSE2L Doc ID 14617 Rev 4 13 44 Electrical specifications VND5E050AJ E VND5E050AK E 14 44 Figure 5 Open load off state delay timing OUTPUT STUCK Vec Vout gt VoL VSENSEH js Vcs itosTKON q Figure 6 Switching characteristics Vour i twon 80 dVour dtoft 10 INPUT A ta on t Doc ID 14617 Rev 4 VND5E050AJ E VND5E050AK E Electrical specifications Figure 7 edge of current sense CS enabled Delay response time between rising edge of output current and rising ViN AtpSENSE2H 90 lourMAx Figure 8 Output voltage drop limitation 150 lout Von Ron T Doc ID 14617 Rev 4 15 44 Electrical specifications VND5E050AJ E VND5E050AK E Note 16 44 Figure 9 lour lsgNsE vs lout lout Isense 3000 2800 max Tj 40 C to 150 C 2600 2400 max Tj 25 to 150 C 2200 2000 ee neeaaea typical 1800 min Tj 40 C to 150 C 1600 1400 1200 4 1 5 2 2 5 3 3 5 4 lout A Figure 10 Maximum current sense ratio drift vs load current dk k Mo 15 1 2 l
35. th external circuitry INPUT Vour VsENsE Doc ID 14617 Rev 4 20 44 Electrical specifications VND5E050AJ E VND5E050AK E Figure 15 Shortto Vcc 5 ge Itb Ec m o gt 9 8 gt gt ot re VoL lour Figure 16 T evolution in overload or short to GND Ty evolution in Power Limitation INPUT lour 21 44 Doc ID 14617 Rev 4 Electrical specifications VND5E050AJ E VND5E050AK E 2 5 Electrical characteristics curves Figure 17 Off state output current Figure 18 High level input current lloff nA lih uA 550 5 500 45 450 _ Off State Vin 2 1V Vec 13V 4 00 Vin Vout 0V 5 350 3 300 2 5 250 200 150 15 100 1 50 0 5 0 J 0 50 25 0 25 50 75 100 125 150 175 50 25 0 25 50 75 100 125 150 175 Tc Tc Figure 19 Input clamp voltage Figure 20 Input low level Vicl V Vil V F 2 6 8 1 8 lin 1mA 6 6 1 6 6 4 1 4 6 2 1 2 6 1 5 8 0 8 5 6 0 6 5 4 0 4 5 2 0 2 5 0 50 25 0 25 50 75 100
36. um front and back side Copper areas from minimum pad lay out to 8cm Figure 36 Rthj amb VS PCB copper area in open box free air condition one channel ON RTHj_amb C W 70 65 60 55 50 45 40 35 30 PCB Cu heatsink area cm 2 Doc ID 14617 Rev 4 VND5E050AJ E VND5E050AK E Package and PCB thermal data Figure 37 PowerSSO 12 thermal impedance junction ambient single pulse one channel ON ZTH C W 100 Pa Footprint 2 2 8 10 1 0 1 m 0 0001 0 001 0 01 0 1 1 10 100 1000 5 Equation 1 pulse calculation formula 2 1 where 6 t T Figure 38 Thermal fitting model of a double channel HSD in PowerSSO 12 a a The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections power limitation or thermal cycling during thermal shutdown are not triggered Doc ID 14617 Rev 4 31 44 Package and PCB thermal data VND5E050AJ E VND5E050AK E 4 2 Note 32 44 Table 15 Thermal parameters Area island cm Footprint 2 8 R1 R7 C W 0 7 R2 R8 C W 28 R3 C W 4 R4 C W 8 8 7 R5 C W 22 15 10 R6

ST VND5E050AJ-E/VND5E050AK-E handbook

Contents

Download Pdf Manuals

Related Search

Related Contents