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ST VND5E050J-E VND5E050K-E handbook

1. 21 STAT DIS clamp 21 High level STAT DIS 21 Low level STAT DIS voltage 1 21 Application 0 22 Open load detection in 24 Maximum turn off current versus inductance for each channel 25 PowerSSO 12 PC 40 1 26 Rthj amb Vs PCB copper area in open box free air condition one channel on 26 PowerSSO 12 thermal impedance junction ambient single pulse one channel on 27 Thermal fitting model of a double channel HSD in PowerSSO 12 27 PowerSSO 24 PC 29 Rthj amb Vs PCB copper area in open box free air condition one channel on 29 PowerSSO 24 thermal impedance junction ambient single pulse one channel on 30 Thermal fitting model of a double channel HSD 550 24 30 PowerSSO 12 package lt 32 PowerSSO 24 package lt 34 PowerSSO 12 tube shipment no suffix
2. End Y 9 d zu i in reu qr m MESS J y 2 components Components No components cover be ele tape 500mm min e Empty components pockets 500mm min UN saled with cover tape a User Direction of Feed User direction of feed 36 40 Doc ID 14472 Rev 3 Ky VND5E050K E Package and packing information 5 5 PowerSSO 24 packing information Figure 47 PowerSS0 24 tube shipment no suffix Base Qty 49 Bulk Qty 1225 Tube length 0 5 532 A 3 5 B 13 8 C 0 1 0 6 dimensions are in mm Figure 48 REEL DIMENSIONS at slot location Base Qty 1000 Bulk Qty 1000 330 pe B min 1 5 C 0 2 13 F 20 2 4 2 0 24 4 Tape sat ve N min 100 his T max 30 4 2 5mm min width 4 I TAPE DIMENSIONS According to Electronic Industries Association EIA Standard 481 rev A Feb 1986 Tape width 24 Hole Spacing PO 0 1 4 Component Spacing P 12 Hole Diameter 0 05 1 55 Hole Diameter D1 min 1 5 Hole Position 0 1 11 5 iss Un Feed Compartment Depth K max 2 85 2 Hole Spacing P1 0 1 2 End 4
3. 36 PowerSSO 12 tape and reel shipment suffix 36 PowerSS0 24 tube shipment no 37 PowerSSO 24 tape and reel shipment suffix 37 Doc ID 14472 Rev 3 437 VND5E050K E Block diagram and pin description 4 Block diagram and description Figure 1 Block diagram Vee Signal Clamp t 9 E Undervoltage Control amp Diagnostic 1 Power Clamp E IN1 DRIVER e E 0 IN2 Von CH1 Limitation 5 o om Lm 2 5 5 5 5 Open 86 ST_ DIS pus 2 OUT2 Q 571 ST2 2 OUT1 L la OVERLOAD PROTECTION LOGIC ACTIVE POWER LIMITATION EJ GND Table 1 Pin function Name Function Vcc Battery connection OUTPUTn Power output GND Ground connection Must be reverse battery protected by an external diode resistor network Voltage controlled input pin with hysteresis CMOS compatible Controls output INPUTn switch state STATUSn Open drain digital diagnostic pin STAT DIS Activ
4. 33 PowerSSO 24 mechanical data 35 Document revision history 39 Doc ID 14472 Rev 3 3 40 List of figures VND5E050K E List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 4 40 Block diagram 5 Configuration diagram view 6 Current and voltage conventions 7 Status TIMINGS exorta wae xm ola a nee ete 12 Output voltage drop 12 Switching characteristics 13 Normal operation 1 15 Undervoltage shutdown 15 Overload or Short to GND
5. Status delay in overload tsp conditions Ti see Figure 4 20 us VDEMAG 2 output voltage 2 Vin 0 L 6mH 41 46 52 V lour 0 1 A Vou top T 40 150 25 limitation see Figure 5 1 To ensure long term reliability under heavy overload or short circuit conditions protection and related diagnostic signals must be used together with a proper software strategy If the device is subjected to abnormal conditions this software must limit the duration and number of activation cycles Table 9 Openload detection 8V Vcc 18V Symbol Parameter Test conditions Min Typ Max Unit Openload on state ENN loL detection threshold Vn 5V 5 Openload on state lout 0 Vec 13V MT DOL on detection delay see Figure 4 Doc ID 14472 Rev 3 3 VND5E050K E Electrical specifications Table 9 Openload detection 8 lt lt 18 continued Symbol Parameter Test conditions Min Typ Max Unit Delay between input falling edge and status _ 5 rising edge in open load lout see Figure 4 200 500 1200 us condition Openload off state VoL voltage detection Vin OV 2 4 V threshold Output short circuit to ipsrkoN Vcc detection delay at See Figure 4 180 HS turn off Vin 4V Off state output n OUT IL oft2 currenti see Section 3 4 Open load
6. C Star cover User Direction of Feed No components Components No components 500mm min Empty components pockets S sealed with cover tape sgt User direction of feed Doc ID 14472 Rev 3 37 40 Order codes VND5E050K E 6 38 40 Order codes Table 19 Device summary Package PowerSSO 12 Order codes Tube VND5E050J E Tape and reel VND5EO050JTR E PowerSSO 24 VND5EO50K E VND5EOSOKTR E Doc ID 14472 Rev 3 VND5E050K E Revision history 7 Revision history Table 20 Document revision history Date 04 Feb 2008 Revision 1 Changes Initial release 19 Jun 2009 Table 18 PowerSSO 24 mechanical data Deleted A min value Changed A max value from 2 47 to 2 45 Changed A2 max value from 2 40 to 2 35 Changed a1 max value from 0 075 to 0 1 Added F row Updated k row 22 Jul 2009 Updated Figure 44 PowerSSO 24 package dimensions Updated Table 18 PowerSSO 24 mechanical data Deleted G1 row Added O Q S T and U rows Doc ID 14472 Rev 3 39 40 VND5E050K E Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to thi
7. Values are generated with 0 Q In case of repetitive pulses at beginning of each demagnetization of every pulse must not exceed the temperature specified above for curves A and B Doc ID 14472 Rev 3 25 40 Package and PCB thermal data VND5E050K E 4 Package and PCB thermal data 4 1 PowerSSO 12 thermal data Figure 35 PowerSSO 12 PC board PSSO12L 7 PSSOL2L PSSO12L We 2cm 2 the 8cm 2 Note Layout condition of Ri and measurements PCB Double layer Thermal Vias FR4 area 77mm 86mm PCB thickness 1 6mm Cu thickness 70um front and back side Copper areas from minimum pad lay out to 8 Figure 36 Rthj amb VS PCB copper area in open box free air condition one channel on RTHj_amb C W 70 65 60 55 50 45 40 35 30 heatsink area 2 26 40 Doc ID 14472 Rev 3 ky VND5E050K E Package and PCB thermal data Figure 37 PowerSSO 12 thermal impedance junction ambient single pulse one channel on ZTH C W 100 Footprint a 2 8 cm 10 0 1 0 0001 0 001 0 01 0 1 1 10 100 1000 5 Equation 1 pulse calculation formula 2 5 2 79 where 6 tp
8. 2 16 Intermittent Overload 16 Open load with external pull up 17 Open load without external 17 Short t Veg sspe bep 18 T evolution in overload or short to 18 Off state output 19 High level input 01 19 Input clamp 1 19 Iriput high leVel RR om E eat 19 Input low level uem emnes EE p Rm ee ee 19 Low level STAT_DIS current 19 On state resistance VS 20 High level STAT DIS 20 On state resistance VS 20 Low level input 4 20 ILIM VS Tease UE ctu ni cat par tyes akan Saas 20 Turn On voltage slope 20 Undervoltage shutdown 21 Turn Off voltage slope
9. 57 VND5E050J E VNDSE050K E Double channel high side driver for automotive applications Features Max supply voltage Voc 41 Operating voltage range Voc 4 5 to 28V Max On State resistance per ch Ron 50 mQ Current limitation typ ILIMH 27A Off state supply current Is 2 1 Typical value with all loads connected m General Inrush current active management by power limitation Very low standby current 3 0V CMOS compatible inputs Optimized electromagnetic emissions Very low electromagnetic susceptibility In compliance with the 2002 95 EC european directive Diagnostic functions Open Drain status output On state open load detection Off state open load detection Output short to Vcc detection Overload and short to ground power limitation indication Thermal shutdown indication m Protections July 2009 Undervoltage shutdown Overvoltage clamp Load current limitation Self limiting of fast thermal transients Protection against loss of ground and loss of Voc Over temperature shutdown with auto restart thermal shutdown Reverse battery protected see Figure 32 Electrostatic discharge protection PowerSSO 12 PowerSSO 24 Applications m Alltypes of resistive inductive and capacitive loads Description The VND5E050J E and VND5E050K E are double channel high side drivers manufactured in the ST proprietary MO 5
10. o gt 2 c LLL ND oN 5 3 o 2 B 5 D LL Doc ID 14472 Rev 3 Electrical specifications 18 40 VND5E050K E Electrical specifications 2 5 Electrical characteristics curves Figure 15 Off state output current Figure 16 High level input current lloff nA 700 600 500 400 Off State Vec 13V X Vin Vout 0V 300 200 100 lih uA Vin 2 1V 50 25 0 25 50 75 100 125 150 175 C Figure 17 Input clamp voltage Figure 18 Input high level lin 1mA 25 25 50 75 100 125 150 175 C Vih V 4 3 5 3 2 5 50 25 0 25 50 75 100 125 150 175 C Figure 19 Input low level Figure 20 Low level STAT_DIS current 25 25 50 75 100 125 150 175 Isdl uA Vsd 0 9V 50 25 0 25 50 75 100 125 150 175 4 Doc ID 14472 Rev 3 19 40 Electrical specifications VND5E050K E Figure 21 On state resistance vs Figure 22 High level STAT DIS current Ron mOhm 300 250 lout 2A Vec
11. 3b 75 100V th 90 ms 100 ms 0 1 us 50 Q 4 6V 7V 1 pulse 100 ms 0 01 Q 5b 65V 87V 1 pulse 400 ms 2Q 1 Valid in case of external load dump clamp 40V maximum referred to ground Table 13 Electrical transient requirements part 2 3 ISO 7637 2 2004 E test pulse 1 2a Test level results 3a 3b 4 5 2 1 above test levels must be considered referred to Vcc 13 5V except pulse 56 2 Valid in case of external load dump clamp 40V maximum referred to ground Table 14 Electrical transient requirements part 3 3 Class Contents All functions of the device are performed as designed after exposure to disturbance One or more functions of the device not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device 3 Doc ID 14472 Rev 3 VND5E050K E Electrical specifications 2 4 Waveforms Figure 7 Normal operation Normal operation VsrATUS Vsr pis 5 Figure 8 Undervoltage shutdown Undervoltage shut down Vstatus Vsr pis Doc ID 14472 Rev 3 15 40 Electrical specifications VND5E050K E 16 40 Figure 9 Overload or Short to GND Overload or Short to GND INPUT Thermal cyc
12. 75 0 detection in off state Delay response from output rising edge to A td_vol status falling edge in Vin OV Vour 4V ee CHS open load 1 For each channel Table 10 Logic input Symbol Parameter Test conditions Min Typ Max Unit Input low level 0 9 V li Low level input current Vin 20 9 V 1 Vin Input high level 2 1 V High level input current Vin 2 1 V 10 Input hysteresis voltage 0 25 V Vic Input clamp voltage 5 5 lin 1mA 0 7 V STAT_DIS low level voltage 0 9 V IspL Low level STAT DIS current Vsp 0 9 V 1 STAT_DIS high level voltage 2 1 V ISDH High level STAT_DIS current Vsp 2 1 V 10 Vsp hys STAT DIS hysteresis voltage 0 25 V STAT_DIS clamp voltage 1 95 f M Doc ID 14472 Rev 3 11 40 Electrical specifications VND5E050K E 12 40 Figure 4 Status timings Vin OPEN LOAD STATUS TIMING without external pull up lout lt lon Vin Vout lt OUTPUT STUCK lout gt lot Vout gt OPEN LOAD STATUS TIMING with external pull up lout lt lon __ DoL on _ P OVER TEMP STATUS TIMING Tj gt Vout gt VsrAT foL on ItpsrkoN tsp Figure 5 Output voltage dro
13. to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark PowerSSO 12 package information Figure 43 PowerSSO 12 package dimensions Doc ID 14472 Rev 3 437 VND5E050K E Package and packing information 4 Table 17 PowerSSO 12 mechanical data Millimeters Symbol Min Typ Max A 1 25 1 62 Al 0 0 1 A2 1 10 1 65 B 0 23 0 41 C 0 19 0 25 D 4 8 5 0 E 3 8 4 0 e 0 8 H 5 8 6 2 h 0 25 0 5 L 0 4 1 27 k 0 8 X 1 9 2 5 Y 3 6 4 2 ddd 0 1 Doc ID 14472 Rev 3 33 40 Package and packing information VND5E050K E 5 3 34 40 PowerSSO 24 package information Figure 44 PowerSSO 24 package dimensions S 18 1 9 4 T UUUUCULUUUUI BOTTOM VIEW Doc ID 14472 Rev 3 VND5E050K E Package and packing information 3 Table 18 PowerSSO 24 mechanical data Millim
14. 100 125 150 175 Figure 29 STAT_DIS clamp voltage Figure 30 High level STAT_DIS voltage 15 1 50 25 0 25 50 75 100 125 150 175 VsdH V 4 3 5 3 2 5 50 25 25 50 75 100 125 150 175 Figure 31 Low level STAT_DIS voltage VsdL V 3 2 5 0 5 50 25 25 50 75 100 125 150 175 4 Doc ID 14472 Rev 3 21 40 Application information VND5E050K E 3 Note 22 40 Application information Figure 32 Application schematic 5V 5V Rprot STAT_DIS r 1 LZ 1 A Dig INPUT T yen C gt i82 OUTPUT STATUS AD GND Reno f Channel 2 has the same internal circuit as channel 1 GND protection network against reverse battery Solution 1 resistor in the ground line Rgnp only This can be used with any type of load The following is an indication on how to dimension the Renp resistor 1 Renp lt 600 15 2 Rawp2 C Voo lenp where is th
15. 13V 200 150 100 50 Isdh Vsd 2 1V 50 25 0 25 50 75 100 125 150 175 Te C Figure 23 On state resistance vs Figure 24 Low level input current Ron mOhm 100 150 80 125 60 25 40 Tc 40 C 20 0 0 5 10 15 20 25 30 35 40 C lil uA Vin 0 9V 50 25 0 25 50 75 100 125 150 175 Te C Figure 25 VS Tease Figure 26 Turn On voltage slope dVout dt On V ms 40 1000 900 99 13 TA Vecmd3V 6 5 Ohm 700 30 600 25 500 1 400 20 300 200 15 100 10 0 50 25 0 25 50 75 100 125 150 50 25 0 25 50 75 100 125 150 175 C Tc C 20 40 Doc ID 14472 Rev 3 ky VND5E050K E Electrical specifications Figure 27 Undervoltage shutdown Figure 28 Turn Off voltage slope Vusd V 8 7 6 50 25 0 25 50 75 100 125 150 175 Te C dVout dt Off V ms 600 550 500 Vec 13V 450 400 350 300 250 200 50 25 0 25 50 75
16. AFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2009 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 40 40 Doc ID 14472 Rev 3 437
17. T Figure 38 Thermal fitting model of a double channel HSD in PowerSSO 12 a i C5 R1 2 R3 R4 R5 T PdCh2 ce e m T m T fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections power limitation or thermal cycling during thermal shutdown are not triggered ky Doc ID 14472 Rev 3 27 40 Package and PCB thermal data VND5E050K E 28 40 Table 15 PowerSSO 12 thermal parameters Area island cm Footprint 2 8 1 R7 C W 0 7 R2 R8 C W 2 8 R3 C W 4 R4 C W 8 8 7 85 C W 22 15 10 R6 C W 26 20 15 C1 C7 Ws C 0 001 C2 C8 W s C 0 0025 C3 W s C 0 05 C4 W s C 0 2 0 1 0 1 C5 W s C 0 27 0 8 1 W s C 3 6 9 Doc ID 14472 Rev 3 VND5E050K E Package and PCB thermal data 4 2 PowerSSO 24 thermal data Figure 39 PowerSSO 24 PC board PSS024L S PSS024L PSS024L 2 2 Note Layout condition of Hy and measurements PCB Double layer Thermal Vias FR4 area 77mm x 86mm PCB thickness 1 6mm Cu thickness 70um front and back side Copper areas from minimum pad lay out to 8 Figure 40 Rthj amb Vs PCB copper area in open bo
18. Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 20 PIN FUNGON 2522 degen ea ar Ge ae ede ae ae hee ee 5 Suggested connections for unused and not connected pins 6 Absolute maximum 05 7 Sate Breer 8 Power Section ies d kee bea dae eae Peed dae Re 9 Switching VCC 13V Tj 25 C tee 9 Status pin Vep OV ke Rn ec eRe 10 ize a ached ee aie ae Ree 10 Openload detection 8 lt lt 18 2 10 LOGIC InpUt eo 11 Truth tablen 13 Electrical transient requirements part 1 3 14 Electrical transient requirements part 2 3 14 Electrical transient requirements part 3 3 14 PowerSSO 12 thermal 28 PowerSSO 24 thermal lt 31 PowerSSO 12 mechanical
19. Unit ta on Turn On delay time 6 50 see Figure 6 20 Hs Turn Off delay time 6 50 see Figure 6 40 us dVoyt at Turn On voltage slope R 6 50 E V us OUT 26 dVou dt Turn Off voltage slope 6 50 See V us Ol off 17 gt 28 Switching energy _ WoN losses during tyon 6 50 see Figure 6 0 21 mJ Switching energy Worr losses during 5 4 6 50 see Figure 6 0 28 mJ Doc ID 14472 Rev 3 9 40 Electrical specifications VND5E050K E 10 40 Table 7 Status pin Vsp 0V Symbol Parameter Test conditions Min Typ Max Unit Status low output _ voltage 1 6 mA 0 0 5 V Status leakage current Montiel Operation St 10 pA Vstat 5V Status pin input Normal Operation or Vsp 5V Csrar capacitance 5V 1097 pE ISTAT 1 5 5 7 V V Status clamp voltage SCL g ISTAT 1mA 0 7 V Table 8 Protections 1 Symbol Parameter Test conditions Min Typ Max Unit 19 27 38 A DC short circuit current 13 5 lt lt 28 38 A Short circuit current Voc 13V limL during thermal cycling Ta lt T lt T 7 R lt j lt TSD Trsp Shutdown temperature 150 175 200 Reset temperature Trs 1 45 Thermal reset of TRS _ STATUS 139 2 Thermal hysteresis 7 HYST
20. alue Symbol Parameter Unit PowerSSO 12 PowerSSO 24 Thermal resistance junction case max Rihi 2 8 2 8 C W thi case with one channel Thermal resistance junction ambient See Figure 36 See Figure 40 C W max Doc ID 14472 Rev 3 3 VND5E050K E Electrical specifications 2 3 4 Electrical characteristics Values specified in this section are for 8 lt lt 28 V 40 C T 150 C unless otherwise stated Table 5 Power section Symbol Parameter Test conditions Min Typ Max Unit Voc Operating supply voltage 4 5 13 28 V Vusp Undervoltage shutdown 3 5 45 V Undervoltage shutdown Vusphyst hysteresis 0 5 V 2 Tj 25 C 50 Ron _ resistance 2 150 100 2 Vec 5V 25 65 Clamp voltage 20 41 46 52 V Off state 1 3V 25 Ig Supply current Vin Vour OV 20 50 On state 13 Vin 5V 3 6 mA lour 0A Vin Vout 0V 1 3V Off state output 25 001 3 current Vin Vout 0V Vec 13V H Tj 125 C 0 5 Output diode pape voltage 2 A 150 0 7 V 1 PowerMOS leakage included 2 Foreach channel Table 6 Switching Vcc 13V Tj 25 C Symbol Parameter Test conditions Min Typ Max
21. ay cause permanent damage to the device These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied Exposure to the conditions in table below for extended periods may affect device reliability Refer also to the STMicroelectronics SURE Program and other relevant quality document Table 3 Absolute maximum ratings Symbol Parameter Value Unit Vcc DC supply voltage 41 V Reverse DC supply voltage 0 3 V lenp reverse ground pin current 200 mA lour DC output current Internally limited lour Reverse DC output current 15 A lin DC input current 10 1 Istar status current 10 1 mA lerar pis DC status disable current 10 1 mA Maximum switching ener L 3 mH 00 Tjstart 150 C lout di is Doc ID 14472 Rev 3 7 40 Electrical specifications VND5E050K E 2 2 8 40 Table 3 Absolute maximum ratings continued Symbol Parameter Value Unit Electrostatic discharge Human Body Model R 1 5KQ C 100pF Input 4000 V VEsp Status 4000 V STAT DIS 4000 V Output 5000 V 5000 V Vesp Charge device model CDM AEC Q100 01 1 750 V Ti Junction operating temperature 40 to 150 Storage temperature 55 to 150 Thermal data Table 4 Thermal data V
22. cs curves 19 3 Application information 22 3 1 GND protection network against reverse battery 22 3 1 1 Solution 1 resistor in the ground line RGND only 22 3 1 2 Solution 2 diode DGND the ground line 23 3 2 Load dump 23 3 3 MCU I Os 23 34 Open load detection in off state 24 3 5 Maximum demagnetization energy VCC 2 13 5V 25 4 Package and PCB thermal data 26 4 1 PowerSSO 12 thermal data 26 4 2 PowerSSO 24 thermal data 29 5 Package and packing information 32 51 ECOPACK packages 32 5 2 PowerSSO 12 package information 32 5 3 PowerSSO 24 package information 34 5 4 PowerSSO 12 packing information 36 5 5 PowerSSO 24 packing information 37 6 Order codes MTM 38 7 Revision 39 2 40 Doc ID 14472 Rev 3 437 VND5E050K E List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5
23. cted in this case we have to avoid Vout to be higher than this results in the following condition Vout Veu RL Rpu RL lt Voimin 2 misdetection when load is disconnected in this case the has to be higher than VoL this results in the following condition Rpy lt Vpy Votmax L oft2 Because may significantly increase if is pulled high up to several mA the pull up resistor Rpy should be connected to a supply that is switched OFF when the module is in standby The values of Vo min max and off2 are available in the Electrical Characteristics section Figure 33 Open load detection in off state V batt Veu Vcc DRIVER INPUT OF h LOGIC A Reu IL off2 STATUS Ri GROUND 7 7 7 7 Doc ID 14472 Rev 3 ky VND5E050K E Application information 3 5 Note Maximum demagnetization energy 13 5V Figure 34 Maximum turn off current versus inductance for each channel 100 10 lt 1 0 1 1 10 100 L mH A Tjstart 150 C single pulse 100 C repetitive pulse Tjstart 125 C repetitive pulse Vine IL A Demagnetization Demagnetization Demagnetization 7 gt P 7 p 4
24. e DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet Power Dissipation in Rgnp when lt 0 during reverse battery situations is Voc Renp This resistor can be shared amongst several different HSDs Please note that the value of this resistor should be calculated with formula 1 where becomes the sum of the maximum on state currents of the different devices Please note that if the microprocessor ground is not shared by the device ground then the Renp Will produce a shift Is on max in the input thresholds and the status output values This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same Renp Doc ID 14472 Rev 3 437 VND5E050K E Application information 3 2 3 3 If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 see below Solution 2 diode the ground line A resistor 1 should be inserted in parallel to Dawp if the device drives an inductive load This small signal diode can be safely shared amongst several different HSDs Also in this case the presence of the ground network will produce a shift 600mV in the input threshold and in the status output values if the microprocessor ground is not common to the device ground This shif
25. e high CMOS compatible pin to disable the STATUS pin Doc ID 14472 Rev 3 5 40 Block diagram and pin description VND5E050K E 6 40 Figure 2 Configuration diagram top view TAB Veg Vcc PEN OUTPUT1 GND OUTPUT1 GND 4 7 B 412 Veo OUTPUT1 STAT_DIS OUTPUT1 STAT_DIS 2 11 OUTPUT 1 1 INPUT 1 3 10 OUTPUT srarusi OUTPUT1 STATUS 1 4i 9 OUTPUT 2 N C OUTPUT2 STATUS 2 5 18 OUTPUT 2 STATUS2 OUTPUT2 INPUT 2 6 7 Voc OUTPUT2 INPUT2 OUTPUT2 N C OUTPUT2 Voc OUTPUT2 TAB Vcc PowerSSO 12 PowerSSO 24 Table 2 Suggested connections for unused and not connected pins Connection pin Status N C Output Input STAT_DIS Floating X To ground Not allowed X Not allowed Through Through 1088 resistor resistor Doc ID 14472 Rev 3 3 VND5E050K E Electrical specifications 2 Note 2 1 Electrical specifications Figure 3 Current and voltage conventions Ig V EE Vcc Isp loutn gt amp STAT_DIS OUTPUTn Vsp Voutn linn Istatn PL INPUTn STATUSn Vstatn GND IGND Ven Voutn during reverse battery condition Absolute maximum ratings Stressing the device above the rating listed in the Absolute maximum ratings table m
26. eters Symbol Min Typ Max A 2 45 A2 2 15 2 35 al 0 0 1 b 0 33 0 51 0 23 0 32 D 10 10 10 50 E 7 4 7 6 e 0 8 e3 8 8 F 2 3 G 0 1 H 10 1 10 5 h 0 4 k 0 8 L 0 55 0 85 1 2 0 8 5 2 9 T 3 65 U 1 0 N 10 4 1 4 7 6 5 7 1 Doc ID 14472 Rev 3 35 40 Package and packing information VND5E050K E 5 4 PowerSSO 12 packing information Figure 45 PowerSSO 12 tube shipment no suffix Base Q ty 100 Bulk Q ty 2000 Tube length 0 5 532 1 85 n B 6 75 C 0 1 0 6 dimensions are in mm Figure 46 PowerSSO 12 tape and reel shipment suffix TR T 40mm min Access hae REEL DIMENSIONS at slot location Base Q ty 2500 Bulk Q ty 2500 A max 330 B min 1 5 x 0 2 13 20 2 2 0 12 4 G measured N min 60 slot athut T max 18 4 in core for tape start 2 5mm min width TAPE DIMENSIONS According to Electronic Industries Association EIA Standard 481 rev A Feb 1986 Tape width Ww 12 Tape Hole Spacing 0 1 4 Component Spacing P 8 TAPE Hole Diameter D 0 05 1 5 Hole Diameter D1 min 1 5 7 Hole Position F x 0 1 5 5 Compartment Depth K max 45 Hole Spacing P1 0 1 2 K dimensions are in mm
27. ling i gt i i lout 3 Vstatus Vsr pis ________ Figure 10 Intermittent Overload Intermittent Overload INPUT b E Overload gt gt n Nominal load lout f Vstatus Vsr pis Doc ID 14472 Rev 3 ky VND5E050K E Electrical specifications Figure 11 Open load with external pull up Open Load INPUT Vout lout VstaTus Vsr pis Figure 12 Open load without external pull up Open Load without external pull up INPUT Vout lout V status Vsr pis ky Doc ID 14472 Rev 3 17 40 VND5E050K E Short to Vece Figure 13 Short to INPUT Vout lout Vstatus Vsr pis INPUT Ty lout 8 gt 8 B A v nS 5 2 2 2 Q N gt z 5 5 m PN NE 9 E z ct 5 960 9 o 5865 E gt 9 5 o OG 5 2 20 D 45 5 zi gt o 2 gt 5 x S O Jooo 59 Al 8 Or E gt 5 o E 89 gt 4
28. p limitation yoo out Tj 150 C 250 Von Ron T 9 lout Doc ID 14472 Rev 3 3 VND5E050K E Electrical specifications 2 Figure 6 Switching characteristics Vout 4 AV ouT dt on gt INPUT 4 la on la otf Table 11 Truth table Conditions Input Output Sense 0 1 Normal operation 5 H H H H Over temperature F E H 5 L L L L X Undervoltage 3 H L X H BM H Overload and no power limitation short circuit to GND H Cycling L power limitation L H L2 tput volt Vi Output voltage gt VoL H H L L tput t lt l utput current lt loj H H L 1 If the Vegp is high the SENSE output is at a high impedance its potential depends on leakage currents and external circuit The STATUS pin is low with a delay equal to after INPUT falling edge The STATUS pin becomes high with a delay equal to tpo after INPUT falling edge Doc ID 14472 Rev 3 13 40 Electrical specifications VND5E050K E 14 40 Table 12 Electrical transient requirements part 1 3 ISO 7637 2 Test levels Number of Burst cycle pulse Delays and 2004 E pulses or repetition time Impedance test pulse IV test times 1 75V 100V 5000 pulses 0 55 55 2 ms 100 37V 50V 5000 pulses 0 2 55 50 us 2 Q 100V 150V 1h 90 ms 100 ms 0 1 us 50 Q
29. s document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CR
30. t will not vary if more than one HSD shares the same diode resistor network Load dump protection Dig is necessary Voltage Transient Suppressor if the load dump peak voltage exceeds the Vcc max DC rating The same applies if the device is subject to transients on the Vcc line that are greater than the ones shown in the ISO 7637 2 2004 E table MCU 05 protection If a ground protection network is used and negative transient are present on the Vec line the control pins will be pulled negative ST suggests to insert a resistor Rprot in line to prevent the uC I Os pins to latch up The value of these resistors is a compromise between the leakage current of uC pand the current required by the HSD I Os Input levels compatibility with the latch up limit of uC I Os VoCpeak llatchup lt Rprot lt Calculation example For 100V and liatchup gt 20mA 2 4 5V 5 lt Rorot lt 180kQ Recommended values Rprot 10kQ Doc ID 14472 Rev 3 23 40 Application information VND5E050K E 3 4 24 40 Open load detection in off state Off state open load detection requires an external pull up resistor connected between output pin and a positive supply voltage Vpy like the 5V line used to supply the microprocessor The external resistor has to be selected according to the following requirements 1 no false open load indication when load is conne
31. technology and housed in the tiny PowerSSO 12 and 5 50 24 packages VND5E050J E and VND5E050K E designed to drive automotive grounded loads delivering protection diagnostics and easy 3V and 5V CMOS compatible interface with any microcontroller The devices integrate advanced protective functions such as load current limitation inrush and overload active management by power limitation over temperature shut off with auto restart and over voltage active clamp A dedicated active low digital status pin is associated with every output channel in order to provide Enhanced diagnostic functions including fast detection of overload and short circuit to ground over temperature indication short circuit to diagnosis and amp off state open load detection The diagnostic feedback of the whole device can be disabled by pulling the STAT_DIS pin up thus allowing wired ORing with other similar devices Doc ID 14472 Rev 3 1 40 www st com Contents VND5E050K E Contents 1 Block diagram and pin description 5 2 Electrical specifications 7 2 1 Absolute maximum 06 7 2 2 Thermal data 8 2 3 Electrical 9 2 4 Waveftorms ars UAR Dodds eS 15 2 5 Electrical characteristi
32. x free air condition one channel on RTHj amb C W 55 4 50 45 40 35 PCB Cu heatsink area cm 2 ky Doc ID 14472 Rev 3 29 40 Package and PCB thermal data VND5E050K E PowerSSO 24 thermal impedance junction ambient single pulse one channel on Figure 41 2 ii tT Ht 0 0001 0 001 0 01 0 1 Time s 10 100 1000 Equation 2 pulse calculation formula 2 ATH where tp T Figure 42 Thermal fitting model of a double channel HSD in PowerSSO 24 b b The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections power limitation or thermal cycling during thermal shutdown are not triggered 30 40 Doc ID 14472 Rev 3 VND5E050K E Package and PCB thermal data Table 16 PowerSSO 24 thermal parameters Area island cm Footprint 2 8 R1 R7 C W 0 4 R2 R8 C W 2 R3 C W 6 R4 C W 7 7 5 C W 9 9 8 C W 28 17 10 C1 C7 W s C 0 001 C2 C8 W s C 0 0022 C3 W s C 0 025 C4 W s C 0 75 C5 W s C 1 4 9 W s C 2 2 5 17 Doc ID 14472 Rev 3 31 40 Package and packing information VND5E050K E 5 5 1 5 2 32 40 Package and packing information ECOPACK packages In order

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